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to our customers, old company name in catalogs and other documents on april 1 st , 2010, nec electronics corporation merged with renesas technology corporation, and renesas electronics corporation took over all the business of both companies. therefore, although the old company name remains in this document, it is a valid renesas electronics document. we appreciate your understanding. renesas electronics website: http://www.renesas.com april 1 st , 2010 renesas electronics corporation issued by: renesas electronics corporation ( http://www.renesas.com ) send any inquiries to http://www.renesas.com/inquiry .
notice 1. all information included in this document is current as of th e date this document is issued. such information, however, is subject to change without any prior notice. before purchasing or using any renesas electronics products listed herein, please confirm the latest product information with a renesas electronics sales office. also, please pay regular and careful attention to additional and different information to be disclosed by renesas electronics such as that disclosed through our website. 2. renesas electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property ri ghts of third parties by or arising from the use of renesas electronics products or technical information described in this document . no license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property right s of renesas electronics or others. 3. you should not alter, modify, copy, or otherwise misappropriate any renesas electronics product, whether in whole or in part . 4. descriptions of circuits, software and other related information in this document are provided only to illustrate the operat ion of semiconductor products and application examples. you are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 5. when exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. you should not use renesas electronics products or the technology de scribed in this document for any purpose re lating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. renesas electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 6. renesas electronics has used reasonable care in preparing the information included in this document, but renesas electronics does not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or om issions from the information included herein. 7. renesas electronics products are classified according to the following three quality grades: ?standard?, ?high quality?, an d ?specific?. the recommended applications for each renesas electronics product depends on the product?s quality grade, as indicated below. you must check the quality grade of each renesas electronics product before using it in a particular application. you may not use any renesas electronics product for any application categorized as ?specific? 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rje03c0112-0200 rev.2.00, dec.1.2008, page 1 of 12 r1rp0408d series 4m high speed sram (512-kword 8-bit) rej03c0112-0200 rev. 2.00 dec.1.2008 description the r1rp0408d series is a 4-mbit high speed static ram organized 512-k word 8-bit. it has realized high speed access time by employing cmos process (6-transistor memory cell) and high speed circuit designing technology. it is most appropriate for the application which requires high speed, high density memory and wide bit width configuration, such as cache and buffer memory in system. it is packaged in 400-mil 36-pin plastic soj. features ? single 5.0 v supply: 5.0 v 10% ? access time: 10 ns / 12 ns (max) ? completely static memory ? no clock or timing strobe required ? equal access and cycle times ? directly ttl compatible ? all inputs and outputs ? operating current: 140ma /130ma (max) ? ttl standby current: 40 ma (max) ? cmos standby current : 5 ma (max) : 1.0 ma (max) (l-version) ? data retention current: 0.5 ma (max) (l-version) ? data retention voltage: 2 v (min) (l-version) ? center v cc and v ss type pin out
r1rp0408d series rje03c0112-0200 rev.2.00, dec.1.2008, page 2 of 12 ordering information type no. access time package r1rp0408dge-0pr 10 ns 400-mil 36-pin plastic soj (36p0k) R1RP0408DGE-2PR 12 ns r1rp0408dge-2lr 12 ns pin arrangement 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 a0 a1 a2 a3 a4 cs# i/o1 i/o2 v cc v ss i/o3 i/o4 we# a5 a6 a7 a8 a9 nc a18 a17 a16 a15 oe# i/o8 i/o7 v ss v cc i/o6 i/o5 a14 a13 a12 a11 a10 nc (top view) 36-pin soj
r1rp0408d series rje03c0112-0200 rev.2.00, dec.1.2008, page 3 of 12 pin description pin name function a0 to a18 address input i/o1 to i/o8 data input/output cs# chip select oe# output enable we# write enable v cc power supply v ss ground nc no connection
r1rp0408d series rje03c0112-0200 rev.2.00, dec.1.2008, page 4 of 12 block diagram i/o1 . . . i/o8 we# input data control column i/o column decoder 1024-row 32-column 16-block 8-bit (4,194,304 bits) row decoder oe# cs# cs cs v cc v ss cs a14 a13 a12 a5 a6 a7 a11 a10 a3 a1 a8 a9 a18 a16 a17 a0 a2 a4 a15 (lsb) (msb) (lsb) (msb) internal voltage generator
r1rp0408d series rje03c0112-0200 rev.2.00, dec.1.2008, page 5 of 12 operation table cs# oe# we# mode v cc current i/o ref. cycle h standby i sb , i sb1 high-z ? l h h output disable i cc high-z ? l l h read i cc d out read cycle (1) to (3) l h l write i cc d in write cycle (1) l l l write i cc d in write cycle (2) note: h: v ih , l: v il , : v ih or v il absolute maximum ratings parameter symbol value unit supply voltage relative to v ss v cc ? 0.5 to +7.0 v voltage on any pin relative to v ss v t ? 0.5 * 1 to v cc + 0.5 * 2 v power dissipation p t 1.0 w operating temperature topr 0 to +70 c storage temperature tstg ? 55 to +125 c storage temperature under bias tbias ? 10 to +85 c notes: 1. v t (min) = ? 2.0 v for pulse width (under shoot) 6 ns. 2. v t (max) = v cc + 2.0 v for pulse width (over shoot) 6 ns. recommended dc operating conditions (ta = 0 to +70 c) parameter symbol min typ max unit supply voltage v cc * 3 4.5 5.0 5.5 v v ss * 4 0 0 0 v input voltage v ih 2.2 ? v cc + 0.5 * 2 v v il ? 0.5 * 1 ? 0.8 v notes: 1. v il (min) = ? 2.0 v for pulse width (under shoot) 6 ns. 2. v ih (max) = v cc + 2.0 v for pulse width (over shoot) 6 ns. 3. the supply voltage with all v cc pins must be on the same level. 4. the supply voltage with all v ss pins must be on the same level.
r1rp0408d series rje03c0112-0200 rev.2.00, dec.1.2008, page 6 of 12 dc characteristics (ta = 0 to +70 c, v cc = 5.0 v 10%, v ss = 0 v) parameter symbol min max unit test conditions input leakage current ii li i ? 2 a v in = v ss to v cc output leakage current ii lo i ? 2 a v in = v ss to v cc 10nscycle i cc ? 140 ma operation power supply current 12nscycle i cc ? 130 ma min cycle cs# = v il , l out = 0 ma other inputs = v ih /v il standby power supply current i sb ? 40 ma min cycle, cs# = v ih , other inputs = v ih /v il i sb1 ? 5 ma f = 0 mhz v cc cs# v cc ? 0.2 v, (1) 0 v v in 0.2 v or (2) v cc v in v cc ? 0.2 v ? * 1 1.0 * 1 output voltage v ol ? 0.4 v i ol = 8 ma v oh 2.4 ? v i oh = ? 4 ma note: 1. this characteristics is guaranteed only for l-version. capacitance (ta = +25 c, f = 1.0 mhz) parameter symbol min max unit test conditions input capacitance * 1 c in ? 6 pf v in = 0 v input/output capacitance * 1 c i/o ? 8 pf v i/o = 0 v note: 1. this parameter is sampled and not 100% tested.
r1rp0408d series rje03c0112-0200 rev.2.00, dec.1.2008, page 7 of 12 ac characteristics (ta = 0 to +70 c, v cc = 5.0 v 10%, unless otherwise noted.) test conditions ? input pulse levels: 3.0 v/0.0 v ? input rise and fall time: 3 ns ? input and output timing reference levels: 1.5 v ? output load: see figures (including scope and jig) d out 255 ? 480 ? 5 v 5 pf output load (b) (for t clz , t olz , t chz , t ohz , t whz , and t ow ) output load (a) 1.5 v 30 pf d out rl = 50 ? zo = 50 ? read cycle r1rp0408d 10ns version 12ns version parameter symbol min max min max unit notes read cycle time t rc 10 ? 12 ? ns address access time t aa ? 10 ? 12 ns chip select access time t acs ? 10 ? 12 ns output enable to output valid t oe ? 5 ? 6 ns output hold from address change t oh 3 ? 3 ? ns chip select to output in low-z t clz 3 ? 3 ? ns 1 output enable to output in low-z t olz 0 ? 0 ? ns 1 chip deselect to output in high-z t chz ? 5 ? 6 ns 1 output disable to output in high-z t ohz ? 5 ? 6 ns 1
r1rp0408d series rje03c0112-0200 rev.2.00, dec.1.2008, page 8 of 12 write cycle r1rp0408d 10ns version 12ns version parameter symbol min max min max unit notes write cycle time t wc 10 ? 12 ? ns address valid to end of write t aw 7 ? 8 ? ns chip select to end of write t cw 7 ? 8 ? ns 9 write pulse width t wp 7 ? 8 ? ns 8 address setup time t as 0 ? 0 ? ns 6 write recovery time t wr 0 ? 0 ? ns 7 data to write time overlap t dw 5 ? 6 ? ns data hold from write time t dh 0 ? 0 ? ns write disable to output in low-z t ow 3 ? 3 ? ns 1 output disable to output in high-z t ohz ? 5 ? 6 ns 1 write enable to output in high-z t whz ? 5 ? 6 ns 1 notes: 1. transition is measured 200 mv from steady voltage with output load (b). this parameter is sampled and not 100% tested. 2. address should be valid prior to or coincident with cs# transition low. 3. we# and/or cs# must be high during address transition time. 4. if cs# and oe# are low during this period, i/o pi ns are in the output state. then, the data input signals of opposite phase to the outp uts must not be applied to them. 5. if the cs# low transition occurs simultaneous ly with the we# low transition or after the we# transition, output remains a high impedance state. 6. t as is measured from the latest address transi tion to the later of cs# or we# going low. 7. t wr is measured from the earlier of cs# or we# going high to the first address transition. 8. a write occurs during the overlap of a low cs # and a low we#. a write begins at the latest transition among cs# going low and we# going lo w. a write ends at the earliest transition among cs# going high and we# going high. t wp is measured from the beginning of write to the end of write. 9. t cw is measured from the later of cs# going low to the end of write.
r1rp0408d series rje03c0112-0200 rev.2.00, dec.1.2008, page 9 of 12 timing waveforms read timing waveform (1) (we# = v ih ) t aa t acs t rc t oe t clz valid data address cs# d out valid address high impedance t ohz oe# t oh t chz t olz read timing waveform (2) (we# = v ih , cs# = v il , oe# = v il ) t aa t rc valid data address d out valid address t oh t oh
r1rp0408d series rje03c0112-0200 rev.2.00, dec.1.2008, page 10 of 12 read timing waveform (3) (we# = v ih , cs# = v il , oe# = v il )* 2 valid data cs# d out high impedance high impedance t clz t acs t rc t chz write timing waveform (1) (we# controlled) address we# * 3 d out d in t wc t wp t wr t cw t dw t dh valid address t aw valid data t as cs# * 3 t ohz * 4 * 4 oe# high impedance * 5
r1rp0408d series rje03c0112-0200 rev.2.00, dec.1.2008, page 11 of 12 write timing waveform (2) (cs# controlled) address we# * 3 d out d in t wc t wp t wr t cw t dw t dh valid address t aw valid data t as cs# * 3 t whz t ow * 4 * 4 high impedance * 5
r1rp0408d series rje03c0112-0200 rev.2.00, dec.1.2008, page 12 of 12 low v cc data retention characteristics (ta = 0 to +70 c) this characteristics is guaranteed only for l-version. parameter symbol min max unit test conditions v cc for data retention v dr 2.0 ? v v cc cs# v cc ? 0.2 v (1) 0 v v in 0.2 v or (2) v cc v in v cc ? 0.2 v data retention current i ccdr ? 500 a v cc = 3 v, v cc cs# v cc ? 0.2 v (1) 0 v v in 0.2 v or (2) v cc v in v cc ? 0.2 v chip deselect to data retention time t cdr 0 ? ns see retention waveform operation recovery time t r 5 ? ms low v cc data retention timing waveform cc v 2.2 v 4.5 v 0 v cs# t cdr t r dr v data retention mode v cc cs# v cc ? 0.2 v
revision history r1rp0408d series data sheet contents of modification rev. date page description 0.01 sep. 30, 2003 ? initial issue 1.00 mar.12.2004 ? deletion of preliminary 2.00 dec.01.2008 ? p1 p2 p7 p8/p9 part number 10ns version adding features access time 10ns and operating current 140ma adding order information type no r1rp0408dge-0pr adding dc characteristics operating power supply current 10ns parameter adding ac characteristics read ,write parameter 10ns parameter adding
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(http://www.renesas.com ) 5. renesas has used reasonable care in compiling the information included in this document, but renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. when using or otherwise relying on the information in this document, you should evaluate the information in light of the t otal system before deciding about the applicability of such information to the intended application. renesas makes no representations, warranties or guaranties regarding th e suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this do cument or renesas products. 7. with the exception of products specified by renesas as suitable for automobile applications, renesas products are not desi gned, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of h uman injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion co ntrol, aerospace and aeronautics, nuclear power, or undersea communication transmission. if you are considering the use of our products for such purposes, please contact a r enesas sales office beforehand. renesas shall have no liability for damages arising out of the uses set forth above. 8. notwithstanding the preceding paragraph, you should not use renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to us e renesas products in any of the foregoing applications shall indemnify and hold harmless renesas technology corp., its affiliated companies and their officers, dir ectors, and employees against any and all damages arising out of such applications. 9. you should use the products described herein within the range specified by renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas sha ll have no liability for malfunctions or damages arising out of the use of renesas products beyond such specified ranges. 10. although renesas endeavors to improve the quality and reliability of its products, ic products have specific characteristic s such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. please be sure to implement safety measures to guard against the poss ibility of physical injury, and injury or damage caused by fire in the event of the failure of a renesas product, such as safety design for hardware and software includin g but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. among others, sinc e the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. in case renesas products listed in this document are detached from the products to which the renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. you should implement safety measures so that renesas products may not be easily detached from your products. renesas shall have no liability for damages arising out of such detachment. 12. this document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from r enesas. 13. please contact a renesas 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