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  1 features ? single supply voltage, range 2.7v to 3.6v  single supply for read and write  software protected programming  fast read access time ? 250 ns  low power dissipation ? 15maactivecurrent ? 40 a cmos standby current  sector program operation ? single cycle reprogram (erase and program) ? 2048 sectors (256 bytes/sector) ? internal address and data latches for 256 bytes  two 16k bytes boot blocks with lockout  fast sector program cycle time ? 20 ms max.  internal program control and timer  data polling for end of program detection  typical endurance > 10,000 cycles  cmos and ttl compatible inputs and outputs  commercial and industrial temperature ranges description the at29bv040a is a 3-volt-only in-system flash programmable and erasable read only memory (perom). its 4 megabits of memory is organized as 524,288 words by 8 bits. manufactured with atmel?s advanced nonvolatile cmos eeprom technology, the device offers access times to 250 ns, and a low 54 mw power dissipation. when the device is deselected, the cmos standby current is less than 40 a. the device 4-megabit (512k x 8) single 2.7-volt battery- voltage ? flash memory at29bv040a rev. 0383d?flash?02/02 tsop top view type 1 pin configurations pin name function a0 - a18 addresses ce chip enable oe output enable we write enable i/o0 - i/o7 data inputs/outputs nc no connect 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a11 a9 a8 a13 a14 a17 we vcc a18 a16 a15 a12 a7 a6 a5 a4 oe a10 ce i/o7 i/o6 i/o5 i/o4 i/o3 gnd i/o2 i/o1 i/o0 a0 a1 a2 a3 cbga top view a b c d e f g h 1 234 a7 a6 a5 a4 a3 a2 a1 a0 a18 a16 a15 a12 i/o0 i/o1 i/o2 gnd a14 a17 we vcc i/o3 i/o4 i/o5 i/o6 a13 a8 a9 a11 i/o7 ce a10 oe
2 at29bv040a 0383d ? flash ? 02/02 endurance is such that any sector can typically be written to in excess of 10,000 times. the programming algorithm is compatible with other devices in atmel ? s 2.7-volt-only flash memories. to allow for simple in-system reprogrammability, the at29bv040a does not require high input voltages for programming. the device can be operated with a single 2.7v to 3.6v supply. reading data out of the device is similar to reading from an eprom. reprogramming the at29bv040a is performed on a sector basis; 256 bytes of data are loaded into the device and then simultaneously programmed. during a reprogram cycle, the address locations and 256 bytes of data are captured at microprocessor speed and internally latched, freeing the address and data bus for other operations. following the initiation of a program cycle, the device will automatically erase the sector and then program the latched data using an internal control timer. the end of a program cycle can be detected by data polling of i/o7. once the end of a pro- gram cycle has been detected, a new access for a read or program can begin. block diagram device operation read: the at29bv040a is accessed like an eprom. when ce and oe are low and we is high, the data stored at the memory location determined by the address pins is asserted on the outputs. the outputs are put in the high impedance state whenever ce or oe is high. this dual-line control gives designers flexibility in preventing bus contention. software data protection programming: the at29bv040 has 2048 indi- vidual sectors, each 256 bytes. using the software data protection feature, byte loads are used to enter the 256 bytes of a sector to be programmed. the at29bv040a can only be programmed or reprogrammed using the software data protection feature. the device is programmed on a sector basis. if a byte of data within the sector is to be changed, data for the entire 256-byte sector must be loaded into the device. the at29bv040a automatically does a sector erase prior to loading the data into the sector. an erase command is not required. software data protection protects the device from inadvertent programming. a series of three program commands to specific addresses with specific data must be presented to the device before programming may occur. the same three program commands must begin each program operation. all software program commands must obey the sector program timing specifications. power transitions will not reset the software data protec- tion feature, however the software feature will guard against inadvertent program cycles during power transitions.
3 at29bv040a 0383d ? flash ? 02/02 any attempt to write to the device without the 3-byte command sequence will start the internal write timers. no data will be written to the device; however, for the duration of t wc , a read operation will effectively be a polling operation. after the software data protection ? s 3-byte command code is given, a byte load is per- formed by applying a low pulse on the we or ce input with ce or we low (respectively) and oe high. the address is latched on the falling edge of ce or we , whichever occurs last. the data is latched by the first rising edge of ce or we . the 256 bytes of data must be loaded into each sector. any byte that is not loaded dur- ing the programming of its sector will be indeterminate. once the bytes of a sector are loaded into the device, they are simultaneously programmed during the internal pro- gramming period. after the first data byte has been loaded into the device, successive bytes are entered in the same manner. each new byte to be programmed must have its high-to-low transition on we (or ce ) within 150 s of the low-to-high transition of we (or ce ) of the preceding byte. if a high-to-low transition is not detected within 150 s of the last low-to-high transition, the load period will end and the internal programming period will start. a8 to a18 specify the sector address. the sector address must be valid during each high-to-low transition of we (or ce ). a0 to a7 specify the byte address within the sector. the bytes may be loaded in any order; sequential loading is not required. hardware data protection: hardware features protect against inadvertent programs to the at29bv040a in the following ways: (a) v cc sense ? if v cc is below 1.8v (typical), the program function is inhibited; (b) v cc power on delay ? once v cc has reached the v cc sense level, the device will automatically time out 10 ms (typical) before programming; (c) program inhibit ? holding any one of oe low, ce high or we high inhibits program cycles; and (d) noise filter ? pulses of less than 15 ns (typical) on the we or ce inputs will not initiate a program cycle. input levels: while operating with a 2.7v to 3.6v power supply, the address inputs and control inputs ( oe ,ce and we ) may be driven from 0 to 5.5v without adversely affecting the operation of the device. the i/o lines can only be driven from 0 to v cc + 0.6v. product identification: the product identification mode identifies the device and manufacturer as atmel. it may be accessed by hardware or software operation. the hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the atmel product. in addition, users may wish to use the software product identification mode to identify the part (i.e. using the device code), and have the system software use the appropriate sector size for program operations. in this manner, the user can have a common board design for 256k to 4-megabit densities and, with each density ? s sector size in a memory map, have the system software apply the appropriate sector size. for details, see operating modes (for hardware operation) or software product identifi- cation. the manufacturer and device code is the same for both modes. data polling: the at29bv040a features data polling to indicate the end of a program cycle. during a program cycle an attempted read of the last byte loaded will result in the complement of the loaded data on i/o7. once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. data polling may begin at any time during the program cycle. toggle bit: in addition to data polling the at29bv040a provides another method for determining the end of a program or erase cycle. during a program or erase opera- tion, successive attempts to read data from the device will result in i/o6 toggling between one and zero. once the program cycle has completed, i/o6 will stop toggling
4 at29bv040a 0383d ? flash ? 02/02 and valid data will be read. examining the toggle bit may begin at any time during a pro- gram cycle. optional chip erase modes: the entire device may be erased by using a 6-byte software code. please see software chip erase application note for details. boot block programming lockout: the at29bv040a has two designated memory blocks that have a programming lockout feature. this feature prevents pro- gramming of data in the designated block once the feature has been enabled. each of these blocks consists of 16k bytes; the programming lockout feature can be set inde- pendently for either block. while the lockout feature does not have to be activated, it can be activated for either or both blocks. these two 16k memory sections are referred to as boot blocks . secure code which will bring up a system can be contained in a boot block. the at29bv040a blocks are located in the first 16k bytes of memory and the last 16k bytes of memory. the boot block programming lockout feature can therefore support systems that boot from the lower addresses of memory or the higher addresses. once the programming lockout feature has been activated, the data in that block can no longer be erased or pro- grammed; data in other memory locations can still be changed through the regular programming methods. to activate the lockout feature, a series of seven program com- mands to specific addresses with specific data must be performed. please see boot block lockout feature enable algorithm. if the boot block lockout feature has been activated on either block, the chip erase func- tion will be disabled. boot block lockout detection: a software method is available to determine whether programming of either boot block section is locked out. see software product identification entry and exit sections. when the device is in the software product identifi- cation mode, a read from location 00002h will show if programming the lower address boot block is locked out while reading location ffff2h will do so for the upper boot block. if the data is fe, the corresponding block can be programmed; if the data is ff, the program lockout feature has been activated and the corresponding block cannot be programmed. the software product identification exit mode should be used to return to standard operation. absolute maximum ratings* temperature under bias ................................ -55 cto+125 c *notice: stresses beyond those listed under ? absolute maximum ratings ? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability storage temperature ..................................... -65 cto+150 c all input voltages (including nc pins) with respect to ground ...................................-0.6v to +6.25v all output voltages with respect to ground .............................-0.6v to v cc +0.6v voltage on a9 (including nc pins) with respect to ground ...................................-0.6v to +13.5v
5 at29bv040a 0383d ? flash ? 02/02 note: 1. after power is applied and v cc is at the minimum specified data sheet value, the system should wait 20 ms before an opera- tional mode is started. notes: 1. x can be v il or v ih . 2. refer to ac programming waveforms. 3. v h = 12.0v 0.5v. 4. manufacturer code is 1f. the device code is c4. 5. see details under software product identification entry/exit. dc and ac operating range at29bv040a-25 at29bv040a-35 operating temperature (case) com. 0 c-70 c0 c-70 c ind. -40 c-85 c-40 c-85 c v cc power supply (1) 2.7v to 3.6v 2.7v to 3.6v operating modes mode ce oe we ai i/o read v il v il v ih ai d out program (2) v il v ih v il ai d in standby/write inhibit v ih x (1) xxhighz program inhibit x x v ih program inhibit x v il x output disable x v ih xhighz product identification hardware v il v il v ih a1 - a18 = v il ,a9=v h (3) ,a0=v il manufacturer code (4) a1 - a18 = v il ,a9=v h (3) ,a0=v ih device code (4) software (5) a0 = v il, a1 - a18 = v il manufacturer code (4) a0 = v ih, a1 - a18 = v il device code (4) dc characteristics symbol parameter condition min max units i li input load current v in =0vtov cc 1a i lo output leakage current v i/o =0vtov cc 1a i sb1 v cc standby current cmos ce =v cc -0.3vtov cc com. 40 a ind. 50 a i sb2 v cc standby current ttl ce =2.0vtov cc 1ma i cc v cc active current f = 5 mhz; i out =0ma;v cc =3.6v 15 ma v il input low voltage 0.6 v v ih input high voltage 2.0 v v ol output low voltage i ol =1.6ma;v cc =3.0v 0.45 v v oh output high voltage i oh =-100a;v cc =3.0v 2.4 v
6 at29bv040a 0383d ? flash ? 02/02 ac read waveforms notes: 1. ce may be delayed up to t acc -t ce after the address transition without impact on t acc . 6. oe may be delayed up to t ce -t oe after the falling edge of ce without impact on t ce or by t acc -t oe after an address change without impact on t acc . 7. t df is specified from oe or ce whichever occurs first (cl = 5 pf). 8. this parameter is characterized and is not 100% tested. input test waveforms and measurement level output test load ac read characteristics symbol parameter at29bv040a-25 at29bv040a-35 units min max min max t acc address to output delay 250 350 ns t ce (1) ce to output delay 250 350 ns t oe (6) oe to output delay 0 120 0 150 ns t df (7)(8) ce or oe to output float 0 60 0 75 ns t oh output hold from oe ,ce or address, whichever occurred first 00ns t r ,t f <5ns
7 at29bv040a 0383d ? flash ? 02/02 note: 1. these parameters are characterized and not 100% tested. ac byte load waveforms (1)(2) we controlled ce controlled pin capacitance f=1mhz,t=25 c (1) symbol typ max units conditions c in 46pfv in =0v c out 812pfv out =0v ac byte load characteristics symbol parameter min max units t as ,t oes address, oe set-up time 10 ns t ah address hold time 100 ns t cs chip select set-up time 0 ns t ch chip select hold time 0 ns t wp write pulse width (we or ce ) 200 ns t ds data set-up time 100 ns t dh ,t oeh data, oe hold time 10 ns t wph write pulse width high 200 ns
8 at29bv040a 0383d ? flash ? 02/02 software protected program waveform notes: 1. oe must be high when we and ce arebothlow. 2. a8 through a18 must specify the sector address during each high to low transition of we (or ce ) after the software code has been entered. 3. all bytes that are not loaded within the sector being programmed will be indeterminate. programming algorithm (1) notes: 1. data format: i/o7 - i/o0 (hex); address format: a14 - a0 (hex). 2. data protect state will be re-activated at end of program cycle. 3. 256 bytes of data must be loaded. program cycle characteristics symbol parameter min max units t wc writecycletime 20 ms t as address set-up time 10 ns t ah address hold time 100 ns t ds data set-up time 100 ns t dh data hold time 10 ns t wp write pulse width 200 ns t blc byte load cycle time 150 s t wph write pulse width high 200 ns load data aa to address 5555 load data 55 to address 2aaa load data a0 to address 5555 load data to sector (256 bytes) (3) writes enabled enter data protect state (2)
9 at29bv040a 0383d ? flash ? 02/02 notes: 1. these parameters are characterized and not 100% tested. 2. see t oe spec in ac read characteristics. data polling waveforms notes: 1. these parameters are characterized and not 100% tested. 2. see t oe spec in ac read characteristics. toggle bit waveforms (1)(4) notes: 1. toggling either oe or ce or both oe and ce will operate toggle bit. 3. beginning and ending state of i/o6 will vary. 4. any address location may be used but the address should not vary. data polling characteristics (1)(2) symbol parameter min typ max units t dh data hold time 10 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t wr write recovery time 0 ns toggle bit characteristics (1) symbol parameter min typ max units t dh data hold time 10 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t oehp oe high pulse 150 ns t wr write recovery time 0 ns
10 at29bv040a 0383d ? flash ? 02/02 software product identification entry (1) software product identification exit (1) notes: 1. data format: i/o7 - i/o0 (hex); address format: a14 - a0 (hex). 2. a1 - a18 = v il . manufacturer code is read for a0 = v il ; device code is read for a0 = v ih . 3. the device does not remain in identification mode if powered down. 4. the device returns to standard operation mode. 5. manufacturer code is 1f. the device code is c4. load data aa to address 5555 load data 55 to address 2aaa load data 90 to address 5555 pause 20 ms enter product identification mode (2)(3) load data aa to address 5555 load data 55 to address 2aaa load data f0 to address 5555 pause 20 ms exit product identification mode (4) boot block lockout feature enable algorithm (1) notes: 1. data format: i/o7 - i/o0 (hex); address format: a14 - a0 (hex). 2. lockout feature set on lower address boot block. 3. lockout feature set on higher address boot block. load data aa to address 5555 load data 55 to address 2aaa load data 80 to address 5555 load data aa to address 5555 load data 55 to address 2aaa load data 40 to address 5555 load data 00 to address 00000h (2) pause 20 ms load data ff to address fffffh (3) pause 20 ms
11 at29bv040a 0383d ? flash ? 02/02 ordering information t acc (ns) i cc (ma) ordering code package operation range active standby 250 15 0.04 at29bv040a-25cc at29bv040a-25tc 32c1 32t commercial (0 to 70 c) 15 0.05 at29bv040a-25ci at29bv040a-25ti 32c1 32t industrial (-40 to 85 c) 350 15 0.04 at29bv040a-35cc at29bv040a-35tc 32c1 32t commercial (0 to 70 c) 15 0.05 AT29BV040A-35CI at29bv040a-35ti 32c1 32t industrial (-40 to 85 c) package type 32c1 32-ball, plastic chip-scale ball grid array package (cbga) 32t 32-lead, thin small outline package (tsop)
12 at29bv040a 0383d ? flash ? 02/02 packaging information 32c1 ? cbga 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 32c1 , 32-ball (4 x 8 array), 0.80 mm pitch, 5.0 x 10.0 x 1.20 mm plastic chip-scale ball grid array package (cbga) a 32c1 2/13/02 top view bottom view side view a b c d e f g h 2.00 ref 2.70 ref e d a1 ball id 4 321 e1 d1 a a1 e e a1 ball corner ? b common dimensions (unit of measure = mm) symbol min nom max note e 4.90 5.00 5.10 e1 2.4 typ d 9.90 10.00 10.10 d1 5.6 typ a ? ? 1.20 a1 0.25 ? ? e 0.80 bsc b 0.40 typ
13 at29bv040a 0383d ? flash ? 02/02 32t ? tsop 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 32t , 32-lead (8 x 20 mm package) plastic thin small outline package, type i (tsop) b 32t 10/18/01 pin 1 0 o ~ 8 o d1 d pin 1 identifier b e e a a1 a2 c l gage plane seating plane l1 notes: 1. this package conforms to jedec reference mo-142, variation bd. 2. dimensions d1 and e do not include mold protrusion. allowable protrusion on e is 0.15 mm per side and on d1 is 0.25 mm per side. 3. lead coplanarity is 0.10 mm maximum. common dimensions (unit of measure = mm) symbol min nom max note a ?? 1.20 a1 0.05 ? 0.15 a2 0.95 1.00 1.05 d 19.80 20.00 20.20 d1 18.30 18.40 18.50 note 2 e 7.90 8.00 8.10 note 2 l 0.50 0.60 0.70 l1 0.25 basic b 0.17 0.22 0.27 c 0.10 ? 0.21 e 0.50 basic
printed on recycled paper. ? atmel corporation 2002. atmel corporation makes no warranty for the use of its products, other than those expressly contained in the company ? s standard warranty whichisdetailedinatmel ? s terms and conditions located on the company ? s web site. the company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. no licenses to patents or other intellectual property of atmel are granted by the company in connection with the sale of atmel products, expressly or by implication. atmel ? s products are not authorized for use as critical components in life support devices or systems. atmel headquarters atmel operations corporate headquarters 2325 orchard parkway san jose, ca 95131 tel 1(408) 441-0311 fax 1(408) 487-2600 europe atmel sarl route des arsenaux 41 casa postale 80 ch-1705 fribourg switzerland tel (41) 26-426-5555 fax (41) 26-426-5500 asia atmel asia, ltd. room 1219 chinachem golden plaza 77 mody road tsimhatsui east kowloon hong kong tel (852) 2721-9778 fax (852) 2722-1369 japan atmel japan k.k. 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel (81) 3-3523-3551 fax (81) 3-3523-7581 memory atmel corporate 2325 orchard parkway san jose, ca 95131 tel 1(408) 436-4270 fax 1(408) 436-4314 microcontrollers atmel corporate 2325 orchard parkway san jose, ca 95131 tel 1(408) 436-4270 fax 1(408) 436-4314 atmel nantes la chantrerie bp 70602 44306 nantes cedex 3, france tel (33) 2-40-18-18-18 fax (33) 2-40-18-19-60 asic/assp/smart cards atmel rousset zone industrielle 13106 rousset cedex, france tel (33) 4-42-53-60-00 fax (33) 4-42-53-60-01 atmel colorado springs 1150 east cheyenne mtn. blvd. colorado springs, co 80906 tel 1(719) 576-3300 fax 1(719) 540-1759 atmel smart card ics scottish enterprise technology park maxwell building east kilbride g75 0qr, scotland tel (44) 1355-803-000 fax (44) 1355-242-743 rf/automotive atmel heilbronn theresienstrasse 2 postfach 3535 74025 heilbronn, germany tel (49) 71-31-67-0 fax (49) 71-31-67-2340 atmel colorado springs 1150 east cheyenne mtn. blvd. colorado springs, co 80906 tel 1(719) 576-3300 fax 1(719) 540-1759 biometrics/imaging/hi-rel mpu/ high speed converters/rf datacom atmel grenoble avenue de rochepleine bp 123 38521 saint-egreve cedex, france tel (33) 4-76-58-30-00 fax (33) 4-76-58-34-80 e-mail literature@atmel.com web site http://www.atmel.com 0383d ? flash ? 02/02 xm at m e l ? is the registered trademark of atmel. other terms and product names may be the trademarks of others.


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