the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. bipolar analog integrated circuit pc4574gr-9lg quad ultra low-noise, wideband, operational amplifier data sheet document no. g17931ej1v0ds00 date published november 2006 ns cp(n) printed in japan 2006 description the pc4574gr-9lg is an ultra low noise, high slew rate quad operational amplifier specifically designed for audio, instrumentation, and communication circuits. the low noise and high frequency capabilities make it ideal for preamps and active filters for instrumentat ion and professional audio. features ? ultra low noise ? high slew rate ? wide bandwidth ? internal frequency compensation ordering information part number package pc4574gr-9lg-a pc4574gr(5)-9lg-a 14-pin plastic tssop (5.72 mm (225)) 14-pin plastic tssop (5.72 mm (225)) equivalent circuit (1/4 circuit) r 1 r 7 r 6 r 9 r 8 r 10 d q 15 r 4 r 5 r 2 r 3 i i i n q 1 q 2 q 8 q 16 q 7 q 10 q 11 q 13 q 12 q 5 q 14 q 3 q 4 q 10 q 6 c 2 c 1 out v ? v + pin configuration (top view) 1 14 23 2 3 4 5 6 7 out 4 i i4 i n4 v ? i n3 i i3 out 3 out 1 i i1 i n1 v + i n2 i i2 out 2 14 13 12 11 10 9 8 ?+ ?+ ?+ ?+
data sheet g17931ej1v0ds 2 parameter symbol ratings unit voltage between v + and v ? note1 v + ? v ? ? 0.3 to +36 v differential input voltage v id 30 v input voltage note2 v i v ? ? 0.3 to v + +0.3 v output voltage note3 v o v ? ? 0.3 to v + +0.3 v power dissipation note4 p t 550 mw output short circuit duration note5 10 sec operating ambient temperature t a ? 40 to +85 c storage temperature t stg ? 55 to +125 c notes 1. reverse connection of supply voltage can cause destruction. 2. the input voltage should be allowed to input without da mage or destruction. even during the transition period of supply voltage, power on/off etc., this specification should be kept. the normal operation will establish when the both inputs are within the common mode input voltage range of electrical characteristics. 3. this specification is the voltage which should be allowed to supply to the output terminal from external without damage or destructive. even during the transiti on period of supply voltage, power on/off etc., this specification should be kept. the out put voltage of normal operation will be the output voltage swing of electrical characteristics. 4. power dissipation is specified with mounting on the glass epoxy printed wiring board as follows, and ambient temperature condition is 46c or less. board size : 100 mm square thickness : 1.6 mm cupper area : 15% of mounting area (single side) thermal deleting factor is ? 7.0 mv/c when operating ambient temperature is higher than 46c. 5. pay careful attention to the total power dissipation no t to exceed the absolute maximum ratings, note4. recommended operating conditions parameter symbol min. typ. max. unit supply voltage v 4 16 v output current i o 10 ma source resistance r s 50 k capacitive load (a v = +1) c l 100 pf
data sheet g17931ej1v0ds 3 pc4574gr-9lg electrical characteristics (t a = 25c, v = 15 v) parameter symbol conditions min. typ. max. unit input offset voltage v io r s 50 0.3 5 mv input offset current note6 i io 10 200 na input bias current note6 i b 500 1000 na large signal voltage gain a v r l 2 k , v o = 10 v 30000 300000 supply current note7 i cc i o = 0 a 8.5 12 ma common mode rejection ratio cmr 80 100 db supply voltage rejection ratio svr 80 100 db r l 10 k 12 13.4 v output voltage swing v om r l 2 k 10 + 12.8 ? 12.4 v common mode input voltage range v icm 12 14 v slew rate sr r l 2 k 4 6 v/ s gain band width product gbw f o = 100 khz 10 14 mhz unity gain frequency f unity open loop 7 mhz phase margin unity open loop 50 degree total harmonic distortion thd v o = 3 v r.m.s ., f = 20 hz to 20 khz (fig.1) 0.002 % riaa (fig.2) 1.2 v r.m.s. input equivalent noise voltage v n flat+jis a, r s = 100 (fig.3) 0.53 0.65 v r.m.s. f o = 10 hz, r s = 100 5.5 nv/ hz input equivalent noise voltage density e n f o = 1 khz, r s = 100 5.0 nv/ hz input equivalent noise current density i n f o = 1 khz 0.7 pa/ hz channel separation f = 20 hz to 20 khz 120 db notes 6. input bias currents flow out from ic. because each cu rrents are base current of pnp-transistor on input stage. 7. this current flows irrespective of the existence of use.
data sheet g17931ej1v0ds 4 pc4574gr(5)-9lg electrical characteristics (t a = 25c, v = 15v) parameter symbol conditions min. typ. max. unit input offset voltage v io r s 50 0.3 1 mv input offset current note6 i io 10 60 na input bias current note6 i b 500 650 na large signal voltage gain a v r l 2 k , v o = 10 v 50000 300000 supply current note7 i cc i o = 0 a 8.5 11 ma common mode rejection ratio cmr 85 100 db supply voltage rejection ratio svr 85 100 db r l 10 k 13 13.4 v output voltage swing v om r l 2 k 11.5 + 12.8 ? 12.4 v common mode input voltage range v icm 13 14 v slew rate sr r l 2 k 4 6 v/ s gain band width product gbw f o = 100 khz 10 14 mhz unity gain frequency f unity open loop 7 mhz phase margin unity open loop 50 degree total harmonic distortion thd v o = 3 v r.m.s ., f = 20 hz to 20 khz (fig.1) 0.002 % riaa (fig.2) 1.2 v r.m.s. input equivalent noise voltage v n flat+jis a, r s = 100 (fig.3) 0.53 0.65 v r.m.s. f o = 10 hz, r s = 100 5.5 nv/ hz input equivalent noise voltage density e n f o = 1 khz, r s = 100 5.0 nv/ hz input equivalent noise current density i n f o = 1 khz 0.7 pa/ hz channel separation f = 20 hz to 20 khz 120 db notes 6. input bias currents flow out from ic. because each cu rrents are base current of pnp-transistor on input stage. 7. this current flows irrespective of the existence of use.
data sheet g17931ej1v0ds 5 fig.2 noise measurement circuit (riaa) fig.1 total harmonic distortion measurement circuit + ? + ? v o = 3 v r.m.s. v o = (36.5 db+40 db) x v n v n = v o 76.5 db 610 47 f 2.2 k 30 k 2400 pf 8200 pf 40 db amp. 330 k 56 k + + 33 f 2 k + 1.5 f 100 k fig.3 flat noise measurement circuit (flat+jis a) + ? v o = 40 db x v n 100 10 k r s = 100 (f o = 30 khz) lpf jis a v n = v o 40 db
data sheet g17931ej1v0ds 6 t a - operating ambient temperature - ?c power dissipation p t - total power dissipation - mw 800 600 400 200 0 20 40 60 80 100 with glass epoxy pwb (see note4) 144?c/w 0 20 40 60 80 100 120 1 100 10 k 1 m 1 k 10 100 k 10 m f - frequency - hz open loop frequency response a v - open loop voltage gain - db v = 15 v ? 200 20406080 2 1.5 1 0.5 0 ? 0.5 ? 1 ? 1.5 ? 2 t a - operating ambient temperature - ?c input offset voltage v io - input offset voltage - mv = 1 5 v v each 5 samples data 80 60 40 20 0 ? 20 550 530 510 490 470 450 t a - operating ambient temperature - ?c input bias current i b - input bias current - na = 1 5 v v f - frequency - hz large signal frequency response v om - output voltage swing - v p-p 0 10 20 30 100 1 k 10 k 100 k 1 m 10 m v= 15 v r l = 10 k i o - output current - ma output current limit v o - output voltage - v 5 10 15 20 40 60 80 0 v= 15 v v,i o sink ? v,i o source t a - operating ambient temperature - ?c supply current i cc - supply current - ma 12 9 6 3 ? 20 40 20 06080 0 v= 15 v supply current i cc - supply current - ma 12 9 6 3 0 10 20 v - supply voltage - v
data sheet g17931ej1v0ds 7 common mode input voltage range v icm - common mode input voltage range - v 20 10 0 ? 10 ? 20 0 10 20 v - supply voltage - v voltage follower pulse response v o - output voltage - v 10 5 0 ? 5 ? 10 02468 t - time - s v= 15 v a v = 1 r l = 2 k input noise voltage (flat + jis a) v n - input noise voltage - v r.m.s. 100 10 1 0.1 10 100 1 k 10 k 100 k r s - source resistance - v= 15 v f - frequency - hz input equivalent noise voltage density e n - input equivalent noise voltage density - nv/ hz 2 0 4 6 8 100 1 k 10 k 100 k 10 v= 15 v r s = 100 v total harmonic distortion thd - total harmonic distortion - % 1 0.001 0.01 0.1 0.0001 10 100 1 k 10 k 100 k f - frequency - hz v= 15 v v o = 3 v r.m.s. a v = 1 r l = 2 k
data sheet g17931ej1v0ds 8 s y e s x b m l c lp d he zd a1 a2 a d1 e a3 s 0.145 0.055 (unit:mm) item dimensions d d1 e he a a1 a2 a3 5.15 0.15 5.00 0.10 4.40 0.10 6.40 0.20 1.20 max. 0.10 0.05 1.00 0.05 0.25 c e x y zd 0.65 0.10 0.10 0.625 l lp l1 0.50 0.60 0.15 1.00 0.20 p14gr-65-9lg 3 + 5 ? 3 note each lead centerline is located within 0.10mm of its true position at maximum material condition. detail of lead end 14-pin plastic tssop (5.72mm (225)) 0.24 b 7 8 1 14 l1 + 0.06 ? 0.05
data sheet g17931ej1v0ds 9 the pc4574gr-9lg should be soldered and mounted under the following recommended conditions. for soldering methods and conditions other than thos e recommended below, contact an nec electronics sales representative. for technical information, see the following website. semiconductor device mount manual (htt p://www.necel.com/pkg/en/mount/index.html) process conditions symbol infrared ray reflow peak temperature: 260c or below (package surface temperature), reflow time: 60 seconds or less (at 220c or higher), maximum number of reflow processes: 1 time. ir60-00-3 wave soldering solder temperature: 260c or below, flow time: 10 seconds or less, maximum number of flow processes: 1 time, pre-heating temperature: 120c or below (package surface temperature). ws60-00-1 partial heating method pin temperature: 350c or below, heat time: 3 seconds or less (per each side of the device). p350 caution apply only one kind of soldering condition to a device, except for "partial heating method", or the device will be damaged by heat stress.
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