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september 2003 i ? 2003 actel corporation mx automotive family fpgas features ? single-chip asic alternative for automotive applications 3,000 to 54,000 system gates up to 2.5 kbits configurable dual-port sram fast wide-decode circuitry up to 202 user-programmable i/o pins ease of integration synthesis-friendly architecture supports asic design methodologies up to 100% resource utilization and 100% pin fixing deterministic, user-controllable timing unique in-system diagnostic and verification capability with silicon explorer ii low power consumption ieee standard 1149.1 (jtag) boundary scan testing product profile ? e u device a40mx02 a40mx04 a42mx09 a42mx16 a42mx24 a42mx36 capacity system gates sram bits 3,000 ? 6,000 ? 14,000 ? 24,000 ? 36,000 ? 54,000 2,560 logic modules sequential combinatorial decode ? 295 ? ? 547 ? 348 336 ? 624 608 ? 954 912 24 1,230 1,184 24 sram modules (64x4 or 32x8) ??? ? ?10 dedicated flip-flops ? ? 348 624 954 1,230 maximum flip-flops 147 273 516 928 1,410 1,822 clocks 112 2 26 maximum user i/os 57 69 104 140 176 202 boundary scan test (bst) no no no no yes yes packages (by pin count) plcc pqfp vqfp tqfp 68 100 80 ? 84 100 80 ? 84 100, 160 100 176 ? 208 100 176 ? 160, 208 ? 176 ? 208, 240 ? ? v2.0
mx automotive family fpgas ii v2.0 ordering information plastic device resources application (temperature range) a = automotive (-40 to +125?c) package type pl = plastic leaded chip carrier pq = plastic quad flat pack tq = thin (1.4 mm) quad flat pack vq = very thin (1.0 mm) quad flat pack speed grade (blank for standard) part number a40mx02 a40mx04 a42mx09 a42mx16 a42mx24 a42mx36 package lead count a42mx16 ? pq 208 a 3,000 system gates 6,000 system gates 14,000 system gates 24,000 system gates 36,000 system gates 54,000 system gates = = = = = = device user i/os plcc 68-pin plcc 84-pin pqfp 100-pin pqfp 160-pin pqfp 208-pin pqfp 240-pin vqfp 80-pin vqfp 100-pin tqfp 176-pin a40mx02 57?57? ? ?57? ? a40mx04 ? 69 69 ? ? ? 69 ? ? a42mx09 ? 72 83 101 ? ? ? 83 104 a42mx16 ? ? ? ? 140 ? ? 83 140 a42mx24 ? ? ? 125 176 ? ? ? 150 a42mx36 ? ? ? ? 176 202 ? ? ? package definitions (contact your actel sales representative for product availability.) plcc = plastic leaded chip carrier, pqfp = plastic quad flat pack, tqfp = thin quad flat pack, vqfp = very thin quad flat pack
mx automotive family fpgas v2.0 iii product plan speed grade application std ?1 ?2 ?3 ?f c i** a* m*** b*** a40mx02 device 44-pin plastic leaded chip carrier (plcc) ????? ?? ? ? ? 68-pin plastic leaded chip carrier (plcc) ????? ??? ? ? 100-pin plastic quad flat pack (pqfp) ????? ??? ? ? 80-pin very thin plastic quad flat pack (vqfp) ????? ??? ? ? a40mx04 device 44-pin plastic leaded chip carrier (plcc) ????? ?? ? ? ? 68-pin plastic leaded chip carrier (plcc) ????? ?? ? ? ? 84-pin plastic leaded chip carrier (plcc) ????? ??? ? ? 100-pin plastic quad flat pack (pqfp) ????? ??? ? ? 80-pin very thin plastic quad flat pack (vqfp) ????? ??? ? ? a42mx09 device 84-pin plastic leaded chip carrier (plcc) ????? ??? ? ? 100-pin plastic quad flat pack (pqfp) ????? ??? ? ? 160-pin plastic quad flat pack (pqfp) ????? ??? ? ? 176-pin thin plastic quad flat pack (tqfp) ????? ??? ? ? 100-pin very thin plastic quad flat pack (vqfp) ????? ??? ? ? a42mx16 device 84-pin plastic leaded chip carrier (plcc) ????? ?? ? ? ? 100-pin plastic quad flat pack (pqfp) ????? ?? ? ? ? 160-pin plastic quad flat pack (pqfp) ????? ?? ? ? ? 208-pin plastic quad flat pack (pqfp) ????? ??? ? ? 176-pin thin plastic quad flat pack (tqfp) ????? ??? ? ? 100-pin very thin plastic quad flat pack (vqfp) ????? ??? ? ? a42mx24 device 84-pin plastic leaded chip carrier (plcc) ????? ?? ? ? ? 160-pin plastic quad flat pack (pqfp) ????? ??? ? ? 208-pin plastic quad flat pack (pqfp) ????? ??? ? ? 176-pin thin plastic quad flat pack (tqfp) ????? ??? ? ? contact your actel sales representative for product availability. for more information on commercial-, industrial- and military-grade mx devices, refer to the 40mx and 42mx fpga families datasheet. applications: availability: speed grade: c = commercial ? = available ?1 = approx. 15% faster than standard i = industrial p = planned ?2 = approx. 25% faster than standard a = automotive ? = not planned ?3 = approx. 35% faster than standard m = military ?f = approx. 45% faster than standard b = mil-std-883 class b * a is available in std only. **i is available in std, ?1, ?2 and ?3 only.. ***m and b are offered only in -std and -1 only.
mx automotive family fpgas iv v2.0 a42mx36 device 208-pin plastic quad flat pack (pqfp) ????? ??? ? ? 240-pin plastic quad flat pack (pqfp) ????? ??? ? ? 272-pin plastic ball grid array (pbga) ????? ?? ? ? ? 208-pin ceramic quad flat pack (cqfp) ??? ?? ? ?? ?? 256-pin ceramic quad flat pack (cqfp) ??? ?? ? ?? ?? speed grade application std ?1 ?2 ?3 ?f c i** a* m*** b*** contact your actel sales representative for product availability. for more information on commercial-, industrial- and military-grade mx devices, refer to the 40mx and 42mx fpga families datasheet. applications: availability: speed grade: c = commercial ? = available ?1 = approx. 15% faster than standard i = industrial p = planned ?2 = approx. 25% faster than standard a = automotive ? = not planned ?3 = approx. 35% faster than standard m = military ?f = approx. 45% faster than standard b = mil-std-883 class b * a is available in std only. **i is available in std, ?1, ?2 and ?3 only.. ***m and b are offered only in -std and -1 only.
v2.0 v table of contents mx automotive family fpgas general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 power requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 mx architectural overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 development tool support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 5.0v operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 timing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 parameter measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16 sequential timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17 decode module timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19 dual-port sram timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20 predictable performance: tight delay distributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22 temperature and voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23 timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-42 package pin assignments 68-pin plcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 84-pin plcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 100-pin pqfp package (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 160-pin pqfp package (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 208-pin pqfp package (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 240-pin pqfp package (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 80-pin vqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 100-pin vqfp package (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 176-pin tqfp package (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23

mx automotive family fpgas v2.0 1-1 mx automotive family fpgas general description actel?s automotive-grade mx families provide a high- performance, single-chip solution for shortening the system design and development cycle, offering a cost- effective alternative to asics for in-cabin telematics and automobile interconnect applications. the 40mx and 42mx devices are excellent choices for integrating logic that is currently implemented in multiple pals, cplds, and fpgas. the mx device architecture is based on actel?s patented antifuse technology implemented in a 0.45 triple-metal cmos process. with capacities ranging from 3,000 to 54,000 system gates, the synthesis-friendly automotive- grade mx devices are live on power-up, and require only one-fifth the standby power of comparable fpgas. actel?s mx fpgas provide up to 202 user i/os and are available in a wide variety of packages and speed grades. the automotive-grade a42mx24 and a42mx36 devices also include system-level features such as ieee standard 1149.1 (jtag) boundary scan testing, and fast wide- decode modules. the a42mx36 device offers dual-port sram for implementing fast fifos, lifos, and temporary data storage. the large number of storage elements can efficiently address applications requiring wide datapath manipulation and can perform transformation functions such as those required for telecommunications, networking, and dsp. power requirements automotive-grade 40mx and 42mx devices operate in 5.0v systems. 40mx 42mx mx architectural overview the 40mx and 42mx devices are composed of fine- grained building blocks that enable fast, efficient logic designs. all devices within these families are composed of logic modules, i/o modules, routing resources, and clock networks, which are the building blocks for designing fast logic designs. in addition, the a42mx24 and a42mx36 devices contain wide decode modules, and the latter also contains embedded dual-port sram. the dual-port sram modules are optimized for high- speed datapath functions such as fifos, lifos, and scratchpad memory. ?product profile? at the beginning of this document lists the specific logic resources contained within each device. logic modules the 40mx logic module is an eight-input, one-output logic circuit designed to implement a wide range of logic functions with efficient use of interconnect routing resources ( figure 1-1 ). the logic module can implement the four basic logic functions (nand, and, or, and nor) in gates of two, three, or four inputs. each function may have many versions with different combinations of active low inputs. the logic module can also implement a variety of d-latches, exclusivity functions, and-ors, and or-ands. no dedicated hard-wired latches or flip-flops are required in the array; latches and flip-flops can be constructed from logic modules wherever needed in the application. the 42mx devices contain three types of logic modules: combinatorial (c-modules), sequential (s-modules), and decode (d-modules). v cc input output 5.0v 5.0v 5.0v v cc av cci input output 5.0v 5.0v 5.0v 5.0v figure 1-1 ? 40mx logic module
mx automotive family fpgas 1-2 v2.0 the c-module, shown in figure 1-2 , implements the following function: y=!s1*!s0*d00+!s1*s0*d01+s1*!s0*d10+s1*s0*d11 where s0=a0*b0 s1=a1+b1 the s-module, shown in figure 1-3 , is designed to implement high-speed sequential functions within a single logic module. the s-module implements the same combinatorial logic function as the c-module while adding a sequential element. the sequential element can be configured as either a d flip-flop or a transparent latch. to increase flexibility, the s-module register can be bypassed so that it implements purely combinatorial logic. figure 1-2 c-module implementation in 42mx devices d00 d01 d10 d11 s0 s1 y a0 b0 a1 b1 figure 1-3 s-module implementation in 42mx devices d11 d01 d00 d10 y s1 s0 out clr dq up to 7-input function plus d-type flip-flop with clear d11 d01 d00 d10 y s1 s0 out gate dq up to 7-input function plus latch d1 d0 y s out clr gate dq up to 4-input function plus latch with clear d11 d01 d00 d10 y s1 s0 out up to 7-input function plus d-type flip-flop with clear
mx automotive family fpgas v2.0 1-3 d-modules, available in a42mx24 and a42mx36 devices, contain wide-decode circuitry which provide a fast, wide- input and function similar to that found in cpld architectures ( figure 1-4 ). these modules are arranged around the periphery of the device. the d-module allows 42mx devices to perform wide-decode functions at speeds comparable to cplds and pals. the output of the d-module has a programmable inverter for active high or low assertion. the d-module output is hard-wired to an output pin, but it can also be fed back into the array to be incorporated into other logic. dual-port sram modules the a42mx36 device contains dual-port sram modules that have been optimized for synchronous or asynchronous applications. the sram modules are arranged in 256-bit blocks that can be configured as 32x8 or 64x4. sram modules can be cascaded together to form memory spaces of user-definable width and depth. a block diagram of the 42mx dual-port sram block is shown in figure 1-5 . the 42mx sram modules are true dual-port structures containing independent read and write ports. each sram module contains six bits of read and write addressing (rdad[5:0] and wrad[5:0], respectively) for 64x4-bit blocks. when configured in byte mode, the highest order address bits (rdad5 and wrad5) are not used. the read and write ports of the sram block contain independent clocks (rclk and wclk) with programmable polarities offering active high or low implementation. the sram block contains eight data inputs (wd[7:0]), and eight outputs (rd[7:0]) which are connected to segmented vertical routing tracks. the 42mx dual-port sram blocks provide an optimal solution for high-speed buffered applications requiring fast fifo and lifo queues. actel?s actgen macro builder provides the capability to quickly design memory functions, such as fifos, lifos, and ram arrays. in addition, unused sram blocks can be used to implement registers for other logic within the design. figure 1-4 d-module implementation in 42mx devices 7 inputs hard-wire to i/o feedback to array programmable inverter figure 1-5 42mx dual-port sram block sram module 32 x 8 or 64 x 4 (256 bits) read port logic write port logic rd[7:0] routing tracks [5:0] rdad[5:0] ren rclk latches wd[7:0] wrad[5:0] write logic mode blken wen wclk [5:0] latches read logic [7:0] latches
mx automotive family fpgas 1-4 v2.0 multiplex i/o modules automotive-grade 42mx devices offer multiplex i/os, which support both 3.3v and 5.0v operations. the multiplex i/o modules provide a flexible interface between the device pins and the logic array. figure 1-6 is a block diagram of the 42mx i/o module. a variety of user functions, determined by a library macro selection, can be implemented in the module. (refer to the macro library guide for more information.) all 42mx i/o modules contain tri-state buffers, with input and output latches that can be configured for input, output, or bi- directional operation. each output buffer has a dedicated output enable control. the i/o module can be used to latch input or output data, or both, providing a fast set-up time. in addition, the actel designer series software tools can build a d-type flip-flop using a c- module to register input and output signals. actel?s designer series development tools provide a design library of i/o macro functions that can implement all i/o configurations supported by the automotive- grade mx fpgas. routing structure the mx architecture uses vertical and horizontal routing tracks to interconnect the various logic and i/o modules. these routing tracks are metal interconnects that may be either of continuous length or broken into pieces called segments. varying segment lengths allows the interconnect of over 90% of design tracks to occur with only two antifuse connections. segments can be joined together at the ends using antifuses to increase their lengths up to the full length of the track. all interconnects can be accomplished with a maximum of four antifuses. horizontal routing horizontal channels are located between the rows of modules and are composed of several routing tracks. the horizontal routing tracks within the channel are divided into one or more segments. the minimum horizontal segment length is the width of a module pair, and the maximum horizontal segment length is the full length of the channel. any segment that spans more than one- third at the row length is considered a long horizontal segment. a typical channel is shown in figure 1-7 . non- dedicated horizontal routing tracks are used to route signal nets; dedicated routing tracks are used for global clock networks and for power and ground tie-off tracks. vertical routing another set of routing tracks run vertically through the module. there are three types of vertical tracks: input, output, and long, which are also divided into one or more segments. each segment in an input track is dedicated to the input of a particular module; each segment in an output track is dedicated to the output of a particular module. long segments are uncommitted and can be assigned during routing. each output segment spans four channels (two above and two below), except near the top and bottom of the array, where edge effects occur. long vertical tracks contain either one or two segments. an example of vertical routing tracks and segments is shown in figure 1-7 . note: *can be configured as a latch or d flip-flop (using c- module) figure 1-6 42mx i/o module figure 1-7 routing structure g/clk* qd oe pa d from array to array g/clk* qd vertical routing tracks antifuses logic segmented horizontal routing tracks modules
mx automotive family fpgas v2.0 1-5 antifuse structures an antifuse is a ?normally open? structure as opposed to the normally connected fuse structure used in proms or pals. the use of antifuses to implement a programmable logic device results in highly testable structures as well as efficient programming algorithms. the structure is highly-testable because there are no pre-existing connections; therefore, temporary connections can be made using pass transistors. these temporary connections can isolate individual antifuses to be programmed and individual circuit structures to be tested, which can be done before and after programming. for example, all metal tracks can be tested for continuity and shorts between adjacent tracks, and the functionality of all logic modules can be verified. clock networks the 40mx devices have one global clock distribution network (clk). two low-skew, high-fanout clock distribution networks are provided in each 42mx device. these networks are referred to as clk0 and clk1 . each network has a clock module (clkmod) that selects the source of the clock signal and may be driven as follows: externally from the clka pad externally from the clkb pad internally from the clkinta input internally from the clkintb input the clock modules are located in the top row of i/o modules. clock drivers and a dedicated horizontal clock track are located in each horizontal routing channel. the user controls the clock module by selecting one of two clock macros from the macro library. the macro clkbuf is used to connect one of the two external clock pins to a clock network, and the macro clkint is used to connect an internally-generated clock signal to a clock network. since both clock networks are identical, it does not matter whether clk0 or clk1 is being used. the clock input pads can also be used as normal i/os, bypassing the clock networks ( figure 1-8 ). the a42mx36 device has four additional register control resources, called quadrant clock networks ( figure 1-9 on page 1-6 ). each quadrant clock provides a local, high- fanout resource to the contiguous logic modules within its quadrant of the device. quadrant clock signals can originate from specific i/o pins or from the internal array and can be used as a secondary register clock, register clear, or output enable. test circuitry all mx automotive-grade devices contain probing circuitry which test and debug a design once it is programmed into a device. the test circuitry allows the designer to probe any internal node during device operation to aid in debugging a design. ieee standard 1149.1 boundary scan testing (bst) a42mx24 and a42mx36 devices contain ieee standard 1149.1 boundary scan test circuitry. ieee standard 1149.1 defines a four-pin test access port (tap) interface for testing integrated circuits in a system. the a42mx24 and a42mx36 devices provide the following bst pins: test data in (tdi), test data out (tdo), test clock (tck), and test mode select (tms). devices are configured in a test ?chain? where bst data can be transmitted serially between devices via tdo-to-tdi interconnections. the tms and tck signals are shared among all devices in the test chain so that all components operate in the same state. the 42mx family implements a subset of the ieee standard 1149.1 bst instruction in addition to a private instruction. refer to the ieee standard 1149.1 specification for detailed information regarding bst. boundary scan circuitry the a42mx24 and a42mx36 boundary-scan circuitry consists of a test access port (tap) controller, test instruction register, a bypass register, and a boundary scan register. figure 1-10 on page 1-6 shows a block diagram of the 42mx boundary scan circuitry. figure 1-8 42mx clock networks clkb clka from pads clock drivers clkmod clkinb clkina s0 s1 internal signal clko(17) clko(16) clko(15) clko(2) clko(1) clock tracks
mx automotive family fpgas 1-6 v2.0 *qclk1in, qclk2in, qclk3in, and qclk4in are internally-generated signals. figure 1-9 a42mx36 quadrant clock network figure 1-10 ieee 1149.1 boundary scan circuitry in a42mx24 and a42mx36 quad clock module qclka qclkb *qclk1in s0 s1 qclk1 quad clock module *qclk2in s0 s1 qclk2 quad clock module qclkc qclkd *qclk3in s0 s1 qclk3 quad clock module *qclk4in qclk4 s0 s1 boundary scan register instruction decode control logic tap controller instruction register bypass register tms tck tdi output mux tdo jtag jtag
mx automotive family fpgas v2.0 1-7 when a device is operating in bst mode, four i/o pins are used for the tdi, tdo, tms, and tck signals. an active reset (trst) pin is not supported; however, the a42mx24 and a42mx36 devices contain power-on circuitry that resets the boundary scan circuitry upon power-up. table 1-1 summarizes the functions of the ieee 1149.1 bst signals. jtag a42mx24 and a42mx36 automotive-grade mx devices offer superior diagnostic and testing capabilities by providing jtag and probing capabilities. these functions are controlled through the special jtag pins in conjunction with the program fuse. jtag fuse programmed: tck must be terminated?logical high or low doesn?t matter (to avoid floating input) tdi, tms may float or at logical high (internal pull-up is present) tdo may float or connect to tdi of another device (it?s an output) jtag fuse not programmed: tck, tdi, tdo, tms are user i/o. if not used, they will be configured as tri-stated output. bst instructions boundary scan testing within the a42mx24 and a42mx36 devices is controlled by a test access port (tap) state machine. the tap controller drives the three-bit instruction register, a bypass register, and the boundary scan data registers within the device. the tap controller uses the tms signal to control the testing of the device. the bst mode is determined by the bitstream entered on the tms pin. table 1-2 describes the test instructions supported by the a42mx24 and a42mx36 devices. reset the tms pin is equipped with an internal pull-up resistor. this allows the tap controller to remain in or return to the test-logic-reset state when there is no input or when a logical 1 is on the tms pin. to reset the controller, tms must be high for at least five tck cycles. development tool support the automotive-grade mx family of fpgas is fully supported by both actel's libero? integrated design environment and designer fpga development software. actel libero ide is a design management environment that streamlines the design flow. libero ide provides an integrated design manager that seamlessly integrates design tools while guiding the user through the design flow, managing all design and log files, and passing necessary design data among tools. additionally, libero ide allows users to integrate both schematic and hdl synthesis into a single flow and verify the entire design in a single environment ( figure 1-11 on page 1-8 ). libero ide includes synplify? for actel from synplicity?, viewdraw for actel from mentor graphics, model sim ? hdl simulator from model technology?, waveformer lite? from synapticad?, and designer software from actel. actel's designer software provides a comprehensive suite of backend development tools for fpga development. the designer software includes timing-driven place-and- route, and a world-class integrated static timing analyzer and constraints editor. with the designer software, a user can lock his/her design pins before layout while minimally impacting the results of place-and-route. additionally, the back-annotation flow is compatible table 1-1 ieee 1149.1 bst signals signal name function tdi test data in serial data input for bst instructions and data. data is shifted in on the rising edge of tck. tdo test data out serial data output for bst instructions and test data. tms test mode select serial data input for bst mode. data is shifted in on the rising edge of tck. tck test clock clock signal to shift the bst data into the device. table 1-2 bst instructions test mode code description extest 000 allows the external circuitry and board- level interconnections to be tested by forcing a test pattern at the output pins and capturing test results at the input pins. sample/ preload 001 allows a snapshot of the signals at the device pins to be captured and examined during device operation. high z 101 refer to the ieee standard 1149.1 specification. clamp 110 refer to the ieee standard 1149.1 specification. bypass 111 enables the bypass register between the tdi and tdo pins. the test data passes through the selected device to adjacent devices in the test chain.
mx automotive family fpgas 1-8 v2.0 with all the major simulators and the simulation results can be cross-probed with silicon explorer ii, actel?s integrated verification and logic analysis tool. another tool included in the designer software is the actgen macro builder, which easily creates popular and commonly used logic functions for implementation into your schematic or hdl design. actel's designer software is compatible with the most popular fpga design entry and verification tools from companies such as mentor graphics, synplicity, synopsys, and cadence design systems. the designer software is available for both the windows and unix operating systems. note: *only available in axcelerator and proasic plus devices. figure 1-11 design flow timing simulation functional simulation model sim r simulator viewdraw r schematic entry synthesis libraries fuse or bitstream layout compile back-annotate smartpower* timer netlistviewer i/o attribute editor * pineditor multiview navigator i/o assignments select i/o standards chipplanner or chipeditor floorplanning design synthesis and optimization static timing analysis and constraints editor power analysis back-annotation timing for simulation design schematic viewer cross-probing waveformer lite tm testbench stimulus generation user testbench design implementation design implementation design creation/verification design creation/verification libero tm ide design flow hdl editor actgen macro builder optimization and drc timing driven place-and-route synplify r synthesis silicon sculptor (antifuse and flash families) silicon explorer ii (antifuse families) flashpro (flash families) flashpro lite (proasic plus family) bp microsystems programmers actel device programming programming system verification system verification
mx automotive family fpgas v2.0 1-9 5.0v operating conditions absolute maximum ratings * free air temperature range recommended operating conditions electrical specifications symbol parameter limits units v cc/ v cca/ v cci dc supply voltage ?0.5 to +6.5 v v i input voltage ?0.5 to v cc +0.5 v v o output voltage ?0.5 to v cc +0.5 v t stg storage temperature ?65 to +150 c note: *stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. exposure to absolute maximum rated conditions for extended periods may affect device reliability. devices should not be operated outside the recommended operating conditions. parameter automotive units temperature range * -40 to +125 c v cci 4.75 to 5.25 v v cca 4.75 to 5.25 v v cc 4.75 to 5.25 v note: *ambient temperature (t a ) symbol parameter automotive units min. max. v oh (i oh = ?4 ma) 3.1 v v ol (i ol = 4 ma) 0.4 v v il 0.6 v v ih 2.1 v i il ?20 20 a i ih ?20 20 a input transition time t r , t f 1 250 ns c io i/o capacitance 1, 2 10 pf standby current, i cc 3 35 ma i cc(d) dynamic v cci supply current see ?power dissipation? on page 1-10 . 1. not tested, for information only. 2. includes worst-case 84-pin plcc package capacitance. v out = 0 v, f = 1 mhz. 3. all outputs unloaded. all inputs = v cc or gnd.
mx automotive family fpgas 1-10 v2.0 package thermal characteristics the device junction-to-case thermal characteristic is jc , and the junction-to-ambient air characteristic is ja . the thermal characteristics for ja are shown with two different air flow rates. maximum junction temperature is 150c. a sample calculation of the absolute maximum power dissipation allowed for a pqfp 160-pin package at commercial temperature is as follows: power dissipation general power equation p = [i cc standby + i cc active] * v cci + i ol * v ol * n + i oh * (v cci ? v oh ) * m where: i cc standby is the current flowing when no inputs or outputs are changing. i cc active is the current flowing due to cmos switching. i ol , i oh are ttl sink/source currents. v ol , v oh are ttl level output voltages. n equals the number of outputs driving ttl loads to v ol . m equals the number of outputs driving ttl loads to v oh . accurate values for n and m are difficult to determine because they depend on the family type, on design details, and on the system i/o. the power can be divided into two components: static and active. static power component actel fpgas have small static power components that result in power dissipation lower than pals or cplds. by integrating multiple pals/cplds into one fpga, an even greater reduction in board-level power dissipation can be achieved. the power due to standby current is typically a small component of the overall power. the static power dissipation by ttl loads depends on the number of outputs driving high or low, and on the dc load current. again, this number is typically small. for instance, a 32-bit bus sinking 4 ma at 0.33v will generate 42 mw with all outputs driving low, and 140 mw with all outputs driving high. the actual dissipation will average somewhere in between, as i/os switch states with time. plastic packages pin count jc ja still air 300 ft/min plastic quad flat pack 100 12 34c/w 31c/w plastic quad flat pack 160 10 32c/w 24c/w plastic quad flat pack 208 8 30c/w 23c/w plastic quad flat pack 240 3.5 19c/w 16c/w plastic leaded chip carrier 68 13 36c/w 25c/w plastic leaded chip carrier 84 12 32c/w 22c/w thin plastic quad flat pack 176 11 28c/w 21c/w very thin plastic quad flat pack 80 12 39c/w 33c/w very thin plastic quad flat pack 100 10 38c/w 32c/w max. junction temp. (c) ? max. commercial temp. ja (c/w) ------------------------------------------------------------------------------------------------------------------------------- --- - 150c ? 125c 32c/w -------------------------------------- -0.78 w ==
mx automotive family fpgas v2.0 1-11 active power component power dissipation in cmos devices is usually dominated by the active (dynamic) power dissipation. this component is frequency-dependent and a function of the logic and the external i/o. active power dissipation results from charging internal chip capacitances of the interconnect, unprogrammed antifuses, module inputs, and module outputs, plus external capacitance due to pc board traces and load device inputs. an additional component of the active power dissipation is the totem pole current in the cmos transistor pairs. the net effect can be associated with an equivalent capacitance that can be combined with frequency and voltage to represent active power dissipation. equivalent capacitance the power dissipated by a cmos circuit can be expressed by the equation: power (w) = c eq * v cca 2 * f eq 1-1 where: equivalent capacitance is calculated by measuring i cc active at a specified frequency and voltage for each circuit component of interest. measurements have been made over a range of frequencies at a fixed value of v cc . equivalent capacitance is frequency-independent, so the results can be used over a wide range of operating conditions. equivalent capacitance values are shown below. c eq values for actel mx fpgas to calculate the active power dissipated from the complete design, the switching frequency of each part of the logic must be known. the equation below shows a piece-wise linear summation over all components. power = v cca 2 * [(m x c eqm * f m ) modules + (n * c eqi * f n ) inputs + (p * (c eqo + c l ) * f p ) outputs + 0.5 * (q 1 * c eqcr * f q1 ) routed_clk1 + (r 1 * f q1 ) routed_clk1 + 0.5 * (q 2 * c eqcr * f q2 ) routed_clk2 + (r 2 * f q2 ) routed_clk2 eq 1-2 where: c eq = equivalent capacitance expressed in picofarads (pf) v cca = power supply in volts (v) f = switching frequency in megahertz (mhz) modules (c eqm ) 3.5 input buffers (c eqi )6.9 output buffers (c eqo ) 18.2 routed array clock buffer loads (c eqcr )1.4 m = number of logic modules switching at frequency f m n = number of input buffers switching at frequency f n p = number of output buffers switching at frequency f p q 1 = number of clock loads on the first routed array clock q 2 = number of clock loads on the second routed array clock r 1 = fixed capacitance due to first routed array clock r 2 = fixed capacitance due to second routed array clock c eqm = equivalent capacitance of logic modules in pf c eqi = equivalent capacitance of input buffers in pf c eqo = equivalent capacitance of output buffers in pf c eqcr = equivalent capacitance of routed array clock in pf c l = output load capacitance in p f m = average logic module switching rate in mhz f n = average input buffer switching rate in mhz f p = average output buffer switching rate in mhz f q1 = average first routed array clock rate in mhz f q2 = average second routed array clock rate in mhz
mx automotive family fpgas 1-12 v2.0 fixed capacitance values for mx fpgas (pf) determining average switching frequency to determine the switching frequency for a design, the data input values to the circuit must be clearly understood. the following guidelines represent worst- case scenarios; these can be used to generally predict the upper limits of power dissipation. device type r1 routed_clk1 r2 routed_clk2 a40mx02 41.4 n/a a40mx04 68.6 n/a a42mx09 118 118 a42mx16 165 165 a42mx24 185 185 a42mx36 220 220 logic modules (m) = 80% of combinatorial modules inputs switching (n) = # of inputs/4 outputs switching (p) = # of outputs/4 first routed array clock loads (q 1 ) = 40% of sequential modules second routed array clock loads (q 2 ) = 40% of sequential modules load capacitance (c l ) = 35 pf average logic module switching rate (f m ) =f/10 average input switching rate (f n )=f/5 average output switching rate (f p )=f/10 average first routed array clock rate (f q1 ) =f average second routed array clock rate (f q2 ) =f/2
mx automotive family fpgas v2.0 1-13 timing information * values are shown for 40mx at worst-case 5.0v automotive conditions. figure 1-12 40mx timing model* *values are shown for a42mx09 at worst-case 5.0v automotive conditions ? input module predicted routing delay figure 1-13 42mx timing model* output delay input delay i/o module inyl = 1.22 ns ird2 = 4.89 ns logic module pd = 2.32 ns i/o module t rd1 = 2.45 ns dlh = 6.24 ns array clock max = 164 mhz t rd4 = 5.38 ns t rd8 = 9.29 ns predicted routing delays ckh = 8.57 ns fo = 128 = 3.92 ns = 6.85 ns = 10.77 ns co = 2.32 ns enhz = 14.93 ns t rd2 = 3.43 ns internal delays t t t f t ird1 ird4 ird8 t t t t t t output delays i/o module t dlh = 4.23 ns i/o module t outh = 0.00 ns t outsu = 0.47 ns t glh = 4.47 ns t dlh = 4.23 ns t enhz = 8.58 ns t rd1 = 0.80 ns t inh = 0.00 ns t insu = 0.47 ns t ingl = 2.23 ns array clocks t ckh = 4.23 ns dq t co = 2.23 ns g internal delays input delays i/o module dq t inyl = 1.41 ns t ird1 = combinatorial logic module t pd = 2.12 ns sequential logic module t rd1 = 1.18 ns f max = 229 mhz dq t sud = 0.59 ns t hd = 0.00 ns t rd4 = 2.35 ns t rd8 = 3.99 ns predicted routing delays g fo = 32 t rd2 = 1.65 ns t lco = 9.05 ns (light loads, pad-to-pad) 3.53 ns combin- atorial logic included in t sud ?
mx automotive family fpgas 1-14 v2.0 * preliminary values are shown for a42mx36 at worst-case 5.0v automotive conditions ** load-dependent figure 1-14 a42mx36 timing model (logic functions using quadrant clocks)* output delays internal delays input delays i/o module = 1.76 ns = 3.41 ns combinatorial module i/o module predicted routing delays t inpy t dlh = 4.47 ns = 0.00 ns = 0.82 ns dq = 2.47 ns t ird1 t pd = 2.35 ns t rd1 = 1.65 ns g decode module t pdd = 2.82 ns t rdd = 0.59 ns t rd2 = 2.23 ns t rd4 = 3.41 ns t inh t insu t ingo quadrant clocks f max = 154 mhz t lh = 0.00 ns t lsu = 0.82 ns t ghl = 5.17 ns t enhz t ckh = 4.70 ns** i/o module dq t dlh = 4.47 ns = 8.58 ns g sequential logic module combin- atorial logic included in t dq t rd1 = 1.65 ns t co = 2.23 ns t sud = 0.59 ns t hd = 0.00 ns sud
mx automotive family fpgas v2.0 1-15 *values are shown for a42mx36 at worst-case 5.0v automotive conditions. figure 1-15 a42mx36 timing model (sram functions)* input delays wd [7:0] wrad [5:0] blken wen wclk rd [7:0] rdad [5:0] ren rclk predicted routing delays t ghl = 5.17 ns t lsu = 0.82 ns i/o module t lh = 0.00 ns t dlh = 4.47 ns t adsu = 2.82 ns t adh = 0.00 ns t wensu = 4.70 ns t bens = 4.82 ns t adsu = 2.82 ns t adh = 0.00 ns t rensu = 1.06 ns t rd1 = 1.65 ns t rco = 5.88 ns t inh = 0.00 ns t insu = 0.82 ns dq t ingo = 2.47 ns array clocks f max = 154 mhz g i/o module t inpy = 1.76 ns t ird1 = 3.41 ns dq g
mx automotive family fpgas 1-16 v2.0 parameter measurement figure 1-16 output buffer delays e pad gnd t enzh 50% v oh 1.5v 50% 90% to ac test loads (shown below) t enhz pad e 50% pad v ol 1.5v t enzl 50% 10% t enlz v cci d e tribuff in 50% pad v ol v oh 1.5v t dlh 50% 1.5v t dhl figure 1-17 ac test loads load 2 (used to measure rising/falling edges) v cci gnd 35 pf to the output under test r to v cci for t plz /t pzl r to gnd for t phz /t pzh r = 1 k ? load 1 (used to measure propagation delay) 35 pf to the output under test
mx automotive family fpgas v2.0 1-17 sequential timing characteristics figure 1-18 input buffer delays pad y inbuf pad 3v 0v 1.5v y gnd v cci 50% t inyh 1.5v 50% t inyl figure 1-19 module delays s a b y s, a or b y 50% t plh y 50% 50% 50% 50% 50% t phl t phl t plh d represents all data functions involving a. b. and s for multiplexed flip-flops. figure 1-20 flip-flops and latches (positive edge-triggered) d e clk clr pre y t wclka t hd sud t t suena t wclki t hena t co d 1 g, clk e q pre, clr t wasyn t rs t a
mx automotive family fpgas 1-18 v2.0 figure 1-22 output buffer latches figure 1-21 input buffer latches d g t outsu t outh pad obdlhs d g g pad pad clk clkbuf data t inh t hext data g clk t insu t suext ibdl
mx automotive family fpgas v2.0 1-19 decode module timing figure 1-23 decode module timing figure 1-24 sram timing characteristics a b c d e f g t phl a?g, h y t plh 50% y h wrad [5:0] blken wen wclk rdad [5:0] lew ren rclk rd [7:0] wd [7:0] write port ram array 32x8 or 64x4 (256 bits) read port
mx automotive family fpgas 1-20 v2.0 dual-port sram timing waveforms note: identical timing for falling edge clock. figure 1-25 42mx sram write operation note: identical timing for falling edge clock. figure 1-26 42mx sram synchronous read operation wclk wd[7:0] wrad[5:0] wen blken valid t bensu t wenh t benh valid t rckhl t wensu t adsu t adh t rckhl rclk ren rdad[5:0] rd[7:0] old data valid t rckhl t ckhl t renh t rco t adh t doh t adsu new data t rensu
mx automotive family fpgas v2.0 1-21 figure 1-27 42mx sram asynchronous read operation?type 1 figure 1-28 42mx sram asynchronous read operation?type 2 rdad[5:0] rd[7:0] data 1 t rdadv t doh addr2 addr1 data 2 t rpd (read address controlled) wen wd[7:0] wclk rd[7:0] wrad[5:0] blken old data valid t wenh t rpd t wensu new data t doh t adsu t adh (write address controlled)
mx automotive family fpgas 1-22 v2.0 predictable performance: tight delay distributions propagation delay between logic modules depends on the resistive and capacitive loading of the routing tracks, the interconnect elements, and the module inputs being driven. propagation delay increases as the length of routing tracks, the number of interconnect elements, or the number of inputs increases. from a design perspective, the propagation delay can be statistically correlated or modeled by the fanout (number of loads) driven by a module. higher fanout usually requires some paths to have longer routing tracks. the mx fpgas deliver a tight fanout delay distribution, which is achieved in two ways: by decreasing the delay of the interconnect elements and by decreasing the number of interconnect elements per path. actel?s patented antifuse offers a very low resistive/ capacitive interconnect. the antifuses, fabricated in 0.45 lithography, offer nominal levels of 100 ? resistance and 7.0 femtofarad (ff) capacitance per antifuse. mx fanout distribution is also tight due to the low number of antifuses required for each interconnect path. the proprietary architecture limits the number of antifuses per path to a maximum of four, with 90 percent of interconnects using only two antifuses. timing characteristics device timing characteristics fall into three categories: family-dependent, device-dependent, and design- dependent. the input and output buffer characteristics are common to all mx devices. internal routing delays are device-dependent. design dependency means actual delays are not determined until after place-and-route of the user?s design is complete. delay values may then be determined by using the designer series utility or by performing simulation with post-layout delays. critical nets and typical nets propagation delays in this data sheet apply to typical nets. the abundant routing resources in the mx architecture allows for deterministic timing using actel?s designer series development tools, which include tdpr, a timing-driven place-and-route tool. using timer, the designer can specify timing-critical nets and system clock frequency. using these timing specifications, the place- and-route software optimizes the layout of the design to meet the user?s specifications. long tracks some nets in the design use long tracks, which are special routing resources that span multiple rows, columns, or modules. long tracks employ three and sometimes four antifuse connections, which increase capacitance and resistance, resulting in longer net delays for macros connected to long tracks. typically, up to 6 percent of nets in a fully utilized device require long tracks. long tracks add approximately a 3 ns to a 6 ns delay, which is represented statistically in higher fanout (fo=8) routing delays in the data sheet specifications section, beginning on ?timing information? on page 1- 13 .
mx automotive family fpgas v2.0 1-23 temperature and voltage table 1-3 42mx temperature and voltage derating factors (normalized to t j = 125c, v cca /v cci = 4.5v) 42mx voltage temperature ?55c ?40c 0c 25c 70c 85c 125c 4.50 0.66 0.67 0.74 0.78 0.89 0.91 1.00 4.75 0.62 0.64 0.70 0.73 0.84 0.86 0.94 5.00 0.60 0.62 0.68 0.71 0.82 0.84 0.92 5.25 0.59 0.60 0.66 0.69 0.79 0.81 0.89 5.50 0.58 0.59 0.66 0.68 0.79 0.81 0.88 note: this derating factor applies to all routing and propagation delays. figure 1-29 42mx junction temperature and voltage derating curves (normalized to t j = 125c, v cca /v cci = 4.5v) 42mx derating factor (normalized to t j = 125?c, v cca /v cci =4.5v) -55 -40 0 25 70 85 125 derating factor 0.40 0.50 0.60 0.70 0.80 0.90 1.00 1.10 4.50 4.75 5.00 5.25 5.50 voltage
mx automotive family fpgas 1-24 v2.0 table 1-4 40mx temperature and voltage derating factors (normalized to t j = 125c, v cc = 4.5v) 40mx voltage temperature ?55c ?40c 0c 25c 70c 85c 125c 4.50 0.62 0.64 0.71 0.75 0.86 0.90 1.00 4.75 0.58 0.60 0.67 0.71 0.82 0.85 0.94 5.00 0.57 0.59 0.65 0.69 0.79 0.83 0.92 5.25 0.55 0.57 0.63 0.67 0.77 0.80 0.89 5.50 0.54 0.56 0.62 0.66 0.76 0.79 0.88 note: this derating factor applies to all routing and propagation delays. figure 1-30 40mx junction temperature and voltage derating curves (normalized to t j = 125c, v cca /v cci = 4.5v) 40mx derating factor (normalized to t j = 125?c, v cca /v cci =4.5v) -55 -40 0 25 70 85 125 derating factor 0.40 0.50 0.60 0.70 0.80 0.90 1.00 1.10 4.50 4.75 5.00 5.25 5.50 voltage
mx automotive family fpgas v2.0 1-25 timing characteristics table 1-5 a40mx02 timing characteristics (nominal 5.0v operation) worst-case automotive conditions, v cc = 4.75v, t j = 125c ?std? speed parameter description min. max. units logic module propagation delays t pd1 single module 2.3 ns t pd2 dual-module macros 5.0 ns t co sequential clock-to-q 2.3 ns t go latch g-to-q 2.3 ns t rs flip-flop (latch) reset-to-q 2.3 ns logic module predicted routing delays1 t rd1 fo=1 routing delay 2.5 ns t rd2 fo=2 routing delay 3.4 ns t rd3 fo=3 routing delay 4.4 ns t rd4 fo=4 routing delay 5.4 ns t rd8 fo=8 routing delay 9.3 ns logic module sequential timing2 t sud flip-flop (latch) data input set-up 5.8 ns t hd 3 flip-flop (latch) data input hold 0.0 ns t suena flip-flop (latch) enable set-up 5.8 ns t hena flip-flop (latch) enable hold 0.0 ns t wclka flip-flop (latch) clock active pulse width 6.1 ns t wasyn flip-flop (latch) asynchronous pulse width 6.1 ns t a flip-flop clock input period 9.2 ns f max flip-flop (latch) clock frequency (fo = 128) 163 mhz input module propagation delays t inyh pad-to-y high 1.4 ns t inyl pad-to-y low 1.2 ns input module predicted routing delays1 t ird1 fo=1 routing delay 3.9 ns t ird2 fo=2 routing delay 4.9 ns t ird3 fo=3 routing delay 5.9 ns t ird4 fo=4 routing delay 6.9 ns t ird8 fo=8 routing delay 10.8 ns 1. routing delays are for typical designs across worst-case operat ing conditions. these parameters should be used for estimating device performance. post-route timing analysis or si mulation is required to determine actual performance. 2. set-up times assume fanout of 3. further testing information can be obtained from the timer utility. 3. the hold time for the dfme1a macro may be greater than 0 ns. use the series or later timer to check the hold time for this ma cro. 4. delays based on 35 pf loading.
mx automotive family fpgas 1-26 v2.0 global clock network t ckh input low to high fo = 16 fo = 128 8.6 8.6 ns t ckl input high to low fo = 16 fo = 128 9.1 9.1 ns t pwh minimum pulse width high fo = 16 fo = 128 4.2 4.4 ns t pwl minimum pulse width low fo = 16 fo = 128 4.2 4.4 ns t cksw maximum skew fo = 16 fo = 128 0.7 1.0 ns t p minimum period fo = 16 fo = 128 8.8 7.2 ns f max maximum frequency fo = 16 fo = 128 170 164 mhz ttl output module timing 4 t dlh data-to-pad high 6.2 ns t dhl data-to-pad low 7.5 ns t enzh enable pad z to high 7.1 ns t enzl enable pad z to low 8.8 ns t enhz enable pad high to z 14.9 ns t enlz enable pad low to z 11 ns d tlh delta low to high 0.04 ns/pf d thl delta high to low 0.05 ns/pf cmos output module timing 4 t dlh data-to-pad high 7.4 ns t dhl data-to-pad low 6.4 ns t enzh enable pad z to high 6.4 ns t enzl enable pad z to low 9.2 ns t enhz enable pad high to z 14.9 ns t enlz enable pad low to z 11 ns d tlh delta low to high 0.06 ns/pf d thl delta high to low 0.04 ns/pf table 1-5 a40mx02 timing characteristics (nominal 5.0v operation) worst-case automotive conditions, v cc = 4.75v, t j = 125c (continued) ?std? speed parameter description min. max. units 1. routing delays are for typical designs across worst-case operat ing conditions. these parameters should be used for estimating device performance. post-route timing analysis or si mulation is required to determine actual performance. 2. set-up times assume fanout of 3. further testing information can be obtained from the timer utility. 3. the hold time for the dfme1a macro may be greater than 0 ns. use the series or later timer to check the hold time for this ma cro. 4. delays based on 35 pf loading.
mx automotive family fpgas v2.0 1-27 table 1-6 a40mx04 timing characteristics (nominal 5.0v operation) worst-case automotive conditions, v cc = 4.75v, t j = 125c ?std? speed parameter description min. max. units logic module propagation delays t pd1 single module 2.3 ns t pd2 dual-module macros 5.0 ns t co sequential clock-to-q 2.3 ns t go latch g-to-q 2.3 ns t rs flip-flop (latch) reset-to-q 2.3 ns logic module predicted routing delays 1 t rd1 fo=1 routing delay 2.6 ns t rd2 fo=2 routing delay 3.6 ns t rd3 fo=3 routing delay 4.5 ns t rd4 fo=4 routing delay 5.5 ns t rd8 fo=8 routing delay 9.5 ns logic module sequential timing 2 t sud flip-flop (latch) data input set-up 5.8 ns t hd 3 flip-flop (latch) data input hold 0.0 ns t suena flip-flop (latch) enable set-up 5.8 ns t hena flip-flop (latch) enable hold 0.0 ns t wclka flip-flop (latch) clock active pulse width 6.1 ns t wasyn flip-flop (latch) asynchronous pulse width 6.2 ns t a flip-flop clock input period 9.2 ns f max flip-flop (latch) clock frequency (fo = 128) 164 mhz input module propagation delays t inyh pad-to-y high 1.4 ns t inyl pad-to-y low 1.2 ns input module predicted routing delays 1 t ird1 fo=1 routing delay 3.9 ns t ird2 fo=2 routing delay 4.9 ns t ird3 fo=3 routing delay 5.9 ns t ird4 fo=4 routing delay 6.9 ns t ird8 fo=8 routing delay 10.7 ns 1. routing delays are for typical designs across worst-case operat ing conditions. these parameters should be used for estimating device performance. post-route timing analysis or si mulation is required to determine actual performance. 2. set-up times assume fanout of 3. further testing information can be obtained from the timer utility. 3. the hold time for the dfme1a macro may be greater than 0 ns. use the series or later timer to check the hold time for this ma cro. 4. delays based on 35 pf loading.
mx automotive family fpgas 1-28 v2.0 global clock network t ckh input low to high fo = 16 fo = 128 8.7 8.7 ns t ckl input high to low fo = 16 fo = 128 9.2 9.2 ns t pwh minimum pulse width high fo = 16 fo = 128 4.2 4.4 ns t pwl minimum pulse width low fo = 16 fo = 128 4.2 4.2 ns t cksw maximum skew fo = 16 fo = 128 0.7 1.0 ns t p minimum period fo = 16 fo = 128 8.8 9.2 ns f max maximum frequency fo = 16 fo = 128 170 164 mhz ttl output module timing 4 t dlh data-to-pad high 6.2 ns t dhl data-to-pad low 7.5 ns t enzh enable pad z to high 7.1 ns t enzl enable pad z to low 8.8 ns t enhz enable pad high to z 14.9 ns t enlz enable pad low to z 11 ns d tlh delta low to high 0.04 ns/pf d thl delta high to low 0.05 ns/pf cmos output module timing 4 t dlh data-to-pad high 7.5 ns t dhl data-to-pad low 6.4 ns t enzh enable pad z to high 6.4 ns t enzl enable pad z to low 9.2 ns t enhz enable pad high to z 14.9 ns t enlz enable pad low to z 11 ns d tlh delta low to high 0.07 ns/pf d thl delta high to low 0.05 ns/pf table 1-6 a40mx04 timing characteristics (nominal 5.0v operation) worst-case automotive conditions, v cc = 4.75v, t j = 125c (continued) ?std? speed parameter description min. max. units 1. routing delays are for typical designs across worst-case operat ing conditions. these parameters should be used for estimating device performance. post-route timing analysis or si mulation is required to determine actual performance. 2. set-up times assume fanout of 3. further testing information can be obtained from the timer utility. 3. the hold time for the dfme1a macro may be greater than 0 ns. use the series or later timer to check the hold time for this ma cro. 4. delays based on 35 pf loading.
mx automotive family fpgas v2.0 1-29 table 1-7 a42mx09 timing characteristics (nominal 5.0v operation) worst-case automotive conditions, v cc = 4.75v, t j = 125c ?std? speed parameter description min. max. units logic module propagation delays 1 t pd1 single module 2.1 ns t co sequential clock-to-q 2.2 ns t go latch g-to-q 2.1 ns t rs flip-flop (latch) reset-to-q 2.5 ns logic module predicted routing delays 2 t rd1 fo=1 routing delay 1.2 ns t rd2 fo=2 routing delay 1.7 ns t rd3 fo=3 routing delay 2.0 ns t rd4 fo=4 routing delay 2.4 ns t rd8 fo=8 routing delay 4.0 ns logic module sequential timing 3, 4 t sud flip-flop (latch) data input set-up 0.6 ns t hd flip-flop (latch) data input hold 0.0 ns t suena flip-flop (latch) enable set-up 0.7 ns t hena flip-flop (latch) enable hold 0.0 ns t wclka flip-flop (latch) clock active pulse width 5.9 ns t wasyn flip-flop (latch) asynchronous pulse width 7.8 ns t a flip-flop clock input period 6.0 ns t inh input buffer latch hold 0.0 ns t insu input buffer latch set-up 0.5 ns t outh output buffer latch hold 0.0 ns t outsu output buffer latch set-up 0.5 ns f max flip-flop (latch) clock frequency 229 mhz input module propagation delays t inyh pad-to-y high 1.9 ns t inyl pad-to-y low 1.4 ns 1. for dual-module macros, use t pd1 + t rd1 + t pdn , t co + t rd1 + t pdn , or t pd1 + t rd1 + t sud , whichever is appropriate. 2. routing delays are for typical designs across worst-case operat ing conditions. these parameters should be used for estimating device performance. post-route timing analysis or si mulation is required to determine actual performance. 3. data applies to macros based on the s-module. timing parameters for sequential macros constructed from c-modules can be obtained from the timer utility. 4. set-up and hold timing parameters for the input buffer latch are defined with respect to the pad and the d input. external se tup/ hold timing parameters must account for delay from an external pad signal to the g inputs. delay from an external pad signal to the g input subtracts (adds) to the internal setup (hold) time. 5. delays based on 35 pf loading.
mx automotive family fpgas 1-30 v2.0 t ingh g to y high 2.2 ns t ingl g to y low 2.2 ns input module predicted routing delays 2 t ird1 fo=1 routing delay 3.5 ns t ird2 fo=2 routing delay 4.0 ns t ird3 fo=3 routing delay 4.4 ns t ird4 fo=4 routing delay 4.8 ns t ird8 fo=8 routing delay 6.5 ns global clock network t ckh input low to high fo = 32 fo = 256 4.2 4.7 ns ns t ckl input high to low fo = 32 fo = 256 6.1 6.7 ns ns t pwh minimum pulse width high fo = 32 fo = 256 2.1 2.4 ns ns t pwl minimum pulse width low fo = 32 fo = 256 2.1 2.4 ns ns t cksw maximum skew fo = 32 fo = 256 0.6 0.6 ns ns t suext input latch external set-up fo = 32 fo = 256 0.0 0.0 ns ns t hext input latch external hold fo = 32 fo = 256 4.1 4.6 ns ns t p minimum period fo = 32 fo = 256 5.5 6.1 ns ns f max maximum frequency fo = 32 fo = 256 253 229 mhz mhz ttl output module timing 5 t dlh data-to-pad high 4.2 ns t dhl data-to-pad low 5.1 ns t enzh enable pad z to high 4.6 ns table 1-7 a42mx09 timing characteristics (nominal 5.0v operation) worst-case automotive conditions, v cc = 4.75v, t j = 125c (continued) ?std? speed parameter description min. max. units 1. for dual-module macros, use t pd1 + t rd1 + t pdn , t co + t rd1 + t pdn , or t pd1 + t rd1 + t sud , whichever is appropriate. 2. routing delays are for typical designs across worst-case operat ing conditions. these parameters should be used for estimating device performance. post-route timing analysis or si mulation is required to determine actual performance. 3. data applies to macros based on the s-module. timing parameters for sequential macros constructed from c-modules can be obtained from the timer utility. 4. set-up and hold timing parameters for the input buffer latch are defined with respect to the pad and the d input. external se tup/ hold timing parameters must account for delay from an external pad signal to the g inputs. delay from an external pad signal to the g input subtracts (adds) to the internal setup (hold) time. 5. delays based on 35 pf loading.
mx automotive family fpgas v2.0 1-31 t enzl enable pad z to low 5.1 ns t enhz enable pad high to z 8.6 ns t enlz enable pad low to z 9.3 ns t glh g-to-pad high 4.5 ns t ghl g-to-pad low 4.5 ns t lsu i/o latch set-up 0.8 ns t lh i/o latch hold 0.0 ns t lco i/o latch clock-to-out (pad-to-pad), 64 clock loading 9.1 ns t aco array clock-to-out (pad-to-pad), 64 clock loading 12.8 ns d tlh capacity loading, low to high 0.05 ns/pf d thl capacity loading, high to low 0.06 ns/pf cmos output module timing 5 t dlh data-to-pad high 4.2 ns t dhl data-to-pad low 5.1 ns t enzh enable pad z to high 4.6 ns t enzl enable pad z to low 5.1 ns t enhz enable pad high to z 8.6 ns t enlz enable pad low to z 9.3 ns t glh g-to-pad high 7.2 ns t ghl g-to-pad low 7.2 ns t lsu i/o latch set-up 0.8 ns t lh i/o latch hold 0.0 ns t lco i/o latch clock-to-out (pad-to-pad), 64 clock loading 9.1 ns t aco array clock-to-out (pad-to-pad), 64 clock loading 12.8 ns d tlh capacity loading, low to high 0.03 ns/pf d thl capacity loading, high to low 0.06 ns/pf table 1-7 a42mx09 timing characteristics (nominal 5.0v operation) worst-case automotive conditions, v cc = 4.75v, t j = 125c (continued) ?std? speed parameter description min. max. units 1. for dual-module macros, use t pd1 + t rd1 + t pdn , t co + t rd1 + t pdn , or t pd1 + t rd1 + t sud , whichever is appropriate. 2. routing delays are for typical designs across worst-case operat ing conditions. these parameters should be used for estimating device performance. post-route timing analysis or si mulation is required to determine actual performance. 3. data applies to macros based on the s-module. timing parameters for sequential macros constructed from c-modules can be obtained from the timer utility. 4. set-up and hold timing parameters for the input buffer latch are defined with respect to the pad and the d input. external se tup/ hold timing parameters must account for delay from an external pad signal to the g inputs. delay from an external pad signal to the g input subtracts (adds) to the internal setup (hold) time. 5. delays based on 35 pf loading.
mx automotive family fpgas 1-32 v2.0 table 1-8 a42mx16 timing characteristics (nominal 5.0v operation) worst-case automotive conditions, v cc = 4.75v, t j = 125c ?std? speed parameter description min. max. units logic module propagation delays 1 t pd1 single module 2.4 ns t co sequential clock-to-q 2.5 ns t go latch g-to-q 2.4 ns t rs flip-flop (latch) reset-to-q 2.7 ns logic module predicted routing delays 2 t rd1 fo=1 routing delay 1.4 ns t rd2 fo=2 routing delay 1.8 ns t rd3 fo=3 routing delay 2.2 ns t rd4 fo=4 routing delay 2.7 ns t rd8 fo=8 routing delay 4.5 ns logic module sequential timing 3,4 t sud flip-flop (latch) data input set-up 0.6 ns t hd flip-flop (latch) data input hold 0.0 ns t suena flip-flop (latch) enable set-up 1.2 ns t hena flip-flop (latch) enable hold 0.0 ns t wclka flip-flop (latch) clock active pulse width 5.9 ns t wasyn flip-flop (latch) asynchronous pulse width 7.8 ns t a flip-flop clock input period 11.8 ns t inh input buffer latch hold 0.0 ns t insu input buffer latch set-up 0.8 ns t outh output buffer latch hold 0.0 ns t outsu output buffer latch set-up 0.8 ns f max flip-flop (latch) clock frequency 1839.8 mhz input module propagation delays t inyh pad-to-y high 1.9 ns t inyl pad-to-y low 1.5 ns 1. for dual-module macros, use t pd1 + t rd1 + t pdn , t co + t rd1 + t pdn , or t pd1 + t rd1 + t sud , point and position whichever is appropriate. 2. routing delays are for typical designs across worst-case operat ing conditions. these parameters should be used for estimating device performance. post-route timing analysis or si mulation is required to determine actual performance. 3. data applies to macros based on the s-module. timing parameters for sequential macros constructed from c-modules can be obtained from the timer utility. 4. set-up and hold timing parameters for the input buffer latch are defined with respect to the pad and the d input. external se tup/ hold timing parameters must account for delay from an external pad signal to the g inputs. delay from an external pad signal to the g input subtracts (adds) to the internal setup (hold) time. 5. delays based on 35 pf loading.
mx automotive family fpgas v2.0 1-33 t ingh g to y high 2.5 ns t ingl g to y low 2.5 ns input module predicted routing delays2 t ird1 fo=1 routing delay 3.2 ns t ird2 fo=2 routing delay 3.6 ns t ird3 fo=3 routing delay 4.1 ns t ird4 fo=4 routing delay 4.6 ns t ird8 fo=8 routing delay 6.3 ns global clock network t ckh input low to high fo = 32 fo = 384 4.6 5.1 ns ns t ckl input high to low fo = 32 fo = 384 6.6 7.8 ns ns t pwh minimum pulse width high fo = 32 fo = 384 5.5 6.3 ns ns t pwl minimum pulse width low fo = 32 fo = 384 5.5 6.3 ns ns t cksw maximum skew fo = 32 fo = 384 0.6 0.6 ns ns t suext input latch external set-up fo = 32 fo = 384 0.0 0.0 ns ns t hext input latch external hold fo = 32 fo = 384 4.8 5.5 ns ns t p minimum period fo = 32 fo = 384 6.8 7.5 ns ns f max maximum frequency fo = 32 fo = 384 202 183 mhz mhz ttl output module timing5 t dlh data-to-pad high 4.4 ns t dhl data-to-pad low 5.2 ns table 1-8 a42mx16 timing characteristics (nominal 5.0v operation) worst-case automotive conditions, v cc = 4.75v, t j = 125c (continued) ?std? speed parameter description min. max. units 1. for dual-module macros, use t pd1 + t rd1 + t pdn , t co + t rd1 + t pdn , or t pd1 + t rd1 + t sud , point and position whichever is appropriate. 2. routing delays are for typical designs across worst-case operat ing conditions. these parameters should be used for estimating device performance. post-route timing analysis or si mulation is required to determine actual performance. 3. data applies to macros based on the s-module. timing parameters for sequential macros constructed from c-modules can be obtained from the timer utility. 4. set-up and hold timing parameters for the input buffer latch are defined with respect to the pad and the d input. external se tup/ hold timing parameters must account for delay from an external pad signal to the g inputs. delay from an external pad signal to the g input subtracts (adds) to the internal setup (hold) time. 5. delays based on 35 pf loading.
mx automotive family fpgas 1-34 v2.0 t enzh enable pad z to high 4.7 ns t enzl enable pad z to low 5.2 ns t enhz enable pad high to z 9.4 ns t enlz enable pad low to z 8.7 ns t glh g-to-pad high 5.1 ns t ghl g-to-pad low 5.1 ns t lco i/o latch clock-to-out (pad-to-pad), 64 clock loading 9.9 ns t aco array clock-to-out (pad-to-pad), 64 clock loading 14 ns d tlh capacitive loading, low to high 0.05 ns/pf d thl capacitive loading, high to low 0.06 ns/pf cmos output module timing 5 t dlh data-to-pad high 5.5 ns t dhl data-to-pad low 4.2 ns t enzh enable pad z to high 4.7 ns t enzl enable pad z to low 5.2 ns t enhz enable pad high to z 9.4 ns t enlz enable pad low to z 8.7 ns t glh g-to-pad high 8.8 ns t ghl g-to-pad low 8.8 ns t lco i/o latch clock-to-out (pad-to-pad), 64 clock loading 9.9 ns t aco array clock-to-out (pad-to-pad), 64 clock loading 14 ns d tlh capacitive loading, low to high 0.05 ns/pf d thl capacitive loading, high to low 0.06 ns/pf table 1-8 a42mx16 timing characteristics (nominal 5.0v operation) worst-case automotive conditions, v cc = 4.75v, t j = 125c (continued) ?std? speed parameter description min. max. units 1. for dual-module macros, use t pd1 + t rd1 + t pdn , t co + t rd1 + t pdn , or t pd1 + t rd1 + t sud , point and position whichever is appropriate. 2. routing delays are for typical designs across worst-case operat ing conditions. these parameters should be used for estimating device performance. post-route timing analysis or si mulation is required to determine actual performance. 3. data applies to macros based on the s-module. timing parameters for sequential macros constructed from c-modules can be obtained from the timer utility. 4. set-up and hold timing parameters for the input buffer latch are defined with respect to the pad and the d input. external se tup/ hold timing parameters must account for delay from an external pad signal to the g inputs. delay from an external pad signal to the g input subtracts (adds) to the internal setup (hold) time. 5. delays based on 35 pf loading.
mx automotive family fpgas v2.0 1-35 table 1-9 a42mx24 timing characteristics (nominal 5.0v operation) worst-case automotive conditions, v cc = 4.75v, t j = 125c ?std? speed parameter description min. max. units logic module combinatorial functions 1 t pd internal array module delay 2.1 ns t pdd internal decode module delay 2.5 ns logic module predicted routing delays 2 t rd1 fo=1 routing delay 1.4 ns t rd2 fo=2 routing delay 1.7 ns t rd3 fo=3 routing delay 2.2 ns t rd4 fo=4 routing delay 2.6 ns t rd5 fo=8 routing delay 4.2 ns logic module sequential timing 3, 4 t co flip-flop clock-to-output 2.2 ns t go latch gate-to-output 2.1 ns t su flip-flop (latch) set-up time 0.6 ns t h flip-flop (latch) hold time 0.0 ns t ro flip-flop (latch) reset-to-output 2.5 ns t suena flip-flop (latch) enable set-up 0.7 ns t hena flip-flop (latch) enable hold 0.0 ns t wclka flip-flop (latch) clock active pulse width 5.8 ns t wasyn flip-flop (latch) asynchronous pulse width 7.6 ns input module propagation delays t inpy input data pad-to-y 1.8 ns t ingo input latch gate-to-output 2.2 ns t inh input latch hold 0.0 ns t insu input latch set-up 0.8 ns t ila latch active pulse width 8.1 ns input module predicted routing delays 2 t ird1 fo=1 routing delay 3.2 ns 1. for dual-module macros, use t pd1 + t rd1 + t pdn , t co + t rd1 + t pdn , or t pd1 + t rd1 + t sud , whichever is appropriate. 2. routing delays are for typical designs across worst-case operat ing conditions. these parameters should be used for estimating device performance. post-route timing analysis or si mulation is required to determine actual performance. 3. data applies to macros based on the s-module. timing parameters for sequential macros constructed from c-modules can be obtained from the timer utility. 4. set-up and hold timing parameters for the input buffer latch are defined with respect to the pad and the d input. external se tup/ hold timing parameters must account for delay from an external pad signal to the g inputs. delay from an external pad signal to the g input subtracts (adds) to the internal setup (hold) time. 5. delays based on 35 pf loading.
mx automotive family fpgas 1-36 v2.0 t ird2 fo=2 routing delay 3.6 ns t ird3 fo=3 routing delay 4.0 ns t ird4 fo=4 routing delay 4.3 ns t ird8 fo=8 routing delay 6.0 ns global clock network t ckh input low to high fo=32 fo=486 4.6 5.1 ns ns t ckl input high to low fo=32 fo=486 6.3 7.4 ns ns t pwh minimum pulse width high fo=32 fo=486 3.8 4.1 ns ns t pwl minimum pulse width low fo=32 fo=486 3.8 4.1 ns ns t cksw maximum skew fo=32 fo=486 0.9 0.9 ns ns t suext input latch external set-up fo=32 fo=486 0.0 0.0 ns ns t hext input latch external hold fo=32 fo=486 4.8 5.8 ns ns t p minimum period (1/f max )fo=32 fo=486 7.6 8.4 ns ns f max maximum datapath frequency fo=32 fo=486 180 165 mhz mhz ttl output module timing5 t dlh data-to-pad high 4.2 ns t dhl data-to-pad low 4.9 ns t enzh enable pad z to high 4.5 ns t enzl enable pad z to low 4.9 ns t enhz enable pad high to z 8.9 ns t enlz enable pad low to z 8.3 ns t glh g-to-pad high 5.1 ns table 1-9 a42mx24 timing characteristics (nominal 5.0v operation) worst-case automotive conditions, v cc = 4.75v, t j = 125c (continued) ?std? speed parameter description min. max. units 1. for dual-module macros, use t pd1 + t rd1 + t pdn , t co + t rd1 + t pdn , or t pd1 + t rd1 + t sud , whichever is appropriate. 2. routing delays are for typical designs across worst-case operat ing conditions. these parameters should be used for estimating device performance. post-route timing analysis or si mulation is required to determine actual performance. 3. data applies to macros based on the s-module. timing parameters for sequential macros constructed from c-modules can be obtained from the timer utility. 4. set-up and hold timing parameters for the input buffer latch are defined with respect to the pad and the d input. external se tup/ hold timing parameters must account for delay from an external pad signal to the g inputs. delay from an external pad signal to the g input subtracts (adds) to the internal setup (hold) time. 5. delays based on 35 pf loading.
mx automotive family fpgas v2.0 1-37 t ghl g-to-pad low 5.1 ns t lsu i/o latch output set-up 0.8 ns t lh i/o latch output hold 0.0 ns t lco i/o latch clock-to-out (pad-to-pad) 32 i/o 9.5 ns t aco array latch clock-to-out (pad-to-pad) 32 i/o 18.5 ns d tlh capacitive loading, low to high 0.06 ns/pf d thl capacitive loading, high to low 0.05 ns/pf cmos output module timing 5 t dlh data-to-pad high 5.1 ns t dhl data-to-pad low 4.1 ns t enzh enable pad z to high 4.1 ns t enzl enable pad z to low 4.9 ns t enhz enable pad high to z 8.9 ns t enlz enable pad low to z 8.3 ns t glh g-to-pad high 8.5 ns t ghl g-to-pad low 8.5 ns t lsu i/o latch set-up 0.8 ns t lh i/o latch hold 0.0 ns t lco i/o latch clock-to-out (pad-to-pad) 32 i/o 9.5 ns t aco array latch clock-to-out (pad-to-pad) 32 i/o 18.5 ns d tlh capacitive loading, low to high 0.06 ns/pf d thl capacitive loading, high to low 0.05 ns/pf table 1-9 a42mx24 timing characteristics (nominal 5.0v operation) worst-case automotive conditions, v cc = 4.75v, t j = 125c (continued) ?std? speed parameter description min. max. units 1. for dual-module macros, use t pd1 + t rd1 + t pdn , t co + t rd1 + t pdn , or t pd1 + t rd1 + t sud , whichever is appropriate. 2. routing delays are for typical designs across worst-case operat ing conditions. these parameters should be used for estimating device performance. post-route timing analysis or si mulation is required to determine actual performance. 3. data applies to macros based on the s-module. timing parameters for sequential macros constructed from c-modules can be obtained from the timer utility. 4. set-up and hold timing parameters for the input buffer latch are defined with respect to the pad and the d input. external se tup/ hold timing parameters must account for delay from an external pad signal to the g inputs. delay from an external pad signal to the g input subtracts (adds) to the internal setup (hold) time. 5. delays based on 35 pf loading.
mx automotive family fpgas 1-38 v2.0 table 1-10 a42mx36 timing characteristics (nominal 5.0v operation) worst-case automotive conditions, v cc = 4.75v, t j = 125c ?std? speed parameter description min. max. units logic module combinatorial functions 1 t pd internal array module delay 2.4 ns t pdd internal decode module delay 2.8 ns logic module predicted routing delays 2 t rd1 fo=1 routing delay 1.6 ns t rd2 fo=2 routing delay 2.2 ns t rd3 fo=3 routing delay 2.8 ns t rd4 fo=4 routing delay 3.4 ns t rd5 fo=8 routing delay 5.8 ns t rdd decode-to-output routing delay 0.6 ns logic module sequential timing 3, 4 t co flip-flop clock-to-output 2.2 ns t go latch gate-to-output 2.2 ns t su flip-flop (latch) set-up time 0.6 ns t h flip-flop (latch) hold time 0.0 ns t ro flip-flop (latch) reset-to-output 2.7 ns t suena flip-flop (latch) enable set-up 1.2 ns t hena flip-flop (latch) enable hold 0.0 ns t wclka flip-flop (latch) clock active pulse width 5.8 ns t wasyn flip-flop (latch) asynchronous pulse width 7.5 ns synchronous sram operations t rc read cycle time 11.8 ns t wc write cycle time 11.8 ns t rckhl clock high/low time 5.9 ns t rco data valid after clock high/low 5.9 ns t adsu address/data set-up time 2.8 ns t adh address/data hold time 0.0 ns 1. for dual-module macros, use t pd1 + t rd1 + t pdn , t co + t rd1 + t pdn , or t pd1 + t rd1 + t sud , whichever is appropriate. 2. routing delays are for typical designs across worst-case operat ing conditions. these parameters should be used for estimating device performance. post-route timing analysis or si mulation is required to determine actual performance. 3. data applies to macros based on the s-module. timing parameters for sequential macros constructed from c-modules can be obtained from the timer utility. 4. set-up and hold timing parameters for the input buffer latch are defined with respect to the pad and the d input. external se tup/ hold timing parameters must account for delay from an external pad signal to the g inputs. delay from an external pad signal to the g input subtracts (adds) to the internal setup (hold) time. 5. delays based on 35 pf loading.
mx automotive family fpgas v2.0 1-39 t rensu read enable set-up 1.1 ns t renh read enable hold 5.9 ns t wensu write enable set-up 4.7 ns t wenh write enable hold 0.0 ns t bens block enable set-up 4.8 ns t benh block enable hold 0.0 ns asynchronous sram operations t rpd asynchronous access time 14.1 ns t rdadv read address valid 15.3 ns t adsu address/data set-up time 2.9 ns t adh address/data hold time 0.0 ns t rensua read enable set-up to address valid 1.1 ns t renha read enable hold 5.9 ns t wensu write enable set-up 4.7 ns t wenh write enable hold 0.0 ns t doh data out hold time 2.1 ns input module propagation delays t inpy input data pad-to-y 1.8 ns t ingo input latch gate-to-output 2.5 ns t inh input latch hold 0.0 ns t insu input latch set-up 0.8 ns t ila latch active pulse width 8.1 ns input module predicted routing delays 2 t ird1 fo=1 routing delay 3.4 ns t ird2 fo=2 routing delay 4.0 ns t ird3 fo=3 routing delay 4.6 ns t ird4 fo=4 routing delay 5.2 ns table 1-10 a42mx36 timing characteristics (nominal 5.0v operation) worst-case automotive conditions, v cc = 4.75v, t j = 125c (continued) ?std? speed parameter description min. max. units 1. for dual-module macros, use t pd1 + t rd1 + t pdn , t co + t rd1 + t pdn , or t pd1 + t rd1 + t sud , whichever is appropriate. 2. routing delays are for typical designs across worst-case operat ing conditions. these parameters should be used for estimating device performance. post-route timing analysis or si mulation is required to determine actual performance. 3. data applies to macros based on the s-module. timing parameters for sequential macros constructed from c-modules can be obtained from the timer utility. 4. set-up and hold timing parameters for the input buffer latch are defined with respect to the pad and the d input. external se tup/ hold timing parameters must account for delay from an external pad signal to the g inputs. delay from an external pad signal to the g input subtracts (adds) to the internal setup (hold) time. 5. delays based on 35 pf loading.
mx automotive family fpgas 1-40 v2.0 t ird8 fo=8 routing delay 7.5 ns global clock network t ckh input low to high fo=32 fo=635 4.7 5.2 ns ns t ckl input high to low fo=32 fo=635 6.6 8.5 ns ns t pwh minimum pulse width high fo=32 fo=635 3.1 3.4 ns ns t pwl minimum pulse width low fo=32 fo=635 3.1 3.4 ns ns t cksw maximum skew fo=32 fo=635 1.2 1.2 ns ns t suext input latch external set-up fo=32 fo=635 0.0 0.0 ns ns t hext input latch external hold fo=32 fo=635 4.9 5.8 ns ns t p minimum period (1/f max )fo=32 fo=635 8.9 9.8 ns ns f hmax maximum datapath frequency fo=32 fo=635 154 142 mhz mhz ttl output module timing 1 t dlh data-to-pad high 4.5 ns t dhl data-to-pad low 5.2 ns t enzh enable pad z to high 4.6 ns t enzl enable pad z to low 5.1 ns t enhz enable pad high to z 9.2 ns t enlz enable pad low to z 8.6 ns t glh g-to-pad high 5.2 ns t ghl g-to-pad low 5.2 ns t lsu i/o latch output set-up 0.8 ns t lh i/o latch output hold 0.0 ns table 1-10 a42mx36 timing characteristics (nominal 5.0v operation) worst-case automotive conditions, v cc = 4.75v, t j = 125c (continued) ?std? speed parameter description min. max. units 1. for dual-module macros, use t pd1 + t rd1 + t pdn , t co + t rd1 + t pdn , or t pd1 + t rd1 + t sud , whichever is appropriate. 2. routing delays are for typical designs across worst-case operat ing conditions. these parameters should be used for estimating device performance. post-route timing analysis or si mulation is required to determine actual performance. 3. data applies to macros based on the s-module. timing parameters for sequential macros constructed from c-modules can be obtained from the timer utility. 4. set-up and hold timing parameters for the input buffer latch are defined with respect to the pad and the d input. external se tup/ hold timing parameters must account for delay from an external pad signal to the g inputs. delay from an external pad signal to the g input subtracts (adds) to the internal setup (hold) time. 5. delays based on 35 pf loading.
mx automotive family fpgas v2.0 1-41 t lco i/o latch clock-to-out (pad-to-pad) 32 i/o 8.4 ns t aco array latch clock-to-out (pad-to-pad) 32 i/o 11.5 ns d tlh capacitive loading, low to high 0.10 ns/pf d thl capacitive loading, high to low 0.10 ns/pf cmos output module timing 5 t dlh data-to-pad high 6.1 ns t dhl data-to-pad low 4.2 ns t enzh enable pad z to high 4.6 ns t enzl enable pad z to low 5.1 ns t enhz enable pad high to z 9.2 ns t enlz enable pad low to z 8.6 ns t glh g-to-pad high 8.8 ns t ghl g-to-pad low 8.8 ns t lsu i/o latch set-up 0.8 ns t lh i/o latch hold 0.0 ns t lco i/o latch clock-to-out (pad-to-pad) 32 i/o 9.9 ns t aco array latch clock-to-out (pad-to-pad) 32 i/o 13.5 ns d tlh capacitive loading, low to high 0.12 ns/pf d thl capacitive loading, high to low 0.12 ns/pf table 1-10 a42mx36 timing characteristics (nominal 5.0v operation) worst-case automotive conditions, v cc = 4.75v, t j = 125c (continued) ?std? speed parameter description min. max. units 1. for dual-module macros, use t pd1 + t rd1 + t pdn , t co + t rd1 + t pdn , or t pd1 + t rd1 + t sud , whichever is appropriate. 2. routing delays are for typical designs across worst-case operat ing conditions. these parameters should be used for estimating device performance. post-route timing analysis or si mulation is required to determine actual performance. 3. data applies to macros based on the s-module. timing parameters for sequential macros constructed from c-modules can be obtained from the timer utility. 4. set-up and hold timing parameters for the input buffer latch are defined with respect to the pad and the d input. external se tup/ hold timing parameters must account for delay from an external pad signal to the g inputs. delay from an external pad signal to the g input subtracts (adds) to the internal setup (hold) time. 5. delays based on 35 pf loading.
mx automotive family fpgas 1-42 v2.0 pin descriptions clk, clka,b, i/o global clock (input) ttl clock inputs for clock distribution networks. the clock input is buffered prior to clocking the logic modules. this pin can also be used as an i/o. dclk, i/o diagnostic clock (input) ttl clock input for diagnostic probe and device programming. dclk is active when the mode pin is high. this pin functions as an i/o when the mode pin is low. gnd ground (input) input low supply voltage. i/o input/output (input, output) input, output, tri-state, or bi-directional buffer. input and output levels are compatible with standard ttl and cmos specifications. unused i/o pins are automatically driven low by the designer series software. mode mode (input) controls the use of multifunction pins (dclk, pra, prb, sdi, tdo). to provide verification capability, the mode pin should be held high. to facilitate this, the mode pin should be tied to gnd through a 10k ? resistor so that the mode pin can be pulled high when required. nc no connection this pin is not connected to circuitry within the device. these pins can be driven to any voltage or can be left floating with no effect on the operation of the device. pra, prb, i/o probe the pins are used for real-time diagnostic output of any signal path within the device. each pin can be used as a user-defined i/o when verification has been completed. the pin?s probe capabilities can be permanently disabled to protect programmed design confidentiality. pra and prb are accessible when the mode pin is high. these pins function as i/os when the mode pin is low. qclka,b,c,d, i/o quadrant clock (input/output) quadrant clock inputs. when not used as a register control signal, these pins can function as general- purpose i/os. sdi, i/o serial data input serial data input for diagnostic probe and device programming. sdi is active when the mode pin is high. this pin functions as an i/o when the mode pin is low. sdo, tdo, i/o serial data output serial data output for diagnostic probe and device programming. sdo is active when the mode pin is high. this pin functions as an i/o when the mode pin is low. sdo is not available for 40mx devices. tck, i/o test clock clock signal to shift the boundary scan test (bst) data into the device. this pin functions as an i/o when the test fuse is not programmed. bst pins are only available in the a42mx24 and a42mx36 devices. tdi, i/o test data in serial data input for bst instructions and data. data is shifted in on the rising edge of tck. this pin functions as an i/o when the test fuse is not programmed. bst pins are only available in the a42mx24 and a42mx36 devices. tdo, i/o test data out serial data output for bst instructions and test data. this pin functions as an i/o when the test fuse is not programmed. bst pins are only available in the a42mx24 and a42mx36 devices. tms, i/o test mode select serial data input for boundary scan test mode. data is shifted in on the rising edge of tck. this pin functions as an i/o when the test fuse is not programmed. bst pins are only available in the a42mx24 and a42mx36 devices. v cc supply voltage input input high supply voltage for 40 mx devices. v cca supply voltage input input high supply voltage, supplies array core for 42mx devices. v cci supply voltage input input high supply voltage, supplies i/o cells only for 42mx devices. wd, i/o wide decode output when a wide decode module is used in a 42mx device, this pin can be used as a dedicated output from the wide decode module. this direct connection eliminates additional interconnect delays associated with regular logic modules. to implement the direct i/o connection, connect an output buffer of any type to the output of the wide decode macro and place this output on one of the reserved wd pins. when a wide decode module is not used, this pin functions as a regular i/o pin.
package pin assignments v2.0 2-1 package pin assignments 68-pin plcc figure 2-1 68-pin plcc 68-pin plcc 1 68 68-pin plcc pin number a40mx02 function 1i/o 2i/o 3i/o 4v cc 5i/o 6i/o 7i/o 8i/o 9i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 gnd 15 gnd 16 i/o 17 i/o 18 i/o 19 i/o 20 i/o 21 v cc 22 i/o 23 i/o 24 i/o 25 v cc 26 i/o 27 i/o 28 i/o 29 i/o 30 i/o 31 i/o 32 gnd 33 i/o 34 i/o 35 i/o 36 i/o 68-pin plcc pin number a40mx02 function 37 i/o 38 v cc 39 i/o 40 i/o 41 i/o 42 i/o 43 i/o 44 i/o 45 i/o 46 i/o 47 i/o 48 i/o 49 gnd 50 i/o 51 i/o 52 clk, i/o 53 i/o 54 mode 68-pin plcc pin number a40mx02 function 55 v cc 56 sdi, i/o 57 dclk, i/o 58 pra, i/o 59 prb, i/o 60 i/o 61 i/o 62 i/o 63 i/o 64 i/o 65 i/o 66 gnd 67 i/o 68 i/o 68-pin plcc pin number a40mx02 function
package pin assignments 2-2 v2.0 84-pin plcc figure 2-2 84-pin plcc 184 84-pin plcc
package pin assignments v2.0 2-3 84-pin plcc pin number a40mx04 function a42mx09 function 1i/oi/o 2i/oclkb, i/o 3i/oi/o 4v cc prb, i/o 5i/oi/o 6i/ognd 7i/oi/o 8i/oi/o 9i/oi/o 10 i/o dclk, i/o 11 i/o i/o 12 nc mode 13 i/o i/o 14 i/o i/o 15 i/o i/o 16 i/o i/o 17 i/o i/o 18 gnd i/o 19 gnd i/o 20 i/o i/o 21 i/o i/o 22 i/o v cca 23 i/o v cci 24 i/o i/o 25 v cc i/o 26 v cc i/o 27 i/o i/o 28 i/o gnd 29 i/o i/o 30 i/o i/o 31 i/o i/o 32 i/o i/o 33 v cc i/o 34 i/o i/o 35 i/o i/o 36 i/o i/o 37 i/o i/o 38 i/o i/o 39 i/o i/o 40 gnd i/o 41 i/o i/o 42 i/o i/o 43 i/o v cca 44 i/o i/o 45 i/o i/o 46 v cc i/o 47 i/o i/o 48 i/o i/o 49 i/o gnd 50 i/o i/o 51 i/o i/o 52 i/o sdo, i/o 53 i/o i/o 54 i/o i/o 55 i/o i/o 56 i/o i/o 57 i/o i/o 58 i/o i/o 59 i/o i/o 60 gnd i/o 61 gnd i/o 62 i/o i/o 63 i/o gnd 64 clk, i/o v cca 65 i/o v cci 66 mode i/o 67 v cc i/o 68 v cc i/o 69 i/o i/o 70 i/o gnd 84-pin plcc pin number a40mx04 function a42mx09 function 71 i/o i/o 72 sdi, i/o i/o 73 dclk, i/o i/o 74 pra, i/o i/o 75 prb, i/o i/o 76 i/o sdi, i/o 77 i/o i/o 78 i/o i/o 79 i/o i/o 80 i/o i/o 81 i/o pra, i/o 82 gnd i/o 83 i/o clka, i/o 84 i/o v cca 84-pin plcc pin number a40mx04 function a42mx09 function
package pin assignments 2-4 v2.0 100-pin pqfp package (top view) figure 2-3 100-pin pqfp 100-pin pqfp 1 100
package pin assignments v2.0 2-5 100-pin pqfp pin number a40mx02 function a40mx04 function a42mx09 function 1ncnci/o 2ncncdclk, i/o 3ncnci/o 4ncncmode 5ncnci/o 6 prb, i/o prb, i/o i/o 7 i/o i/o i/o 8 i/o i/o i/o 9i/oi/ognd 10 i/o i/o i/o 11 i/o i/o i/o 12 i/o i/o i/o 13 gnd gnd i/o 14 i/o i/o i/o 15 i/o i/o i/o 16 i/o i/o v cca 17 i/o i/o v cci 18 i/o i/o i/o 19 v cc v cc i/o 20 i/o i/o i/o 21 i/o i/o i/o 22 i/o i/o gnd 23 i/o i/o i/o 24 i/o i/o i/o 25 i/o i/o i/o 26 i/o i/o i/o 27 nc nc i/o 28 nc nc i/o 29 nc nc i/o 30 nc nc i/o 31 nc i/o i/o 32 nc i/o i/o 33 nc i/o i/o 34 i/o i/o gnd 35 i/o i/o i/o 36 gnd gnd i/o 37 gnd gnd i/o 38 i/o i/o i/o 39 i/o i/o i/o 40 i/o i/o v cca 41 i/o i/o i/o 42 i/o i/o i/o 43 v cc v cc i/o 44 v cc v cc i/o 45 i/o i/o i/o 46 i/o i/o gnd 47 i/o i/o i/o 48 nc i/o i/o 49 nc i/o i/o 50 nc i/o i/o 51 nc nc i/o 52 nc nc sdo, i/o 53 nc nc i/o 54 nc nc i/o 55 nc nc i/o 56 v cc v cc i/o 57 i/o i/o gnd 58 i/o i/o i/o 59 i/o i/o i/o 60 i/o i/o i/o 61 i/o i/o i/o 62 i/o i/o i/o 63 gnd gnd i/o 64 i/o i/o gnd 65 i/o i/o v cca 66 i/o i/o v cci 67 i/o i/o v cca 68 i/o i/o i/o 69 v cc v cc i/o 70 i/o i/o i/o 100-pin pqfp pin number a40mx02 function a40mx04 function a42mx09 function
package pin assignments 2-6 v2.0 71 i/o i/o i/o 72 i/o i/o gnd 73 i/o i/o i/o 74 i/o i/o i/o 75 i/o i/o i/o 76 i/o i/o i/o 77 nc nc i/o 78 nc nc i/o 79 nc nc sdi, i/o 80 nc i/o i/o 81 nc i/o i/o 82 nc i/o i/o 83 i/o i/o i/o 84 i/o i/o gnd 85 i/o i/o i/o 86 gnd gnd i/o 87 gnd gnd pra, i/o 88 i/o i/o i/o 89 i/o i/o clka, i/o 90 clk, i/o clk, i/o v cca 91 i/o i/o i/o 92 mode mode clkb, i/o 93 v cc v cc i/o 94 v cc v cc prb, i/o 95 nc i/o i/o 96 nc i/o gnd 97 nc i/o i/o 98 sdi, i/o sdi, i/o i/o 99 dclk, i/o dclk, i/o i/o 100 pra, i/o pra, i/o i/o 100-pin pqfp pin number a40mx02 function a40mx04 function a42mx09 function
package pin assignments v2.0 2-7 160-pin pqfp package (top view) figure 2-4 pin pqfp 160 1 160-pin pqfp
package pin assignments 2-8 v2.0 160-pin pqfp pin number a42mx09 function a42mx24 function 1i/oi/o 2 dclk, i/o dclk, i/o 3nci/o 4 i/o wd, i/o 5 i/o wd, i/o 6ncv cci 7i/oi/o 8i/oi/o 9i/oi/o 10 nc i/o 11 gnd gnd 12 nc i/o 13 i/o wd, i/o 14 i/o wd, i/o 15 i/o i/o 16 prb, i/o prb, i/o 17 i/o i/o 18 clkb, i/o clkb, i/o 19 i/o i/o 20 v cca v cca 21 clka, i/o clka, i/o 22 i/o i/o 23 pra, i/o pra, i/o 24 nc wd, i/o 25 i/o wd, i/o 26 i/o i/o 27 i/o i/o 28 nc i/o 29 i/o wd, i/o 30 gnd gnd 31 nc wd, i/o 32 i/o i/o 33 i/o i/o 34 i/o i/o 35 nc v cci 36 i/o wd, i/o 37 i/o wd, i/o 38 sdi, i/o sdi, i/o 39 i/o i/o 40 gnd gnd 41 i/o i/o 42 i/o i/o 43 i/o i/o 44 gnd gnd 45 i/o i/o 46 i/o i/o 47 i/o i/o 48 i/o i/o 49 gnd gnd 50 i/o i/o 51 i/o i/o 52 nc i/o 53 i/o i/o 54 nc v cca 55 i/o i/o 56 i/o i/o 57 v cca v cca 58 v cci v cci 59 gnd gnd 60 v cca v cca 61 gnd gnd 62 i/o tck, i/o 63 i/o i/o 64 gnd gnd 65 i/o i/o 66 i/o i/o 67 i/o i/o 68 i/o i/o 69 gnd gnd 70 nc i/o 160-pin pqfp pin number a42mx09 function a42mx24 function
package pin assignments v2.0 2-9 71 i/o i/o 72 i/o i/o 73 i/o i/o 74 i/o i/o 75 nc i/o 76 i/o i/o 77 nc i/o 78 i/o i/o 79 nc i/o 80 gnd gnd 81 i/o i/o 82 sdo, i/o sdo, tdo, i/o 83 i/o wd, i/o 84 i/o wd, i/o 85 i/o i/o 86 nc v cci 87 i/o i/o 88 i/o wd, i/o 89 gnd gnd 90 nc i/o 91 i/o i/o 92 i/o i/o 93 i/o i/o 94 i/o i/o 95 i/o i/o 96 i/o wd, i/o 97 i/o i/o 98 v cca v cca 99 gnd gnd 100 nc i/o 101 i/o i/o 102 i/o i/o 103 nc i/o 104 i/o i/o 105 i/o i/o 160-pin pqfp pin number a42mx09 function a42mx24 function 106 i/o wd, i/o 107 i/o wd, i/o 108 i/o i/o 109 gnd gnd 110 nc i/o 111 i/o wd, i/o 112 i/o wd, i/o 113 i/o i/o 114 nc v cci 115 i/o wd, i/o 116 nc wd, i/o 117 i/o i/o 118 i/o tdi, i/o 119 i/o tms, i/o 120 gnd gnd 121 i/o i/o 122 i/o i/o 123 i/o i/o 124 nc i/o 125 gnd gnd 126 i/o i/o 127 i/o i/o 128 i/o i/o 129 nc i/o 130 gnd gnd 131 i/o i/o 132 i/o i/o 133 i/o i/o 134 i/o i/o 135 nc v cca 136 i/o i/o 137 i/o i/o 138 nc v cca 139 v cci v cci 140 gnd gnd 160-pin pqfp pin number a42mx09 function a42mx24 function
package pin assignments 2-10 v2.0 141 nc i/o 142 i/o i/o 143 i/o i/o 144 i/o i/o 145 gnd gnd 146 nc i/o 147 i/o i/o 148 i/o i/o 149 i/o i/o 150 nc v cca 151 nc i/o 152 nc i/o 153 nc i/o 154 nc i/o 155 gnd gnd 156 i/o i/o 157 i/o i/o 158 i/o i/o 159 mode mode 160 gnd gnd 160-pin pqfp pin number a42mx09 function a42mx24 function
package pin assignments v2.0 2-11 208-pin pqfp package (top view) figure 2-5 208-pin pqfp 208-pin pqfp 1 208
package pin assignments 2-12 v2.0 208-pin pqfp pin number a42mx16 function a42mx24 function a42mx36 function 1 gnd gnd gnd 2ncv cca v cca 3 mode mode mode 4 i/o i/o i/o 5 i/o i/o i/o 6 i/o i/o i/o 7 i/o i/o i/o 8 i/o i/o i/o 9nci/oi/o 10 nc i/o i/o 11 nc i/o i/o 12 i/o i/o i/o 13 i/o i/o i/o 14 i/o i/o i/o 15 i/o i/o i/o 16 nc i/o i/o 17 v cca v cca v cca 18 i/o i/o i/o 19 i/o i/o i/o 20 i/o i/o i/o 21 i/o i/o i/o 22 gnd gnd gnd 23 i/o i/o i/o 24 i/o i/o i/o 25 i/o i/o i/o 26 i/o i/o i/o 27 gnd gnd gnd 28 v cci v cci v cci 29 v cca v cca v cca 30 i/o i/o i/o 31 i/o i/o i/o 32 v cca v cca v cca 33 i/o i/o i/o 34 i/o i/o i/o 35 i/o i/o i/o 36 i/o i/o i/o 37 i/o i/o i/o 38 i/o i/o i/o 39 i/o i/o i/o 40 i/o i/o i/o 41 nc i/o i/o 42 nc i/o i/o 43 nc i/o i/o 44 i/o i/o i/o 45 i/o i/o i/o 46 i/o i/o i/o 47 i/o i/o i/o 48 i/o i/o i/o 49 i/o i/o i/o 50 nc i/o i/o 51 nc i/o i/o 52 gnd gnd gnd 53 gnd gnd gnd 54 i/o tms, i/o tms, i/o 55 i/o tdi, i/o tdi, i/o 56 i/o i/o i/o 57 i/o wd, i/o wd, i/o 58 i/o wd, i/o wd, i/o 59 i/o i/o i/o 60 v cci v cci v cci 61 nc i/o i/o 62 nc i/o i/o 63 i/o i/o i/o 64 i/o i/o i/o 65 i/o i/o qclka, i/o 66 i/o wd, i/o wd, i/o 67 nc wd, i/o wd, i/o 68 nc i/o i/o 69 i/o i/o i/o 70 i/o wd, i/o wd, i/o 208-pin pqfp pin number a42mx16 function a42mx24 function a42mx36 function
package pin assignments v2.0 2-13 71 i/o wd, i/o wd, i/o 72 i/o i/o i/o 73 i/o i/o i/o 74 i/o i/o i/o 75 i/o i/o i/o 76 i/o i/o i/o 77 i/o i/o i/o 78 gnd gnd gnd 79 v cca v cca v cca 80 nc v cci v cci 81 i/o i/o i/o 82 i/o i/o i/o 83 i/o i/o i/o 84 i/o i/o i/o 85 i/o wd, i/o wd, i/o 86 i/o wd, i/o wd, i/o 87 i/o i/o i/o 88 i/o i/o i/o 89 nc i/o i/o 90 nc i/o i/o 91 i/o i/o qclkb, i/o 92 i/o i/o i/o 93 i/o wd, i/o wd, i/o 94 i/o wd, i/o wd, i/o 95 nc i/o i/o 96 nc i/o i/o 97 nc i/o i/o 98 v cci v cci v cci 99 i/o i/o i/o 100 i/o wd, i/o wd, i/o 101 i/o wd, i/o wd, i/o 102 i/o i/o i/o 103 sdo, i/o sdo, tdo, i/o sdo, tdo, i/o 104 i/o i/o i/o 105 gnd gnd gnd 208-pin pqfp pin number a42mx16 function a42mx24 function a42mx36 function 106 nc v cca v cca 107 i/o i/o i/o 108 i/o i/o i/o 109 i/o i/o i/o 110 i/o i/o i/o 111 i/o i/o i/o 112 nc i/o i/o 113 nc i/o i/o 114 nc i/o i/o 115 nc i/o i/o 116 i/o i/o i/o 117 i/o i/o i/o 118 i/o i/o i/o 119 i/o i/o i/o 120 i/o i/o i/o 121 i/o i/o i/o 122 i/o i/o i/o 123 i/o i/o i/o 124 i/o i/o i/o 125 i/o i/o i/o 126 gnd gnd gnd 127 i/o i/o i/o 128 i/o tck, i/o tck, i/o 129 gnd gnd gnd 130 v cca v cca v cca 131 gnd gnd gnd 132 v cci v cci v cci 133 v cca v cca v cca 134 i/o i/o i/o 135 i/o i/o i/o 136 v cca v cca v cca 137 i/o i/o i/o 138 i/o i/o i/o 139 i/o i/o i/o 140 i/o i/o i/o 208-pin pqfp pin number a42mx16 function a42mx24 function a42mx36 function
package pin assignments 2-14 v2.0 141 nc i/o i/o 142 i/o i/o i/o 143 i/o i/o i/o 144 i/o i/o i/o 145 i/o i/o i/o 146 nc i/o i/o 147 nc i/o i/o 148 nc i/o i/o 149 nc i/o i/o 150 gnd gnd gnd 151 i/o i/o i/o 152 i/o i/o i/o 153 i/o i/o i/o 154 i/o i/o i/o 155 i/o i/o i/o 156 i/o i/o i/o 157 gnd gnd gnd 158 i/o i/o i/o 159 sdi, i/o sdi, i/o sdi, i/o 160 i/o i/o i/o 161 i/o wd, i/o wd, i/o 162 i/o wd, i/o wd, i/o 163 i/o i/o i/o 164 v cci v cci v cci 165 nc i/o i/o 166 nc i/o i/o 167 i/o i/o i/o 168 i/o wd, i/o wd, i/o 169 i/o wd, i/o wd, i/o 170 i/o i/o i/o 171 nc i/o qclkd, i/o 172 i/o i/o i/o 173 i/o i/o i/o 174 i/o i/o i/o 175 i/o i/o i/o 208-pin pqfp pin number a42mx16 function a42mx24 function a42mx36 function 176 i/o wd, i/o wd, i/o 177 i/o wd, i/o wd, i/o 178 pra, i/o pra, i/o pra, i/o 179 i/o i/o i/o 180 clka, i/o clka, i/o clka, i/o 181 nc i/o i/o 182 nc v cci v cci 183 v cca v cca v cca 184 gnd gnd gnd 185 i/o i/o i/o 186 clkb, i/o clkb, i/o clkb, i/o 187 i/o i/o i/o 188 prb, i/o prb, i/o prb, i/o 189 i/o i/o i/o 190 i/o wd, i/o wd, i/o 191 i/o wd, i/o wd, i/o 192 i/o i/o i/o 193 nc i/o i/o 194 nc wd, i/o wd, i/o 195 nc wd, i/o wd, i/o 196 i/o i/o qclkc, i/o 197 nc i/o i/o 198 i/o i/o i/o 199 i/o i/o i/o 200 i/o i/o i/o 201 nc i/o i/o 202 v cci v cci v cci 203 i/o wd, i/o wd, i/o 204 i/o wd, i/o wd, i/o 205 i/o i/o i/o 206 i/o i/o i/o 207 dclk, i/o dclk, i/o dclk, i/o 208 i/o i/o i/o 208-pin pqfp pin number a42mx16 function a42mx24 function a42mx36 function
package pin assignments v2.0 2-15 240-pin pqfp package (top view) figure 2-6 240-pin pqfp 240-pin pqfp 1 240 ?
package pin assignments 2-16 v2.0 240-pin pqfp pin number a42mx36 function 1i/o 2dclk, i/o 3i/o 4i/o 5i/o 6wd, i/o 7wd, i/o 8v cci 9i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 qclkc, i/o 16 i/o 17 wd, i/o 18 wd, i/o 19 i/o 20 i/o 21 wd, i/o 22 wd, i/o 23 i/o 24 prb, i/o 25 i/o 26 clkb, i/o 27 i/o 28 gnd 29 v cca 30 v cci 31 i/o 32 clka, i/o 33 i/o 34 pra, i/o 35 i/o 36 i/o 37 wd, i/o 38 wd, i/o 39 i/o 40 i/o 41 i/o 42 i/o 43 i/o 44 i/o 45 qclkd, i/o 46 i/o 47 wd, i/o 48 wd, i/o 49 i/o 50 i/o 51 i/o 52 v cci 53 i/o 54 wd, i/o 55 wd, i/o 56 i/o 57 sdi, i/o 58 i/o 59 v cca 60 gnd 61 gnd 62 i/o 63 i/o 64 i/o 65 i/o 66 i/o 67 i/o 68 i/o 69 i/o 70 i/o 240-pin pqfp pin number a42mx36 function 71 v cci 72 i/o 73 i/o 74 i/o 75 i/o 76 i/o 77 i/o 78 i/o 79 i/o 80 i/o 81 i/o 82 i/o 83 i/o 84 i/o 85 v cca 86 i/o 87 i/o 88 v cca 89 v cci 90 v cca 91 gnd 92 tck, i/o 93 i/o 94 gnd 95 i/o 96 i/o 97 i/o 98 i/o 99 i/o 100 i/o 101 i/o 102 i/o 103 i/o 104 i/o 105 i/o 240-pin pqfp pin number a42mx36 function 106 i/o 107 i/o 108 v cci 109 i/o 110 i/o 111 i/o 112 i/o 113 i/o 114 i/o 115 i/o 116 i/o 117 i/o 118 v cca 119 gnd 120 gnd 121 gnd 122 i/o 123 sdo, tdo, i/o 124 i/o 125 wd, i/o 126 wd, i/o 127 i/o 128 v cci 129 i/o 130 i/o 131 i/o 132 wd, i/o 133 wd, i/o 134 i/o 135 qclkb, i/o 136 i/o 137 i/o 138 i/o 139 i/o 140 i/o 240-pin pqfp pin number a42mx36 function
package pin assignments v2.0 2-17 141 i/o 142 wd, i/o 143 wd, i/o 144 i/o 145 i/o 146 i/o 147 i/o 148 i/o 149 i/o 150 v cci 151 v cca 152 gnd 153 i/o 154 i/o 155 i/o 156 i/o 157 i/o 158 i/o 159 wd, i/o 160 wd, i/o 161 i/o 162 i/o 163 wd, i/o 164 wd, i/o 165 i/o 166 qclka, i/o 167 i/o 168 i/o 169 i/o 170 i/o 171 i/o 172 v cci 173 i/o 174 wd, i/o 175 wd, i/o 240-pin pqfp pin number a42mx36 function 176 i/o 177 i/o 178 tdi, i/o 179 tms, i/o 180 gnd 181 v cca 182 gnd 183 i/o 184 i/o 185 i/o 186 i/o 187 i/o 188 i/o 189 i/o 190 i/o 191 i/o 192 v cci 193 i/o 194 i/o 195 i/o 196 i/o 197 i/o 198 i/o 199 i/o 200 i/o 201 i/o 202 i/o 203 i/o 204 i/o 205 i/o 206 v cca 207 i/o 208 i/o 209 v cca 210 v cci 240-pin pqfp pin number a42mx36 function 211 i/o 212 i/o 213 i/o 214 i/o 215 i/o 216 i/o 217 i/o 218 i/o 219 v cca 220 i/o 221 i/o 222 i/o 223 i/o 224 i/o 225 i/o 226 i/o 227 v cci 228 i/o 229 i/o 230 i/o 231 i/o 232 i/o 233 i/o 234 i/o 235 i/o 236 i/o 237 gnd 238 mode 239 v cca 240 gnd 240-pin pqfp pin number a42mx36 function
package pin assignments 2-18 v2.0 80-pin vqfp figure 2-7 80-pin vqfp 80-pin vqfp 80 1
package pin assignments v2.0 2-19 80-pin vqfp pin number a40mx02 function a40mx04 function 1i/oi/o 2nci/o 3nci/o 4nci/o 5i/oi/o 6i/oi/o 7gndgnd 8i/oi/o 9i/oi/o 10 i/o i/o 11 i/o i/o 12 i/o i/o 13 v cc v cc 14 i/o i/o 15 i/o i/o 16 i/o i/o 17 nc i/o 18 nc i/o 19 nc i/o 20 v cc v cc 21 i/o i/o 22 i/o i/o 23 i/o i/o 24 i/o i/o 25 i/o i/o 26 i/o i/o 27 gnd gnd 28 i/o i/o 29 i/o i/o 30 i/o i/o 31 i/o i/o 32 i/o i/o 33 v cc v cc 34 i/o i/o 35 i/o i/o 36 i/o i/o 37 i/o i/o 38 i/o i/o 39 i/o i/o 40 i/o i/o 41 nc i/o 42 nc i/o 43 nc i/o 44 i/o i/o 45 i/o i/o 46 i/o i/o 47 gnd gnd 48 i/o i/o 49 i/o i/o 50 clk, i/o clk, i/o 51 i/o i/o 52 mode mode 53 v cc v cc 54 nc i/o 55 nc i/o 56 nc i/o 57 sdi, i/o sdi, i/o 58 dclk, i/o dclk, i/o 59 pra, i/o pra, i/o 60 nc nc 61 prb, i/o prb, i/o 62 i/o i/o 63 i/o i/o 64 i/o i/o 65 i/o i/o 66 i/o i/o 67 i/o i/o 68 gnd gnd 69 i/o i/o 70 i/o i/o 71 i/o i/o 72 i/o i/o 73 i/o i/o 74 v cc v cc 75 i/o i/o 76 i/o i/o 77 i/o i/o 78 i/o i/o 79 i/o i/o 80 i/o i/o 80-pin vqfp pin number a40mx02 function a40mx04 function
package pin assignments 2-20 v2.0 100-pin vqfp package (top view) figure 2-8 100-pin vqfp 1 100-pin vqfp 100
package pin assignments v2.0 2-21 100-pin vqfp pin number a42mx09 function a42mx16 function 1i/oi/o 2 mode mode 3i/oi/o 4i/oi/o 5i/oi/o 6i/oi/o 7gndgnd 8i/oi/o 9i/oi/o 10 i/o i/o 11 i/o i/o 12 i/o i/o 13 i/o i/o 14 v cca nc 15 v cci v cci 16 i/o i/o 17 i/o i/o 18 i/o i/o 19 i/o i/o 20 gnd gnd 21 i/o i/o 22 i/o i/o 23 i/o i/o 24 i/o i/o 25 i/o i/o 26 i/o i/o 27 i/o i/o 28 i/o i/o 29 i/o i/o 30 i/o i/o 31 i/o i/o 32 gnd gnd 33 i/o i/o 34 i/o i/o 35 i/o i/o 36 i/o i/o 37 i/o i/o 38 v cca v cca 39 i/o i/o 40 i/o i/o 41 i/o i/o 42 i/o i/o 43 i/o i/o 44 gnd gnd 45 i/o i/o 46 i/o i/o 47 i/o i/o 48 i/o i/o 49 i/o i/o 50 sdo, i/o sdo, i/o 51 i/o i/o 52 i/o i/o 53 i/o i/o 54 i/o i/o 55 gnd gnd 56 i/o i/o 57 i/o i/o 58 i/o i/o 59 i/o i/o 60 i/o i/o 61 i/o i/o 62 gnd gnd 63 v cca v cca 64 v cci v cci 65 v cca v cca 66 i/o i/o 67 i/o i/o 68 i/o i/o 69 i/o i/o 70 gnd gnd 100-pin vqfp pin number a42mx09 function a42mx16 function
package pin assignments 2-22 v2.0 71 i/o i/o 72 i/o i/o 73 i/o i/o 74 i/o i/o 75 i/o i/o 76 i/o i/o 77 sdi, i/o sdi, i/o 78 i/o i/o 79 i/o i/o 80 i/o i/o 81 i/o i/o 82 gnd gnd 83 i/o i/o 84 i/o i/o 85 pra, i/o pra, i/o 86 i/o i/o 87 clka, i/o clka, i/o 88 v cca v cca 89 i/o i/o 90 clkb, i/o clkb, i/o 91 i/o i/o 92 prb, i/o prb, i/o 93 i/o i/o 94 gnd gnd 95 i/o i/o 96 i/o i/o 97 i/o i/o 98 i/o i/o 99 i/o i/o 100 dclk, i/o dclk, i/o 100-pin vqfp pin number a42mx09 function a42mx16 function
package pin assignments v2.0 2-23 176-pin tqfp package (top view) figure 2-9 176-pin tqfp 176-pin tqfp 176 1
package pin assignments 2-24 v2.0 176-pin tqfp pin number a42mx09 function a42mx16 function a42mx24 function 1 gnd gnd gnd 2 mode mode mode 3 i/o i/o i/o 4 i/o i/o i/o 5 i/o i/o i/o 6 i/o i/o i/o 7 i/o i/o i/o 8ncnci/o 9 i/o i/o i/o 10 nc i/o i/o 11 nc i/o i/o 12 i/o i/o i/o 13 nc v cca v cca 14 i/o i/o i/o 15 i/o i/o i/o 16 i/o i/o i/o 17 i/o i/o i/o 18 gnd gnd gnd 19 nc i/o i/o 20 nc i/o i/o 21 i/o i/o i/o 22 nc i/o i/o 23 gnd gnd gnd 24 nc v cci v cci 25 v cca v cca v cca 26 nc i/o i/o 27 nc i/o i/o 28 v cci v cca v cca 29 nc i/o i/o 30 i/o i/o i/o 31 i/o i/o i/o 32 i/o i/o i/o 33 nc nc i/o 34 i/o i/o i/o 35 i/o i/o i/o 36 i/o i/o i/o 37 nc i/o i/o 38 nc nc i/o 39 i/o i/o i/o 40 i/o i/o i/o 41 i/o i/o i/o 42 i/o i/o i/o 43 i/o i/o i/o 44 i/o i/o i/o 45 gnd gnd gnd 46 i/o i/o tms, i/o 47 i/o i/o tdi, i/o 48 i/o i/o i/o 49 i/o i/o wd, i/o 50 i/o i/o wd, i/o 51 i/o i/o i/o 52 nc v cci v cci 53 i/o i/o i/o 54 nc i/o i/o 55 nc i/o wd, i/o 56 i/o i/o wd, i/o 57 nc nc i/o 58 i/o i/o i/o 59 i/o i/o wd, i/o 60 i/o i/o wd, i/o 61 nc i/o i/o 62 i/o i/o i/o 63 i/o i/o i/o 64 nc i/o i/o 65 i/o i/o i/o 66 nc i/o i/o 67 gnd gnd gnd 68 v cca v cca v cca 69 i/o i/o wd, i/o 70 i/o i/o wd, i/o 71 i/o i/o i/o 72 i/o i/o i/o 73 i/o i/o i/o 74 nc i/o i/o 176-pin tqfp pin number a42mx09 function a42mx16 function a42mx24 function
package pin assignments v2.0 2-25 75 i/o i/o i/o 76 i/o i/o i/o 77 nc nc wd, i/o 78 nc i/o wd, i/o 79 i/o i/o i/o 80 nc i/o i/o 81 i/o i/o i/o 82 nc v cci v cci 83 i/o i/o i/o 84 i/o i/o wd, i/o 85 i/o i/o wd, i/o 86 nc i/o i/o 87 sdo, i/o sdo, i/o sdo, tdo, i/o 88 i/o i/o i/o 89 gnd gnd gnd 90 i/o i/o i/o 91 i/o i/o i/o 92 i/o i/o i/o 93 i/o i/o i/o 94 i/o i/o i/o 95 i/o i/o i/o 96 nc i/o i/o 97 nc i/o i/o 98 i/o i/o i/o 99 i/o i/o i/o 100 i/o i/o i/o 101 nc nc i/o 102 i/o i/o i/o 103 nc i/o i/o 104 i/o i/o i/o 105 i/o i/o i/o 106 gnd gnd gnd 107 nc i/o i/o 108 nc i/o tck, i/o 109 gnd gnd gnd 110 v cca v cca v cca 111 gnd gnd gnd 176-pin tqfp pin number a42mx09 function a42mx16 function a42mx24 function 112 v cci v cci v cci 113 v cca v cca v cca 114 nc i/o i/o 115 nc i/o i/o 116 nc v cca v cca 117 i/o i/o i/o 118 i/o i/o i/o 119 i/o i/o i/o 120 i/o i/o i/o 121 nc nc i/o 122 i/o i/o i/o 123 i/o i/o i/o 124 nc i/o i/o 125 nc i/o i/o 126 nc nc i/o 127 i/o i/o i/o 128 i/o i/o i/o 129 i/o i/o i/o 130 i/o i/o i/o 131 i/o i/o i/o 132 i/o i/o i/o 133 gnd gnd gnd 134 i/o i/o i/o 135 sdi, i/o sdi, i/o sdi, i/o 136 nc i/o i/o 137 i/o i/o wd, i/o 138 i/o i/o wd, i/o 139 i/o i/o i/o 140 nc v cci v cci 141 i/o i/o i/o 142 i/o i/o i/o 143 nc i/o i/o 144 nc i/o wd, i/o 145 nc nc wd, i/o 146 i/o i/o i/o 147 nc i/o i/o 148 i/o i/o i/o 176-pin tqfp pin number a42mx09 function a42mx16 function a42mx24 function
package pin assignments 2-26 v2.0 149 i/o i/o i/o 150 i/o i/o wd, i/o 151 nc i/o wd, i/o 152 pra, i/o pra, i/o pra, i/o 153 i/o i/o i/o 154 clka, i/o clka, i/o clka, i/o 155 v cca v cca v cca 156 gnd gnd gnd 157 i/o i/o i/o 158 clkb, i/o clkb, i/o clkb, i/o 159 i/o i/o i/o 160 prb, i/o prb, i/o prb, i/o 161 nc i/o wd, i/o 162 i/o i/o wd, i/o 163 i/o i/o i/o 164 i/o i/o i/o 165 nc nc wd, i/o 166 nc i/o wd, i/o 167 i/o i/o i/o 168 nc i/o i/o 169 i/o i/o i/o 170 nc v cci v cci 171 i/o i/o wd, i/o 172 i/o i/o wd, i/o 173 nc i/o i/o 174 i/o i/o i/o 175 dclk, i/o dclk, i/o dclk, i/o 176 i/o i/o i/o 176-pin tqfp pin number a42mx09 function a42mx16 function a42mx24 function
package pin assignments v2.0 2-27 data sheet categories in order to provide the latest information to designers, some datasheets are published before data has been fully characterized. datasheets are designated as ?product brief,? ?advanced,? ?production,? and ?datasheet supplement.? the definition of these categories are as follows: product brief the product brief is a summarized version of a datasheet (advanced or production) containing general product information. this brief gives an overview of specific device and family information. advanced this datasheet version contains initial estimated information based on simulation, other products, devices, or speed grades. this information can be used as estimates, but not for production. unmarked (production) this datasheet version contains information that is considered to be final. datasheet supplement the datasheet supplement gives specific device information for a derivative family that differs from the general family datasheet. the supplement is to be used in conjunction with the datasheet to obtain more detailed information and for specifications that do not differ between the two families.
51700025-0/09.01 http://www.actel.com actel and the actel logo are registered trademarks of actel corporation. all other trademarks are the property of their owners. actel corporation 2061 stierlin court mountain view, ca 94043-4655 usa tel: (650) 318-4200 fax: (650) 318-4600 actel europe ltd. dunlop house, riverside way camberley, surrey gu15 3yl united kingdom tel: +44 (0)1276 401450 fax: +44 (0)1276 401490 actel japan exos ebisu bldg. 4f 1-24-14 ebisu shibuya-ku tokyo 150 japan tel: +81 03-3445-7671 fax: +81 03-3445-7668 actel hong kong 39th floor one pacific place 88 queensway admiralty, hong kong tel: 852-22735712

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