26185.114h description the merging of low-power cmos logic and bipolar output power drivers using the proprietary dabic-5 fabrication process permit the a6841 integrated circuits to be used in a wide variety of peripheral power driver applications. each device has an eight-bit cmos shift register and cmos control circuitry, eight cmos data latches, and eight bipolar current-sinking darlington output drivers. the 500 ma, npn darlington outputs, with integral transient-suppression diodes, are suitable for use with relays, solenoids, and other inductive loads. all package variations of the a6841 offer premium performance with a minimum output-breakdown voltage rating of 50 v (35 v sustaining). all drivers can be operated with a split supply where the negative supply is up to ?20 v. the cmos inputs are compatible with standard cmos logic levels. ttl circuits may require the use of appropriate pull-up resistors. by using the serial data output, drivers can be cascaded for interface applications requiring additional drive lines. the a6841 is provided in an 18-pin plastic dip (suffix a), and a 20-pin wide-body soic (suffix lw) with improved thermal characteristics compared to the 18-pin soic version it replaces (100% pin-compatible electrically). these devices are lead (pb) free, with 100% matte tin plated leadframes. applications include: ? relays ? solenoids ? inductive loads features and benefits ? 3.3 to 5 v logic supply range ? power-on reset (por) ? to 10 mhz data input rate ? cmos, ttl compatible inputs ? ?40c operation available ? low-power cmos logic and latches ? schmitt trigger inputs for improved noise immunity ? high-voltage current-sink outputs ? internal pull-up/pull-down resistors ? output transient-protection diodes ? single or split supply operation dabic-5 8-bit serial input latched sink drivers packages: functional block diagram not to scale a6841 mos bipolar ground strobe output enable (active low) serial data out clock serial data in serial-parallel shift register latches v dd logic supply out 1 out 2 out 3 out 6 out 7 out 8 out 4 out 5 vee or power ground vee or power ground sub k 18-pin dip (package a) 20-pin soicw (package lw) (drop-in replacement for discon- tinued 18-pin soic variants)
dabic-5 8-bit serial input latched sink drivers a6841 2 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com absolute maximum ratings* characteristic symbol notes rating units logic supply voltage v dd 7v emitter supply voltage v ee ?20 v input voltage range v in ?0.3 to v dd +0.3 v output voltage v ce 50 v v ce(sus) for inductive load applications 35 v continuous output current i out each output 500 ma operating ambient temperature t a range e ?40 to 85 oc range s ?20 to 85 oc maximum junction temperature t j (max) 150 oc storage temperature t stg ?55 to 150 oc caution: cmos devices have input-static protection, but are susceptible to damage when exposed to extremely high static-electri cal charges. selection guide part number package packing ambient A6841EA-T* 18-pin dip 21 pieces per tube ?40oc to 85oc a6841elwtr-20-t* 20-pin wide body soic 1000 pieces per reel a6841sa-t 18-pin dip 21 pieces per tube ?20oc to 85oc a6841slwtr-20-t 20-pin wide body soic 1000 pieces per reel *variant is in production but has been determined to be last time buy. this classification indicates that the variant is obsole te and notice has been given. sale of the variant is currently restricted to existing customer applications. the variant should not be purchased for n ew design applications because of obsolescence in the near future. samples are no longer available. status date change november 2, 2009. deadline for receipt of last time buy orders is april 30, 2010. allowable package power dissipation, p d 50 75 100 125 150 2.5 0.5 0 power dissipation (w) ambient temperature (o c) 2.0 1.5 1.0 25 20-pin soic, r q ja = 90 o c/w 18-pin dip, r q ja = 65 o c/w
dabic-5 8-bit serial input latched sink drivers a6841 3 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com electrical characteristics 1 unless otherwise noted: t a = 25c, v ee = 0 v, logic supply operating voltage v dd = 3.0 to 5.5 v characteristic symbol test conditions v dd = 3.3 v v dd = 5 v units min. typ. max. min. typ. max. output leakage current i cex v out = 50 v ? ? 10 ? ? 10 a output sustaining voltage v ce(sus) i out = 350 ma, l = 3 mh 35 ? ? 35 ? ? v collector?emitter saturation voltage v ce(sat) i out = 100 ma ? ? 1.1 ? ? 1.1 v i out = 200 ma ? ? 1.3 ? ? 1.3 v i out = 350 ma ? ? 1.6 ? ? 1.6 v input voltage v in(1) 2.2 ? ? 3.3 ? ? v v in(0) ? ? 1.1 ? ? 1.7 v input resistance r in 50 ? ? 50 ? ? k serial data output voltage v out(1) i out = ?200 a 2.8 3.05 ? 4.5 4.75 ? v v out(0) i out = 200 a ? 0.15 0.3 ? 0.15 0.3 v maximum clock frequency 2 f c 10 ? ? 10 ? ? mhz logic supply current i dd(1) one output on, oe = l, st = h ? ? 2.0 ? ? 2.0 ma i dd(0) all outputs off, oe = h, st = h, p1 through p8 = l ? ? 100 ? ? 100 a clamp diode leakage current i r v r = 50 v ? ? 50 ? ? 50 a clamp diode forward voltage v f i f = 350 ma ? ? 2 ? ? 2 v output enable-to-output delay t dis(bq) v cc = 50 v, r1 = 500 , c1 30 pf ? ? 1.0 ? ? 1.0 s t en(bq) v cc = 50 v, r1 = 500 , c1 30 pf ? ? 1.0 ? ? 1.0 s strobe-to-output delay t p(sth-ql) v cc = 50 v, r1 = 500 , c1 30 pf ? ? 1.0 ? ? 1.0 s t p(sth-qh) v cc = 50 v, r1 = 500 , c1 30 pf ? ? 1.0 ? ? 1.0 s output fall time t f v cc = 50 v, r1 = 500 , c1 30 pf ? ? 1.0 ? ? 1.0 s output rise time t r v cc = 50 v, r1 = 500 , c1 30 pf ? ? 1.0 ? ? 1.0 s clock-to-serial data out delay t p(ch-sqx) i out = 200 a ? 50 ? ? 50 ? ns 1 positive (negative) current is de ned as conventional current going into (coming out of) the speci ed device pin. 2 operation at a clock frequency greater than the speci ed minimum value is possible but not warranteed. serial shift register contents serial latch contents output output contents data clock data strobe enable input input i 1 i 2 i 3 ... i 8 output input i 1 i 2 i 3 ... i 8 input i 1 i 2 i 3 ... i 8 r 7 r 7 r 1 r 2 r 3 ... r 8 r 8 xxx...x x x l r 1 r 2 ... r 7 l l r 1 r 2 r 3 ... r 8 p 1 p 2 p 3 ... p 8 p 8 p 1 p 2 p 3 ... p 81 p 2 p 3 ... p 8 xxx...x l p h h h h h r 1 r 2 ... r 7 h h h ... truth table l = low logic level h = high logic level x = irrelevant p = present state r = previous state
dabic-5 8-bit serial input latched sink drivers a6841 4 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com timing requirements and speci cations (logic levels are v dd and ground) clock serial data in strobe output enable out n 50% serial data out data data 10% 90% 50% 50% 50% c a b d e low = all outp uts e nable d p(sth-ql) t p(ch-sqx) t data p(sth-qh) t output enable out n data 10% 50% dis(bq) t en(bq) t high = all outp uts blanke d (dis able d) r t f t 50% 90% note: timing is representative of a 10 mhz clock. higher speeds may be attainable; operation at high temperatures will reduce the speci ed maxi- mum clock frequency. powering-on with the inputs in the low state ensures that the registers and latches power-on in the low state (por). s erial data present at the input is transferred to the shift register on the logical 0 to logical 1 transition of the clock input pulse. on succeeding clock pulses, the registers shift data information towards the serial data out- put. the serial data must appear at the input prior to the rising edge of the clock input waveform. information present at any register is transferred to the respective latch when the strobe is high (serial-to-parallel conversion). the latches will continue to accept new data as long as the strobe is held high. applica- tions where the latches are bypassed (strobe tied high) will require that the output enable input be high during serial data entry. when the output enable input is high, all of the output buffers are disabled (off). the information stored in the latches or shift register is not affected by the output enable input. with the output enable input low, the outputs are controlled by the state of their respective latches. key description symbol time (ns) a data active time before clock pulse (data set-up time) t su(d) 25 b data active time after clock pulse (data hold time) t h(d) 25 c clock pulse width t w(ch) 50 d time between clock activation and strobe t su(c) 100 e strobe pulse width t w(sth) 50
dabic-5 8-bit serial input latched sink drivers a6841 5 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com terminal list table name description number package a package lw vee power ground to substrate 1, 9 1, 9 clock clock 2 2 serial data in serial data in 3 3 ground logic ground 4 4 vdd logic supply 5 5 serial data out serial data out, for cascading devices 6 6 strobe strobe 7 7 output enable output enable (active low) 8 8 k common to +v l , for inductive loads 10 12 nc not internally connected ? 10, 11 out8 sink output 8 11 13 out7 sink output 7 12 14 out6 sink output 6 13 15 out5 sink output 5 14 16 out4 sink output 4 15 17 out3 sink output 3 16 18 out2 sink output 2 17 19 out1 sink output 1 18 20 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 out1 out2 out3 out4 out5 out6 out7 out8 k vee clock serial data in ground logic supply serial data out strobe output enable vee out1 out2 out3 out4 out5 out6 out7 out8 k nc vee clock serial data in ground logic supply serial data out strobe output enable vee nc package a package lw pin-out diagrams (nc pins, 10 and 11, not present on discontinued 18-pin lw package)
dabic-5 8-bit serial input latched sink drivers a6841 6 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com typical input circuits typical output driver clock serial data in v dd strobe output enable v dd out sub k v ee sub 2 3 4 5 6 7 8 serial data out serial data in output enable strobe clock +5 v C15 v +30 v clk v dd st oe 1 shift register latches 14 15 16 17 18 19 20 9 sub 12 10 11 13 sub 2 3 4 5 6 7 8 serial data out serial data in output enable strobe clock +5 v C15 v +30 v clk v dd st oe 1 shift register latches 12 13 14 15 16 17 18 9 sub 10 11 typical application relay/solenoid driver using split supply pins 10 and 11 can oat; other pins match discontinued 18-pin soic: 1 to 9 same, pins 12 to 20 match pins 10 to 18 18-pin dip (a package) 20-pin soicw (lw package)
dabic-5 8-bit serial input latched sink drivers a6841 7 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com package lw, 20-pin soicw package a, 18-pin dip 5.33 max 0.46 0.12 22.86 0.51 6.35 +0.76 ?0.25 3.30 +0.51 ?0.38 10.92 +0.38 ?0.25 1.52 +0.25 ?0.38 7.62 2.54 0.25 +0.10 ?0.05 c seating plane 2 1 18 a dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown a terminal #1 mark area all dimensions nominal, not for tooling use (reference jedec ms-001 ac) dimensions in inches 2 1 20 2 1 20 a 2.65 max c seating plane c 0.10 20x a terminal #1 mark area gauge plane seating plane b 2.25 0.65 9.50 1.27 pcb layout reference view for reference only dimensions in millimeters (reference jedec ms-013 ac) dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown b reference pad layout (reference ipc soic127p1030x265-20m) all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances 1.27 0.25 0.20 0.10 0.41 0.10 12.800.20 10.300.33 7.500.10 4 4 0.27 +0.07 ?0.06 0.84 +0.44 ?0.43
dabic-5 8-bit serial input latched sink drivers a6841 8 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com copyright ?2004-2009 allegro microsystems, inc. the products described here are manufactured under one or more u.s. patents or u.s. patents pending. allegro microsystems, inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per- mit improvements in the per for mance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro?s products are not to be used in life support devices or systems, if a failure of an allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. the in for ma tion in clud ed herein is believed to be ac cu rate and reliable. how ev er, allegro microsystems, inc. assumes no re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. for the latest version of this document, visit our website: www.allegromicro.com
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