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1 www.semtech.com sc470 synchronous buck controller for dynamic load-voltage applications power management september 27, 2005 description features applications the sc470 is a single output, constant on-time synchronous-buck, pseudo-fixed frequency, pwm controller intended for use in notebook computers and other battery operated portable devices. features include high efficiency and fast dynamic response with no minimum on-time. the excellent transient response means that sc470 based solutions will require less output capacitance than competing fixed frequency converters. the sc470 is specifically targeted for graphics processor power supplies that require dynamic voltage transition, with a tight 0.85% dc accuracy and a 20% ovp threshold. the frequency is constant until a step-in load or line voltage occurs, at which time the pulse density and frequency will increase or decrease to counter the change in output or input voltage. after the transient event, the controller frequency will return to steady state operation. at light loads, power-save mode enables the sc470 to skip pwm pulses for better efficiency. the output voltage can be adjusted from 0.5v to vcca. the integrated gate drivers feature adaptive shoot- through protection and soft switching. additional features include cycle-by-cycle current limit, digital soft-start, over- voltage and under-voltage protection, and a pgd output. ? graphics cards ? embedded graphics processors ? high performance processors ? constant on-time for fast dynamic response ? programmable vout range = 0.5 ? vcca ? vbat range = 1.8v ? 25v ? dc current sense using low-side rds(on) sensing or rsense in source of low-side mosfet for greater accuracy ? resistor programmable on-time ? cycle-by-cycle current limit ? digital soft-start ? combined en and psave functions ? over-voltage/under-voltage fault protection and pgd output ? 20% ovp threshold for simpler dynamic voltage transition circuitry ? 5a typical shutdown current ? low quiescent power dissipation ? 14 lead tssop and 16 pin mlpq (4mm x 4mm) packages ? industrial temperature range ? 0.85% dc accuracy ? integrated gate drivers with soft-switching typical application circuit 5vsus 5vsus vbat r2 r1 rton pgood r3 c4 1uf vout r4 l1 r2 c2 10uf u1 sc470 en/psv ton vout vcca fb pgd vssa pgnd dl vddp ilim lx dh bst c6 1uf vout d1 r1 10r vbat + c3 q2 c1 0.1uf q1 c5 1nf not recommended for new design not recommended for new design
2 ? 2005 semtech corp. www.semtech.com sc470 power management absolute maximum ratings (1) electrical characteristics test conditions: v bat = 15v, en/psv = 5v, vcca = vddp = 5.0v, v out = 1.25v, r ton = 1m ? , 0.1% resistor dividers. retemara ps noitidno cc 5 2c 521otc04 -s tinu ni mp y tx a mn i mx am seilppustupni egatlovtupniaccv 0. 55 . 45 . 5v egatlovtupnipddv 0. 55 . 45 . 5v egatlovtupnini vs n008>emitffo,v52-v8.1=ni v8 . 15 2v tnerrucgnitarepopdd vi ,tniopnoitaluger>bf daol a0 =0 70 5 1a tnerrucgnitarepoacc vi ,tniopnoitaluger>bf daol a0 =0 0 70 01 1a tnerrucgnitarepono tr not m1= ? 5 1a tnerrucnwodtuh sv 0=vsp/n e5 -0 1 -a acc v50 1a niv+pdd v01 a noitanibmocni pl obmy sm umixa ms tinu assvotnot 0.52+ot3.0 -v dngpottsb,hd 0.03+ot3.0 -v dngpotxl 0.52+ot0.2 -v assvotdngp 3.0+ot3.0 -v xlottsb 0.6+ot3.0 -v dngpotpddv,mili,ld 0.6+ot3.0 -v ,vsp/n ea ssvottuov,accv,dgp,bf 0.6+ot3.0 -v tuov,dgp,bf,vsp/neotaccv 0.6+ot3.0 -v trtsti-tneibmaotnoitcnuj,ecnatsiserlamreht )2( aj 00 1w /c trtlmi-tneibmaotnoitcnuj,ecnatsiserlamreht )2( aj 1 3w /c egnarerutarepmetnoitcnujgnitarep ot j 521+ot04 -c egnarerutarepmetegarot st gts 051+ot56 -c trtsti.ontrap-s01)gniredlos(erutarepmetdae lt dael 00 3c trtlmi.ontrap-s03ots01)gniredlos(wolferr it dael 06 2c exceeding the specifications below may result in permanent damage to the device or device malfunction. operation outside of the parameters specified in the electrical characteristics section is not implied. exposure to absolute maximum rated conditions for extended periods of time may affect device reliability. notes: 1) this device is esd sensitive. use of standard esd handling precautions is required. 2) calculated from package in still air, mounted to 3? to 4.5?, 4 layer fr4 pcb with thermal vias under the exposed pad per jes d51 standards. not recommended for new design not recommended for new design
3 ? 2005 semtech corp. www.semtech.com sc470 power management electrical characteristics (cont.) retemara ps noitidno c5 2c 0 4 - 5 21ot cc s tinu ni mp y tx a mn i mx am rellortnoc dlohserhtrotarapmocrorre dlohserhtno-nrutkbf( )2( ,v5.5otv5.4=accv c0 t a c58 005. 0% 58.0 -% 58.0+ v ,v5.5otv5.4=accv c04- t a c58 %1 -% 1+ egnaregatlovtuptu oe domtsujd a5 . 0a cc vv v,emit-no tab v5.2 =r not m1= ? 167 17 94 15 20 2s n r not k005= ? 63 96 9 76 70 1s n emitffomuminim 00 40 0 5s n ecnatsisertupnituov 00 5k ? tnerrucsaibtupnibf 0.1 -0 .1 +a gnisnestnerruc-revo tnerrucknismil ih gihl d0 10 . 90 .1 1a tesfforotarapmoctnerru cm ili-dng p0 1 -0 1v m evasp dlohserhtgnissorc-ore zv 5=vsp/ne,xl-dng p5v m noitcetorptluaf )evitisop(timiltnerruc )3( r,xl-dngp mili k5= ? 0 55 35 6v m r,xl-dngp mili k01= ? 00 10 80 2 1v m r,xl-dngp mili k02= ? 00 20 7 10 3 2v m )evitagen(timiltnerru cx l-dng p5 21 -0 61 -0 9 -v m tluafegatlov-rednutuptu ol anretniottcepserhtiw .ecnerefer 03 -0 4 -5 2 -% tluafegatlov-revotuptu ol anretniottcepserhtiw .ecnerefer 02 +6 1 +4 2 +% yaledtluafegatlov-rev oh tvvoevobadecrofb f0 . 5s egatlovtuptuowoldg pa m1kni s4 . 0v tnerrucegakaeldg pv 5=dgp,noitalugernibf 1a dlohserhtvudg pl anretniottcepserhtiw .ecnerefer 01 -2 1 -8 -% not recommended for new design not recommended for new design
4 ? 2005 semtech corp. www.semtech.com sc470 power management notes: (1) calculated from package in still air, mounted to 3? x 4.5?, 4 layer fr4 pcb with thermal vias under the exposed pad per jes d51 standards. (2) when the inductor is in continuous and discontinuous conduction mode, the output voltage will have a dc regulation level higher than the error-comparator threshold by 50% of the ripple voltage. this voltage will vary slightly with load and vbat. (3) using a current sense resistor, this measurement relates to pgnd minus the voltage of the source on the low-side mosfet. th ese values guaranteed by the ilim source current and current comparator offset tests. (4) clks = switching cycles. electrical characteristics (cont.) retemara ps noitidno cc 5 2c 521otc04 -s tinu ni mp y tx a mn i mx am ).tnoc(noitcetorptluaf yaledtluafdg p. wodniwdgpedistuodecrofb f0 . 5s egatlovrednuaccv dlohserht )siseretsyhvm001(gnilla f0 . 47 . 33 . 4v tuokcolerutarepmetrev o0 1 o siseretsyh c5 6 1c stuptuo/stupni egatlovwoltupnicigo lw olvsp/n e2 . 1v egatlovhgihtupnicigo lw olvsp,hgihne )gnitaolfnip( 0. 2v egatlovhgihtupnicigo lh gihvsp/n e1 . 3v tupnievasrewop/elbane ecnatsiser accvotpullup r5 . 1m ? ? tratstfos emitpmartrats-tfo sh gihdgpothgihvsp/n e0 4 4s klc )4( emitknalbegatlov-redn uh gihvuothgihvsp/n e0 4 4s klc )4( srevirdetag emitdae dg nisirldroh d0 3s n ecnatsisernwod-llupl dw oll d8 . 06 .1 ? = ? = = ? = ? = not recommended for new design not recommended for new design
5 ? 2005 semtech corp. www.semtech.com sc470 power management pin configuration ordering information top view 1 2 3 4 12 11 10 9 16 15 14 13 5678 mlpq16: 4x4 body t ton en/psv nc bst dh lx ilim vddp vout vcca fb pgd nc vssa pgnd dl ecived )1( egakcap trtlmi074cs )3()2( 61-qplm trtsti074cs )3()2( 41-posst bve074cs )4( draobnoitaulave notes: (1) only available in tape and reel packaging. a reel contains 2500 devices. (2) this product is fully weee and rohs compliant. (3) lead-free product. this product is j-std-020b compliant and all homogeneous subcomponents are rohs compliant. (4) part-specific evaluation boards - consult factory for availability. 1 2 3 4 5 6 7 bst en/psv top view (14 pin tssop) 13 12 14 11 10 dh ton lx vout ilim vcca vddp fb dl pgd pgnd vssa 9 8 not recommended for new design not recommended for new design
6 ? 2005 semtech corp. www.semtech.com sc470 power management emanni p# 61-qpl m# 41-poss tn oitcnufnip tuo v13 . daolehttatuovottcennoc.tupniesnesegatlovtuptuo acc v24 retlifcrf1/mho01aesu.ylppusgolanaehtroftupniegatlovylppus .assvotsusv5morf b f35 tesotassvottuovmorfredividrotsiseraottcennoc.tupnikcabdeef .accvdnav5.0neewtebegatlovtuptuoeht dg p46 elcyckcolcdexifaretfahgihseog.tuptuosomnniardnepodoogrewop .pu-rewopgniwollof)selcyc044(yaled c n5- . tcennocon ass v67 tuptuoehtfomottobehtottcennoc.yrtiucricgolanarofecnereferdnuorg .roticapac dng p78 . dnuorgrewop l d89 . hctiwstefsomediswolehtroftuptuoevirdetag pdd v90 1 f1ahtiwnipsihtelpuoced.srevirdetagehtroftupniegatlovylppusv5+ .dngpotroticapaccimarec mil i0 11 1 )no(sdrroftefsomedis-wolfoniardottcennoc.tupnitimiltnerruc gnisnesdlohserhtahguorhtgnisnesrofrotsiserecruosehtro,gnisnes .rotsiser x l1 12 1 )rotcudnituptuoehtdnastefsommottobdnapotfonoitcnuj(edonesahp .noitcennoc h d2 13 1. hctiwstefsomedishgihehtroftuptuoevirdetag ts b3 14 1. evirdetagedishgihehtrofnoitcennocroticapactsoob c n4 1- . tcennocon vsp/n e5 11 pu-llup.ciehtnwodtuhsotassvotnwodllup.tupnievasrewop/elbane dnaciehtelbaneottaolf.edomevaspetavitcadnaciehtelbaneot assvotssapyb,detaolffi.)mcc(edomnoitcudnocsuonitnocetavitca .roticapaccimarecfn01ahtiw no t6 12 otdna,notr,rotsiserpullupahguorhttabvesnesotdesusinipsiht roticapaccimarecfn1ahtiwnipsihtssapyb.emit-notefsompotehttes .assvot lamreht dap t- elpitlumgnisuenalpdnuorgottcennoc.sesoprupgniknistaehrofdap .yllanretnidetcennocton.saiv pin descriptions not recommended for new design not recommended for new design
7 ? 2005 semtech corp. www.semtech.com sc470 power management block diagram + - ref + 20% vssa x3 ov dl pgd dh control zero i uv toff vddp por / ss bst vout hi en/spv lx ilim vcca monitor 1.5v ref ref - 30% fault on fb logic ot ton isense pwm ton off pgnd ref - 10% lo oc figure 1: sc470 block diagram not recommended for new design not recommended for new design
8 ? 2005 semtech corp. www.semtech.com sc470 power management +5v bias supplies the sc470 requires an external +5v bias supply in addition to the battery. if stand-alone capability is required, the +5v supply can be generated with an external linear regulator such as the semtech lp2951. for optimal operation, the controller has its own ground reference, vssa, which should be tied by a single trace to pgnd at the negative terminal of the output capacitor (see layout guidelines). all external compo- nents referenced to vssa in the typical applications cir- cuit on page 1 should be connected to vssa. the supply decoupling capacitor should be tied directly between the vcca and vssa pins. a 10? resistor should be used to decouple vcca from the main vddp supply. pgnd can then be a separate plane which is not used for routing traces. all pgnd connections are connected directly to the ground plane with special attention given to avoiding indirect connections which may create ground loops. as mentioned above, vssa must be connected to the pgnd plane at the negative terminal of the output capacitor only. the vddp input provides power to the upper and lower gate drivers. a decoupling capacitor is required. no series resistor between vddp and 5v is required. see layout guidelines for more details. pseudo-fixed frequency constant on-time pwm controller the pwm control architecture consists of a constant on- time, pseudo-fixed frequency pwm controller (see figure 1, block diagram, page 7). the output ripple voltage developed across the output filter capacitor?s esr provides the pwm ramp signal eliminating the need for a current sense resistor. the high-side switch on-time is determined by a one-shot whose period is directly proportional to output voltage and inversely proportional to input voltage. a second one-shot sets the minimum off-time which is typically 400ns. on-time one-shot (t on ) the on-time one-shot comparator has two inputs. one input looks at the output voltage, while the other input samples the input voltage and converts it to a current. this input voltage-proportional current is used to charge an internal on-time capacitor. the on-time is the time required for the voltage on this capacitor to charge from zero volts to vout, thereby making the on-time of the high-side switch directly proportional to output voltage and inversely proportional to input voltage. this implementation results in a nearly constant switching frequency without the need for a clock generator. for vout < 3.3v: ns50 v v )10x37r(10x3.3t bat out 3 ton 12 on + ? ? ? ? ? ? ? ? ?+? = ? for 3.3v vout 5v: ns50 v v )10x37r(10x3.385.0t bat out 3 ton 12 on + ? ? ? ? ? ? ? ? ?+? ?= ? r ton is a resistor connected from the input supply (vbat) to the ton pin. due to the high impedance of this resistor, the ton pin should always be bypassed to vssa using a 1nf ceramic capacitor. enable & psave the en/psv pin enables the supply. when en/psv is tied to vcca the controller is enabled and power save will also be enabled. when the en/psv pin is tri-stated, an internal pull-up will activate the controller and power save will be disabled. if psave is enabled, the sc470 psave comparator will look for the inductor current to cross zero on eight consecutive switching cycles by comparing the phase node (lx) to pgnd. once observed, the controller will enter power save and turn off the low side mosfet when the current crosses zero. to improve light-load efficiency and add hysteresis, the on-time is increased by 50% in power save. the efficiency improvement at light-loads more than offsets the disadvantage of slightly higher output ripple. if the inductor current does not cross zero on any switching cycle, the controller will immediately exit power save. since the controller counts zero crossings, the converter can sink current as long as the current does not cross zero on eight consecutive cycles. this allows the output voltage to recover quickly in response to negative load steps even when psave is enabled. application information not recommended for new design not recommended for new design
9 ? 2005 semtech corp. www.semtech.com sc470 power management application information (cont.) output voltage selection the output voltage is set by the feedback resistors r3 & r7 of figure 2 below. the internal reference is 1.5v, so the voltage at the feedback pin is multiplied by three to match the 1.5v reference. therefore, the output can be set to a minimum of 0.5v. the equation for setting the output voltage is: figure 2: setting the output voltage current limit circuit current limiting of the sc470 can be accomplished in two ways. the on-state resistance of the low-side mosfet can be used as the current sensing element or sense resistors in series with the low-side source can be used if greater accuracy is desired. r ds(on) sensing is more efficient and less expensive. in both cases, the r ilim resistor between the ilim pin and lx pin set the over current threshold. this resistor r ilim is connected to a 10 a current source within the sc470 which is turned on when the low side mosfet turns on. when the voltage drop across the sense resistor or low side mosfet equals the voltage across the rilim resistor, positive current limit will activate. the high-side mosfet will not be turned on until the voltage drop across the sense element (resistor or mosfet) falls below the voltage across the r ilim resistor. in an extreme over- current situation, the top mosfet will never turn back on and eventually the part will latch off due to output undervoltage (see output under-voltage protection). the current sensing circuit actually regulates the inductor valley current (see figure 3). this means that if the current limit is set to 10a, the peak current through the inductor would be 10a plus the peak ripple current, and the average current through the inductor would be 10a plus 1/2 the peak-to-peak ripple current. the equations for setting the valley current and calculating the average current through the inductor are shown below: i limit i load i peak inductor curren t time valley current-limit threshold point figure 3: valley current limiting the equation for the current limit threshold is as follows: a r r 10ei sense ilim 6- limit ?= where (referring to figure 8 on page 17) r ilim is r4 and r sense is the r ds(on) of q2. for resistor sensing, a sense resistor is placed between the source of q2 and pgnd. the current through the source sense resistor develops a voltage that opposes the voltage developed across r ilim . when the voltage developed across the r sense resistor reaches the voltage r3 20k0 r7 20k0 en/psv ton vout vcca fb pgd vssa pgnd dl vddp ilim lx dh bst u1 sc470 vout 0402 0402 c5 56p 0402 5.0 7r 3r 1 v out ? ? ? ? ? ? ? += not recommended for new design not recommended for new design
10 ? 2005 semtech corp. www.semtech.com sc470 power management drop across r ilim , a positive over-current exists and the high side mosfet will not be allowed to turn on. when using an external sense resistor r sense is the resistance of the sense resistor. the current limit circuitry also protects against negative over-current (i.e., when the current is flowing from the load to pgnd through the inductor and bottom mosfet). in this case, when the bottom mosfet is turned on, the phase node, lx, will be higher than pgnd initially. the sc470 monitors the voltage at lx, and if it is greater than a set threshold voltage of 140mv (nom.) the bottom mosfet is turned off. the device then waits for approximately 2.5s and then dl goes high for 300ns (typ.) once more to sense the current. this repeats until either the over-current condition goes away or the part latches off due to output over-voltage (see output over-voltage protection). power good output the power good output is an open-drain output and requires a pull-up resistor. when the output voltage is 20% above or 10% below its set voltage, pgd gets pulled low. it is held low until the output voltage returns to within + 20%/-10% of the output set voltage. pgd is also held low during start-up and will not be allowed to transition high until soft-start is over (440 switching cycles) and the output reaches 90% of its set voltage. there is a 5s delay built into the pgd circuitry to prevent false transitions. output over-voltage protection when the output exceeds 20% of the its set voltage the low-side mosfet is latched on. it stays latched on and the controller is latched off until reset. there is a 5s delay built into the ov protection circuit to prevent false transitions. output under-voltage protection when the output is 30% below its set voltage the output is latched in a tri-stated condition. it stays latched and the controller is latched off until reset. there is a 5s delay built into the uv protection circuit to prevent false transitions. note: to reset from any fault, vcca or en/psv must be toggled. application information (cont.) por, uvlo and softstart an internal power-on reset (por) occurs when vcca ex- ceeds 3v, resetting the fault latch and soft-start counter, and preparing the pwm for switching. vcca under-volt- age lockout (uvlo) circuitry inhibits switching and forces the dl gate driver high until vcca rises above 4.2v. at this time the circuit will come out of uvlo and begin switching, and with the soft-start circuit enabled, will pro- gressively limit the output current (by limiting the current out of the ilim pin) over a predetermined time period of 440 switching cycles. the ramp occurs in four steps: 1) 110 cycles at 25% ilim with double minimum off-time (for purposes of the on-time one-shot there is an internal positive offset of 120mv to vout during this period to aid in start-up). 2) 110 cycles at 50% ilim with normal minimum off-time. 3) 110 cycles at 75% ilim with normal minimum off-time. 4) 110 cycles at 100% ilim with normal minimum off-time. at this point the output under-voltage and power good circuitry is enabled. there is 100mv of hysteresis built into the uvlo circuit and when vcca falls to 4.1v (nom.) the output drivers are shut down and tristated. mosfet gate drivers the dh and dl drivers are optimized for driving moderate-sized high-side, and larger low-side power mosfets. an adaptive dead-time circuit monitors the dl output and prevents the high-side mosfet from turning on until dl is fully off (below ~1v). conversely, it monitors the phase node, lx, to determine the state of the high side mosfet, and prevents the low-side mosfet from turning on until dh is fully off (lx below ~1v). note: be sure there is low resistance and low inductance be- tween the dh and dl outputs to the gate of each mosfet. dropout performance the output voltage adjust range for continuous- conduction operation is limited by the fixed 550ns not recommended for new design not recommended for new design
11 ? 2005 semtech corp. www.semtech.com sc470 power management (maximum) minimum off-time one-shot. for best dropout performance, use the slowest on-time setting of 200khz. when working with low input voltages, the duty-factor limit must be calculated using worst-case values for on and off times. the ic duty-factor limitation is given by: ) max ( off t )min(on t )min(on t duty + = be sure to include inductor resistance and mosfet on- state voltage drops when performing worst-case dropout duty-factor calculations. 470 system dc accuracy two ic parameters affect system dc accuracy, the error comparator threshold voltage variation and the switching frequency variation with line and load. the error comparator threshold does not drift significantly with supply and temperature. thus, the error comparator contributes 0.85% or less to dc system inaccuracy. board components and layout also influence dc accuracy. the use of 1% feedback resistors contribute 1%. if tighter dc accuracy is required use 0.1% feedback resistors. the on-pulse in the sc470 is calculated to give a pseudo- fixed frequency. nevertheless, some frequency variation with line and load can be expected. this variation changes the output ripple voltage. because constant on- regulators regulate to the valley of the output ripple, ? of the output ripple appears as a dc regulation error. for example, if the feedback resistors are chosen to divide down the output by a factor of five, the valley of the output ripple will be vout. for example: if vout is 2.5v and the ripple is 50mv with vbat = 6v, then the measured dc output will be 2.525v. if the ripple increases to 80mv with vbat = 25v, then the measured dc output will be 2.540v. the output inductor value may change with current. this will change the output ripple and thus the dc output voltage. it will not change the frequency. switching frequency variation with load can be minimized by choosing mosfets with lower r ds(on) . high r ds(on) mosfets will cause the switching frequency to increase as the load current increases. this will reduce the ripple and thus the dc output voltage. design procedure prior to designing an output and making component selections, it is necessary to determine the input voltage range and the output voltage specifications. for purposes of demonstrating the procedure the output for the schematic in figure 8 on page 17 will be designed. the maximum input voltage (v bat(max) ) is determined by the highest ac adaptor voltage. the minimum input voltage (v bat(min) ) is determined by the lowest battery voltage after accounting for voltage drops due to connectors, fuses and battery selector switches. for the purposes of this design we will use a v bat range of 8v to 20v. four parameters are needed for the output: 1) nominal output voltage, v out (we will use 1.2v). 2) static (or dc) tolerance, tol st (we will use +/-4%). 3) transient tolerance, tol tr and size of transient (we will use +/-8% for purposes of this demonstration). 4) maximum output current, i out (we will design for 6a). switching frequency determines the trade-off between size and efficiency. increased frequency increases the switching losses in the mosfets, since losses are a function of vin 2 , knowing the maximum input voltage and budget for mosfet switches usually dictates where the design ends up. a default r ton value of 1m ? is suggested as a starting point, but this is not set in stone. the first thing to do is to calculate the on-time, t on , at v bat(min) and v bat(max) , since this depends only upon v bat , v out and r ton . for v out < 3.3v: () s1050 v v 1037r103.3 t 9 )min(bat out 3 ton 12 )min(vbat_on ? ? ?+ ? ? ? ? ? ? ? ? ??+??= and, () s1050 v v 1037r103.3 t 9 ) max (bat out 3 ton 12 ) max (vbat_on ? ? ?+ ? ? ? ? ? ? ? ? ??+??= from these values of t on we can calculate the nominal switching frequency as follows: application information (cont.) not recommended for new design not recommended for new design
12 ? 2005 semtech corp. www.semtech.com sc470 power management application information (cont.) () hz tv v f )min(vbat_on)min(bat out )min(vbat_ sw ? = and, () hz tv v f ) max (vbat_on) max (bat out ) max (vbat_ sw ? = t on is generated by a one-shot comparator that samples v bat via r ton , converting this to a current. this current is used to charge an internal 3.3pf capacitor to v out . the equations on page 11 reflect this along with any internal components or delays that influence t on . for our example we select r ton = 1m ? : t on_vbat(min) = 563ns and t on_vbat(max) = 255ns f sw_vbat(min) = 266khz and f sw_vbat(max) = 235khz now that we know t on we can calculate suitable values for the inductor. to do this we select an acceptable inductor ripple current. the calculations below assume 50% of i out which will give us a starting place. () () h i5.0 t vv l out )min(vbat_on out )min(bat )min(vbat ? ?? = and, () () h i5.0 t v v l out ) max (vbat_on out ) max (bat ) max (vbat ? ?? = for our example: l vbat(min) = 1.3h and l vbat(max) = 1.6h we will select an inductor value of 2.2h to reduce the ripple current, which can be calculated as follows: () pp )min(vbat_on out )min(bat )min(vbat_ripple a l t vv i ? ?? = and, () pp ) max (vbat_on out ) max (bat ) max (vbat_ripple a l t v v i ? ?? = for our example: i ripple_vbat(min) = 1.74a p-p and i ripple_vbat(max) = 2.18a p-p from this we can calculate the minimum inductor current rating for normal operation: )min( ) max (vbat_ripple ) max (out)min( inductor a 2 i i i += for our example: i inductor(min) = 7.1a (min) next we will calculate the maximum output capacitor equivalent series resistance (esr). this is determined by calculating the remaining static and transient tolerance allowances. then the maximum esr is the smaller of the calculated static esr (r esr_st(max) ) and transient esr (r esr_tr(max) ): () ohms i 2 err err r ) max (vbat_ripple dc st ) max (st_esr ?? = where err st is the static output tolerance and err dc is the dc error. the dc error will be 0.85% plus the tolerance of the feedback resistors, thus 1.85% total for 1% feedback resistors. for our example: err st = 48mv and err dc = 22mv, therefore, r esr_st(max) = 24m ? () ohms 2 i i err err r ) max (vbat_ripple out dc tr ) max (tr_esr ? ? ? ? ? ? ? ? + ? = where err tr is the transient output tolerance. note that this calculation assumes that the worst case load transient is full load. for half of full load, divide the i out term by 2. for our example: err tr = 96mv and err dc = 22mv, therefore, not recommended for new design not recommended for new design
13 ? 2005 semtech corp. www.semtech.com sc470 power management application information (cont.) r esr_tr(max) = 10.4m ? for a full 6a load transient wewill select a value of 12.5m ? maximum for our design, which would be achieved by using two 25m ? output capacitors in parallel. note that for constant-on converters there is a mini- mum esr requirement for stability which can be calculated as follows: sw out )min(esr fc2 3 r ??? = this criteria should be checked once the output capacitance has been determined. now that we know the output esr we can calculate the output ripple voltage: pp) max ( vbat _ ripple esr ) max ( vbat _ ripple v ir v ? ?= and, pp) min ( vbat _ ripple esr ) min ( vbat _ ripple v ir v ? ?= for our example: v ripple_vbat(max) = 27mv p-p and v ripple_vbat(min) = 22mv p-p note that in order for the device to regulate in a controlled manner, the ripple content at the feedback pin, v fb , should be approximately 15mv p-p at minimum v bat , and worst-case no smaller than 10mv p-p . if v ripple_vbat(min) is less than 15mv p-p the above component values should be revisited in order to improve this. quite often a small capacitor, c top , is required in parallel with the top feedback resistor, r top , in order to ensure that v fb is large enough. c top should not be greater than 100pf. the value of c top can be calculated as follows, where r bot is the bottom feedback resistor. firstly calculating the value of z top required: () ohms 015.0 v 015.0 r z )min(vbat_ripple bot top ? ?= secondly calculating the value of c top required to achieve this: for our example we will use r top = 20.0k ? and r bot = 14.3k ? , therefore: z top = 6.67k ? and c top = 60pf we will select a value of c top = 56pf. calculating the value of v fb based upon the selected c top : pp top )min( vbat _ sw top bot bot )min( vbat _ripple )min( vbat _fb v c f2 r 1 1 r r v v ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ??+ + ? = for our example: v fb_vbat(min) = 14.8mv p-p - good next we need to calculate the minimum output capacitance required to ensure that the output voltage does not exceed the transient maximum limit, poslim tr , starting from the actual static maximum, v out_st_pos , when a load release occurs: verrv v dc out pos_st_out += for our example: v out_st_pos = 1.222v vtolv poslim tr out tr ?= where tol tr is the transient tolerance. for our example: poslim tr = 1.296v the minimum output capacitance is calculated as follows: () f v poslim 2 i i l c 2 pos_st_out 2 tr 2 ) max (vbat_ripple out )min(out ? ? ? ? ? ? ? ? ? + ?= f f2 r 1 z 1 c )min(vbat_sw top top top ?? ? ? ? ? ? ? ? ? ? = not recommended for new design not recommended for new design
14 ? 2005 semtech corp. www.semtech.com sc470 power management application information (cont.) this calculation assumes the absolute worst-case condition of a full-load to no-load step transient occurring when the inductor current is at its highest. the capacitance required for smaller transient steps may be calculated by substituting the desired current for the i out term. for our example: c out(min) = 595f. we will select 440f, using two 220f, 25m ? capacitors in parallel. for smaller load release overshoot, 660f may be used. next we calculate the rms input ripple current, which is largest at the minimum battery voltage: () rms min_bat out out )min(bat out ) rms (in a v i vvvi ???= for our example: i in(rms) = 2.14a rms input capacitors should be selected with sufficient ripple current rating for this rms current, for example a 10f, 1210 size, 25v ceramic capacitor can handle a little more than 2a rms (refer to manufacturer?s data sheets). finally, we calculate the current limit resistor value. as described in the current limit section, the current limit looks at the ?valley current?, which is the average output current minus half the ripple current. we use the maximum room temperature specification for mosfet r ds(on) at v gs = 4.5v for purposes of this calculation: a 2 i ii )min(vbat_ripple out valley ?= the ripple at low battery voltage is used because we want to make sure that current limit does not occur under normal operating conditions. () ohms 1010 4.1r 2.1ir 6 )on(ds valley ilim ? ? ? ??= for our example: i valley = 5.13a, r ds(on) = 9m? and r ilim = 7.76k ? we select the next lowest 1% resistor value: 7.68k ? adding an additional output voltage for dynamic voltage switching if we design this output to be capable of dynamically switching between 1.2v and 1.0v, then we would repeat these calculations to determine if any components need changing. the 1.0v output suggests a value for c top of 82pf, but the value of 56pf required by the 1.2v design should work fine, and can always be increased if neces- sary. also, the current limit resistor required is slightly higher: r ilim = 7.87k ? . the higher value should be used. lastly, the bottom feedback resistor, r bot will need to change to 20.0k ? . the schematic in figure 8 on page 17 shows the complete design. dynamically switching output voltages it is important to note that in order for dynamic output voltage switching to work, the sc470 must be in continuous conduction mode (en/psv = floating) when transitioning from v out(high) to v out(low) . otherwise the sc470 has no means to discharge the output voltage and may ovp and latch off when this transition is initiated (depending upon the difference between the two voltages). if ccm is on, the sc470 will actively discharge the output down to the correct voltage. dynamically switching output voltages is very easy, requiring one switch to add or remove an additional resistor in parallel to the bottom feedback resistor. ideally, the resistor will be switched using an open drain output from another ic, as shown in figure 4. not recommended for new design not recommended for new design
15 ? 2005 semtech corp. www.semtech.com sc470 power management application information (cont.) figure 4: dynamic voltage switching using direct drive method (v out(high) /v out(low) < 1.16 only) another option is to switch using an external discrete mosfet, as shown in figure 5. figure 5: dynamic voltage switching using indirect drive method the problem with the external mosfet method is that the drain-gate capacitance, c dg , can cause the output voltage to go even higher when the mosfet is first turned off (which should make the output voltage drop). this is because the gate going low causes the drain to go low momentarily due to c dg , which in turn causes v fb to go low, making the output rise. the extra r9 and c11 in the gate drive for the mosfet are there to slow down the slew rate of the gate voltage, thus avoiding this problem. determining what circuit to use depends upon the ratio between v out(high) and v out(low) , since the goal is to avoid inadvertently tripping the over-voltage protection. if: 16 .1 v v ) low ( out ) high ( out < this means that the ratio is less than the worst-case ovp threshold (worst-case in this case is the lowest threshold), then the direct drive (simplest) method may be used. of course the indirect drive method may also be used if desired. if: 16 .1 v v ) low ( out ) high ( out > this means that the ratio is greater than the worst-case ovp threshold, therefore we automatically need to slew the rate of change, and the indirect drive method must be used. if using the indirect drive method, the goal is to slow down the gate drive for the transition from v out(high) to v out(low) , which is when the external mosfet is turned off. the pull-up resistor, pull-down resistor and gate capacitor can be selected as follows: 1) v gate must be below the gate threshold voltage of the mosfet in order to ensure that it can be turned off (see figure 6): 2) the rc time constant of r9 and c11 should be at least 4 times greater than the typical over-voltage fault delay time of 5s to avoid v out rising prior to falling. 3) v pullup must be high enough to turn the mosfet on. figure 6: ensuring q3 will turn off r3 20k0 r7 20k0 en/psv ton vout vcca fb pgd vssa pgnd dl vddp ilim lx dh bst u1 sc470 vout 0402 0402 0402 c5 56p r5 49k9 0402 low = 1.0v high = 1.2v open drain signal q3 r8 pull-up c11 r9 r3 20k0 r7 20k0 en/psv ton vout vcca fb pgd vssa pgnd dl vddp ilim lx dh bst u1 sc470 vout 0402 0402 c5 56p 0402 r5 49k9 0402 open drain signal low = 1.2v high = 1.0v q3 r8 pul l - up c11 r9 vgate vpullup () ) th ( gs pullup v 9r8r v9r < + ? not recommended for new design not recommended for new design
16 ? 2005 semtech corp. www.semtech.com sc470 power management application information (cont.) figure 7 below shows recommended components that work well. figure 7: recommended component values please see the example switching waveforms on pages 25 and 26. thermal considerations the junction temperature of the device may be calculated as follows: c ptt jadaj ?+= where: t a = ambient temperature (c) p d = power dissipation in (w) ja = thermal impedance junction to ambient from absolute maximum ratings (c/w) the power dissipation may be calculated as follows: wdma1vbstfqv i vddp i vcca p gg vddp vcca d ??+??+ ?+?= where: vcca = chip supply voltage (v) i vcca = operating current (a) vddp = gate drive supply voltage (v) i vddp = gate drive operating current (a) v g = gate drive voltage, typically 5v (v) q g = fet gate charge, from the fet datasheet (c) f = switching frequency (khz) vbst = boost pin voltage during t on (v) d = duty cycle inserting the following values for vbat (min) condition (since this is the worst-case condition for power dissipation in the controller) as an example (vout = 1.2v): t a = 85c ja = 100c/w (for tssop-14) ja = 46c/w (for mlpq-16) vcca = vddp = 5v i vcca = 1100a (data sheet maximum) i vddp = 150a (data sheet maximum) v g = 5v q g = 60nc f = 266khz vbat (min) = 8v vbst (min) = vbat (min) +vddp = 13v d (min) = 1.2/8 = 0.15 gives us: w088.0 15.0101131026610605 1015051011005p 3 3 9 6 6 d = ???+????+ ??+??= ? ? ? ? so for tssop-14, c8.93100088.085t j =?+= and for mlpq-16, c0.8946088.085t j =?+= as can be seen, the heating effects due to internal power dissipation are practically negligible, thus requiring no special consideration thermally during layout. q3 r8 10k c11 22n r9 1k vgate vpullup not recommended for new design not recommended for new design
17 ? 2005 semtech corp. www.semtech.com sc470 power management application information (cont.) c10 1uf r3 20k0 r7 20k0 en/psv 1 ton 2 vout 3 vcca 4 fb 5 pgd 6 vssa 7 pgnd 8 dl 9 vddp 10 ilim 11 lx 12 dh 13 bst 14 u1 sc470 vout c8 1nf r1 1m 5vsus vbat pgood q1 irf7811av q2 fds6676s c9 1uf r4 7k87 c1 0.1uf d1 sod323 c2 2n2/50v vbat 5vsus l1 2u2 + c7 220u/25m vout r2 10r 0402 0402 0402 0402 c5 56p 0402 r5 49k9 0402 vout switch (1) 0402 0603 r6 0r (2) 0402 7343 + c6 220u/25m 7343 0402 c3 0u1/25v c4 10u/25v 0603 1210 0603 0402 0603 notes (1) driv en by an open drain with no pullup. low = 1.2v out, floating = 1v out. (2) r6 is not required but aids keeping vssa separate f rom pgnd except where desired in lay out. vbat = 8v to 20v vout = 1.2v or 1.0v @ 6a figure 8: reference design for dynamic output switching one (or more) ground planes is/are recommended to minimize the effect of switching noise and copper losses, and maximize heat dissipation. the ic ground reference, vssa, should be kept separate from power ground. all components that are referenced to vssa should connected to it locally at the chip. vssa should connect to power ground at the output capacitor(s) only. the vout feedback trace must be kept far away from noise sources such as switching nodes, inductors and gate drives. route the feedback trace with vssa as a differential pair from the output capacitor back to the chip. run them in a ?quiet layer? if possible. vssa may be separated from pgnd using a zero ohm resistor (that will be placed at the bottom of the output capacitors) to aid in net separation. chip decoupling capacitors (vddp, vcca) should be located next to the pins (vddp and pgnd, vcca and vssa) and connected directly to them on the same side. power sections should connect directly to the ground plane(s) using multiple vias as required for current handling (including the chip power ground connections). power components should be placed to minimize loops and reduce losses. make all the connections on one side of the pcb using wide copper filled areas if possible. do not use ?minimum? land patterns for power components. minimize trace lengths between the gate drivers and the gates of the mosfets to reduce parasitic impedances (and mosfet switching losses), the low-side mosfet is most critical. maintain a length to width ratio of <20:1 for gate drive signals. use multiple vias as required by current handling requirement (and to reduce parasitics) if routed on more than one layer current sense connections must always be made using kelvin connections to ensure an accurate signal, with the current limit resistor located at the device. we will examine the reference design used in the design procedure section while explaining the layout guidelines in more detail. layout guidelines - tssop-14 as an example: not recommended for new design not recommended for new design
18 ? 2005 semtech corp. www.semtech.com sc470 power management the layout can be considered in two parts, the control section referenced to vssa and the power section. looking at the control section first, locate all components referenced to vssa on the schematic and place these components at the chip. connect vssa using either a wide (>0.020?) trace or a copper pour if room allows. very little current flows in the chip ground therefore large areas of copper are not needed. c10 1uf r3 20k0 r7 20k0 en/psv 1 ton 2 vout 3 vcca 4 fb 5 pgd 6 vssa 7 pgnd 8 dl 9 vddp 10 ilim 11 lx 12 dh 13 bst 14 u1 sc470 vout c8 1nf r1 1m 5vsus pgood vbat c9 1uf 5vsus r2 10r 0402 0402 0402 0402 c5 56p 0402 r5 49k9 0402 vout switch (1) 0603 0402 0603 figure 9: components connected to vssa figure 10: example vssa 0.020? traces application information (cont.) in figure 10 above, all components referenced to vssa have been placed and have been connected using 0.020? traces. decoupling capacitors c9 and c10 are as close as possible to their pins. c9 should connect to the ground plane using two vias not recommended for new design not recommended for new design
19 ? 2005 semtech corp. www.semtech.com sc470 power management as shown below, vout and vssa should be routed as a differential pair to the output capacitor(s). c11 1uf r4 20k0 r8 20k0 en/psv 1 ton 2 vout 3 vcca 4 fb 5 pgd 6 vssa 7 pgnd 8 dl 9 vddp 10 ilim 11 lx 12 dh 13 bst 14 u2 sc470 vout + c7 220u/25m vout 0402 0402 c6 56p 0402 0603 r12 0r (2) 7343 0402 + c14 220u/25m 7343 vout vout vssa figure 11: differential routing of feedback and ground reference traces next, the schematic in figure 12 below shows the power section. the highest di/dts occur in the input loop (highlighted in red) and thus this loop should be kept as small as possible. q1 irf7811av q2 fds6676s c2 2n2/50v vbat l1 2u2 + c7 220u/25m vout r6 0r (2) 7343 0402 + c6 220u/25m 7343 0402 c3 0u1/25v c4 10u/25v 1210 0603 figure 12: power section and input loop the input capacitors should be placed with the highest frequency capacitors closest to the loop to reduce emi. use large copper pours to minimize losses and parasitics. see figure 13 on page 20 for an example. application information (cont.) not recommended for new design not recommended for new design
20 ? 2005 semtech corp. www.semtech.com sc470 power management application information (cont.) figure 13: power component placement and copper pours key points for the power section: 1) there should be a very small input loop, well decoupled. 2) the phase node should be a large copper pour, but compact since this is the noisiest node. 3) input power ground and output power ground should not connect directly, but through the ground planes instead. 4) notice in figure 10 on page 18, the placement of 0 ? resistor at the bottom of the output capacitor to connect to vssa. 5) the current limit resistor should be placed as close as possible to the ilim and lx pins. connecting the control and power sections should be accomplished as follows (see figure 14 on page 21): 1) route vssa and vout as differential pairs routed in a ?quiet? layer away from noise sources. 2) route dl, dh and lx (low-side fet gate drive, high side fet gate drive and phase node) to chip using wide traces with multiple vias if using more than one layer. these connections to be as short as possible for loop minimization, with a length to width ratio less than 20:1 to minimize impedance. dl is the most critical gate drive, with power ground as its return path. lx is the noisiest node in the circuit, switching between v bat and ground at high frequencies, thus should be kept as short as practical. dh has lx as its return path. 3) bst is also a noisy node and should be kept as short as possible. 4) connect pgnd pin on the chip directly to the vddp decoupling capacitor and then drop vias directly to the ground plane. not recommended for new design not recommended for new design
21 ? 2005 semtech corp. www.semtech.com sc470 power management figure 14: connecting the control and power sections application information (cont.) en/psv 1 ton 2 vout 3 vcca 4 fb 5 pgd 6 vssa 7 pgnd 8 dl 9 vddp 10 ilim 11 lx 12 dh 13 bst 14 u1 sc470 q1 irf7811av q2 fds6676s r4 7k87 l1 2u2 0402 not recommended for new design not recommended for new design
22 ? 2005 semtech corp. www.semtech.com sc470 power management typical characteristics 1.2v efficiency (power save mode) vs. output current vs. input voltage 1.2v efficiency (continuous conduction mode) vs. output current vs. input voltage 1.2v output voltage (power save mode) vs. output current vs. input voltage 1.2v output voltage (continuous conduction mode) vs. output current vs. input voltage 1.2v switching frequency (power save mode) vs. output current vs. input voltage 1.2v switching frequency (continuous conduction mode) vs. output current vs. input voltage 50 55 60 65 70 75 80 85 90 95 100 0123456 i out (a) efficiency (%) v bat = 20v v bat = 8v 1.180 1.184 1.188 1.192 1.196 1.200 1.204 1.208 1.212 1.216 1.220 0123456 i out (a) v out (v) v bat = 20v v bat = 8v 0 50 100 150 200 250 300 350 400 0123456 i out (a) frequency (khz) v bat = 20v v bat = 8v 50 55 60 65 70 75 80 85 90 95 100 0123456 i out (a) efficiency (%) v bat = 8v v bat = 20v 1.180 1.184 1.188 1.192 1.196 1.200 1.204 1.208 1.212 1.216 1.220 0123456 i out (a) v out (v) v bat = 20v v bat = 8v 0 50 100 150 200 250 300 350 400 0123456 i out (a) frequency (khz) v bat = 20v v bat = 8v please refer to figure 8 on page 17 for test schematic not recommended for new design not recommended for new design
23 ? 2005 semtech corp. www.semtech.com sc470 power management typical characteristics (cont.) load transient response, continuous conduction mode, 0a to 6a to 0a trace 1: 1.2v, 50mv/div., ac coupled trace 2: lx, 20v/div trace 3: not connected trace 4: load current, 5a/div timebase: 40s/div. load transient response, continuous conduction mode, 0a to 6a zoomed load transient response, continuous conduction mode, 6a to 0a zoomed trace 1: 1.2v, 50mv/div., ac coupled trace 2: lx, 10v/div trace 3: not connected trace 4: load current, 5a/div timebase: 10s/div. trace 1: 1.2v, 20mv/div., ac coupled trace 2: lx, 10v/div trace 3: not connected trace 4: load current, 5a/div timebase: 10s/div. please refer to figure 8 on page 17 for test schematic not recommended for new design not recommended for new design
24 ? 2005 semtech corp. www.semtech.com sc470 power management typical characteristics (cont.) load transient response, power save mode, 0a to 6a to 0a trace 1: 1.2v, 50mv/div., ac coupled trace 2: lx, 20v/div trace 3: not connected trace 4: load current, 5a/div timebase: 40s/div. load transient response, power save mode, 0a to 6a zoomed load transient response, power save mode, 6a to 0a zoomed trace 1: 1.2v, 50mv/div., ac coupled trace 2: lx, 10v/div trace 3: not connected trace 4: load current, 5a/div timebase: 10s/div. trace 1: 1.2v, 20mv/div., ac coupled trace 2: lx, 10v/div trace 3: not connected trace 4: load current, 5a/div timebase: 10s/div. please refer to figure 8 on page 17 for test schematic not recommended for new design not recommended for new design
25 ? 2005 semtech corp. www.semtech.com sc470 power management typical characteristics (cont.) dynamic output voltage switching from 1v to 1.2v to 1v, no load trace 1: toggle signal (for reference only) trace 2: lx, 20v/div trace 3: vout, 50mv/div, offset 1v trace 4: not connected timebase: 200s/div. dynamic output voltage switching from 1v to 1.2v zoomed, no load dynamic output voltage switching from 1.2v to 1v zoomed, no load trace 1: toggle signal (for reference only) trace 2: lx, 20v/div trace 3: vout, 50mv/div, offset 1v trace 4: not connected timebase: 10s/div. trace 1: toggle signal (for reference only) trace 2: lx, 20v/div trace 3: vout, 50mv/div, offset 1v trace 4: not connected timebase: 10s/div. please refer to figure 8 on page 17 for test schematic not recommended for new design not recommended for new design
26 ? 2005 semtech corp. www.semtech.com sc470 power management typical characteristics (cont.) dynamic output voltage switching from 1v to 1.2v to 1v, 6a load trace 1: toggle signal (for reference only) trace 2: lx, 20v/div trace 3: vout, 50mv/div, offset 1v trace 4: not connected timebase: 200s/div. dynamic output voltage switching from 1v to 1.2v zoomed, 6a load dynamic output voltage switching from 1.2v to 1v zoomed, 6a load trace 1: toggle signal (for reference only) trace 2: lx, 20v/div trace 3: vout, 50mv/div, offset 1v trace 4: not connected timebase: 10s/div. trace 1: toggle signal (for reference only) trace 2: lx, 20v/div trace 3: vout, 50mv/div, offset 1v trace 4: not connected timebase: 10s/div. please refer to figure 8 on page 17 for test schematic not recommended for new design not recommended for new design
27 ? 2005 semtech corp. www.semtech.com sc470 power management typical characteristics (cont.) startup (psv), en/psv going high trace 1: 1.2v, 0.5v/div. trace 2: lx, 10v/div trace 3: en/psv, 5v/div trace 4: pgd, 5v/div. timebase: 1ms/div. startup (ccm), en/psv 0v to floating trace 1: 1.2v, 0.5v/div. trace 2: lx, 10v/div trace 3: en/psv, 5v/div trace 4: pgd, 5v/div. timebase: 1ms/div. please refer to figure 8 on page 17 for test schematic not recommended for new design not recommended for new design
28 ? 2005 semtech corp. www.semtech.com sc470 power management marking information - mlpq-16 outline drawing - mlpq-16 indicator (laser mark) pin 1 dimensions nom inches n bbb aaa a2 a1 e1 d1 dim l e e d a b min max millimeters minmax nom .153 .157 .161 3.90 4.00 4.10 .153 .157 .161 3.90 4.00 4.10 e1 .003 .010 .079 16 .012 .085 - .000 .031 (.008) 0.08 0.30 16 .014 .089 0.25 2.00 .040 - .002 - 0.00 0.80 2.25 0.35 2.15 - 0.05 1.00 (0.20) .004 0.10 2.00 2.15 2.25 0.65 bsc .026 bsc 0.30 .012 .020 .016 0.40 0.50 .089 .085 .079 d/2 2 a a1 1 lxn bbb c a b a2 bxn e seating plane c e/2 d1 n e/2 aaa c controlling dimensions are in millimeters (angles in degrees). coplanarity applies to the exposed pad as well as the terminals. 1. 2. notes: a d e b - - - - marking for the 4 x 4mm mlpq 16 lead package: yyww nnnnn = part number (example: sc470) yyww = date code (example: 0552) xxxxx = semtech lot no. (example: e9010 xxxxx 1-100) xxxxx xxxxx sc470 not recommended for new design not recommended for new design
29 ? 2005 semtech corp. www.semtech.com sc470 power management land pattern - mlpq-16 this land pattern is for reference purposes only. consult your manufacturing group to ensure your company's manufacturing guidelines are met. notes: 1. 2x g h 2x (c) 2x z x p y k c z p y x g k h .189 .026 .016 .037 .114 .091 .091 4.80 0.40 0.95 0.65 2.30 2.30 2.90 dim (3.85) millimeters dimensions (.152) inches not recommended for new design not recommended for new design
30 ? 2005 semtech corp. www.semtech.com sc470 power management outline drawing - tssop-14 marking information - tssop-14 top mark bottom yyww = datecode (example: 9812) xxxxxx = semtech lot # (example: 81101) sc470i xxxxxx yyww nom inches dimensions c n ccc aaa bbb 01 e l1 l e e1 d min a a1 a2 b dim millimeters min max nom max e reference jedec std mo-153, variation ab-1. 4. gage plane see detail detail a a 0.25 .026 bsc .252 bsc 14 .004 .169 .193 .173 .197 .007 - 14 0.10 0.65 bsc 6.40 bsc 4.40 5.00 - .177 .201 4.30 4.90 .012 0.19 4.50 5.10 0.30 pin 1 indicator seating bbb c a-b d ccc c plane dimensions "e1" and "d" do not include mold flash, protrusions 3. or gate burrs. datums and to be determined at datum plane controlling dimensions are in millimeters (angles in degrees). -b- notes: 1. 2. -a- -h- side view a b c d e h d 0 .008 - .004 .018 .003 (.039) .024 - .031 .002 - - - - 0.10 0.20 8 0 - 8 0.60 (1.0) .030 .007 0.45 0.09 .047 .042 .006 0.80 0.05 - 0.20 0.75 - 1.05 0.15 1.20 - - - bxn a a2 a1 e/2 2x e1 2x n/2 tips 12 3 aaa c l (l1) c 01 not recommended for new design not recommended for new design
31 ? 2005 semtech corp. www.semtech.com sc470 power management land pattern - tssop-14 (.222) (5.65) z g y p (c) 4.10 .161 0.65 .026 0.40 .016 1.55 .061 7.20 .283 x inches dimensions z p y x dim c g millimeters this land pattern is for reference purposes only. consult your manufacturing group to ensure your company's manufacturing guidelines are met. notes: 1. visit us at: www .semtech.com semtech corporation power management products division 200 flynn road, camarillo, ca 93012 phone: (805) 498-2111 fax (805)498-3804 contact information not recommended for new design not recommended for new design

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