p roduction d ata s heet t he i nfinite p ower of i nnovation not recommended for new desi g n l in f inity m icroelectronics i nc . 11861 w estern a venue , g arden g rove , ca. 92841, 714-898-8121, f ax : 714-893-2570 1 copyright ? 1994 rev. 1.3a,2005-03-21 sg1825c / sg2825c / sg3825c h igh -s peed c urrent -m ode pwm description the sg1825c is a high-performance pulse width modulator optimized for high frequency current-mode power supplies. included in the controller are a precision voltage reference, micro power start-up circuitry, soft start, high- frequency oscillator, wideband error amplifier, fast current limit comparator, full double-pulse suppression logic, and dual totem pole output drivers. innovative circuit design and an advanced linear schottky process result in very short propagation delays through the current limit comparator, logic, and output drivers. this device can be used to implement either current mode or voltage- mode switching power supplies. it also is useful as a series-resonant controller to frequencies beyond 1mhz. the sg1825c is specified for operation over the full military ambient temperature range of -55c to 125c. the sg2825c is characterized for the industrial range of -25c to 85c, and the sg3825c is selected for the commercial range of 0c to 70c. important: for the most current data, consult microsemi ?s website: http://www.microsemi.com product highlight 0 5 15 10 390 395 400 405 410 initial oscillator accuracy - khz 415 sample size = 279 mean 401.661 std. dev. = 3.8 i nitial o scillator a ccuracy percentage of units - % key features ? improved reference initial tolerance (1% max.) ? improved oscillator initial accuracy (3% typ.) ? improved startup current (500a typ.) ? prop delay to outputs (50ns typ.) ? 10v to 30v operation ? 5.1v reference trimmed to 1% ? 2mhz oscillator capability ? 1.5a peak totem-pole drivers ? u.v. lockout with hysteresis ? no output driver "float" ? programmable softstart ? double-pulse suppression logic ? wideband low-impedance error amplifier ? current-mode or voltage-mode control ? wide choice of high- frequency packages key features ? available to mil-std-883b ? microsemi level "s" processing avail. package order info n plastic dip 16-pin dw plastic soic 16-pin q plastic lcc 20-pin j ceramic dip 16-pin l ceramic lcc 20-pin t j ( c) rohs compliant / pb-free transition dc: 0503 rohs compliant / pb-free transition dc: 0516 0 to 70 sg3825cn sg3825cdw sg32825cq sg3825cj - -25 to 85 sg2825cn sg2825cdw sg2825cq sg282cj - -55 to 125 - - - sg1825cj sg1825cl mil-std-883 - - - sg1825cj/883b sg1825cl/883 desc - - - sg1825cj/desc sg1825cl/desc note: available in tape & reel. append the letters ?tr? to the part number. (i.e. sg3825cn-tr)
h igh -s peed c urrent -m ode pwm sg1825c/sg2825c/sg3825c product databook 1996/1997 copyright ? 1994 rev. 1.3a 2 n ot r ecommended for n ew d esigns absolute maximum ratings (note 1) input voltage (v in and v c ) .......................................................................................... 30v analog inputs: error amplifier and ramp ........................................................................ -0.3v to 7.0v softstart and i lim /s.d. ................................................................................ -0.3v to 6.0v digital input (clock) .................................................................................... 1.5v to 6.0v driver outputs ........................................................................................ -0.3v to v c +1.5v source / sink output current (each output): continuous .............................................................................................................. 0.5a pulse, 500ns ............................................................................................................ 2.0a softstart sink current ................................................................................................ 20ma clock output current ................................................................................................. 5ma error amplifier output current ................................................................................. 5ma oscillator charging current ....................................................................................... 5ma operating junction temperature: hermetic (j, l package) ....................................................................................... 150c plastic (dw, n, q packages) ............................................................................... 150c storage temperature range ...................................................................... -65c to 150c lead temperature (soldering, 10 seconds) ............................................................ 300c package pin outs 1 16 215 314 413 512 611 710 89 j & n* package (top view) 4 5 6 7 8 321 9111213 10 14 15 16 17 18 20 19 dw package* (top view) note 1. exceeding these ratings could cause damage to the device. n package: thermal resistance-junction to ambient, q q q q q ja 65c/w dw package: thermal resistance-junction to ambient, q q q q q ja 95c/w q package: thermal resistance-junction to ambient, q q q q q ja 80c/w j package: thermal resistance-junction to ambient, q q q q q ja 80c/w l package: thermal resistance-junction to case, q q q q q jc 35c/w thermal resistance-junction to ambient, q q q q q ja 120c/w junction temperature calculation: t j = t a + (p d x q ja ). the q ja numbers are guidelines for the thermal performance of the device/pc-board system. all of the above assume no ambient airflow. thermal data inv. input n.i. input e/a output clock r t c t ramp softstart v ref +v in output b v c pwr gnd output a ground i lim / s.d. 1 16 215 314 413 512 611 710 89 +v ref +v in output b v c pwr gnd output a ground i lim / s.d. inv. input n.i. input e/a output clock r t c t ramp softstart 11. n.c. 12. i lim / s.d. 13. ground 14. output a 15. pwr gnd 16. n.c. 17. v c 18. output b 19. +v in 20. v ref 1. n.c. 2. inv. input 3. n.i. input 4. e/a output 5. clock 6. n.c. 7. r t 8. c t 9. ramp 10. softstart l package (top view) q package (top view) 3212019 418 17 5 616 15 7 814 9 111213 10 rohs peak package solder reflow temp. (40 sec. max. exp.)......................................................... 260 (+0, -5) *dw & n packages: rohs / pb-free 100% matte tin lead finish
h igh -s peed c urrent -m ode pwm sg1825c/sg2825c/sg3825c product databook 1996/1997 3 copyright ? 1994 rev. 1.3a n ot r ecommended for n ew d esigns supply voltage range voltage amp common mode range ramp input voltage range current limit / shutdown voltage range source / sink output current continuous pulse, 500ns voltage reference output current oscillator frequency range oscillator charging current oscillator timing resistor r t oscillator timing capacitor c t operating ambient temperature range: sg1825c t a sg2825c t a sg3825c t a recommended operating conditions (note 2) parameter symbol units recommended operating conditions min. typ. max. 10 30 v 1.5 5.5 v 0 5.0 v 0 4.0 v 200 ma 1.0 a 110ma 4 1500 khz 0.030 3 ma 1 100 k w 0.470 10 nf 070c -25 85 c -55 125 c note 2. range over which the device is functional. electrical characteristics (note 3) (unless otherwise specified, these specifications apply over the operating ambient temperatures for sg3825c with 0c t a 70c, sg2825c with -25c t a 85c, sg1825c with -55c t a 125c, and v in =v c =15v. low duty cycle pulse testing techniques are used which maintains junction and case temperatures equal to the ambient temperature.) reference section parameter symbol test conditions output voltage t j = 25c, i l = 1ma line regulation v in = 10 to 30v load regulation i l = 1 to 10ma temperature stability (note 3) over operating temperature total output range (note 3) over line, load, and temperature output noise voltage (note 3) f = 10hz to 10khz, i l = 0ma long term stability (notes 3 &4) t j = 125c, t = 1000hrs short circuit current v ref = 0v oscillator section (note 5) initial accuracy t j = 25c, c clk 10pf voltage stability v in = 10 to 30v temperature stability (note 3) over rated operating temperature total frequency limits (note 3) over line and temperature minimum frequency r t = 100k w , c t = 0.01f maximum frequency r t = 1k w , c t = 470pf clock high level i clk = -1ma clock low level i clk = -1ma ramp peak voltage ramp valley voltage valley-to-peak amplitude note 3. this parameter is guaranteed by design and process control, but is not 100% tested in production. note 4. this parameter is non-accumulative, and represents the random fluctuation of the reference voltage within some error ban d when observed over any 1000 hour period of time. sg3825c units min. typ. max. min. typ. max. sg1825c/2825c 5.05 5.10 5.15 5.05 5.10 5.15 v 215 215 mv 515 515 mv 0.2 0.4 0.2 0.4 mv/c 5.00 5.20 5.00 5.20 v 50 200 50 v rms 525 525 mv -15 -50 -100 -15 -50 -100 ma 370 400 430 370 400 430 khz 0.2 2 0.2 2 % 58 58 % 350 450 350 450 khz 4 4 khz 1.5 1.5 mhz 3.9 4.5 3.9 4.5 v 2.3 2.9 2.3 2.9 v 2.6 2.8 3.0 2.6 2.8 3.0 v 0.7 1.0 1.25 0.7 1.0 1.25 v 1.6 1.8 2.0 1.6 1.8 2.0 v
h igh -s peed c urrent -m ode pwm sg1825c/sg2825c/sg3825c product databook 1996/1997 copyright ? 1994 rev. 1.3a 4 n ot r ecommended for n ew d esigns electrical characteristics (cont'd.) parameter symbol test conditions error amplifier section (note 6) input offset voltage r s 2k w , v error = 2.5v input bias current v error = 2.5v input offset current v error = 2.5v dc open loop gain a vol v error = 1 to 4v common mode rejection over rated voltage range, v error = 2.5v power supply rejection v in = 10v to 30v, v error = 2.5v output sink current v error = 1v output source current v error = 4v output high voltage i error = -0.5ma output low voltage i error = 1ma unity gain bandwidth (note 3) a vol = 0db slew rate (note 3) pwm comparator section (note 5 & 7) ramp input bias current minimum duty cycle v error = 1v maximum duty cycle (note 8) v error = 4v zero duty cycle threshold delay to driver output (note 3) v ramp = 0v to 2v, v error = 2v softstart section c ss charge current v softstart = 0.5v c ss discharge current v softstart = 1.0v current limit / shutdown section (note 9) i lim input bias current current limit threshold shutdown threshold delay to driver output (note 3) v shutdown = 0v to 1.2v output drivers section (each output) output low level i sink = 20ma i sink = 200ma output high level i source = 20ma i source = 200ma v c standby current v c = 30v output rise / fall time (note 3) c l = 1000pf undervoltage lockout section start threshold voltage uv lockout hysteresis supply current section (note 5) start up current v in = 8v operating current v inv , v ramp , v(i lim /s.d.) = 0v, v n.i. = 1v note 5. f osc = 400khz (r t = 3.65k w , c t = 1.0nf). note 6. v cm = 1.5v to 5.5v. note 7. v ramp = 0v, unless otherwise specified. note 8. 100% duty cycle is defined as a pulsewidth equal to one oscillator period. note 9. v(i lim /s.d.) = 0v to 4.0v, unless otherwise specified. sg3825c units min. typ. max. min. typ. max. sg1825c/2825c 15 15 mv 0.6 3 0.6 3 a 0.1 1 0.1 1 a 60 95 60 95 db 75 95 75 95 db 85 110 85 110 db 1 2.5 1 2.5 ma -0.5 -1.3 -0.5 -1.3 ma 4.0 4.7 5.0 4.0 4.7 5.0 v 0 0.5 1.0 0 0.5 1.0 v 3 5.5 3 5.5 mhz 6 6 v/sec -1 -5 -1 -5 a 00% 85 85 % 1.1 1.25 1.1 1.25 v 50 80 50 80 ns 39203920 a 11 ma 15 10 a 0.9 1.0 1.1 0.9 1.0 1.1 v 1.25 1.40 1.55 1.20 1.40 1.55 v 50 80 50 80 ns 0.25 0.40 0.25 0.40 v 1.2 2.0 1.2 2.0 v 13.0 13.5 13.0 13.5 v 12.0 13.0 12.0 13.0 v 150 500 150 500 a 30 60 30 60 ns 8.8 9.2 9.7 8.8 9.2 9.7 v 0.4 0.8 1.2 0.4 0.8 1.2 v 0.5 1.2 0.5 1.2 ma 22 33 22 33 ma
h igh -s peed c urrent -m ode pwm sg1825c/sg2825c/sg3825c product databook 1996/1997 5 copyright ? 1994 rev. 1.3a n ot r ecommended for n ew d esigns block diagram figure index application circuits figure # 1. high-speed layout and bypassing 2. micropower startup 3. softstart fast reset 4. oscillator sychronization 5. oscillator functional diagram 6. voltage amplifier connections 7. driving shielded cable +9v reference regulator 15 10 16 oscillator 5 6 4 + 4.0v s rq 7 1.25v 3 error 2 1 8 + 1.4v 9 11 i lim /s.d. output a v ref +v in gnd clock r t c t ramp e/a output n.i. input inv. input softstart 9a + 1.0v 12 power gn d 14 output b q q t 13 v c
h igh -s peed c urrent -m ode pwm sg1825c/sg2825c/sg3825c product databook 1996/1997 copyright ? 1994 rev. 1.3a 6 n ot r ecommended for n ew d esigns application information the sg1825c, like all high-speed circuits, requires extra attention to external conductor and component layout to minimize undesired inductive and capacitive effects. all lead lengths must be as short as possible. the best printed circuit board choice would be a four-layer design, with the two internal planes supplying power and ground. signal interconnects should be placed on the outside, giving a conductor-over-ground-plane (microstrip) configuration. a two-sided printed circuit board with one side dedicated as a ground plane is next best, and requires careful component placement by a skilled pc designer. two supply bypass capacitors should be employed: a low-inductance 0.1f ceramic within 0.25 inches of the +v in pin for high frequencies, and a 1 to 5f solid tantalum within 0.5 inches of the v c pin to provide an energy reservoir for the high-peak output currents. a low-inductance .01f bypass for the reference output is also recommended. high-speed layout and bypassing figure 1. ? high-speed layout and bypassing frequency synchronization two or three sg1825c oscillators may be locked together with the interconnection scheme shown, if the devices are within an inch or so of each other. a master unit is programmed for desired frequency with r t and c t as usual. the oscillators in the slave units are disabled by grounding c t and by connecting r t to v ref . the logic in the slave units is locked to the clock of the master with the wire-or connection shown. many sg1825cs can be locked to a master system clock by wiring the oscillators as slave units, and distributing the master clock to each using a tree-fanout geometry. since the sg1825c typically draws 700a of supply current before turning on, a low power bleeder resistor from the rectified ac line supply is all that is required for startup. a start capacitor, c s , is charged with the excess current from the bleeder resistor. when the turn-on threshold voltage is reached, the pwm circuit becomes active, energizing the power transistors. the additional operating current required by the pwm is then provided by a bootstrap winding on the main high-frequency power transformer. softstart circuit / output duty cycle limit the softstart pin of the sg1825c is held low when either the chip is in the micropower mode, or when a voltage greater than +1.4 volts is present at the i lim/s.d. pin. the maximum positive swing of the voltage error amplifier is clamped to the softstart pin voltage, providing a ramp-up of peak charging currents in the power semiconductors at turn-on. in some cases, the duration of the shutdown signal can be too short to fully discharge the softstart capacitor. the illustrated resistor/discrete pnp transistor configuration can be used to shorten the discharge time by a factor of 50 or more. when the internal discharge transistor in the sg1825c turns on, current will flow through surge limit resistor r1. as the resistor drop approaches 0.6 volts, the external pnp turns on, providing a low resistance discharge path for the energy in the softstart capacitor. the capacitor will be rapidly discharged to +0.7 volts, which corresponds to zero duty cycle in the pulse width modulator. application figures figure 3. ? softstart fast reset micropower startup 13 12 10 v c power gnd gnd 15 +v in 0.1f + v in r b c s to power transformer sg1825c l1 gnd l2 240 120 1f c t r t 10 12 6 pwr gnd gnd +v in 15 0.1f + v in 5 sg1825c clk 4 c t r t 10 12 6 pwr gnd gnd +v in 15 0.1f 5 sg1825c v ref 16 clk 4 c t r t master slave v ref v c 0.01f v ref 10 12 13 pwr gnd gnd +v in 15 0.1f + v in 1f 16 sg1825c figure 2. ? micropower startup v c c ss 10 12 13 pwr gnd gnd +v in 15 0.1f + v in 1f 8 sg1825c r 1 100 w c softstart figure 4. ? oscillator sychronization
h igh -s peed c urrent -m ode pwm sg1825c/sg2825c/sg3825c product databook 1996/1997 7 copyright ? 1994 rev. 1.3a n ot r ecommended for n ew d esigns application information figure 5. ? oscillator functional diagram application figures the oscillator frequency is programmed by external timing components r t and c t . a nominal +3.0 volts appears at the r t pin. the current flowing through r t is mirrored internally with a 1:1 ratio. this causes an identical current to flow out the c t pin, charging the timing capacitor and generating a linear ramp. when the upper threshold of +2.8 volts is reached, a discharge network reduces the ramp voltage to +1.0, where a new charge cycle begins. the clock output pin is low (+2.3 volts) during the charge cycle, and high (+4.5 volts) during the discharge cycle. the clock pin is driven by an npn emitter follower, and so can be wire-ored. each clock pin can drive a 1ma load. since the internal current-source pulldown is approximately 400a, the dc fan-out to other sg1825c clock pins is at least two. the type of capacitor selected for c t is very important. at high frequencies, non-ideal characteristics such as effective series resistance (esr), effective series inductance (esl), dielectric loss and dielectric absorption all affect frequency accuracy and stability. rf capacitors such as silver mica, glass, polystrene, or cog ceramics are recommended. avoid high-k ceramics, which work best in dc bypass applications. oscillator error amplifier the voltage error amplifier is a true operational amplifier with low- impedance output, and can be gain-stabilized using conventional feedback techniques. the typical dc open-loop gain is 95db, with a single low- frequency pole at 100hz. the input connections to the error amplifier are determined by the polarity of the power supply output voltage. for positive supplies, the common-mode voltage is +5.1 volts and the feedback connections in figure a are used. with negative outputs, the common-mode voltage is half the reference, and the feedback divider is connected between the negative output and the +5.1 volt reference as shown in figure b. figure 6. ? voltage amplifier connections figure 7. ? driving shielded cable output driver the output drivers are designed to provide up to 1.5 amps peak output current. to minimize ringing on the output waveform, which can be destructive to both the power mosfet and the pwm chip, the series inductance seen by the drivers should be as low as possible. one solution is to keep the distance between the pwm and mosfet gate as short as possible, and to use carbon composition series damping resistors. a faraday shield to intercept radiated emi from the power transistors is usually required with its choice. a second approach is to place the mosfets some distance from the pwm chip, and use a series-terminated transmission line to preserve drive pulse fidelity. this will minimize noise radiated back to the sensitive analog circuitry of the sg1825c. a faraday shield may also be required. if the drivers are connected to an isolation transformer, or if kickback through c gd of the mosfet is severe, clamp diodes may be required. 1 amp peak schottky diodes will limit undershoot to less than -0.3 volts. 4 + 5.1v 2.8v 1.0v 400a sg1825c i c = i r c t r t clock + 4.5 v + 2.3 v i r 3v 5 6 v ref 2 1 3 r 3 r z c p r 4 positive output voltage v ref 2 1 3 r 3 r z c p v ref 2 v error v error figure b figure a r 1 r 2 r 1 r 2 negative output voltage r 4 12 11 13 10 pwr gnd gnd * 50 w 50 w v c 24 w faraday shield * schottky clamp may be required sg1825c
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