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dac3282 www.ti.com slas646a ? december 2009 ? revised february 2010 16-bit, 625 msps, 2x interpolating, dual-channel digital-to-analog converter (dac) check for samples: dac3282 1 features description ? dual, 16-bit, 625 msps dacs ? 8-bit input lvds data bus the dac3282 is a dual-channel 16-bit 625 msps digital-to-analog converter (dac) with an 8-bit lvds ? byte-wide interleaved data load input data bus with on-chip termination, optional 2x ? 8 sample input fifo interpolation filter, and internal voltage reference. the ? optional data pattern checker dac3282 offers superior linearity, noise and crosstalk performance. ? multi-dac synchronization ? optional 2x interpolation filter input data can be interpolated by 2x through an on-chip interpolating fir filter with over 85 db of ? zero-if sinc correction filter stop-band attenuation. multiple dac3282 devices can ? fs/2 and fs/4 coarse mixer be fully synchronized. ? digital offset adjustment for lo correction the dac3282 allows either a complex or real output. ? temperature sensor an optional coarse mixer in complex mode provides ? 3- or 4-wire serial control interface frequency upconversion and the dual dac output produces a complex hilbert transform pair. the ? on chip 1.2-v reference digital offset correction feature allows optimization of ? differential scalable output: 2 to 20 ma lo feed-through of an external quadrature modulator ? low power: 950 mw at 625 msps, 845 mw at performing the final single sideband rf 500 mhz, full operating conditions up-conversion. ? space saving package: 48-pin 7 7mm qfn the dac3282 is characterized for operation over the entire industrial temperature range of ? 40 c to 85 c applications and is available in a 48-pin 7 7mm qfn package. ? cellular base stations ? diversity transmit ? wideband communications ? digital synthesis spacer for space above the ordering information table spacer for space above the ordering information table ordering information package transport t a order code quantity drawing/type (1) (2) media dac3282irgzt rgz / 48qfn quad flatpack 250 ? 40 c to 85 c tape and reel no-lead dac3282irgzr 2500 (1) thermal pad size: 5,6 mm x 5,6 mm (2) msl peak temperature: level-3-260c-168 hr 1 please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. production data information is current as of publication date. copyright ? 2009 ? 2010, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters.
dac3282 slas646a ? december 2009 ? revised february 2010 www.ti.com this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. functional block diagram 2 submit documentation feedback copyright ? 2009 ? 2010, texas instruments incorporated product folder link(s): dac3282 100 100 pattern test de-interleave 8 sample fifo 16 16 100 x sin(x) x sin(x) x2 x2 coarse mixer fs/4, -fs/4, fs/2 programmable delay (0-15t) 1.2 v reference 16-b dac 16-b dac control interface temp sensor clock distribution a gain b gain frame strobe extiobiasj iouta1 iouta2 ioutb1 ioutb2 dacclkp dacclkn dataclkp dataclkn d7p d7n d0p d0n framep framen ostrp ostrn a offset b offset alarm_sdo sdio sdenb sclk txenable resetb avdd33 clkvdd18 digvdd18 vfuse dacvdd18 gnd lvpecl lvds lvpecl lvds lvds fir0 fir4 5 taps 59 taps 100 lvds
dac3282 www.ti.com slas646a ? december 2009 ? revised february 2010 pinout pin functions pin i/o description name no. 37, 40, 42, avdd33 i analog supply voltage. (3.3 v) 45, 48 1.8v cmos output for alarm condition. the alarm output functionality is defined through the config6 register. default polarity is active low, but can be changed to active high via config0 alarm_sdo 34 o alarm_pol control bit. optionally, it can be used as the uni-directional data output in 4-pin serial interface mode (config 23 sif4_ena = ? 1 ? ). biasj 43 o full-scale output current bias. for 20ma full-scale output current, connect a 960 ? resistor to gnd. internal clock buffer supply voltage. (1.8 v) clkvdd18 1 i it is recommended to isolate this supply from dacvdd18 and digvdd18. lvds positive input data bits 0 through 7. each positive/negative lvds pair has an internal 100 ? termination resistor. data format relative to dataclkp/n clock is double data rate (ddr) with two data transfers per datackp/n clock cycle. dual channel 16-bit data is transferred byte-wide on this 9, 11, 13, single 8-bit data bus using framep/n as a frame strobe indicator. d[7..0]p 15, 21, 23, i d7p is most significant data bit (msb) ? pin 9 25, 27 d0p is least significant data bit (lsb) ? pin 27 the order of the bus can be reversed via config19 rev bit. lvds negative input data bits 0 through 15. (see d[7:0]p description above) 10, 12, 14, d[7..0]n 16, 22, 24, i d7n is most significant data bit (msb) ? pin 10 26, 28 d0n is least significant data bit (lsb) ? pin 28 copyright ? 2009 ? 2010, texas instruments incorporated submit documentation feedback 3 product folder link(s): dac3282 37 38 39 40 41 42 43 44 45 46 47 48 12 3 45 67 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 3534 33 3231 3029 28 27 26 25 dac3282 rgz package 48-qfn 7x7mm (top view ) 36 gnd dacclkn d5p d5n d4p d4n dataclkp dataclkn framep framen d3p d3n d2p d2n d1p d1n d0p d0n txenable sdio sclk sdenb avdd33 avdd33 ioutb1 ioutb2 vfuse biasj extio avdd33 iouta2 iouta1 avdd33 avdd33 d6n d6p d7n d7p digvdd18 ostrn ostrp dacclkp dacvdd18 clkvdd18 resetb dacvdd18 alarm_sdo digvdd18
dac3282 slas646a ? december 2009 ? revised february 2010 www.ti.com pin functions (continued) pin i/o description name no. dacclkp 3 i positive external lvpecl clock input for dac core with a self-bias of approximately clkvdd18/2. dacclkn 4 i complementary external lvpecl clock input for dac core. (see the dacclkp description) dac core supply voltage. (1.8 v) dacvdd18 2, 35 i it is recommended to isolate this supply from clkvdd18 and digvdd18. lvds positive input data clock. this positive/negative pair has an internal 100 termination resistor. dataclkp 17 i input data d[7:0]p/n is latched on both edges of dataclkp/n (double data rate) with two data transfers input per dataclkp/n clock cycle. dataclkn 18 i lvds negative input data clock. (see dataclkp description) digital supply voltage. (1.8v) digvdd18 8, 29 i it is recommended to isolate this supply from clkvdd18 and dacvdd18. used as external reference input when internal reference is disabled through config25 extref_ena = extio 44 i/o ? 1 ? . used as internal reference output when config25 extref_ena = ? 0 ? (default). requires a 0.1 m f decoupling capacitor to agnd when used as reference output. lvds frame indicator positive input. this positive/negative pair has an internal 100 termination resistor. this signal is captured with the rising edge of dataclkp/n and used to indicate the framep 19 i beginning of the frame. it is also used as a reset signal by the fifo. the framep/n signal should be edge-aligned with d[7:0]p/n. framen 20 i lvds frame indicator negative input. (see the framen description) 5, thermal gnd i pin 5 and the thermal pad located on the bottom of the qfn package is ground for all supplies. pad a-channel dac current output. an offset binary data pattern of 0x0000 at the dac input results in a iouta1 38 o full scale current sink and the least positive voltage on the iouta1 pin. similarly, a 0xffff data input results in a 0 ma current sink and the most positive voltage on the iouta1 pin. a-channel dac complementary current output. the iouta2 has the opposite behavior of the iouta1 iouta2 39 o described above. an input data value of 0x0000 results in a 0 ma sink and the most positive voltage on the iouta2 pin. ioutb1 47 o b-channel dac current output. refer to iouta1 description above. ioutb2 46 o b-channel dac complementary current output. refer to iouta2 description above. lvpecl output strobe positive input. this positive/negative pair is captured with the rising edge of ostrp 6 i dacclkp/n. it is used to reset the clock dividers and for multiple dac synchronization. if unused it can be left floating. ostrn 7 i lvpecl output strobe negative input. (see the ostrp description) resetb 36 i 1.8v cmos active low input for chip reset. internal pull-up. sclk 32 i 1.8v cmos serial interface clock. internal pull-down. sdenb 33 i 1.8v cmos active low serial data enable, always an input to the dac3282. internal pull-up. 1.8v cmos serial interface data. bi-directional in 3-pin mode (default). in 4-pin interface mode, the sdio 31 i/o sdio pin is an input only. internal pull-down. 1.8v cmos active high input. txenable must be high for the data to the dac to be enabled. txenable 30 i when txenable is low, the digital logic section is forced to all 0, and any input data is ignored. internal pull-down. digital supply voltage. (1.8v) this supply pin is also used for factory fuse programming. connect to vfuse 41 i dacvdd18 pins for normal operation. 4 submit documentation feedback copyright ? 2009 ? 2010, texas instruments incorporated product folder link(s): dac3282
dac3282 www.ti.com slas646a ? december 2009 ? revised february 2010 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) value unit dacvdd18 (2) ? 0.5 to 2.3 v digvdd18 (2) ? 0.5 to 2.3 v supply voltage range clkvdd18 (2) ? 0.5 to 2.3 v vfuse (2) ? 0.5 to 2.3 v avdd33 (2) ? 0.5 to 4 v terminal voltage range clkvdd18 to digvdd18 ? 0.5 to 0.5 v dacvdd18 to digvdd18 ? 0.5 to 0.5 v d[7..0]p ,d[7..0]n, dataclkp,dataclkn, framep, ? 0.5 to digvdd18 + 0.5 v framen (2) dacclkp, dacclkn, ostrp, ostrn (2) ? 0.5 to clkvdd18 + 0.5 v alarm_sdo, sdio, sclk, sdenb, resetb, txenable (2) ? 0.5 to digvdd18 + 0.5 v iouta1/b1, iouta2/b2 (2) ? 1.0 to avdd33 + 0.5 v extio, biasj (2) ? 0.5 to avdd33 + 0.5 v peak input current (any input) 20 ma peak total input current (all inputs) ? 30 ma operating free-air temperature range, t a : dac3282 ? 40 to 85 c storage temperature range ? 65 to 150 c lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds 260 c (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and functional operation of these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) measured with respect to gnd. thermal characteristics over operating free-air temperature range (unless otherwise noted) thermal conductivity 48ld qfn unit t j maximum junction temperature (1) (2) 125 c theta junction-to-ambient (still air) 30 c/w q ja theta junction-to-ambient (150 lfm) 24 c/w q jb theta junction-to-board 8 c/w q jp theta junction-to-pad 1.3 c/w (1) air flow or heat sinking reduces q ja and may be required for sustained operation at 85 and maximum operating conditions. (2) it is strongly recommended to solder the device thermal pad to the board ground plane. copyright ? 2009 ? 2010, texas instruments incorporated submit documentation feedback 5 product folder link(s): dac3282
dac3282 slas646a ? december 2009 ? revised february 2010 www.ti.com electrical characteristics ? dc specifications (1) over recommended operating free-air temperature range, nominal supplies, iout fs = 20 ma (unless otherwise noted) parameter test conditions min typ max unit resolution 16 bits dc accuracy dnl differential nonlinearity 2 lsb 1 lsb = iout fs /2 16 inl integral nonlinearity 4 lsb analog output coarse gain linearity 0.04 lsb offset error mid code offset 0.01 %fsr with external reference 2 %fsr gain error with internal reference 2 %fsr gain mismatch with internal reference ? 2 2 %fsr minimum full scale output current 2 nominal full-scale current, ma iout fs = 16 ibias current. maximum full scale output current 20 avdd avdd output compliance range (2) iout fs = 20 ma v ? 0.5v +0.5v output resistance 300 k ? output capacitance 5 pf reference output v ref reference output voltage 1.14 1.2 1.26 v reference output current (3) 100 na reference input v extio input voltage range 0.1 1.2 1.25 v external reference mode input resistance 1 m ? small signal bandwidth 472 khz input capacitance 100 pf temperature coefficients ppm of offset drift 1 fsr/ c with external reference 15 ppm of gain drift fsr/ c with internal reference 30 reference voltage drift 8 ppm/ c (1) measured differential across iouta1 and iouta2 or ioutb1 and ioutb2 with 25 ? each to avdd. (2) the lower limit of the output compliance is determined by the cmos process. exceeding this limit may result in transistor breakdown, resulting in reduced reliability of the dac3282 device. the upper limit of the output compliance is determined by the load resistors and full-scale output current. exceeding the upper limit adversely affects distortion performance and integral nonlinearity. (3) use an external buffer amplifier with high impedance input to drive any external load. 6 submit documentation feedback copyright ? 2009 ? 2010, texas instruments incorporated product folder link(s): dac3282
dac3282 www.ti.com slas646a ? december 2009 ? revised february 2010 electrical characteristics ? dc specifications (1) (continued) over recommended operating free-air temperature range, nominal supplies, iout fs = 20 ma (unless otherwise noted) parameter test conditions min typ max unit power supply avdd33 3.0 3.3 3.6 v dacvdd18, digvdd18, clkvdd18 1.7 1.8 1.9 v i (avdd33) analog supply current 96 ma i (digvdd18) digital supply current 268 ma mode 1(below) i (dacvdd18) dac supply current 74 ma i (clkvdd18) clock supply current 10 ma power down mode analog supply i (avdd33) 2 ma current power down mode digital supply i (digvdd18) 3 ma current mode 4 (below) power down mode dac supply i (dacvdd18) 0.5 ma current power down mode clock supply i (clkvdd18) 1 ma current mode 1: f dac = 625msps, 2x interpolation, mixer on, 950 1100 mw digital offset control on mode 2: f dac = 491.52msps, 2x interpolation, zero-if 845 mw correction filter on, mixer off, digital offset control on mode 3: sleep mode, f dac = 625msps, 2x interpolation, mixer on, p power dissipation 575 mw dac in sleep mode: config24 sleepa, sleepb set to 1 mode 4: power-down mode, no clock, static data pattern, dac in power-down mode: 15 mw config23 clkpath_sleep_a, clkpath_sleepb set to 1 config24 clkrecv_sleep, sleepa, sleepb set to 1 psrr power supply rejection ratio dc tested ? 0.4 0.4 %/fsr/v t operating range ? 40 25 85 c copyright ? 2009 ? 2010, texas instruments incorporated submit documentation feedback 7 product folder link(s): dac3282
dac3282 slas646a ? december 2009 ? revised february 2010 www.ti.com electrical characteristics ? ac specifications over recommended operating free-air temperature range, nominal supplies, ioutfs = 20 ma (unless otherwise noted) parameter test conditions min typ max unit analog output (1) 1x interpolation 312.5 f dac maximum output update rate msps 2x interpolation 625 t s(dac) output settling time to 0.1% transition: code 0x0000 to 0xffff 10.4 ns dac outputs are updated on the falling edge of dac clock. t pd output propagation delay 2 ns does not include digital latency (see below). t r(iout) output rise time 10% to 90% 220 ps t f(iout) output fall time 90% to 10% 220 ps iout current settling to 1% of iout fs . measured from sdenb dac wake-up time 90 m s rising edge; register config24, toggle sleepa from 1 to 0 power-up iout current settling to less than 1% of iout fs . measured from time dac sleep time sdenb rising edge; register config24, toggle sleepa from 0 90 m s to 1. no interpolation, fifo off, offset off, inverse sinc off 38 2x interpolation 59 dac clock digital latency zero-if sinc correction filter 16 cycles fifo 8 offset 4 ac performance (2) f dac = 625 msps, f out = 10.1 mhz 2x interp, dac a+b on 83 spurious free dynamic range sfdr sfdr f dac = 625 msps, f out = 20.1 mhz 2x interp, dac a+b on 78 dbc (0 to f dac /2) tone at 0 dbfs f dac = 625 msps, f out = 70.1 mhz 2x interp, dac a+b on 64 f dac = 625 msps, f out = 30 0.5 mhz 2x interp, dac a+b on 82 third-order two-tone intermodulation f dac = 625 msps, f out = 50 0.5 mhz 2x interp, dac a+b on 80 imd3 dbc distortion each tone at ? 6 dbfs f dac = 625 msps, f out = 150 0.5 mhz 2x interp, dac a+b 69 on, f dac = 625 msps, f out = 10.1 mhz 2x interp, dac a+b on 161 noise spectral density single tone at nsd dbc/hz 0 dbm f dac = 625 msps, f out = 150.1 mhz 2x interp, dac a+b on 150 f dac = 491.52 msps, f out = 30.72 mhz 2x interp, dac a+b on 81 adjacent channel leakage ratio, dbc single carrier f dac = 491.52 msps, f out = 153.6 mhz 2x interp, dac a+b on 76 wcdma (3) f dac = 491.52 msps, f out = 30.72 mhz 2x interp, dac a+b on 84 dbc alternate channel leakage ratio, single carrier f dac = 491.52 msps, f out = 153.6 mhz 2x interp, dac a+b on 77 dbc channel isolation f dac = 625 msps, f out = 10 mhz 84 dbc (1) measured single ended into 50 ? load. (2) 4:1 transformer output termination, 50 ? doubly terminated load. (3) single carrier, w-cdma with 3.84 mhz bw, 5-mhz spacing, centered at if, par = 12db. testmodel 1, 10 ms 8 submit documentation feedback copyright ? 2009 ? 2010, texas instruments incorporated product folder link(s): dac3282
dac3282 www.ti.com slas646a ? december 2009 ? revised february 2010 electrical characteristics ? digital specifications over recommended operating free-air temperature range, nominal supplies, iout fs = 20 ma (unless otherwise noted) parameter test conditions min typ max unit lvds interface: d[7:0]p/n, dataclkp/n, framep/n (1) byte-wide ddr format f data input data rate 312.5 msps dataclk frequency = 625 mhz 1x interpolation 1250 f bus byte-wide lvds data transfer rate msps 2x interpolation 1250 v a,b+ logic high differential input voltage threshold 175 400 mv v a,b ? logic low differential input voltage threshold ? 175 ? 400 mv v com input common mode 1.0 1.2 2.0 v z t internal termination 85 110 135 ? c l lvds input capacitance 2 pf timing lvds inputs: dataclkp/n, double edge latching ? see figure 36 setup time, d[7:0]p/n and framep/n, valid to framep/n latched on rising edge of t s(data) 0 ps either edge of dataclkp/n dataclkp/n only hold time, d[7:0]p/n and framep/n, valid framep/n latched on rising edge of t h(data) 400 ps after either edge of dataclkp/n dataclkp/n only t (frame) framep/n pulse width f dataclk is dataclk frequency in mhz 1/2f dataclk ns maximum offset between dataclkp/n and fifo bypass mode only 1/2f dacclk t _align ns dacclkp/n rising edges f dacclk is dacclk frequency in mhz ? 0.55 clock input (dacclkp/n) duty cycle 40% 60% differential voltage (2) 0.4 1.0 v dacclkp/n input frequency 625 mhz output strobe (ostrp/n) f ostr = f dacclk / (n 8 interp) where n f dacclk / f ostr frequency is any positive integer f dacclk is dacclk mhz (8 x interp) frequency in mhz duty cycle 40% 60% differential voltage 0.4 1.0 v timing ostrp/n input: dacclkp/n rising edge latching setup time, ostrp/n valid to rising edge of t s(ostr) 200 ps dacclkp/n hold time, ostrp/n valid after rising edge of t h(ostr) 200 ps dacclkp/n cmos interface: alarm_sdo, sdio, sclk, sdenb, resetb, txenable v ih high-level input voltage 1.25 v v il low-level input voltage 0.54 v i ih high-level input current ? 40 40 m a i il low-level input current ? 40 40 m a c i cmos input capacitance 2 pf sdo, sdio iload = ? 100 m a digvdd18 ? 0.2 v v oh sdo, sdio iload = ? 2 ma 0.8 x digvdd18 v sdo, sdio iload = 100 m a 0.2 v v ol sdo, sdio iload = 2 ma 0.5 v (1) see lvds inputs section for terminology. (2) driving the clock input with a differential voltage lower than 1 v will result in degraded performance. copyright ? 2009 ? 2010, texas instruments incorporated submit documentation feedback 9 product folder link(s): dac3282
dac3282 slas646a ? december 2009 ? revised february 2010 www.ti.com electrical characteristics ? digital specifications (continued) over recommended operating free-air temperature range, nominal supplies, iout fs = 20 ma (unless otherwise noted) parameter test conditions min typ max unit serial port timing ? see figure 32 and figure 33 t s(sdenb) setup time, sdenb to rising edge of sclk 20 ns t s(sdio) setup time, sdio valid to rising edge of sclk 10 ns t h(sdio) hold time, sdio valid to rising edge of sclk 5 ns register config5 read (temperature 1 m s sensor read) t (sclk) period of sclk all other registers 100 ns register config5 read (temperature 0.4 m s sensor read) t (sclkh) high time of sclk all other registers 40 ns register config5 read (temperature 0.4 m s sensor read) t (sclkl) low time of sclk all other registers 40 ns t d(data) data output delay after falling edge of sclk 10 ns t reset minimum resetb pulsewidth 25 ns 10 submit documentation feedback copyright ? 2009 ? 2010, texas instruments incorporated product folder link(s): dac3282
dac3282 www.ti.com slas646a ? december 2009 ? revised february 2010 typical characteristics figure 1. integral non-linearity figure 2. differential non-linearity figure 3. sfdr vs input scale figure 4. sfdr vs interpolation copyright ? 2009 ? 2010, texas instruments incorporated submit documentation feedback 11 product folder link(s): dac3282 0 10000 20000 30000 40000 50000 60000 70000 code -5 -4 -3 -2 -1 0 1 2 3 4 5 error - lsb inl -5 -4 -3 -2 -1 0 1 2 3 4 5 error - lsb 0 10000 20000 30000 40000 50000 60000 70000 code dnl 0 20 40 60 80 100 120 1x interpolation 2x interpolation f = 312.5 msps, 0 dbfs, ioutfs = 20 ma dac 50 55 60 65 70 75 80 85 90 sfdr - spurious free dynamic range - dbc f out - output frequency - mhz 50 55 60 65 70 75 80 85 90 0 50 100 150 200 250 0 dbfs -6 dbfs -12 dbfs sfdr - spurious free dynamic range - dbc f - output frequency - mhz out f = 625 msps, 2x interpolation, ioutfs = 20 ma dac
dac3282 slas646a ? december 2009 ? revised february 2010 www.ti.com typical characteristics (continued) figure 5. sfdr vs f dac figure 6. sfdr vs i outfs figure 7. single tone spectral plot figure 8. single tone spectral plot 12 submit documentation feedback copyright ? 2009 ? 2010, texas instruments incorporated product folder link(s): dac3282 0 50 100 150 200 250 300 f - frequency - mhz -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 power - dbm 2x interpolation, 0 dbfs, f = 625 msps, = 10 mhz dac f out 20 ma 10 ma 2 ma 50 55 60 65 70 75 80 85 90 sfdr - spurious free dynamic range - dbc 0 50 100 150 200 250 f out - output frequency - mhz f = 625 msps, 2x interpolation, 0 dbfs dac 0 50 100 150 200 250 300 f - frequency - mhz -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 power - dbm 2x interpolation, 0 dbfs, f = 625 msps, f = 100 mhz dac out 50 55 60 65 70 75 80 f = 200 msps dac f = 600 msps dac f = 400 msps dac sfdr - spurious free dynamic range - dbc 0 50 100 150 200 250 f out - output frequency - mhz 2x interpolation, 0 dbfs,iouts = 20 ma
dac3282 www.ti.com slas646a ? december 2009 ? revised february 2010 typical characteristics (continued) figure 9. imd3 vs input scale figure 10. imd3 vs interpolation figure 11. imd3 vs f dac figure 12. imd3 vs i outfs copyright ? 2009 ? 2010, texas instruments incorporated submit documentation feedback 13 product folder link(s): dac3282 50 55 60 65 70 75 80 85 90 95 0 dbfs -6 dbfs -12 dbfs 0 50 100 150 200 250 f out - output frequency - mhz imd3 - dbc f = 625 msps, 2x interpolation, tones at f 0.5 mhz, ioutfs = 20 ma dac out 65 70 75 80 85 90 0 20 40 60 80 100 120 1x interpolation 2x interpolation f out - output frequency - mhz imd3 - dbc f = 312.5 msps, tones at f 0.5 mhz, 0 dbfs, ioutfs = 20 ma dac out 50 55 60 65 70 75 80 85 90 0 50 100 150 200 250 f = 200 msps dac f = 400 msps dac f = 600 msps dac 2x interpolation, tones at f 0.5 mhz, 0 dbfs, iouts = 20 ma out f out - output frequency - mhz imd3 - dbc 50 55 60 65 70 75 80 85 90 95 100 0 50 100 150 200 250 20 ma 10 ma 2 ma f = 625 msps, 2x interpolation, tones at f 0.5 mhz, 0 dbfs dac out imd3 - dbc f out - output frequency - mhz
dac3282 slas646a ? december 2009 ? revised february 2010 www.ti.com typical characteristics (continued) figure 13. nsd vs input scale figure 14. nsd vs interpolation figure 15. nsd vs f dac figure 16. nsd vs i outfs 14 submit documentation feedback copyright ? 2009 ? 2010, texas instruments incorporated product folder link(s): dac3282 130 135 140 145 150 155 160 165 170 f = 200 msps dac f = 400 msps dac f = 600 msps dac 0 50 100 150 200 250 f out - output frequency - mhz nsd - dbc/hz 2x interpolation, 0 dbfs,iouts = 20 ma 140 145 150 155 160 165 170 0 20 40 60 80 100 120 1x interpolation 2x interpolation f out - output frequency - mhz nsd - dbc/hz f = 312.5 msps, 0 dbfs, ioutfs = 20 ma dac 130 135 140 145 150 155 160 165 170 0 dbfs -6 dbfs -12 dbfs 0 50 100 150 200 250 f out - output frequency - mhz nsd - dbc/hz f = 625 msps, 2x interpolation, ioutfs = 20 ma dac 130 135 140 145 150 155 160 165 170 20 ma 10 ma 2 ma 0 50 100 150 200 250 f out - output frequency - mhz f = 625 msps, 2x interpolation 0 dbfs dac
dac3282 www.ti.com slas646a ? december 2009 ? revised february 2010 typical characteristics (continued) figure 17. single carrier wcdma aclr vs input scale figure 18. four carrier wcdma aclr vs input scale figure 19. single carrier w-cdma test model 1, f out = 70 mhz figure 20. single carrier w-cdma test model 1, f out = 153.6 mhz copyright ? 2009 ? 2010, texas instruments incorporated submit documentation feedback 15 product folder link(s): dac3282 a ref -14.4 dbm * * * clrwr rbw 30 khz vbw 300 khz swt 10 s att 10 db * 1 rm nor * center 153.6 mhz span 20 mhz 2 mhz/ ext -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 tx channel w-cdma 3gpp fwd bandwidth 3.84 mhz power -8.89 dbm adjacent channel bandwidth 3.84 mhz lower -76.86 db spacing 5 mhz upper -76.18 db 2x interpolation, 0 dbfs, f = 491.52 msps, f = 153.6 mhz dac out 65 70 75 80 85 90 adjacent 0 dbfs adjacent -6 dbfs alternate 0 dbfs alternate -6 dbfs 0 50 100 150 200 250 f out - output frequency - mhz aclr - dbc f = 491.52 msps, 2x interpolation, ioutfs = 20 ma dac e x t t x c h a n n e l w - c d m a 3 g p p f w d b a n d w i d t h 3 . 8 4 m h z p o w e r - 7 . 6 2 d b m a d j a c e n t c h a n n e l b a n d w i d t h 3 . 8 4 m h z l o w e r - 7 8 . 8 9 d b s p a c i n g 5 m h z u p p e r - 7 8 . 8 3 d b a n o r c e n t e r 7 0 m h z s p a n 2 0 m h z 2 m h z / r e f - 1 3 d b m * c l r w r * * r b w 3 0 k h z v b w 3 0 0 k h z s w t 1 0 s a t t 1 5 d b * 1 r m * - 1 3 0 - 1 2 0 - 1 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 2x interpolation, 0 dbfs, f = 491.52 msps, f = 70 mhz dac out 55 60 65 70 75 80 aclr, 0 dbfs aclr -6 dbfs aternate, 0 dbfs alternate, -6 dbfs 0 50 100 150 200 250 f out - output frequency - mhz aclr - dbc f = 491.52 msps, 2x interpolation ioutfs = 20 ma dac
dac3282 slas646a ? december 2009 ? revised february 2010 www.ti.com typical characteristics (continued) figure 21. four carrier w-cdma test model 1, f out = 70 mhz figure 22. four carrier w-cdma test model 1, f out = 153.6 mhz figure 23. 10mhz single carrier lte, f out = 70 mhz figure 24. 10mhz single carrier lte, f out = 153.6 mhz 16 submit documentation feedback copyright ? 2009 ? 2010, texas instruments incorporated product folder link(s): dac3282 a ref -18 dbm * * * clrwr rbw 30 khz vbw 300 khz swt 10 s att 10 db * 1 rm nor * center 70 mhz span 35 mhz 3.5 mhz/ ext -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 standard: w-cdma 3gpp fwd tx channels ch1 -14.16 dbm (ref) ch2 -14.20 dbm ch3 -14.34 dbm ch4 -14.39 dbm total -8.25 dbm adjacent channel lower -74.09 db upper -74.14 db 2x interpolation, 0 dbfs, f = 491.52 msps, f = 70 mhz dac out ref -17.3 dbm rbw 30 khz vbw 300 khz swt 10 s clrwr a * * * att 10 db * 1 rm nor * center 70 mhz span 35 mhz 3.5 mhz/ ext -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 tx channel bandwidth 10 mhz power -8.39 dbm adjacent channel bandwidth 10 mhz lower -74.18 db spacing 10 mhz upper -70.40 db 2x interpolation, 0 dbfs, f = 491.52 msps, f = 70 mhz dac out a ref -18.3 dbm * * * clrwr rbw 30 khz vbw 300 khz swt 10 s att 10 db * 1 rm nor * center 153.6 mhz span 35 mhz 3.5 mhz/ ext -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 tx channel bandwidth 10 mhz power -9.49 dbm adjacent channel bandwidth 10 mhz lower -71.66 db spacing 10 mhz upper -69.13 db 2x interpolation, 0 dbfs, f = 491.52 msps, f = 153.6 mhz dac out a ref -19.7 dbm * * * clrwr rbw 30 khz vbw 300 khz att 10 db * 1 rm center 153.6 mhz span 35 mhz 3.5 mhz/ ext nor swt 10 s * -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 standard: w-cdma 3gpp fwd tx channels ch1 -15.80 dbm (ref) ch2 -15.92 dbm ch3 -16.08 dbm ch4 -16.21 dbm total -9.98 dbm adjacent channel lower -70.59 db upper -69.18 db 2x interpolation, 0 dbfs, f = 491.52 msps, f = 153.6 mhz dac out
dac3282 www.ti.com slas646a ? december 2009 ? revised february 2010 typical characteristics (continued) figure 25. 20mhz single carrier lte, f out = 70 mhz figure 26. 20mhz single carrier lte, f out = 153.6 mhz figure 27. power vs f data figure 28. dvdd18 vs f data copyright ? 2009 ? 2010, texas instruments incorporated submit documentation feedback 17 product folder link(s): dac3282 a * * * clrwr rbw 30 khz vbw 300 khz swt 10 s ref -18.8 dbm att 15 db * 1 rm nor * center 70 mhz span 65 mhz 6.5 mhz/ ext -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 tx channel bandwidth 20 mhz power -7.17 dbm adjacent channel bandwidth 20 mhz lower -65.69 db spacing 20 mhz upper -67.79 db 2x interpolation, 0 dbfs, f = 491.52 msps, f = 70 mhz dac out a ref -18 dbm clrwr * * * rbw 30 khz vbw 300 khz swt 10 s att 10 db * 1 rm nor * center 153.6 mhz span 65 mhz 6.5 mhz/ ext -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 tx channel bandwidth 20 mhz power -8.23 dbm adjacent channel bandwidth 20 mhz lower -65.14 db spacing 20 mhz upper -64.96 db 2x interpolation, 0 dbfs, f = 491.52 msps, f = 153.6 mhz dac out 0 50 100 150 200 250 300 1x 1x+invsinc 2x 2x+invsinc 2x+coarse_mix 0 50 100 150 200 250 300 350 f - msps data dvdd18 - ma 1x 1x+invsinc 2x 2x+invsinc 2x+coarse_mix 0 50 100 150 200 250 300 350 f - msps data 400 500 600 700 800 900 1000 power - mw
dac3282 slas646a ? december 2009 ? revised february 2010 www.ti.com typical characteristics (continued) figure 29. dacvdd18 vs f dac figure 30. clkvdd18 vs f dac figure 31. avdd33 vs f dac 18 submit documentation feedback copyright ? 2009 ? 2010, texas instruments incorporated product folder link(s): dac3282 0 2 4 6 8 10 12 14 16 18 20 0 100 200 300 400 500 600 clkvdd18 - ma f - msps dac 0 10 20 30 40 50 60 70 80 90 100 0 100 200 300 400 500 600 coarse_mix on coarse_mix off dacvdd - ma f - msps dac 0 20 40 60 80 100 120 0 100 200 300 400 500 600 avdd33 - ma f - msps dac
dac3282 www.ti.com slas646a ? december 2009 ? revised february 2010 definition of specifications adjacent carrier leakage ratio (aclr): defined for a 3.84mcps 3gpp w-cdma input signal measured in a 3.84mhz bandwidth at a 5mhz offset from the carrier with a 12db peak-to-average ratio. analog and digital power supply rejection ratio (apssr, dpssr): defined as the percentage error in the ratio of the delta iout and delta supply voltage normalized with respect to the ideal iout current. differential nonlinearity (dnl): defined as the variation in analog output associated with an ideal 1 lsb change in the digital input code. gain drift: defined as the maximum change in gain, in terms of ppm of full-scale range (fsr) per c, from the value at ambient (25 c) to values over the full operating temperature range. gain error: defined as the percentage error (in fsr%) for the ratio between the measured full-scale output current and the ideal full-scale output current. integral nonlinearity (inl): defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full scale. intermodulation distortion (imd3): the two-tone imd3 is defined as the ratio (in dbc) of the 3rd-order intermodulation distortion product to either fundamental output tone. offset drift: defined as the maximum change in dc offset, in terms of ppm of full-scale range (fsr) per c, from the value at ambient (25 c) to values over the full operating temperature range. offset error: defined as the percentage error (in fsr%) for the ratio between the measured mid-scale output current and the ideal mid-scale output current. output compliance range: defined as the minimum and maximum allowable voltage at the output of the current-output dac. exceeding this limit may result reduced reliability of the device or adversely affecting distortion performance. reference voltage drift: defined as the maximum change of the reference voltage in ppm per c from value at ambient (25 c) to values over the full operating temperature range. spurious free dynamic range (sfdr): defined as the difference (in dbc) between the peak amplitude of the output signal and the peak spurious signal. signal to noise ratio (snr): defined as the ratio of the rms value of the fundamental output signal to the rms sum of all other spectral components below the nyquist frequency, including noise, but excluding the first six harmonics and dc. copyright ? 2009 ? 2010, texas instruments incorporated submit documentation feedback 19 product folder link(s): dac3282
dac3282 slas646a ? december 2009 ? revised february 2010 www.ti.com application information serial interface the serial port of the dac3282 is a flexible serial interface which communicates with industry standard microprocessors and microcontrollers. the interface provides read/write access to all registers used to define the operating modes of dac3282. it is compatible with most synchronous transfer formats and can be configured as a 3 or 4 pin interface by sif4_ena in register config23 . in both configurations, sclk is the serial interface input clock and sdenb is serial interface enable. for 3 pin configuration, sdio is a bidirectional pin for both data in and data out. for 4 pin configuration, sdio is data in only and alarm_sdo is data out only. data is input into the device with the rising edge of sclk. data is output from the device on the falling edge of sclk. each read/write operation is framed by signal sdenb (serial data enable bar) asserted low for 2 to 5 bytes, depending on the data length to be transferred (1 ? 4 bytes). the first frame byte is the instruction cycle which identifies the following data transfer cycle as read or write, how many bytes to transfer, and what address to transfer the data. table 1 indicates the function of each bit in the instruction cycle and is followed by a detailed description of each bit. frame bytes 2 to 5 comprise the data transfer cycle. table 1. instruction byte of the serial interface msb lsb bit 7 6 5 4 3 2 1 0 description r/w n1 n0 a4 a3 a2 a1 a0 r/w identifies the following data transfer cycle as a read or write operation. a high indicates a read operation from dac3282 and a low indicates a write operation to dac3282. [n1 : n0] identifies the number of data bytes to be transferred per table 2 . data is transferred msb first. table 2. number of transferred bytes within one communication frame n1 n0 description 0 0 transfer 1 byte 0 1 transfer 2 bytes 1 0 transfer 3 bytes 1 1 transfer 4 bytes [a4 : a0] identifies the address of the register to be accessed during the read or write operation. for multi-byte transfers, this address is the starting address. note that the address is written to the dac3282 msb first and counts down for each byte. figure 32 shows the serial interface timing diagram for a dac3282 write operation. sclk is the serial interface clock input to dac3282. serial data enable sdenb is an active low input to dac3282. sdio is serial data in. input data to dac3282 is clocked on the rising edges of sclk. 20 submit documentation feedback copyright ? 2009 ? 2010, texas instruments incorporated product folder link(s): dac3282
dac3282 www.ti.com slas646a ? december 2009 ? revised february 2010 figure 32. serial interface write timing diagram figure 33 shows the serial interface timing diagram for a dac3282 read operation. sclk is the serial interface clock input to dac3282. serial data enable sdenb is an active low input to dac3282. sdio is serial data in during the instruction cycle. in 3 pin configuration, sdio is data out from dac3282 during the data transfer cycle(s), while alarm_sdo is in a high-impedance state. in 4 pin configuration, alarm_sdo is data out from dac3282 during the data transfer cycle(s). at the end of the data transfer, alarm_sdo will output low on the final falling edge of sclk until the rising edge of sdenb when it will 3-state. figure 33. serial interface read timing diagram copyright ? 2009 ? 2010, texas instruments incorporated submit documentation feedback 21 product folder link(s): dac3282 rwb n1 n0 - a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 instruction cycle data transfer cycle t s ( sdenb ) t s ( sdio ) t h ( sdio ) t sclk t sclkh t sclkl sdenb sclk sdio sdenb sclk sdio rwb n1 n0 - a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 instruction cycle data transfer cycle t d (data) sdenbsclk sdio sdenb sclk sdio or alarm_sdo d7 d6 d5 d4 d3 d2 d1 d0 alarm_ sdo data n data n-1 3-pin interface 4-pin interface
dac3282 slas646a ? december 2009 ? revised february 2010 www.ti.com register descriptions register map table 3. register map (msb) (lsb) name address default bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 7 bit 0 config0 0x00 0x70 qmc_offset_ena fifo_ena fifo_reset_ena multi_sync_ena alarm_out_ena alarm_pol mixer_func(1:0) config1 0x01 0x11 unused unused unused fir_ena fir4_ena iotest_ena unused twos config2 0x02 0x00 unused unused unused unused output_delay(3:0) alarm_ alarm_ config3 0x03 0x10 64cnt_ena unused unused fifo_offset(2:0) 2away_ena 1away_ena config4 0x04 0xff coarse_daca(3:0) coarse_dacb(3:0) config5 0x05 n/a tempdata(7:0) config6 0x06 0x00 unused alarm_mask(6:0) alarm_from_ alarm_fifo_ alarm_fifo_ alarm_fifo_ config7 0x07 0x00 unused reserved alarm_from_ iotest unused zerochk collision 2away 1away config8 0x08 0x00 iotest_results(7:0) config9 0x09 0x7a iotest_pattern0(7:0) config10 0x0a 0xb6 iotest_pattern1(7:0) config11 0x0b 0xea iotest_pattern2(7:0) config12 0x0c 0x45 iotest_pattern3(7:0) config13 0x0d 0x1a iotest_pattern4(7:0) config14 0x0e 0x16 iotest_pattern5(7:0) config15 0x0f 0xaa iotest_pattern6(7:0) config16 0x10 0xc6 iotest_pattern7(7:0) config17 0x11 0x00 reserved reserved reserved reserved daca_ dacb_ clkdiv_ config18 0x12 0x02 reserved reserved unused complement complement sync_ena multi_ config19 0x13 0x00 bequalsa aequalsb reserved unused unused unused rev sync_sel config20 0x14 0x00 qmc_offseta(7:0) config21 0x15 0x00 qmc_offsetb(7:0) config22 0x16 0x00 qmc_offseta(12:8) unused unused unused clkpath_ clkpath_ config23 0x17 0x00 qmc_offsetb(12:8) sif4_ena sleep_a sleep_b config24 0x18 0x83 tsense_ena clkrecv_sleep unused reserved sleepb sleepa reserved reserved config25 0x19 0x00 reserved extref_ena reserved reserved config26 0x1a 0x00 unused unused unused unused unused reserved config27 0x1b 0x00 reserved config28 0x1c 0x00 reserved config29 0x1d 0x00 reserved config30 0x1e 0x00 reserved version31 0x1f 0x43 deviceid(1:0) version(5:0) 22 submit documentation feedback copyright ? 2009 ? 2010, texas instruments incorporated product folder link(s): dac3282
dac3282 www.ti.com slas646a ? december 2009 ? revised february 2010 register name: config0 ? address: 0x00, default: 0x70 register default address bit name function name value config0 0x00 7 qmc_offset_ena when asserted the dac offset correction is enabled. 0 when asserted the fifo is enabled. when the fifo is bypassed 6 fifoin_ena 1 daccclkp/n and dataclkp/n must be aligned to within t _align . 5 fifo_reset_ena allows the frame input to act as a fifo write reset when asserted.. 1 allows the frame or ostr signals to be used as a sync signal when 4 multi_sync_ena asserted. 1 this selection is determined by multi_sync_sel in register config19. when asserted the alarm_sdo pin becomes an output. the 3 alarm_out_ena functionality of this pin is controlled by the config6 alarm_mask 0 setting. this bit changes the polarity of the alarm signal. (0=negative logic, 2 alarm_pol 0 1=positive 1:0 mixer_func(1:0) controls the function of the mixer block. 00 mode mixer_func(1:0) normal 00 high pass(fs/2) 01 fs/4 10 ? fs/4 11 register name: config1 ? address: 0x01, default: 0x11 register default address bit name function name value config1 0x01 7 unused reserved for factory use. 0 6 unused reserved for factory use. 0 5 unused reserved for factory use. 0 4 fir_ena when asserted the chip does 2x interpolation of the data. 1 when asserted, the zero-if sinc correction filter is enabled. this filter 3 fir4_ena 0 cannot be used unless fir_ena is asserted. 2 iotest_ena when asserted enables the data pattern checker operation. 0 1 unused reserved for factory use. 0 when asserted the inputs are expected to be in 2 ? s complement 0 twos format. when de-asserted the input format is expected to be 1 offset-binary. register name: config2 ? address: 0x02, default: 0x00 register default address bit name function name value config2 0x02 7 unused reserved for factory use. 0 6 unused reserved for factory use. 0 5 unused reserved for factory use. 0 4 unused reserved for factory use. 0 3:0 output_delay(3:0) delays the output to the dacs from 0 to 15 dac clock cycles. 0000 copyright ? 2009 ? 2010, texas instruments incorporated submit documentation feedback 23 product folder link(s): dac3282
dac3282 slas646a ? december 2009 ? revised february 2010 www.ti.com register name: config3 ? address: 0x03, default: 0x10 register default address bit name function name value config1 0x00 7 64cnt_ena this enables resetting the alarms after 64 good samples with the goal of removing unnecessary errors. for instance, when checking setup/hold through the pattern checker test, there may initially be 0 errors. setting this bit removes the need for a sif write to clear the alarm register. 6 unused reserved for factory use. 0 5 unused reserved for factory use. 0 when the fifo is reset, this is the value loaded into the fifo read pointer. with this value the initial difference between write and read 4:2 fifo_offset(2:0) 100 pointers can be controlled. this may be helpful in controlling the delay through the device. when asserted alarms from the fifo that represent the write and read 1 alarm_2away_ena 0 pointers being 2 away are enabled. when asserted alarms from the fifo that represent the write and read 0 alarm_1away_ena 0 pointers being 1 away are enabled. register name: config4 ? address: 0x04, default: 0xff register default address bit name function name value config4 0x04 7:4 coarse_daca(3:0) scales the output current in 16 equal steps. 1111 3:0 coarse_dacb(3:0) scales the output current in 16 equal steps. 1111 register name: config5 ? address: 0x05, read only register default address bit name function name value config5 0x05 7:0 tempdata(7:0) this is the output from the chip temperature sensor. the value of this register in two ? s complement format represents the temperature in n/a degrees celsius. this register must be read with a minimum sclk period of 1 m s . (read only) register name: config6 ? address: 0x06, default: 0x00 register default address bit name function name value config6 0x06 7 unused reserved for factory use. 0 6:0 alarm_mask(6:0) these bits control the masking of the alarm outputs. this means that the 0000000 alarm_sdo pin will not be asserted if the appropriate bit is set. the alarm will still show up in the config7 bits. (0=not masked, 1= masked). alarm_mask masked alarm 6 alarm_from_zerochk 5 alarm_fifo_collision 4 reserved 3 alarm_from_iotest 2 not used (expansion) 1 alarm_fifo_2away 0 alarm_fifo_1away 24 submit documentation feedback copyright ? 2009 ? 2010, texas instruments incorporated product folder link(s): dac3282 ( ) extio v coarse_daca/b+1 rbias
dac3282 www.ti.com slas646a ? december 2009 ? revised february 2010 register name: config7 ? address: 0x07, default: 0x00 (write to clear) register default address bit name function name value config7 0x07 7 unused reserved for factory use. 0 6 alarm_from_ zerochk when this bit is asserted the fifo write pointer has an all zeros 0 pattern in it. since this pointer is a shift register, all zeros will cause the input point to be stuck until the next sync. this alarm allows checking for this condition. 5 alarm_fifo_ collision alarm occurs when the fifo pointers over/under run each other. 0 4 reserved reserved for factory use. 0 this is asserted when the input data pattern does not match the 3 alarm_from_ iotest 0 pattern in the iotest_pattern registers. 2 unused reserved for factory use. 0 alarm occurs with the read and write pointers of the fifo are 1 alarm_fifo_ 2away 0 within 2 addresses of each other. alarm occurs with the read and write pointers of the fifo are 0 alarm_fifo_ 1away 0 within 1 address of each other. register name: config8 ? address: 0x08, default: 0x00 (write to clear) register default address bit name function name value config8 0x08 7:0 iotest_results(7:0) the values of these bits tell which bit in the word failed during the 0x00 pattern checker test. register name: config9 ? address: 0x09, default: 0x7a register default address bit name function name value config9 0x09 7:0 iotest_pattern0(7:0) this is dataword0 in the io test pattern. it is used with the seven 0x7a other words to test the input data. register name: config10 ? address: 0x0a, default: 0xb6 register default address bit name function name value config10 0x0a 7:0 iotest_pattern1(7:0) this is dataword1 in the io test pattern. it is used with the seven 0xb6 other words to test the input data. register name: config11 ? address: 0x0b, default: 0xea register default address bit name function name value config11 0x0b 7:0 iotest_pattern2(7:0) this is dataword2 in the io test pattern. it is used with the seven 0xea other words to test the input data. register name: config12 ? address: 0x0c, default: 0x45 register default address bit name function name value config12 0x0c 7:0 iotest_pattern3(7:0) this is dataword3 in the io test pattern. it is used with the seven 0x45 other words to test the input data. copyright ? 2009 ? 2010, texas instruments incorporated submit documentation feedback 25 product folder link(s): dac3282
dac3282 slas646a ? december 2009 ? revised february 2010 www.ti.com register name: config13 ? address: 0x0d, default: 0x1a register default address bit name function name value config13 0x0d 7:0 iotest_pattern4(7:0) this is dataword4 in the io test pattern. it is used with the seven 0x1a other words to test the input data. register name: config14 ? address: 0x0e, default: 0x16 register default address bit name function name value config14 0x0e 7:0 iotest_pattern5(7:0) this is dataword5 in the io test pattern. it is used with the seven 0x16 other words to test the input data. register name: config15 ? address: 0x0f, default: 0xaa register default address bit name function name value config15 0x0f 7:0 iotest_pattern6(7:0) this is dataword6 in the io test pattern. it is used with the seven 0xaa other words to test the input data. register name: config16 ? address: 0x10, default: 0xc6 register default address bit name function name value config16 0x10 7:0 iotest_pattern7(7:0) this is dataword7 in the io test pattern. it is used with the seven 0xc6 other words to test the input data. register name: config17 ? address: 0x11, default: 0x00 register default address bit name function name value config17 0x11 7:6 reserved reserved for factory use. 00 5 reserved reserved for factory use. 0 4 reserved reserved for factory use. 0 3:0 reserved reserved for factory use. 0000 register name: config18 ? address: 0x12, default: 0x02 register default address bit name function name value config18 0x12 7:5 reserved reserved for factory use. 000 4 reserved reserved for factory use. 0 3 daca_complement when asserted the output to the daca is complemented. this allows to effectively change the + and ? designations of the 0 lvds data lines. 2 dacb_complement when asserted the output to the dacb is complemented. this allows to effectively change the + and ? designations of the 0 lvds data lines. 1 clkdiv_sync_ena enables the syncing of the clock divider using the ostr signal or the frame signal passed through the fifo. this selection is 1 determined by multi_sync_sel in register config19. syncing of the clock divider should be done only during device initialization. 0 unused reserved for factory use. 0 26 submit documentation feedback copyright ? 2009 ? 2010, texas instruments incorporated product folder link(s): dac3282
dac3282 www.ti.com slas646a ? december 2009 ? revised february 2010 register name: config19 ? address: 0x13, default: 0x00 register default address bit name function name value config 0x13 7 bequalsa when asserted the daca data is driven onto dacb. 0 19 6 aequalsb when asserted the dacb data is driven onto daca. 0 5 reserved reserved for factory use. 0 4 unused reserved for factory use. 0 3 unused reserved for factory use. 0 2 unused reserved for factory use. 0 1 multi_sync_sel selects the signal source for multiple device and clock divider synchronization. 0 multit_sync_sel sync source 0 ostr 1 frame through fifo handoff 0 rev reverse the input bits for the data word. msb becomes lsb. 0 register name: config20 ? address: 0x14, default: 0x00 (causes autosync) register default address bit name function name value config20 0x14 7:0 qmc_offseta(7:0) lower 8 bits of the dac a offset correction. the offset is measured in 0x00 dac lsbs. writing this register causes an autosync to be generated. this loads the values of all four qmc_offset registers (config20-config23) into the offset block at the same time. when updating the offset values config20 should be written last. programming any of the other three registers will not affect the offset setting. register name: config21 ? address: 0x15, default: 0x00 register default address bit name function name value config21 0x15 7:0 qmc_offsetb(7:0) lower 8 bits of the dac b offset correction. the offset is measured in 0x00 dac lsbs. register name: config22 ? address: 0x16, default: 0x00 register default address bit name function name value config22 0x16 7:3 qmc_offseta(12:8 upper 5 bits of the dac a offset correction. 00000 ) 2 unused reserved for factory use. 0 1 unused reserved for factory use. 0 0 unused reserved for factory use. 0 copyright ? 2009 ? 2010, texas instruments incorporated submit documentation feedback 27 product folder link(s): dac3282
dac3282 slas646a ? december 2009 ? revised february 2010 www.ti.com register name: config23 ? address: 0x27, default: 0x00 register default address bit name function name value config23 0x17 7:3 qmc_offsetb(12:8) upper 5 bits of the dac b offset correction. 00000 2 sif4_ena when asserted the sif interface becomes a 4 pin interface. the 0 alarm_sdo pin is turned into a dedicated output for the reading of data. 1 clkpath_sleep_a when asserted puts the clock path through dac a to sleep. this is 0 useful for sleeping individual dacs. even if the dac is asleep the clock needs to pass through it for the logic to work. however, if the chip is being put into a power down mode, then all parts of the dac can be turned off. 0 clkpath_sleep_b when asserted puts the clock path through dac b to sleep. 0 register name: config24 ? address: 0x18, default: 0x83 register default address bit name function name value config24 0x18 7 tsense_ena turns on the temperature sensor when asserted. 1 6 clkrecv_sleep when asserted the clock input receiver gets put into sleep mode. 0 this also affects the ostr receiver. 5 unused reserved for factory use. 0 4 reserved reserved for factory use. 0 3 sleepb when asserted dacb is put into sleep mode. 0 2 sleepa when asserted daca is put into sleep mode. 0 1 reserved reserved for factory use. 1 0 reserved reserved for factory use. 1 register name: config25 ? address: 0x19, default: 0x00 register default address bit name function name value config25 0x19 7:3 reserved reserved for factory use. 00000 2 extref_ena allows the device to use an external reference or the internal 0 reference. (0=internal, 1=external) 1 reserved reserved for factory use. 0 0 reserved reserved for factory use. 0 register name: config26 ? address: 0x1a, default: 0x00 register default address bit name function name value config26 0x1a 7 unused reserved for factory use. 0 6 unused reserved for factory use. 0 5 unused reserved for factory use. 0 4 unused reserved for factory use. 0 3 unused reserved for factory use. 0 2:0 reserved reserved for factory use. 000 register name: config27 ? address: 0x1b, default: 0x00 register default address bit name function name value config27 0x1b 7:0 reserved reserved for factory use. 0x00 28 submit documentation feedback copyright ? 2009 ? 2010, texas instruments incorporated product folder link(s): dac3282
dac3282 www.ti.com slas646a ? december 2009 ? revised february 2010 register name: config28 ? address: 0x1c, default: 0x00 register default address bit name function name value config28 0x1c 7:0 reserved reserved for factory use. 0x00 register name: config29 ? address: 0x1d, default: 0x00 register default address bit name function name value config29 0x1d 7:0 reserved reserved for factory use. 0x00 register name: config30 ? address: 0x1e, default: 0x00 register default address bit name function name value config30 0x1e 7:0 reserved reserved for factory use. 0x00 register name: version31 ? address: 0x1f, default: 0x43 (read only) register default address bit name function name value version31 0x1f 7:0 deviceid(1:0) returns ? 01 ? for dac3282. (read only) 01 5:0 version(5:0) a hardwired register that contains the version of the chip. (read only) 000011 copyright ? 2009 ? 2010, texas instruments incorporated submit documentation feedback 29 product folder link(s): dac3282
dac3282 slas646a ? december 2009 ? revised february 2010 www.ti.com functional description data interface the dac3282 has a single 8-bit lvds bus that accepts dual, 16-bit data input in byte-wide format. data into the dac3282 is formatted according to the diagram shown in figure 34 where index 0 is the data lsb and index 15 is the data msb. the data is sampled by dataclk, a double data rate (ddr) clock. the frame signal is required to indicate the beginning of a frame. the frame signal can be either a pulse or a periodic signal where the frame period corresponds to 8 samples. the pulse-width (t (frame) ) needs to be at least equal to 1/2f the dataclk period. frame is sampled by a rising edge in dataclk. the setup and hold requirements listed in the specifications tables must be met to ensure proper sampling. figure 34. byte-wide data transmission format input fifo the dac3282 includes a 2-channel, 16-bits wide and 8-samples deep input fifo which acts as an elastic buffer. the purpose of the fifo is to absorb any timing variations between the input data and the internal dac data rate clock such as the ones resulting from clock-to-data variations from the data source. figure 35 shows the block diagram of the fifo. figure 35. dac3282 fifo block diagram data is written to the device 8-bits at a time on the rising and falling edges of dataclk. in order to form a complete 32-bit wide sample (16-bit i-data and 16-bit q-data) two dataclk periods are required as shown in 30 submit documentation feedback copyright ? 2009 ? 2010, texas instruments incorporated product folder link(s): dac3282 frame align 0 1 2 3 4 5 6 7 frame d[7:0] 0 7 write pointer fifo i outputfifo q output clock handoff input side clocked by dataclk output side clocked by fifo out clock (dacclk/interpolation factor ) fifo: 2 x 16-bits wide 8-samples deep 0 1 2 3 4 5 6 7 sample 0 i 0 [15:0], q 0 [15:0] sample 2 i 2 [15:0], q 2 [15:0] sample 3 i 3 [15:0], q 3 [15:0] sample 4 i 4 [15:0], q 4 [15:0] sample 5 i 5 [15:0], q 5 [15:0] sample 6 i 6 [15:0], q 6 [15:0] sample 7 i 7 [15:0], q 7 [15:0] sample 1 i 1 [15:0], q 1 [15:0] initial position 0 7 read pointer initial position 32-bit 32-bit i-data, 16-bit q-data, 16-bit 16-bit 16-bit data[15:8] data[7:0] x2 two cycles, one for i-data and another for q-data 8-bit 8-bit write pointer reset read pointer reset dataclkp /n (ddr) framep/n d[7:0]p/n sample 0 sample 1 t (frame) i 0 [15:8] i 0 [7:0] q 0 [15:8] q 0 [7:0] i 1 [15:8] i 1 [7:0] q 1 [15:8] q 1 [7:0]
dac3282 www.ti.com slas646a ? december 2009 ? revised february 2010 figure 36 . each 32-bit wide sample is written into the fifo at the address indicated by the write pointer. similarly, data from the fifo is read by the fifo out clock 32-bits at a time from the address indicated by the read pointer. the fifo out clock is generated internally from the dacclk signal and its rate is equal to dacclk/interpolation. each time a fifo write or fifo read is done the corresponding pointer moves to the next address. the reset position for the fifo read and write pointers is set by default to addresses 0 and 4 as shown in figure 35 . this offset gives optimal margin within the fifo. the default read pointer location can be set to another value using fifo_offset(2:0) in register config3. under normal conditions data is written-to and read-from the fifo at the same rate and consequently the write and read pointer gap remains constant. if the fifo write and read rates are different, the corresponding pointers will be cycling at different speeds which could result in pointer collision. under this condition the fifo attempts to read and write data from the same address at the same time which will result in errors and thus must be avoided. the frame signal besides acting as a frame indicator can also used to reset the fifo pointers to their initial location. unlike data, the frame signal is latched only on the rising edges of dataclk. when a rising edge occurs on frame, the pointers will return to their original position. the write pointer is always set back to position 0 upon reset. the read pointer reset position is determined by fifo_offset (address 4 by default). the reset can be done periodically or only once during initialization as the pointer automatically returns to the initial position when the fifo has been filled. to enable a single reset, fifo_reset_ena (config0, bit 5) must be set to 0 after initialization. figure 36. fifo write description fifo alarms the fifo only operates correctly when the write and read pointers are positioned properly. if either pointer over or under runs the other, samples will be duplicated or skipped. to prevent this, register config7 can be used to track three fifo related alarms: ? alarm_fifo_2away. occurs when the pointers are within two addresses of each other. ? alarm_fifo_1away. occurs when the pointers are within one address of each other. ? alarm_fifo_collision. occurs when the pointers are equal to each other. these three alarm events are generated asynchronously with respect to the clocks and can be accessed either through config7 or through the alarm_sdo pin. fifo modes of operation the dac3282 fifo can be completely bypassed through register config0. the register configuration for each mode is described in table 4 . register control bits config0 fifo_ena, fifo_reset_ena, multi_sync_ena copyright ? 2009 ? 2010, texas instruments incorporated submit documentation feedback 31 product folder link(s): dac3282 i 4 [15:8] i 4 [7:0] q 4 [15:8] q 4 [7:0] q 3 [7:0] i 5 [7:0] q 5 [15:8] q 5 [7:0] i 5 [15:8] i 6 [7:0] q 6 [15:8] i 6 [15:8] q 6 [7:0] i 7 [15:8] i 7 [7:0] q 7 [15:8] q 3 [15:8] d[7:0]p/n dataclkp /n (ddr) framep/n resets write pointer to position 0 lvds pairs (data source) write i 4 [15:8] (8-bits) to dac on rising edge write i 4 [7:0] (8-bits) to dac on falling edge write q 4 [15:8] (8-bits) to dac on rising edge write q 4 [7:0] (8-bits) to dac on falling edge write sample 4 to fifo (32-bits) t s(data ) t h(data ) t s(data ) t h(data ) t s(data ) t h(data )
dac3282 slas646a ? december 2009 ? revised february 2010 www.ti.com table 4. fifo operation modes config0 fifo bits fifo mode fifo_ena fifo_reset_ena multi_sync_ena enabled 1 1 1 bypass 0 x x enabled mode this is the recommended mode of operation for the dac3282. in fifo enabled mode, the fifo is active and can be reset continuously or only once during initialization. to reset only once, fifo_reset_ena must be set to 0 after initialization. bypass mode in fifo bypass mode, the fifo block is not used. as a result the input data is handed off from the dataclk to the dacclk domain without any compensation. in this mode the relationship between dataclk and dacclk (t _align ) is critical and used as a synchronizing mechanism for the internal logic. due to the t _align constraint it is highly recommended that a clock synchronizer device such as texas instruments ? cdcm7005 or cdce62005 is used to provide both clock inputs. in bypass mode the pointers have no effect on the data path or handoff. data pattern checker the dac3282 incorporates a simple pattern checker test in order to determine errors in the data interface. the test mode is enabled by asserting iotest_ena in register config1. in test mode the analog outputs are deactivated regardless of the state of txenable. the data pattern key used for the test is 8 words long and is specified by the contents of iotest_pattern[0:7] in registers config9 through config16. the data pattern key can be modified by changing the contents of these registers. the first word in the test frame is determined by a rising edge transition in framep/n. the test mode determines if one or more words were received incorrectly by comparing the received data against the data pattern key. the bits in iotest_results(7:0) in register config8 indicate which words were received incorrectly. furthermore, an error condition will trigger the alarm_from_iotest bit in register config7. once set, the alarm_from_iotest bit must be reset through the serial interface to allow further testing. alternatively, the 64cnt_ena bit in register config3 can be enabled to reset the alarms automatically after 64 good samples without the need for a sif write to clear the alarm. fir filters the dac3282 has two fir filters, a 2x interpolation fir (fir0) and a non-interpolating fir (fir4) that compensates for the sinc droop of the dac on zero-if applications. the correction filter is placed before the interpolating filter and can only be used with both firs enabled. figure 37 shows the magnitude spectrum response for fir0, a 59-tap interpolating half-band filter. the transition band is from 0.4 to 0.6 f in (the input data rate for the fir filter) with < 0.002db of pass-band ripple and > 85 db stop-band attenuation. figure 38 shows the transition band region from 0.36 to 0.46 f in . up to 0.45 f in there is less than 0.5 db of attenuation. the dac sample and hold operation results in the well known sin(x)/x or sinc(x) frequency response shown in figure 39 (red line). the dac3282 has a 5-tap inverse sinc filter (fir4) placed before the 2x interpolation filter to compensate for this effect up to 0.2 f dac . the inverse sinc filter runs at the input data rate and is operational only if the 2x interpolation filter is enabled as well, correspondingly the rate of this filter is always half of the dac update rate. as a result, the filter cannot completely flatten the frequency response of the sample and hold output as shown in figure 39 . figure 40 shows the magnitude spectrum for fir4 over the correction range. the inverse sinc filter response ( figure 40 , black line) has approximately the opposite frequency response to sin(x)/x between 0 to 0.2 x f dac , resulting in the corrected response in figure 40 (blue line). between 0 to 0.2 f dac , the inverse sinc filter compensates for the sample and hold roll-off with less than 0.04-db error. 32 submit documentation feedback copyright ? 2009 ? 2010, texas instruments incorporated product folder link(s): dac3282
dac3282 www.ti.com slas646a ? december 2009 ? revised february 2010 the zero-if sinc filter has a gain > 1 at all frequencies. therefore, the input data must be reduced from full scale to prevent saturation in the filter. the amount of back-off required depends on the signal frequency, and is set such that at the signal frequencies the combination of the input signal and filter response is less than 1 (0 db). for example, if the signal input to fir4 is at 0.1 f dac , the response of fir4 is 0.1 db, and the signal must be backed off from full scale by 0.1 db to avoid saturation. the filter taps for all digital filters are listed in table 5 . note that the loss of signal amplitude may result in lower snr due to decrease in signal amplitude. figure 37. magnitude spectrum for fir0 figure 38. fir0 transition band figure 39. magnitude spectrum for zero-if sinc figure 40. correction range of zero-if sinc correction filter up to 0.5 f dac correction filter 0 to 0.2 f dac copyright ? 2009 ? 2010, texas instruments incorporated submit documentation feedback 33 product folder link(s): dac3282 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 fir4 sin(x)/x corrected magnitude - db f /f out dac 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 -160 -140 -120 -100 -80 -60 -40 -20 0 20 magnitude - db f/f in 0.36 0.37 0.38 0.39 0.4 0.41 0.42 0.43 0.44 0.45 0.46 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 magnitude - db f/f in 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 -4 -3 -2 -1 0 1 2 3 4 fir4 corrected sin(x)/x f /f out dac magnitude - db
dac3282 slas646a ? december 2009 ? revised february 2010 www.ti.com table 5. fir filter coefficients fir4 fir0 non-interpolating zero-if 2x interpolating half-band filter sinc correction filter 59 taps 5 taps 4 4 1 0 0 ? 5 ? 12 ? 12 264 (1) 0 0 ? 5 28 28 1 0 0 ? 58 ? 58 0 0 108 108 0 0 ? 188 ? 188 0 0 308 308 0 0 ? 483 ? 483 0 0 734 734 0 0 ? 1091 ? 1091 0 0 1607 1607 0 0 ? 2392 ? 2392 0 0 3732 3732 0 0 ? 6681 ? 6681 0 0 20768 20768 32768 (1) (1) center taps are highlighted in bold. 34 submit documentation feedback copyright ? 2009 ? 2010, texas instruments incorporated product folder link(s): dac3282
dac3282 www.ti.com slas646a ? december 2009 ? revised february 2010 coarse mixer the dac3282 has a coarse mixer block capable of shifting the input signal spectrum by the fixed mixing frequencies f s /2 or f s /4. the coarse mixing function is built into the interpolation filter and thus fir0 must be enabled to use it. treating channels a and b as a complex vector of the form i(t) + j q(t), where i(t) = a(t) and q(t) = b(t), the outputs of the coarse mixer, a out (t) and b out (t) are equivalent to: (1) (2) where f cmix is the fixed mixing frequency selected by mixer_func(1:0). for f s /2, +f s /4 and ? f s /4 the above operations result in the simple mixing sequences shown in table 6 . table 6. coarse mixer sequences mode mixer_func(1:0) mixing sequence normal 00 a out = { +a, +a , +a, +a } (low pass, no mixing) b out = { +b, +b , +b, +b } f s /2 01 a out = { +a, ? a , +a, ? a } b out = { +b, ? b , +b, ? b } +f s /4 10 a out = { +a, ? b , ? a, +b } b out = { +b, +a , ? b, ? a } ? f s /4 11 a out = { +a, +b , ? a, ? b } b out = { +b, ? a , ? b, +a } figure 41. coarse mixers block diagram the coarse mixer in the dac3282 treats the a and b inputs as complex input data and for most mixing frequencies produces a complex output. only when the mixing frequency is set to f s /2 the a and b channels can be maintained isolated as shown in table 6 . in this case the two channels are upconverted as independent signals. by setting the mixer to f s /2 the fir0 outputs are inverted thus behaving as a high-pass filter. copyright ? 2009 ? 2010, texas instruments incorporated submit documentation feedback 35 product folder link(s): dac3282 x2 x2 fir 0 (x2 bypass) coarse mixer a data in b data in a data out b data out block diagram 01 0 1 1 -1 0 1 0 1 1 -1 mix sequencer mixer_func(1:0) a mix in b mix in a mix out b mix out out cmix cmix b (t) = a(t)sin(2 f t) + b(t)cos(2 f t) p p out cmix cmix a (t) = a(t)cos(2 f t) b(t)sin(2 f t) p p -
dac3282 slas646a ? december 2009 ? revised february 2010 www.ti.com table 7. dual-channel real upconversion options fir mode input frequency (1) output frequency (1) signal bandwidth (1) spectrum inverted? low pass 0.0 to 0.4 x f data 0.0 to 0.4 x f data 0.4 x f data no high pass 0.0 to 0.4 x f data 0.6 to 1.0 x f data 0.4 x f data yes (1) f data is the input data rate of each channel after de-interleaving. digital offset control the qmc_offseta(12:0) and qmc_offsetb(12:0) values in registers config20 through config23 can be used to independently adjust the a and b path dc offsets. both offset values are in represented in 2s-complement format with a range from ? 4096 to 4095. note that a write to register config20 is required to load the values of all four qmc_offset registers (config20-config23) into the offset block simultaneously. when updating the offset values config20 should be written last. programming any of the other three registers will not affect the offset setting. the offset value adds a digital offset to the digital data before digital-to-analog conversion. since the offset is added directly to the data it may be necessary to back off the signal to prevent saturation. both data and offset values are lsb aligned. figure 42. digital offset block diagram temperature sensor the dac3282 incorporates a temperature sensor block which monitors the temperature by measuring the voltage across 2 transistors. the voltage is converted to an 8-bit digital word using a successive-approximation (sar) analog to digital conversion process. the result is scaled, limited and formatted as a twos complement value representing the temperature in degrees celsius. the sampling is controlled by the serial interface signals sdenb and sclk. if the temperature sensor is enabled (tsense_ena = 1 in register config24) a conversion takes place each time the serial port is written or read. the data is only read and sent out by the digital block when the temperature sensor is read in register config5. the conversion uses the first eight clocks of the serial clock as the capture and conversion clock, the data is valid on the falling eighth sclk. the data is then clocked out of the chip on the rising edge of the ninth sclk. no other clocks to the chip are necessary for the temperature sensor operation. as a result the temperature sensor is enabled even when the device is in sleep mode. in order for the process described above to operate properly, the serial port read from config5 must be done with an sclk period of at least 1 s. if this is not satisfied the temperature sensor accuracy is greatly reduced. 36 submit documentation feedback copyright ? 2009 ? 2010, texas instruments incorporated product folder link(s): dac3282 s 13 qmc_offseta {-4096 , -4095, , 4095} a data in s 13 qmc_offsetb {-4096 , -4095, , 4095} b data in a data out b data out 16 16 16 16
dac3282 www.ti.com slas646a ? december 2009 ? revised february 2010 power-up sequence the following startup sequence is recommended to power-up the dac3282: 1. set txenable low. 2. supply 1.8v to dacvdd18, digvdd18, clkvdd18 and vfuse simultaneously and 3.3v to avdd33. within avdd33 the multiple avdd33 pins should be powered up simultaneously. the 1.8v and 3.3v supplies can be powered up simultaneously or in any order. there are no specific requirements on the ramp rate for the supplies. 3. provide all lvpecl inputs: dacclkp/n and if used ostrp/n. 4. toggle the resetb pin for a minimum 25 ns active low pulse width. 5. program the sif registers. 6. provide all lvds inputs (d[7:0]p/n, dataclkp/n and framep/n) simultaneously. 7. sync the clock dividers and fifo. after a framep/n low-to-high transition, clock divider syncing must be disabled by setting clkdiv_sync_ena (config18, bit 1) to 0. optionally, disable fifo and device syncing by setting fifo_reset_ena (config0, bit 5) and multi_sync_ena (config0, bit 4) to 0. except when in multi-dac operation it is recommended to sync the dacs and their fifos only once during initialization. 8. enable transmit of data by asserting the txenable pin. sleep modes the dac3282 features independent sleep control of each dac (sleepa and sleepb), their corresponding clock path (clkpath_sleep_a and clkpath_sleep_b) as well as the clock input receiver of the device (clkrecv_sleep). the sleep control of each of these components is done through the sif interface and is enabled by setting a 1 to the corresponding sleep register. complete power down of the device is set by setting all of these components to sleep. under this mode the supply power consumption is reduced to 15mw. power-up time in this case will be in the milliseconds range. alternatively for those applications were power-up and power-down times are critical it is recommended to only set the dacs to sleep through the sleepa and sleepb registers. in this case both the sleep and wake-up times are only 90 s. lvpecl inputs figure 43 shows an equivalent circuit for the dac input clock (dacclkp/n) and the fifo output strobe clock (ostrp/n). figure 43. dacclkp/n and ostrp/n equivalent input circuit figure 44 shows the preferred configuration for driving the clkin/clkinc input clock with a differential ecl/pecl source. copyright ? 2009 ? 2010, texas instruments incorporated submit documentation feedback 37 product folder link(s): dac3282 dacclkp ostrp dacclkn ostrn gnd 666 w 2 k w clkvdd note: input common mode level is approximately 2/3*clkvdd18, or 1.2v nominal. 2 k w 333 w
dac3282 slas646a ? december 2009 ? revised february 2010 www.ti.com figure 44. preferred clock input configuration with a differential ecl/pecl clock source lvds inputs the d[7:0]p/n, dataclkp/n and framep/n lvds pairs have the input configuration shown in figure 45 . figure 46 shows the typical input levels and common-move voltage used to drive these inputs. figure 45. d[7:0]p/n, dataclkp/n and framep/n lvds input configuration figure 46. lvds data (d[7:0]p/n, dataclkp/n, framep/n pairs) input levels 38 submit documentation feedback copyright ? 2009 ? 2010, texas instruments incorporated product folder link(s): dac3282 clkin clkinc + - 0.1 f m 0.1 f m 100 w c ac 82.5 w r t 82.5 w r t 130 w 130 w v tt differential ecl or (lv)pecl source d[7:0]p, dataclkp , framep 50 d[7:0]n, dataclkn , framen 50 lvds receiver 100pf total to adjacent lvds input to adjacent lvds input ref note (1) note (1): r center node common to the d[7:0] p/n, dataclkp / n and framep/n receiver inputs d[7:0]p, dataclkp , framep 100 lvds receiver dac3282 d[7:0]n, dataclkn , framen gnd v com = (v a +v b )/2 v b v a,b v a v a v b v a,b logical bit equivalent 1.40v 1.00v 400mv 0v -400mv 1 0 example
dac3282 www.ti.com slas646a ? december 2009 ? revised february 2010 table 8. example lvds data input levels resulting resulting differential applied voltages common-mode logical bit binary voltage voltage equivalent v a v b v a,b v com 1.4 v 1.0 v 400 mv 1 1.2 v 1.0 v 1.4 v ? 400 mv 0 1.2 v 0.8 v 400 mv 1 1.0 v 0.8 v 1.2 v ? 400 mv 0 cmos digital inputs figure 47 shows a schematic of the equivalent cmos digital inputs of the dac3282. sdio, sclk and txenable have pull-down resistors while sdenb and resetb have pull-up resistors internal to the dac3282. see the specification table for logic thresholds. the pull-up and pull-down circuitry is approximately equivalent to 100k ? . figure 47. cmos/ttl digital equivalent input reference operation the dac3282 uses a bandgap reference and control amplifier for biasing the full-scale output current. the full-scale output current is set by applying an external resistor r bias to pin biasj. the bias current i bias through resistor r bias is defined by the on-chip bandgap reference voltage and control amplifier. the default full-scale output current equals 16 times this bias current and can thus be expressed as: iout fs = 16 i bias = 16 v extio / r bias each dac has a 4-bit independent coarse gain control via coarse_daca(3:0) and coarse_dacb (3:0) in the config4 register. using gain control, the iout fs can be expressed as: iouta fs = (daca_gain + 1) i bias = (daca_gain + 1) v extio / r bias ioutb fs = (dacb_gain + 1) i bias = (dacb_gain + 1) v extio / r bias where v extio is the voltage at terminal extio. the bandgap reference voltage delivers an accurate voltage of 1.2v. this reference is active when extref_ena = ? 0 ? in config25. an external decoupling capacitor c ext of 0.1 m f should be connected externally to terminal extio for compensation. the bandgap reference can additionally be used for external reference operation. in that case, an external buffer with high impedance input should be applied in order to limit the bandgap load current to a maximum of 100 na. the internal reference can be disabled and overridden by an external reference by setting the config25 extref_ena control bit. capacitor c ext may hence be omitted. terminal extio thus serves as either input or output node. the full-scale output current can be adjusted from 20 ma down to 2 ma by varying resistor r bias or changing the externally applied reference voltage. the internal control amplifier has a wide input range, supporting the full-scale output current range of 20 db. copyright ? 2009 ? 2010, texas instruments incorporated submit documentation feedback 39 product folder link(s): dac3282 sdio sclk txenable internal digital in digvdd 18 gnd sdenb resetb internal digital in digvdd 18 gnd
dac3282 slas646a ? december 2009 ? revised february 2010 www.ti.com dac transfer function the cmos dac ? s consist of a segmented array of nmos current sinks, capable of sinking a full-scale output current up to 20 ma. differential current switches direct the current to either one of the complementary output nodes iout1 or iout2. (daca = iouta1 or iouta2 and dacb = ioutb1 or ioutb2.) complementary output currents enable differential operation, thus canceling out common mode noise sources (digital feed-through, on-chip and pcb noise), dc offsets, even order distortion components, and increasing signal output power by a factor of two. the full-scale output current is set using external resistor r bias in combination with an on-chip bandgap voltage reference source (+1.2v) and control amplifier. current i bias through resistor r bias is mirrored internally to provide a maximum full-scale output current equal to 16 times i bias . the relation between iout1 and iout2 can be expressed as: iout1 = ? iout fs ? iout2 we will denote current flowing into a node as ? current and current flowing out of a node as + current. since the output stage is a current sink the current can only flow from avdd into the iout1 and iout2 pins. the output current flow in each pin driving a resistive load can be expressed as: iout1 = iout fs (65535 ? code) / 65536 iout2 = iout fs code / 65536 where code is the decimal representation of the dac data input word. for the case where iout1 and iout2 drive resistor loads r l directly, this translates into single ended voltages at iout1 and iout2: vout1 = avdd ? | iout1 | r l vout2 = avdd ? | iout2 | r l assuming that the data is full scale (65536 in offset binary notation) and the r l is 25 ? , the differential voltage between pins iout1 and iout2 can be expressed as: vout1 = avdd ? | ? 0ma | 25 ? = 3.3 v vout2 = avdd ? | ? 20ma | 25 ? = 2.8 v vdiff = vout1 ? vout2 = 0.5v note that care should be taken not to exceed the compliance voltages at node iout1 and iout2, which would lead to increased signal distortion. 40 submit documentation feedback copyright ? 2009 ? 2010, texas instruments incorporated product folder link(s): dac3282
dac3282 www.ti.com slas646a ? december 2009 ? revised february 2010 analog current outputs figure 48 shows a simplified schematic of the current source array output with corresponding switches. differential switches direct the current of each individual nmos current source to either the positive output node iout1 or its complementary negative output node iout2. the output impedance is determined by the stack of the current sources and differential switches, and is typically > 300 k ? in parallel with an output capacitance of 5 pf. the external output resistors are referred to an external ground. the minimum output compliance at nodes iout1 and iout2 is limited to avdd ? 0.5 v, determined by the cmos process. beyond this value, transistor breakdown may occur resulting in reduced reliability of the dac3282 device. the maximum output compliance voltage at nodes iout1 and iout2 equals avdd + 0.5 v. exceeding the minimum output compliance voltage adversely affects distortion performance and integral non-linearity. the optimum distortion performance for a single-ended or differential output is achieved when the maximum full-scale signal at iout1 and iout2 does not exceed 0.5 v. figure 48. equivalent analog current output the dac3282 can be easily configured to drive a doubly terminated 50 ? cable using a properly selected rf transformer. figure 49 and figure 50 show the 50 ? doubly terminated transformer configuration with 1:1 and 4:1 impedance ratio, respectively. note that the center tap of the primary input of the transformer has to be connected to avdd to enable a dc current flow. applying a 20 ma full-scale output current would lead to a 0.5 vpp for a 1:1 transformer and a 1 vpp output for a 4:1 transformer. the low dc-impedance between iout1 or iout2 and the transformer center tap sets the center of the ac-signal at avdd, so the 1 vpp output for the 4:1 transformer results in an output between avdd + 0.5 v and avdd ? 0.5 v. copyright ? 2009 ? 2010, texas instruments incorporated submit documentation feedback 41 product folder link(s): dac3282 avdd s(1) s(1)c s(2) s(2)c s(n) s(n)c ... iout1 iout2 r load r load
dac3282 slas646a ? december 2009 ? revised february 2010 www.ti.com figure 49. driving a doubly terminated 50 ? cable using a 1:1 impedance ratio transformer figure 50. driving a doubly terminated 50 ? cable using a 4:1 impedance ratio transformer 42 submit documentation feedback copyright ? 2009 ? 2010, texas instruments incorporated product folder link(s): dac3282 iout 1 1 : 1 iout 2 r load 100 w 50 w avdd avdd 3.3 v 3.3 v 50 w 50 w iout 1 4 : 1 50 w r load 100 w iout 2 avdd 3.3 v avdd 3.3 v 100 w
dac3282 www.ti.com slas646a ? december 2009 ? revised february 2010 passive interface to analog quadrature modulators a common application in communication systems is to interface the dac to an iq modulator like the trf3703 family of modulators from texas instruments. the input of the modulator is generally of high impedance and requires a specific common-mode voltage. a simple resistive network can be used to maintain 50 load impedance for the dac3282 and also provide the necessary common-mode voltages for both the dac and the modulator. figure 51. dac to analog quadrature modulator interface the dac3282 has a maximum 20ma full-scale output and a voltage compliance range of avdd 0.5 v. the trf3703 iq modulator family can be operated at three common-mode voltages: 1.5v, 1.7v, and 3.3v. figure 52 shows the recommended passive network to interface the dac3282 to the trf3703-17 which has a common mode voltage of 1.7v. the network generates the 3.3v common mode required by the dac output and 1.7v at the modulator input, while still maintaining 50 ? load for the dac. figure 52. dac3282 to trf3703-17 interface if v1 is set to 5v and v2 is set to -5v, the corresponding resistor values are r1 = 57 , r2 = 80 , and r3 = 336 . the loss developed through r2 is about -1.86 db. in the case where there is no ? 5v supply available and v2 is set to 0v, the resistor values are r1 = 66 , r2 = 101 , and r3 = 107 . the loss with these values is ? 5.76db. figure 53 shows the recommended network for interfacing with the trf3703-33 which requires a common mode of 3.3v. this is the simplest interface as there is no voltage shift. because there is no voltage shift there isn't any loss in the network. with v1 = 5v and v2 = 0v, the resistor values are r1 = 66 and r3 = 208 . copyright ? 2009 ? 2010, texas instruments incorporated submit documentation feedback 43 product folder link(s): dac3282 iouta1 iouta2 ioutb1 ioutb2 s rf signal conditioning quadrature modulator v out ~ 2.8 to 3.8 v v in ~ varies i1 i2 q1 q2 i /i trf3703-17 i /i v1 v1 r1 r1 r2 r2 r3 r3 v2 dac3282
dac3282 slas646a ? december 2009 ? revised february 2010 www.ti.com figure 53. dac3282 to trf3703-33 interface in most applications a baseband filter is required between the dac and the modulator to eliminate the dac images. this filter can be placed after the common-mode biasing network. for the dac to modulator network shown in figure 54 , r2 and the filter load r4 need to be considered into the dac impedance. the filter has to be designed for the source impedance created by the resistor combination of r3 // (r2+r1). the effective impedance seen by the dac is affected by the filter termination resistor resulting in r1 // (r2+r3 // (r4/2)). figure 54. dac3282 to modulator interface with filter factoring in r4 into the dac load, a typical interface to the trf3703-17 with v1 = 5v and v2 = 0v results in the following values: r1 = 72 , r2 = 116 , r3 = 124 and r4 = 150 . this implies that the filter needs to be designed for 75 input and output impedance (single-ended impedance). the common mode levels for the dac and modulator are maintained at 3.3v and 1.7v and the dac load is 50 . the added load of the filter termination causes the signal to be attenuated by ? 10.8 db. a filter can be implemented in a similar manner to interface with the trf3703-33. in this case it is much simpler to balance the loads and common mode voltages due to the absence of r2. an added benefit is that there is no loss in this network. with v1 = 5v and v2 = 0v the network can be designed such that r1 = 115 , r3 = 681 , and r4 = 200 . this results in a filter impedance of r1 // r2=100 , and a dac load of r1 // r3 // (r4/2) which is equal to 50 . r4 is a differential resistor and does not affect the common mode level created by r1 and r3. the common-mode voltage is set at 3.3 v for a full-scale current of 20ma. for more information on how to interface the dac3282 to an analog quadrature modulator please refer to the application reports passive terminations for current output dacs ( slaa399 ) and design of differential filters for high-speed signal chains ( slwa053 ). 44 submit documentation feedback copyright ? 2009 ? 2010, texas instruments incorporated product folder link(s): dac3282 dac3282 i /i trf3703 v1 r1 r1 r3 r3 filter r4 v1 r2 r2 v2 i /i trf3703-33 i /i v1 v1 r1 r1 r3 r3 v2 dac3282
dac3282 www.ti.com slas646a ? december 2009 ? revised february 2010 application example direct conversion radio refer to figure 55 for an example direct conversion radio. the dac3282 receives an interleaved complex i/q baseband input data stream and increases the sample rate through interpolation by a factor of 2. by performing digital interpolation on the input data, undesired images of the original signal can be push out of the band of interest and more easily suppressed with analog filters. for a zero if (zif) frequency plan, complex mixing of the baseband signal is not required. alternatively, for a complex if frequency plan the input data can be pre-placed at an if within the bandwidth limitations of the interpolation filters. in addition, complex mixing is available using the coarse mixer block to up-convert the signal. the output of both dac channels is used to produce a hilbert transform pair and can be expressed as: a out (t) = a(t)cos( w c t) ? b(t)sin( w c t) = m(t) b out (t) = a(t)sin( w c t) + b(t)cos( w c t) = m h (t) where m(t) and m h (t) connote a hilbert transform pair and w c is the mixer frequency. the complex output is input to an analog quadrature modulator (aqm) such as the texas instruments trf3720 for a single side-band (ssb) up conversion to rf. a passive (resistor only) interface to the aqm with an optional lc filter network is recommended. the trf3720 includes a vco/pll to generate the lo frequency. upper single-sideband upconversion is achieved at the output of the analog quadrature modulator, whose output is expressed as: rf(t) = a(t)cos( w c + w lo )t ? b(t)sin( w c + w lo )t flexibility is provided to the user by allowing for the selection of negative mixing frequency to produce a lower-sideband upconversion. note that the process of complex mixing translates the signal frequency from 0hz means that the analog quadrature modulator iq imbalance produces a sideband that falls outside the signal of interest. dc offset error in dac and aqm signal path may produce lo feed-through at the rf output which may fall in the band of interest. to suppress the lo feed-through, the dac3282 provides a digital offset correction capability for both dac-a and dac-b paths. the complex if architecture has several advantages over the real if architecture: ? uncalibrated side-band suppression ~ 35dbc compared to 0dbc for real if architecture. ? direct dac to aqm interface ? no amplifiers required ? dac 2nd nyquist zone image is offset f dac compared with f dac ? 2 if for a real if architecture, reducing the need for filtering at the dac output. ? uncalibrated lo feed through for aqm is ~ 35dbc and calibration can reduce or completely remove the lo feed through. copyright ? 2009 ? 2010, texas instruments incorporated submit documentation feedback 45 product folder link(s): dac3282
dac3282 slas646a ? december 2009 ? revised february 2010 www.ti.com figure 55. system diagram of direct conversion radio 46 submit documentation feedback copyright ? 2009 ? 2010, texas instruments incorporated product folder link(s): dac3282 div dataclkp /n framep/n dac-a q-fir cmix i-fir q- isinc i- isinc dacclkp/n dac3282 dac fpga pfd/cp cdce62005 clock generator with vco vco n- divider r- div pfd cpout vctrl_in 90 0 trf3720 aqm with pll/vco loopfilter div 2/4/8 rf out optional filter network lvds data interface loopfilter 5v d0p/n d7p/n byte-wide data 100 100 100 100 dac-b 10 mhz osc clock divider/ distribution /1 div 100 fifo & demux 100 pll/ dll /2
dac3282 www.ti.com slas646a ? december 2009 ? revised february 2010 revision history note: page numbers of current version may differ from previous versions changes from original (december 2009) to revision a page ? deleted fifo_ostrp and fifo_ostrn descriptions from pin functions table. n/a for this device. .............................. 4 ? changed default from 0x41 to 0x43 for register name version31 in table 3 register map ........................................ 22 ? changed default address from 0x41 to 0x43 for register name: version31 ; and default value for bit 5:0 from 000001 to 000011. .............................................................................................................................................................. 29 copyright ? 2009 ? 2010, texas instruments incorporated submit documentation feedback 47 product folder link(s): dac3282
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant dac3282irgzr vqfn rgz 48 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 q2 dac3282irgzt vqfn rgz 48 250 330.0 16.4 7.3 7.3 1.5 12.0 16.0 q2 package materials information www.ti.com 20-jul-2010 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) dac3282irgzr vqfn rgz 48 2500 333.2 345.9 28.6 dac3282irgzt vqfn rgz 48 250 333.2 345.9 28.6 package materials information www.ti.com 20-jul-2010 pack materials-page 2

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