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description the rdc-19220 series of converters are low-cost, versatile, 16-bit monolith- ic, state-of-the-art resolver(/lvdt)-to- digital converters. these single-chip converters are available in small 40-pin ddip, or 44-pin j-lead packages and offer programmable features such as resolution, bandwidth and velocity output scaling. resolution programming allows selection of 10-, 12-, 14-, or 16-bit, with accuracies to 2.3 min. this fea- ture combines the high tracking rate of a 10-bit converter with the preci- sion and low-speed velocity resolution of a 16-bit converter in one package. the velocity output (vel) from the rdc-19220 series, which can be used to replace a tachometer, is a 4 v signal (3.5 v with the +5 v only option) referenced to ground with a linearity of 0.75% of output voltage. the full scale value of vel is set by the user with a single resistor. rdc-19220 series converters are available with operating temperature ranges of 0 to +70c, -40 to +85c and -55 to +125c. military pro- cessing is available (consult factory). applications with its low cost, small size, high accuracy and versatile performance, the rdc-19220 series converter is ideal for use in modern high-perfor- mance industrial and military control systems. typical applications include motor control, radar antenna position- ing, machine tool control, robotics, and process control. features ? +5 volt only option ? only five external passive components ? programmable: - resolution: 10-, 12-, 14-, or 16-bit - bandwidth: to 1200 hz - tracking: to 2300 rps ? differential resolver and lvdt input modes ? velocity output eliminates tachometer ? built-in-test (bit) output, no 180 hangup ? small size: 40-pin ddip or 44-pin j-lead package ? -55 to +125c operating temperature available sin -s +s cos -c +c +5c +cap -cap -5c a gnd +5 v gnd -5 v control transformer -5 v inverter data latch gain demodulator 16 bit up/down counter hysteresis +ref -ref bit r 1 vco & timing - + - + ab inh em bit 1 thru bit 16 el ab cb e r s r c r v r b c bw c bw 10 -vsum vel -vco integrator ? 1990, 1999 data device corporation figure 1. rdc-19220 series block diagram available as radiation hardened in rad-pak? technology by space electronics inc. rdc-19220 series 16-bit monolithic tracking resolver(/lvdt)-to-digital converters
2 table 1. rdc-19220 specifications these specifications apply over the rated power supply, temperature and reference frequency ranges, and 10% signal amplitude variation and harmonic distortion. parameter unit value resolution bits 10, 12, 14, or 16 accuracy min 4, or 2 + 1 lsb (note 3) repeatability lsb 1 max differential linearity lsb 1 max in the 16th bit reference type voltage: differential single ended overload frequency input impedance v p - p v p v hz ohm (+ref, -ref) differential 10 max 5 max 25 continuous, 100 transient dc to 40,000 (note 4) 10m min // 20 pf signal input type voltage: operating overload input impedance vrms v ohm (+s, -s, sin, +c, -c, cos) resolver, differential, groundbased 2 15% 25 continuous 10m min//10 pf. digital input/output logic type inputs inhibit (inh) enable bits 1 to 8 (em) enable bits 9 to 16 (el) resolution and mode control(a & b) (see notes 1 and 2.) outputs parallel data (1-16) converter busy (cb) zero index (zl) notes: 1. unused data bits are set to logic 0. 2. in lvdt mode, bit 16 is lsb for 14-bit resolution or bit 12 is lsb for 10-bit resolution. 3. accuracy in lvdt mode is 0.15% + 1 lsb of full scale. 4. see text, general setup considerations and higher tracking rates. 5. see text: general setup considerations for rdc19222. table 1. rdc-19220 specifications (contd) unit parameter value digital input/output (continued) outputs (continued) built-in-test (bit) drive capability dynamic characteristics resolution tracking rate (max)(note 4) bandwidth(closed loop) (max) (note 4) ka a1 a2 a b acceleration (1 lsb lag) settling time(179 step) bits rps hz 1/sec 2 1/sec 1/sec 1/sec 1/sec deg/s 2 msec (at maximum bandwidth) 10 12 14 16 1152 288 72 18 1200 1200 600 300 5.7m 5.7m 1.4m 360k 19.5 19.5 4.9 1.2 295k 295k 295k 295k 2400 2400 1200 600 1200 1200 600 300 2m 500k 30k 2k 2 8 20 50 velocity characteristics polarity voltage range(full scale) scale factor error scale factor tc reversal error linearity zero offset zero offset tc load noise v % ppm/c % % mv v/c k w ( vp/v)% positive for increasing angle 4 (at nominal ps) 10 typ 20 max 100 typ 200 max 0.75 typ 1.3 max 0.25 typ 0.50 max 5 typ 10 max 15 typ 30max 8 max 1 typ .125 min 2 max power supplies nominal voltage voltage range max volt. w/o damage current v % v ma (note 5) +5 -5 5 +5, -20 (-4 v to -5.25 v) +7 -7 14 typ, 22 max (each) temperature range operating -30x -20x -10x storage plastic package ceramic package c c c c c 0 to +70 -40 to +85 -55 to +125 -40 to +85 -65 to +150 physical characteristics size: 40 pin ddip 44 pin j-lead in(mm) in(mm) 2.0 x 0.6 x 0.2 (50.8 x 15.24 x 5.08) 0.690 square (17.526) weight: 40 pin ddip 44 pin j-lead oz(g) oz(g) plastic ceramic 0.21 (5.95) 0.24 (6.80) 0.08 (2.27) 0.065 (1.84) ttl/cmos compatible logic 0 = 0.8 v max. logic 1 = 2.0 v min. loading =10 a max p.u. current source to +5 v //5 pf max. cmos transient protected logic 0 inhibits; data stable within 0.3 s logic 0 enables; data stable within 150 ns logic 1 = high impedance data high z within 100 ns mode b a resolution resolver 0 0 10 bits " 0 1 12 bits " 1 0 14 bits " 1 1 16 bits lvdt - 5 v 0 8 bits " 0 -5 v 10 bits " 1 -5 v 12 bits " -5 v -5 v 14 bits 10, 12, 14, or 16 parallel lines; natural binary angle positive logic (see table 2) 0.25 to 0.75 s positive pulse leading edge initiates counter update. logic 1 at all 0s (enl to -5 v); lsbs are enabled logic 0 for bit condition. 100 lsbs of error typ. with a fil- ter of 500 s, or total loss-of- signal (los) 50 pf + logic 0; 1 ttl load, 1.6 ma at 0.4 v max logic 1; 10 ttl loads, -0.4 ma at 2.8 v min logic 0; 100 mv max driving cmos logic 1; +5 v supply minus 100 mv min driving cmos high z; 10 ua // 5 pf max
theory of operation the rdc-19220 series of converters are single cmos custom monolithic chips. they are implemented using the latest ic tech- nology which merges precision analog circuitry with digital logic to form a complete, high-performance tracking resolver-to-digital converter. for user flexibility and convenience, the converter bandwidth, dynamics and velocity scaling are externally set with passive components. figure 1 is the functional block diagram of the rdc-19220 series. the converter operates with 5 vdc power supplies. analog signals are referenced to analog ground, which is at ground potential. the converter is made up of two main sections; a converter and a digital interface. the converter front-end con- sists of sine and cosine differential input amplifiers. these inputs are protected to 25 v with 2 k w resistors and diode clamps to the 5 vdc supplies. these amplifiers feed the high accuracy control transformer (ct). its other input is the 16-bit digital angle f . its output is an analog error angle, or difference angle, between the two inputs. the ct performs the ratiometric trigono- metric computation of sin q cos f - cos q sin f = sin( q - f ) using amplifiers, switches, logic and capacitors in precision ratios. note: the transfer function of the ct is normally trigonometric, but in ldvt-mode the transfer function is triangular (linear) and could thereby convert any linear transducer output. the converter accuracy is limited by the precision of the com- puting elements in the ct. in these converters, ratioed capacitors are used in the ct instead of the more conventional precision ratioed resistors. capacitors, used as computing elements with op-amps, need to be sampled to eliminate voltage drifting. therefore, the circuits are sampled at a high rate (67 khz) to eliminate this drifting and at the same time to cancel out the op- amp offsets. the error processing is performed using the industry standard technique for type ii tracking r/d converters. the dc error is inte- grated yielding a velocity voltage which in turn drives a voltage controlled oscillator (vco). this vco is an incremental integra- tor (constant voltage input to position rate output) which togeth- er with the velocity integrator forms a type ii servo feedback loop. a lead in the frequency response is introduced to stabilize the loop and another lag at higher frequency is introduced to reduce the gain and ripple at the carrier frequency and above. the set- tings of the various error processor gains and break frequencies are done with external resistors and capacitors so that the con- verter loop dynamics can be easily controlled by the user. transfer function and bode plot the dynamic performance of the converter can be determined from its transfer function block diagrams and its bode plots (open and closed loop). these are shown in figures 2, 3, and 4. the open loop transfer function is as follows: s a 2 +1 b ( ) open loop transfer function = s s 2 +1 10b ( ) where a is the gain coefficient and a 2 = a 1 a 2 and b is the frequency of lead compensation. 3 gain 11 mv/lsb 16 bit up/down counter r 1 vco r v r b c bw c /10 bw vel -vco h = 1 -vsum vel c f s s ct + - resolver input ( q ) r s 50 pf c vco digital output ( f ) demod 1.25 v threshold 1 figure 2. transfer function block diagram #1 table 2. digital angle outputs bit deg/bit min/bit 1(msb) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 180 90 45 22.5 11.25 5.625 2.813 1.405 0.7031 0.3516 0.1758 0.0879 0.0439 0.0220 0.0110 0.0055 10800 5400 2700 1350 675 337.5 168.75 84.38 42.19 21.09 10.55 5.27 2.64 1.32 0.66 0.33 note: em enables the msbs and el enables the lsbs.
the components of gain coefficient are error gradient, integrator gain and vco gain. these can be broken down as follows: - error gradient = 0.011 volts per lsb (ct+error amp+demod with 2 vrms input) c s f s - integrator gain = volts per second per volt 1.1c bw 1 - vco gain = lsbs per second per volt 1.25 r v c vco where: c s = 10 pf f s = 67 khz when r s = 30 k w f s = 100 khz when r s = 20 k w f s = 134 khz when r s = 15 k w c vco = 50 pf r v , r b , and c bw are selected by the user to set velocity scaling and bandwidth. general setup considerations ddc has external component selection software which consid- ers all the criteria below, and in a simple fashion, asks the key parameters (carrier frequency, resolution, bandwidth, and track- ing rate) to derive the external component value. the following recommendations should be considered when installing the rdc-19220 series r/d converters: 1) in setting the bandwidth (bw) and tracking rate (tr) (selecting five external components), the system require- ments need to be considered. for greatest noise immunity, select the minimum bw and tr the system will allow. 2) power supplies are 5 v dc. for lowest noise performance it is recommended that a 0.1 f or larger cap be connected from each supply to ground near the converter package. 4 error processor resolver input ( q ) velocity out digital position out ( f ) vco ct s a + 1 1 b s s + 1 10b h = 1 + - e a 2 s -12 db/oct ba 2a -6 db/oct 10b w (rad/sec) 2a 2 2 a w (rad/sec) f = bw (hz) = bw 2 a p closed loop (b = a/2) gain = 0.4 gain = 4 (critically damped) open loop figure 3. transfer function block diagram #2 figure 4. bode plots 3) resolver inputs and velocity output are referenced to a gnd. this pin should be connected to gnd near the converter package. digital currents flowing through ground will not disturb the analog signals. 4) the bit output which is active low is activated by an error of approximately 100 lsbs. during normal operation for step inputs or on power up, a large error can exist. 5) this device has several high impedence amplifier inputs (+c, -c, +s, -s, -vco and -vsum). these nodes are sensitive to noise and cou- pling components should be connected as close as possible. 6) setup of bandwidth and velocity scaling for the optimized critically damped case should proceed as follows: - select the desired f bw (closed loop), based on overall sys- tem dynamics. - select fcarrier 3 3.5 f bw for the converter max tracking rate value, see the row indicated in table 3. { } - compute r v = 55 k w x application max rate 3.2 x f s (hz) x 10 8 - compute c bw (pf) = r v x (f bw ) 2 - where f s = 67 khz for r s = 30 k w 100 khz for r s = 20 k w 134 khz for r s = 15 k w 0.9 - compute r b = c bw x f bw c bw - compute 10 note: ddc has software available to perform the previous calcu- lations. contact ddc to request software or visit our website at www.ddc-web.com to download software.
for a 12-bit converter there are 2 12 or 4096 counts per rotation. 1,333,333/4096 = 325 rotations per second or 333,333 counts per second per volt. 1 r v = = 48k ohms (333,333 x 50 pf x 1.25) the maximum rate capability of the rdc-19220 is set by r s . when r s = 30 k w it is nominally 1,333,333 counts/sec, which equates to 325 rps (rotations per second). this is the absolute maximum rate; it is recommended to only run at <90% of this rate (as seen in table 3), therefore the minumum r v will be limited to 55 k w. the converter maximum tracking rate can be increased 50% in the 16- and 14-bit modes and 100% in the 12- and 10-bit modes by increasing the supply current from 12 to 15 ma (by using an r c = 23 k w ), and by increasing the sampling rate by changing r s to 20 k w for 16- and 14-bit resolution or to 15 k w for 12- and 10-bit resolution (see table 4). the maximum carrier frequency can, in the same way, increase from: 5 to 10 khz in the 16-bit mode, 7 to 14 khz in the 14-bit mode,11 to 32 khz in the 12-bit mode, and 20 to 40 khz in the 10-bit mode (see table 5). the maximum tracking rate and carrier frequency for full perfor- mance are set by the power supply current control resistor (r c ) per the following tables: 7) selecting a f bw that is too low relative to the maximum appli- cation tracking rate can create a spin-around condition in which the converter never settles. the relationship to insure aganist spin-around is as follows (table 3): 5 table 3. tracking/bw relationship rps (max)/bw resolution 1 10 0.45 12 0.25 14 0.125 16 table 4. max tracking rate (min) in rps r c ( w w ) r s ( w w ) resolution 10 12 14 16 30k** or open 30k 1152 288 72 18 23k 20k 1728 432 108 27 23k 15k 2304 576 * * * 10 * 14 32 24 40 34 15k 20k 23k 23k 7 11 12 24 30k 23k 5 7 11 20 30k 30k** or open 16 14 12 10 resolution r s ( w w ) r c ( w w ) table 5. carrier frequency (max) in khz depending on the res- olution, select one of the values from this row, for use in convert- er max tracking rate formula. (see previous page for formula.) * not recommended. ** the use of a high quality thin-film resistor will provide better temperature stability than leaving open. * not recommended. ** the use of a high quality thin-film resistor will provide better temperature stability than leaving open. 8) for rdc-19222: this version is capable of +5v only operation. it accomplishes this with a charge pump technique that inverts the +5v supply for use as -5v, hence the +5v supply current doubles. the built-in -5 v inverter can be used by connecting pin 2 to 26, pin 17 to 22, a 10 f/10 vdc capacitor from pin 23 (negative ter- minal) to pin 25 (positive terminal), and a 47 f/10 vdc capac- itor from -5 v to gnd. the current drain from the +5 v supply doubles. no external -5 v supply is needed. when using the -5 v inverter, the max. tracking rate should be scaled for a velocity output of 3.5 v max. use the following equation to determine tracking rate used in the formula on page 4: tr (required) x (4.0) = tracking rate used in calculation (3.5) note: when using the highest bw and tracking rates, using the -5 v inverter is not recommended. higher tracking rates and carrier frequencies. tracking rate (nominally 4 v) is limited by two factors: velocity voltage saturation and maximum internal clock rate (nominally 1,333,333 hz). an understanding of their interaction is essential to extending performance. the general setup considerations section makes note of the selection of r v for the desired velocity scaling. r v is the input resistor to an inverting integrator with a 50 pf nominal feedback capacitor. when it integrates to -1.25 v, the converter counts up 1 lsb and when it integrates to +1.25 v, the converter counts down 1 lsb. when a count is taken, a charge is dumped on the capacitor; such that, the voltage on it changes 1.25 v in a direc- tion to bring it to 0 v. the output counts per second per volt input is therefore: 1 (r v x 50 pf x 1.25) as an example: calculate rv for the maximum counting rate, at a vel voltage of 4 v. the carrier frequency should be 1/10, or less, of the sampling frequency in order to have many samples per carrier cycle. the converter will work with reduced quadrature rejection at a carri- er frequency up to 1/4 the sampling frequency. carrier frequen- cy should be at least 3.5 times the bw in order to eliminate the chance of jitter.
6 bottom view 0.81 max (20.57) 0.30 max (7.62) 0.61 max (15.49) 0.15 max (3.81) 0.09 max (2.29) 0.100 (2.54) typ tol non cum 0.61 max (15.49) 0.15 max (3.81) 0.09 max (2.29) 0.600 (15.24) 0.115 max (2.92) 1 345 109876 11 12 14 15 20 19 18 17 16 pin numbers for ref. only terminals 0.025 0.001 (6.35 0.03) diam 0.125 (3.18) min length solder plated brass t1a t1b bottom view side view dimensions are shown in inches (mm). 1 5 3 6 10 11 15 16 20 t1a t1b synchro input resolver output -sin +sin -cos +cos s1 s3 s2 figure 5a. transformer layout and schematic (synchro input - 52034/52035) figure 5b. transformer layout and schematic (resolver input - 52036/52037/52038) 1 3 6 10 11 15 16 20 t1a t1b resolver input resolver output -sin +sin -cos +cos s1 s3 s2 s4 bottom view 0.81 max (20.57) 0.30 max (7.62) 0.61 max (15.49) 0.15 max (3.81) 0.09 max (2.29) 0.100 (2.54) typ tol non cum 0.61 max (15.49) 0.15 max (3.81) 0.09 max (2.29) 0.600 (15.24) 0.115 max (2.92) 1 345 109876 11 12 14 15 20 19 18 17 16 pin numbers for ref. only terminals 0.025 0.001 (6.35 0.03) diam 0.125 (3.18) min length solder plated brass t1a t1b bottom view side view dimensions are shown in inches (mm). * beta transformer ** 60 hz synchro transformers are active (require 15v dc power supplies) and are available in two temperature ranges; -1: -55 to +125 and -3: 0 to 70. 5d 24133** 60 reference reference 5d 52039** 60 synchro synchro 5c b-426* 400 reference reference 5b 52038 400 90 resolver 5b 52037 400 26 resolver 5b 52036 400 11.8 resolver 5a 52035 400 90 synchro 5a 52034 400 11.8 synchro figure number part number input frequency (hz) input voltage (vrms) input signal type table 6. transformers
7 1 5 6 10 input output bottom view 0.32 max (8.13) 0.61 max (15.49) 0.15 max (3.81) 0.09 max (2.29) 0.100 (2.54) typ tol non cum 13 25 109876 terminals 0.025 0.001 (6.35 0.03) diam 0.125 (3.18) min length solder-plated brass t1a side view dimensions are shown in inches (mm). 0.105 (2.66) 0.600 (15.24) 0.81 max (20.57) 0.125 min (3.17) figure 5c. transformer layout and schematic (reference input - b-426) b-426 1 5 6 10 rl rh rl rh s1 s3 s4 s2 1 3 6 10 11 15 20 16 external reference lo hi -s sin -r +r -vsum vel -vco digital output 16 cb bit inh em el a b +5v -5v +s +c -c cos agnd gnd rdc-19220 tib tia tia tib s1 s3 s2 resolution control } 52036(11.8v) 52037(26v) or 52038(90v) or 52034(11.8v) 52037(90v) or 1 3 10 6 16 11 15 20 5 or synchro input +s +c agnd gnd rs rc rb cbw cbw/10 rv 30k w 30k w figure 6. typical transformer connections 1.14 max (28.96) case is black and non-conductive 1.14 max (28.96) ? * s1 ? * s3 ? (+15 v) +15 v ? (-r) +s + * * (rh) ? s2 (rl) + * (v) ? v (+r) ? +c (-vs) ? -vs 52039 or 24133 0.21 0.3 (5.33 0.76) 0.85 0.010 (21.59 0.25) 0.175 0.010 (4.45 0.25) noncumulative tolerance 0.040 0.002 dia. pin. solder plated brass 0.42 (10.67) max. 0.25 (6.35) min. (bottom view) 0.13 0.03 (3.30 0.76) the mechanical outline is the same for the synchro input trans- former (52039) and the reference input transformer (24133), except for the pins. pins for the reference transformer are shown in parenthesis ( ) below. an asterisk * indicates that the pin is omitted. figure 5d. 60 hz synchro and reference transformer diagrams (synchro input - 52039 / reference input - 24133)
8 r 1 r 3 r 2 r 4 external ref lo hi resolver s4 s3 s1 s2 gnd +s -s sin cos -c +c a gnd -r +r notes: 1) resistors selected to limit vref peak to between 1 v and 4 v. 2) external reference lo is grounded, then r3 and r4 are not needed, and -r is connected to gnd. 10k w (1%) 10k w (1%) r 1 r 2 s3 s1 s2 +s -s sin cos -c +c a gnd s4 r 1 r 2 figure 7a. typical connections, 2 v resolver, direct input figure 7b. typical connections, x- volt resolver, direct input typical input connections figures 7 through 9 illustrate typical input configurations r2 2 = r1 + r2 x volt r1 + r2 should not load the resolver too much; it is recommended to use a r2 = 10k. r1 + r2 ratio errors will result in angular errors, 2 cycle, 0.1% ratio error = 0.029 peak error. note: the five external bw components as shown in figure 1 and 2 are necessary for the r/d to function. note: the five external bw components as shown in figure 1 and 2 are necessary for the r/d to function.
9 r i s1 s3 +s -s sin r f r i r f r i s4 s2 +c -c r f r i r f cos a gnd resolver input converter - + - + r i s1 s3 +s -s sin r f r i r f r i s4 s2 +c -c r f r i r f cos a gnd converter 810 12 15 13 2 3 1 6 16 7 4 5 - + - + resolver input ri x 2 vrms = resolver l-l rms voltage rf rf 3 6 k w s1 and s3, s2 and s4, and rh and rl should be ideally twisted shielded, with the shield tied to gnd at the converter. figure 8a. differential resolver input figure 8b. differential resolver input, using ddc-49530 (11.8 v) or ddc-49590 (90 v) s1 and s3, s2 and s4, and rh and rl should be ideally twisted shielded, with the shield tied to gnd at the converter. for ddc-49530 or ddc-57470: ri = 70.8 k w , 11.8 v input, synchro or resolver. for ddc-49590: ri = 270 k w , 90 v input, synchro or resolver. maximum addition error is 1 minute. note: the five external bw components as shown in figure 1 and 2 are necessary for the r/d to function. note: the five external bw components as shown in figure 1 and 2 are necessary for the r/d to function.
10 r i s1 s3 +s -s sin r f r i r f r i s2 +c -c r /2 i cos a gnd converter r i r / 3 f r / 3 f - + - + r i s1 s3 +s -s sin r f r i r f r i s2 +c -c r /2 i cos a gnd converter 8 15 11 15 14 2 3 1 6 16 7 4 5 r i 9 r / 3 f r / 3 f 10 - + - + ri x 2 vrms = synchro l-l rms voltage rf rf 3 6 k w s1, s2, and s3 should be triple twisted shielded; rh and rl should be twisted shielded, in both cases the shield should be tied to gnd at the converter. figure 9a. synchro input figure 9b. synchro input, using ddc-49530/ddc-57470 (11.8 v) or ddc-49590 (90 v) s1, s2, and s3 should be triple twisted shielded; rh and rl should be twisted shielded, in both cases the shield should be tied to gnd at the converter. 90 v input = ddc-49590: ri = 270 k w , 90 v input, synchro or resolver. 11.8 v input = ddc-49530 or ddc-57470: ri = 70.8 k w , 11.8 v input, synchro or resolver. maximum addition error is 1 minute. note: the five external bw components as shown in figure 1 and 2 are necessary for the r/d to function. note: the five external bw components as shown in figure 1 and 2 are necessary for the r/d to function.
11 8 10 -vco vel +5 v -5 v 100 k w (offset) 100 r v 0.8 r v 0.4 r (scaling) v rdc-19220 r + ref c lag - ref + ref - ref r + ref c lead - ref + ref - ref figure 10. velocity trimming figure 11. phase-shift compensation x c tan j = r where j = desired phase-shift 1 x c = 2 p fc where f = carrier frequency where c = capacitance reduced power supply currents when r s = 30 k w (tracking rate is not being pushed), nominal power supply current can be cut from 14 to 9 ma by setting r c = 53 k w . transformer isolation system requirements often include electrical isolation. there are transformers available for reference and synchro/resolver signal isolation. table 6 includes a listing of the most common trans- formers. the synchro/resolver transformers reduce the voltage to 2 vrms for a direct connection to the converter. see figures 5a, 5b, 5c and 5d for transformer layouts and schematics, and figure 6 for typical connections. dc inputs as noted in table 1 the rdc-19220 will accept dc inputs. it is necessary to set the ref input to dc by tying +ref to +5 v and -ref to gnd or -5 \/. (with dc inputs, the converter will function from 0 to 180 and bit will remain at logic 0.) velocity trimming rdc-19220 series specifications for velocity scaling, reversal error and offset are contained in table 1. velocity scaling and offset are externally trimmable for applications requiring tighter specifications than those available from the standard unit. fig- ure 9 shows the setup for trimming these parameters with external pots. it should also be noted that when the resolution is changed, vel scaling is also changed. since the vel output is from an integrator with capacitor feedback, the vel voltage can- not change instantaneously. therefore, when changing resolu- tion while moving there will be a transient with a magnitude pro- portional to the velocity and a duration determined by the con- verter bandwidth. increased tracking/decreased settling (gear shifting) connecting the bit output to the resolution control lines (a and b) wil change the resolution of the converter down (gear shift) make the converter settle faster and track at higher rates. the converter bandwidth is independent of the resolution. additional error sources quadrature voltages in a resolver or synchro are by definition the resulting 90 fundamental signal in the nulled out error voltage (e) in the converter. this voltage is due to capacitive or inductive coupling in the synchro or resolver signals. a digital position error will result due to the interaction of this quadrature voltage and a reference phase shift between the converter signal and refer- ence inputs. the magnitude of this error is given in the following formula: magnitude of error = (quadrature voltage/f.s.signal) ? tan a where: magnitude of error is in radians quadrature voltage is in volts
12 +s -s sin ar r +c -c cos r - + - + r r r ar c 1 br 2r 2r r br +ref -ref r c 2 2 wire lvdt ref in r 2 v fs = 2 v figure 12a. 2-wire lvdt direct input table 7. lvdt output code (14-bit r/d or 12-bit lvdt) lvdt output msb lsb + over full travel + full travel -1 lsb +0.5 travel +1 lsb null - 1 lsb -0.5 travel - full travel - over full travel 01 xxxx xxxx xxxx 00 1111 1111 1111 00 1100 0000 0000 00 1000 0000 0001 00 1000 0000 0000 00 0111 1111 1111 00 0100 0000 0000 00 0000 0000 0000 11 xxxx xxxx xxxx c 1 = c 2 , set for phase lag = phase lead through the lvdt. note: table 7 refers to figure 12c. full scale signal is in volts a = signal to ref phase shift an example of the magnitude of error is as follows: let: quadrature voltage = 11.8 mv let: f.s. signal = 11.8 v let: a = 6 then: magniture of error = 0.36 min @ 1 lsb in the 16th bit. note: quadrature is composed of static quadrature which is specified by the synchro or resolver supplier plus the speed volt- age which is determined by the following formula: speed voltage = (rotational speed/carrier frequency) ? f.s. signal where: speed voltage is the quadrature due to rotation. rotation speed is the rps (rotations per second) of the synchro or resolver. carrier frequency is the ref in hz. a circuit to lead or lag the reference into the converter will compensate for phase-shift between the signal and the refer- ence to reduce the effects of the quadrature is illustrated in fig- ure 11. lvdt mode as shown in table 1 the rdc-19220 series units can be made to operate as lvdt-to-digital converters by connecting resolution control inputs a and b to 0, 1, or the -5 volt supply. in this mode the rdc-19220 series functions as a ratiometric tracking linear converter. when linear ac inputs are applied from a lvdt the converter operates over one quarter of its range. this results in two less bits of resolution for lvdt mode than are pro- vided in resolver mode. figure 12b shows a direct lvdt 2 vrms full scale input. some ldvt output signals will need to be scaled to be compatible with the converter input. figure 12c is a schematic of an input scal- ing circuit applicable to 3-wire lvdts. the value of the scaling
13 +s -s sin -c cos -ref +ref a gnd +c rdc-19220 +s -s sin ar r +c -c cos r' - + - + r/2 r r ar br 2r' 2r' r' br +ref -ref r' r' r v b v a v b v a lvdt output +fs -fs null cos sin rdc-19220 input -fs +fs null 1v 2v figure 12b. 3-wire lvdt direct input notes: 1. r' 3 10 k w 2. consideration for the value of r is lvdt loading. 1 1 b = = v a null v b null 2 a = (v a - v b ) max a sin = 1+ (v a - v b ) 2 a cos = 1- (v a - v b ) 2 figure 12c. 3-wire lvdt scaling circuit
14 data data valid 300 ns max inhibit 100 ns max enable 150 ns max data data valid high z high z 1/40 f s (375 nsec nominal) cb 50 ns data data valid data valid figure 13. inhibit timing figure 14. enable timing figure 15. converter busy timing constant a is selected to provide an input of 2 vrms at full stroke of the lvdt. the value of scaling constant b is selected to pro- vide an input of 1 vrms at null of the lvdt. suggested compo- nents for implementing the input scaling circuit are a quad op- amp, such as a 4741 type, and precision film resistors of 0.1% tolerance. figure 12a illustrates a 2-wire lvdt configuration. data output of the rdc-19220 series is binary coded in lvdt mode. the most negative stroke of the lvdt is represented by all zeros and the most positive stroke of the lvdt is represent- ed by all ones . the most significant 2 bits (2 msbs) may be used as overrange indicators. positive overrange is indicated by code 01 and negative overrange is indicated by code 11 (see table 7). inhibit, enable, and cb timing the inhibit (inh) signal is used to freeze the digital output angle in the transparent output data latch while data is being trans- ferred. application of an inhibit signal does not interfere with the continuous tracking of the converter. as shown in figure 13, angular output data is valid 300 ns maximum after the applica- tion of the negative inhibit pulse. output angle data is enabled onto the tri-state data bus in two bytes. enable msbs (em) is used for the most significant 8 bits and enable lsbs (el) is used for the least significant 8 bits. as shown in figure 14, output data is valid 150 ns maximum after the application of a negative enable pulse. the tri-state data bus returns to the high impedance state 100 ns maximum after the rising edge of the enable signal. the converter busy (cb) signal indicates that the tracking con- verter output angle is changing 1 lsb. as shown in figure 15, output data is valid 50 ns maximum after the middle of the cb pulse. cb pulse width is 1/40 fs, which is nominally 375 ns. built-in-test (bit) the built-ln-test output (bit) monitors the level of error from the demodulator. this signal is the difference in the input and output angles and ideally should be zero. however, if it exceeds approx- imately 100 lsbs (of the selected resolution) the logic level at bit will change from a logic 1 to a logic 0. this condition will occur during a large step and reset after the converter settles out. bit will also change to logic 0 for an over- velocity condition, because the converter loop cannot maintain input/output or if the converter malfunctions where it cannot maintain the loop at a null. bit will also be set low for a detected total loss-of-signal (los). the bit signal may pulse during cer- tain error conditions (i.e., converter spin around or signal ampli- tude on threshold of los). los will be detected if both sin and cos input voltages are less than 800 mv peak.
15 lsb +1 lsb el -5 v rdc-19220 cb/nrp r1 2k d1 1n4148 c1 220 pf 4 5 c2 220 pf 13 12 c3 120 pf 9 10 r2 2k u2a 74ac86 2 1 a b nrp 8 6 11 3 note: cmos logic is recomended. ttl and ttl compatable logic will skew the delays. u2d 74ac86 u2b 74ac86 u2c 74ac86 r3 2k figure 16b. filtered/buffered encoder emulator circuit lsb +1 lsb el -5 v cb (zi) (zi) a b figure 16a. incremental encoder emulation encoder emulation the rdc-19220 can be made to emulate incremental optical encoder output signals, where such an interface is desired. this is accomplished by tying el to -5 v, whereby cb becomes zero index (zl) logic 1 at all 0s, the lsb+1 becomes a, and the exclu- sive-or of the lsb and lsb+1 becomes b emulating a quad b signals as illustrated in figure 16a. also, the lsb byte is always enabled. figure 16b illustrates a more detailed circuit with delays and filtering to eliminate potential glitch due to data skew and rise/fall differences caused by logic loading.
16 pinout function tables by model number the following tables detail pinout functions by the ddc model number. the rdc-19220 has differential inputs but requires both 5 v power supplies. the rdc-19222 has differential inputs and can be used with the +5 v only option. # name # name 1 el 44 bit 16 (lsb) 2 +5 v 43 bit 8 3 a 42 bit 15 4 b 41 bit 7 5 inh 40 bit 14 6 +ref 39 bit 6 7 -ref 38 bit 13 8 -vco 37 bit 5 9 -vsum 36 bit 12 10 vel 35 bit 4 11 +c 34 bit 11 12 cos 33 bit 3 13 -c 32 bit 10 14 +s 31 bit 2 15 sin 30 bit 9 16 -s 29 bit 1 (msb) 17 -5 v 28 cb 18 rs 27 bit 19 rc 26 +5c (+5 v) 20 em 25 +cap 21 a gnd 24 gnd 22 -5v (-5 v) 23 -cap notes: 1. when -5 v is applied to pin 1 (el), converter busy (cb) becomes zero index (zi). 2. when using the built-in -5 v inverter: connect pin 2 to 26, pin 17 to 22, and a 10 f/10 vdc capacitor from pin 23 (negative terminal) to pin 25 (positive terminal). connect a 47 f/10 vdc capacitor from -5 v to gnd. the current drain from the +5 v supply doubles. no external -5 v supply is needed. built-in-test bit 21 ground gnd 20 converter busy cb 22 analog ground a gnd 19 msb bit 1 23 enable msbs em 18 bit 9 24 current set r c 17 bit 2 25 sampling set r s 16 bit 10 26 power supply -5 v 15 bit 3 27 signal input -s 14 bit 11 28 signal output +sin 13 bit 4 29 signal input +s 12 bit 12 30 signal input -c 11 bit 5 31 signal output cos 10 bit 13 32 signal input +c 9 bit 6 33 velocity output vel 8 bit 14 34 vel sum point -vsum 7 bit 7 35 neg vco input -vco 6 bit 15 36 -reference input -ref 5 bit 8 37 +reference input +ref 4 lsb bit 16 38 inhibit inh 3 enable lsbs (see note) el 39 resolution control b 2 power supply +5 v 40 resolution control a 1 description name # description name table 8. rdc-19220 pinouts (40-pin) # table 9. rdc-19222 pinouts (44-pin, +5 v only) -5 -15 3 terminal negative regulator -5 6.8 v zener 10.2 v zener -12 -5 -5 -15 -15 5.1 v zener 79lo5 figure 17. typical -5 volt circuits typical-5 volt circuits since the 40-pin ddip rdc-19220 does not have a pinout for the -5 v inverter, it may be necessary to create a -5 v from other supplies on the board. figure 17 illustrates several possibili- ties.
17 2.035 - 2.065 (40 pin) (51.65 - 52.45) 0.590 0.010 (14.99 0.25) dimensions shown are in inches (mm). 0.580 - 0.695 (14.73 - 17.65) 0.150 - 0.160 (3.81 - 4.06) 0.120 - 0.160 (3.05 - 4.06) 0.012 - 0.025 (0.31 - 0.64) 0.090 - 0.110 (2.29 - 2.79 0.008 - 0.015 (0.20 - 0.38) 0.030 - 0.070 (0.76 - 1.78) 0.010 - 0.020 (0.25 - 0.51) 2.000 0.020 (50.8 0.51) 0.590 0.010 (14.99 0.25) 0.100 0.010 typ (2.54 0.25) 0.018 0.006 typ (0.46 0.15) 0.050 0.020 typ (1.27 0.51) 0.012 0.004 typ (0.31 0.10) +0.050 0.600 - 0.020 +1.27 (15.25 ) - 0.51 dimensions shown are in inches (mm). 1 20 0.125 0.020 (3.18 0.508) 0.050 0.010 (1.27 0.25) 0.085 0.010 (2.16 0.25) 40 21 pin numbers for ref only 0.095 0.010 (2.41 0.25) figure 18. rdc-19220 (40-pin ddip) plastic package mechanical outline figure 19. rdc-19220 (40-pin ddip) ceramic package mechanical outline
18 0.620 sq. nom (15.75) pin 1 identifier 0.230 (5.84) 0.650 sq. nom (16.51) 0.690 sq. nom (17.53) 0.325 (8.26) 0.050 nom (1.27) dimensions shown are in inches (mm) 0.045 x 45? chfr (1.14) 0.045 x 45? chfr (1.14) 0.170 nom (4.32) 0.149 nom (3.79) 0.021 nom (0.53) 0.098 nom (2.49) 0.015 nom (0.38) 0.026 nom (0.66) 0.072 nom (1.83) 0.088 nom (2.24) 0.010 x 45? chfr (3) (0.25) 640 0.325 (8.26) 0.630 0.020 typ (16.00 0.51) 0.500 0.010 (12.70 0.25) dimensions shown are in inches (mm) 0.020 x 45? (0.51) chamfer (orientation mark) 0.040 x 45? chamfer (1.02) (3 places) 0.113 (ref) (2.87) 0.065 0.007 (1.65 0.18) 640 0.075 0.010 (1.91 0.25) 17 18 28 29 39 1 0.075 0.010 (1.91 0.25) 0.500 0.010 (12.70 0.25) 0.050 typ (1.27) 7 0.650 sq 0.010 (16.51 0.25) 0.690 0.010 typ (17.53 0.25) pin numbers for ref only 0.017 typ (0.43) figure 20. rdc-19222 (44-pin plastic j-lead) mechanical outline figure 21. rdc-19222 (44-pin ceramic j-lead) mechanical outline
19 0.870 max (22.10) 0.250 0.005 (6.35 0.13) dimensions shown are in inches (mm). +0.025 0.325 -0.015 +0.64 (8.26 ) -0.38 0.13 0.005 (3.30 0.13) 0.020 min (0.51) 0.125 min (3.18) 0.075 0.015 (1.91 0.38) 0.018 0.003 (0.46 0.08) 0.100 typ (2.54) 0.320 - 0.300 (8.13 - 7.62) 0.015 0.009 (0.38 0.23) r11 r10 r9 16 15 14 13 r8 r7 r6 12 11 10 9 r1 r2 12 3 r5 78 r3 r4 45 6 figure 23b. 16-pin surface mount thin-film resistor network mechanical outline (ddc-57470) figure 22. (ddc-49530, ddc-57470, ddc-49590) layoutand resistor values (see table 10) ddc-49530/ddc-57470 resistor values (11.8 v inputs) table 10. front-end thin-film resistor networks (see figure 22) symbol abs value ( w w ) tol (%) rel to rel value ( w w ) tol (%) tcr(ppm) r1 70.8 k 0.1 25 r2 r3 r1 r4 12 k 12 k 0.02 0.02 2 2 r4 r1 70.8 k 0.02 2 r5 r1 70.8 k 0.02 2 r6 r1 35.4 k 0.02 2 r7 r6 6.9282 k 0.02 2 r8 r6 5.0718 k 0.02 2 r9 r11 5.0718 k 0.02 2 r10 r11 6.9282 k 0.02 2 r11 r1 70.8 k 0.02 2 ddc-49590 resistor values (90 v inputs) r1 270 k 0.1 25 r2 r1 6 k 0.02 2 r3 r4 6 k 0.02 2 r4 r1 270 k 0.02 2 r5 r1 270 k 0.02 2 r6 r1 135 k 0.02 2 r7 r6 3.4641 k 0.02 2 r8 r6 2.5359 k 0.02 2 r9 r11 2.5359 k 0.02 2 r10 r11 3.4641 k 0.02 2 r11 r1 270 k 0.02 2 .405 0.299 (7.6) dimensions shown are in inches (mm). 0.406 (10.3) 0.014 (.36) 0.342 (8.7) 7 45 0.101 (2.6) 0.092 (2.3) 0.009 (0.23) figure 23a. 16-pin thin-film resistor network mechanical outline (ddc-49530, ddc-49590)
20 the information in this data sheet is believed to be accurate; however, no responsibility is assumed by data device corporation for its use, and no license or rights are granted by implication or otherwise in connection therewith. specifications are subject to change without notice. g-08/99-500 ordering information rdc-1922x-xxxx supplemental process requirements: t = tape and reel accuracy: 2 = 4 minutes + 1 lsb 3 = 2 minutes + 1 lsb process requirements: 0 = standard ddc processing, no burn-in* 1 = mil-prf-38534 compliant (-55 to +125c devices only) 2 = 168 hour burn-in at +125c (-55 to +125c devices only) temperature grade: 1 = -55 to +125c 2 = -40 to +85c 3 = 0 to +70c package: 0 = 40-pin ddip** 2 = 44-pin j-lead** with +5 volt-only option *10x not available. **plastic for -20x and -3xx, ceramic for -1xx. notes: 1) ddc reserves the right to supply ceramic packages in place of plastic packages. 2) consult factory for external component selection software. thin-film resistor networks: (operating temperature range: -55 to +125c) ddc-49530 = 11.8 v input, dip ddc-49590 = 90 v input, dip ddc-57470 = 11.8 v input, surface mount printed in the u.s.a. ilc data device corporation registered to iso 9001 file no. a5976 105 wilbur place, bohemia, new york 11716-2482 for technical support - 1-800-ddc-5757 ext. 7389 or 7413 headquarters - tel: (631) 567-5600 ext. 7389 or 7413, fax: (631) 567-7358 southeast - tel: (703) 450-7900, fax: (703) 450-6610 west coast - tel: (714) 895-9777, fax: (714) 895-4988 europe - tel: +44-(0)1635-811140, fax: +44-(0)1635-32264 asia/pacific - tel: +81-(0)3-3814-7688, fax: +81-(0)3-3814-7689 world wide web - http://www.ddc-web.com

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