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october 2009 doc id 13448 rev 7 1/49 1 stts424e02 memory module temperature sensor with a 2 kb spd eeprom features stts424e02 includes a jedec jc 42.4 compatible temperature sensor, integrated with industry standard 2 kbit serial presence detect (spd) eeprom temperature sensor temperature sensor resolution: 0.25 c (typ)/lsb temperature sensor accuracy: ? 1 c from +75 c to +95 c ? 2 c from +40 c to +125 c ? 3 c from ?40 c to +125 c adc conversion time: 125 ms (max) supply voltage: 2.7 v to 3.6 v maximum operating supply current: 210 a (eeprom standby) hysteresis selectable set points from: 0, 1.5, 3, 6.0 c ambient temperature sensing range: ?40 c to +125 c 2 kb spd eeprom functionality identical to st?s m34e02 spd eeprom permanent and reversible software data protection for the lower 128 bytes single supply voltage: 2.7 v to 3.6 v byte and page write (up to 16 bytes) self-time write cycle (5 ms, max) automatic address incrementing operating temperature range: ? ?40 c to +85 c (da package only) ? ?40 c to +125 c (dn package only) two-wire bus 2-wire smbus/i 2 c - compatible serial interface temperature sensor supports smbus timeout supports up to 400 khz transfer rate packages dn: 2 mm x 3 mm tdfn8, height: 0.80 mm (max) (a) da: 2 mm x 3 mm dfn8, height: 0.90 mm (max) rohs compliant , halogen-free a. compliant to jedec mo-229, wced-3 b. contact local st sales office for availability dfn8 (da) (b) 2 mm x 3 mm (max height 0.90 mm) tdfn8 (dn) (a) 2 mm x 3 mm (max height 0.80 mm) www.st.com
contents stts424e02 2/49 doc id 13448 rev 7 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 serial communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 device type identifier (dti) code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2.1 a0, a1, a2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2.2 v ss (ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2.3 sda (open drain) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2.4 scl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2.5 event (open drain) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2.6 v dd (power) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 temperature sensor operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1 smbus/i 2 c communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.2 smbus/i 2 c slave sub-address decoding . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.3 smbus/i 2 c ac timing consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4 temperature sensor registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1 capability register (read-only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1.1 alarm window trip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1.2 critical trip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.2 configuration register (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2.1 event thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2.2 interrupt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2.3 comparator mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2.4 shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2.5 event output pin functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.3 temperature register (read-only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.3.1 temperature format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.4 temperature trip point registers (r/w ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.5 manufacturer id register (read-only) . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.6 device id and device revision id register (read-only) . . . . . . . . . . . . . . . 26
stts424e02 contents doc id 13448 rev 7 3/49 5 spd eeprom operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.1 2 kb spd eeprom operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.2 internal device reset - spd eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.3 memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.4 setting the write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.4.1 swp and cwp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.4.2 pswp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.5 write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.5.1 byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.5.2 page write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.5.3 write cycle polling using ack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.6 read operations - spd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.6.1 random address read - spd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.6.2 current address read - spd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.6.3 sequential read - spd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.6.4 acknowledge in read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.7 initial delivery state - spd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6 use in a memory module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.1 programming the spd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.1.1 dimm isolated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.1.2 dimm inserted in the application motherboard . . . . . . . . . . . . . . . . . . . 36 7 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 10 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 11 package marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 12 landing pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 13 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
list of tables stts424e02 4/49 doc id 13448 rev 7 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 2. ac smbus and i 2 c compatibility timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 3. temperature sensor registers summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 4. pointer register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 5. pointer register select bits (type, width, and default values). . . . . . . . . . . . . . . . . . . . . . . . 17 table 6. capability register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 7. capability register bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 8. configuration register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 9. configuration register bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 10. hysteresis as applied to temperature movement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 11. legend for figure 9: event output boundary timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 12. temperature register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 13. temperature register bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 14. temperature trip point register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 15. alarm temperature upper boundary register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 16. alarm temperature lower boundary register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 17. critical temperature register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 18. manufacturer id register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 19. device id and device revision id register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 20. device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 21. operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 22. acknowledge when writing data or de fining the write-protection (instructions with r/w bit=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 23. acknowledge when reading the write protection (instructions with r/w bit=1). . . . . . . . . . 35 table 24. dram dimm connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 25. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 26. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 27. dc/ac characteristics - temperature sensor component with eeprom . . . . . . . . . . . . . . 38 table 28. dfn8 ? 8-lead dual flat, no-lead (2 mm x 3 mm) mechanical data (da) . . . . . . . . . . . . . . 41 table 29. tdfn8 ? 8-lead thin dual flat, no-lead (2 mm x 3 mm) mechanical data (dn) . . . . . . . . . . 42 table 30. carrier tape dimensions for dfn8 and tdfn8 packages . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 31. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 32. parameters for landing pattern - tdfn package (dn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 33. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
stts424e02 list of figures doc id 13448 rev 7 5/49 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 2. dfn8 and tdfn8 connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 3. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 4. smbus/i2c write to pointer register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 5. smbus/i 2 c write to pointer register, followed by a read data word. . . . . . . . . . . . . . . . . . . 12 figure 6. smbus/i 2 c write to pointer register, followed by a write data word . . . . . . . . . . . . . . . . . . 13 figure 7. smbus/i 2 c timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 8. hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 9. event output boundary timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 10. result of setting the write protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 11. setting the write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 12. write mode sequences in a non write-protected area of spd . . . . . . . . . . . . . . . . . . . . . . 31 figure 13. write cycle polling flowchart using ack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 14. read mode sequences - spd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 15. dfn8 ? 8-lead dual flat, no-lead (2 mm x 3 mm) package outline (da) . . . . . . . . . . . . . . . 41 figure 16. tdfn8 ? 8-lead thin dual flat, no-lead (2 mm x 3 mm) package outline (dn) . . . . . . . . . . 42 figure 17. carrier tape for dfn8 and tdfn8 packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 18. da package topside marking information (dfn-8l) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 19. dn package topside marking information (tdfn-8l). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 20. landing pattern - tdfn package (dn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
description stts424e02 6/49 doc id 13448 rev 7 1 description the stts424e02 is targeted for dimm modules in mobile personal computing platforms (laptops), server memory modules and other industrial applications. the thermal sensor (ts) in the stts424e02 is compliant with the jedec specification jc 42.4, which defines memory module thermal sensors requirements for mobile platforms. the 2 kbit serial presence detect (spd) i 2 c-compatible electrically erasable programmable memory (eeprom) in the stts424e02 is organized as 256 x8 bits and is functionally identical to the industry standard m34e02. the ts-spd eeprom combination provides space as well as cost savings for mobile and server platform dual inline memory modules (dimm) manufacturers, as it is packaged in the compact 2 mm x 3 mm 8-lead dfn package which is available in two variations. the da package has a maximum height of 0.90 mm. the dn package has an identical footprint as the da package with a thinner maximum height of 0.80 mm. the dn package is compliant to jedec mo-229, variation wced-3. the temperature sensor includes a band gap-based temperature sensor and 10-bit analog- to-digital converter (adc) which monitor and digitize the temperature to a resolution of up to 0.25 c. the typical accuracies over these temperature ranges are: 3 c over the full temperature measurement range of ?40 c to 125 c, 2 c in the +40 c to +125 c temperature range, and 1 c in the +75 c to +95 c temperature range. the temperature sensor in the stts424e02 is specified for operating at supply voltages from 2.7 v to 3.6 v. operatin g at 3.3 v, the supply current is 100 a (typ) with eeprom in standby mode. the on-board sigma delta adc converts the measured temperature to a digital value that is calibrated in c. for fahrenheit applications, a lookup table or conversion routine is required. the stts424e02 is factory-calibrated and requires no external components to measure temperature. the digital temperature sensor component has user-programmable registers that provide the capabilities for dimm temperature-sensing applications. the open drain event output pin is active when the monitoring temperature exceeds a programmable limit, or it falls above or below an alarm window. the user has the option to set the event output as a critical temperature output. this pin can be configured to operate in either a comparator mode for thermostat operation or in interrupt mode. the 2 kbit serial eeprom memory in the st ts424e02 has the ability to permanently lock the data in its first half (u pper) 128 bytes (locations 00h to 7fh). this facility has been designed specifically for use in dram dimms with spd. all of the information concerning the dram module configuration (e.g. access speed, size, and organization) can be kept write protected in the first half of the memory. the second half (lower) 128 bytes of the memory can be write protected using two different software write protection mechanisms. by sending the device a specific sequence, the first 128 bytes of the memory become write protected: permanently or resettable. in the st ts424e02 the eeprom write control (wc ) is always held low. thus, the write protection of the memory array is dependent on whether the software protection has been set.
stts424e02 serial communications doc id 13448 rev 7 7/49 2 serial communications the stts424e02 has a simple 2-wire smbus?/i 2 c-compatible digital serial interface which allows the user to access both the 2 kbit serial eeprom and the data in the temperature register at any time. it communicates via the serial interface with a master controller which operates at speeds of up to 400 khz. it also gives the user easy access to all of the stts424e02 registers in order to customize device operation. 2.1 device type identifier (dti) code the jedec temperature s ensor and eeprom each have their own unique i 2 c address, which ensures that there are no compatibility or data tran slation issues. this is due to the fact that each of the devices have their own 4-bit dti code, while the remaining three bits are configurable. this enables the eeprom and thermal sensors to provide their own individual data via their unique addresses and still not interfere with ea ch others? operation in any way. the dti codes are: '0011' for the ts, and '1010' for addressing the eeprom memory array, and ?0110? to access the so ftware write protection settings of the eeprom. note: the eeprom in the stts 424e02 package has its wc pin internally tied to the v ss (ground) pad inside the package while the a0, a1, and a2 pins in the logic diagram (see figure 1 on page 8 ) correspond to the ch ip enable pins e0, e1 and e2 of eeprom.
serial communications stts424e02 8/49 doc id 13448 rev 7 figure 1. logic diagram 1. sda and event are open drain. note: see section 2.2: pin descriptions on page 10 for details. figure 2. dfn8 and tdfn8 connections (top view) 1. sda and event are open drain. table 1. signal names pin symbol description direction 1 a0 serial bus address selection pin. can be tied to v ss or v dd . input 2 a1 serial bus address selection pin. can be tied to v ss or v dd . input 3 a2 serial bus address selection pin. can be tied to v ss or v dd . input 4v ss supply ground. 5sda (1) 1. sda and event are open drain. serial data. input/output 6 scl serial clock. input 7 event (1) event output pin. open drain and active-low. output 8v dd supply power (2.7 v to 3.6 v). s da (1) v dd s tt s 424e02 v ss s cl event (1) a 2 a 1 a 0 ai12261 1 sda (1) gnd scl event (1) a1 a0 v dd a2 2 3 4 8 7 6 5 ai12262
stts424e02 serial communications doc id 13448 rev 7 9/49 figure 3. block diagram temperature sensor adc address pointer register 1 2 3 4 5 6 capability register configuration register temperature register upper register lower register critical register manufacturer id device id/ revision logic control comparator timing smbus/i 2 c interface 2kb spd eeprom software write protect 7 8 v dd scl sda a0 a1 a2 v ss v ss event wc e0 e1 e2 ai12278a
serial communications stts424e02 10/49 doc id 13448 rev 7 2.2 pin descriptions 2.2.1 a0, a1, a2 a2, a1, and a0 are selectable address pins for the 3 lsbs of the i 2 c interface address. they can be set to v dd or gnd to provide 8 unique address selections. these pins are internally connected to the e2, e1, e0 (chip selects) of eeprom. 2.2.2 v ss (ground) this is the reference for the power supply. it must be connected to system ground. 2.2.3 sda (open drain) this is the serial data input/output pin. 2.2.4 scl this is the serial clock input pin. 2.2.5 event (open drain) this output pin is open drain and active-low, and functions as an alert interrupt. 2.2.6 v dd (power) this is the supply voltage pin, and ranges from +2.7 v to +3.6 v.
stts424e02 temperature sensor operation doc id 13448 rev 7 11/49 3 temperature sensor operation the temperature sensor continuously monitors the ambient temperature and updates the temperature data register at least eight times per second. temperature data is latched internally by the device and may be read by software from the bus host at any time. the smbus/i 2 c slave address selection pins allow up to 8 such devices to co-exist on the same bus. this means that up to 8 memory modules can be supported, given that each module has one such slave device address slot. after initial power-on, the configuration registers are set to the default values. the software can write to the configuration register to set bits per the bit definitions in section 3.1: smbus/i 2 c communications . for details of operation and usage of 2 kb spd eeprom, refer to section 5: spd eeprom operation . 3.1 smbus/i 2 c communications the registers in this device are selected by the pointer register. at power-up, the pointer register is set to ?00?, which is the capability register location. the poi nter register latches the last location it was set to. each data register falls into one of three types of user accessibility: 1. read-only 2. write-only, and 3. write/read same address a write to this device will always include t he address byte and the pointer byte. a write to any register other than the pointer register, requires two data bytes. reading this device is achieved in one of two ways: if the location latched in the pointer register is correct (most of the time it is expected that the pointer register will po int to one of the read temperature regi sters because that will be the data most freq uently read), then th e read can simply c onsist of an address byte, followed by retrieval of the two data bytes. if the pointer register needs to be set, then an address byte, pointer byte, repeat start, and another address byte will accomplish a read. the data byte transfers the msb first. at the end of a read, this device can accept either an acknowledge (ack) or no acknowledge (noack) status from the master. the noack status is typically used as a signal for the slave that the master has read its last byte. this device subsequently takes up to 125 ms to measure the temperature. note: stts424e02 does not initiate cloc k stretching which is an optional i 2 c bus feature.
temperature sensor operation stts424e02 12/49 doc id 13448 rev 7 figure 4. smbus/i 2 c write to pointer register figure 5. smbus/i 2 c write to pointer register, followed by a read data word 11 99 0 start by master address byte pointer byte ack by stts424e02 ack by stts424e02 0 1 1 a2 a1 a0 r/w 0 0 0 0 0 d2 d1 d0 scl sda ai12264 1919 ack by master no ack by master stop cond. by master d7 d6 d5 d4 d3 d2 d1 d0 msb data byte lsb data byte 11 99 0 start by master address byte pointer byte ack by stts424e02 ack by stts424e02 011a2a1a0r/w 00000d2d1d0 scl sda d9 d10 d11 d12 d13 d14 d15 d8 19 repeat start by master ack by stts424e02 0 0 1 1 a2 a1 a0 r/w address byte scl (continued) sda (continued) ai12265
stts424e02 temperature sensor operation doc id 13448 rev 7 13/49 figure 6. smbus/i 2 c write to pointer register, followed by a write data word 3.2 smbus/i 2 c slave sub-address decoding the physical address for the ts is different than th at used by the eeprom. the ts physical address is binary 0011a2a1a0rw, where a2, a1, and a0 are the three slave sub- address pins, and the lsb ?rw? is the read/write flag. the eeprom physical address is binary 1 010a2a1a0rw for the memory array and is 0110a2a1a0rw for permanently set write protection mode. 1919 ack by stts424e02 ack by stts424e02 stop cond. by master d7 d6 d5 d4 d3 d2 d1 d0 msb data byte lsb data byte 11 99 0 start by master address byte pointer byte ack by stts424e02 ack by stts424e02 011a2a1a0r/w 00000d2d1d0 scl scl (continued) sda d8 d9 d10 d11 d12 d13 d14 d15 sda (continued) ai14012
temperature sensor operation stts424e02 14/49 doc id 13448 rev 7 3.3 smbus/i 2 c ac timing consideration in order for this device to be both smbus- and i 2 c-compatible, it comp lies to a subset of each specification. th e requirements which enable this device to co-exist with devices on either an smbus or an i 2 c bus include: the smbus minimum clock frequency is required. the 300 ns smbus data hold time (thd:dat) is required (see figure 7 and table 2 on page 15 . the smbus timeout is maximum 50 ms (temperature sensor only). note: since the voltage levels are specified onl y within 3.3 v 10%, there are no compatibility concerns with the smbus/i 2 c dc specifications. figure 7. smbus/i 2 c timing diagram a12266 scl p tsu:sto tsu:sta s sda v ih v il v ih v il tsu:dat tf thd:dat tr thigh tlow thd:sta tbuf s p
stts424e02 temperature sensor operation doc id 13448 rev 7 15/49 table 2. ac smbus and i 2 c compatibility timings symbol parameter da package dn package units min max min max t buf bus free time between stop (p) and start (s) conditions 4.7 ? 1.3 ? s t hd:sta hold time after (repeated) start condition. after this period, the first clock cycle is generated. 4.0 ? 0.6 ? s t su:sta (1) repeated start condition setup time 4.7 ? 0.6 ? s t high clock high period 4.0 ? 0.6 ? s t low (2) clock low period 4.7 ? 1.3 ? s t f clock/data fall time ? 300 ? 300 ns t r clock/data rise time ? 1000 ? 300 ns t su:dat data setup time 250 ? 100 ? ns t hd:dat data hold time 300 ? 300 ? ns t su:sto stop condition setup time 4.0 ? 0.6 ? s t w (3) write time for eeprom ? 10 ? 10 ms f scl smbus/i 2 c clock frequency 10 100 10 400 khz t timeout bus timeout (temperature sensor only) 25 50 25 50 ms 1. for a restart condition, or following a write cycle. 2. stts424e02 will not initiate clock stretching which is an i 2 c bus optional feature. 3. this parameter reflects maximum write time for eeprom.
temperature sensor registers stts424e02 16/49 doc id 13448 rev 7 4 temperature sensor registers the temperature sensor component is comprised of various user-programmable registers. these registers are required to write their corresponding addresses to the pointer register. they can be accessed by writing to their respective addresses (see table 3 ). pointer register bits 7-3 must always be written to '0' (see table 4 ). this must be maintained, as not setting these bits to '0' may keep the device from performing to specifications. the main registers include: capability register (read-only) configuration register (read/write) temperature register (read-only) temperature trip point registers (r/w) , including ? alarm temperature upper boundary, ? alarm temperature lower boundary, and ? critical temperature. manufacturer id register format device id and device revision id register format see table 5 on page 17 for pointer register selection bit details. table 3. temperature sensor registers summary address (hex) register name power-on default not applicable address pointer undefined 00 capability c-grade 0x002d b-grade 0x002f 01 configuration 0x0000 02 alarm temperature upper boundary trip 0x0000 03 alarm temperature lower boundary trip 0x0000 04 critical temperature trip 0x0000 05 temperature undefined 06 manufacturer?s id 0x104a 07 device id/revision da package 0x0000 dn package 0x0001 table 4. pointer register format msb lsb bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 0 0 0 p2 p1 p0 pointer/register select bits
stts424e02 temperature sensor registers doc id 13448 rev 7 17/49 4.1 capability register (read-only) this 16-bit register is read-only, and provides the ts capabilities which comply with the minimum jedec jc 42.4 specifications (see table 6 and table 7 on page 18 ). the stts424e02 provides temperatures at 0.25 resolution (10-bit). 4.1.1 alarm window trip the device provides a comparison window with an upper temperature trip point in the alarm upper boundary register, and a lower trip point in the alarm lower boundary register. when enabled, the event output will be triggered whenever entering or exiting (crossing above or below) the alarm window. 4.1.2 critical trip the device can be programmed in such a way that the event output is only triggered when the temperature exceeds the critical trip point. the critical temperature setting is programmed in the critical temperature register. when the temperature sensor reaches the critical temperature value in this register, the device is automatically placed in comparator mode, which means that the critical event output cannot be cleared by using software to set the clear event bit. table 5. pointer register select bits (type, width, and default values) p2 p1 p0 name register description width (bits) type (r/w ) default state (por) 0 0 0 capa thermal sensor capabilities c-grade 16 r 0x002d b-grade 0x002f 0 0 1 conf configuration 16 r/w 0x0000 0 1 0 upper alarm temperature upper boundary 16 r/w 0x0000 0 1 1 lower alarm temperature lower boundary 16 r/w 0x0000 1 0 0 critical critical temperature 16 r/w 0x0000 1 0 1 temp temperature 16 r 0x0000 1 1 0 manu manufacturer id 16 r 0x104a 1 1 1 id device id/revision da package 16 r 0x0000 dn package 0x0001
temperature sensor registers stts424e02 18/49 doc id 13448 rev 7 table 6. capability register format bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 rfu rfu rfu rfu rfu rfu rfu rfu bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rfu rfu v hv tres1 tres0 wider range higher precision alarm and critical trips table 7. capability regi ster bit definitions bit definition 0 basic capability ? 0 = alarm and critical trips turned off. ? 1 = alarm and critical trips turned on. 1 accuracy ? 0 = accuracy 2 c over the active range and 3 c over the monitoring range (c-grade). ? 1 = high accuracy 1 c over the active range and 2 c over the monitoring range (b-grade) (default). 2 range width ? 0 = values lower than 0 c will be clamped and represented as binary value '0'. ? 1 = temperatures below 0 c can be read and the sign bit will be set accordingly. 4:3 temperature resolution ? 01 = this 10-bit value is fixed for stts 424e02, providing temperatures at 0.25 c resolution (lsb). 5 (v hv ) high voltage support for a0 (pin 1) ? 1 = stts424e02 supports a voltage up to 10 volts on the a0 pin - (default) 15:6 reserved these values must be set to '0'.
stts424e02 temperature sensor registers doc id 13448 rev 7 19/49 4.2 configuration re gister (read/write) the 16-bit configuration register stores various configuration modes that are used to set up the sensor registers and configure according to application and jedec requirements (see table 8 on page 19 and table 9 on page 20 ). 4.2.1 event thresholds all event thresholds use hysteresis as programm ed in register address 0x01 (bits 10 through 9) to be set when they de-assert. 4.2.2 interrupt mode the interrupt mode allows an event to occur where software may write a '1' to the clear event bit (bit 5) to de-assert the event interrupt output until the next trigger condition occurs. 4.2.3 comparator mode comparator mode enables the device to be used as a thermostat. reads and writes on the device registers will not affect the event ou tput in comparator m ode. the event signal will remain asserted until temperature drops outside the range or is re-programmed to make the current temperature ?out of range?. 4.2.4 shutdown mode the stts424e02 features a shutdown mode which disables all power-consuming activities (e.g. temperature sampling operations), and leaves the serial interface active. this is selected by setting shutdown bit (bit 8) to '1'. in this mode, the devices consume the minimum current (i shdn ), as shown in table 27 on page 38 . note: bit 8 cannot be set to '1' while bits 6 and 7 (the lock bits) are set to '1'. the device may be enabled for continuous operation by clearing bit 8 to '0'. in shutdown mode, all registers may be read or written to. power recyclin g will also clear this bit and return the device to continuous mode as well. table 8. configuration register format bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 rfu rfu rfu rfu rfu hysteresis hysteresis shutdown mode bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 critical lock bit alarm lock bit clear event event output status event output control critical event only event polarity event mode
temperature sensor registers stts424e02 20/49 doc id 13448 rev 7 table 9. configuration re gister bit definitions bit definition 0 event mode ? 0 = comparator output mode (this is the default). ? 1 = interrupt mode; when either of the lock bits is set, this bit cannot be altered until it is unlocked. 1 event polarity (1) the event polarity bit controls the active state of the event pin. the event pin is driv en to this state when it is asserted. ? 0 = active-low (this is th e default). requires a pull-up resistor to set the inactive state of the open- drain output. the power to the pull-up resistor should not be greater than v dd + 0.2 v. active state is logical ?0?. ? 1 = active-high. the active state of the pin is then logical ?1?. 2 critical event only ? 0 = event output on alarm or critical temperature event (th is is the default). ? 1 = event only if the temperature is above the value in the critical temperatur e register; when the alarm window lock bit is set, this bit cannot be altered until it is unlocked. 3 event output control ? 0 = event output disabl ed (this is the default). ? 1 = event output enabled; when either of the lock bits is set, this bit cannot be altered until it is unlocked. 4 event status (read-only) (2) ? 0 = event output condition is not being asserted by this device. ? 1 = event output condition is being asserted by this device via the alarm window or critical trip event. 5 clear event (write-only) (3) ?0 = no effect. ? 1 = clears the active event in interrupt mode. 6 alarm window lock bit ? 0 = alarm trips are not locked and can be altered (this is the default). ? 1 = alarm trip register settings cannot be altered. this bit is initially cleared. when set, this bit returns a logic '1' and remains locked until cleared by an internal power-on reset. these bits can be written to with a single write, and do not require double writes. 7 critical trip lock bit ? 0 = critical trip is not locked and can be altered (this is the default). ? 1 = critical trip register settings cannot be altered. th is bit is initially cleared. when set, this bit returns a logic '1' and remains locked until cleared by an internal power-on reset. these bits can be written to with a single write, and do not require double writes. 8 shutdown mode ? 0 = ts is enabled (this is the default). ? 1 = shutdown ts when the shutdown, device, and a/d converter are disabled in order to save power. no event conditions will be asserted; when either of the lock bits is set, this bit cannot be altered until it is unlocked. however, it can be cleared at any time.
stts424e02 temperature sensor registers doc id 13448 rev 7 21/49 figure 8. hysteresis 1. t h = value stored in the alarm tem perature upper boundary trip register. 2. t l = value stored in the alarm temperature lower boundary trip register. 3. hys = absolute value of selected hysteresis 10:9 hysteresis enable (see figure 8 and table 10 ) ? 00 = hysteresis is disabled (this is the default). ? 01 = hysteresis is enabled at 1.5 c. ? 10 = hysteresis is enabled at 3 c. ? 11 = hysteresis is enabled at 6 c. hysteresis applies to all limits when the temperatur e is dropping below the threshold so that once the temperature is above a given threshold, it must drop below the threshold minus the hysteresis in order to be flagged as an interrupt event. note that hysteresis is also appli ed to the event pin functionality. when either of the lock bits is se t, these bits cannot be altered. 15:11 reserved for future use. these bits will always read ?0? and writing to them will have no effect. for future compatibility, all rfu bits must be programmed as ?0?. 1. as this device is used in dimm (memory modules) applications, it is strongly recommended that only the active-low polarity (d efault) is used. this is the recommended configuration for the stts424e02. 2. t he actual incident causing the event can be determined from the re ad temperature register. interrupt events can be cleared by w riting to the clear event bit (writing to this bit will ha ve no effect on overall device functioning). 3. writing to this register has no effect on overall device functioning in comparator mode. when read, this bit will always retu rn a logic '0' result. table 9. configuration re gister bit definitions bit definition below window bit above window bit t h - hys t l - hys t h t l ai12270 table 10. hysteresis as applied to temperature movement below alarm window bit above alarm window bit temperature slope temperature threshold temperature slope temperature threshold sets falling t l - hys rising t h clears rising t l falling t h - hys
temperature sensor registers stts424e02 22/49 doc id 13448 rev 7 4.2.5 event output pin functionality the event outputs can be programmed to be configured as either a comparator output or as an interrupt. this is done by enabling the output control bit (bit 3) and setting the event mode bit (bit 0). the output pin polarity can also be specified as active-high or active-low by setting the event polarity bit (bit 1). when the hysteresis bits (bits 10 and 9) are enabled, hysteresis may be used to sense temperature movement around trigger points. for example, when using the ?above alarm window? bit (temperature register bit 14, see table 12 on page 24 ) and hysteresis is set to 3 c, as the temperature rises, bit 14 is set (bit 14 = 1). the temperature is above the alarm window and the temperature register contains a value that is greater than the value set in the alarm temperature upper boundary register (see table 15 on page 25 ). if the temperature decreases, bi t 14 will remain set until the m easured temperat ure is less than or equal to the value in the alarm temperature upper boundary register minus 3 c (see figure 8 on page 21 and table 10 on page 21 for details. similarly, when using the ?below alarm window? bit (temperature register bit 13, see table 12 on page 24 ) will be set to '0'. the temperature is equal to or grea ter than the value set in the alarm temperature lower boundary register (see table 16 on page 25 ). as the temperature decreases, bi t 13 will be set to '1' when the val ue in the temperature register is less than the value in the alarm temperature lower boundary register minus 3 c (see figure 8 on page 21 and table 10 on page 21 for details. the device will retain the previo us state when entering the sh utdown mode. if the device enters the shutdown mode while the event pin is low, the shutdo wn current will increase due to the additional event output pull-down current. note: hysteresis is also applied to the event pin functionality. when either of the lock bits (bits 6 and 7) are set, these bits cannot be altered.
stts424e02 temperature sensor registers doc id 13448 rev 7 23/49 figure 9. event output boundary timings table 11. legend for figure 9: event output boundary timings . note event output boundary conditions event output t a bits comparator interrupt critical 15 14 13 1t a t lower h l h 000 2t a < t lower - t hys l l h 001 3t a > t upper l l h 010 4t a t upper - t hys h l h 000 5t a t crit l l l 110 6t a < t crit - t hys l h h 010 7 when t a t crit and t a < t crit - t hys , the event output is in comparator mode and bit 0 of the configuration register (i nterrupt mode) is ignored. comparator t crit t upper t lower t a t lower - t hys interrupt s/w int. clear critical event output (active-low) t upper - t hys t crit - t hys t upper - t hys t lower - t hys 1213357 4642 ai12271
temperature sensor registers stts424e02 24/49 doc id 13448 rev 7 4.3 temperature regi ster (read-only) this 16-bit, read-only register stores the temperature measured by the internal band gap ts as shown in table 12 . the stts424e02 meets the jedec mandatory 0.25 c resolution requirement. when reading this register, the msbs (bit 15 to bit 8) are read first, and then the lsbs (bit 7 to bit 0) are read. the result is the current-sensed temperature. the data format is 2s complement with one lsb = 0.25 c. the msb has a 128 c resolution. the trip status bits represent the internal temperature trip detection, and are not affected by the status of the event or configuration bits (e.g. event output control or clear event). if neither of the above or below values are set (i.e. both are 0), then the temperature is exactly within the user-defined alarm window boundaries. 4.3.1 temperature format the 16-bit value used in the trip point set and temperature read-back registers is 2s complement, with the lsb equal to 0.0625 c (see table 13 ). for example: 1. a value of 019ch represents 25.75 c, 2. a value of 07c0h represents 124 c, and 3. a value of 1e74h represents ?24.75 c all unused resolution bits are set to zero . the msb will have a resolution of 128 c. the stts424e02 supports the 0.25 c/lsb only. the upper 3 bits indicate trip status based on the current temperature, and are not affected by the event output status. table 12. temperature register format sign msb lsb bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 above critical input (1) above alarm window (1) below alarm window (1) temperature 0 0 1. see table 13 for explanation. table 13. temperature re gister bit definitions bit definition with hysteresis = 0 13 below (temperature) alarm window ? 0 = temperature is equal to or above the alarm window lower boundary temperature. ? 1 = temperature is below the alarm window. 14 above (temperature) alarm window. ? 0 = temperature is equal to or below the alarm window upper boundary temperature. ? 1 = temperature is above the alarm window. 15 above critical trip ? 0 = temperature is below the critical temperature setting. ? 1 = temperature is equal to or above the critical temperature setting.
stts424e02 temperature sensor registers doc id 13448 rev 7 25/49 4.4 temperature trip point registers (r/w ) the stts424e02 alarm mode registers provide for 11-bit data in 2s compliment format. the data provides for one lsb = 0.25 c. all unused bits in these registers are read as '0'. the stts424e02 has three temperature trip point registers (see table 14 ): alarm temperature upper boundary threshold ( table 15 ), alarm temperature lower boundary threshold ( table 16 ), and critical temperature trip point value ( table 17 ). note: if the upper or lower boundary threshold valu es are being altered in-system, all interrupts should be turned off until a known state can be obtained to avoid superfluous interrupt activity. table 14. temperature trip point register format p2 p1 p0 name register description width (bits) type (r/w ) default state (por) 0 1 0 upper alarm temperatur e upper boundary 16 r/w 00 00 0 1 1 lower alarm temperature lower boundary 16 r/w 00 00 1 0 0 critical critical temperature 16 r/w 00 00 table 15. alarm temperature upper boundary register format sign msb lsb bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 000 alarm window upper boundary temperature 00 table 16. alarm temperature lower boundary register format sign msb lsb bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 000 alarm window lower boundary temperature 00 table 17. critical temperature register format sign msb lsb bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 000 critical temperature trip point 00
temperature sensor registers stts424e02 26/49 doc id 13448 rev 7 4.5 manufacturer id re gister (read-only) the manufacturer?s id (programmed value 104ah) in this register is the stmicroelectronics identification provided by the peripheral co mponent interconnect special interest group (pcisig). 4.6 device id and device revisi on id register (read-only) the device ids and device revision ids are maintained in this register. the register format is shown in table 19 . the device ids and device revision ids are currently '0' and will be incremented whenever an update of the device is made. table 18. manufacturer id register format bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 00010000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 01001010 table 19. device id and device revision id register format bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 00000000 device id bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 (1) 1. da package, bit0 is 0 (see table 27 on page 38 ). dn package, bit0 is 1 (see table 27 on page 38 ). 00000000 or 1 device revision id
stts424e02 spd eeprom operation doc id 13448 rev 7 27/49 5 spd eeprom operation 5.1 2 kb spd eeprom operation the 2 kbit serial eeprom is able to lock perman ently the data in its fi rst half (from location 00h to 7fh). this facility has been designed sp ecifically for use in dram dimms (dual inline memory modules) with serial presence detect. all the information concerning the dram module configuration (such as its access speed, its size, its organization) can be kept write protected in the first half of the memory. the first half of the memory area can be write-protected using two different software write protection mechanisms. by sending the device a specific sequence, the first 128 bytes of the memory become write protected: permanently or resetable. these i 2 c-compatible electrically erasable pr ogrammable memory (eeprom) devices are organized as 256x8 bits. i 2 c uses a two wire serial interface, comprising a bi-directional data line and a clock line. the device carries a built-in 4-bit device type identifier code (1010) in accordance with the i 2 c bus definition to access the memory area and a second device type identifier code (0110) to define the protection. these codes are used together with the voltage level applied on the three chip enable inputs (a2, a1, a0). these input signals are used to set the value that is to be looked for on the three least significant bits (b3, b2, b1) of the 7-bit device select code. in the end application, a0, a1 and a2 must be directly (not through a pull-up or pull- down resistor) connected to v dd or v ss to establish the device select code. when these inputs are not connected, an internal pull-down circuitry makes (a0,a1,a2) = (0,0,0). the a0 input is used to detect the v hv voltage, when decoding an swp or cwp instruction (refer to table 20: device select code ). the device behaves as a slave device in the i 2 c protocol, with all memory operations synchronized by the serial clock. read and write operations are initiated by a start condition, generated by the bus master. the start condition is followed by a device select code and r/w bit (as described in table 20: device select code ), terminated by an acknowledge bit. when writing data to the memory, the memory inserts an acknowledge bit during the 9 th bit time, following the bus master?s 8-bit transmission. when data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. data transfers are terminated by a stop condition after an ack for write, and after a noack for read. 5.2 internal device reset - spd eeprom in order to prevent inadvertent write operations during power-up, a power on reset (por) circuit is included. at power-up (phase during which v dd is lower than v dd min but increases continuously), the device will not respond to any instruction until v dd has reached the power on reset threshold voltage (this threshold is lower than the minimum v dd operating voltage defined in table 2: ac smbus and i 2 c compatibility timings ). once v dd has passed the por threshold, the device is reset.
spd eeprom operation stts424e02 28/49 doc id 13448 rev 7 prior to selecting the memory and issu ing instructions, a valid and stable v dd voltage must be applied. this voltage must remain stable and valid until the end of the transmission of the instruction and, for a write instruction, unt il the completion of the internal write cycle (t w ). at power-down (phase during which v dd decreases continuously), as soon as v dd drops from the normal operating voltage below the power on reset threshold voltage, the device stops responding to any instruction sent to it. 5.3 memory addressing to start communication between the bus master and the slave device, the bus master must initiate a start condition. follo wing this, the bus master sends the device select code, shown in table 20: device select code (on serial data (sda), most significant bit first). the device select code consists of a 4-bit device type identifier, and a 3-bit chip enable ?address? (a2, a1, a0). to address the memory array, the 4-bit device type identifier is 1010b; to access the write-protection settings, it is 0110b. up to eight memory devices can be connected on a single i 2 c bus. each one is given a unique 3-bit code on the chip enable (a0, a1, a2) inputs. when the device select code is received, the device only responds if the chip enable address is the same as the value on the chip enable (a0, a1, a2) inputs. the 8 th bit is the read/write bit (r/w ). this bit is set to 1 for read and 0 for write operations. if a match occurs on the device select code, the corresponding device gives an acknowledgment on serial data (sda) during the 9 th bit time. if the device does not match the device select code, it deselects itself from the bus, and goes into standby mode. the operating modes are detailed in table 21 . table 20. device select code chip enable signals device type identifier chip enable bits r/w b7 (1) 1. the most significant bit, b7, is sent first. b6 b5 b4 b3 b2 b1 b0 memory area select code (two arrays) (2) 2. a0, a1 and a2 are compared against the respec tive external pins on the memory device. a2a1a01010a2a1a0r/w set write protection (swp) v ss v ss v hv 0110 0010 clear write protection (cwp) v ss v dd v hv 0110 permanently set write protection (pswp) (2) a2 a1 a0 a2 a1 a0 0 read swp v ss v ss v hv 0011 read cwp v ss v dd v hv 0111 read pswp (2) a2 a1 a0 a2 a1 a0 1
stts424e02 spd eeprom operation doc id 13448 rev 7 29/49 figure 10. result of setting the write protection 5.4 setting the write protection the write control (wc ) is tied low, hence the write protection of the memory array is dependent on whether software write-protection has been set. software write-protection allows the bottom half of the memory area (addresses 00h to 7fh) to be write protected irrespective of subsequent states of the write control (wc ) signal. software write-protection is handled by three instructions: swp: set write protection cwp: clear write protection pswp: permanently set write protection the level of write-protection (set or cleared) that has been defined using these instructions, remains defined even after a power cycle. table 21. operating modes mode r/w bit bytes initial sequence current address read 1 1 star t, device select, r/w = 1 random address read 0 1 start, device select, r/w = 0, address 1 restart, device select, r/w = 1 sequential read 1 1 similar to current or random address read byte write 0 1 start, device select, r/w = 0 page write 0 16 start, device select, r/w = 0 ts write 0 2 start, device select, r/w = 0, pointer data, stop ts read 1 2 start, device select, r/w = 1, pointer data, stop default eeprom memory area state before write access to the protect register ai01936c standard array ffh standard array 80h 7fh 00h standard array ffh write protected array 80h 7fh 00h state of the eeprom memory area after write access to the protect register memory area
spd eeprom operation stts424e02 30/49 doc id 13448 rev 7 5.4.1 swp and cwp if the software write-protection has been set with the swp instruction, it can be cleared again with a cwp instruction. the two instructions (swp and cwp) have the same format as a byte write instruction, but with a different device type identifier (as shown in table 20 ). like the byte write instruction, it is followed by an address byte and a data byte, but in this case the contents are all ?don?t care? ( figure 11 ). another difference is that the voltage, v hv , must be applied on the a0 pin, and specific logical levels must be applied on the other two address pins a1 and a2 (as shown in table 20 ). 5.4.2 pswp if the software write-protection has been set with the pswp instruction, the first 128 bytes of the memory are permanently write-protected. this write-protection cannot be cleared by any instruction, or by power-cycling the device. also, once the pswp instruction has been successfully executed, the spd eeprom no longer acknowledges any instruction (with a device type identifier of 0110) to access the write-protection settings. figure 11. setting the write protection 5.5 write operations following a start condition the bus master sends a device select code with the r/w bit reset to 0. the device acknowledges this, as shown in figure 12 , and waits for an address byte. the device responds to the address byte with an acknowledge bit, and then waits for the data byte. when the bus master generates a stop condition immediately after the ack bit (in the ?10 th bit? time slot), either at the end of a byte write or a page write, the internal memory write cycle is triggered. a stop condition at any other time slot does not trigger the internal write cycle. during the internal write cycle, serial data (sda) and serial clock (scl) are ignored, and the device does not respond to any requests. start sda line ai01935b ack word address value (don't care) ack data value (don't care) stop ack control byte bus activity master bus activity
stts424e02 spd eeprom operation doc id 13448 rev 7 31/49 5.5.1 byte write after the device select code and the address byte, the bus master sends one data byte. if the addressed location is hardware write-protected, the device replies to the data byte with noack, and the location is not modified. if, instead, the addressed location is not write- protected, the device replies with ack. the bus master terminates the transfer by generating a stop condition, as shown in figure 12 . 5.5.2 page write the page write mode allows up to 16 bytes to be written in a single write cycle, provided that they are all located in the same page in the memory: that is, the most significant memory address bits are the same. if more bytes are sent than will fit up to the end of the page, a condition known as ?roll-over? occurs. this should be avoided, as data starts to become overwritten in an implementation dependent way. the bus master sends from 1 to 16 bytes of data, each of which is acknowledged by the device. after each byte is transferred, the internal byte address counter (the 4 least significant address bits only) is incremented. the transfer is terminated by the bus master generating a stop condition. figure 12. write mode sequences in a non write-protected area of spd stop start byte write dev sel byte addr data in start page write dev sel byte addr data in 1 data in 2 ai01941 stop data in n ack ack ack r/w ack ack ack r/w ack ack
spd eeprom operation stts424e02 32/49 doc id 13448 rev 7 5.5.3 write cycle polling using ack during the internal write cycle, the device disconnects itself from the bus, and writes a copy of the data from its internal latches to the memory cells. the maximum write time (t w ) is shown in table 2: ac smbus and i 2 c compatibility timings , but the typical time is shorter. to make use of this, a polling sequence can be used by the bus master. the sequence, as shown in figure 13 , is: initial condition: a write cycle is in progress. step 1: the bus master issues a start condition followed by a device select code (the first byte of the new instruction). step 2: if the device is busy with the inter nal write cycle, no ack will be returned and the bus master goes back to step 1. if the device has terminated the internal write cycle, it responds with an ack, indicating that the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during step 1). figure 13. write cycle polling flowchart using ack write cycle in progress ai01847c next operation is addressing the memory start condition device select with rw = 0 ack returned yes no yes no restart stop data for the write operation device select with rw = 1 send address and receive ack first byte of instruction with rw = 0 already decoded by the device yes no start condition continue the write operation continue the random read operation
stts424e02 spd eeprom operation doc id 13448 rev 7 33/49 5.6 read operations - spd read operations are performed independently of whether hardware or software protection has been set. the device has an internal address counter which is incremented each time a byte is read. figure 14. read mode sequences - spd 1. the seven most significant bits of the dev ice select code of a random read (in the 1 st and 3 rd bytes) must be identical. 5.6.1 random address read - spd a dummy write is first performed to load the address into this address counter (as shown in figure 14 ) but without sending a stop condition. then, the bus master sends another start condition, and repeats the device select code, with the r/w bit set to 1. the device acknowledges this, and outputs the contents of the addressed byte. the bus master must not acknowledge the byte, and terminates the transfer with a stop condition. start dev sel (1) byte addr start dev sel data out 1 ai01942 data out n stop start current address read dev sel data out random address read stop start dev sel (1) data out sequential current read stop data out n start dev sel (1) byte addr sequential random read start dev sel (1) data out 1 stop ack r/w no ack ack r/w ack ack r/w ack ack ack no ack r/w no ack ack ack r/w ack ack r/w ack no ack
spd eeprom operation stts424e02 34/49 doc id 13448 rev 7 5.6.2 current address read - spd for the current address read operation, following a start condition, the bus master only sends a device select code with the r/w bit set to 1. the device acknowledges this, and outputs the byte addressed by the internal address counter. the counter is then incremented. the bus master terminates the transfer with a stop condition, as shown in figure 14 , without acknowledging the byte. 5.6.3 sequential read - spd this operation can be used after a current address read or a random address read. the bus master does acknowledge the data byte output, and sends additional clock pulses so that the device continues to output the next byte in sequence. to terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a stop condition, as shown in figure 14 . the output data comes from consecutive addresses, with the internal address counter automatically incremented after each byte output. after the last memory address, the address counter ?rolls-over?, and the device continues to output data from memory address 00h. 5.6.4 acknowledge in read mode for all read commands, the device waits, after each byte read, for an acknowledgment during the 9 th bit time. if the bus master does not drive serial data (sda) low during this time, the device terminates the data transfer and switches to its standby mode. table 22 and table 23 show how the ack bits can be used to identify the write-protection status. table 22. acknowledge when writing data or defining the write-protection (instructions with r/w bit=0) status wc input level instruction ack address ack data byte ack write cycle(t w ) permanently protected x pswp, swp or cwp noack not significant noack not significant noack no page or byte write in lower 128 bytes ack address ack data noack no protected with swp swp noack not significant noack not significant noack no cwp ack not significant ack not significant ack ye s 0 pswp ack not significant ack not significant ack ye s page or byte write in lower 128 bytes ack address ack data noack no not protected 0 pswp, swp or cwp ack not significant ack not significant ack ye s page or byte write ack address ack data ack ye s
stts424e02 spd eeprom operation doc id 13448 rev 7 35/49 5.7 initial delivery state - spd the device is delivered with all bits in the memory array set to ?1? (each byte contains ffh). table 23. acknowledge when reading the wr ite protection (instructions with r/w bit=1) status instruction ack address ack data byte ack permanently protected pswp, swp or cwp noack not significant noack not significant noack protected with swp swp noack not significant noack not significant noack cwp ack not significant noack not significant noack pswp ack not significant noack not significant noack not protected pswp, swp or cwp ack not significant noack not significant noack
use in a memory module stts424e02 36/49 doc id 13448 rev 7 6 use in a memory module in the dual inline memory module (dimm) application, the spd is soldered directly on to the printed circuit module. the three chip enable inputs (a0, a1, a2) must be connected to v ss or v dd directly (that is without using a pull-up or pull-down resistor) through the dimm socket (see table 24 ). the write control (wc ) of the device is tied to ground to maintain full read and write access. 6.1 programming the spd the situations in which t he spd eeprom is programmed ca n be consider ed under two headings: when the dimm is isolated (not inserted on the pcb motherboard) when the dimm is inserted on the pcb motherboard 6.1.1 dimm isolated with specific programming eq uipment, it is possible to define the spd eeprom content, using byte and page write instructions, and its write-protection using the swp and cwp instructions. to issue the swp and cwp instru ctions, the dimm must be inserted in the application-specific slot where the a0 signal can be driven to v hv during the whole instruction. this programming step is mainly intended for use by dimm makers, whose end application manufacturers will want to clear th is write-protection with the cwp on their own specific programming equipment, to modify the lower 128 bytes, and finally to set permanently the write-protection with the pswp instruction. 6.1.2 dimm inserted in th e application motherboard as the final application cannot drive the a0 pin to v hv , the only possible action is to freeze the write-protection with the pswp instruction. table 24. dram dimm connections dimm position a2 a1 a0 0 v ss (0) v ss (0) v ss (0) 1 v ss (0) v ss (0) v dd (1) 2 v ss (0) v dd (1) v ss (0) 3 v ss (0) v dd (1) v dd (1) 4 v dd (1) v ss (0) v ss (0) 5 v dd (1) v ss (0) v dd (1) 6 v dd (1) v dd (1) v ss (0) 7 v dd (1) v dd (1) v dd (1)
stts424e02 maximum ratings doc id 13448 rev 7 37/49 7 maximum ratings stressing the device above the ratings listed in the absolute maximum ratings table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not imp lied. exposure to absolute ma ximum rating conditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality documents. table 25. absolute maximum ratings symbol parameter value unit t stg storage temperature ?65 to 150 c t sld (1) 1. reflow at peak temperature of 260 c. the time above 255 c must not exceed 30 seconds. lead solder temperature for 10 seconds 260 c v io input or output voltage a0 v ss ? 0.3 to 10.0 v others v ss ? 0.3 to 6.5 v v dd supply voltage v ss ? 0.3 to 6.5 v i o output current 10 ma p d power dissipation 320 mw ja thermal resistance da package 128 c/w dn package 87.4 c/w
dc and ac parameters stts424e02 38/49 doc id 13448 rev 7 8 dc and ac parameters this section summarizes the operating measurement conditions, and the dc and ac characteristics of the device. the parameters in the dc and ac characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in table 26 , operating and ac measurement conditions. designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. table 26. operating and ac measurement conditions parameter conditions unit v dd supply voltage - temperature sensor 2.7 to 3.6 v operating temperature ?40 to 85 c input rise and fall times 50 ns load capacitance 100 pf input pulse voltages 0.2 to 0.8v dd v input and output timing reference voltages 0.3 to 0.7v dd v table 27. dc/ac characteristics - temperature sensor component with eeprom sym description test condition (1) min typ (2) max unit v dd supply voltage 2.7 3.3 3.6 v i dd v dd supply current (no load) eeprom active, ts shutdown f = 400 khz 2ma eeprom (standby) active temperature conversions f = 400 khz 100 210 a v dd supply current, communication only (no conversions) eeprom (standby) 100 khz 40 a 400 khz 115 a i dd1 ts shutdown mode supply current eeprom standby, ts shutdown da package at 85 c 1.0 3 a dn package at 125 c 1.0 5 a i sink smbus output low sink current sda forced to 0.6 v 6 ma i ili input leakage current (scl, sda) v in = v ss or v dd 4 a i ilo output leakage current v out = v ss or v dd , sda in hi-z 4 a
stts424e02 dc and ac parameters doc id 13448 rev 7 39/49 v por (3) power on reset (por) threshold v dd falling edge: da package 0.6 v v dd falling edge: dn package 2.0 v c-grade (4) accuracy for corresponding range 2.7 v v dd 3.6 v +75 c < t a < +95 1.0 2.0 c +40 c < t a < +125 2.0 3.0 c ?40 c < t a < +125 3.0 4.0 c b-grade accuracy for corresponding range 2.7 v v dd 3.6 v +75 c < t a < +95 0.5 1.0 c +40 c < t a <+ 125 1.0 2.0 c ?40 c < t a < +125 2.0 3.0 c resolution 10-bit temperature data 0.25 c/ls b 10 bits t conv conversion time 10-bit 125 ms v ol1 low level voltage event ; i ol = 2.1 ma 0.4 v smbus/i 2 c interface v ih input logic high scl, sda, a0-a2 2.1 v v il input logic low scl, sda, a0-a2 0.8 v c in smbus/i 2 c input capacitance 5 pf f scl smbus/i 2 c clock frequency da package 10 100 khz dn package 10 400 khz t timeout smbus timeout 25 50 ms v hv allowable voltage on pin a0 10 v l ao leakage on pin a0 in overvoltage state 500 a v ol2 low level voltage sda i ol = 6 ma 0.6 v z ail (a0, a1, a2) input impedance v in < 0.3 v cc 30 k z aih (a0, a1, a2) input impedance v in > 0.7 v cc 800 k t a ambient operating temperature (3) da package ?40 85 c dn package ?40 125 c 1. guaranteed operating temperature for da package: t a = ?40 c to 85 c and for dn package: t a = ?40 c to 125 c; v dd = 2.7 v to 3.6 v (except where noted). 2. typical numbers taken at v dd = 3.3 v, t a = 25 c. 3. dn is tdfn package max 0.80 mm height. da is dfn package max 0.90 mm height. 4. contact local st sales office for availability. table 27. dc/ac characteristics - temperatur e sensor component with eeprom (continued) sym description test condition (1) min typ (2) max unit
package mechanical data stts424e02 40/49 doc id 13448 rev 7 9 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark.
stts424e02 package mechanical data doc id 13448 rev 7 41/49 figure 15. dfn8 ? 8-lead dual flat, no-lead (2 mm x 3 mm) package outline (da) 1. drawing is not to scale. 7904084_b table 28. dfn8 ? 8-lead dual flat, no-lead (2 mm x 3 mm) mechanical data (da) sym mm inches min typ max min typ max a 0.80 0.85 0.90 0.031 0.033 0.035 a1 0.00 0.00 0.05 0.000 0.000 0.002 a3 0.20 0.008 b 0.20 0.25 0.30 0.008 0.010 0.012 d 1.95 2.00 2.05 0.077 0.079 0.081 d2 1.35 1.40 1.45 0.053 0.055 0.057 e 2.95 3.00 3.05 0.116 0.118 0.120 e2 1.25 1.30 1.35 0.049 0.051 0.053 e 0.50 0.020 l 0.20 0.30 0.40 0.008 0.012 0.016 ddd 0.08 0.003
package mechanical data stts424e02 42/49 doc id 13448 rev 7 figure 16. tdfn8 ? 8-lead thin dual flat, no-lead (2 mm x 3 mm) package outline (dn) note: jedec mo-229, variation wced-3 proposal note: jedec mo-229, variation wced-3 proposal 8089094_a table 29. tdfn8 ? 8-lead thin dual flat, no-lead (2 mm x 3 mm) mechanical data (dn) sym mm inches min typ max min typ max a 0.70 0.75 0.80 0.028 0.030 0.031 a1 0.00 0.00 0.05 0.000 0.000 0.002 a3 0.20 0.008 b 0.20 0.25 0.30 0.008 0.010 0.012 d 1.95 2.00 2.05 0.077 0.079 0.081 d2 1.35 1.40 1.45 0.053 0.055 0.057 e 2.95 3.00 3.05 0.116 0.118 0.120 e2 1.25 1.30 1.35 0.049 0.051 0.053 e 0.50 0.020 l 0.30 0.35 0.40 0.012 0.014 0.016 ddd 0.08 0.003
stts424e02 package mechanical data doc id 13448 rev 7 43/49 figure 17. carrier tape for dfn8 and tdfn8 packages t k 0 p 1 a 0 b 0 p 2 p 0 center lines of cavity w e f d top cover tape user direction of feed am0 3 07 3 v1 table 30. carrier tape dimensions for dfn8 and tdfn8 packages package w d e p 0 p 2 fa 0 b 0 k 0 p 1 tunit bulk qty dfn8 8.00 + 0.30 ?0.10 1.50 +0.10/ ?0.00 1.75 0.10 4.00 0.10 2.00 0.10 3.50 0.05 2.30 0.10 2.80 0.10 1.10 0.01 4.00 0.10 0.30 0.05 mm 3000 tdfn8 8.00 + 0.30 ?0.10 1.50 +0.10/ ?0.00 1.75 0.10 4.00 0.10 2.00 0.10 3.50 0.05 2.30 0.10 3.20 0.10 1.10 0.10 4.00 0.10 0.30 0.05 mm 3000
part numbering stts424e02 44/49 doc id 13448 rev 7 10 part numbering table 31. ordering information scheme for other options, or for more information on any aspect of this device, please contact the st sales office nearest you. example: stts424e02 b dn 3 f device type stts424e02 grade b: maximum accuracy 75 c to 95 c = 1 c c: maximum accuracy 75 c to 95 c = 2 c (1) 1. contact local st sales office for availability. package dn = tdfn8 (0.80 mm max height) (2) 2. dn package is only available in b ac curacy grade and in temperature grade 3. da = dfn8 (0.90 mm max height) (3) 3. da package available onl y in temperature grade 6. temperature 3 = ?40 c to 125 c (dn package only) 6 = ?40 c to 85 c (da package only) shipping method f = ecopack ? package, tape & reel packing e = ecopack ? package, tube packing
stts424e02 package marking information doc id 13448 rev 7 45/49 11 package marking information figure 18. da package topside marking information (dfn-8l) 1. option codes: x = b or c accuracy grade. for example, e42c is c-grade. 2. traceability codes p = plant code y = year ww = work week note: contact local st sale s office for availability. figure 19. dn package topside marking information (tdfn-8l) 1. option codes: x = b or c accuracy grade. for example, e42c is c-grade. 2. package/fab code identifier dn = 0.80 mm (package height) xx = fab code: blank = crn, v6 = amk 3. traceability codes p = plant code y = year ww = work week e42x (1) ai13907 pyww (2) ai13907b e42x (1) pyww (3) dnxx (2)
landing pattern stts424e02 46/49 doc id 13448 rev 7 12 landing pattern the landing pattern recommendations per the jedec proposal for the tdfn package (dn) are shown in figure 20 . the preferred implementation with wide corner pads enhances device centering during assembly, but a narrower option is defined for modules with tight routing requirements. figure 20. landing pattern - tdfn package (dn) e/2 e/2 e2 k k e2/2 e2/2 e2 d2/2 d2 d2/2 l l e b b b2 b4 k2 k2 k2 e3 e3 e4 ai14000
stts424e02 landing pattern doc id 13448 rev 7 47/49 table 32 lists variations of landing pattern implementations, ranked as ?preferred? and ?minimum acceptable? based on the jedec proposal. table 32. parameters for landing pattern - tdfn package (dn) parameter description dimension min nom max d2 heat paddle width 1.40 - 1.60 e2 heat paddle height 1.40 - 1.60 e3 heat paddle centerline to contact inner locus 1.00 - - l contact length 0.70 - 0.80 k heat paddle to contact keepout 0.20 - - k2 contact to contact keepout 0.20 - - e contact centerline to contact centerline pitch for inner contacts - 0.50 - b contact width for inner contacts 0.25 - 0.30 e2 landing pattern centerline to outer contact centerline, ?minimum acceptable? option (1) -0.50- b2 corner contact width, ?minimum acceptable option? (1) 0.25 - 0.30 e4 landing pattern centerline to outer contact centerline, ?preferred? option (2) -0.60- b4 corner contact width, ?preferred? option (2) 0.45 - 0.50 1. minimum acceptable option to be used when routing prevents preferred width contact. 2. preferred option to be used when possible.
revision history stts424e02 48/49 doc id 13448 rev 7 13 revision history table 33. document revision history date revision changes 13-apr-2007 1 initial release. 09-may-2007 2 updated ta ble 3 , 5 , 6 , 7 , 27 , 28 and 31 . 04-jun-2007 3 updated ta ble 27 . 02-jul-2007 4 added por threshold values to table 27 , updated table 28 . 18-mar-2008 5 added tdfn package (cover page, figure 16 , table 29 ) and landing pattern recommendations ( figure 20 , ta ble 32 ); updated section 1 , 2 , table 2 , 3 , 5 , 6 , 7 , 11 , 19 , 25 , 27 , 28 , 29 , 31 , figure 2 , 15 , 18 , 19 ). 12-jun-2008 6 updated cover page, figure 4 , 5 , 8 , 14 ; section 4.3.1 , section 5.4.1 ; table 5 , 11 , 25 , 27 , 31 ; added figure 6 ; removed tssop8 package throughout datasheet. 08-oct-2009 7 reformatted document; added tape and reel specifications ( figure 17 , table 30 ); updated features , text in section 1 , section 3.1 , section 3.3 , section 5.3 , section 5.4.2 , section 5.5.2 , section 5.5.3 , section 9 ; updated figure 5 , 16 , 18 , 19 , ta ble 2 , 7 , 9 , 11 , 13 , 21 , 25 , 26 , 27 , 29 , 31 .
stts424e02 doc id 13448 rev 7 49/49 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in military , air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2009 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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