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advance data sheet august 2000 ts16-type 2.5 gbits/s translight ? transponder with 16-channel 155 mbits/s multiplexer/demultiplexer the translight transponders integrate up to 15 discrete ics and optical components, including a 2.5 gbits/s optical trans- mitter and receiver pair, all in a single, compact package. features n 2.5 gbits/s optical transmitter and receiver with 16-channel 155 mbits/s multiplexer/demultiplexer n available with 1.31 m m fabry-perot (f-p) laser transmitter and pin receiver for short-reach appli- cations, and 1.31 m m or 1.55 m m dfb laser trans- mitters and pin or apd receiver for intermediate to long-haul applications n pigtailed low-pro?le package n differential lvpecl data interface n operating case temperature range: 0 c to 65 c n automatic transmitter optical power control n laser bias monitor output n optical transmitter disable input n sonet frame-detect enable n loss of signal, loss of sync, loss of framing alarms n diagnostic loopback capability n line loopback operation applications n telecommunications: inter- and intraof?ce sonet/sdh subscriber loop metropolitan area networks n high-speed data communications description the ts16 transponder performs the parallel-to- serial-to-optical transport and optical transport-to- serial-to-parallel function of the sonet/sdh proto- col. the ts16 transmitter performs the bit serializa- tion and optical transmission of sonet/sdh oc-48/ stm-16 data that has been formatted into standard sonet/sdh compliant, 16-bit parallel format. the ts16 receiver performs the optical-to-electrical con- version function and is then able to detect frame and byte boundaries and demultiplex the serial data into 16-bit parallel oc-48/stm-16 format. note : the ts16 transponder does not perform byte- level multiplexing or interleaving. figure 1 shows a simpli?ed block diagram of the ts16-type transponder. this device is a bidirectional module designed to provide a sonet or sdh com- pliant electro-optical interface between the sonet/ sdh photonic physical layer and the electrical sec- tion layer. the module contains a 2.5 gbits/s optical transmitter and a 2.5 gbits/s optical receiver in the same physical package along with the electronics necessary to multiplex and demultiplex sixteen 155 mbits/s electrical channels. clock synthesis and clock recovery circuits are also included within the module. in the transmit direction, the transponder module multiplexes sixteen 155 mbits/s lvpecl electrical data signals into an optical signal at 2488.32 mbits/s for launching into optical ?ber. an internal 2.488 ghz reference oscillator is phase-locked to an external 155 mhz data timing reference.
2 table of contents lucent technologies inc. contents page tables page ts16-type 2.5 gbits/s translight transponder with advance data sheet 16-channel 155 mbits/s multiplexer/demulitplexer august 2000 features ......................................................................1 applications .................................................................1 description ..................................................................1 absolute maximum ratings ........................................3 block diagram .............................................................4 pin information ............................................................5 pin descriptions ..........................................................6 functional description ..............................................12 receiver..................................................................12 transmitter .............................................................12 loopback modes ................................................... 13 transponder interfacing .........................................13 optical characteristics ..............................................15 electrical characteristics ...........................................16 timing characteristics ..............................................18 transmitter data input timing ...............................18 input timing mode 1 .............................................. 19 input timing mode 2 ...............................................20 pc lk -to-pic lk timing ............................................21 pherr/phinit ......................................................22 receiver framing ...................................................24 qualification and reliability....................................... 26 laser safety information........................................... 26 class i laser product ............................................ 26 electromagnetic emissions and immunity ............. 26 outline diagram ........................................................ 27 ordering information ................................................. 28 table 1. ts16-type transponder pinout .................. 6 table 2. ts16-type transponder input pin descriptions ......................................... 10 table 3. ts16-type transponder output pin descriptions ......................................... 11 table 4. oc48/stm-16 transmitter optical characteristics ........................................... 15 table 5. oc48/stm-16 receiver optical characteristics ........................................... 15 table 6. transmitter electrical i/o characteristics .. 16 table 7. receiver electrical i/o characteristics ...... 17 table 8. power supply characteristics ................... 17 table 9. transmitter ac timing characteristics ....... 23 table 10. receiver ac timing characteristics ......... 23 table 11. ordering information ................................ 28 figures page figure 1. ts16-type transponder block diagram .... 4 figure 2. ts16-type transponder pinout ................. 5 figure 3. transponder interfacing............................ 13 figure 4. interfacing to the txrefclk input .............. 14 figure 5. block diagram timing mode 1.................. 19 figure 6. block diagram timing mode 2.................. 20 figure 7. pc lk -to-pic lk timings.............................21 figure 8. pherr/phinit timing.............................22 figure 9. ac input timing ........................................23 figure 10. receiver output timing diagram ...........23 figure 11. frame and byte detection ......................24 figure 12. oof timing (framen = high) ..............24 figure 13. framen timing.....................................25
3 lucent technologies inc. advance data sheet ts16-type 2.5 gbits/s translight transponder with august 2000 16-channel 155 mbits/s multiplexer/demulitplexer description (continued) the optical transmitter is available with either a 1.31 m m fabry-perot laser for short-reach applications or 1.31 m m and 1.55 m m dfb lasers for intermediate- to long-reach applications. the optical output signal is sonet and itu compliant for oc-48/stm-16 applica- tions as shown in table 4. in the receive direction, the transponder module receives a 2488.32 mbits/s optical signal and converts it to an electrical signal, extracts a clock signal, and then demultiplexes the data into sixteen 155 mbits/s differential lvpecl data signals. the optical receiver is available with either a pin photodetector or with an apd photodetector. the receiver operates over the wavelength range of 1.1 m m to 1.6 m m and is fully com- pliant to sonet/sdh oc-48/stm-16 physical layer speci?cations as shown in table 5. absolute maximum ratings stresses in excess of the absolute maximum ratings can cause permanent damage to the device. these are abso- lute stress ratings only. functional operation of the device is not implied at these or any other conditions in excess of those given in the operations sections of the data sheet. exposure to absolute maximum ratings for extended periods can adversely affect reliability. 1. human-body model. parameter symbol min max unit operating case temperature range t c 065 c storage case temperature range t s C40 85 c supply voltage C0.5 5.5 v voltage on any lvpecl pin 0 v cc high-speed lvpecl output source current 50 ma static discharge voltage 1 esd 500 v relative humidity (noncondensing) rh 85 % receiver optical input powerbiased: apd pin p in p in 0 8 dbm dbm minimum fiber bend radius 1.25 (31.8) in. (mm)
4 lucent technologies inc. ts16-type 2.5 gbits/s translight transponder with advance data sheet 16-channel 155 mbits/s multiplexer/demulitplexer august 2000 block diagram 1-11011 (f).c figure 1. ts16-type transponder block diagram oc-48/stm-16 optical transmitter d ck d oc-48/stm-16 optical receiver w/clock recovery 16:1 parallel timing clock divider frame/byte timing 1:16 serial mux mux t x dis mux generation to serial and phase detect detect gen to parallel mux lsrbias lsralrm lpm t x d[0:15]p t x d[0:15]n piclkp/n phinit pherr pclkp/n t x refclkp/n lloop dloop framen search fp poclkp/n r x q[0:15]p r x q[0:15]n los 16 16 2 2 2 2 16 16 oof lockdet reset ipdmon
5 lucent technologies inc. advance data sheet ts16-type 2.5 gbits/s translight transponder with august 2000 16-channel 155 mbits/s multiplexer/demulitplexer pin information 1-1014(f).c figure 2. ts16-type transponder pinout rxq13n rxq13p rxq15n rxq15p rxdgnd nc nc nc nc poclkn poclkp rx3.3a rxagnd rxagnd search rx3.3d rx3.3d rxdgnd oof rxdgnd los lloop pherr nc txdis phinit nc tx3.3a tx3.3d txagnd txdgnd pclkn pclkp txdgnd txd00n txd00p txdgnd txd02n txd02p txd04n txd04p txdgnd txd06n txd06p txd08n txd08p txdgnd txd10n txd10p txd12n txd12p txdgnd txd14n txd14p txrefclkn txdgnd reset fgnd rxdgnd rxq12n rxq12p rxq14n rxq14p rxdgnd nc nc nc rxdgnd rxagnd rxagnd rx3.3a rxagnd rxagnd nc rx3.3d fp nc dloop nc lsrbias lsralm lpm txagnd tx3.3a tx3.3a txagnd tx3.3d tx3.3d txdgnd lockdet piclkn piclkp txdgnd txd01n txd01p txd03n txd03p txdgnd txd05n txd05p txd07p txdgnd txd09n txd09p txd11n txd11p txdgnd txd13n txd13p txd15n txd15p txdgnd ipdmon fgnd rxdgnd 140 60 130 50 120 40 110 30 100 20 90 10 1 81 tx txrefclkp txd07n framen rx3.3d rxdgnd rxq05n rxq05p rxq07n rxq07p rxdgnd rxq09n rxq09p rxq11n rxq11p rxdgnd rxq04n rxq04p rxq06n rxq06p rxdgnd rxq08n rxq08p rxq10n rxq10p rxdgnd 150 70 nc nc nc nc rxdgnd rxq01n rxq01p rxq03n rxq03p fgnd nc nc nc nc rxdgnd rxq00n rxq00p rxq02n rxq02p fgnd 160 80 rx top view
6 lucent technologies inc. ts16-type 2.5 gbits/s translight transponder with advance data sheet 16-channel 155 mbits/s multiplexer/demulitplexer august 2000 pin descriptions table 1. ts16-type transponder pinout pin # pin name i/o logic description 01 fgnd i supply frame ground * 02 ipdmon o analog receiver photodiode current monitor 03 txdgnd i supply transmitter digital ground 04 txd15p i lvpecl transmitter 155 mbits/s msb data input 05 txd15n i lvpecl transmitter 155 mbits/s msb data input 06 txd13p i lvpecl transmitter 155 mbits/s data input 07 txd13n i lvpecl transmitter 155 mbits/s data input 08 txdgnd i supply transmitter digital ground 09 txd11p i lvpecl transmitter 155 mbits/s data input 10 txd11n i lvpecl transmitter 155 mbits/s data input 11 txd09p i lvpecl transmitter 155 mbits/s data input 12 txd09n i lvpecl transmitter 155 mbits/s data input 13 txdgnd i supply transmitter digital ground 14 txd07p i lvpecl transmitter 155 mbits/s data input 15 txd07n i lvpecl transmitter 155 mbits/s data input 16 txd05p i lvpecl transmitter 155 mbits/s data input 17 txd05n i lvpecl transmitter 155 mbits/s data input 18 txdgnd i supply transmitter digital ground 19 txd03p i lvpecl transmitter 155 mbits/s data input 20 txd03n i lvpecl transmitter 155 mbits/s data input 21 txd01p i lvpecl transmitter 155 mbits/s data input 22 txd01n i lvpecl transmitter 155 mbits/s data input 23 txdgnd i supply transmitter digital ground 24 pic lk p i lvpecl byte-aligned parallel input clock at 155 mhz 25 pic lk n i lvpecl byte-aligned parallel input clock at 155 mhz 26 lockdet o lvttl lock detect 27 txdgnd i supply transmitter digital ground 28 tx3.3d i supply transmitter 3.3 v digital supply 29 tx3.3d i supply transmitter 3.3 v digital supply 30 txagnd i supply transmitter analog ground 31 tx3.3a i supply transmitter 3.3 v analog supply 32 tx3.3a i supply transmitter 3.3 v analog supply 33 txagnd i supply transmitter analog ground 34 lpm o analog laser power monitor 35 lsralrm o lvttl laser degrade alarm (active-low) 36 lsrbias o analog transmitter laser bias output 37 nc no user connection permitted 38 d loop i lvttl diagnostic loopback 39 nc no user connection permitted 40 fp o lvpecl frame pulse 41 framen i lvttl frame enable 42 rxdgnd i supply receiver digital ground * frame ground is connected to the housing and is isolated from all circuit grounds (txdgnd, txagnd, rxdgnd, rxagnd).
7 lucent technologies inc. advance data sheet ts16-type 2.5 gbits/s translight transponder with august 2000 16-channel 155 mbits/s multiplexer/demulitplexer 43 rx3.3d i supply receiver 3.3 v digital supply 44 rx3.3d i supply receiver 3.3 v digital supply 45 nc no user connection permitted 46 rxagnd i supply receiver analog ground 47 rxagnd i supply receiver analog ground 48 rx3.3a i supply receiver 3.3 v analog supply 49 rxagnd i supply receiver analog ground 50 rxagnd i supply receiver analog ground 51 rxdgnd i supply receiver digital ground 52 nc no user connection permitted 53 nc no user connection permitted 54 nc no user connection permitted 55 rxdgnd i supply receiver digital ground 56 rxq14p o lvpecl receiver 155 mbits/s data output 57 rxq14n o lvpecl receiver 155 mbits/s data output 58 rxq12p o lvpecl receiver 155 mbits/s data output 59 rxq12n o lvpecl receiver 155 mbits/s data output 60 rxdgnd i supply receiver digital ground 61 rxq10p o lvpecl receiver 155 mbits/s data output 62 rxq10n o lvpecl receiver 155 mbits/s data output 63 rxq08p o lvpecl receiver 155 mbits/s data output 64 rxq08n o lvpecl receiver 155 mbits/s data output 65 rxdgnd i supply receiver digital ground 66 rxq06p o lvpecl receiver 155 mbits/s data output 67 rxq06n o lvpecl receiver 155 mbits/s data output 68 rxq04p o lvpecl receiver 155 mbits/s data output 69 rxq04n o lvpecl receiver 155 mbits/s data output 70 rxdgnd i supply receiver digital ground 71 rxq02p o lvpecl receiver 155 mbits/s data output 72 rxq02n o lvpecl receiver 155 mbits/s data output 73 rxq00p o lvpecl receiver 155 mbits/s lsb data output 74 rxq00n o lvpecl receiver 155 mbits/s lsb data output 75 rxdgnd i supply receiver digital ground 76 nc no user connection permitted 77 nc no user connection permitted 78 nc no user connection permitted 79 nc no user connection permitted 80 fgnd i supply frame ground * 81 fgnd i supply frame ground * 82 reset i lvttl master reset 83 txdgnd i supply transmitter digital ground 84 txr ef c lk p i lvpecl transmitter 155 mbits/s reference clock input pin # pin name i/o logic description pin descriptions (continued) table 1. ts16-type transponder pinout (continued) * frame ground is connected to the housing and is isolated from all circuit grounds (txdgnd, txagnd, rxdgnd, rxagnd).
8 lucent technologies inc. ts16-type 2.5 gbits/s translight transponder with advance data sheet 16-channel 155 mbits/s multiplexer/demulitplexer august 2000 85 txr ef c lk n i lvpecl transmitter 155 mbits/s reference cloc k input 86 txd14p i lvpecl transmitter 155 mbits/s data input 87 txd14n i lvpecl transmitter 155 mbits/s data input 88 txdgnd i supply transmitter digital ground 89 txd12p i lvpecl transmitter 155 mbits/s data input 90 txd12n i lvpecl transmitter 155 mbits/s data input 91 txd10p i lvpecl transmitter 155 mbits/s data input 92 txd10n i lvpecl transmitter 155 mbits/s data input 93 txdgnd i supply transmitter digital ground 94 txd08p i lvpecl transmitter 155 mbits/s data input 95 txd08n i lvpecl transmitter 155 mbits/s data input 96 txd06p i lvpecl transmitter 155 mbits/s data input 97 txd06n i lvpecl transmitter 155 mbits/s data input 98 txdgnd i supply transmitter digital ground 99 txd04p i lvpecl transmitter 155 mbits/s data input 100 txd04n i lvpecl transmitter 155 mbits/s data input 101 txd02p i lvpecl transmitter 155 mbits/s data input 102 txd02n i lvpecl transmitter 155 mbits/s data input 103 txdgnd i supply transmitter digital ground 104 txd00p i lvpecl transmitter 155 mbits/s lsb data input 105 txd00n i lvpecl transmitter 155 mbits/s lsb data input 106 txdgnd i supply transmitter digital ground 107 pc lk p o lvpecl transmitter parallel reference clock output 108 pc lk n o lvpecl transmitter parallel reference clock output 109 txdgnd i supply transmitter digital ground 110 txagnd i supply transmitter analog ground 111 tx3.3d i supply transmitter digital 3.3 v supply 112 tx3.3a i supply transmitter analog 3.3 v supply 113 nc no user connection permitted 114 phinit i lvpecl phase initialization 115 t x dis i ttl transmitter disable 116 nc no user connection permitted 117 pherr o lvpecl phase error 118 l loop i lvttl line loopback (active-low) 119 los o lvttl loss of signal 120 rxdgnd i supply receiver digital ground 121 oof i lvttl out of frame (enable frame detection) 122 rxdgnd i supply receiver digital ground 123 rx3.3d i supply receiver digital 3.3 v supply 124 rx3.3d i supply receiver digital 3.3 v supply 125 search o lvttl frame search output 126 rxagnd i supply receiver analog ground pin # pin name i/o logic description pin descriptions (continued) table 1. ts16-type transponder pinout (continued) * frame ground is connected to the housing and is isolated from all circuit grounds (txdgnd, txagnd, rxdgnd, rxagnd).
9 lucent technologies inc. advance data sheet ts16-type 2.5 gbits/s translight transponder with august 2000 16-channel 155 mbits/s multiplexer/demulitplexer * frame ground is connected to the housing and is isolated from all circuit grounds (txdgnd, txagnd, rxdgnd, rxagnd). 127 rxagnd i supply receiver analog ground 128 rx3.3a i supply receiver analog 3.3 v supply 129 poc lk p o lvpecl byte-aligned parallel output clock at 155 mhz 130 poc lk n o lvpecl byte-aligned parallel output clock at 155 mhz 131 nc no user connection permitted 132 nc no user connection permitted 133 nc no user connection permitted 134 nc no user connection permitted 135 rxdgnd i supply receiver digital ground 136 rxq15p o lvpecl receiver msb 155 mbits/s data output 137 rxq15n o lvpecl receiver msb 155 mbits/s data output 138 rxq13p o lvpecl receiver 155 mbits/s data output 139 rxq13n o lvpecl receiver 155 mbits/s data output 140 rxdgnd i supply receiver digital ground 141 rxq11p o lvpecl receiver 155 mbits/s data output 142 rxq11n o lvpecl receiver 155 mbits/s data output 143 rxq09p o lvpecl receiver 155 mbits/s data output 144 rxq09n o lvpecl receiver 155 mbits/s data output 145 rxdgnd i supply receiver digital ground 146 rxq07p o lvpecl receiver 155 mbits/s data output 147 rxq07n o lvpecl receiver 155 mbits/s data output 148 rxq05p o lvpecl receiver 155 mbits/s data output 149 rxq05n o lvpecl receiver 155 mbits/s data output 150 rxdgnd i supply receiver digital ground 151 rxq03p o lvpecl receiver 155 mbits/s data output 152 rxq03n o lvpecl receiver 155 mbits/s data output 153 rxq01p o lvpecl receiver 155 mbits/s data output 154 rxq01n o lvpecl receiver 155 mbits/s data output 155 rxdgnd i supply receiver digital ground 156 nc no user connection permitted 157 nc no user connection permitted 158 nc no user connection permitted 159 nc no user connection permitted 160 fgnd i supply frame ground * pin # pin name i/o logic description pin descriptions (continued) table 1. ts16-type transponder pinout (continued)
10 lucent technologies inc. ts16-type 2.5 gbits/s translight transponder with advance data sheet 16-channel 155 mbits/s multiplexer/demulitplexer august 2000 pin descriptions (continued) * future versions of the ts16 transponder will not support the frame-detect function. table 2. ts16-type transponder input pin descriptions pin name pin description txd[0:15]p txd[0:15]n parallel input data bus (16-bit differential lvpecl). txd15p/n is the most signif- icant bit of the input word and is the ?rst bit serialized. txd00p/n is the least signi?- cant bit of the input word and is the last bit serialized. txd[0:15]p/n is sampled on the rising edge of pic lk . pic lk p pic lk n parallel input clock (differential lvpecl). a 155 mhz nominally 50% duty cycle input clock to which txd[0:15]p/n is aligned. the rising edge of pic lk transfers the data on the 16 txd inputs into the holding register of the parallel-to-serial converter. txr ef c lk p txr ef c lk n reference clock input (internally biased differential lvpecl). this input is used as the reference for the internal clock frequency synthesizer that generates the 2.5 ghz bit rate clock used to shift data out of the parallel-to-serial converter and also for the byte-rate clock, which transfers the 16-bit parallel input data from the input holding register into the parallel-to-serial shift register. internally terminated and biased. see discussion on timing interfacing in the transponder interfacing section, page 14. txdis transmitter disable input. a logic high on this input pin shuts off the transmitters laser so that there is no optical output. if left open circuit, the transmitter will be per- manently enabled. d loop diagnostic loopback enable (lvttl). when the d loop input is low, the 2.5 gbits/s serial data stream from the parallel-to-serial converter is looped back internally to the serial-to-parallel converter along with an internally generated bit syn- chronous serial clock. the received serial data path from the optical receiver is dis- abled. l loop line loopback enable (lvttl). when l loop is low, the 2.5 gbits/s serial data and recovered clock from the optical receiver are looped directly back to the optical trans- mitter. the multiplexed serial data from the parallel-to-serial converter is ignored. phinit phase initialization (single-ended lvpecl). this input is used to align the internal elastic store (fifo). a rising edge on phinit will realign internal timing. (see discus- sion on fifo in the timing characteristics section, page 18.) framen* frame enable (lvttl). enables the frame detection circuitry to detect a1 a2 byte alignment and to lock to a word boundary. the ts16 transponder will contin- ually perform frame acquisition as long as framen is held high. when this input is low, the frame-detection circuitry is disabled. frame-detection process is initiated by rising edge of out-of-frame pulse. oof* out of frame (lvttl). this input indicator is typically generated by external sonet/sdh overhead monitor circuitry in response to a state in which the frame boundaries of the received sonet/sdh signal are unknown, i.e., after system reset or loss of synchronization. the rising edge of the oof input initiates the frame detec- tion function if framen is high. the fp output goes high when the frame boundary is detected in the incoming serial data stream from the optical receiver. reset master reset (lvttl). reset input for the multiplexer/demultiplexer. a logic low on this input clears all buffers and registers. during reset, poc lk and pc lk do not tog- gle.
11 lucent technologies inc. advance data sheet ts16-type 2.5 gbits/s translight transponder with august 2000 16-channel 155 mbits/s multiplexer/demulitplexer pin descriptions (continued) * future versions of the ts16 transponder will not support the frame-detect function. table 3. ts16-type transponder output pin descriptions pin name pin description rxq[0:15]p rxq[0:15]n parallel output data (16-bit differential lvpecl) . rxq[0:15] is the 155 mbyte/s 16-bit output word. rxq15p/n is the most signi?cant bit of the received word and is the ?rst bit serialized. rxq00p/n is the least signi?cant bit of the received word and is the last bit serialized. rxq[0:15]p/n is updated on the falling edge of poc lk . poc lk p poc lk n parallel output clock (differential lvpecl). a 155 mhz nominally 50% duty cycle, byte rate output clock that is aligned to the rxq[0:15] byte serial output data. rxq[0:15] and fp are updated on the falling edge of poc lk . fp* frame pulse (lvpecl). indicates frame boundaries in the received serial data stream. if framing pattern detection is enabled (framen high and oof), fp pulses high for one poc lk cycle when a 32-bit sequence matching the framing pattern is detected in the received serial data. fp is updated on the falling edge of poc lk . search* a1 a2 frame search output (lvttl). a high on this output pin indicates that the frame detection circuit is activated and is searching for a new a1 a2 byte alignment. this output will be high during the entire a1 a2 frame search. once a new alignment is found, this signal will remain high for a minimum of one 155 mhz clock period beyond the third a2 byte before it will be set low. los loss of signal (lvttl). a low on this output indicates a loss of lock by the clock recovery circuit in the optical receiver. lsrbias laser bias (analog). provides an indication of the health of the laser in the trans- mitter. this output changes at the rate of 20 mv/ma of bias current. if this output volt- age reaches 1.4 v (70 ma of bias), the automatic power control circuit is struggling to maintain output power. this may indicate that the transmitter has reached an end- of-life condition. lsralrm laser degrade alarm (lvttl). active-low alarm that indicates when the transmit- ters optical output power has degraded 3 db from its nominal operating power. lpm laser power monitor (analog). provides an indication of the output power level from the transmitter laser. this output is typically 500 mv for the nominal transmitter optical output power. if the optical power decreases by 3 db, this output will drop to approximately 250 mv, and if the output power should increase by 3 db, this output will increase to 1000 mv. pc lk p/n parallel byte clock (differential lvpecl). a byte-rate reference clock generated by dividing the internal 2.488 ghz serial bit clock by 16. this output is normally used to synchronize byte-wide transfers from upstream logic into the ts16 transponder. (see timing characteristics section for additional details, page 18.) pherr phase error signal (single-ended lvpecl). pulses high during each pc lk cycle for which there is a potential setup/hold timing violation between the internal byte clock and the plc lk timing domains. pherr is updated on the falling edge of the plc lk outputs. idpmon receiver photodiode current monitor (analog). this pin provides an output that is a mirror of the photocurrent generated by the optical receivers photodiode (apd or pin). this output will range from ~1 mv to ~800 mv, depending on the optical input power. lockdet lock detect (lvttl). this output goes low after the transmit side pll has locked to the clock signal provided at the t x r ef c lk input pins. lockdet is an asynchronous output.
12 12 lucent technologies inc. ts16-type 2.5 gbits/s translight transponder with advance data sheet 16-channel 155 mbits/s multiplexer/demulitplexer august 2000 functional description receiver the optical receiver in the ts16-type transponder is opti- mized for the particular sdh/sonet application segment in which it was designed to operate and will have either an apd or pin photodetector. the detected serial data output of the optical receiver is connected to a clock and data recovery circuit (cdr), which extracts a 2488.32 mhz clock signal. this recovered serial bit clock signal and a retimed serial data signal are presented to the 16-bit serial-to-parallel converter and to the frame and byte detection logic. note: future versions of the ts16-type transponder will not support the frame-detect function. the serial-to-parallel converter consists of three 16-bit registers. the ?rst is a serial-in parallel-out shift register, which performs serial-to-parallel conversion. the second is an internal 16-bit holding register, which transfers data from the serial-to-parallel register on byte boundaries as determined by the frame and byte detection logic. on the falling edge of the free-running poc lk signal, the data in the holding register is transferred to the output holding register where it becomes available as r x q[0:15]. the frame and byte boundary detection circuitry searches the incoming data for three consecutive a1 bytes followed immediately by an a2 byte. framing pattern detection is enabled and disabled by the framen input. the frame detection process is started by a rising edge on oof while framen is active (framen = high). it is disabled when a framing pattern is detected. when framing pattern detection is enabled (framen = high), the framing pat- tern is used to locate byte and frame boundaries in the incoming serial data stream from the cdr circuits. during this time, the parallel output data bus (r x q[0:15]) will not contain valid data. the timing generator circuitry takes the located byte boundary and uses it to block the incoming serial data stream into bytes for output on the parallel out- put data bus (r x q[0:15]). the frame boundary is reported on the framing pulse (fp) output when any 32-bit pattern matching the framing pattern is detected in the incoming serial data stream. when framing detection is disabled (framen = low), the byte boundary is ?xed at the loca- tion found when frame detection was previously enabled. transmitter the optical transmitter in the ts16-type transponder is optimized for the particular sdh/sonet segment in which it is designed to operate. the transmitter will have either a fabry-perot or a dfb laser as the optical element and can operate at either 1310 nm or 1550 nm. the trans- mitter is driven by a serial data stream developed in the parallel-to-serial conversion logic and by a 2488.32 mhz serial bit clock signal synthesized from the 155.52 mhz t x r ef c lk input. note that the clock divider and phase-detect circuitry shown in figure 1 generates internal reference clocks and timing functions for the transmitter. therefore, it is impor- tant that the t x r ef c lk input is generated from a precise and stable source. to prevent internal timing signals from producing jitter in the transmitted serial data that exceeds the sdh/sonet jitter generation requirements of 0.01 ui, it is required that the t x r ef c lk input be generated from a crystal oscillator or other source having a frequency accu- racy better than 20 ppm. in order to meet the sdh/ sonet jitter generation requirement, the reference clock jitter must be guaranteed to be less than 1 ps rms over the 12 khz to 20 mhz bandwidth. when used in sonet net- work applications, this input clock must be derived from a source that is synchronized to the primary reference clock. the timing generation circuitry provides two separate functions. it develops a byte rate clock that is synchro- nized to the 2488.32 mhz transmit serial clock, and it pro- vides a mechanism for aligning the phase between the incoming byte clock (piclk) and the clock that loads the parallel data from the input register into the parallel-to- serial shift register. the pc lk output is a byte rate (155 mhz) version of the serial transmit clock and is intended for use by upstream multiplexing and overhead processing circuits. using pc lk for upstream circuits will ensure a stable frequency and phase relationship between the parallel data coming into the transmitter and the subsequent parallel-to-serial timing functions. in the parallel-to-serial conversion pro- cess, the incoming data is passed from the pic lk byte clock timing domain to the internally generated byte clock timing domain that is phase aligned to the internal serial transmit clock. the timing generator also produces a feed- back reference clock to the phase detector. a counter divides the synthesized clock down to the same frequency as the reference clock t x r ef c lk . the parallel-to-serial converter shown in figure 1 is com- prised of an fifo and a parallel-to-serial register. the fifo input latches the data from the t x d[0:15]p/n bus on the rising edge of pic lk . the parallel-to-serial register is a loadable shift register that takes parallel input from the fifo output. an internally generated divide-by-16 clock, which is phase aligned to the transmit serial clock, as described above, activates the parallel data transfer between registers. the serial data is shifted out of the par- allel-to-serial register at the transmit serial clock rate.
13 lucent technologies inc. advance data sheet ts16-type 2.5 gbits/s translight transponder with august 2000 16-channel 155 mbits/s multiplexer/demulitplexer functional description (continued) loopback modes the ts16 transponder is capable of operating in either of the two loopback modes: diagnostic loopback or line loopback. line loopback when lloop is pulled low, the received serial data stream and recovered 2488.32 mhz serial clock from the optical receiver are connected directly to the serial data and clock inputs of the optical transmitter. this establishes a receive-to-transmit loopback at the serial line rate. diagnostic loopback when dloop is pulled low, a loopback path is estab- lished from the transmitter to the receiver. in this mode, the serial data from the parallel-to-serial converter and the transmit serial clock are looped back to the serial- to-parallel converter and the frame and byte detect cir- cuitry, respectively. transponder interfacing the txd[0:15]p/n and pic lk p/n inputs and the rxq[0:15]p/n, poc lk p/n, and pc lk p/n outputs are high-speed (155 mbits/s), lvpecl differential data and clock signals. to maintain optimum signal ?delity, these inputs and outputs must be connected to their termi- nating devices via 50 w controlled-impedance trans- mission lines. the transmitter inputs (txd[0:15]p/n and pic lk p/n) must be terminated as close as possi- ble to the ts16 transponder connector with a thvenin equivalent impedance equal to 50 w terminated to vcc C 2 v. the receiver outputs (rxq[0:15]p/n, poc lk p/n, and pc lk p/n) must be terminated as close as possible to the device (ic) that these signals interface with a thvenin-equivalent impedance equal to 50 w termi- nated to vcc C 2 v. figure 3, below, shows one example of the proper ter- minations. other methods may be used, provided they meet the requirements stated above. 1-1054(f).b figure 3. transponder interfacing txd[0:15]p 130 w 80 w 80 w 130 w 3.3 v 130 w 80 w 80 w 130 w 3.3 v sonet/sdh rxline txline 50 w impedance ts16-type transponder transmission lines 50 w impedance transmission lines interface ic connector (lvpecl) txd[0:15]n (lvpecl) rxd[0:15]p (lvpecl) rxd[0:15]n (lvpecl) mux demux tx rx
14 14 lucent technologies inc. ts16-type 2.5 gbits/s translight transponder with advance data sheet 16-channel 155 mbits/s multiplexer/demulitplexer august 2000 functional description (continued) transponder interfacing (continued) txr ef c lk p/n the t x r ef c lk input is different than the other inputs to the transmitter in that it is internally terminated, ac-cou- pled, and self-biased. therefore, it must be treated dif- ferently than the t x d and pic lk inputs. differentially, the input impedance at this input is 100 w , but due to the way it is biased internally, when driven single- ended, the impedance appears as 60 w . the proper termination scheme for the t x r ef c lk input is shown in figure 4. figure 4. interfacing to the txrefclk input interface ic (v cc = 3.3 v) pll clock synthesizer multiplexer ts16 transponder txrefclkp txrefclkn 50 w transmission lines differential interface connector 100 w 330 w 330 w sonet/sdh interface ic (v cc = 3.3 v) pll clock synthesizer multiplexer ts16 transponder txrefclkp txrefclkn 50 w transmission lines single-ended interface connector 60 w 330 w 0.1 m f 300 w for a single-ended input, the input impedance is equivalent to 60 w. sonet/sdh lvpecl lvpecl 1-1084(f.b)
15 lucent technologies inc. advance data sheet ts16-type 2.5 gbits/s translight transponder with august 2000 16-channel 155 mbits/s multiplexer/demulitplexer optical characteristics minimum and maximum values speci?ed over operating case temperature range at 50% duty cycle data signal. typical values are measured at room temperature unless otherwise noted. table 4. oc48/stm-16 transmitter optical characteristics (tc = 0 c to 65 c) 1. output power de?nitions and measurements per itu-t recommendation g.957. 2. full spectral width measured 20 db down from the central wavelength peak under fully modulated conditions. 3. ratio of the average output power in the dominant longitudinal mode to the power in the most signi?cant side mode under fully modulated conditions. 4. ratio of logic 1 output power to logic 0 output power under fully modulated conditions. 5. gr-253-core, synchronous optical network (sonet) transport systems: common generic criteria. 6. itu-t recommendation g.957, optical interfaces for equipment and systems relating to the synchronous digital hierarchy. table 5. oc48/stm-16 receiver optical characteristics (tc = 0 c to 65 c) 1. at 1310 nm, 1 x 10 C10 ber, 2 23 C 1 pseudorandom data input. parameter symbol min typ max unit average output power: 1 intraof?ce (f-p laser) short reach (dfb laser) p o C10 C5 C5 C2 C3 0 dbm dbm operating wavelength: intraof?ce (f-p laser) short reach (dfb laser) l 1270 1270 1360 1360 nm nm spectral width: intraof?ce (f-p laser) short reach and long reach (dfb laser) 2 dl rms dl 20 4 1 nm nm side-mode suppression ratio (dfb laser) 3 ssr 30 db extinction ratio 4 r e 8.2 db optical rise and fall times t r , t f 200 ps eye mask of optical output 5, 6 compliant with gr-253 and itu-t g.957 jitter generation compliant with gr-253 and itu-t g.958 parameter symbol min typ max unit average receiver sensitivity 1 : pin receiver apd receiver p rmin p rmin C21 C30 dbm dbm maximum optical power: pin receiver apd receiver (long reach) p rmax p rmax 0 C6 dbm dbm optical path penalty 1 db receiver re?ectance C27 db jitter tolerance and jitter transfer compliant with gr-253 and itu-t g.958
16 lucent technologies inc. ts16-type 2.5 gbits/s translight transponder with advance data sheet 16-channel 155 mbits/s multiplexer/demulitplexer august 2000 electrical characteristics table 6. transmitter electrical i/o characteristics (t c = 0 c to 65 c, v cc = 3.3 v 5%) 1. 20% to 80%. 2. internally biased and ac-coupled. 3. the transmitter is normally enabled and only requires an external voltage to disable. 4. output conversion factor is 20 mv/ma of laser bias current. 5. set at 500 mv at nominal output power. will track p o linearly (C3 db = 250 mv, +3 db = 1000 mv). 6. terminated into 220 w to gnd and 100 w line-to-line. parameter symbol logic min typ max unit parallel input clock pic lk p/n diff. lvpecl 153.90 155.52 157.00 mhz parallel clock in duty cycle 40 60 % reference clock frequency tolerance txr ef c lk p/n diff. lvpecl C20 20 ppm reference clock input duty cycle 45 55 % reference clock rise and fall times 1 1.5 ns reference clock jitter (in 12 khz to 20 mhz band) 1 ps rms reference clock input signal levels 2 : differential input signal level, d v indiff single-ended input signal level, d v insingle differential input resistance, d r txr ef c lk ? diff. lvpecl 260 130 80 100 1200 600 120 mv mv w input data signal levels: input high, v ih input low, v il differential input voltage swing, d v indiff single-ended input voltage swing, d v insingle txd[0:15]p/n diff. lvpecl v cc C 1.2 v cc C 2.0 400 200 v cc C 0.3 v cc C 0.5 2000 1000 v v mv mv transmitter disable input 3 txd is ttl (5 v) 2.0 5.5 v transmitter enable input 3 txe n ttl (5 v) 0 0.8 v laser bias voltage output 4 lsrbias analog 0 200 1600 mv laser power monitor output 5 lpm analog 35 500 1000 mv laser degrade alarm: output high, v oh output low, v ol lsralm lvttl 2.0 0 v cc 0.8 v v phase initialization: input high, v ih input low, v il phinit lvpecl v cc C 1.2 v cc C 2.3 v cc C 0.47 v cc C 1.44 v v phase error 5 : output high, v oh output low, v ol pulse lvpecl v cc C 1.15 v cc C 1.95 v cc C 0.60 v cc C 1.44 v v line loopback enable (active-low): input high, v ih input low, v il l loop lvttl 2.0 0 v cc + 1.0 0.8 v v diagnostic loopback enable (active-low): input high, v ih input low, v il d loop lvttl 2.0 0 v cc + 1.0 0.8 v v parallel output clock 6 : output high, v oh output low, v ol pc lk p/n diff. lvpecl v cc C 1.15 v cc C 1.95 v cc C 0.60 v cc C 1.45 v v
17 lucent technologies inc. advance data sheet ts16-type 2.5 gbits/s translight transponder with august 2000 16-channel 155 mbits/s multiplexer/demulitplexer electrical characteristics (continued) table 7. receiver electrical i/o characteristics (tc = 0 c to 65 c, vcc = 3.3 v 5%) 1. terminated into 220 w to gnd and 100 w line-to-line. 2. 20% to 80%, 330 w to ground. 3. 220 w to gnd. table 8. power supply characteristics (tc = 0 c to 65 c) * does not include current in output load terminations. parameter symbol logic min typ max unit parallel output clock: output high, v oh output low, v ol poc lk p/n differential lvpecl v cc C 1.15 v cc C 1.95 v cc C 0.6 v cc C 1.45 v v poc lk duty cycle 45 55 % output data signal levels 1 : output high, v oh output low, v ol rxq[0:15]p/n differential lvpecl v cc C 1.15 v cc C 1.95 v cc C 0.6 v cc C 1.45 v v rxq[0:15] rise/fall time 2 1.0 ns frame pulse 3 : output high, v oh output low, v ol fp lvpecl v cc C 1.15 v cc C 1.95 v cc C 0.6 v cc C 1.45 v v loss-of-signal output: output high, v oh output low, v ol los lvttl 2.2 0 v cc 0.5 v v out-of-frame input: input high, v ih input low, v il oof lvttl 2.0 0.0 v cc 0.8 v v frame enable input input high, v ih input low, v il f ram e n lvttl 2.0 0.0 v cc 0.8 v v parameter symbol min typ max unit supply voltage v cc 3.13 3.3 3.47 v dc power supply current drain* i cc 1.15 1.7 a power dissipation p diss 3.8 6 w
18 18 lucent technologies inc. ts16-type 2.5 gbits/s translight transponder with advance data sheet 16-channel 155 mbits/s multiplexer/demulitplexer august 2000 timing characteristics transmitter data input timing the ts16 transponder utilizes a unique fifo to decouple the internal and external (pic lk ) clocks. the fifo can be initialized, which allows the system designer to have an in?nite pc lk -to-pic lk delay through the interfacing logic (asic or commercial chip set). the con?guration of the fifo is dependent upon the i/o pins, which comprise the synch timing loop. this loop is formed from pherr to phinit and pc lk to pic lk . the fifo can be thought of as a memory stack that can be initialized by phint or lockdet. the pherr signal is a pointer that goes high when a potential tim- ing mismatch is detected between pic lk and the inter- nally generated pc lk clock. when pherr is fed back to phinit, it initializes the fifo so that it does not over- ?ow or under?ow. the internally generated divide-by-16 clock is used to clock out data from the fifo. phinit and lockdet signals will center the fifo after the third pic lk pulse. this is done to ensure that pic lk is stable. this scheme allows the user to have an in?nite pc lk to pic lk delay through the asic. once the fifo is cen- tered, the pc lk and pic lk can have a maximum drift of 5 ns. during normal operation, the incoming data is passed from the pic lk i nput timing domain to the internally generated divide-by-16 pc lk timing domain. although the frequency of pic lk and pc lk are the same, their phase relationship is arbitrary. to prevent errors caused by short setup or hold times between the two domains, the timing generator circuitry monitors the phase rela- tionship between pic lk and pc lk . when an fifo timing violation is detected, the phase error (pherr) signal pulses high. if the condition per- sists, pherr will remain high. when pherr is fed back into the phinit input (by shorting them on the printed-circuit board [pcb]), phinit will initialize the fifo if phinit is held high for at least two byte clocks. the initialization of the fifo prevents pc lk and pic lk from concurrently trying to read and write over the same fifo bank. during realignment, one to three bytes (16 bits wide) will be lost. alternatively, the customer logic can take in the pherr signal, process it, and send an output to the phinit input in such a way that only idle bytes are lost during the initialization of the fifo. once the fifo has been initialized, pherr will go inactive.
19 lucent technologies inc. advance data sheet ts16-type 2.5 gbits/s translight transponder with august 2000 16-channel 155 mbits/s multiplexer/demulitplexer timing characteristics (continued) input timing mode 1 in the con?guration shown in figure 5, pherr to phinit has a zero delay (shorted on the pcb) and the pc lk is used to clock 16-bit-wide data out of the cus- tomer asic. the fifo in the multiplexer is 16-bits wide and six registers deep. the pc lk and pic lk signals respectively control the read and write counters for the fifo. the data bank from the fifo has to be read by the internally generated clock (pc lk ) only once after it has been writ- ten by the pic lk input. since the delay in the customer asic is unknown, the two clocks (pc lk and pic lk ) might drift in respect to each other and try to perform the read and write opera- tion on the same bank in the fifo at the same time. however, before such a clock mismatch can occur, pherr goes high and, if externally connected to phinit, will initialize the fifo provided phinit remains high for at least two byte clocks. one to three 16-bit words of data will be lost during the initialization of the fifo. figure 5. block diagram timing mode 1 customer logic ts16 transponder fifo pll divider oscillator t x refclk 16 pherr phinit pclk piclk lockdet 155.52 mhz 20 ppm timing generator internal txd[0:15] clock data centers fifo pclk 1-1120(f).a
20 20 lucent technologies inc. ts16-type 2.5 gbits/s translight transponder with advance data sheet 16-channel 155 mbits/s multiplexer/demulitplexer august 2000 timing characteristics input timing mode 2 to avoid the loss of data, idle or dummy bytes should be sent on the t x d[0:15] bus whenever pherr goes high. in the con?guration shown in figure 6, the pherr signal is used as an input to the customer logic. upon detecting a high on the pherr signal, the customer logic should return a high signal, one that remains high for at least two byte-clock cycles, to the phinit input of the ts16. also, when pherr goes high, the customer logic should start sending idle or dummy bytes to the ts16 on the t x d[0:15] bus. this should continue until pherr goes low. the fifo is initialized two-to-eight byte clocks after phinit goes high for two byte clocks. pherr goes low after the fifo is initialized. upon detecting a low on pherr, the customer logic can start sending real data bytes on t x d[0:15]. the two timing loops (pc lk to pic lk and pherr to phinit) do not have to be of equal length. figure 6. block diagram timing mode 2 customer logic ts16 transponder fifo pll divider oscillator t x refclk 16 pherr phinit pclk piclk lockdet 155.52 mhz 20 ppm timing generator internal txd[0:15] clock data centers fifo pclk d q 1121(f).a
21 lucent technologies inc. advance data sheet ts16-type 2.5 gbits/s translight transponder with august 2000 16-channel 155 mbits/s multiplexer/demulitplexer timing characteristics (continued) pc lk -to-pic lk timing after powerup or reset, the lockdet signal will go active, signifying that the pll has locked to the clock provided on the t x r ef c lk input. the fifo is initialized on the third pic lk after lockdet goes active. the pc lk -to-pic lk delay (t d ) can have any value before the fifo is initialized. the t d is ?xed at the third piclk after lockdet goes active. once the fifo is initial- ized, pc lk and pic lk cannot drift more than 5.2 ns; tch cannot be more than 5.2 ns. figure 7. pc lk -to-pic lk timing pclk piclk lockdet active 3rd is initalized at the third rising edge of piclk after lockdet goes active. pclk-to-piclk delay is fixed and fifo 2nd 1st tch tch td td 1123(f).a
22 22 lucent technologies inc. ts16-type 2.5 gbits/s translight transponder with advance data sheet 16-channel 155 mbits/s multiplexer/demulitplexer august 2000 timing characteristics (continued) pherr/phinit case 1 pherr and phinit are shorted on the printed-circuit board: phinit would go high whenever there is a potential timing mismatch between pc lk and pic lk . phinit would remain high as long as the timing mismatch between pc lk and pic lk exists. if phinit is high for more than two byte clocks, the fifo will be initialized. phinit will initialize the fifo two-to-eight byte clocks after it is high for at least two byte clocks, pherr (and thus phinit) goes active once the fifi is initialized. case 2pherr signal is input to the customer logic and the customer logic outputs a signal to phinit: another possible con?guration is where the pherr signal is input into the customer logic and the customer logic sends an output to the phinit input. however, the customer logic must ensure that, upon detecting a high on pherr, the phinit signal remains high for more than two byte clocks. if phinit is high for less than two byte clocks, the fifo is not guaranteed to be initialized. also, the customer logic must ensure that phinit goes low after the fifo is initialized (pherr goes low). figure 8. pherr/phinit timing pherr phinit pclk piclk internal pclk minimum pulse width required to center the fifo 2 byte clocks 28 byte clocks customer asic sends a minimum pulse width of 2 byte clocks upon detecting a high on pherr fifo is initialized 28 byte clocks after phinit is high for 2 byte clocks pherr goes high on detecting a fifo timing error 1-1125(f)
23 lucent technologies inc. advance data sheet ts16-type 2.5 gbits/s translight transponder with august 2000 16-channel 155 mbits/s multiplexer/demulitplexer timing characteristics (continued) transmitter data input timing (continued) figure 9. ac input timing * 20% to 80%; 330 w to gnd. figure 10. receiver output timing diagram table 9. transmitter ac timing characteristics symbol description min max unit t st x d txd[0:15] setup time w. r. t. pic lk 1.5 ns t ht x d txd[0:15] hold time w. r. t. pic lk 0.5 ns pc lk p/n duty cycle 40 60 % pic lk p/n duty cycle 40 60 % t ppic lk pic lk -to-pic lk drift after fifo centered 5 ns table 10. receiver ac timing characteristics symbol description min max unit poc lk duty cycle 45 55 % rxd[15:0] rise and fall time * 1.0 ns tp pout poc lk low to rxd[15:0] valid prop. delay C1 1 ns ts pout rxd[15:0] and fp setup time w. r. t. poc lk 2ns th pout rxd[15:0] and fp hold time w. r. t. poc lk 2ns piclkp txd[0:15] t stxd t htxd poclkp fp tp pout ts pout th pout rxd[15:0] 1-1027(f).r1 1-1022(f)
24 24 lucent technologies inc. ts16-type 2.5 gbits/s translight transponder with advance data sheet 16-channel 155 mbits/s multiplexer/demulitplexer august 2000 timing characteristics (continued) receiver framing note: future versions of the ts16-type transponder will not support frame synchronous opera- tion. figure 11 shows a typical reframe sequence in which a byte realignment is made. the frame and byte bound- ary detection is enabled by the rising edge of oof. both the frame and byte boundaries are recognized upon receipt of the ?rst a2 byte following three consec- utive a1 bytes. the third a2 byte is the ?rst data byte to be reported with the correct byte alignment on the out- going data bus (rxd[15:0]). concurrently, the frame pulse (fp) is set high for one poc lk cycle. the frame and byte boundary detection block is acti- vated by the rising edge of oof and stays active until the ?rst fp pulse. figure 12 shows the frame and byte boundary detec- tion activation by a rising edge of oof and deactivation by the ?rst fp pulse. figure 13 shows the frame and byte boundary detec- tion by the activation of a rising edge of oof and deac- tivation by the framen input. figure 11. frame and byte detection figure 12. oof timing (framen = high) recovered clock oof serial data r x d[15:0] poclk a1 a1 a1 a2 a2 a2 a2 a2 a2 a1, a1 a1, a1 a1, a1 a2, a2 a2, a2 a2, a2 a2, a2 invalid data valid data fp note 1 1. range of input to output delay can be 1.5 2.5 poc lk cycles. oof fp search boundary detection enabled 1-1023(f).a 1-1024(f)
25 lucent technologies inc. advance data sheet ts16-type 2.5 gbits/s translight transponder with august 2000 16-channel 155 mbits/s multiplexer/demulitplexer timing characteristics (continued) receiver framing 1-1024(f).a figure 13. framen timing oof fp search boundary detection enabled framen
26 lucent technologies inc. ts16-type 2.5 gbits/s translight transponder with advance data sheet 16-channel 155 mbits/s multiplexer/demulitplexer august 2000 quali?cation and reliability to help ensure high product reliability and customer satisfaction, lucent is committed to an intensive quality pro- gram that starts in the design phase and proceeds through the manufacturing process. optoelectronics modules are quali?ed to lucent internal standards using mil-std-883 test methods and procedures and using sampling techniques consistent with telcordia technologies * requirements. this quali?cation program fully meets the intent of telcordia technologies reliability practices tr-nwt-000468 and ta-tsy-000983. in addition, the lucent tech- nologies microelectronics group optoelectronics design, development, and manufacturing facility has been certi- ?ed to be in full compliance with the latest iso ? -9001 quality system standards. laser safety information class i laser product all versions of the ts16-type transponders are classi?ed as class i laser products per fda/cdrh, 21 cfr 1040 laser safety requirements. the transponders have been registered/certi?ed with the fda under accession number 8720009. all versions are classi?ed as class i laser products per iec ? 60825-1:1993. caution: use of controls, adjustments, and procedures other than those speci?ed herein may result in hazardous laser radiation exposure. this product complies with 21 cfr 1040.10 and 1040.11. 8.8 m m/125 m m single-mode pigtail with 900 m m tight buffer jacket and connector. wavelength = 1.3 m m. maximum power = 1.5 mw. product is not shipped with power supply. because of size constraints, laser safety labeling is not af?xed to the module but is attached to the outside of the shipping carton. notice unterminated optical connectors can emit laser radiation. do not view with optical instruments. electromagnetic emissions and immunity the ts16 transponder will be tested against cenelec en50 081 part 1 and part 2, fcc 15, class b limits for emissions. the ts16 transponder will be tested against cenelec en50 082 part 1 immunity requirements. * telcordia technologies is a trademark of bell communications research, inc. ? iso is a registered trademark of the international organization for standardization. ? iec is a registered trademark of the international electrotechnical commission.
27 lucent technologies inc. advance data sheet ts16-type 2.5 gbits/s translight transponder with august 2000 16-channel 155 mbits/s multiplexer/demulitplexer outline diagram dimensions are in inches and (millimeters). 1-1096 (f).b 2.008 pin 1 1.840 160-pin jae connector p/n wr-160sb-vf-a3 (4x) m2.5 mounting holes 4 places (51.00) (46.74) 0.471 (11.96) c l 0.512 (13.00) 0.084 (2.13) 2.854 (72.49) 0.689 (17.50) max sc connectors 1.800 (45.72) 0.396 (10.06) 0.984 (24.99) 1 m 10 cm product label rx tx mating p/n wr-160pb-vf50-a3 pin 81 pin 80 pin 160 (4x) m2.5 mounting holes 4 places 8.75 mm maximum length into package.
for additional information, contact your microelectronics group account manager or the following: internet: http://www.lucent.com/micro , or for optoelectronics information, http://www.lucent.com/micro/opto e-mail: docmaster@micro.lucent.com n. america: microelectronics group, lucent technologies inc., 555 union boulevard, room 30l-15p-ba, allentown, pa 18109-3286 1-800-372-2447 , fax 610-712-4106 (in canada: 1-800-553-2448 , fax 610-712-4106) asia pacific: microelectronics group, lucent technologies singapore pte. ltd., 77 science park drive, #03-18 cintech iii, singapore 118256 tel. (65) 778 8833 , fax (65) 777 7495 china: microelectronics group, lucent technologies (china) co., ltd., a-f2, 23/f, zao fong universe building, 1800 zhong shan xi road, shanghai 200233 p. r. china tel. (86) 21 6440 0468 , ext. 325 , fax (86) 21 6440 0652 japan: microelectronics group, lucent technologies japan ltd., 7-18, higashi-gotanda 2-chome, shinagawa-ku, tokyo 141, japan tel. (81) 3 5421 1600 , fax (81) 3 5421 1700 europe: data requests: microelectronics group dataline: tel. (44) 7000 582 368 , fax (44) 1189 328 148 technical inquiries: optoelectronics marketing: (44) 1344 865 900 (ascot uk) lucent technologies inc. reserves the right to make changes to the product(s) or information contained herein without notice. no liability is assumed as a result of their use or application. no rights under any patent accompany the sale of any such product(s) or information. translight is a trademark of lucent technologies inc. copyright ? 2000 lucent technologies inc. all rights reserved august 2000 ds00-257opto (replaces ds00-133opto) ts16-type 2.5 gbits/s translight transponder with advance data sheet 16-channel 155 mbits/s multiplexer/demulitplexer august 2000 ordering information * other connectors may be made available. table 11. ordering information code application connector comcode ts16n1caa 1310 nm, intraof?ce sc 108482415 TS16N1FAA 1310 nm, intraof?ce fc/pc 108482423 ts16n1waa 1310 nm, intraof?ce lc 108770900 ts16s1caa 1310 nm, short haul sc 108482431 ts16s1faa 1310 nm, short haul fc/pc 108482449 ts16l1caa 1310 nm, long haul sc 108482480 ts16l1faa 1310 nm, long haul fc/pc 108482498 ts16l2caa 1550 nm, long haul sc 108482506 ts16l2faa 1550 nm, long haul fc/pc 108482514 order code: 16 xx x xx ts C CC basic part number stm level application 16 = stm-16 (sonet oc-48) n1 = i-16, 1310 nm, intraoffice (sonet short reach) s1 = s-16.1, 1310 nm, short haul (sonet ir-1) l1 = l-16.1 1310 nm, long haul (sonet lr-1) options connector * c = sc l2 = l-16.2, 1550 nm, long haul (sonet lr-2) f = fc/pc w = lc

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