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1 ltc1871-7 18717fb high input voltage, current mode boost, flyback and sepic controller the ltc ? 1871-7 is a current mode, boost, flyback and sepic controller optimized for driving 6v-rated mosfets in high voltage applications. the ltc1871-7 works equally well in low or high power applications and requires few components to provide a complete power supply solu- tion. the switching frequency can be set with an external resistor over a 50khz to 1mhz range, and can be synchro- nized to an external clock using the mode/sync pin. burst mode operation at light loads, a low minimum operating supply voltage of 6v and a low shutdown quiescent current of 10 a make the ltc1871-7 well suited for battery-operated systems. for applications requiring constant frequency operation, burst mode op- eration can be defeated using the mode/sync pin. the ltc1871-7 is available in the 10-lead msop package. optimized for high input voltage applications wide chip supply voltage range: 6v to 36v internal 7v low dropout voltage regulator optimized for 6v-rated mosfets current mode control provides excellent transient response high maximum duty cycle (92% typ) 2% run pin threshold with 100mv hysteresis 1% internal voltage reference micropower shutdown: i q = 10 a programmable operating frequency (50khz to 1mhz) with one external resistor synchronizable to an external clock up to 1.3 f osc user-controlled pulse skip or burst mode ? operation output overvoltage protection can be used in a no r sense tm mode for v ds < 36v small 10-lead msop package telecom power supplies 42v automotive systems 24v industrial controls ip phone power supplies figure 1. small, nonisolated 12v flyback telecom housekeeping supply , ltc and lt are registered trademarks of linear technology corporation. burst mode is a registered trademark of linear technology corporation. no r sense is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. parameter ltc1871-7 ltc1871 intv cc 7.0v 5.2v intv cc uv + 5.6v 2.1v intv cc uv C 4.6v 1.9v descriptio u features applicatio s u typical applicatio u run i th fb freq mode/sync sense v in intv cc gate gnd ltc1871-7 120k 4.7 f x5r 2.2 f 100v x7r m1 fdc2512 0.12 ? v in 36v to 72v 3.4k 2.2nf 26.7k d3 10bq060 47 f 16v x5r v out 12v 0.4a 604k 12.4k t1 vp1-0076 100k 10 ? q1 fmmt625 d2 4148 d1 9.1v 110k 0.1 f x5r 3:1 18717 f01 ? ?
2 ltc1871-7 18717fb (note 1) v in voltage ............................................... C 0.3v to 36v intv cc voltage ........................................... C 0.3v to 9v intv cc output current ........................................ 50ma gate voltage ........................... C 0.3v to v intvcc + 0.3v i th , fb voltages ....................................... C 0.3v to 2.7v run voltage ............................................... C 0.3v to 7v mode/sync voltage ...................................C 0.3v to 9v freq voltage ............................................C 0.3v to 1.5v sense pin voltage ................................... C 0.3v to 36v operating temperature range (note 2) ltc1871e-7 ....................................... C 40 c to 85 c ltc1871i-7 ...................................... C 40 c to 125 c junction temperature (note 3) ............................ 125 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c absolute axi u rati gs w ww u package/order i for atio uu w electrical characteristics the denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v in = 8v, v run = 1.5v, r freq = 80k, v mode/sync = 0v, unless otherwise specified. symbol parameter conditions min typ max units main control loop v in(min) minimum input voltage 6 v i-grade (note 2) 6v i q input voltage supply current (note 4) continuous mode v mode/sync = 5v, v fb = 1.4v, v ith = 0.75v 550 1000 a v mode/sync = 5v, v fb = 1.4v, v ith = 0.75v, 600 1100 a i-grade (note 2) burst mode operation, no load v mode/sync = 0v, v ith = 0.2v (note 5) 280 500 a v mode/sync = 0v, v ith = 0.2v (note 5), 280 600 a i-grade (note 2) shutdown mode v run = 0v 12 25 a v run = 0v, i-grade (note 2) 12 25 a v run + rising run input threshold voltage 1.348 v v run C falling run input threshold voltage 1.223 1.248 1.273 v 1.198 1.298 v v run(hyst) run pin input threshold hysteresis 50 100 150 mv i-grade (note 2) 35 100 175 mv i run run input current 560 na v fb feedback voltage v ith = 0.2v (note 5) 1.218 1.230 1.242 v 1.212 1.248 v v ith = 0.2v (note 5), i-grade (note 2) 1.205 1.255 v i fb fb pin input current v ith = 0.2v (note 5) 18 60 na ? v fb line regulation 6v v in 30v 0.002 0.02 %/v ? v in 6v v in 30v, i-grade (note 2) 0.002 0.02 %/v t jmax = 125 c, ja = 120 c/ w 1 2 3 4 5 run i th fb freq mode/ sync 10 9 8 7 6 sense v in intv cc gate gnd top view ms package 10-lead plastic msop order part number ms part marking consult ltc marketing for parts specified with wider operating temperature ranges. ltc1871ems-7 ltc1871ims-7 ltg4 ltbtr order options tape and reel: add #tr lead free: add #pbf lead free tape and reel: add #trpbf lead free part marking: http://www.linear.com/leadfree/
3 ltc1871-7 18717fb electrical characteristics the denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v in = 8v, v run = 1.5v, r freq = 80k, v mode/sync = 0v, unless otherwise specified. symbol parameter conditions min typ max units ? v fb load regulation v mode/sync = 0v, v ith = 0.5v to 0.9v (note 5) C1 C0.1 % ? v ith v mode/sync = 0v, v ith = 0.5v to 0.9v (note 5) C1 C0.1 % i-grade (note 2) ? v fb(ov) ? fb pin, overvoltage lockout v fb(ov) C v fb(nom) in percent 2.5 6 10 % g m error amplifier transconductance i th pin load = 5 a (note 5) 600 mho v ith(burst) burst mode operation i th pin voltage falling i th voltage (note 5) 0.3 v v sense(max) maximum current sense input threshold duty cycle < 20% 120 150 180 mv duty cycle < 20%, i-grade (note 2) 100 200 mv i sense(on) sense pin current (gate high) v sense = 0v 35 70 a i sense(off) sense pin current (gate low) v sense = 30v 0.1 5 a oscillator f osc oscillator frequency r freq = 80k 250 300 350 khz r freq = 80k, i-grade (note 2) 250 300 350 khz oscillator frequency range 50 1000 khz i-grade (note 2) 50 1000 khz d max maximum duty cycle 87 92 97 % i-grade (note 2) 87 92 98.5 % f sync/ f osc recommended maximum synchronized f osc = 300khz (note 6) 1.25 1.30 frequency ratio f osc = 300khz (note 6), i-grade (note 2) 1.25 1.30 t sync(min) mode/sync minimum input pulse width v sync = 0v to 5v 25 ns t sync(max) mode/sync maximum input pulse width v sync = 0v to 5v 0.8/f osc ns v il(mode) low level mode/sync input voltage 0.3 v i-grade (note 2) 0.3 v v ih(mode) high level mode/sync input voltage 1.2 v i-grade (note 2) 1.2 v r mode/sync mode/sync input pull-down resistance 50 k ? v freq nominal freq pin voltage 0.62 v low dropout regulator v intvcc intv cc regulator output voltage v in = 8v 6.5 7 7.5 v v in = 8v, i-grade (note 2) 6.5 7 7.5 v uvlo intvcc undervoltage lockout threshold rising intv cc 5.6 v falling intv cc 4.6 v uvlo hysteresis 1.0 v ? v intvcc intv cc regulator line regulation 8v v in 15v 8 25 mv ? v in1 ? v intvcc intv cc regulator line regulation 15v v in 30v 70 200 mv ? v in2 v ldo(load) intv cc load regulation 0 i intvcc 20ma, v in = 8v C 2 C 0.2 % v dropout intv cc regulator dropout voltage v in = 6v, intv cc load = 20ma 280 mv gate driver t r gate driver output rise time c l = 3300pf (note 7) 17 100 ns t f gate driver output fall time c l = 3300pf (note 7) 8 100 ns
4 ltc1871-7 18717fb typical perfor a ce characteristics uw fb voltage vs temp fb voltage line regulation fb pin current vs temperature shutdown mode i q vs v in burst mode i q vs v in shutdown mode i q vs temperature temperature ( c) C50 fb voltage (v) 1.23 1.24 150 18717 g01 1.22 1.21 0 50 100 C25 25 75 125 1.25 v in (v) 0 1.229 fb voltage (v) 1.230 1.231 5101520 18717 g02 25 30 35 temperature ( c) C50 0 fb pin current (na) 10 20 30 40 60 C25 25 0 50 100 75 18717 g03 125 150 50 v in (v) 0 0 shutdown mode i q ( a) 10 20 10 20 30 40 18717 g04 30 temperature ( c) C50 0 shutdown mode i q ( a) 5 10 15 20 C25 0 25 50 18717 g05 75 100 125 150 v in = 8v v in (v) 0 0 burst mode i q ( a) 100 200 300 400 600 10 20 18717 g06 30 40 500 electrical characteristics note 1: absolute maximum ratings are those values beyond which the life of the device may be impaired. note 2: the ltc1871e-7 is guaranteed to meet performance specifications from 0 c to 70 c junction temperature. specifications over the C 40 c to 85 c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the ltc1871i-7 is guaranteed over the full C40 c to 125 c operating junction temperature range. note 3: t j is calculated from the ambient temperature t a and power dissipation p d according to the following formula: t j = t a + (p d ? 120 c/w) note 4: the dynamic input supply current is higher due to power mosfet gate charging (q g ? f osc ). see applications information. note 5: the ltc1871-7 is tested in a feedback loop that servos v fb to the reference voltage with the i th pin forced to a voltage between 0v and 1.4v (the no load to full load operating voltage range for the i th pin is 0.3v to 1.23v). note 6: in a synchronized application, the internal slope compensation gain is increased by 25%. synchronizing to a significantly higher ratio will reduce the effective amount of slope compensation, which could result in subharmonic oscillation for duty cycles greater than 50%. note 7: rise and fall times are measured at 10% and 90% levels.
5 ltc1871-7 18717fb typical perfor a ce characteristics uw run thresholds vs v in r t vs frequency frequency vs temperature sense pin current vs temperature maximum sense threshold vs temperature run thresholds vs temperature v in (v) 0 1.2 run thresholds (v) 1.3 1.4 10 20 30 40 18717 g10 1.5 temperature ( c) C50 run thresholds (v) 1.30 1.35 150 18717 g11 1.25 1.20 0 50 100 C25 25 75 125 1.40 frequency (khz) 100 r t (k ? ) 300 1000 18717 g12 10 100 200 1000 900 800 700 600 500 400 0 temperature ( c) C50 275 gate frequency (khz) 280 290 295 300 325 310 0 50 75 18717 g13 285 315 320 305 C25 25 100 125 150 temperature ( c) C50 140 max sense threshold (mv) 145 150 155 160 C25 0 25 50 18717 g14 75 100 125 150 temperature ( c) C50 25 sense pin current ( a) 30 35 0 50 75 18717 g15 C25 25 100 125 150 gate high v sense = 0v burst mode i q vs temperature gate drive rise and fall time vs c l dynamic i q vs frequency temperature ( c) C50 0 burst mode i q ( a) 200 500 0 50 75 18717 g07 100 400 300 C25 25 100 125 150 frequency (khz) 0 0 i q (ma) 2 6 8 10 800 18 18717 g08 4 400 1200 600 200 1000 12 14 16 c l = 3300pf i q(tot) = 600 a + qg ? f c l (pf) 0 0 time (ns) 10 20 30 40 60 2000 4000 6000 8000 18717 g09 10000 12000 50 rise time fall time
6 ltc1871-7 18717fb uu u pi fu ctio s run (pin 1): the run pin provides the user with an accurate means for sensing the input voltage and pro- gramming the start-up threshold for the converter. the falling run pin threshold is nominally 1.248v and the comparator has 100mv of hysteresis for noise immunity. when the run pin is below this input threshold, the ic is shut down and the v in supply current is kept to a low value (typ 10 a). the absolute maximum rating for the voltage on this pin is 7v. i th (pin 2): error amplifier compensation pin. the cur- rent comparator input threshold increases with this control voltage. nominal voltage range for this pin is 0v to 1.40v. fb (pin 3): receives the feedback voltage from the external resistor divider across the output. nominal voltage for this pin in regulaton is 1.230v. freq (pin 4): a resistor from the freq pin to ground programs the operating frequency of the chip. the nomi- nal voltage at the freq pin is 0.6v. mode/sync (pin 5): this input controls the operating mode of the converter and allows for synchronizing the operating frequency to an external clock. if the mode/ sync pin is connected to ground, burst mode operation is enabled. if the mode/sync pin is connected to intv cc , or if an external logic-level synchronization signal is applied to this input, burst mode operation is disabled and the ic operates in a continuous mode. gnd (pin 6): ground pin. gate (pin 7): gate driver output. i ntv cc (pin 8): the internal 7v regulator output. the gate driver and control circuits are powered from this voltage. decouple this pin locally to the ic ground with a minimum of 4.7 f low esr tantalum or ceramic capacitor. this 7v regulator has an undervoltage lockout circuit with 5.6v and 4.6v rising and falling thresholds, respectively. v in (pin 9): main supply pin. must be closely decoupled to ground. sense (pin 10): the current sense input for the control loop. connect this pin to a resistor in the source of the power mosfet. alternatively, the sense pin may be connected to the drain of the power mosfet, in applications where the maximum v ds is less than 36v. internal leading edge blanking is provided for both sens- ing methods. typical perfor a ce characteristics uw intv cc load regulation intv cc dropout voltage vs current, temperature intv cc line regulation intv cc load (ma) 0 intv cc voltage (v) 7.0 30 50 80 18717 g16 6.9 6.8 10 20 40 60 70 v in = 8v v in (v) 0 6.9 intv cc voltage (v) 7.0 7.1 10 20 30 40 18717 g17 7.2 515 25 35 intv cc load (ma) 0 0 dropout voltage (mv) 50 150 200 250 500 350 5 10 18717 g18 100 400 450 300 15 20 150 c 75 c 125 c 25 c C50 c 0 c
7 ltc1871-7 18717fb block diagra w C + C + + 1.230v 85mv ov 50k ea uv to start-up control burst comparator s r q logic pwm latch current comparator 0.30v 1.230v 7v C + 5.6v up 4.6v down 1.230v slope 1.230v i loop fb i th C + g m 3 mode/sync 5 freq 4 2 intv cc 8 ldo v-to-i osc v-to-i slope compensation bias and start-up control v in bias v ref i osc r loop C + C + c1 sense 10 gnd 18717 bd 6 gate intv cc gnd 7 v in 1.248v 9 run c2 1 0.6v
8 ltc1871-7 18717fb main control loop the ltc1871-7 is a constant frequency, current mode controller for dc/dc boost, sepic and flyback converter applications. with the ltc1871-7 the current control loop can be closed by sensing the voltage drop either across the power mosfet switch or across a discrete sense resistor, as shown in figure 2. the nominal operating frequency of the ltc1871-7 is programmed using a resistor from the freq pin to ground and can be controlled over a 50khz to 1000khz range. in addition, the internal oscillator can be synchronized to an external clock applied to the mode/sync pin and can be locked to a frequency between 100% and 130% of its nominal value. when the mode/sync pin is left open, it is pulled low by an internal 50k resistor and burst mode operation is enabled. if this pin is taken above 2v or an external clock is applied, burst mode operation is disabled and the ic operates in continuous mode. with no load (or an extremely light load), the controller will skip pulses in order to maintain regulation and prevent excessive output ripple. the run pin controls whether the ic is enabled or is in a low current shutdown state. a micropower 1.248v refer- ence and comparator c2 allow the user to program the supply voltage at which the ic turns on and off (compara- tor c2 has 100mv of hysteresis for noise immunity). with the run pin below 1.248v, the chip is off and the input supply current is typically only 10 a. an overvoltage comparator ov senses when the fb pin exceeds the reference voltage by 6.5% and provides a reset pulse to the main rs latch. because this rs latch is reset-dominant, the power mosfet is actively held off for the duration of an output overvoltage condition. the ltc1871-7 can be used either by sensing the voltage drop across the power mosfet or by connecting the sense pin to a conventional shunt resistor in the source of the power mosfet, as shown in figure 2. sensing the voltage across the power mosfet maximizes converter efficiency and minimizes the component count, but limits the output voltage to the maximum rating for this pin (36v). by connecting the sense pin to a resistor in the source of the power mosfet, the user is able to program output voltages significantly greater than 36v. programming the operating mode for applications where maximizing the efficiency at very light loads (e.g., <100 a) is a high priority, the current in the output divider could be decreased to a few micro- amps and burst mode operation should be applied (i.e., the mode/sync pin should be connected to ground). figure 2. using the sense pin on the ltc1871-7 operatio u c out v sw v sw 2a. sense pin connection for maximum efficiency (v sw < 36v) v out v in gnd l d + c out r s 18717 f02 2b. sense pin connection for precise control of peak current or for v sw > 36v v out v in gnd l d + gate gnd v in sense gate gnd v in sense for circuit operation, please refer to the block diagram of the ic and figure 1. in normal operation, the power mosfet is turned on when the oscillator sets the pwm latch and is turned off when the current comparator c1 resets the latch. the divided-down output voltage is com- pared to an internal 1.230v reference by the error amplifier ea, which outputs an error signal at the i th pin. the voltage on the i th pin sets the current comparator c1 input threshold. when the load current increases, a fall in the fb voltage relative to the reference voltage causes the i th pin to rise, which causes the current comparator c1 to trip at a higher peak inductor current value. the average inductor current will therefore rise until it equals the load current, thereby maintaining output regulation.
9 ltc1871-7 18717fb operatio u in applications where fixed frequency operation is more critical than low current efficiency, or where the lowest output ripple is desired, pulse-skip mode operation should be used and the mode/sync pin should be connected to the intv cc pin. this allows discontinuous conduction mode (dcm) operation down to near the limit defined by the chips minimum on-time (about 175ns). below this output current level, the converter will begin to skip cycles in order to maintain output regulation. figures 3 and 4 show the light load switching waveforms for burst mode and pulse-skip mode operation for the converter in figure 1. burst mode operation burst mode operation is selected by leaving the mode/ sync pin unconnected or by connecting it to ground. in normal operation, the range on the i th pin corresponding to no load to full load is 0.30v to 1.2v. in burst mode operation, if the error amplifier ea drives the i th voltage below 0.525v, the buffered i th input to the current comparator c1 will be clamped at 0.525v (which corre- sponds to 25% of maximum load current). the inductor current peak is then held at approximately 30mv divided by the power mosfet r ds(on) . if the i th pin drops below 0.30v, the burst mode comparator b1 will turn off the power mosfet and scale back the quiescent current of the ic to 250 a (sleep mode). in this condition, the load current will be supplied by the output capacitor until the i th voltage rises above the 50mv hysteresis of the burst comparator. at light loads, short bursts of switching (where the average inductor current is 20% of its maxi- mum value) followed by long periods of sleep will be observed, thereby greatly improving converter efficiency. oscilloscope waveforms illustrating burst mode opera- tion are shown in figure 3. pulse-skip mode operation with the mode/sync pin tied to a dc voltage above 2v, burst mode operation is disabled. the internal, 0.525v buffered i th burst clamp is removed, allowing the i th pin to directly control the current comparator from no load to full load. with no load, the i th pin is driven below 0.30v, the power mosfet is turned off and sleep mode is invoked. oscilloscope waveforms illustrating this mode of operation are shown in figure 4. when an external clock signal drives the mode/sync pin at a rate faster than the chips internal oscillator, the oscillator will synchronize to it. in this synchronized mode, burst mode operation is disabled. the constant frequency associated with synchronized operation provides a more controlled noise spectrum from the converter, at the expense of overall system efficiency of light loads. when the oscillators internal logic circuitry detects a synchronizing signal on the mode/sync pin, the internal oscillator ramp is terminated early and the slope compen- sation is increased by approximately 30%. as a result, in applications requiring synchronization, it is recommended that the nominal operating frequency of the ic be pro- grammed to be about 75% of the external clock frequency. figure 3. ltc1871-7 burst mode operation (mode/sync = 0v) at low output current figure 4. ltc1871-7 low output current operation with burst mode operation disabled (mode/sync = intv cc ) v out 50mv/div i l 5a/div 10 s/div 18717 f03 mode/sync = 0v (burst mode operation) v out 50mv/div i l 5a/div 2 s/div 18717 f04 mode/sync = intv cc (pulse skip mode)
10 ltc1871-7 18717fb attempting to synchronize to too high an external fre- quency (above 1.3f o ) can result in inadequate slope com- pensation and possible subharmonic oscillation (or jitter). the external clock signal must exceed 2v for at least 25ns, and should have a maximum duty cycle of 80%, as shown in figure 5. the mosfet turn on will synchronize to the rising edge of the external clock signal. programming the operating frequency the choice of operating frequency and inductor value is a tradeoff between efficiency and component size. low frequency operation improves efficiency by reducing mosfet and diode switching losses. however, lower frequency operation requires more inductance for a given amount of load current. the ltc1871-7 uses a constant frequency architecture that can be programmed over a 50khz to 1000khz range with a single external resistor from the freq pin to ground, as shown in figure 1. the nominal voltage on the freq pin is 0.6v, and the current that flows into the freq pin is used to charge and discharge an internal oscillator capacitor. a graph for selecting the value of r t for a given operating frequency is shown in figure 6. intv cc regulator bypassing and operation an internal, p-channel low dropout voltage regulator pro- duces the 7v supply which powers the gate driver and logic circuitry within the ltc1871-7, as shown in figure 7. the intv cc regulator can supply up to 50ma and must be bypassed to ground immediately adjacent to the ic pins with a minimum of 4.7 f tantalum or ceramic capacitor. good bypassing is necessary to supply the high transient currents required by the mosfet gate driver. the ltc1871-7 contains an undervoltage lockout circuit which protects the external mosfet from switching at low gate-to-source voltages. this undervoltage circuit senses the intv cc voltage and has a 5.6v rising threshold and a 4.6v falling threshold. for input voltages that dont exceed 8v (the absolute maximum rating for intv cc is 9v), the internal low drop- out regulator in the ltc1871-7 is redundant and the intv cc pin can be shorted directly to the v in pin. with the intv cc pin shorted to v in , however, the divider that programs the regulated intv cc voltage will draw 14 a of current from the input supply, even in shutdown mode. for applications that require the lowest shutdown mode input supply current, do not connect the intv cc pin to v in . regardless of whether the intv cc pin is shorted to v in or not, it is always necessary to have the driver circuitry bypassed with a 4.7 f ceramic capacitor to ground immediately adjacent to the intv cc and gnd pins. in an actual application, most of the ic supply current is used to drive the gate capacitance of the power mosfet. as a result, high input voltage applications in which a large power mosfet is being driven at high frequencies can operatio u figure 6. timing resistor (r t ) value figure 5. mode/sync clock input and switching waveforms for synchronized operation 18717 f05 2v to 7v mode/ sync gate i l t min = 25ns 0.8t d = 40% t t = 1/f o frequency (khz) 100 r t (k ? ) 300 1000 18717 f06 10 100 200 1000 900 800 700 600 500 400 0
11 ltc1871-7 18717fb cause the ltc1871-7 to exceed its maximum junction temperature rating. the junction temperature can be estimated using the following equations: i q(tot) i q + f ? q g p ic = v in ? (i q + f ? q g ) t j = t a + p ic ? r th(ja) the total quiescent current i q(tot) consists of the static supply current (i q ) and the current required to charge and discharge the gate of the power mosfet. the 10-pin msop package has a thermal resistance of r th(ja) = 120 c/w. as an example, consider a power supply with v in =10v. the switching frequency is 200khz, and the maximum ambient temperature is 70 c. the power mosfet chosen is the fds3670(fairchild), which has a maximum r ds(on) of 35m ? (at room temperature) and a maximum total gate charge of 80nc (the temperature coefficient of the gate charge is low). i q(tot) = 600 a + 80nc ? 200khz = 16.6ma p ic = 10v ? 16.6ma = 166mw t j = 70 c + 120 c/w ? 166mw = 89.9 c t jrise = 19.9 c operatio u this demonstrates how significant the gate charge current can be when compared to the static quiescent current in the ic. to prevent the maximum junction temperature from being exceeded, the input supply current must be checked when operating in a continuous mode at high v in . a tradeoff between the operating frequency and the size of the power mosfet may need to be made in order to maintain a reliable ic junction temperature. prior to lowering the operating frequency, however, be sure to check with power mosfet manufacturers for their latest-and-great- est low q g , low r ds(on) devices. power mosfet manu- facturing technologies are continually improving, with newer and better performance devices being introduced almost yearly. output voltage programming the output voltage is set by a resistor divider according to the following formula: vv r r o =+ ? ? ? ? ? ? 1 230 1 2 1 .? the external resistor divider is connected to the output as shown in figure 1, allowing remote voltage sensing. the figure 7. bypassing the ldo regulator and gate driver supply C + 1.230v r2 r1 p-ch 7v driver gate c vcc 4.7 f x5r c in input supply 6v to 30v gnd place as close as possible to device pins m1 18717 f07 intv cc v in gnd logic 6v-rated power mosfet
12 ltc1871-7 18717fb figure 8b. on/off control using external logic figure 8c. external pull-up resistor on run pin for ?lways on?operation figure 8a. programming the turn-on and turn-off thresholds using the run pin operatio u resistors r1 and r2 are typically chosen so that the error caused by the current flowing into the fb pin during normal operation is less than 1% (this translates to a maximum value of r1 of about 250k). programming turn-on and turn-off thresholds with the run pin the ltc1871-7 contains an independent, micropower voltage reference and comparator detection circuit that remains active even when the device is shut down, as shown in figure 8. this allows users to accurately program an input voltage at which the converter will turn on and off. the falling threshold voltage on the run pin is equal to the internal reference voltage of 1.248v. the comparator has 100mv of hysteresis to increase noise immunity. the turn-on and turn-off input voltage thresholds are programmed using a resistor divider according to the following formulas: vv r r vv r r in off in on () () .? .? =+ ? ? ? ? ? ? =+ ? ? ? ? ? ? 1 248 1 2 1 1 348 1 2 1 the resistor r1 is typically chosen to be less than 1m. for applications where the run pin is only to be used as a logic input, the user should be aware of the 7v absolute maximum rating for this pin! the run pin can be connected to the input voltage through an external 1m resistor, as shown in figure 8c, for always on operation. C + run comparator v in run r2 r1 input supply optional filter capacitor + C gnd 18717 f8a bias and start-up control 1.248v power reference 6v C + run comparator 1.248v 18717 f08b run 6v external logic control C + run comparator v in run r2 1m input supply + C gnd 1.248v 18717 f08c 6v
13 ltc1871-7 18717fb application circuits a basic ltc1871-7 application circuit is shown in figure 9. external component selection is driven by the characteristics of the load and the input supply. the first topology to be analyzed will be the boost converter, followed by sepic (single-ended primary inductance converter). boost converter: duty cycle considerations for a boost converter operating in a continuous conduc- tion mode (ccm), the duty cycle of the main switch is: d vvv vv odin od = + + ? ? ? ? ? ? C where v d is the forward voltage of the boost diode. for converters where the input voltage is close to the output voltage, the duty cycle is low and for converters that develop a high output voltage from a low voltage input supply, the duty cycle is high. the maximum output voltage for a boost converter operating in ccm is: v v d v o max in min max d () () C C = () 1 the maximum duty cycle capability of the ltc1871-7 is typically 92%. this allows the user to obtain high output voltages from low input supply voltages. boost converter: the peak and average input currents the control circuit in the ltc1871-7 is measuring the input current typically using a sense resistor in the mosfet source, so the output current needs to be reflected back to the input in order to dimension the power mosfet prop- erly. based on the fact that, ideally, the output power is equal to the input power, the maximum average input current is: i i d the peak input current is i i d in max o max max in peak o max max () () () () C : ? C = =+ ? ? ? ? ? ? 1 1 21 the maximum duty cycle, d max , should be calculated at minimum v in . applicatio s i for atio wu uu run i th fb freq mode/sync sense v in intv cc gate gnd 1 2 3 4 5 10 9 8 7 6 ltc1871-7 f = 250khz r t 100k 1% r1 12.4k 1% r2 412k 1% r3 1m c vcc 4.7 f x5r r sense 0.005 ? 1w c in2 10 f 50v x5r 2 m1 d1 l1 6.8 h r c 24k c c1 2.2nf c c2 100pf c out1 68 f 100v 2 v in 8v to 28v v out 42v 1.5a gnd 18717 f09 + c in1 * 560 f 50v + c out2 10 f 50v x5r 2 c in1 : sanyo 50mv560axl (*recommended for lab evaluation for supply lead lengths greater than a few inches) c in2 : tdk c5750x5r1h106m c out1 : sanyo 100cv68fs c out2 : tdk c5750x5r1h106m d1: diodes inc b360b l1: cooper dr127-6r8 m1: siliconix/vishay si7370dp figure 9. a high efficiency 42v, 1.5a automotive boost converter
14 ltc1871-7 18717fb boost converter: ripple current ? i l and the ?factor the constant in the equation above represents the percentage peak-to-peak ripple current in the inductor, relative to its maximum value. for example, if 30% ripple current is chosen, then = 0.30, and the peak current is 15% greater than the average. for a current mode boost regulator operating in ccm, slope compensation must be added for duty cycles above 50% in order to avoid subharmonic oscillation. for the ltc1871-7, this ramp compensation is internal. having an internally fixed ramp compensation waveform, however, does place some constraints on the value of the inductor and the operating frequency. if too large an inductor is used, the resulting current ramp ( ? i l ) will be small relative to the internal ramp compensation (at duty cycles above 50%), and the converter operation will approach voltage mode (ramp compensation reduces the gain of the current loop). if too small an inductor is used, but the converter is still operating in ccm (near critical conduction mode), the internal ramp compensation may be inadequate to prevent subharmonic oscillation. to ensure good current mode gain and avoid subharmonic oscillation, it is recom- mended that the ripple current in the inductor fall in the range of 20% to 40% of the maximum average current. for example, if the maximum average input current is 1a, choose a ? i l between 0.2a and 0.4a, and a value between 0.2 and 0.4. boost converter: inductor selection given an operating input voltage range, and having chosen the operating frequency and ripple current in the inductor, the inductor value can be determined using the following equation: l v if d where i i d in min l max l omax max = ? ? = () () ? ? : ? C 1 remember that boost converters are not short-circuit protected. under a shorted output condition, the inductor current is limited only by the input supply capability. for applications requiring a step-up converter that is short- circuit protected, please refer to the applications section covering sepic converters. the minimum required saturation current of the inductor can be expressed as a function of the duty cycle and the load current, as follows: i i d l sat o max max () () ? C + ? ? ? ? ? ? 1 21 the saturation current rating for the inductor should be checked at the minimum input voltage (which results in the highest inductor current) and maximum output current. boost converter: operating in discontinuous mode discontinuous mode operation occurs when the load cur- rent is low enough to allow the inductor current to run out during the off-time of the switch, as shown in figure 10. once the inductor current is near zero, the switch and di- ode capacitances resonate with the inductance to form damped ringing at 1mhz to 10mhz. if the off-time is long enough, the drain voltage will settle to the input voltage. depending on the input voltage and the residual energy in the inductor, this ringing can cause the drain of the power mosfet to go below ground where it is clamped by the body diode. this ringing is not harmful to the ic and it has not been shown to contribute significantly to emi. any attempt to damp it with a snubber will degrade the efficiency. applicatio s i for atio wu uu figure 10. discontinuous mode waveforms for the converter shown in figure 9 output voltage 200mv/div inductor current 1a/div 1 s/div 18717 f10 mosfet drain voltage 20v/div
15 ltc1871-7 18717fb sense resistor selection during the switch on-time, the control circuit limits the maximum voltage drop across the sense resistor to about 150mv (at low duty cycle). the peak inductor current is therefore limited to 150mv/r sense . the relationship be- tween the maximum load current, duty cycle and the sense resistor r sense is: rv d i sense sense max max omax + ? ? ? ? ? ? () () ? C ? 1 1 2 the v sense(max) term is typically 150mv at low duty cycle, and is reduced to about 100mv at a duty cycle of 92% due to slope compensation, as shown in figure 11. it is worth noting that the 1 C d max relationship between i o(max) and r sense can cause boost converters with a wide input range to experience a dramatic range of maxi- mum input and output current. this should be taken into consideration in applications where it is important to limit the maximum current drawn from the input supply. the gate drive voltage is set by the 7v intv cc low drop regulator. consequently, 6v rated mosfets are required in most high voltage ltc1871-7 applications. pay close attention to the bv dss specifications for the mosfets relative to the maximum actual switch voltage in the application. the switch node can ring during the turn- off of the mosfet due to layout parasitics. check the switching waveforms of the mosfet directly across the drain and source terminals using the actual pc board lay- out (not just on a lab breadboard!) for excessive ringing. calculating power mosfet switching and conduction losses and junction temperatures in order to calculate the junction temperature of the power mosfet, the power dissipated by the device must be known. this power dissipation is a function of the duty cycle, the load current and the junction temperature itself (due to the positive temperature coefficient of its r ds(on) ). as a result, some iterative calculation is normally required to determine a reasonably accurate value. care should be taken to ensure that the converter is capable of delivering the required load current over all operating conditions (line voltage and temperature), and for the worst-case specifications for v sense(max) and the r ds(on) of the mosfet listed in the manufacturers data sheet. the power dissipated by the mosfet in a boost converter is: p i d rd kv i d cf fet omax ds on t o omax rss = ? ? ? ? ? ? + () () () () C ??? ?? C ?? 1 1 2 2 the first term in the equation above represents the i 2 r losses in the device, and the second term, the switching losses. the constant, k = 1.7, is an empirical factor inversely related to the gate drive current and has the dimension of 1/current. the t term accounts for the temperature coefficient of the r ds(on) of the mosfet, which is typically 0.4%/ c. figure 12 illustrates the varia- tion of normalized r ds(on) over temperature for a typical power mosfet. applicatio s i for atio wu uu duty cycle 0 maximum current sense voltage (mv) 100 150 0.8 18717 f11 50 0 0.2 0.4 0.5 1.0 200 figure 11. maximum sense threshold votlage vs duty cycle boost converter: power mosfet selection important parameters for the power mosfet include the drain-to-source breakdown voltage (bv dss ), the thresh- old voltage (v gs(th) ), the on-resistance (r ds(on) ) versus gate-to-source voltage, the gate-to-source and gate-to- drain charges (q gs and q gd , respectively), the maximum drain current (i d(max) ) and the mosfets thermal resis- tances (r th(jc) and r th(ja) ).
16 ltc1871-7 18717fb from a known power dissipated in the power mosfet, its junction temperature can be obtained using the following formula: t j = t a + p fet ? r th(ja) the r th(ja) to be used in this equation normally includes the r th(jc) for the device plus the thermal resistance from the case to the ambient temperature (r th(ca) ). this value of t j can then be compared to the original, assumed value used in the iterative calculation process. boost converter: output diode selection to maximize efficiency, a fast switching diode with low forward drop and low reverse leakage is desired. the output diode in a boost converter conducts current during the switch off-time. the peak reverse voltage that the diode must withstand is equal to the regulator output voltage. the average forward current in normal operation is equal to the output current, and the peak current is equal to the peak inductor current. ii i d d peak l peak o max max ()() () ? C ==+ ? ? ? ? ? ? 1 21 the power dissipated by the diode is: p d = i o(max) ? v d and the diode junction temperature is: t j = t a + p d ? r th(ja) the r th(ja) to be used in this equation normally includes the r th(jc) for the device plus the thermal resistance from the board to the ambient temperature in the enclosure. remember to keep the diode lead lengths short and to observe proper switch-node layout (see board layout checklist) to avoid excessive ringing and increased dissipation. boost converter: output capacitor selection contributions of esr (equivalent series resistance), esl (equivalent series inductance) and the bulk capacitance must be considered when choosing the correct compo- nent for a given output ripple voltage. the effects of these three parameters (esr, esl and bulk c) on the output voltage ripple waveform are illustrated in figure 13 for a typical boost converter. the choice of component(s) begins with the maximum acceptable ripple voltage (expressed as a percentage of the output voltage), and how this ripple should be divided between the esr step and the charging/discharging ? v. for the purpose of simplicity we will choose 2% for the maximum output ripple, to be divided equally between the esr step and the charging/discharging ? v. this percent- age ripple will change, depending on the requirements of the application, and the equations provided below can easily be modified. for a 1% contribution to the total ripple voltage, the esr of the output capacitor can be determined using the following equation: esr v i cout o in peak 001 .? () where: i i d in peak omax max () () ? C =+ ? ? ? ? ? ? 1 21 for the bulk c component, which also contributes 1% to the total ripple: c i vf out o max o () .? ? 001 applicatio s i for atio wu uu junction temperature ( c) C50 t normalized on resistance 1.0 1.5 150 18717 f12 0.5 0 0 50 100 2.0 figure 12. normalized r ds(on) vs temperature
17 ltc1871-7 18717fb for some designs it may be possible to choose a single capacitor type that satisfies both the esr and bulk c requirements for the design. in certain demanding appli- cations, however, the ripple voltage can be improved significantly by connecting two or more types of capaci- tors in parallel. for example, using a low esr ceramic capacitor can minimize the esr step, while an electrolytic capacitor can be used to supply the required bulk c. once the output capacitor esr and bulk capacitance have been determined, the overall ripple voltage waveform should be verified on a dedicated pc board (see board layout section for more information on component place- ment). lab breadboards generally suffer from excessive series inductance (due to inter-component wiring), and these parasitics can make the switching waveforms look significantly worse than they would be on a properly designed pc board. the output capacitor in a boost regulator experiences high rms ripple currents, as shown in figure 13. the rms output capacitor ripple current is: ii vv v rms cout o max o in min in min ()() () () ? C note that the ripple current ratings from capacitor manu- facturers are often based on only 2000 hours of life. this makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. several capacitors may also be placed in parallel to meet size or height requirements in the design. in surface mount applications, multiple capacitors may have to be placed in parallel in order to meet the esr or rms current handling requirements of the application. aluminum electrolytic and dry tantalum capacitors are both available in surface mount packages. in the case of tantalum, it is critical that the capacitors have been surge tested for use in switching power supplies. also, ceramic capacitors are now available with extremely low esr, esl and high ripple current ratings. boost converter: input capacitor selection the input capacitor of a boost converter is less critical than the output capacitor, due to the fact that the inductor is in series with the input and the input current waveform is continuous (see figure 13b). the input voltage source impedance determines the size of the input capacitor, which is typically in the range of 10 f to 100 f. a low esr capacitor is recommended, although it is not as critical as for the output capacitor. the rms input capacitor ripple current for a boost con- verter is: i v lf d rms cin in min max () () .? ? ? = 03 applicatio s i for atio wu uu v in ld sw 13a. circuit diagram 13b. inductor and input currents c out v out r l i in i l 13c. switch current i sw t on 13d. diode and output currents 13e. output voltage ripple waveform i o 18717 f13 i d v out (ac) t off ? v esr ringing due to total inductance (board + cap) ? v cout figure 13. switching waveforms for a boost converter
18 ltc1871-7 18717fb please note that the input capacitor can see a very high surge current when a battery is suddenly connected to the input of the converter and solid tantalum capacitors can fail catastrophically under these conditions. be sure to specify surge-tested capacitors! burst mode operation and considerations the choice of sense resistor and inductor value also determines the load current at which the ltc1871-7 enters burst mode operation. when bursting, the control- ler clamps the peak inductor current to approximately: i mv r burst peak sense () = 30 which represents about 20% of the maximum 150mv sense pin voltage. the corresponding average current depends upon the amount of ripple current. lower induc- tor values (higher ? i l ) will reduce the load current at which burst mode operations begins, since it is the peak current that is being clamped. the output voltage ripple can increase during burst mode operation if ? i l is substantially less than i burst . this can occur if the input voltage is very low or if a very large inductor is chosen. at high duty cycles, a skipped cycle causes the inductor current to quickly decay to zero. however, because ? i l is small, it takes multiple cycles for the current to ramp back up to i burst(peak) . during this inductor charging interval, the output capacitor must applicatio s i for atio wu uu table 1. recommended component manufacturers vendor components telephone web address avx capacitors (207) 282-5111 avxcorp.com bh electronics inductors, transformers (952) 894-9590 bhelectronics.com coilcraft inductors (847) 639-6400 coilcraft.com coiltronics inductors (407) 241-7876 coiltronics.com diodes, inc diodes (805) 446-4800 diodes.com fairchild mosfets (408) 822-2126 fairchildsemi.com general semiconductor diodes (516) 847-3000 generalsemiconductor.com international rectifier mosfets, diodes (310) 322-3331 irf.com irc sense resistors (361) 992-7900 irctt.com kemet tantalum capacitors (408) 986-0424 kemet.com magnetics inc toroid cores (800) 245-3984 mag-inc.com microsemi diodes (617) 926-0404 microsemi.com murata-erie inductors, capacitors (770) 436-1300 murata.co.jp nichicon capacitors (847) 843-7500 nichicon.com on semiconductor diodes (602) 244-6600 onsemi.com panasonic capacitors (714) 373-7334 panasonic.com sanyo capacitors (619) 661-6835 sanyo.co.jp sumida inductors (847) 956-0667 sumida.com taiyo yuden capacitors (408) 573-4150 t-yuden.com tdk capacitors, inductors (562) 596-1212 component.tdk.com thermalloy heat sinks (972) 243-4321 aavidthermalloy.com tokin capacitors (408) 432-8020 tokin.com toko inductors (847) 699-3430 tokoam.com united chemicon capacitors (847) 696-2000 chemi-com.com vishay/dale resistors (605) 665-9301 vishay.com vishay/siliconix mosfets (800) 554-5565 vishay.com vishay/sprague capacitors (207) 324-4140 vishay.com zetex small-signal discretes (631) 543-7100 zetex.com
19 ltc1871-7 18717fb supply the load current and a significant droop in the output voltage can occur. generally, it is a good idea to choose a value of inductor ? i l between 25% and 40% of i in(max) . the alternative is to either increase the value of the output capacitor or disable burst mode operation using the mode/sync pin. burst mode operation can be defeated by connecting the mode/sync pin to a high logic-level voltage (either with a control input or by connecting this pin to intv cc ). in this mode, the burst clamp is removed, and the chip can oper- ate at constant frequency from continuous conduction mode (ccm) at full load, down into deep discontinuous conduction mode (dcm) at light load. prior to skipping pulses at very light load (i.e., <5% of full load), the control- ler will operate with a minimum switch on-time in dcm. pulse skipping prevents a loss of control of the output at very light loads and reduces output voltage ripple. efficiency considerations the efficiency of a switching regulator is equal to the output power divided by the input power (100%). per- cent efficiency can be expressed as: % efficiency = 100% C (l1 + l2 + l3 + ), where l1, l2, etc. are the individual loss components as a percentage of the input power. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. although all dissipative elements in the circuit produce losses, four main sources usually account for the majority of the losses in ltc1871-7 application circuits: 1. the supply current into v in . the v in current is the sum of the dc supply current i q (given in the electrical characteristics) and the mosfet driver and control currents. the dc supply current into the v in pin is typically about 650 a and represents a small power loss (much less than 1%) that increases with v in . the driver current results from switching the gate capaci- tance of the power mosfet; this current is typically much larger than the dc current. each time the mosfet is switched on and then off, a packet of gate charge q g is transferred from intv cc to ground. the resulting dq/dt is a current that must be supplied to the intv cc capacitor through the v in pin by an external supply. if the ic is operating in ccm: i q(tot) i q = f ? q g p ic = v in ? (i q + f ? q g ) 2. power mosfet switching and conduction losses: p i d rd kv i d cf fet omax max ds on max t o omax max rss = ? ? ? ? ? ? + () () () C ??? ?? C ?? 1 1 2 2 3. the i 2 r losses in the sense resistor can be calculated almost by inspection. p i d rd r sense omax max sense max () () C ?? = ? ? ? ? ? ? 1 2 4. the losses in the inductor are simply the dc input current squared times the winding resistance. express- ing this loss as a function of the output current yields: p i d r r winding o max max w () () C ? = ? ? ? ? ? ? 1 2 5. losses in the boost diode. the power dissipation in the boost diode is: p diode = i o(max) ? v d the boost diode can be a major source of power loss in a boost converter. for 13.2v input, 42v output at 1.5a example given in figure 9, a schottky diode with a 0.4v forward voltage would dissipate 600mw, which repre- sents about 1% of the input power. diode losses can become significant at low output voltages where the forward voltage is a significant percentage of the output voltage. 6. other losses, including c in and c o esr dissipation and inductor core losses, generally account for less than 2% of the total losses. applicatio s i for atio wu uu
20 ltc1871-7 18717fb checking transient response the regulator loop response can be verified by looking at the load transient response at minimum and maximum v in . switching regulators generally take several cycles to respond to an instantaneous step in resistive load current. when the load step occurs, v o immediately shifts by an amount equal to ( ? i load )(esr), and then c o begins to charge or discharge (depending on the direction of the load step) as shown in figure 14. the regulator feedback loop acts on the resulting error amp output signal to return v o to its steady-state value. during this recovery time, v o can be monitored for overshoot or ringing that would indicate a stability problem. a second, more severe transient can occur when connect- ing loads with large (>1 f) supply bypass capacitors. the discharged bypass capacitors are effectively put in parallel with c o , causing a nearly instantaneous drop in v o . no regulator can deliver enough current to prevent this prob- lem if the load switch resistance is low and it is driven quickly. the only solution is to limit the rise time of the switch drive in order to limit the inrush current di/dt to the load. boost converter design example the design example given here will be for the circuit shown in figure 9. the input voltage is 8v to 28v, and the output is 42v at a maximum load current of 1.5a. 1. the maximum duty cycle is: d vvv vv odin od = + + ? ? ? ? ? ? = + + = C.C . .% 42 0 4 8 42 0 4 81 1 2. pulse-skip operation is chosen so the mode/sync pin is shorted to intv cc . 3. the operating frequency is chosen to be 250khz to reduce the size of the inductor. from figure 5, the resistor from the freq pin to ground is 100k. 4. an inductor ripple current of 40% of the maximum load current is chosen, so the peak input current (which is also the minimum saturation current) is: i i d a in peak o max max () () ? C .? . C. . =+ ? ? ? ? ? ? == 1 21 12 15 1081 947 the inductor ripple current is: ? == = i i d a l omax max ? C .? . C. . () 1 04 15 1081 32 and so the inductor value is: l v if d k h in min l max = ? == () ? ? .? ?. . 8 3 2 250 081 81 applicatio s i for atio wu uu v out 500mv/div i out 0.5a/div 0.5a 250 s/div 18717 f14a 1.5a v in = 8v v out 500mv/div i out 0.5a/div 0.5a 250 s/div 18717 f14b 1.5a v in = 28v figure 14a. load transient response for the circuit in figure 9 figure 14b. load transient response for the circuit in figure 9
21 ltc1871-7 18717fb the component chosen is a 6.8 h inductor made by cooper (part number dr127-6r8) which has a satura- tion current of greater than 13.3a. 5. because the duty cycle is 81%, the maximum sense pin threshold voltage is reduced from its low duty cycle typical value of 150mv to approximately 115mv. in addition, we need to apply a worst-case derating factor to this sense threshold to account for manufacturing tolerances within the ic. finally, the nominal current limit value should exceed the maximum load current by some safety margin (in this case 50%). therefore, the value of the sense resistor is: rv d i m sense sense max max o max = + ? ? ? ? ? ? == ? 08 1 1 04 2 15 08 0115 1081 12 15 15 65 .? ? C . ?.? .?. ? C. .?.?. . () () a 1w, 5m ? resistor is used in this design. 6. the mosfet chosen is a vishay/siliconix si7370dp, which has a bv dss of greater than 60v and an r ds(on) of less than 13m ? at a v gs of 6v. 7. the diode for this design must handle a maximum dc output current of 1.5a and be rated for a minimum reverse voltage of v out , or 42v. a 3a, 60v diode from diodes inc. (b360b) is chosen. 8. the output capacitor usually consists of a high valued bulk c connected in parallel with a lower valued, low esr ceramic. based on a maximum output ripple voltage of 1%, or 50mv, the bulk c needs to be greater than: c i vf k f out out max out == () .? ? . .? ? 001 15 0 01 42 250 14 the rms ripple current rating for this capacitor needs to exceed: ii vv v a rms cout o max oinmin in min ()() () () ? C .? C . = = 15 42 8 8 309 t o satisfy the low esr, high frequency decoupling requirements, two 10 f, 50v, x5r ceramic capacitors are used (tdk part number c5750x5r1h106m). in parallel with these, two 68 f, 100v electrolytic capaci- tors are used (sanyo part number 100cv68fs). check the output ripple with a single oscilloscope probe connected directly across the output capacitor termi- nals, where the hf switching currents flow. 9. the choice of an input capacitor for a boost converter depends on the impedance of the source supply and the amount of input ripple the converter will safely tolerate. for this particular design and lab setup a 560 f, 50v sanyo electrolytic (50mv560axl), in par- allel with two 10 f, 100v tdk ceramic capacitors (c5750x5r1h106m) is required (the input and return lead lengths are kept to a few inches, but the peak input current is close to 10a!). as with the output node, check the input ripple with a single oscilloscope probe connected across the input capacitor terminals. applicatio s i for atio wu uu v out 1v/div i l 2a/div mosfet drain voltage 20v/div 1 s/div 18717 f15 v in = 8v i out = 0.5a v out = 42v d = 81% figure 15. switching waveforms for the converter in figure 9 at minimum v in (8v)
22 ltc1871-7 18717fb pc board layout checklist 1. in order to minimize switching noise and improve output load regulation, the gnd pin of the ltc1871-7 should be connected directly to 1) the negative terminal of the intv cc decoupling capacitor, 2) the negative terminal of the output decoupling capacitors, 3) the bottom termi- nal of the sense resistor, 4) the negative terminal of the input capacitor and 5) at least one via to the ground plane immediately adjacent to pin 6. the ground trace on the top layer of the pc board should be as wide and short as possible to minimize series resistance and inductance. 2. beware of ground loops in multiple layer pc boards. try to maintain one central ground node on the board and use the input capacitor to avoid excess input ripple for high output current power supplies. if the ground plane is to be used for high dc currents, choose a path away from the small-signal components. 3. place the c vcc capacitor immediately adjacent to the intv cc and gnd pins on the ic package. this capacitor carries high di/dt mosfet gate drive currents. a low esr and esl 4.7 f ceramic capacitor works well here. 4. the high di/dt loop from the bottom terminal of the output capacitor, through the power mosfet, through the boost diode and back through the output capacitors should be kept as tight as possible to reduce inductive ringing. excess inductance can cause increased stress on the power mosfet and increase hf noise on the output. if low esr ceramic capacitors are used on the output to reduce output noise, place these capacitors close to the boost diode in order to keep the series inductance to a minimum. 5. check the stress on the power mosfet by measuring its drain-to-source voltage directly across the device ter- minals (reference the ground of a single scope probe directly to the source pad on the pc board). beware of inductive ringing which can exceed the maximum speci- fied voltage rating of the mosfet. if this ringing cannot be avoided and exceeds the maximum rating of the device, either choose a higher voltage device or specify an ava- lanche-rated power mosfet. not all mosfets are created equal (some are more equal than others). 6. place the small-signal components away from high frequency switching nodes. in the layout shown in fig- ure 18, all of the small-signal components have been placed on one side of the ic and all of the power compo- nents have been placed on the other. this also allows the use of a pseudo-kelvin connection for the signal ground, where high di/dt gate driver currents flow out of the ic ground pin in one direction (to the bottom plate of the intv cc decoupling capacitor) and small-signal currents flow in the other direction. v out 1v/div i l 1a/div mosfet drain voltage 20v/div 1 s/div 18717 f16 v in = 28v i out = 0.5a v out = 42v d = 27% applicatio s i for atio wu uu figure 16. switching waveforms for the converter in figure 9 at maximum v in (28v) i load (ma) 80 efficiency (%) 85 90 95 100 0.001 0.1 1 10 18717 f17 75 0.01 v in = 8v v in = 12v v in = 28v figure 17. efficiency vs load current and input voltage for the converter in figure 9
23 ltc1871-7 18717fb 7. minimize the capacitance between the sense pin trace and any high frequency switching nodes. the ltc1871-7 contains an internal leading edge blanking time of ap- proximately 180ns, which should be adequate for most applications. 8. for optimum load regulation and true remote sensing, the top of the output resistor divider should connect independently to the top of the output capacitor (kelvin connection), staying away from any high dv/dt traces. place the divider resistors near the ltc1871-7 in order to keep the high impedance fb node short. ltc1871-7 m1 v in 1871 f18 v out switch node is also the heat spreader for l1, m1, d1 l1 r t r s r c c c r3 j1 c in c out c vcc r1 r2 pseudo-kelvin signal ground connection true remote output sensing vias to ground plane r4 pin 1 c out jumper d1 applicatio s i for atio wu uu run i th fb freq mode/ sync sense v in intv cc gate gnd ltc1871-7 + r4 j1 10 9 8 7 6 1 2 3 4 5 c vcc pseudo-kelvin ground connection c in m1 d1 l1 v in gnd 18717 f19 v out switch node c out r c r s r1 r t bold lines indicate high current paths r2 c c r3 + figure 18. ltc1871-7 boost converter suggested layout figure 19. ltc1871-7 boost converter layout diagram
24 ltc1871-7 18717fb 9. for applications with multiple switching power convert- ers connected to the same input supply, make sure that the input filter capacitor for the ltc1871-7 is not shared with other converters. ac input current from another converter could cause substantial input voltage ripple, and this could interfere with the operation of the ltc1871-7. a few inches of pc trace or wire (l 100nh) between the c in of the ltc1871-7 and the actual source v in should be sufficient to prevent current sharing problems. sepic converter applications the ltc1871-7 is also well suited to sepic (single-ended primary inductance converter) converter applications. the sepic converter shown in figure 20 uses two inductors. the advantage of the sepic converter is the input voltage may be higher or lower than the output voltage, and the output is short-circuit protected. the first inductor, l1, together with the main switch, resembles a boost converter. the second inductor, l2, together with the output diode d1, resembles a flyback or buck-boost converter. the two inductors l1 and l2 can be independent but can also be wound on the same core since identical voltages are applied to l1 and l2 throughout the switching cycle. by making l1 = l2 and winding them on the same core the input ripple is reduced along with cost applicatio s i for atio wu uu + + + ? ? ? ? sw l2 c out r l v out v in c1 d1 l1 20a. sepic topology + + + ? r l v out 18717 f20 v in d1 20c. current flow during switch off-time + + + ? r l v out v in v in v in 20b. current flow during switch on-time figure 20. sepic topolgy and current flow 21a. input inductor current i in i l1 sw on sw off 21b. output inductor current i o i l2 21c. dc coupling capacitor current i o i in i c1 21e. output ripple voltage v out (ac) ? v esr ringing due to total inductance (board + cap) ? v cout 21d. diode current i o 18717 f21 i d1 figure 21. sepic converter switching waveforms and size. all of the sepic applications information that follows assumes l1 = l2 = l. sepic converter: duty cycle considerations for a sepic converter operating in a continuous conduc- tion mode (ccm), the duty cycle of the main switch is: d vv vvv od in o d = + ++ ? ? ? ? ? ? where v d is the forward voltage of the diode. for convert- ers where the input voltage is close to the output voltage the duty cycle is near 50%.
25 ltc1871-7 18717fb the maximum output voltage for a sepic converter is: vvv d d v d o max in d max max d max () C C C =+ () 1 1 1 the maximum duty cycle of the ltc1871-7 is typically 92%. sepic converter: the peak and average input currents the control circuit in the ltc1871-7 is measuring the input current (using a sense resistor in the mosfet source), so the output current needs to be reflected back to the input in order to dimension the power mosfet properly. based on the fact that, ideally, the output power is equal to the input power, the maximum input current for a sepic converter is: ii d d the peak input current is ii d d in max o max max max in peak o max max max () () () () ? C : ?? C = =+ ? ? ? ? ? ? 1 1 21 the maximum duty cycle, d max , should be calculated at minimum v in . the constant represents the fraction of ripple current in the inductor relative to its maximum value. for example, if 30% ripple current is chosen, then = 0.30 and the peak current is 15% greater than the average. it is worth noting here that sepic converters that operate at high duty cycles (i.e., that develop a high output voltage from a low input voltage) can have very high input currents, relative to the output current. be sure to check that the maximum load current will not overload the input supply. sepic converter: inductor selection for most sepic applications the equal inductor values will fall in the range of 10 h to 100 h. higher values will reduce the input ripple voltage and reduce the core loss. lower inductor values are chosen to reduce physical size and improve transient response. like the boost converter, the input current of the sepic converter is calculated at full load current and minimum input voltage. the peak inductor current can be signifi- cantly higher than the output current, especially with smaller inductors and lighter loads. the following formu- las assume ccm operation and calculate the maximum peak inductor currents at minimum v in : ii vv v ii vv v l peak o max od in min l peak o max in min d in min 1 2 1 2 1 2 () () () () () () () ?? ?? =+ ? ? ? ? ? ? + =+ ? ? ? ? ? ? + the ripple current in the inductor is typically 20% to 40% (i.e., a range of from 0.20 to 0.40) of the maximum average input current occurring at v in(min) and i o(max) and ? i l1 = ? i l2 . expressing this ripple current as a function of the output current results in the following equations for calculating the inductor value: l v if d where ii d d in min l max lomax max max = ? ? = () () ? ? ?? C 1 by making l1 = l2 and winding them on the same core, the value of inductance in the equation above is replace by 2l due to mutual inductance. doing this maintains the same ripple current and energy storage in the inductors. for example, a coiltronix ctx10-4 is a 10 h inductor with two windings. with the windings in parallel, 10 h inductance is obtained with a current rating of 4a (the number of turns hasnt changed, but the wire diameter has doubled). splitting the two windings creates two 10 h inductors with a current rating of 2a each. therefore, substituting 2l yields the following equation for coupled inductors: ll v if d in min l max 12 2 == ? () ?? ? specify the maximum inductor current to safely handle i l(pk) specified in the equation above. the saturation applicatio s i for atio wu uu
26 ltc1871-7 18717fb current rating for the inductor should be checked at the minimum input voltage (which results in the highest inductor current) and maximum output current. sepic converter: power mosfet selection important parameters for the power mosfet include the drain-to-source breakdown voltage (bv dss ), the thresh- old voltage (v gs(th) ), the on-resistance (r ds(on) ) versus gate-to-source voltage, the gate-to-source and gate-to- drain charges (q gs and q gd , respectively), the maximum drain current (i d(max) ) and the mosfets thermal resis- tances (r th(jc) and r th(ja) ). the gate drive voltage is set by the 7v intv cc low dropout regulator. consequently, 6v rated threshold mosfets are required in most ltc1871-7 applications. the maximum voltage that the mosfet switch must sustain during the off-time in a sepic converter is equal to the sum of the input and output voltages (v o + v in ). as a result, careful attention must be paid to the bv dss speci- fications for the mosfets relative to the maximum actual switch voltage in the application. many logic-level devices are limited to 30v or less. check the switching waveforms directly across the drain and source terminals of the power mosfet to ensure the v ds remains below the maximum rating for the device. sense resistor selection during the mosfets on-time, the control circuit limits the maximum voltage drop across the power mosfet to about 150mv (at low duty cycle). the peak inductor current is therefore limited to 150mv/r sense . the rela- tionship between the maximum load current, duty cycle and the sense resistor is: r v i vv v sense sense max omax od in min + ? ? ? ? ? ? + ? ? ? ? ? ? + () () () ?? 1 1 2 1 1 the v sense(max) term is typically 150mv at low duty cycle and is reduced to about 100mv at a duty cycle of 92% due to slope compensation, as shown in figure 11. the constant in the denominator represents the ripple current in the inductors relative to their maximum cur- rent. for example, if 30% ripple current is chosen, then = 0.30. calculating power mosfet switching and conduction losses and junction temperatures in order to calculate the junction temperature of the power mosfet, the power dissipated by the device must be known. this power dissipation is a function of the duty cycle, the load current and the junction temperature itself. as a result, some iterative calculation is normally required to determine a reasonably accurate value. since the con- troller is using the mosfet as both a switching and a sensing element, care should be taken to ensure that the converter is capable of delivering the required load current over all operating conditions (load, line and temperature) and for the worst-case specifications for v sense(max) and the r ds(on) of the mosfet listed in the manufacturers data sheet. the power dissipated by the mosfet in a sepic converter is: pi d d rd kv v i d d cf fet o max ds on t in o o max rss = ? ? ? ? ? ? ++ () () () () ? C ??? ??? C ?? 1 1 2 2 the first term in the equation above represents the i 2 r losses in the device and the second term, the switching losses. the constant k = 1.7 is an empirical factor inversely related to the gate drive current and has the dimension of 1/current. the t term accounts for the temperature coefficient of the r ds(on) of the mosfet, which is typically 0.4%/ c. figure 12 illustrates the variation of normalized r ds(on) over temperature for a typical power mosfet. applicatio s i for atio wu uu
27 ltc1871-7 18717fb from a known power dissipated in the power mosfet, its junction temperature can be obtained using the following formula: t j = t a + p fet ?r th(ja) the r th(ja) to be used in this equation normally includes the r th(jc) for the device plus the thermal resistance from the board to the ambient temperature in the enclosure. this value of t j can then be used to check the original assumption for the junction temperature in the iterative calculation process. sepic converter: output diode selection to maximize efficiency, a fast-switching diode with low forward drop and low reverse leakage is desired. the output diode in a sepic converter conducts current during the switch off-time. the peak reverse voltage that the diode must withstand is equal to v in(max) + v o . the average forward current in normal operation is equal to the output current, and the peak current is equal to: ii vv v d peak o max od in min () () () ?? =+ ? ? ? ? ? ? + + ? ? ? ? ? ? 1 2 1 the power dissipated by the diode is: p d = i o(max) ? v d and the diode junction temperature is: t j = t a + p d ? r th(ja) the r th(ja) to be used in this equation normally includes the r th(jc) for the device plus the thermal resistance from the board to the ambient temperature in the enclosure. sepic converter: output capacitor selection because of the improved performance of todays electro- lytic, tantalum and ceramic capacitors, engineers need to consider the contributions of esr (equivalent series resis- tance), esl (equivalent series inductance) and the bulk capacitance when choosing the correct component for a given output ripple voltage. the effects of these three parameters (esr, esl, and bulk c) on the output voltage ripple waveform are illustrated in figure 21 for a typical coupled-inductor sepic converter. the choice of component(s) begins with the maximum acceptable ripple voltage (expressed as a percentage of the output voltage), and how this ripple should be divided between the esr step and the charging/discharging ? v. for the purpose of simplicity we will choose 2% for the maximum output ripple, to be divided equally between the esr step and the charging/discharging ? v. this percent- age ripple will change, depending on the requirements of the application, and the equations provided below can easily be modified. for a 1% contribution to the total ripple voltage, the esr of the output capacitor can be determined using the following equation: esr v i cout o d peak 001 .? () where: ii vv v d peak o max od in min () () () ?? =+ ? ? ? ? ? ? + + ? ? ? ? ? ? 1 2 1 for the bulk c component, which also contributes 1% to the total ripple: c i vf out o max o () .? ? 001 for many designs it is possible to choose a single capaci- tor type that satisfies both the esr and bulk c require- ments for the design. in certain demanding applications, however, the ripple voltage can be improved significantly by connecting two or more types of capacitors in parallel. for example, using a low esr ceramic capacitor can minimize the esr step, while an electrolytic or tantalum capacitor can be used to supply the required bulk c. once the output capacitor esr and bulk capacitance have been determined, the overall ripple voltage waveform applicatio s i for atio wu uu
28 ltc1871-7 18717fb should be verified on a dedicated pc board (see board layout section for more information on component place- ment). lab breadboards generally suffer from excessive series inductance (due to inter-component wiring), and these parasitics can make the switching waveforms look significantly worse than they would be on a properly designed pc board. the output capacitor in a sepic regulator experiences high rms ripple currents, as shown in figure 21. the rms output capacitor ripple current is: ii v v rms cout o max o in min ()() () ? = note that the ripple current ratings from capacitor manu- facturers are often based on only 2000 hours of life. this makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. several capacitors may also be placed in parallel to meet size or height requirements in the design. in surface mount applications, multiple capacitors may have to be placed in parallel in order to meet the esr or rms current handling requirements of the application. aluminum electrolytic and dry tantalum capacitors are both available in surface mount packages. in the case of tantalum, it is critical that the capacitors have been surge tested for use in switching power supplies. also, ceramic capacitors are now available with extremely low esr, esl and high ripple current ratings. sepic converter: input capacitor selection the input capacitor of a sepic converter is less critical than the output capacitor due to the fact that an inductor is in series with the input and the input current waveform is triangular in shape. the input voltage source impedance determines the size of the input capacitor which is typically in the range of 10 f to 100 f. a low esr capacitor is recommended, although it is not as critical as for the output capacitor. the rms input capacitor ripple current for a sepic con- verter is: ii rms cin l () ? = ? 1 12 please note that the input capacitor can see a very high surge current when a battery is suddenly connected to the input of the converter and solid tantalum capacitors can fail catastrophically under these conditions. be sure to specify surge-tested capacitors! sepic converter: selecting the dc coupling capacitor the coupling capacitor c1 in figure 20 sees nearly a rectangular current waveform as shown in figure 21. during the switch off-time the current through c1 is i o (v o / v in ) while approximately Ci o flows during the on-time. this current waveform creates a triangular ripple voltage on c1: ? = ++ ? v i cf v vvv cpp o max o in o d 1 1 () () ? ? the maximum voltage on c1 is then: vv v c max in cpp 1 1 2 () () =+ ? ? which is typically close to v in(max) . the ripple current through c1 is: ii vv v rms c o max od in min () ( ) () ? 1 = + the value chosen for the dc coupling capacitor normally starts with the minimum value that will satisfy 1) the rms current requirement and 2) the peak voltage requirement (typically close to v in ). low esr ceramic and tantalum capacitors work well here. applicatio s i for atio wu uu
29 ltc1871-7 18717fb typical applicatio s u 9 7 10 8 6 1 2 4 5 3 100k 100k v in 36v to 72v 10v 26.7k 82.5k 12.4k r2* 21k *r2 = 38.3k for v out = 5v r1 604k 1nf 0.1 f 2.2 f 100v 100 f 6.3v 3 v out 3.3v 3a max t1b ups840 ctx-002-15242 t1a ? ? q1 fdc2512 all capacitors are ceramic x5r type r3 0.1 ? 4.7 f 18717 ta02a run i th freq mode/sync v fb v in gate sense intv cc gnd ltc1871-7 mmbta42 a 48v input flyback converter configurable to 3.3v or 5v outputs i load (a) 0 60 efficiency (%) 65 70 75 80 90 1 234 18717 ta02b 56 85 36v in 48v in 72v in output efficiency at 3.3v output i load (a) 0 60 efficiency (%) 65 70 75 80 90 1 234 18717 ta02c 5 85 36v in 48v in 72v in output efficiency at 5v output
30 ltc1871-7 18717fb run i th fb freq mode/sync 10 9 8 7 6 1 2 3 4 5 sense v in intv cc gate gnd ltc1871-7 d4 33v d5 33v d6 5v 18717 ta01 r7 4.7m r6 1m 1% v in gnd run input 0v to 5v dimming input c5 47 f 20v 2 r8 187k 1% c8 100nf r10 300k r15 0.20 ? 0.5w r13 17.8k c9 4.7 f x5r c5: sanyo os-con 20sp47m c7: itw paktron 106k100cs4 l1: magnetics inc 58206-a2 with 29t 18awg c10 4.7 f r14 1k r12 4.02k r11 0.006 ? r9 1k q3 siliconix sup75n08-9l c7 10 f 100v to leds from leds use 68v or 75v single zener d3 irf12cw10 l1 + 1.2a automotive led headlamp boost converter typical applicatio s u run i th fb freq mode/sync sense v in intv cc gate gnd 1 2 3 4 5 10 9 8 7 6 ltc1871-7 r7 33k r4 75 ? r5 150k r13 0.082 ? r10 64.9k 18717 ta03 c3, c11: tdk c3225x5r0j107m c4: sanyo poscap 10 tpb33m c7: tdk c4532x7r1h335m c13, c13a: sanyo poscap 4tpb470m l1: coilcraft do1608 103 t1: coiltronics vp4-0047 c13 470 f r8 20.5k r3 43.2k r2 12.5k 5.5v 500ma 3.3v 2a r14 1k iso1 moc207 r12 80k r11 12.5k r1 33k q1 si4482dy c15 4.7 f c13a 470 f c11 100 f c8 100pf 200v c12 15nf c10 330nf r9 33k c16 10nf 1kv c3 100 f c4 33 f 123 tab 45 c17 1 f c14 1nf d4 bat54 9 5 8 6 7 t1 vp4-0047 d1 1a 40v d3 ups840 r6 1 ? c9 1nf 4 10 3 11 2 12 1 c6 1 f 35v v in 18v to 33v sync signal 320khz 0v to 2.5v c5 22 f 50v c7 3.3 f 50v d2 10v l1 10 h col comp v + r top ref r mid gndf gnds 1 2 3 4 8 7 6 5 lt1431 shdn in gnd gnd lt1963 out adj + + + dual output cell phone base station flyback converter
31 ltc1871-7 18717fb typical applicatio s u run i th fb freq mode/sync sense intv cc gate 1 2 3 4 5 10 8 7 ltc1871-7 v in 9 q6 fmmt451 t1 vp5-0155 6 gnd r47 133k 1% r59 0.005 ? 1w 1% q9 si4486ey so-8 r61 12.4k 1% r60 124k 1% cr22 1n4148 cr21 mbr10100 c47 6800pf c49 4.7 f c50 4 f x7r c46 100pf v batt 8v to 25v r45 33.2k r43 13.3k 1% r37 75k 1% r46 47k cr4 bzx84c15v 112 4 ? ? 9 211 5 ? ? 8 310 6 ? ? 7 + c51 150 f 35v 18717 ta04 c52 4.7 f x7r 2 c53 22 f 16v x5r 2 c57 10 f x5r (optional hf filter) c55 4.7 f 16v x7r 2 v out 13.5v 3a l7 150 ? 3a bead 1b (optional hf filter) + automotive sepic converter msop (ms) 0603 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 C 0.27 (.007 C .011) typ 0.127 0.076 (.005 .003) 0.86 (.034) ref 0.50 (.0197) bsc 12 3 45 4.90 0.152 (.193 .006) 0.497 0.076 (.0196 .003) ref 8 9 10 7 6 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) (note 4) note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0 C 6 typ detail a detail a gauge plane 5.23 (.206) min 3.20 C 3.45 (.126 C .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.305 0.038 (.0120 .0015) typ 0.50 (.0197) bsc u package descriptio ms package 10-lead plastic msop (reference ltc dwg # 05-08-1661) information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
32 ltc1871-7 18717fb ? linear technology corporation 2002 lt/tp 1005 1k rev b ?printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com related parts part number description comments lt ? 1619 current mode pwm controller 300khz fixed frequency, boost, sepic, flyback topology ltc1624 current mode dc/dc controller so-8; 300khz operating frequency; buck, boost, sepic design; v in up to 36v ltc1700 no r sense synchronous step-up controller up to 95% efficiency, operation as low as 0.9v input ltc1871 wide input range, no r sense controller operation as low as 2.5v input, boost flyback,sepic ltc1872 sot-23 boost controller delivers up to 5a, 550khz fixed frequency, current mode lt1930 1.2mhz, sot-23 boost converter up to 34v output, 2.6v v in 16v, miniature design lt1931 inverting 1.2mhz, sot-23 converter positive-to-negative dc/dc conversion, miniature design ltc3401/ltc3402 1a/2a 3mhz synchronous boost converters up to 97% efficiency, very small solution, 0.5v v in 5v ltc3803 sot-23 flyback controller adjustable slope compensation, internal soft-start, current mode 200khz operation ltc3806 synchronous flyback controller high efficiency, improves cross regulation in multiple output designs, current mode, 3mm 4mm 12-pin dfn package a small, nonisolated 12v flyback telecom housekeeping supply typical applicatio s u run i th fb freq mode/sync sense v in intv cc gate gnd ltc1871-7 r t 120k f = 200khz t1: coiltronics vp1-0076 m1: fairchild fdc2512 (150v, 0.5 ? ) q1: zetex fmmt625 (120v) c2 4.7 f x5r c in 2.2 f 100v x7r m1 r s 0.12 ? t1 1, 2, 3 (series) v in 36v to 72v 4, 5, 6 (parallel) r c 3.4k c c1 2.2nf c c2 47pf c1 1nf optional r2 26.7k 1% d3 c out 47 f x5r v out 12v 0.4a r1 604k 1% r3 12.4k 1% r5 100k r6 10 ? q1 d2 d1 9.1v uv + = 31.8v uv C = 29.5v d1: on semiconductor mmbz5239blt1 (9.1v) d2: on semiconductor mmsd4148t11 d3: international rectifier 10bq060 r4 110k 1% c3 0.1 f x5r 18717 ta05 ? ?

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