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rev.2.00 jan 30, 2006 page 1 of 35 rej03b0101-0200 1. overview this mcu is built using the high-p erformance silicon gate cmos proces s using the r8c/tiny series cpu core and is packaged in a 20-pin plastic mol ded lssop. this mcu operates using sophisticated instructions featuring a high level of instruction efficiency. with 1 mbyte of address space, it is capable of executing instructions at high speed. furthermore, the data flash rom (1kb 2bl ocks) is embedded in the r8c/17 group. the difference between the r8c/16 and r8c/17 groups is only the existence of th e data flash rom. their peripheral functions are the same. 1.1 applications electric household appliance, office equipment, housin g equipment (sensor, security), general industrial equipment, audio, etc. rej03b0101-0200 rev.2.00 jan 30, 2006 r8c/16 group, r8c/17 group single-chip 16-bit cmos microcomputer
r8c/16 group, r8c/17 group 1. overview rev.2.00 jan 30, 2006 page 2 of 35 rej03b0101-0200 1.2 performance overview table 1.1 lists the performance outline of the r8c/16 group and table 1.2 lists the performance outline of the r8c/17 group. notes: 1. i 2 c bus is a trademark of koninklijke philips electronics n. v. table 1.1 performance outline of the r8c/16 group item performance cpu number of basic instructions 89 instructions minimum instruction execution time 50ns(f(xin)=20mhz, vcc=3.0 to 5.5v) 100ns(f(xin)=10mhz, vcc=2.7 to 5.5v) operating mode single-chip address space 1 mbyte memory capacity see table 1.3 r8c/16 group product information peripheral function port i/o port : 13 pins (including led drive port), input : 2 pins led drive port i/o port: 4 pins timer timer x: 8 bits 1 channel, timer z: 8 bits 1 channel (each timer equipped with 8-bit prescaler) timer c: 16 bits 1 channel (circuits of input capture and output compare) serial interface 1 channel clock synchronous serial i/o, uart i 2 c bus interface (iic) (1) 1 channel a/d converter 10-bit a/d converter: 1 circuit, 4 channels watchdog timer 15 bits 1 channel (with prescaler) reset start selectable, count source protection mode interrupt internal: 9 factors, external: 4 factors, software: 4 factors priority level: 7 levels clock generation circuit 2 circuits main clock oscillation circui t (equipped with a built-in feedback resistor) on-chip oscillator (high speed, low speed) equipped with frequency adjustment function on high- speed on-chip oscillator oscillation stop detection function main clock oscillation stop detection function voltage detection circuit included power-on reset circuit included electric characteristics supply voltage vcc=3.0 to 5.5v (f(xin)=20mhz) vcc=2.7 to 5.5v (f(xin)=10mhz) power consumption typ. 9ma (vcc=5.0v, f(xin)=20mhz) typ. 5ma (vcc=3.0v, f(xin)=10mhz) typ. 35 a (vcc=3.0v, wait mode, peripheral clock off) typ. 0.7 a (vcc=3.0v, stop mode) flash memory program/erase supply voltage vcc=2.7 to 5.5v program/erase endurance 100 times operating ambient temperature -20 to 85 c -40 to 85 c (d version) package 20-pin plastic mold lssop
r8c/16 group, r8c/17 group 1. overview rev.2.00 jan 30, 2006 page 3 of 35 rej03b0101-0200 notes: 1. i 2 c bus is a trademark of koninklijke philips electronics n. v. table 1.2 performance outline of the r8c/17 group item performance cpu number of basic inst ructions 89 instructions minimum instruction execution time 50ns(f(xin)=20mhz, vcc=3.0 to 5.5v) 100ns(f(xin)=10mhz, vcc=2.7 to 5.5v) operating mode single-chip address space 1 mbyte memory capacity see table 1.4 r8c/17 group product information peripheral function port i/o : 13 pins (including led drive port), input : 2 pin led drive port i/o port: 4 pins timer timer x: 8 bits 1 channel, timer z: 8 bits 1 channel (each timer equipped with 8-bit prescaler) timer c: 16 bits 1 channel (circuits of input capture and output compare) serial interface 1 channel clock synchronous serial i/o, uart i 2 c bus interface (iic) (1) 1 channel a/d converter 10-bit a/d converter: 1 circuit, 4 channels watchdog timer 15 bits 1 channel (with prescaler) reset start selectable, count source protection mode interrupt internal: 9 factors, external: 4 factors, software: 4 factors priority level: 7 levels clock generation circuit 2 circuits main clock generation circuit (equipped with a built-in feedback resistor) on-chip oscillator (high speed, low speed) equipped with frequency adjustment function on high- speed on-chip oscillator oscillation stop detection function main clock oscillation stop detection function voltage detection circuit included power-on reset circuit included electric characteristics supply voltage vcc=3.0 to 5.5v (f(xin)=20mhz) vcc=2.7 to 5.5v (f(xin)=10mhz) power consumption typ. 9ma (vcc = 5.0v, f(xin) = 20mhz) typ. 5ma (vcc = 3.0v, f(xin) = 10mhz) typ.35 a (vcc = 3.0v, wait mode, peripheral clock off) typ. 0.7 a (vcc = 3.0v, stop mode) flash memory program/erase supply voltage vcc=2.7 to 5.5v program and erase endurance 10,000 times (data flash) 1,000 times (program rom) operating ambient temperature -20 to 85 c -40 to 85 c (d version) package 20-pin plastic mold lssop
r8c/16 group, r8c/17 group 1. overview rev.2.00 jan 30, 2006 page 4 of 35 rej03b0101-0200 1.3 block diagram figure 1.1 shows a block diagram. figure 1.1 block diagram r8c/tiny series cpu core 8 4 1 2 timer timer x (8 bits) timer z (8 bits) timer c (16 bits) a/d converter (10 bits 4 channels) system clock generator xin-xout high-speed on-chip oscillator low-speed on-chip oscillator uart or clock synchronous serial i/o (8 bits 1 channel) memory watchdog timer (15 bits) rom (1) ram (2) multiplier r0h r0l r1h r2 r3 r1l a0 a1 fb sb usp isp intb pc flg i/o port port p1 port p3 port p4 notes: 1. rom size depends on mcu type. 2. ram size depends on mcu type. i 2 c bus interface peripheral function
r8c/16 group, r8c/17 group 1. overview rev.2.00 jan 30, 2006 page 5 of 35 rej03b0101-0200 1.4 product information table 1.3 lists the product information of r8c/16 group and table 1.4 lists the product information of r8c/17 group. figure 1.2 part number, memory size and package of r8c/16 group table 1.3 product information of r8c/16 group as of jan 2006 type no. rom capacity ram capacity package type remarks r5f21162sp 8 kbytes 512 bytes plsp0020jb-a flash memory version r5f21163sp 12 kbytes 768 bytes plsp0020jb-a r5f21164sp 16 kbytes 1 kbyte plsp0020jb-a r5f21162dsp 8 kbytes 512 bytes plsp0020jb-a d version r5f21163dsp 12 kbytes 768 bytes plsp0020jb-a r5f21164dsp 16 kbytes 1 kbyte plsp0020jb-a type no. r 5 f 21 16 4 d sp package type: sp : plsp0020jb-a grouping d : operation ambient temperature -40c to 85c no symbol : operation ambient temperature -20c to 85c rom capacity 2 : 8kb 3 : 12kb 4 : 16kb r8c/16 group r8c/tiny series memory type f : flash memory version renesas mcu renesas semiconductors
r8c/16 group, r8c/17 group 1. overview rev.2.00 jan 30, 2006 page 6 of 35 rej03b0101-0200 figure 1.3 part number, memory size and package of r8c/17 group table 1.4 product information of r8c/17 group as of jan 2006 type no. rom capacity ram capacity package type remarks program rom data flash r5f21172sp 8 kbytes 1 kbyte 2 512 bytes plsp0020jb-a flash memory version r5f21173sp 12 kbytes 1 kbyte 2 768 bytes plsp0020jb-a r5f21174sp 16 kbytes 1 kbyte 2 1 kbyte plsp0020jb-a r5f21172dsp 8 kbytes 1 kbyte 2 512 bytes plsp0020jb-a d version r5f21173dsp 12 kbytes 1 kbyte 2 768 bytes plsp0020jb-a R5F21174DSP 16 kbytes 1 kbyte 2 1 kbyte plsp0020jb-a type no. r 5 f 21 17 4 d sp package type: sp : plsp0020jb-a grouping d : operation ambient temperature -40c to 85c no symbol : operating ambient temperature -20 c to 85c rom capacity 2 : 8kb 3 : 12kb 4 : 16kb r8c/17 group r8c/tiny series memory type f : flash memory version renesas mcu renesas semiconductors
r8c/16 group, r8c/17 group 1. overview rev.2.00 jan 30, 2006 page 7 of 35 rej03b0101-0200 1.5 pin assignments figure 1.4 shows the plsp0020jb-a package pin assignment (top view). figure 1.4 plsp0020jb-a package pin assignment (top view) 1 2 3 4 5 6 7 8 9 10 20 p3_4/sda/cmp1_1 19 p3_3/tcin/int3/cmp1_0 18 p1_0/ki0/an8/cmp0_0 17 p1_1/ki1/an9/cmp0_1 16 avcc/vref 15 p1_2/ki2/an10/cmp0_2 14 p1_3/ki3/an11/tzout 13 p1_4/txd0 12 p1_5/rxd0/cntr01/int11 11 p1_6/clk0 p3_5/scl/cmp1_2 p3_7/cntr0 reset xout/p4_7 (1) vss/avss xin/p4_6 vcc mode p4_5/int0 p1_7/cntr00/int10 pin assignment (top view) package: plsp0020jb-a(20p2f-a) r8c/16 group r8c/17 group notes: 1. p4_7 is a port for the input.
r8c/16 group, r8c/17 group 1. overview rev.2.00 jan 30, 2006 page 8 of 35 rej03b0101-0200 1.6 pin description table 1.5 lists the pin description and table 1.6 lists the pin name information by pin number. i: input o: output i/ o: input and output table 1.5 pin description function pin name i/o type description power supply input vcc vss i apply 2.7v to 5.5v to the vcc pin. apply 0v to the vss pin analog power supply input avcc avss i power supply input pins to a/d converter. connect avcc to vcc. apply 0v to avss. connect a capacitor between avcc and avss. reset input reset i input ?l? on this pin resets the mcu mode mode i connect this pin to vcc via a resistor main clock input xin i these pins are provided for the main clock generation circuit i/o. connect a ceramic resonator or a crystal os cillator between the xin and xout pins. to use an externally derived clock, input it to the xin pin and leave the xout pin open. main clock output xout o int interrupt int0 , int1 , int3 i int interrupt input pins key input interrupt ki0 to ki3 i key input interrupt input pins timer x cntr0 i/o timer x i/o pin cntr0 o timer x output pin timer z tzout o timer z output pin timer c tcin i timer c input pin cmp0_0 to cmp0_2, cmp1_0 to cmp1_2 o timer c output pins serial interface clk0 i/o transfer clock i/o pin rxd0 i serial data input pin txd0 o serial data output pin i 2 c bus interface (iic) scl i/o clock i/o pin sda i/o data i/o pin reference voltage input vref i reference voltage input pin to a/d converter connect vref to vcc a/d converter an8 to an11 i analog input pins to a/d converter i/o port p1_0 to p1_7, p3_3 to p3_5, p3_7, p4_5 i/o these are cmos i/o ports. each port contains an i/o select direction register, allowing each pin in that port to be directed for input or output individually. any port set to input can select whether to use a pull-up resistor or not by program. p1_0 to p1_3 also function as led drive ports. input port p4_6, p4_7 i port for input-only
r8c/16 group, r8c/17 group 1. overview rev.2.00 jan 30, 2006 page 9 of 35 rej03b0101-0200 table 1.6 pin name information by pin number pin number control pin port i/o pin of peripheral functions interrupt timer serial interface i 2 c bus interface a/d converter 1 p3_5 cmp1_2 scl 2p3_7 cntr0 3 reset 4xoutp4_7 5 vss/avss 6xinp4_6 7vcc 8mode 9p4_5 int0 10 p1_7 int10 cntr00 11 p1_6 clk0 12 p1_5 int11 cntr01 rxd0 13 p1_4 txd0 14 p1_3 ki3 tzout an11 15 p1_2 ki2 cmp0_2 an10 16 avcc/vref 17 p1_1 ki1 cmp0_1 an9 18 p1_0 ki0 cmp0_0 an8 19 p3_3 int3 tcin/cmp1_0 20 p3_4 cmp1_1 sda
r8c/16 group, r8c/17 group 2. ce ntral processing unit (cpu) rev.2.00 jan 30, 2006 page 10 of 35 rej03b0101-0200 2. central processi ng unit (cpu) figure 2.1 shows the cpu register. the cpu contains 13 registers. of these, r0, r1, r2, r3, a0, a1 and fb comprise a register bank. two sets of register banks are provided. figure 2.1 cpu register r2 b31 b15 b8b7 b0 data register (1) address register (1) r3 r0h (high-order of r0) r2 r3 a0 a1 intbh b15 b19 b0 intbl fb frame bass register (1) the 4-high order bits of intb are intbh and the 16-low bits of intb are intbl. interrupt table register b19 b0 usp program counter isp sb user stack pointer interrupt stack pointer static base register pc flg flag register carry flag debug flag zero flag sign flag register bank select flag overflow flag interrupt enable flag stack pointer select flag reserved bit processor interrupt priority level reserved bit c ipl d z s b o i u b15 b0 b15 b0 b15 b0 b8 b7 notes: 1. a register bank comprises these register s. two sets of regi ster banks are provided. r0l (low-order of r0) r1h (high-order of r1) r1l (low-order of r1)
r8c/16 group, r8c/17 group 2. ce ntral processing unit (cpu) rev.2.00 jan 30, 2006 page 11 of 35 rej03b0101-0200 2.1 data registers (r 0, r1, r2 and r3) r0 is a 16-bit register for transfer, arithmetic and logic operations. the same applies to r1 to r3. the r0 can be split into high-order bit (r0h) and low-order bit (r0l) to be used separately as 8-bit data registers. the same applies to r1h and r1l as r0 h and r0l. r2 can be combined with r0 to be used as a 32-bit data register (r2r0). the same applies to r3r1 as r2r0. 2.2 address registers (a0 and a1) a0 is a 16-bit register for address register indirect addressing and address register relative addressing. they also are used for transfer, arithmetic and logi c operations. the same app lies to a1 as a0. a0 can be combined with a0 to be used as a 32-bit address register (a1a0). 2.3 frame base register (fb) fb is a 16-bit register for fb relative addressing. 2.4 interrupt table register (intb) intb is a 20-bit register indicates the st art address of an interrupt vector table. 2.5 program counter (pc) pc, 20 bits wide, indicates the address of an instruction to be executed. 2.6 user stack pointer (usp) a nd interrupt stack pointer (isp) the stack pointer (sp), usp and isp, are 16 bits wide each. the u flag of flg is used to switch between usp and isp. 2.7 static base register (sb) sb is a 16-bit register for sb relative addressing. 2.8 flag register (flg) flg is a 11-bit register indicating the cpu state. 2.8.1 carry flag (c) the c flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic logic unit. 2.8.2 debug flag (d) the d flag is for debug only. set to ?0?. 2.8.3 zero flag (z) the z flag is set to ?1? when an arithmetic operation resulted in 0; otherwise, ?0?. 2.8.4 sign flag (s) the s flag is set to ?1? when an arithmetic operat ion resulted in a negativ e value; otherwise, ?0?. 2.8.5 register bank select flag (b) the register bank 0 is selected when the b flag is ?0?. the register bank 1 is selected when this flag is set to ?1?. 2.8.6 overflow flag (o) the o flag is set to ?1? when the operati on resulted in an overflow; otherwise, ?0?.
r8c/16 group, r8c/17 group 2. ce ntral processing unit (cpu) rev.2.00 jan 30, 2006 page 12 of 35 rej03b0101-0200 2.8.7 interrupt enable flag (i) the i flag enables a maskable interrupt. an interrupt is disabled when the i flag is set to ?0?, and are enabled when the i flag is set to ?1?. the i flag is set to ?0? when an interrupt request is acknowledged. 2.8.8 stack pointer select flag (u) isp is selected when the u flag is set to ?0?, usp is selected when the u flag is set to ?1?. the u flag is set to ?0? when a hardware interrupt request is ack nowledged or the int instruction of software interrupt numbers 0 to 31 is executed. 2.8.9 processor interrupt priority level (ipl) ipl, 3 bits wide, assigns processor interrup t priority levels from level 0 to level 7. if a requested interrupt has greater priority than ipl, the interrupt is enabled. 2.8.10 reserved bit when write to this bit, set to ?0?. w hen read, its content is indeterminate.
r8c/16 group, r8c/17 group 3. memory rev.2.00 jan 30, 2006 page 13 of 35 rej03b0101-0200 3. memory 3.1 r8c/16 group figure 3.1 is a memory map of the r8c/16 group. the r8c/16 group provides 1-mbyte address space from addresses 00000h to fffffh. the internal rom is allocated lower addresses beginning with address 0ffffh. for example, a 16- kbyte internal rom is allocated addresses 0c000h to 0ffffh. the fixed interrupt vector table is allocated addresses 0ffdch to 0ffffh. they store the starting address of each interrupt routine. the internal ram is allocated higher addresses beginning with address 00400h. for example, a 1- kbyte internal ram is allocated addresses 00400h to 007ffh. the internal ram is used not only for storing data but for ca lling subroutines and stacks when in terrupt requ est is acknowledged. special function registers (sfr) are allocated add resses 00000h to 002ffh. the peripheral function control registers are allocated them. all addresses, which have nothing allocated within the sfr, are reserved area and cannot be accessed by users. figure 3.1 memory map of r8c/16 group undefined instruction overflow brk instruction address match single step watchdog timer ? oscillation stop detection ? voltage monitor 2 address break (reserved) reset part number internal rom internal ram s i z e 0yyyyh r5f21164sp, r5f21164dsp r5f21163sp, r5f21163dsp r5f21162sp, r5f21162dsp 16 kbytes 12 kbytes 8 kbytes 0c000h 0d000h 0e000h 1 kbyte 768 bytes 512 bytes 007ffh 006ffh 005ffh fffffh 0ffffh 0yyyyh 0xxxxh 00400h 002ffh 00000h internal rom expansion area internal ram sfr (see 4. special function register (sfr) ) 0ffffh 0ffdch s i z e 0xxxxh notes: 1. blank spaces are reserved. no access is allowed.
r8c/16 group, r8c/17 group 3. memory rev.2.00 jan 30, 2006 page 14 of 35 rej03b0101-0200 3.2 r8c/17 group figure 3.2 is a memory map of the r8c/17 group. the r8c/17 group provides 1-mbyte address space from addresses 00000h to fffffh. the internal rom (program rom) is allocated lower addresses beginning with address 0ffffh. for example, a 16-kbyte internal rom is allocated addresses 0c000h to 0ffffh. the fixed interrupt vector table is allocated addresses 0ffdch to 0ffffh. they store the starting address of each interrupt routine. the internal rom (data flash) is allocated addresses 02400h to 02bffh. the internal ram is allocated higher addresses beginning with address 00400h. for example, a 1- kbyte internal ram is allocated addresses 00400h to 007ffh. the internal ram is used not only for storing data but for ca lling subroutines and stacks when in terrupt requ est is acknowledged. special function registers (sfr) are allocated add resses 00000h to 002ffh. the peripheral function control registers are allocated them. all addresses, which have nothing allocated within the sfr, are reserved area and cannot be accessed by users. figure 3.2 memory map of r8c/17 group undefined instruction overflow brk instruction address match single step watchdog timer ? oscillation stop detection ? voltage monitor 2 address break (reserved) reset part number internal rom internal ram s i z e 0yyyyh r5f21174sp, R5F21174DSP r5f21173sp, r5f21173dsp r5f21172sp, r5f21172dsp 16 kbytes 12 kbytes 8 kbytes 0c000h 0d000h 0e000h 1 kbyte 768 bytes 512 bytes 007ffh 006ffh 005ffh fffffh 0ffffh 0yyyyh 0xxxxh 00400h 002ffh 00000h expansion area internal ram 0ffffh 0ffdch s i z e 0xxxxh 02bffh 02400h notes: 1. the data flash block a (1 kbyte) and block b (1 kbyte) are shown. 2. blank spaces are reserved. no access is allowed. internal rom (program rom) internal rom (data flash) (1) sfr (see 4. special function register (sfr) )
r8c/16 group, r8c/17 group 4. sp ecial function register (sfr) rev.2.00 jan 30, 2006 page 15 of 35 rej03b0101-0200 4. special function register (sfr) sfr (special function register) is th e control register of peripheral functi ons. tables 4.1 to 4.4 list the sfr information. table 4.1 sfr information(1) (1) x: undefined notes: 1. blank spaces are reserved. no access is allowed. 2. software reset, the watchdog timer reset or the voltage monitor 2 reset does not affect this register. 3. owing to hardware reset. 4. owing to power-on reset or the voltage monitor 1 reset. 5. software reset, the watchdog timer reset or the voltage monitor 2 reset does not affect the b2 and b3. address register symbol after reset 0000h 0001h 0002h 0003h 0004h processor mode register 0 pm0 00h 0005h processor mode register 1 pm1 00h 0006h system clock control register 0 cm0 01101000b 0007h system clock control register 1 cm1 00100000b 0008h 0009h address match interrupt enable register aier 00h 000ah protect register prcr 00h 000bh 000ch oscillation stop detection register ocd 00000100b 000dh watchdog timer reset register wdtr xxh 000eh watchdog timer start register wdts xxh 000fh watchdog timer control register wdc 00011111b 0010h address match interrupt register 0 rmad0 00h 0011h 00h 0012h x0h 0013h 0014h address match interrupt register 1 rmad1 00h 0015h 00h 0016h x0h 0017h 0018h 0019h 001ah 001bh 001ch count source protection mode register cspr 00h 001dh 001eh int0 input filter select register int0f 00h 001fh 0020h high-speed on-chip oscillator control register 0 hra0 00h 0021h high-speed on-chip oscillator control register 1 hra1 when shipping 0022h high-speed on-chip oscillator control register 2 hra2 00h 0023h 002ah 002bh 002ch 002dh 002eh 002fh 0030h 0031h voltage detection register 1 (2) vca1 00001000b 0032h voltage detection register 2 (2) vca2 00h (3) 01000000b (4) 0033h 0034h 0035h 0036h voltage monitor 1 circuit control register (2) vw1c 0000x000b (3) 0100x001b (4) 0037h voltage monitor 2 circuit control register (5) vw2c 00h 0038h 0039h 003ah 003bh 003ch 003dh 003eh 003fh
r8c/16 group, r8c/17 group 4. sp ecial function register (sfr) rev.2.00 jan 30, 2006 page 16 of 35 rej03b0101-0200 table 4.2 sfr information(2) (1) x: undefined notes: 1. blank spaces are reserved. no access is allowed. address register symbol after reset 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004ah 004bh 004ch 004dh key input interrupt control register kupic xxxxx000b 004eh a/d conversion interrupt control register adic xxxxx000b 004fh iic interrupt control register iic2aic xxxxx000b 0050h compare 1 interrupt control register cmp1ic xxxxx000b 0051h uart0 transmit interrupt control register s0tic xxxxx000b 0052h uart0 receive interrupt control register s0ric xxxxx000b 0053h 0054h 0055h 0056h timer x interrupt control register txic xxxxx000b 0057h 0058h timer z interrupt control register tzic xxxxx000b 0059h int1 interrupt control register int1ic xxxxx000b 005ah int3 interrupt control register int3ic xxxxx000b 005bh timer c interrupt control register tcic xxxxx000b 005ch compare 0 interrupt control register cmp0ic xxxxx000b 005dh int0 interrupt control register int0ic xx00x000b 005eh 005fh 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006ah 006bh 006ch 006dh 006eh 006fh 0070h 0071h 0072h 0073h 0074h 0075h 0076h 0077h 0078h 0079h 007ah 007bh 007ch 007dh 007eh 007fh
r8c/16 group, r8c/17 group 4. sp ecial function register (sfr) rev.2.00 jan 30, 2006 page 17 of 35 rej03b0101-0200 table 4.3 sfr information(3) (1) x: undefined notes: 1. blank spaces are reserved. no access is allowed. 2. when output compare mode (the tcc13 bit in the tcc1 register = 1) is selected, the value after reset is ?ffffh?. address register symbol after reset 0080h timer z mode register tzmr 00h 0081h 0082h 0083h 0084h timer z waveform output control register pum 00h 0085h prescaler z register prez ffh 0086h timer z secondary register tzsc ffh 0087h timer z primary register tzpr ffh 0088h 0089h 008ah timer z output control register tzoc 00h 008bh timer x mode register txmr 00h 008ch prescaler x register prex ffh 008dh timer x register tx ffh 008eh timer count source setting register tcss 00h 008fh 0090h timer c register tc 00h 0091h 00h 0092h 0093h 0094h 0095h 0096h external input enable register inten 00h 0097h 0098h key input enable register kien 00h 0099h 009ah timer c control register 0 tcc0 00h 009bh timer c control register 1 tcc1 00h 009ch capture, compare 0 register tm0 00h 009dh 00h (2) 009eh compare 1 register tm1 ffh 009fh ffh 00a0h uart0 transmit/receive mode register u0mr 00h 00a1h uart0 bit rate register u0brg xxh 00a2h uart0 transmit buffer register u0tb xxh 00a3h xxh 00a4h uart0 transmit/receive control register 0 u0c0 00001000b 00a5h uart0 transmit/receive control register 1 u0c1 00000010b 00a6h uart0 receive buffer register u0rb xxh 00a7h xxh 00a8h 00a9h 00aah 00abh 00ach 00adh 00aeh 00afh 00b0h uart transmit/receive control register 2 ucon 00h 00b1h 00b2h 00b3h 00b4h 00b5h 00b6h 00b7h 00b8h iic bus control register 1 iccr1 00h 00b9h iic bus control register 2 iccr2 7dh 00bah iic bus mode register icmr 18h 00bbh iic bus interrupt enable register icier 00h 00bch iic bus status register icsr 00h 00bdh slave address register sar 00h 00beh iic bus transmit data register icdrt ffh 00bfh iic bus receive data register icdrr ffh
r8c/16 group, r8c/17 group 4. sp ecial function register (sfr) rev.2.00 jan 30, 2006 page 18 of 35 rej03b0101-0200 table 4.4 sfr information(4) (1) x: undefined notes: 1. blank columns, 0100h to 01b2h and 01b8h to 02ffh are all reserved. no access is allowed. 2. the ofs register cannot be changed by program . use a flash programmer to write to it. address register symbol after reset 00c0h a/d register ad xxh 00c1h xxh 00c2h 00c3h 00c4h 00c5h 00c6h 00c7h 00c8h 00c9h 00cah 00cbh 00cch 00cdh 00ceh 00cfh 00d0h 00d1h 00d2h 00d3h 00d4h a/d control register 2 adcon2 00h 00d5h 00d6h a/d control register 0 adcon0 00000xxxb 00d7h a/d control register 1 adcon1 00h 00d8h 00d9h 00dah 00dbh 00dch 00ddh 00deh 00dfh 00e0h 00e1h port p1 register p1 xxh 00e2h 00e3h port p1 direction register pd1 00h 00e4h 00e5h port p3 register p3 xxh 00e6h 00e7h port p3 direction register pd3 00h 00e8h port p4 register p4 xxh 00e9h 00eah port p4 direction register pd4 00h 00ebh 00ech 00edh 00eeh 00efh 00f0h 00f1h 00f2h 00f3h 00f4h 00f5h 00f6h 00f7h 00f8h 00f9h 00fah 00fbh 00fch pull-up control register 0 pur0 00xx0000b 00fdh pull-up control register 1 pur1 xxxxxx0xb 00feh port p1 drive capacity control register drr 00h 00ffh timer c output control register tcout 00h 01b3h flash memory control register 4 fmr4 01000000b 01b4h 01b5h flash memory control register 1 fmr1 1000000xb 01b6h 01b7h flash memory control register 0 fmr0 00000001b 0ffffh optional function select register ofs (2)
r8c/16 group, r8c/17 group 5. electrical characteristics rev.2.00 jan 30, 2006 page 19 of 35 rej03b0101-0200 5. electrical characteristics notes: 1. v cc = av cc = 2.7 to 5.5v at t opr = -20 to 85 c / -40 to 85 c, unless otherwise specified. 2. the typical values when average output current is 100ms. 3. hold v cc = av cc. table 5.1 absolute maximum ratings symbol parameter condition rated value unit v cc supply voltage v cc = av cc -0.3 to 6.5 v av cc analog supply voltage v cc = av cc -0.3 to 6.5 v v i input voltage -0.3 to v cc +0.3 v v o output voltage -0.3 to v cc +0.3 v p d power dissipation t opr = 25 c300mw t opr operating ambient temperature -20 to 85 / -40 to 85 (d version) c t stg storage temperature -65 to 150 c table 5.2 recommended operating conditions symbol parameter conditions standard unit min. typ. max. v cc supply voltage 2.7 ? 5.5 v av cc analog supply voltage ? v cc (3) ? v v ss supply voltage ? 0 ? v av ss analog supply voltage ? 0 ? v v ih input ?h? voltage 0.8v cc ? v cc v v il input ?l? voltage 0 ? 0.2v cc v i oh(sum) peak sum output ?h? current sum of all pins i oh (peak) ?? -60 ma i oh(peak) peak output ?h? current ?? -10 ma i oh(avg) average output ?h? current ?? -5 ma i ol(sum) peak sum output ?l? currents sum of all pins i ol (peak) ?? 60 ma i ol(peak) peak output ?l? currents except p1_0 to p1_3 ?? 10 ma p1_0 to p1_3 drive capacity high ?? 30 ma drive capacity low ?? 10 ma i ol(avg) average output ?l? current except p1_0 to p1_3 ?? 5ma p1_0 to p1_3 drive capacity high ?? 15 ma drive capacity low ?? 5ma f (xin) main clock input oscillation frequency 3.0v v cc 5.5v 0 ? 20 mhz 2.7v v cc < 3.0v 0 ? 10 mhz
r8c/16 group, r8c/17 group 5. electrical characteristics rev.2.00 jan 30, 2006 page 20 of 35 rej03b0101-0200 notes: 1. v cc = av cc = 2.7 to 5.5v at t opr = -20 to 85 c / -40 to 85 c, unless otherwise specified. 2. if f1 exceeds 10mhz, divide the f1 and hold a/d operating clock frequency ( ad ) 10mhz or below. 3. if the avcc is less than 4.2v, divide the f1 and hold a/d operating clock frequency ( ad ) f1/2 or below. 4. hold v cc = v ref figure 5.1 port p1, p3 and p4 measurement circuit table 5.3 a/d converter characteristics symbol parameter conditions standard unit min. typ. max. ? resolution v ref = v cc ?? 10 bits ? absolute accuracy 10-bit mode ad = 10mhz, v ref = v cc = 5.0v ?? 3 lsb 8-bit mode ad = 10mhz, v ref = v cc = 5.0v ?? 2 lsb 10-bit mode ad = 10mhz, v ref = v cc = 3.3v (3) ?? 5 lsb 8-bit mode ad = 10mhz, v ref = v cc = 3.3v (3) ?? 2 lsb r ladder resistor ladder v ref = v cc 10 ? 40 k ? t conv conversion time 10-bit mode ad = 10mhz, v ref = v cc = 5.0v 3.3 ?? s 8-bit mode ad = 10mhz, v ref = v cc = 5.0v 2.8 ?? s v ref reference voltage ? v cc (4) ? v v ia analog input voltage 0 ? v ref v ? a/d operating clock frequency (2) without sample & hold 0.25 ? 10 mhz with sample & hold 1 ? 10 mhz p1 p3 p4 30pf
r8c/16 group, r8c/17 group 5. electrical characteristics rev.2.00 jan 30, 2006 page 21 of 35 rej03b0101-0200 notes: 1. v cc = avcc = 2.7 to 5.5v at t opr = 0 to 60 c, unless otherwise specified. 2. definition of program and erase the program and erase endurance shows an erase endurance for every block. if the program and erase endurance is ?n? times (n = 100, 10000), ?n? times erase can be performed for every block. for example, if performing 1-byte write to the distinct addr esses on block a of 1kbyte block 1,024 times and then erasing that block, program and erase endu rance is counted as one time. however, do not perform multiple programs to the same address for one time ease.(disable overwriting). 3. endurance to guarantee all electrical c haracteristics after program and erase.(1 to ?min.? value can be guaranateed). 4. in the case of a system to execute multiple programs, per form one erase after programming as reducing effective reprogram endurance not to leave blank area as pos sible such as programming write addresse s in turn. if programming a set of 16 bytes, programming up to 128 sets and then erasing them one time can reduce effective r eprogram endurance. additionally, averaging erase endurance for block a and b can reduce effe ctive reprogram endurance more. to leave erase endurance for every block as information and determi ne the restricted endurance are recommended. 5. if error occurs during block er ase, attempt to execute the clear status r egister command, then the block erase command at least three times until the erase error does not occur. 6. customers desiring program/erase failure rate information should contact their renesas te chnical support representative. 7. the data hold time incudes time that the power supply is off or th e clock is not supplied. table 5.4 flash memory (program rom) electrical characteristics symbol parameter conditions standard unit min. typ. max. ? program/erase endurance (2) r8c/16 group 100 (3) ?? times r8c/17 group 1,000 (3) ?? times ? byte program time v cc = 5.0 v at t opr = 25 c ? 50 400 s ? block erase time v cc = 5.0 v at t opr = 25 c ? 0.4 9 s t d(sr-es) time delay from suspend request until erase suspend ?? 8ms ? erase suspend request interval 10 ?? ms ? program, erase voltage 2.7 ? 5.5 v ? read voltage 2.7 ? 5.5 v ? program, erase temperature 0 ? 60 c ? data hold time (7) ambient temperature = 55 c20 ?? year
r8c/16 group, r8c/17 group 5. electrical characteristics rev.2.00 jan 30, 2006 page 22 of 35 rej03b0101-0200 notes: 1. v cc = avcc = 2.7 to 5.5v at topr = ? 20 to 85 c / ? 40 to 85 c, unless otherwise specified. 2. definition of program and erase the program and erase endurance shows an erase endurance for every block. if the program and erase endurance is ?n? times (n = 100, 10000), ?n? times erase can be performed for every block. for example, if performing 1-byte write to the distinct addr esses on block a of 1kbyte block 1,024 times and then erasing that block, program and erase endu rance is counted as one time. however, do not perform multiple programs to the same address for one time ease.(disable overwriting). 3. endurance to guarantee all electrical c haracteristics after program and erase.(1 to ?min.? value can be guaranateed). 4. standard of block a and block b when program and erase endur ance exceeds 1,000 times. byte program time to 1,000 times are the same as that in program area. 5. in the case of a system to execute multiple programs, per form one erase after programming as reducing effective reprogram endurance not to leave blank area as pos sible such as programming write addresse s in turn. if programming a set of 16 bytes, programming up to 128 sets and then erasing them one time can reduce effective r eprogram endurance. additionally, averaging erase endurance for block a and b can reduce effe ctive reprogram endurance more. to leave erase endurance for every block as information and determi ne the restricted endurance are recommended. 6. if error occurs during block er ase, attempt to execute the clear status r egister command, then the block erase command at least three times until the erase error does not occur. 7. customers desiring program/erase failure rate information should contact their renesas te chnical support representative. 8. -40 c for d version. 9. the data hold time incudes time that the power supply is off or th e clock is not supplied. table 5.5 flash memory (data flash block a, block b) electrical characteristics symbol parameter conditions standard unit min. typ. max. ? program/erase endurance (2) 10,000 (3) ?? times ? byte program time (program/erase endurance 1,000 times) v cc = 5.0 v at t opr = 25 c ? 50 400 s byte program time (program/erase endurance > 1,000 times) v cc = 5.0 v at t opr = 25 c ? 65 ? s block erase time (program/erase endurance 1,000 times) v cc = 5.0 v at t opr = 25 c ? 0.2 9 s ? block erase time (program/erase endurance > 1,000 times) v cc = 5.0 v at t opr = 25 c ? 0.3 ? s t d(sr-es) time delay from suspend request until erase suspend ?? 8ms ? erase suspend request interval 10 ?? ms ? program, erase voltage 2.7 ? 5.5 v ? read voltage 2.7 ? 5.5 v ? program, erase temperature -20 (8) ? 85 c ? data hold time (9) ambient temperature = 55 c20 ?? year
r8c/16 group, r8c/17 group 5. electrical characteristics rev.2.00 jan 30, 2006 page 23 of 35 rej03b0101-0200 figure 5.2 time delay from suspend request until erase suspend notes: 1. the measurement condition is v cc = av cc = 2.7v to 5.5v and t opr = -40 c to 85 c. 2. necessary time until the voltage detecti on circuit operates when setting to ?1? again after setting the vca26 bit in the vca2 register to ?0?. 3. hold v det2 > v det1 . notes: 1. the measurement condition is vcc = av cc = 2.7v to 5.5v and topr = -40 c to 85 c. 2. time until the voltage monitor 2 interrupt request is generated since the voltage passes v det1 . 3. necessary time until the voltage detecti on circuit operates when setting to ?1? again after setting the vca27 bit in the vca2 register to ?0?. 4. hold v det2 > v det1 . table 5.6 voltage detection 1 circuit electrical characteristics symbol parameter condition standard unit min. typ. max. v det1 voltage detection level (3) 2.70 2.85 3.00 v ? voltage detection circuit self power consumption vca26 = 1, v cc = 5.0v ? 600 ? na t d(e-a) waiting time until voltage detection circuit operation starts (2) ?? 100 s vccmin microcomputer operating voltage minimum value 2.7 ?? v table 5.7 voltage detection 2 circuit electrical characteristics symbol parameter condition standard unit min. typ. max. v det2 voltage detection level (4) 3.00 3.30 3.60 v ? voltage monitor 2 interrupt request generation time (2) ? 40 ? s ? voltage detection circuit self power consumption vca27 = 1, v cc = 5.0v ? 600 ? na t d(e-a) waiting time until voltage detection circuit operation starts (3) ?? 100 s fmr46 erase-suspend request (maskable interrupt request) t d(sr-es)
r8c/16 group, r8c/17 group 5. electrical characteristics rev.2.00 jan 30, 2006 page 24 of 35 rej03b0101-0200 notes: 1. this condition is not appl icable when using with vcc 1.0v. 2. when turning power on after the time to hold the external power below effective voltage (v por1 ) exceeds10s, refer to table 5.9 reset circuit electrical characteristics (when not using voltage monitor 1 reset) . 3. t w(por2) is time to hold the external power below effective voltage (v por2 ). notes: 1. when not using the voltage monitor 1 reset, use with vcc 2.7v. 2. t w(por1) is time to hold the external power below effective voltage (v por1 ). figure 5.3 reset circuit electrical characteristics table 5.8 reset circuit electrical characte ristics (when using voltage monitor 1 reset ) symbol parameter condition standard unit min. typ. max. v por2 power-on reset valid voltage -20 c to p r < 85 c ?? v det1 v t w(vpor2-vdet1) supply voltage rising time when power-on reset is deasserted (1) -20 c to p r < 85 c, t w(por2) 0s (3) ?? 100 ms table 5.9 reset circuit electrical characteri stics (when not using voltage monitor 1 reset) symbol parameter condition standard unit min. typ. max. v por1 power-on reset valid voltage -20 c topr < 85 c ?? 0.1 v t w(vpor1-vdet1) supply voltage rising time when power-on reset is deasserted 0 c topr 85 c, t w(por1) 10s (2) ?? 100 ms t w(vpor1-vdet1) supply voltage rising time when power-on reset is deasserted -20 c topr < 0 c, t w(por1) 30s (2) ?? 100 ms t w(vpor1-vdet1) supply voltage rising time when power-on reset is deasserted -20 c topr < 0 c, t w(por1) 10s (2) ?? 1ms t w(vpor1-vdet1) supply voltage rising time when power-on reset is deasserted 0 c topr 85 c, t w(por1) 1s (2) ?? 0.5 ms notes: 1. hold the voltage of the microcomputer operation voltage range (vccmin or above) within sampling time. 2. a sampling clock can be selected. refer to 6. voltage detection circuit of hardware manual for details. 3. v det1 indicates the voltage detection level of the voltage detection 1 circuit. refer to 6. voltage detection circuit of hardware manual for details. v det1 (3) v por1 internal reset signal (?l? valid) t w(por1) t w(vpor1?vdet1) sampling time (1, 2) v det1 (3) 1 f ring-s 32 1 f ring-s 32 v por2 vccmin t w(por2) t w(vpor2?vdet1)
r8c/16 group, r8c/17 group 5. electrical characteristics rev.2.00 jan 30, 2006 page 25 of 35 rej03b0101-0200 notes: 1. the measurement condition is v cc = av cc = 5.0v and t opr = 25 c. 2. the standard value shows when the hra1 register is assumed as the value in shipping and the hra2 register value is set to 00h. notes: 1. the measurement condition is v cc = av cc = 2.7 to 5.5v and t opr = 25 c. 2. waiting time until the internal power s upply generation circuit stabilizes during power-on. 3. time until cpu clock supply starts since the interrupt is acknowledged to exit stop mode. table 5.10 high-speed on-chip oscillator circuit electrical characteristics symbol parameter condition standard unit min. typ. max. ? high-speed on-chip oscillator frequency when the reset is deasserted v cc = 5.0v, t opr = 25 c ? 8 ? mhz ? high-speed on-chip oscillator frequency temperature ? supplay voltage dependence 0 to +60 c / 5 v 5 % (2) 7.44 ? 8.56 mhz ? 20 to +85 c / 2.7 to 5.5 v (2) 7.04 ? 8.96 mhz ? 40 to +85 c / 2.7 to 5.5 v (2) 6.80 ? 9.20 mhz table 5.11 power supply circui t timing characteristics symbol parameter condition standard unit min. typ. max. t d(p-r) time for internal power supply stabilization during power-on (2) 1 ? 2000 s t d(r-s) stop exit time (3) ?? 150 s
r8c/16 group, r8c/17 group 5. electrical characteristics rev.2.00 jan 30, 2006 page 26 of 35 rej03b0101-0200 notes: 1. v cc = av cc = 2.7 to 5.5v, v ss = 0v and topr = -20 to 85 c / -40 to 85 c, unless otherwise specified. 2. 1t cyc =1/f1(s) figure 5.4 i/o timing of i 2 c bus interface (iic) table 5.12 timing requirements of i 2 c bus interface (iic) (1) symbol parameter condition standard unit min. typ. max. t scl scl input cycle time 12t cyc + 600 (2) ?? ns t sclh scl input ?h? width 3t cyc + 300 (2) ?? ns t scll scl input ?l? width 5t cyc + 300 (2) ?? ns t sf scl, sda input fall time ?? 300 ns t sp scl, sda input spike pulse rejection time ?? 1t cyc (2) ns t buf sda input bus-free time 5t cyc (2) ?? ns t stah start condition input hold time 3t cyc (2) ?? ns t stas retransmit start condition input setup time 3t cyc (2) ?? ns t stos stop condition input setup time 3t cyc (2) ?? ns t sdas data input setup time 1t cyc +20 (2) ?? ns t sdah data input hold time 0 ?? ns sda t stah t scll t buf v ih v il t sclh scl t sf t sdah t scl t stas t sp t stos t sdas p (2) s (1) sr (3) p (2) notes: 1. start condition 2. stop condition 3. retransmit ?start? condition
r8c/16 group, r8c/17 group 5. electrical characteristics rev.2.00 jan 30, 2006 page 27 of 35 rej03b0101-0200 notes: 1. v cc = av cc = 4.2 to 5.5v at t opr = -20 to 85 c / -40 to 85 c, f(xin)=20mhz, unless otherwise specified. table 5.13 electrical characteristics (1) [v cc = 5v] symbol parameter condition standard unit min. typ. max. v oh output ?h? voltage except x out i oh = -5ma v cc ? 2.0 ? v cc v i oh = -200 av cc ? 0.3 ? v cc v x out drive capacity high i oh = -1ma v cc ? 2.0 ? v cc v drive capacity low i oh = -500 av cc ? 2.0 ? v cc v v ol output ?l? voltage except p1_0 to p1_3, x out i ol = 5ma ?? 2.0 v i ol = 200 a ?? 0.45 v p1_0 to p1_3 drive capacity high i ol = 15ma ?? 2.0 v drive capacity low i ol = 5ma ?? 2.0 v drive capacity low i ol = 200 a ?? 0.45 v x out drive capacity high i ol = 1ma ?? 2.0 v drive capacity low i ol = 500 a ?? 2.0 v v t+- v t- hysteresis int0 , int1 , int3 , ki0 , ki1 , ki2 , ki3 , cntr0, cntr1, tcin, rxd0 0.2 ? 1.0 v reset 0.2 ? 2.2 v i ih input ?h? current vi = 5v ?? 5.0 a i il input ?l? current vi = 0v ?? -5.0 a r pullup pull-up resistance vi = 0v 30 50 167 k ? r fxin feedback resistance xin ? 1.0 ? m ? f ring-s low-speed on-chip oscillator frequency 40 125 250 khz v ram ram hold voltage during stop mode 2.0 ?? v
r8c/16 group, r8c/17 group 5. electrical characteristics rev.2.00 jan 30, 2006 page 28 of 35 rej03b0101-0200 table 5.14 electrical characteristics (2) [vcc = 5v] (topr = -40 to 85 c, unless otherwise specified.) symbol parameter condition standard unit min. typ. max. i cc power supply current (v cc =3.3 to 5.5v) in single-chip mode, the output pins are open and other pins are v ss high-speed mode xin = 20mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on=125khz no division ? 915ma xin = 16mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on=125khz no division ? 814ma xin = 10mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on=125khz no division ? 5 ? ma medium- speed mode xin = 20mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on=125khz divide-by-8 ? 4 ? ma xin = 16mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on=125khz divide-by-8 ? 3 ? ma xin = 10mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on=125khz divide-by-8 ? 2 ? ma high-speed on-chip oscillator mode main clock off high-speed on-chip oscillator on=8mhz low-speed on-chip oscillator on=125khz no division ? 48ma main clock off high-speed on-chip oscillator on=8mhz low-speed on-chip oscillator on=125khz divide-by-8 ? 1.5 ? ma low-speed on-chip oscillator mode main clock off high-speed on-chip oscillator off low-speed on-chip oscillator on=125khz divide-by-8 ? 470 900 a wait mode main clock off high-speed on-chip oscillator off low-speed on-chip oscillator on=125khz while a wait instruction is executed peripheral clock operation vca26 = vca27 = 0 ? 40 80 a wait mode main clock off high-speed on-chip oscillator off low-speed on-chip oscillator on=125khz while a wait instruction is executed peripheral clock off vca26 = vca27 = 0 ? 38 76 a stop mode main clock off, topr = 25 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca26 = vca27 = 0 ? 0.8 3.0 a
r8c/16 group, r8c/17 group 5. electrical characteristics rev.2.00 jan 30, 2006 page 29 of 35 rej03b0101-0200 timing requirements (unless otherwise specified: v cc = 5v, v ss = 0v at topr = 25 c) [ v cc = 5v ] notes: 1. when using timer c input capture mode, adjust the cycle time ( 1/ timer c count source frequency x 3) or above. 2. when using timer c input capture mode, adjust the widt h ( 1/ timer c count source frequency x 1.5) or above. notes: 1. when selecting the digital filter by the int0 input filter select bit, use the int0 input high width to the greater value, either (1/ digital filter clock fr equency x 3) or the minimum value of standard. 2. when selecting the digital filter by the int0 input filter select bit, use the int0 input low width to the greater value, either (1/ digital filter clock fr equency x 3) or the minimum value of standard. table 5.15 xin input symbol parameter standard unit min. max. t c(xin) xin input cycle time 50 ? ns t wh(xin) xin input ?h? width 25 ? ns t wl(xin) xin input ?l? width 25 ? ns table 5.16 cntr0 input, cntr1 input, int1 input symbol parameter standard unit min. max. t c(cntr0) cntr0 input cycle time 100 ? ns t wh(cntr0) cntr0 input ?h? width 40 ? ns t wl(cntr0) cntr0 input ?l? width 40 ? ns table 5.17 tcin input, int3 input symbol parameter standard unit min. max. t c(tcin) tcin input cycle time 400 (1) ? ns t wh(tcin) tcin input ?h? width 200 (2) ? ns t wl(tcin) tcin input ?l? width 200 (2) ? ns table 5.18 serial interface symbol parameter standard unit min. max. t c(ck) clki input cycle time 200 ? ns t w(ckh) clki input ?h? width 100 ? ns t w(ckl) clki input ?l? width 100 ? ns t d(c-q) txdi output delay time ? 50 ns t h(c-q) txdi hold time 0 ? ns t su(d-c) rxdi input setup time 50 ? ns t h(c-d) rcdi input hold time 90 ? ns table 5.19 external interrupt int0 input symbol parameter standard unit min. max. t w(inh) int0 input ?h? width 250 (1) ? ns t w(inl) int0 input ?l? width 250 (2) ? ns
r8c/16 group, r8c/17 group 5. electrical characteristics rev.2.00 jan 30, 2006 page 30 of 35 rej03b0101-0200 figure 5.5 timing diagram when v cc = 5v clk i txd i rxd i int i input t w(ckh) t c(ck) t w(ckl) t h(c-q) t h(c-d) t su(d-c) t d(c-q) t w(inl) t w(inh) x in input t wh(xin) t c(xin) t wl(xin) tcin input t wh(tcin) t c(tcin) t wl(tcin) cntr0 input t wh(cntr0) t c(cntr0) t wl(cntr0) v cc = 5v
r8c/16 group, r8c/17 group 5. electrical characteristics rev.2.00 jan 30, 2006 page 31 of 35 rej03b0101-0200 notes: 1. v cc = av cc = 2.7 to 3.3v at topr = -20 to 85 c / -40 to 85 c, f(xin)=10mhz, unless otherwise specified. table 5.20 electrical characteristics (3) [v cc = 3v] symbol parameter condition standard unit min. typ. max. v oh output ?h? voltage except x out i oh = -1ma v cc ? 0.5 ? v cc v x out drive capacity high i oh = -0.1ma v cc ? 0.5 ? v cc v drive capacity low i oh = -50 av cc ? 0.5 ? v cc v v ol output ?l? voltage except p1_0 to p1_3, x out i ol = 1ma ?? 0.5 v p1_0 to p1_3 drive capacity high i ol = 2ma ?? 0.5 v drive capacity low i ol = 1ma ?? 0.5 v x out drive capacity high i ol = 0.1ma ?? 0.5 v drive capacity low i ol = 50 a ?? 0.5 v v t+- v t- hysteresis int0 , int1 , int3 , ki0 , ki1 , ki2 , ki3 , cntr0, cntr1, tcin, rxd0 0.2 ? 0.8 v reset 0.2 ? 1.8 v i ih input ?h? current vi = 3v ?? 4.0 a i il input ?l? current vi = 0v ?? -4.0 a r pullup pull-up resistance vi = 0v 66 160 500 k ? r fxin feedback resistance xin ? 3.0 ? m ? f ring-s low-speed on-chip oscillator frequency 40 125 250 khz v ram ram hold voltage during stop mode 2.0 ?? v
r8c/16 group, r8c/17 group 5. electrical characteristics rev.2.00 jan 30, 2006 page 32 of 35 rej03b0101-0200 table 5.21 electrical characteristics (4) [vcc = 3v] (topr = -40 to 85 c, unless otherwise specified.) symbol parameter condition standard unit min. typ. max. i cc power supply current (v cc =2.7 to 3.3v) in single-chip mode, the output pins are open and other pins are v ss high-speed mode xin = 20mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on=125khz no division ? 813ma xin = 16mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on=125khz no division ? 712ma xin = 10mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on=125khz no division ? 5 ? ma medium- speed mode xin = 20mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on=125khz divide-by-8 ? 3 ? ma xin = 16mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on=125khz divide-by-8 ? 2.5 ? ma xin = 10mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on=125khz divide-by-8 ? 1.6 ? ma high-speed on-chip oscillator mode main clock off high-speed on-chip oscillator on=8mhz low-speed on-chip oscillator on=125khz no division ? 3.5 7.5 ma main clock off high-speed on-chip oscillator on=8mhz low-speed on-chip oscillator on=125khz divide-by-8 ? 1.5 ? ma low-speed on-chip oscillator mode main clock off high-speed on-chip oscillator off low-speed on-chip oscillator on=125khz divide-by-8 ? 420 800 a wait mode main clock off high-speed on-chip oscillator off low-speed on-chip oscillator on=125khz while a wait instruction is executed peripheral clock operation vca26 = vca27 = 0 ? 37 74 a wait mode main clock off high-speed on-chip oscillator off low-speed on-chip oscillator on=125khz while a wait instruction is executed peripheral clock off vca26 = vca27 = 0 ? 35 70 a stop mode main clock off, topr = 25 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca26 = vca27 = 0 ? 0.7 3.0 a
r8c/16 group, r8c/17 group 5. electrical characteristics rev.2.00 jan 30, 2006 page 33 of 35 rej03b0101-0200 timing requirements (unless otherwise specified: v cc = 3v, v ss = 0v at topr = 25 c) [v cc = 3v] notes: 1. when using the timer c input capture mode, adjust the cycl e time (1/ timer c count source frequency x 3) or above. 2. when using the timer c input capture mode, adjust the wi dth (1/ timer c count source frequency x 1.5) or above. notes: 1. when selecting the digital filter by the int0 input filter select bit, use the int0 input high width to the greater value, either (1/ digital filter clock fr equency x 3) or the minimum value of standard. 2. when selecting the digital filter by the int0 input filter select bit, use the int0 input low width to the greater value, either (1/ digital filter clock fr equency x 3) or the minimum value of standard. table 5.22 xin input symbol parameter standard unit min. max. t c(xin) xin input cycle time 100 ? ns t wh(xin) xin input ?h? width 40 ? ns t wl(xin) xin input ?l? width 40 ? ns table 5.23 cntr0 input, cntr1 input, int1 input symbol parameter standard unit min. max. t c(cntr0) cntr0 input cycle time 300 ? ns t wh(cntr0) cntr0 input ?h? width 120 ? ns t wl(cntr0) cntr0 input ?l? width 120 ? ns table 5.24 tcin input, int3 input symbol parameter standard unit min. max. t c(tcin) tcin input cycle time 1,200 (1) ? ns t wh(tcin) tcin input ?h? width 600 (2) ? ns t wl(tcin) tcin input ?l? width 600 (2) ? ns table 5.25 serial interface symbol parameter standard unit min. max. t c(ck) clki input cycle time 300 ? ns t w(ckh) clki input ?h? width 150 ? ns t w(ckl) clki input ?l? width 150 ? ns t d(c-q) txdi output delay time ? 80 ns t h(c-q) txdi hold time 0 ? ns t su(d-c) rxdi input setup time 70 ? ns t h(c-d) rcdi input hold time 90 ? ns table 5.26 external interrupt int0 input symbol parameter standard unit min. max. t w(inh) int0 input ?h? width 380 (1) ? ns t w(inl) int0 input ?l? width 380 (2) ? ns
r8c/16 group, r8c/17 group 5. electrical characteristics rev.2.00 jan 30, 2006 page 34 of 35 rej03b0101-0200 figure 5.6 timing diagram when v cc = 3v clk i txd i rxd i int i input t w(ckh) t c(ck) t w(ckl) t h(c-q) t h(c-d) t su(d-c) t d(c-q) t w(inl) t w(inh) x in input t wh(xin) t c(xin) t wl(xin) tcin input t wh(tcin) t c(tcin) t wl(tcin) cntr0 input v cc = 3v t wh(cntr0) t c(cntr0) t wl(cntr0)
rev.2.00 jan 30, 2006 page 35 of 35 rej03b0101-0200 r8c/16 group, r8c/17 group package dimensions package dimensions y index mark 1 10 11 20 f * 1 * 3 * 2 c b p e a d e h e include trim offset. dimension " * 3" does not note) do not include mold flash. dimensions " * 1" and " * 2" 1. 2. detail f a 1 a 2 l 0.32 0.22 0.17 b p previous code jeita package code renesas code plsp0020jb-a 20p2f-a mass[typ.] 0.1g p-lssop20-4.4x6.5-0.65 0.2 0.15 0.13 max nom min dimension in millimeters symbol reference 6.6 6.5 6.4 d 4.5 4.4 4.3 e 1.15 a 2 6.6 6.4 6.2 1.45 a 0.2 0.1 0 0.7 0.5 0.3 l 10 0 c 0.65 e 0.10 y h e a 1 0.53 0.77
a - 1 revision history r8c/16 group, r8c/17 group datasheet rev. date description page summary 0.10 sep 06, 2004 ? first edition issued 1.00 feb 25, 2005 2-3 tables 1.1 and 1.2 revised 5 table 1.3 and figure 1.2 revised 6 table 1.4 and figure 1.3 revised 7-8 figures 1.4 and 1.5 revised 16 table 4.1 revised: - 000fh: 000xxxxxb 00011111b - 0036h: 00001000b 0000x000b and 01001001b 0100x001b 18 tabel 4.3 revised: - 009ch: ffh 00h; notes2 added - 009dh: ffh 00h 21 table 5.3 revised 22 tables 5.4 and 5.5 revised 24 tables 5.8 and 5.9 revised 25 table 5.11 revised 26 table 5.12 and figure 5.4 added 27 table 5.13 revised 28 table 5.14 revised 29, 33 table 5.16 and 5.23 revised: table title ?int2? ?int1? 31 table 5.20 revised; note revised 32 table 5.21 revised 35 package dimensions revised 1.10 may 26, 2005 5, 6 tables 1.3 and 1.4 revised 16 table 4.1 revised: - 0009h: xxxxxx00b 00h - 000ah: 00xxx000b 00h - 001eh: xxxxx000b 00h 22 table 5.5 revised; note revised 26 fig 5.4 revised 27 table 5.13 revised 31 table 5.20 revised 2.00 jan 30, 2006 1 1. overview; ?20-pin plastic molded lssop or sdip? ?20-pin plastic molded lssop? revised 2 table 1.1 performance outline of the r8c/16 group; package: ?20-pin plastic molded sdip? deleted 3 table 1.2 performance outline of the r8c/17 group; package: ?20-pin plastic molded sdip? deleted, flash memory: (data area) (data flash) (program area) (program rom) revised 4 figure 1.1 block diagram; ?peripheral function? added, ?system clock generation? ?system clock generator? revised 5, 6 table 1.3 product information of r8c/16 group, table 1.4 product informatio n of r8c/17 group; revised. figure 1.2 part number, memory size and package of r8c/16 group, figure 1.3 part number, memory si ze and package of r8c/17 group; package type: ?dd : prdp0020ba-a? deleted revision history r8c/16 group, r8c/17 group datasheet
a - 2 revision history r8c/16 group, r8c/17 group datasheet 2.00 jan 30, 2006 8 figure 1.5 prdp0020ba-a package pin assignment (top view) deleted table 1.5 pin description; timer c: ?cmp0_0 to cmp0_3, cmp1_0 to cmp1_3? ?cmp0_0 to cmp0_2, cmp1_0 to cmp1_2? revised 10 figure 2.1 cpu register; ?reserved area? ?reserved bit? revised 12 2.8.10 reserved area; ?reserved area? ?reserved bit? revised 13 figure 3.1 memory map of r8c/16 group revised 14 3.2 r8c/17 group; (program area) (program rom), (data area) (data flash) revised figure 3.2 memory map of r8c/17 group revised 17 table 4.3 sfr information(3); 0085h: ?prescaler z? ?prescaler z register? 0086h: ?timer z secondary? ?timer z secondary register? 0087h: ?timer z primary? ?timer z primary register? 008ch: ?prescaler x? ?prescaler x register? 008dh: ?timer x? ?timer x register? 0090h, 0091h: ?timer c? ?timer c register? revised 21 table 5.4 flash memory (program rom) electrical characteristics; ? notes 1 to 7 added ??topr? ?ambient temperature?, ?(program area)? ?(program rom)? revised 22 table 5.5 flash memory (data flash block a, block b) electrical characteristics; ? note1 revised, note9 added ??topr? ?ambient temperature?, ?(program area)? ?(program rom)? revised 23 figure 5.2 time delay from suspend request until erase suspend revised table 5.7 voltage detection 2 circuit electrical characteristics; note1 revised 24 table 5.8 reset circuit electrical characteristics (when using voltage monitor 1 reset ); note2 revised table 5.9 reset circuit electrical ch aracteristics (when not using voltage monitor 1 reset); note1 revised 25 table 5.10 high-speed on-chip oscillato r circuit electrical characteristics revised 26 table 5.12 timing requirements of i2c bus interface (iic); note1 revised 28 table 5.14 electrical characte ristics (2) [vcc = 5v] revised 29 ?timing requirements (unless ... at ta = 25 c) [ vcc = 5v ]? ?timing requirements (unless ... at topr = 25 c) [ vcc = 5v ]? revised table 5.18 serial interface; ?35? ?50?, ?80? ?50? 32 table 5.21 electrical characte ristics (4) [vcc = 3v] revised 33 ?timing requirements (unless ... at ta = 25 c) [vcc = 3v]? ?timing requirements (unless ... at topr = 25 c) [vcc = 3v]? revised table 5.25 serial interface; ?55? ?70?, ?160? ?70? 35 package dimensions; package ?prdp0020ba-a? deleted rev. date description page summary
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