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| rtl8139c(l)+ 2001/12/06 rev.1.5 1 realtek 3.3v single chip fast ethernet controller with power management rtl8139c(l)+ 1. features........................................................................ 3 2. general de scription .................................................... 4 3. block diagram............................................................. 5 4. pin assignments .......................................................... 6 5. pin descriptions .......................................................... 7 5.1 power management/isolation interface ................. 7 5.2 pci interface .......................................................... 8 5.3 flash/bootprom/eep rom/mii interface ..... 10 5.4 power pins ........................................................... 11 5.5 led interface....................................................... 11 5.6 attachment unit interface.................................... 12 5.7 test and other pins .............................................. 12 6. register descriptions ................................................ 13 6.1 receive status register in rx packet header ...... 15 6.2 transmit status register ...................................... 16 6.3 dump tally counter command register (dtccr) ... 17 6.4 ersr: early rx status register .......................... 18 6.5 command register............................................... 18 6.6 interrupt mask register ....................................... 19 6.7 interrupt stat us register....................................... 20 6.8 transmit configur ation register.......................... 21 6.9 receive configur ation register ........................... 22 6.10 9346cr: 93c46 (93c56) command register ... 25 6.11 configuration regi ster 0 (config 0) .............. 25 6.12 configuration regi ster 1 (config 1) .............. 26 6.13 media status register ........................................ 27 6.14 configuration regi ster3 (config 3) ............... 28 6.15 configuration regi ster4 (config 4) ............... 29 6.16 multiple interrupt select register ...................... 30 6.17 pci revision id ................................................. 30 6.18 transmit status of all descriptors register (tsad) .. 30 6.19 basic mode c ontrol register ............................. 31 6.20 basic mode st atus register ............................... 32 6.21 auto-negotiation advertisement register.......... 33 6.22 auto-negotiation link partner ability register ... 34 6.23 auto-negotiation e xpansion register ................ 34 6.24 disconnect counter............................................ 35 6.25 false carrier sense counter............................... 35 6.26 nway test register ........................................... 35 6.27 rx_er counter ................................................. 35 6.28 cs configura tion register ................................. 36 6.29 low address of a tx descriptor with tx dma ok 36 6.30 flash memory read/write register (flash) .. 36 6.31 configuration regi ster 5 (config5) ................... 37 6.32 transmit priority polling register (tppoll) ...... 38 6.33 c+ command register (c+cr) ......................... 38 6.34 receive descriptor start address register (rdsar)... 39 6.35 early transmit threshold register (etthr) .... 39 6.36 function event register..................................... 40 6.37 function event mask register........................... 41 6.38 function present state register ......................... 42 6.39 function force event register/mii register ............. 43 7. eeprom contents................................................... 44 7.1 summary of eeprom registers......................... 46 7.2 summary of eeprom power management registers 46 8. pci configuration space registers......................... 47 8.1 pci bus interface................................................. 47 8.1.1 byte ordering ............................................... 47 8.1.2 interrupt control........................................... 47 8.1.3 latency timer .............................................. 47 8.1.4 32-bit data operation .................................. 48 8.1.5 64-bit addressing ........................................ 48 8.2 bus operation ...................................................... 48 8.2.1 target read .................................................. 48 8.2.2 target write ................................................. 49 8.2.3 master read.................................................. 50 8.2.4 master write................................................. 51 8.2.5 configuration access ................................... 51 8.3 packet buffering .................................................. 51 8.3.1 transmit buffer manager ............................. 52 8.3.2 receive buffer manager .............................. 52 8.3.3 packet recognition....................................... 52 8.4 pci configura tion space table ........................... 53 8.5 pci configurati on space functions..................... 55 8.6 the default value after power-on (rstb asserted)...... 59 8.7 pci power manage ment functions...................... 60 8.8 vital product data (vpd) .................................... 62 9. functional description ............................................. 63 9.1 transmit & receive operations in c mode ......... 63 9.1.1 transmit........................................................ 63 9.1.2 receive ......................................................... 63 9.2 transmit & receive operations in c+ mode ....... 63 9.2.1 transmit........................................................ 64 9.2.2 receive ......................................................... 70 9.3 line quality monitor ........................................... 73 9.4 clock recovery module ...................................... 73 9.5 loopback operation............................................. 73 9.6 tx encapsulation with the internal phyceiver............ 73
rtl8139c(l)+ 2001/12/06 rev.1.5 2 9.7 collision ............................................................... 73 9.8 rx decapsulation with the internal phyceiver ........... 74 9.9 flow control ........................................................ 74 9.9.1. control frame transmission ....................... 74 9.9.2. control frame reception............................. 74 9.10 medium auto-detect ......................................... 75 9.11 cable connec tion status .................................... 75 9.11 cable connec tion status .................................... 76 9.12 mii redundant link........................................... 77 9.13 memory functions ............................................. 78 9.13.1 memory read line (mrl)......................... 78 9.13.2 memory read multiple (mrm) ................. 78 9.13.3 memory write and invalidate (mwi) ........ 79 9.13.4 dual address cycle (dac)........................ 79 9.14 led functions ................................................... 80 9.14.1 10/100 mbps link monitor ........................ 80 9.14.2 led_rx..................................................... 80 9.14.3 led_tx..................................................... 81 9.14.4 led_tx+led_rx ................................... 81 9.15 physical layer interfaces ................................... 82 9.15.1 media independe nt interface (mii) ............ 82 9.15.2 mii management interface......................... 82 10. application diagram .............................................. 83 11. electrical characteristics ....................................... 84 11.1 temperature limit ratings ................................ 84 11.2 dc characteristics ............................................. 84 11.2.1 supply voltage ........................................... 84 11.3 ac characteristics ............................................. 85 11.3.1 flash/boot rom timing..................... 85 11.3.2 pci bus operation timing......................... 87 11.3.3 mii timing ................................................. 94 12. mechanical dimensions .......................................... 98 rtl8139c(l)+ 2001/12/06 rev.1.5 3 1. features 128 pin qfp/lqfp (pin-to-pin compatible with the rtl8139c(l)) software compatible to the rtl8139 series when configured in rtl8139c mode (c mode) supports descriptor-based buffer management when configured in rtl8139c+ mode (c+ mode) supports microsoft* ndis5 checksum offloads (ip, tcp, udp), and largesend offload in c+ mode supports ieee802.1q vlan tagging in c+ mode supports transmit (tx) priority queue for qos, cos applications in c+ mode integrated fast ethernet ma c, phy and transceiver in one chip 10mbps and 100mbps operation supports 10mbps and 100mbps n-way auto-negotiation operation pci local bus single-chip fast ethernet controller compliant to pci revision 2.2 supports pci clocks 16.75mhz-40mhz supports pci target fast back-to-back transaction supports memory read line, memory read multiple, memory write and invalidate, and dual address cycle, when set to c+ mode. provides pci bus master data transfers and pci memory space or i/o space mapped data transfers of the rtl8139c(l)+'s operational registers supports pci vpd (vital product data) supports acpi, pci power management supports optional pci multi-function with additional function in slave mode only. supports cardbus. the cis can be stored in the 93c56 or expansion rom supports either mii or boot rom interface, though only one interface can be implemented at a time. up to 128k byte boot rom interface for both eprom and flash memory can be supported supports 25mhz crystal or 25mhz osc as the internal clock source. the frequency deviation of either crystal or osc must be within 50 ppm compliant to pc99 and pc2001 standards supports wake-on-lan func tion and remote wake-up (magic packet*, linkchg and microsoft wake-up frame) supports 4 wake-on-lan (wol) signals (active high, active low, positive pulse, and negative pulse) supports auxiliary power-on internal reset, to be ready for remote wake-up when main power still remains off supports auxiliary power auto-detect, and sets the related capability of power management registers in pci configuration space includes a programmable, pci burst size and early tx/rx threshold supports a 32-bit general-purpose timer with the external pci clock as clock source, to generate timer-interrupt contains two large (2kbyte) independent receive (rx) and transmit (tx) fifos advanced power saving mode when lan function or wakeup function is not used uses 93c46 (64*16-bit eeprom) or 93c56 (128*16-bit eeprom) to store resource configuration, id parameter, and vpd data. the 93c56 can also be used to store the cis data structure for the cardbus application supports led pins for various network activity indications supports digital and anal og loopback capability on both ports half/full duplex capability supports full duplex flow control (ieee 802.3x) 3.3v power supply with 5v tolerant i/os * third-party brands and names are the property of their respective owners. note: the model number of the qfp package is rtl8139c+. the lqfp package model number is rtl8139cl+. rtl8139c(l)+ 2001/12/06 rev.1.5 4 2. general description the realtek rtl8139c(l)+ is a highly integrated and cost-effec tive single-chip fast ethernet controller that provides 32-bit performance, pci bus master capability, and full compliance with ieee 802.3u 100bas e-t specifications and ieee 802.3x full duplex flow control. it also supports advanced configura tion power management interface (acpi), pci power management for modern operating systems that is capable of operating sy stem directed power management (ospm) to achieve the most efficient power management. the rtl8139cl+ is suitable for applications such as cardbus or mobile with built-in network controller. the cis data can be stored in either the 93c56 eeprom or an external expansion rom. in addition to the acpi feature, the rtl8139c(l)+ also s upports remote wake-up (including amd magic packet, linkchg, and microsoft wake-up frame) in both acpi and apm environmen ts. the rtl8139c(l)+ is capable of performing an internal reset through the application of auxiliary power. when aux iliary power is on and the main power remains off, the rtl8139c(l)+ is ready and waiting for the magic packet or link change to wake the system up. also, the lwake pin provides 4 different output signals including active high, active low, positive pulse, and negative pulse. the versatility of t he rtl8139c(l)+ lwake pin provides motherboards with the wake-on-lan (wol) function. the rtl8139c(l)+ also supports analog auto-power-down, that is , the analog part of the rtl8139c(l)+ can be shut down temporarily according to user requirements or when the rtl8139c(l)+ is in a power down state with the wakeup function disabled. in addition, when the analog part is shut down and the isolateb pin is low (i.e. the main power is off), then both the anal og and digital parts stop functioning and power consumption of the rtl8139c(l)+ will be negligible. the r tl8139c(l)+ also supports an auxiliary power auto-detect function, and will auto-configure related bits of their own pci power management registers in pci configuration space. the pci vital product data (vpd) is also supported to provide the information that uniquely identifies hardware (i.e., the rtl8139c(l)+ lan card). the information may consist of part number, serial number, and other detailed information. in order to provide a lower cost system, the rtl8139c(l)+ is capable of using a 25mhz crystal as its internal clock source. a 25mhz osc can also be used. there are 2 modes of buffer management modes which are supporte d by the rtl8139c(l)+. the first, c mode, is just like the buffer management algorithm which former rtl8139 series products use; the second is c+ mode (set only by software to the relative c+ mode registers and descriptors) which is an enha nced descriptor-based design es pecially suitable for server applications. the rtl8139c(l)+ is hardware compatible to th e rtl8139c(l), and is software backwards compatible to the rtl8139 series when set to c mode (the default setting). the rtl8139c(l)+ can be configured by software to apply a new buffer management algorithm, i.e., enhanced descriptor-based buffe r management architecture, which is an essential design as a modern network server card. the rtl8139c(l)+ fully complies to microsoft ndis5 (ip, tcp, udp) checksum and segmentation task-offload features, and supports ieee802.1q vlan (virtual bridged local area network). all of the above rtl8139c(l)+ new features contribute to lower cpu utilization, which is a plus when serving as a network serv er card. also, the rtl8139c(l)+ boosts its pci performance by supporting pc i memory read line & memory read multip le when transmitting, memory write and invalidate when receiving. to be better qua lified as a server card, the rtl8139c(l)+ also supports the pci dual address cycle (dac) command, when the assigned buffers reside at the physical memory addresses higher than 4 gigabytes. for qos and cos requirements, the rtl8139c(l)+ supports hardware high priority queuing to redu ce software implementation effort and significantly improve performance. the rtl8139c(l)+ keeps network maintenance costs low and eliminates usage barriers. it is the easiest way to upgrade a network from 10 to 100mbps. it also supports full- duplex operation, maki ng 200mbps of bandwidth possibl e at no additional cost. to improve compatibility with other brands? pr oducts, the rtl8139c(l)+ is also capable of receiving packets with interframegap no less than 40 bit-time. the rtl8139c(l)+ is highly integrated and requires no ?glue? logic or external memory. it includes an interface for a boot rom and can be used in diskless workstations, provi ding maximum network security and ease of management. for special applications, the r tl8139c(l)+ also supports an mii interface, which can be used, for example, to provide a redunda nt link with an external phyceiver, or a c onnection to a fiber channel with a fiber tr ansceiver. because of pin count limitation, the rtl8139c(l)+ does not suppor t a boot rom interface when the mii interface is used, and vice versa. rtl8139c(l)+ 2001/12/06 rev.1.5 5 3. block diagram mii interface interrupt control logic fifo transmit/ receive logic interface early interrupt control logic fifo control logic packet type discriminator power control logic pci interface + register packet length register early interrupt threshold register boot rom interface eeprom interface led driver rxin+ rxin- txo+ txo - rxc 25m 25m txc 25m txd rxd td+ variable current 3 level driver master ppl adaptive equalizer peak detect 3 level comparator control voltage mlt-3 to nrzi serial to parrallel ck data slave pll parrallel to serial baseline wander correction 5b 4b decoder data alignment descrambler 4b 5b encoder scrambler 10/100 half/full switch logic 10/100m auto-negotiation control logic manchester coded waveform 10m output waveform shaping data recovery receive low pass filter rxd rxc 25m txd txc 25m txd10 txc10 rxd10 rxc10 link pulse mii interface 10m 100m pci interface mac phy transceiver rtl8139c(l)+ 2001/12/06 rev.1.5 6 4. pin assignments 1 vdd 2 cbe3b 3 idsel 4 ad23 5 ad22 6 ad21 7 gnd 8 ad20 9 ad19 10 ad18 11 ad17 12 vdd 13 ad16 14 cbe2b rtl8139c(l)+ 64 ma10/mcol 63 ma9/mrxc 62 gnd 61 ma8/auxd/mtxd3 60 ma7/mtxd2 59 vdd 58 vdd 57 ma6/9356sel/mtxd1 56 gnd 55 gnd 53 ma5/mtxd0 52 ma4/mtxe 51 ma3/mtxc 49 ma2/eesk 48 ma1/eedi 47 ma0/eedo 46 vdd 45 ad0 44 ad1 43 ad2 42 ad3 41 ad4 40 gnd 39 ad5 17 trdyb 18 gnd 19 devselb 20 stopb 21 perrb 22 serrb 23 par 24 cbe1b 25 vdd 26 ad15 27 ad14 28 ad13 29 ad12 30 gnd 31 ad11 32 ad10 33 ad9 34 ad8 35 vdd 36 cbe0b 37 ad7 38 ad6 103 md4/mfdup 104 md3 105 md2 106 vdd 107 md1 108 md0 109 vdd 110 romcsb 111 gnd 112 gnd 113 gnd 114 intab 115 rstb 119 vdd 120 ad31 121 ad30 122 ad29 123 ad28 124 gnd 125 ad27 126 ad26 127 ad25 128 ad24 65 ma11/mrxdv 66 ma12/mrxd0 67 ma13/mrxd1 68 ma14/mrxd2 69 ma15/mrxd3 70 ma16/mrxer 71 nc 72 nc 73 nc 74 gnd 75 clkrunb 76 pmeb 77 vdd 78 x2 79 x1 80 gnd 81 rtt3 82 rtt2 83 lwake/cstschg 84 rtset 85 gnd 86 rxin- 87 rxin+ 88 oeb 89 web 90 vdd 92 txd+ 93 gnd 94 nc 95 isolateb 96 vdd 97 led2 98 led1 99 led0 101 md6/mdio 102 md5/mlink 100 md7/mdc 16 irdyb 15 frameb 54 nc 50 eecs 91 txd- 116 clk 117 gntb 118 reob avdd avdd avdd agnd agnd agnd agnd rtl8139c(l)+ 2001/12/06 rev.1.5 7 5. pin descriptions in order to reduce pin count, and therefore size and cost, some pins have multiple f unctions. in those cases, the functions are separated with a ?/? symbol. refer to the pin assignment diagram for a graphical representation. 5.1 power management/isolation interface symbol type pin no description pmeb (pme#) o/d 76 power management event: open drain, active low. used by the rtl8139c(l)+ to request a change in its current power management state and/or to indicate that a pow er management event has occurred. isolateb (isolate#) i 95 isolate pin: active low. used to isolate the rtl8139c(l)+ from the pci bus. the rtl8139c(l)+ does not drive its pci outputs (excluding pme#) and does not sample its pci input (including rst# and pciclk) as long as the isolate pin is asserted. lwake/ cstschg o 83 lan wake-up signal (when ca rdb_en=0, bit2 config3): this signal is used to inform the motherboard to execute the wake-up process. the motherboard must support wake-on-lan (wol). there are 4 choices of output, including active high, active low, positive pulse, and negative pulse, that may be asserted from the lwake pin. please refer to the lwact bit in the config1 register and the lwptn bit in the config4 register for the setting of this output signal. the default output is an active high signal. once a pme event is received, the lwake and pmeb assert at the same time when the lwpme (bit4, config4) is set to 0. if the lwpme is set to 1, the lwake asserts only when the pmeb asserts and the isolateb is low. cstschg signal (when cardb_en=1, bit2 config3): this signal is used in cardbus applications only and is used to inform the motherboard to execute the wake- up process whenever a pme event occurs. this is always an active high signal, and the setting of lwact (bit 4, config1), lwptn (bit2, config4), and lwpme (bit4, config4) mean nothing in this case. this pin is a 3.3v signaling output pin. rtl8139c(l)+ 2001/12/06 rev.1.5 8 5.2 pci interface symbol type pin no description ad31-0 t/s 120-123, 125-128, 4-6, 8-11, 13, 26-29, 31-34, 37-39, 41-45 pci address and data multiplexed pins. c/be3-0 t/s 2, 14, 24, 36 pci bus command and byte enables multiplexed pins. clk i 116 clock: this pci bus clock provides timing for all transactions and bus phases, and is input to pci devices. the rising edge defines the start of each phase. the clock frequenc y ranges from 0 to 33mhz. for network operation to be functi onal, the pci bus clock frequency should be higher than 16.75mhz. clkrunb i/o 75 clock run: this signal is used by the rtl8139c(l)+ to request starting (or speeding up) the clock, clk. clkrunb al so indicates the clock status. for the rtl8139c(l)+, clkrunb is an open drain output as well as an input. the rtl8139c(l)+ requests the central resource to start, speed up, or maintain the interface clock by the assertion of clkr unb. for the host system, it is an s/t/s signal. the host system (central resource) is responsible for maintaining clkrunb asserted, and for driving it high to the negated (deasserted) state. devselb s/t/s 19 device select: as a bus master, the rtl8139c(l)+ samples this signal to insure that a pci target recognizes the destination address for the data transfer. as a target, the rtl8139c(l)+ asserts this signal low when it recognizes its target address after frameb is asserted. frameb s/t/s 15 cycle frame: as a bus master, this pin indicates the beginning and duration of an access. frameb is asse rted low to indicate the start of a bus transaction. while frameb is asserted, data transfer continues. when frameb is deasserted, the transaction is in the final data phase. as a target, the device monitors this signal before decoding the address to check if the current transaction is addressed to it. gntb i 117 grant: this signal is asserted low to indicate to the rtl8139c(l)+that the central arbiter has granted ownership of the bus to the rtl8139c(l)+. this input is used when the rtl8139c(l)+is acting as a bus master. reqb t/s 118 request: the rtl8139c(l)+will assert this signal low to request the ownership of the bus from the central arbiter. idsel i 3 initialization device select : this pin allows the rtl8139c(l)+to identify when configuration read/write transactions are intended for it. intab o/d 114 interrupt a: used to request an interrupt. it is asserted low when an interrupt condition occurs, as defined by the interrupt status, and interrupt mask registers. irdyb s/t/s 16 initiator ready : this indicates the initiating agent?s ability to complete the current data phase of the transaction. as a bus master, this signal will be asserted low when the rtl8139c(l)+is ready to complete the current data phase transaction. this signal is used in conjunction with the trdyb signal. data transaction takes place at the rising edge of clk when both irdyb and trdyb are asserted low. as a targ et, this signal indicates that the master has put data on the bus. trdyb s/t/s 17 target ready: this indicates the target agent?s ability to complete the current phase of the transaction. as a bus master, this signal indicates th at the target is ready for the data during write operations and with the data during read operations. as a target, this signal will be asserted low when the (slave) device is ready to com p lete the current data p hase transaction. this si g nal is used in rtl8139c(l)+ 2001/12/06 rev.1.5 9 conjunction with the irdyb signal. da ta transaction takes place at the rising edge of clk when both irdyb and trdyb are asserted low. par t/s 23 parity: this signal indicates even parity across ad31-0 and c/be3-0 including the par pin. as a master, par is asserted during address and write data phases. as a target, par is asserted during read data phases. perrb s/t/s 21 parity error: when the rtl8139c(l)+is the bus target and a parity error is detected, the rtl8139c(l )+asserts this perrb pin low. serrb o/d 22 system error: if an address parity error is detected and configuration space status register bit 15 (detect ed parity error) is enabled, rtl8139c(l)+ asserts both serrb pi n low and bit 14 of status register in configuration space. stopb s/t/s 20 stop: indicates the current target is requesting the master to stop the current transaction. rstb i 115 reset: when rstb is asserted low, the rtl8139c(l)+ performs an internal system hardware reset. rstb must be held for a minimum of 120 ns. rtl8139c(l)+ 2001/12/06 rev.1.5 10 5.3 flash/bootprom/eeprom/mii interface symbol type pin no description ma[16:9], ma7, ma[5:3] ma8 ma6 o o, i o, i 70-63, 60, 53-51 61 57 in boot prom (or flash) mode: ma16-3: (in boot prom mode only) output pins as boot prom address bus. these pins are used to access up to a 128k-byte flash memory or eprom. ma8: (in both boot prom mode and mii mode) input pin as aux. power detect pin to detect if aux. power exists or not, when initial power-on or pci reset is de-asserted. besides connecting this pin to boot prom or mii txd3, it should be pulled high to the aux. power via a resistor to detect aux. power. if this pin is not pulled high to the aux. power, the rtl8139c(l)+ assumes that no aux. power exists. to support wakeup from acpi d3cold or apm power-down, this pin must be pulled high to aux. power via a resistor. ma6/9356sel: (in both boot prom mode and mii mode) input pin as 9356 select pin at initial power-up. when this pin is pulled high with a 10k ? resistor, the 93c56 eeprom is used to store the resource data and cis for the rtl8139c(l)+. the rtl8139c(l)+ latches the status of this pin at power-up to determine what eeprom(93c46 or 93c56) is used, afterwards, this pin is used as ma6 or mtxd1. mrxer(ma16) i 70 in mii mode: mii receive error: (ma16 in mii mode) this pin is asserted to indicate that invalid symbol has been detected in 100mbps mii mode. this signal is synchronized to rxc and can be asserted for a minimum of one recei ve clock. when asserted during a packet reception, it sets the ise bit of the rsr register in the header o f the rx packet. mrxd[3:0](ma [15:12]) i 69-66 mii receive data: (ma15-12 in mii mode) this is a group of 4 data signals aligned on nibble boundaries which are driven synchronous to the rxc by the external physical unit. mrxdv(ma11) i 65 mii receive data valid: (ma11 in mii mode) data valid is asserted by an ex ternal phy when receive data is present on the mrxd[3:0] lines, and it is deasserted at the end of the packet. this signal is valid on the rising of the mrxc. mcol(ma10) i 64 mii collision detected: (ma10 in mii mode) this signal is asserted high synchronously by the external physical unit upon detection of a collision on the medium. it will remain asserted as long as the collision condition persists. mrxc(ma9) i 63 mii receive clock: (ma9 in mii mode) this is a continuous clock that is recovered from the incoming data. mrxc is 25mhz in 100mbps and 2.5mhz in 10mbs. mtxd[3:0](ma [8:5]) o 61, 60, 57, 53 mii transmit data: (ma8-5 in mii mode) four parallel transmit data lines which are driven synchronous to the mtxc for transmission by the external physical layer chip. rtl8139c(l)+ 2001/12/06 rev.1.5 11 mtxe(ma4) o 52 mii transmit enable: (ma4 in mii mode) indicates the presence of valid nibble data on mtxd[3:0]. mtxc(ma3) i 51 mii transmit clock: (ma3 in mii mode) mtxc is a continuous clock that provides a timing reference for the transfer of mtxd[3:0], mtxe. in mii mode, it uses the 25 mhz or 2.5 mhz supplied by the external pmd device. ma2/eesk o 49 the ma2-0 pins are switched to eesk, eedi, eedo in 93c46 (93c56) programming or auto-load mode. ma1/eedi o 48 ma0/eedo o, i 47 eecs o 50 93c46 (93c56) chip select md0-7 i/o 108, 107, 105-100 boot prom data bus in boot prom mode. mdc(md7) o 100 mdc: (md7 at mii mode) management data clock: synchronous clock to the mdio management data i nput/output serial interface which may be asynchronous to transmit and receive clocks. mdio(md6) i/o 101 mdio: (md6 in mii mode) management data: bi-directional signal used to transfer management information. mlink(md5) i 102 mlink: (md5 in mii mode) link status notification from external phyceiver. mfdup(md4) i 103 mfdup: (md4 in mii mode) full-duplex status notification from external phyceiver. romcsb o 110 rom chip select: this is the chip select signal of the boot prom. oeb o 88 output enable: this enables the output buffer of the boot prom or flash memory during a read operation. web o 89 write enable: this signal strobes data into the flash memory during a write cycle. 5.4 power pins symbol type pin no description vdd p 1, 12, 25, 35, 46, 58, 59, 106, 109, 119 digital power +3.3v avdd p 77, 90, 96 analog power +3.3v gnd p 7, 18, 30, 40, 55, 56, 62, 111, 112, 113, 124 digital ground agnd p 74, 80, 85, 93 analog ground 5.5 led interface symbol type pin no description led0, 1, 2 o 99, 98, 97 led pins leds1-0 00 01 10 11 led0 tx/rx tx/rx tx link10/act led1 link100 link10/100 link10/100 link100/act led2 link10 full rx full during power down mode, the leds are off. rtl8139c(l)+ 2001/12/06 rev.1.5 12 5.6 attachment unit interface symbol type pin no description txd+ txd- o o 92 91 100/10base-t transmit (tx) data rxin+ rxin- i i 87 86 100/10base-t receive (rx) data x1 i 79 25 mhz crystal/osc. input x2 o 78 crystal feedback output: this output is used in crystal connection only. it must be left open when x1 is driven with an external 25mhz oscillator. 5.7 test and other pins symbol type pin no description rtt2-3 test 81, 82 chip test pins. rtset i/o 84 this pin must be pulled low by a resistor. please refer to the application circuit for correct value. nc - 54, 71, 72, 73, 94 reserved rtl8139c(l)+ 2001/12/06 rev.1.5 13 6. register descriptions the rtl8139c(l)+ provides the following set of operational registers mapped in to pci memory space or i/o space. offset r/w tag description 0000h r/w idr0 id register 0: the id registers 0-5 are only permitted to write by 4-byte access. read access can be byte, word, or double word access. the initial value is autoloaded from the eeprom ethernetid field. 0001h r/w idr1 id register 1 0002h r/w idr2 id register 2 0003h r/w idr3 id register 3 0004h r/w idr4 id register 4 0005h r/w idr5 id register 5 0006h-0007h - - reserved 0008h r/w mar0 multicast register 0: the mar registers 0-7 are only permitted to write by 4-byte access. read access can be byte, word, or double word access. driver is responsible fo r initializing these registers. 0009h r/w mar1 multicast register 1 000ah r/w mar2 multicast register 2 000bh r/w mar3 multicast register 3 000ch r/w mar4 multicast register 4 000dh r/w mar5 multicast register 5 000eh r/w mar6 multicast register 6 000fh r/w mar7 multicast register 7 0010h-0013h r/w tsd0 transmit status of descriptor 0 (c mode only) 0014h-0017h r/w tsd1 transmit status of descriptor 1 (c mode only) dump tally counter command register (c+ mode only) 0018h-001bh r/w tsd2 transmit status of descriptor 2 (c mode only) 001ch-001fh r/w tsd3 transmit status of descriptor 3 (c mode only) 0020h-0023h r/w tsad0 transmit start address (32-bit) of descriptor0 (c mode only, double-word alignment) 0024h-0027h r/w tsad1 tnpds transmit start address (32-bit) of descriptor1 (c mode only, double-word alignment) transmit normal priority descriptors start address (64-bit). (c+ mode only, 256-byte alignment) 0028h-002bh r/w tsad2 transmit start address (32-bit) of descriptor2 (c mode only, double-word alignment) 002ch-002fh r/w tsad3 thpds transmit start address (32-bit) of descriptor3 (c mode only, double-word alignment) transmit high priority descriptors start address (64-bit). (c+ mode only, 256-byte alignment) 0030h-0033h r/w rbstart receive (rx) buffer start address (c mode only, double-word alignment) 0034h-0035h r erbcr early receive (rx) byte count register 0036h r ersr early rx status register 0037h r/w cr command register 0038h-0039h r/w capr current address of packet read (c mode only, the initial value is 0fff0h) 003ah-003bh r cbr current buffer address: the initial value is 0000h. it reflects total received byte-count in the rx buffer. (c mode only) 003ch-003dh r/w imr interrupt mask register 003eh-003fh r/w isr interrupt status register 0040h-0043h r/w tcr transmit (tx) configuration register 0044h-0047h r/w rcr receive (rx) configuration register rtl8139c(l)+ 2001/12/06 rev.1.5 14 0048h-004bh r/w tctr timer count register: this register contains a 32-bit general-purpose timer. writing any value to this 32-bit register will reset the original timer and begin to count from zero. 004ch-004fh r/w mpc missed packet counter: indicates the number of packets discarded due to rx fifo overflow. it is a 24-bit counter. after a s/w reset, mpc is cleared. only the lower 3 bytes are valid. writing any value to this register will reset mpc. 0050h r/w 9346cr 93c46 (93c56) command register 0051h r/w config0 configuration register 0 0052h r/w config1 configuration register 1 0053h - - reserved 0054h-0057h r /w timerint timer interrupt register: when a nonzero value is written to this register, the timeout bit of the isr register will be set whenever the tctr reaches this value. the timeout bit will never be set as long as the timerint register is zero. 0058h r/w msr media status register 0059h r/w config3 configuration register 3 005ah r/w config4 configuration register 4 005bh - - reserved 005ch-005dh r/w mulint multiple interrupt select 005eh r rerid pci revision id = 10h 005fh - - reserved 0060h-0061h r tsad transmit status of all descriptors (c mode only) 0062h-0063h r/w bmcr basic mode control register 0064h-0065h r bmsr basic mode status register 0066h-0067h r/w anar auto-negotiation advertisement register 0068h-0069h r anlpar auto-negotiation link partner register 006ah-006bh r aner auto-negotiation expansion register 006ch-006dh r dis disconnect counter 006eh-006fh r fcsc false carrier sense counter 0070h-0071h r/w nwaytr n-way test register 0072h-0073h r rec rx_er counter 0074h-0075h r/w cscr cs configuration register 0076-0077h - - reserved 0078h-007bh r/w phy1_parm phy parameter 1 007ch-007fh r/w tw_parm twister parameter 0080h r/w phy2_parm phy parameter 2 0081h - - reserved 0082-0083h r _tdokladdr low address of a tx descriptor with tx dma ok 0084h r/w crc0 power management crc regist er0 for wakeup frame0 0085h r/w crc1 power management crc regist er1 for wakeup frame1 0086h r/w crc2 power management crc regist er2 for wakeup frame2 0087h r/w crc3 power management crc regist er3 for wakeup frame3 0088h r/w crc4 power management crc regist er4 for wakeup frame4 0089h r/w crc5 power management crc regist er5 for wakeup frame5 008ah r/w crc6 power management crc regist er6 for wakeup frame6 008bh r/w crc7 power management crc regist er7 for wakeup frame7 008ch?0093h r/w wakeup0 power management wakeup frame0 (64bit) 0094h?009bh r/w wakeup1 power management wakeup frame1 (64bit) 009ch?00a3h r/w wakeup2 power management wakeup frame2 (64bit) 00a4h?00abh r/w wakeup3 power management wakeup frame3 (64bit) 00ach?00b3h r/w wakeup4 power management wakeup frame4 (64bit) 00b4h?00bbh r/w wakeup5 power management wakeup frame5 (64bit) rtl8139c(l)+ 2001/12/06 rev.1.5 15 00bch?00c3h r/w wakeup6 power management wakeup frame6 (64bit) 00c4h?00cbh r/w wakeup7 power management wakeup frame7 (64bit) 00cch r/w lsbcrc0 lsb of the mask byte of wakeup frame0 within offset 12 to 75 00cdh r/w lsbcrc1 lsb of the mask byte of wakeup frame1 within offset 12 to 75 00ceh r/w lsbcrc2 lsb of the mask byte of wakeup frame2 within offset 12 to 75 00cfh r/w lsbcrc3 lsb of the mask byte of wakeup frame3 within offset 12 to 75 00d0h r/w lsbcrc4 lsb of the mask byte of wakeup frame4 within offset 12 to 75 00d1h r/w lsbcrc5 lsb of the mask byte of wakeup frame5 within offset 12 to 75 00d2h r/w lsbcrc6 lsb of the mask byte of wakeup frame6 within offset 12 to 75 00d3h r/w lsbcrc7 lsb of the mask byte of wakeup frame7 within offset 12 to 75 00d4h-00d7h r/w flash flash memory read/write register 00d8h r/w config5 configuration register 5 00d9h w tppoll transmit priority polling register (c+ mode only) 00dah-00dfh - - reserved 00e0h-00e1h r/w c+cr c+ command register (c+ mode only) 00e2h-00e3h -- - reserved 00e4h-00ebh r/w rdsar receive descriptor start address register (c+ mode only, 256-byte alignment) 00ech r/w etthr c+ early transmit threshold register (c+ mode only) 00edh-00efh - - reserved 00f0h-00f3h r/w fer function event register (cardbus only) 00f4h-00f7h r/w femr function event mask register (cardbus only) 00f8h-00fbh r fpsr function present state register (cardbus only) 00fch-00ffh w ffer/miir function force event register (cardbus only)/mii register (auto-detect or mii mode only) 6.1 receive status register in rx packet header (c mode only) bit r/w symbol description 15 r mar multicast address received: this bit set to 1 indicates that a multicast packet is received. 14 r pam physical address matched: this bit set to 1 indicates that the destination address of this packet matches the value written in id registers. 13 r bar broadcast address received: this bit set to 1 indicates that a broadcast packet is received. bar, mar b it will not be set simultaneously. 12-6 - - reserved 5 r ise invalid symbol error: (100base-tx only) this bit set to 1 indicates that an invalid symbol was encountered during the reception of this packet. 4 r runt runt packet received: this bit set to 1 indicates that the received packet length is smaller than 64 bytes ( i.e. media header + data + crc < 64 bytes ) 3 r long long packet: this bit set to 1 indicates that the size of the received packet exceeds 4k bytes. 2 r crc crc error: when set, indicates that a crc error occurred on the received packet. 1 r fae frame alignment error: when set, indicates that a frame alignment error occurred on this received packet. 0 r rok receive ok: when set, indicates that a good packet is received. rtl8139c(l)+ 2001/12/06 rev.1.5 16 6.2 transmit status register (tsd0-3)(offset 0010h-001fh, r/w, c mode only) the read-only bits (crs, tabt, owc, c dh, ncc3-0, tok, tun) will be cleared by rtl8139c(l)+ when the transmit byte count (bit12-0) in the corresponding tx descriptor is written. it is not affected when software writes to these bits. these reg isters are only permitted to write by double-word access. after softwa re reset, all bits except own bit are reset to ?0?. bit r/w symbol description 31 r crs carrier sense lost: this bit is set to 1 when the carrier is lost during transmission of a packet. 30 r tabt transmit abort: this bit is set to 1 if the transmission of a packet was aborted. this bit is read only, writing to this bit is not affected. 29 r owc out of window collision: this bit is set to 1 if the rtl8139c(l)+ encountered an "out of window" co llision during the transmission of a packet. 28 r cdh cd heart beat: the same as rtl8139(a/b). this bit is cleared in the 100 mbps mode. 27-24 r ncc3-0 number of collision count: indicates the number of collisions encountered during the transmission of a packet. 23-22 - - reserved 21-16 r/w ertxth5-0 early tx threshold: specifies the threshold level in the tx fifo to begin the transmission. when the byte count of the data in the tx fifo reaches this level, (or the fifo cont ains at least one complete packet) the rtl8139c(l)+ will transmit this packet. 000000 = 8 bytes these fields count from 000001 to 111111 in unit of 32 bytes. this threshold must be a voided from exceeding 2k byte. 15 r tok transmit ok: set to 1 indicates that the transmission of a packet was completed successfully and no transmit underrun occurs. 14 r tun transmit fifo underrun: set to 1 if the tx fifo was exhausted during the transmission of a packet. the rtl8139c(l)+can re-transfer data if the tx fifo underruns and can also transmit the packet to the wire successfully even though the tx fifo underruns. that is, when tsd rtl8139c(l)+ 2001/12/06 rev.1.5 17 6.3 dump tally counter command register (dt ccr) (offset 0010h-0017h, r/w, c+ mode only) bit r/w symbol description starting address of the 12 tally counters being dumped to. (64-byte alignment, 64 bytes long) offset of starting address counter description 0 txok 64-bit counter of tx dma ok packets. 8 rxok 64-bit counter of rx ok packets. 16 txerr 64-bit packet counter of tx errors including tx abort, carrier lost, tx underrun (should occur only on jumbo frames), and out of window collision. 24 rxerr 32-bit packet counter of rx errors including crc error packets (should be larger than 8 bytes) and missed packets. 28 misspkt 16-bit counter of missed packets (crc ok) resulted from rx fifo full. 30 fae 16-bit counter of frame alignment error packets (mii mode only) 32 tx1col 32-bit counter of tx ok packets with only 1 collision occurring before tx ok. 36 txmcol 32-bit counter of tx ok packets with more than 1 and less than 16 collisions happened before tx ok. 40 rxokph y 64-bit counter of all rx ok packets with physical addresses matching destination id. 48 rxokbrd 64-bit counter of all rx ok packets with broadcast destination id. 56 rxokmu l 32-bit counter of all rx ok packets with multicast destination id. 60 txabt 16-bit counter of tx abort packets. 62 txundrn 16-bit counter of tx underrun and discard packets (only possible on jumbo frames). 63-6 r/w cntraddr 5-4 - - reserved 3 r/w cmd command: - when set, the rtl8139c(l)+ begins dumping 13 tally counters to the address specified above. - when this bit is reset by rtl8139c(l)+, the dumping is completed. 2-0 - - reserved rtl8139c(l)+ 2001/12/06 rev.1.5 18 6.4 ersr: early rx status register (offset 0036h, r) bit r/w symbol description 7-4 - - reserved 3 r ergood early rx good packet: this bit is set whenever a packet is completely received and the packet is good. this bit is cleared when writing 1 to it. 2 r erbad early rx bad packet: this bit is set whenever a packet is completely received and the packet is bad. writing 1 will clear this bit. 1 r erovw early rx overwrite: this bit is set when the rtl8139c(l)+'s local address pointer is equal to capr. in the early mode, this is different from buffer overflow. it happens that the rtl8139c(l)+ detected an rx error and wanted to fill another packet data from the beginning address of that error packet. writing 1 will clear this bit. 0 r erok early rx ok: the power-on value is 0. it is set when the rx byte count of the arriving packet ex ceeds the rx threshold. after the whole packet is received, the rtl8139c(l)+ will set rok or rer in isr and clear this bit simultaneously. setting this bit will invoke a rok interrupt. 6.5 command register (offset 0037h, r/w) this register is used for issuing comma nds to the rtl8139c(l)+. these commands are issued by setting the corresponding bits for the function. a global software reset along with individual reset and enable/dis able for transmitter and receiver are provided here. bit r/w symbol description 7-5 - - reserved 4 r/w rst reset: setting to 1 forces the rtl8139c(l)+ to a software reset state which disables the transmitter and receiver, reinitializes the fifos, resets the system buffer pointer to the initial value (tx buffer is at tsad0, rx buffer is empty). the values of idr0-5 and mar0-7 and pci configuration space will have no ch anges. this bit is 1 during the reset operation, and is cleared to 0 by the rtl8139c(l)+ when the reset operation is complete. 3 r/w re receiver enable: when set to 1, and the recei ve state machine is idle, the receive machine beco mes active. this bit w ill read back as a 1 whenever the receive st ate machine is active. after initial power-up, software must insure that the r eceiver has completely reset before setting this bit. 2 r/w te transmitter enable: when set to 1, and the transmit state machine is idle, then the transmit state machine becomes active. this bit will read back as a 1 whenever the transmit state machine is active. after initial power-up, software must insure that the transmitter has completely reset before setting this bit. 1 - - reserved 0 r bufe buffer empty: rx buffer empty; there is no packet stored in the rx buffer ring. rtl8139c(l)+ 2001/12/06 rev.1.5 19 6.6 interrupt mask register (offset 003ch-003dh, r/w) this register masks the interrupts that can be generated from the isr. writing a ?1? to the bit enables the corresponding inter rupt. during a hardware reset, all mask bits are cleared. setting a ma sk bit allows the corresponding bit in the isr to cause an inte rrupt. isr bits are always set to 1, however, if the condition is present, regardless of the state of the corresponding mask bit. bit r/w symbol description 15 r/w serr system error interrupt: 1: enable, 0: disable. 14 r/w timeout time out interrupt: 1: enable, 0: disable. 13 r/w lenchg cable length change interrupt: 1: enable, 0: disable. 12 - - reserved 11 - - reserved 10 - - reserved 9 - - reserved 8 r/w _swint software interrupt: 1: enable, 0: disable. 7 r/w _tdu tx descriptor unavailable interrupt: 1: enable, 0: disable. 6 r/w fovw rx fifo overflow interrupt : 1: enable, 0: disable. 5 r/w pun/linkchg packet underrun/link change interrupt: 1: enable, 0: disable. 4 r/w rbo/_rdu rx buffer overflow/rx descri ptor unavailable interrupt: 1: enable, 0: disable. 3 r/w ter tx error interrupt: 1: enable, 0: disable. 2 r/w tok/ti tx (ok) interrupt: 1: enable, 0: disable. 1 r/w rer rx error interrupt: 1: enable, 0: disable. 0 r/w rok rx ok interrupt: 1: enable, 0: disable. rtl8139c(l)+ 2001/12/06 rev.1.5 20 6.7 interrupt status register (offset 003eh-003fh, r/w) this register indicates the source of an interrupt when the inta pin goes active. enabling the corresponding bits in the interr upt mask register (imr) allows bits in this register to produce an interrupt. when an interrupt is active, one of more bits in this register are set to a ?1?. the interrupt status re gister reflects all current pending interrupts, regardless of the state of the corresp onding mask bit in the imr. writing a 1 to any bit will reset that bit, but writing a 0 has no effect. bit r/w symbol description 15 r/w serr system error: set to 1 when the rtl8139c(l)+ signals a system error on the pci bus. 14 r/w timeout time out: set to 1 when the tctr regist er reaches to the value of the timerint register. 13 r/w lenchg cable length change: cable length is changed after receiver is enabled. 12 - - reserved 11 - - reserved 10 - - reserved 9 - - reserved 8 r/w _swint software interrupt: (c+ mode only) i. set to 1 whenever fswint (bit0, offset d9h, tppoll register) is written 1 by software. ii. reserved bit in c mode. 7 r/w _tdu tx descriptor unavailable : (c+ mode only) i. when set, indicates tx descriptor is unavailable. ii. reserved bit in c mode. 6 r/w fovw rx fifo overflow: caused by rbo/rdu, poor pci performance, or overloaded pci traffic. 5 r/w pun/linkchg packet underrun/link change: set to 1 when capr is written but rx buffer is empty, or when link status is changed. 4 r/w rbo/_rdu rx buffer overflow: (c mode only) set when receive (rx) buffer ri ng storage resources have been exhausted. rx descriptor unavailable: (c+ mode only) when set, indicates rx descriptor is unavailable. the mpc (missed packet counter, offset 4ch-4fh) indicates the number of packets discarded after the rx fifo overflow. 3 r/w ter transmit (tx) error: indicates that a packet transmission was aborted, due to excessive collis ions, according to the txrr setting 2 r/w tok/ti transmit (tx) ok: (c mode only) indicates that a packet transm ission is completed successfully. transmit interrupt: (c+ mode only) indicates that the dma of the last descriptor of a tx packet has completed and the last descriptor has been closed. 1 r/w rer receive (rx) error: indicates that a packet has either a crc error or a frame alignment error (fae). the co llided frame will not be recognized as a crc error if the length of this frame is shorter than 16 bytes. 0 r/w rok receive (rx) ok: in normal mode, this indicates the successful completion of a packet reception. in early mode, this indicates that the rx byte count of the arriving pack et exceeds the early rx threshold. rtl8139c(l)+ 2001/12/06 rev.1.5 21 6.8 transmit configuration register (offset 0040h-0043h, r/w) this register defines the transmit configuration for the rtl8139c (l). it controls such functions as loopback, heartbeat, auto transmit padding, programmable interframe gap, fill and drain thresholds, and maximum dma bur st size. the tcr register can only be changed after having set the te (bit2, command register, offset 0037h). bit r/w symbol description 31 - - reserved hardware version id: bit30 bit29 bit28 bit27 bit26 bit23 rtl8139 1 1 0 0 0 0 rtl8139a 1 1 1 0 0 0 rtl8139a-g 1 1 1 0 0 1 rtl8139b 1 1 1 1 0 0 rtl8130 1 1 1 1 1 0 rtl8139c 1 1 1 0 1 0 rtl8139c+ 1 1 1 0 1 1 reserved all other combination 30-26 r hwverid interframe gap time: this field allows adjustment of the interframe gap time below the standards of 9.6 us for 10mbps, 960 ns for 100mbps. the time can be programmed from 9.6 us to 8.4 us (10mbps) and 960ns to 840ns (100mbps). note that any value of ifg [2:0] other than (0,1,1) will violate the ieee 802.3 standard. the formula for the inter frame gap is: ifg[2:0] ifg@100mhz (ns) ifg@10mhz (us) 0 1 1 960 9.6 1 0 0 960 + 8 * 10 9.6 +8 * 0.1 1 0 1 960 + 16 * 10 9.6 + 16 * 0.1 1 1 0 960 + 24 * 10 9.6 + 24 * 0.1 1 1 1 960 + 32 * 10 9.6 + 32 * 0.1 0 0 0 960 + 40 * 10 9.6 + 40 * 0.1 0 0 1 960 + 48 * 10 9.6 + 48 * 0.1 0 1 0 960 + 96 * 10 9.6 + 96 * 0.1 25-24 r/w ifg1, 0 23 r 8139a-g rtl8139a rev.g id = 1. for others, this bit is 0. 22-20 - - reserved. 19 r/w ifg2 interframegap2 18, 17 r/w lbk1, lbk0 loopback test: there will be no packet on the tx+/- lines under the loopback test condition. the loopback function must be independent of the link state. 00 : normal operation 01 : reserved 10 : reserved 11 : loopback mode 16 r/w crc append crc: 0: a crc is appended at the end of a packet 1: no crc appended at the end of a packet 15-11 - - reserved 10-8 r/w mxdma2, 1, 0 max dma burst size per tx dma burst: this field sets the maximum size of transmit dma data bursts according to the following table: 000 = 16 bytes 001 = 32 bytes 010 = 64 bytes rtl8139c(l)+ 2001/12/06 rev.1.5 22 011 = 128 bytes 100 = 256 bytes 101 = 512 bytes 110 = 1024 bytes 111 = 2048 bytes 7-4 r/w txrr tx retry count: these are used to specify additional transmission retries in multiples of 16 (ieee 802.3 csma/cd retry count). if the txrr is set to 0, the transmitter will re-transmit 16 times before aborting due to excessive collisions. if the txrr is set to a value greater than 0, the transmitter will re-transmit a number of times equal to the following formula before aborting: total retries = 16 + (txrr * 16) the ter bit in the isr register or transmit descriptor will be set when the transmission fails and reaches to this specified retry count. 3-1 - - reserved 0 w clrabt clear abort: (c mode only) setting this bit to 1 causes the rtl8139c(l)+ to retransmit the p acket at the last transmitted descriptor when this transmission was aborted. setting this bit is only permitted in the transmit abort state. 6.9 receive configuration register (offset 0044h-0047h, r/w) this register is used to set the receive configuration for the rtl 8139c(l)+. receive properties su ch as accepting error packets , runt packets, setting the receive drai n threshold etc. are controlled here. bit r/w symbol description 31-28 - - reserved 27-24 r/w erth3, 2, 1, 0 early rx threshold bits: these bits are used to select the rx threshold multiplier of the whole packet that has been transferred to the system buffer in early mode when the frame protocol is under the rtl8139c(l)+'s definition. 0000 = no early rx threshold 0001 = 1/16 0010 = 2/16 0011 = 3/16 0100 = 4/16 0101 = 5/16 0110 = 6/16 0111 = 7/16 1000 = 8/16 1001 = 9/16 1010 = 10/16 1011 = 11/16 1100 = 12/16 1101 = 13/16 1110 = 14/16 1111 = 15/16 23-18 - - reserved rtl8139c(l)+ 2001/12/06 rev.1.5 23 17 r/w mulerint multiple early interrupt select: in c mode: when this bit is set, any recei ved packet invokes early interrupt according to the mulint rtl8139c(l)+ 2001/12/06 rev.1.5 24 7 r/w wrap (c mode only) 0: the rtl8139c(l)+ will transfer the rest of the packet data into the beginning of the rx buffer if this packet has not been completely moved into the rx buffer and the transfer has arrived at the end of the rx buffer. 1: the rtl8139c(l)+ will keep moving th e rest of the packet data into the memory immediately after the end of the rx buffer, if this packet has not been completely moved into the rx buffer and the transfer has arrived at the end of the rx buffer. the software driver must reserve at least 1.5k bytes buffe r to accept the remainder of the packet. we assume that the remainde r of the packet is x bytes. the next packet will be moved into the memory from the x byte offset at the top of the rx buffer. this bit is invalid when rx buffer is selected to 64k bytes. 6 r 9356sel eeprom select: this bit reflects what type of eeprom is used. 0: the eeprom used is 9346. 1: the eeprom used is 9356. 5 r/w aer accept error packets: this bit determines if packets with crc error, alignment error and/or collided fragm ents will be accepted or rejected. 0: reject error packets 1: accept error packets 4 r/w ar accept runt packets: this bit allows the r eceiver to accept packets that are smaller than 64 bytes. the packet must be at least 8 bytes long to be accepted as a runt. 0: reject runt packets 1: accept runt packets 3 r/w ab accept broadcast packets: this bit allows the receiver to accept or reject broadcast packets. 0: reject broadcast packets 1: accept broadcast packets 2 r/w am accept multicast packets: this bit allows the receiver to accept or reject multicast packets. 0: reject multicast packets 1: accept multicast packets 1 r/w apm accept physical match packets: this bit allows the receiver to accept or reject physical match packets. 0: reject physical match packets 1: accept physical match packets 0 r/w aap accept physical address packets: this bit allows the receiver to accept or reject packets with a physical destination address. 0: reject packets with a physical destination address 1: accept packets with a phy sical destination address rtl8139c(l)+ 2001/12/06 rev.1.5 25 6.10 9346cr: 93c46 (93c56) command register (offset 0050h, r/w) bit r/w symbol description 7-6 r/w eem1-0 these 2 bits select the rtl8139c(l)+ operating mode. eem1 eem0 operating mode 0 0 normal: rtl8139c(l)+ network/host communication mode. 0 1 auto-load: entering this mode will make the rtl8139c(l)+ load the contents of 93c46 (93c56), as when the rstb signal is asserted. this auto-load operation will take about 2 ms. after it is completed, the rtl8139c(l)+ goes back to the normal mode automatically (eem1 = eem0 = 0) and all the other registers are reset to default values. 1 0 93c46 (93c56) programming: in this mode, both network and host bus master operations are disabled. the 93c46 (93c56) can be directly accessed via bit3-0 which now reflect the states of eecs, eesk, eedi, & eedo pins respectively. 1 1 config. register write enable: before writing to the config0, 1, 3, 4 registers, and bits 13, 12, 8 of bmcr (offset 62h-63h), the rtl8139c(l)+ must be placed in this mode. this will protect the rtl8139c(l)+ configuration from accidental change. 4-5 - - reserved 3 r/w eecs 2 r/w eesk 1 r/w eedi 0 r eedo these bits reflect the state of eecs, eesk, eedi & eedo pins in auto-load or 93c46 (93c56) programming mode. note: eesk, eedi and eedo are invalid during bootrom/flash access. 6.11 configuration register 0 (config 0) (offset 0051h, r/w) bit r/w symbol description 7-3 - - reserved. select boot rom size (autoloaded from eeprom) bs2 bs1 bs0 description 0 0 0 no boot rom 0 0 1 8k boot rom 0 1 0 16k boot rom 0 1 1 32k boot rom 1 0 0 64k boot rom 1 0 1 128k boot rom 1 1 0 unused 1 1 1 unused 2-0 r bs2, bs1, bs0 rtl8139c(l)+ 2001/12/06 rev.1.5 26 6.12 configuration register 1 (config 1) (offset 0052h, r/w) bit r/w symbol description 7-6 r/w leds1-0 refer to led pin definition. these bits initial value com from 93c46/93c56. 5 r/w dvrload driver load: software may use this bit to make sure that the driver has been loaded. writing 1 is 1. writing 0 is 0. when the command register bits ioen, memen, bmen of pci configurati on space are written, the rtl8139c(l)+ will automatically clear this bit. lwake active mode: the lwact and lwptn bits in the config4 register are used to program the output signal of the lwake pin. according to the combination of these two bits, there may be 4 choices of lwake signal, i.e., active high, active low, positive (high) pulse, and negative (low) pulse. the output pulse width is about 150 ms. in cardbus mode applications, lwact and lwptn have no meaning. the default value of each of these two bits is 0, i.e., the default output signal of the lwake pin is an active high signal. lwact lwake output 0 1 0 active high* active low lwptn 1 positive pulse negative pulse 4 r/w lwact * default value. 3 r memmap memory mapping: the operational registers are mapped into pci memory space. 2 r iomap i/o mapping: the operational registers are mapped into pci i/o space. 1 r/w vpd enable vital product data: set to 1 to enable vital product data. the vpd data is stored in 93c46 or 93c56 from within offset 40h-7fh. if this bit is set, the new_cap bit in rtl8139c(l)+?s pci conf iguration space (offset 06h) is set, and the vpd registers are from offset 60h to 67h in the pci configuration space of the rtl8139c(l)+. 0 r/w pmen power management enable: writable only when 93c46cr register eem1=eem0=1 let a denote the new_cap bit (bit 4 of the status register) in the pci configuration space offset 06h. let b denote the cap_ptr register in the pci configuration space offset 34h. let c denote the cap_id (power management) register in the pci configuration space offset 50h. let d denote the power management regi sters in the pci configuration space offset from 52h to 55h. let e denote the next_ptr (power management) register in the pci configuration space offset 51h. pmen setting: - 0: a=b=c=e=0, d is invalid. (assume vpd bit = 0) - 1: a=1, b=50h, c=01h, d is valid, e is valid and depends on whether or not vpd is enabled. rtl8139c(l)+ 2001/12/06 rev.1.5 27 6.13 media status register (offset 0058h, r/w) this register allows configuration of a variety of de vice and phy options, and provides phy status information. bit r/w symbol description 7 r/w txfce/ ldtxfce tx flow control enable: the flow control is valid in full-duplex mode only. this register?s default value comes from 93c46 (93c56). rtl8139c(l)+ remote txfce/ldtxfce ane = 1 nway fly mode r/o ane = 1 nway mode only r/w ane = 1 no nway r/w ane = 0 & full-duplex mode - r/w ane = 0 & half-duplex mode - invalid nway fly mode: nway with flow control capability nway mode only: nway without flow control capability 6 r/w rxfce rx flow control enable: the flow control is enabled in full-duplex mode only. the default value comes from 93c46 (93c56). 5 - - reserved 4 r aux_status aux. power present status: the value of this bit is fixed after each pci reset. 1: aux. power is present 0: aux. power is absent 3 r speed_10 media speed: set when current media is 10 mbps mode. reset when current media is 100 mbps mode. 2 r linkb inverse of link status: 0: link ok 1: link fail 1 r txpf transmit pause flag: set when the rtl8139c(l)+ sends a pause packet. reset when the rtl8139c(l)+ sends a timer done packet. 0 r rxpf receive pause flag: set when the rtl8139c(l)+ is in backoff state because a pause packet has been receive d. reset when pause state is clear. rtl8139c(l)+ 2001/12/06 rev.1.5 28 6.14 configuration register3 (config 3) (offset 0059h, r/w) bit r/w symbol description 7 r gntsel grant select: select the frame?s asserted time after the grant signal has been asserted. the frame and grant are the pci signals. 0: no delay 1: delay one clock from gnt assertion 6 r/w parm_en parameter enable: (these parameters are used in 100mbps mode.) setting to 0 and 9346cr register eem1=eem0=1 enable the phy1_parm, phy2_parm, tw_parm be written via software. setting to 1 will allow parameters to be auto-loaded from the 93c46 (93c56) and disable writing to the phy1_parm, phy2_parm and tw_parm registers via software. the phy1_parm, phy2_parm, and tw_parm can be auto-loaded from eeprom in this mode. the parameter auto-load process is ex ecuted every time when the link is working properly in 100mbps mode. 5 r/w magic magic packet: this bit is valid when the pwen bit of config1 register is set. the rtl8139c(l)+ will assert the pmeb signal to wakeup the operating system when th e magic packet is received. once the rtl8139c(l)+ has been enabled for magic packet wakeup and has been put into an adequate state, it scans all incoming packets addressed to the node for a specific data sequence, which indicates to the controller that this is a magic packet frame. a magic packet frame must also meet the basic requirements: destination address + source address + data + crc the destination address may be the node id of the receiving station or a multicast address, which includes the broadcast address. the specific sequence consists of 16 duplications of 6 byte id registers, with no breaks or interrupts. this sequence can be located anywhere within the packet, but must be pr eceded by a synchronization stream, 6 bytes of ffh. the device will also accep t a multicast address, as long as the 16 duplications of the ieee addr ess match the address of the id registers. if the node id is 11h 22h 33h 44h 55h 66h, then the format of the magic frame format is as follows: destination address + source address + misc + ff ff ff ff ff ff + misc + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + misc + crc 4 r/w linkup link up: this bit is valid when the pwen bit of the config1 register is set. the rtl8139c(l)+, in adequa te power state, will assert the pmeb signal to wakeup the operating system when the cable connection is re-established. rtl8139c(l)+ 2001/12/06 rev.1.5 29 3 r cardb_en card bus enable: set to 1 to enable cardbus related registers and functions. set to 0 to disable cardbus related registers and functions. 2 r clkrun_en clkrun enable: set to 1 to enable clkrun. set to 0 to disable clkrun. 1 r funcregen functions registers enable : cardbus only set to 1 to enable the 4 function registers (function event register, function event mask register, function present state register, and function force event register) for cardbus application. set to 0 to disable the 4 function registers for cardbus application. 0 r fbtben fast back to back enable: set to 1 to enable fast back to back. 6.15 configuration register4 (config 4) (offset 005ah, r/w) bit r/w symbol description 7 r/w rxfifoautoclr clear rx fifo overflow: set to 1, the rtl8139c(l)+ will clear rx fifo overflow automatically. 6 r/w anaoff analog power off: this bit can not be auto-loaded from eeprom (9346 or 9356). 0: normal working state. this is also the power-on default value. 1: turn off the analog power of the rtl8139c(l)+ internally. 5 r/w longwf long wake-up frame: the initial power-on value is 0. this bit does not participate in eeprom autoload, and pci rst# has no effect to this bit. 0: the rtl8139c(l)+ supports up to 8 wake-up frames, each with masked bytes selected from offset 12 to 75. 1: the rtl8139c(l)+ supports up to 5 wake-up frames, each with 16-bit crc algorithm for ms wakeup frame, the low byte of 16-bit crc should be placed at the co rresponding crc register, and the high byte of the 16-bit crc shoul d be placed at the corresponding lsbcrc register. wake-up frames 0 and 1 are the same as above, except that the masked bytes star t from offset 0 to 63. wake-up frames 2 and 3 are merged into one long wake-up frame with masked bytes selected from offset 0 to 127. wake-up frames 4 & 5 and 6 & 7 are merged respectively into two other long wake-up frames. please refer to 7.4 pci po wer management functions for a detailed description. 4 r/w lwpme lanwake vs pmeb: 0: the lwake and pmeb are asserted at the same time. 1: the lwake can only be asserted when the pmeb is asserted and the isolateb is low. in cardbus applications, this bit has no meaning. 3 - - reserved 2 r/w lwptn lwake pattern: please refer to lwact bit in the config1 register. 1 - - reserved 0 r/w pbwakeup pre-boot wakeup: the initial value comes from the eeprom autoload. 0: pre-boot wakeup enabled 1: pre-boot wakeup disabled (suitable for cardbus and minipci application.) rtl8139c(l)+ 2001/12/06 rev.1.5 30 6.16 multiple interrupt select register (offset 005ch-005dh, r/w) if the received packet data is not the fa miliar protocol (ipx, ip, ndis, etc.) to rtl8139c(l)+, rcr rtl8139c(l)+ 2001/12/06 rev.1.5 31 6.19 basic mode control register (offset 0062h-0063h, r/w) bit name description/usage default/attribute 15 reset this bit sets the status and control registers of the phy (register 0062-0074h) in a default state. this bit is self-clearing. 1: software reset 0: normal operation 0, rw 14 - reserved - 13 spd_set this bit sets the network speed in utp mode. this bit?s initial value comes from 93c46 (93c56). 1: 100mbps 0: 10mbps 0, rw 12 auto negotiation enable (ane) this bit enables/disables the n-way auto-negotiation function in utp mode. when set to 1 to enable auto-negotiation, bit13 will be ignored. set to 0 disables auto-negotiation, and bits 13 and 8 will determine the link speed and the da ta transfer mode, respectively. this bit?s initial value comes from 93c46 (93c56). 0, rw 11 mlinkp the initial value comes from eeprom. 1: mlink pin = high mii link ok 0: mlink pin = low mii link ok 0, r 10 mfdupp the initial value comes from eeprom. 1: mfdup pin = high mii interface is in full duplex mode 0: mfdup pin = low mii interface is in full duplex mode 0, r 9 restart auto negotiation this bit allows the nway auto-negotiation function to be reset in utp mode. 1: re-start auto-negotiation 0: normal operation 0, rw 8 duplex mode in utp mode: this bit sets the duplex mode. 1 = full-duplex; 0 = normal operation. this bit?s initial value comes from 93c46 (93c56). if bit12 = 1, read = status write = register value. if bit12=1, ie the chip is in n-way mode, and the link partner is in n-way mode as well, then this bit is a read-only status bit showing n-way results. else, this bit is a command bit to force the chip to run in either full-duplex or half duplex mode. if bit12 = 0, read = write = register value. in mii mode (read only): this bit is a status bit, indicating either the external phy chip is in full-duplex mode or half-duplex mode. 1: indicating that the external phy is in full-duplex mode. 0: indicating that the external phy is in half-duplex mode. 0, rw 7-0 - reserved - rtl8139c(l)+ 2001/12/06 rev.1.5 32 6.20 basic mode status register (offset 0064h-0065h, r) bit name description/usage default/attribute 15 100base-t4 1: enable 100base-t4 support 0: suppress 100base-t4 support. 0, ro 14 100base_tx_ fd 1: enable 100base-tx full duplex support 0: suppress 100base-tx full duplex support 1, ro 13 100base_tx_h d 1: enable 100base-tx half-duplex support 0: suppress 100base-tx half-duplex support 1, ro 12 10base_t_fd 1: enable 10base-t full duplex support 0: suppress 10base-t full duplex support 1, ro 11 10_base_t_hd 1: enable 10base-t half-duplex support 0: suppress 10base-t half-duplex support 1, ro 10-8 - reserved - these two bits are used to select medium mode. the initial values of these 2 bits come from eeprom autoload. medium0 medium mode 0 1 0 autodetect utp medium1 1 mii x 7-6 medium1, medium0 in autodetect mode, the priority is utp > mii. (medium1, medium0) = (0,0), r/w 5 auto negotiation complete 1: auto-negotiation process completed 0: auto-negotiation process not completed 0, ro 4 remote fault 1: remote fault condition detected (cleared on read) 0: no remote fault condition detected 0, ro 3 auto negotiation 1: link had not been experienced fail state 0: link had been experienced fail state 1, ro 2 link status 1: valid link established 0: no valid link established 0, ro 1 jabber detect 1: jabber condition detected 0: no jabber condition detected 0, ro 0 extended capability 1: extended register capability 0: basic register capability only 1, ro this register indicates rtl8139c(l)+?s internal phyceiver status, and medium mode. rtl8139c(l)+ 2001/12/06 rev.1.5 33 6.21 auto-negotiation advertisement register (offset 0066h-0067h, r/w) bit name description/usage default/attribute 15 np next page bit. 0: transmitting the primary capability data page 1: transmitting the protocol specific data page 0, ro 14 ack 1: acknowledge recepti on of link partner capability data word 0, ro 13 rf 1: advertise remote fault detection capability 0: do not advertise remote fault detection capability 0, rw 12-11 - reserved - 10 pause 1: flow control is supported by local node 0: flow control is not supported by local mode the default value comes from eeprom, ro 9 t4 1: 100base-t4 is supported by local node 0: 100base-t4 not supported by local node 0, ro 8 txfd 1: 100base-tx full duplex is supported by local node 0: 100base-tx full duplex not supported by local node 1, rw 7 tx 1: 100base-tx is supported by local node 0: 100base-tx not supported by local node 1, rw 6 10fd 1: 10base-t full duplex supported by local node 0: 10base-t full duplex not supported by local node 1, rw 5 10 1: 10base-t is supported by local node 0: 10base-t not supported by local node 1, rw 4-0 selector binary encoded selector supported by this node. currently only csma/cd <00001> is specified. no other protocols are supported. <00001>, rw - this register indicates nway advertisement info of rtl8139c(l)+?s internal phyceiver. rtl8139c(l)+ 2001/12/06 rev.1.5 34 6.22 auto-negotiation link partner ab ility register (offset 0068h-0069h, r) bit name description/usage default/attribute 15 np next page bit. 0: transmitting the primary capability data page 1: transmitting the protocol specific data page 0, ro 14 ack 1: link partner acknowledges reception of local node?s capability data word. 0, ro 13 rf 1: link partner is indicating a remote fault 0, ro 12-11 - reserved - 10 pause 1: flow control is supported by link partner 0: flow control is not supported by link partner 0, ro 9 t4 1: 100base-t4 is supported by link partner 0: 100base-t4 not supported by link partner 0, ro 8 txfd 1: 100base-tx full duplex is supported by link partner 0: 100base-tx full duplex not supported by link partner 0, ro 7 tx 1: 100base-tx is supported by link partner 0: 100base-tx not supported by link partner 0, ro 6 10fd 1: 10base-t full duplex is supported by link partner 0: 10base-t full duplex not supported by link partner 0, ro 5 10 1: 10base-t is supported by link partner 0: 10base-t not supported by link partner 0, ro 4-0 selector link partner's binary encoded node selector. currently only csma/cd <00001> is specified. <00000>, ro when current medium mode is at utp, this register shows the nway link partner?s ability. 6.23 auto-negotiation expansion register (offset 006ah-006bh, r) this register contains additional status of internal phyceiver for nway auto-negotiation. bit name description/usage default/attribute 15-5 - reserved, this bit is always set to 0. - 4 mlf status indicating if a multiple link fault has occurred. 1: fault occurred 0: no fault occurred. 0, ro 3 lp_np_able status indicating if the link partner supports next page negotiation. 1: supported 0: not supported. 0, ro 2 np_able this bit indicates if the local node is able to send additional next pages. 0, ro 1 page_rx this bit is set when a new li nk code word page has been received. the bit is automatically cleared when the auto-negotiation link partner?s ability register (register 5) is read by management. 0, ro 0 lp_nw_able 1: link partner supports n-way auto-negotiation. 0, ro rtl8139c(l)+ 2001/12/06 rev.1.5 35 6.24 disconnect counter (offset 006ch-006dh, r) this register is valid only when in utp mode. bit name description/usage default/attribute 15-0 dcnt this 16-bit counter increments by 1 for every disconnect event. it rolls over when becomes full. it is cleared to zero by a read command. h'[0000], r 6.25 false carrier sense counter (offset 006eh-006fh, r) this counter provides information required to implement the ?fal se carriers? attribute within the mau managed object class of clause 30 of the ieee 802.3u specification. this register is valid only when in utp mode. bit name description/usage default/attribute 15-0 fcscnt this 16-bit counter increments by 1 for each false carrier event. it is cleared to zero by a read command. h'[0000], r 6.26 nway test register (offset 0070h-0071h, r/w) this register is valid only when in utp mode. bit name description/usage default/attribute 15-8 - reserved - 7 nwlpbk 1: set nway to loopback mode. 0, rw 6-4 - reserved - 3 ennwle 1: led0 pin indicates linkpulse 0, rw 2 flagabd 1: auto-neg experienced ability detect state 0, ro 1 flagpdf 1: auto-neg experienced parallel detection fault state 0, ro 0 flaglsc 1: auto-neg experienced link status check state 0, ro 6.27 rx_er counter (offset 0072h-0073h, r) this register is valid only when in utp mode. bit name description/usage default/attribute 15-0 rxercnt this 16-bit count er increments by 1 for each valid packet received. it is cleared to zero by a read command. h'[0000], r rtl8139c(l)+ 2001/12/06 rev.1.5 36 6.28 cs configuration register (offset 0074h-0075h, r/w) this register is valid only when in utp mode. bit name description/usage default/attribute 15 testfun 1: auto-neg speeds up internal timer 0,wo 14-10 - reserved - 9 ld active low tpi link disable signal. when low, tpi still transmits link pulses and tpi stays in good link state. 1, rw 8 heart beat the heart beat function is only valid in 10mbps mode. 1: heart beat enable 0: heart beat disable. 1, rw 7 jben 1: enable jabber function 0: disable jabber function 1, rw 6 f_link_100 used to login force good link in 100mbps for diagnostic purposes. 1: disable 0: enable. 1, rw 5 f_connect assertion of this bit forces the disconnect function to be bypassed. 0, rw 4 - reserved - 3 con_status this bit indicates the status of the connection. 1: valid connected link detected 0: disconnected link detected 0, ro 2 con_status_en assertion of this bit configures led1 pin to indicate connection status. 0, rw 1 - reserved - 0 pass_scr bypass scramble 0, rw 6.29 low address of a tx descriptor with tx dma ok (offset 0082h-0083h, r) bit r/w symbol description 15-0 r _tdokladdr this is a 16-bit address indicating the low part address of a tx descriptor that has already asserted an interrupt of tx dma complete. 6.30 flash memory read/write register (flash) (offset 00d4h-00d7h, r/w) bit r/w symbol description 31-24 r/w md7-md0 flash memory data bus: these bits set and reflect the state of the md7 - md0 pins, during write and read process respectively. 23-21 - - reserved 20 w romcsb chip select: this bit sets the state of the romcsb pin. 19 w oeb output enable: this bit sets the state of the oeb pin. 18 w web write enable: this bit sets the state of the web pin. 17 w swrwen enable software access to flash memory: 0: disable read/write access to flash memory via software 1: enable read/write access to flas h memory via soft ware and disable the eeprom access during flash memory access via software 16-0 w ma16-ma0 flash memory address bus: these bits set the state of the ma16-0 pins. rtl8139c(l)+ 2001/12/06 rev.1.5 37 6.31 configuration register 5 (config5) (offset 00d8h, r/w) this register, unlike other config registers, is not protected by 93c46 command register. therefore, there is no need to enable config register write prior to writing to config5. bit r/w symbol description 7 - - reserved 6 r/w bwf broadcast wakeup frame: 0: disable broadcast wakeup frame with mask bytes of only did field = ff ff ff ff ff ff. 1: enable broadcast wakeup frame with mask bytes of only did field = ff ff ff ff ff ff. the power-on default value of this bit is 0. 5 r/w mwf multicast wakeup frame: 0: disable multicast wakeup frame with mask bytes of only did field, which is a multicast address. 1: enable multicast wakeup frame with mask bytes of only did field, which is a multicast address. the power-on default value of this bit is 0. 4 r/w uwf unicast wakeup frame: 0: disable unicast wakeup frame with mask bytes of only did field, which is its own physical address. 1: enable unicast wakeup frame with mask bytes of only did field, which is its own physical address. the power-on default value of this bit is 0. 3 r/w fifoaddrptr fifo address pointer: (realtek internal use only to test fifo sram) 0: both rx and tx fifo address pointers are updated in ascending way from 0 and upwards. the initial fifo address pointer is 0. 1: both rx and tx fifo address pointers are updated in a descending method from 1ffh and downwards. the initial fifo address pointer is 1ffh. this bit does not participate in the eeprom auto-load. the fifo address pointers can not be reset, except initial power-on. the power-on default value of this bit is 0. 2 r/w ldps link down power saving mode: 1: disable. 0: enable. when cable is disconnect ed (link down), the analog part will power down itself (phy tx part & part of twister) automatically except phy rx part and part of twister to monitor sd signal in case that cable is re-connected and link should be established again. 1 r/w lanwake lanwake signal enable/disable: 1: enable lanwake signal 0: disable lanwake signal 0 r/w pme_sts pme_status bit: always sticky; can be reset by pci rst# and software. 1: the pme_status bit can be reset by pci reset or by software. 0: the pme_status bit can only be reset by software. config5 register, offset d8h: (sym_err register is changed to config5, the function of sym_err register is no longer supported by rtl8139c.) the 3 bits (bit2-0) are auto-loaded from eeprom config5 byte to rtl8139c config5 register. rtl8139c(l)+ 2001/12/06 rev.1.5 38 6.32 transmit priority polling register (tppoll) (offset 00d9h, r/w, c+ mode only) bit r/w symbol description 7 w hpq high priority queue polling: i. write a 1 to this bit by software to notify the rtl8139c(l)+ that there is high priority packet(s) waiting to be transmitted. ii. the rtl8139c(l)+ will clear th is bit automatically after all high priority packets have been transmitted. iii. writing 0 to this bit has no effect. 6 w npq normal priority queue polling: i. write a 1 to this bit by software to notify the rtl8139c(l)+ that there is a normal priority packet(s) waiting to be transmitted. ii. the rtl8139c(l)+ will clear th is bit automatically after all normal priority packets have been transmitted. iii. writing 0 to this bit has no effect. 5-1 - - reserved 0 w fswint forced software interrupt: i. writing a 1 to this bit will trigger an interrupt, and the _swint bit (bit8, isr, offset3eh-3fh) will set. ii. the rtl8139c(l)+ will clear th is bit automatically after the _swint bit (bit8, isr) is cleared. iii. writing 0 to this bit has no effect. 6.33 c+ command register (c+cr) (offset 00e0h-00e1h, r/w, c+ mode only) this register is the key to entering c+ mode operation before c onfiguring other c+ mode registers and descriptors. this registe r is word access only, byte access to this register has no effect. recommendation to c+ mode programming: en able c+ mode functions in c+cr regist er first, => enable transmit/receive in command register (offset 37h), => configure other related re gisters (ex. descriptor start address, tcr, rcr, ?). bit r/w symbol description 15-9 - - reserved 8 - - reserved (home lan enable, always 0) 7 - - reserved 6 r/w rxvlan receive vlan de-tagging enable: (in c+ mode) 1: enable; 0: disable 5 r/w rxchksum receive checksum offload enable: (in c+ mode) 1: enable; 0: disable 4 r/w dac pci dual address cycle enable: (in c+ mode) 1: enable; 0: disable when set, the rtl8139c(l)+ w ill perform tx/rx dma using pci dual address cycle only when the high 32-bit buffer address is not equal to 0. 3 r/w mulrw pci multiple read/write enable: (in c+ mode) 1: enable; 0: disable 2 - - - 1 r/w c+rx receive enable: (in c+ mode) 1: enable; 0: disable 0 r/w c+tx transmit enable: (in c+ mode) 1: enable; 0: disable rtl8139c(l)+ 2001/12/06 rev.1.5 39 6.34 r eceive descriptor start address register (rdsar) (offset 00e4h-00ebh, r/w, c+ mode only) bit r/w symbol description 63-0 r/w rdsa receive descriptor start address: (64-bit address) bit[31:0]: offset e7h-e4h, low 32-bit address. bit[63:32]: offset ebh-e8h, high 32-bit address. 6.35 early transmit threshold register (etthr) (offset 00ech, r/w, c+ mode only) bit r/w symbol description test mode: for rtl8139c(l)+ to operate normally, please set to ?normal? mode. the test1-3 modes are for testing only. bit[7:6] mode description (0,0) normal rtl8139c(l)+ operation mode (0,1) test1 test mode 1: to test waveform?s rise time and fall time. (1,0) test2 test mode 2: internal test signals output from boot rom interface. (1,1) test3 test mode 3: receive signals output from boot rom interface. 7-6 r/w testmode 5-0 r/w etth early tx threshold: 1. specifies the threshold level in the tx fifo to begin the transmission. when the byte count of the data in the tx fifo reaches this level, (or the fifo contains at least one complete packet) the rtl8139c(l)+ w ill transmit this packet. 000000 = 8 bytes 2. these fields count from 000001 to 111111 in unit of 32 bytes. 3. this threshold must be avoided from exceeding 2k byte. rtl8139c(l)+ 2001/12/06 rev.1.5 40 6.36 function event register (offset 00f0h-00f3h, r/w) bit r/w symbol description 31-16 - - reserved 15 r/w intr interrupt: set to 1 when intr field in the function force event register is set. writing a 1 may clear this bit. writing a 0 has no effect. this bit must not be affected by rst# pin and software reset. 14-5 - - reserved 4 r/w gwake general wakeup: set to 1 when the gwake field in the function present state register changes its stat e from 0 to 1. this bit can also be set when the gwake bit of the function force register is set. writing a 1 may clear this bit. writing a 0 has no effect. this bit can not be affected by the rst#. 3-0 - - reserved this register is valid only when card_en=1 (b it3, config3) and funcregen=1 (bit1, config3). the function event (offset f0h), function event mask (offset f4h), function present state (offset f8h), and function force event (offset fch) registers have some corresponding fields with the same names. the gwake and intr bits of these registers reflect the wake-up event signaled on the sctcschg pin. the operation of cstcschg pin is similar to pme# pin except that the cstcschg pin is asserted high. rtl8139c(l)+ 2001/12/06 rev.1.5 41 6.37 function event mask register (offset 00f4h-00f7h, r/w) bit r/w symbol description 31-16 - - reserved 15 r/w intr interrupt mask: when cleared (0), setting of the intr bit in either the function present state register or the function event register will neither cause assertion of the int# signal while the cardbus pc card interface is powered up, nor cause a system wakeup (cstschg) while the interface is powered off. setting this bit to 1 enables the intr bit in both the function present state register and the function event register to generate the int# signal (and the system wakeup if the corresponding wkup field in this function event mask register is also set). this bit is not affected by rst#. 14 r/w wkup wakeup mask: when cleared (0), the wakeup function is disabled, i.e., the setting of this bit in the function event register will not assert the cstschg signal. setting this bit to 1 enables the fields in the function event register to assert the cstschg signal. this bit is not affected by rst#. 13-5 - - reserved 4 r/w gwake general wakeup mask: when cleared (0), setting this bit in the function event register will not cause the cstschg pin to assert. setting this bit to 1 enables the gwake field in the function event register to assert cstschg pin if bit14 of this register is also set. this bit is not affected by rst#. 3-0 - - reserved this register is valid only when card_en=1 (b it3, config3) and funcregen=1 (bit1, config3). rtl8139c(l)+ 2001/12/06 rev.1.5 42 6.38 function present state register (offset 00f8h-00fbh, r) bit r/w symbol description 31-16 - - reserved 15 r intr interrupt: this bit is set when one of the isr register bits has been set to 1 and remains set (1), until all of the isr register bits have been cleared. it is not affected by rst#. 14-5 - - reserved 4 r gwake general wakeup: this bit reflects the current state of the wakeup event(s), and is just like the pme_ status bit of the pmcsr register. this bit remains set (1) until the pme_status bit of the pmcsr register is cleared. it is not affected by rst#. 3-0 - - reserved this register is valid only when card_en=1 (b it3, config3) and funcregen=1 (bit1, config3). this read-only register reflects th e current state of the function. rtl8139c(l)+ 2001/12/06 rev.1.5 43 6.39 function fo rce event register/mii register (offset 00fch-00ffh, w)/(offset 00fch, r/w) bit r/w symbol description 31 r mii 1: the rtl8139c(l)+ processes current network traffic through its external mii interface. 0: the rtl8139c(l)+ processes current network traffic through its utp interface (via its embedded phyceiver). 30 r utp 1: the rtl8139c(l)+ processes current network traffic through its utp interface (via its embedded phyceiver). 0: the rtl8139c(l)+ processes current network traffic through its external mii interface. 29-28 - - reserved 27 r/w mdm management data mode: setting this bit indicates that the mdio pin is output, and the state of the mdio pin reflects with the mdo bit. when this pin is reset, the mdio pin is input. the mdi bit reflects the state of the mdio pin. the default value is "0". 26 r/w mdo mii management data-out: used by the rtl8139c+ to write data to the mdio pin. 25 r/w mdi mii management data-in: used by the rtl8139c+ to read data from the mdio pin. 24 r/w mdc management data clock: this bit reflects the state of the mdc pin. 23-16 - - reserved 15 w intr interrupt: writing a 1 sets the intr bit in the function event register. however, the intr b it in the function present state register is not affected and continue s to reflect the current state of the isr register. writing a 0 to this bit has no effect. 14-5 - - reserved 4 w gwake general wakeup: setting this bit to 1, sets the gwake bit in the function event register. however, the gwake bit in the function present state register is not aff ected and continues to reflect the current state of the wakeup request. writing a 0 to this bit has no effect. 3-0 - - reserved this register (except bits 31-30, and bits 27-24) is valid only when card_en=1 (bit3, config3) and funcregen=1 (bit1, config3). the bit31-30, and bit27-24 are valid only when funcregen=0 (bit1, config3). mii register is valid (i.e. bits 31, 30, 27-24, are valid) only when current medium select is set to auto-dectect or mii mode. bit7, and bit6 indicate current network traffic path that the rtl8139c(l)+ uses. when funcregen=1 (bit1, config3) in cardbus mode, these 2 bits are reserved bits. bits 3-0 provide a path for software to access the mii registers of an extern al phyceiver. when funcregen=1 (bit1, config3) in cardbus mode, these 4 bits are reserved bits. rtl8139c(l)+ 2001/12/06 rev.1.5 44 7. eeprom contents (93c46 or 93c56) the 93c46 is a 1k-bit eeprom (the 93c56 is a 2k-bit eeprom). although it is actually addressed by words, its contents are listed below by bytes for convenience. after the valid duration of the rstb pin or auto-load command in 9346cr, the rtl8139c(l) performs a series of eeprom read opera tions from the 93c46 (93c56) address 00h to 31h. it is suggested to obtain rea ltek approval before changing the default settings of the eeprom. bytes contents description 00h 29h 01h 81h these 2 bytes contain the id code word for the rtl8139c(l)+. the rtl8139c(l)+ will load the contents of the eeprom into the correspondi ng location if the id word (8129h) is correct, otherwise, the vendor id and device id of the pci configuration space are hex 10ec and 8129 respectively. 02h-03h vid pci vendor id, pci conf iguration space offset 00h-01h. 04h-05h did pci device id, pci conf iguration space offset 02h-03h. 06h-07h svid pci subsystem vendor id, pci configuration space offset 2ch-2dh. 08h-09h smid pci subsystem id, pci c onfiguration space offset 2eh-2fh. 0ah mngnt pci minimum grant timer, pci configuration space offset 3eh. 0bh mxlat pci maximum latency timer, pci configuration space offset 3fh. bits 7-6 map to bits 7-6 of the media status register (msr), bits 5, 4, 3, 2, 0 map to bits 13, 12, 8, 3, 2 of the basic mode control register (bmcr). if the network speed is set to auto-detect mode (i.e. nway mode), then bit 1=0 means the local rtl8139c(l)+ supports flow control (ieee 802.3x). in th is case, bit 10=1 in auto-negotiation advertisement register (offset 66h-67h). bit 1=1 means the local rtl8139c(l)+ does not support flow control. in this case, bit 10=0 in auto-negotiation advertisement. th is is because that there are nway switch hubs which keep sending flow control pause packets for no reason, if the link partner supports nway flow control. bit 7 6 5 4 3 2 1 0 load-to txfce/l dtxfce (bit7, msr) rxfc e (bit6, msr) spd_set (bit13, bmcr ) ane (bit12, bmcr) mlinkp (bit3, bmcr ) mfdupp (bit2, bmcr ) - duplex mode (bit8, bmcr) 0ch msrbmcr 0dh config3 rtl8139c(l)+ configuration regi ster 3, operational register offset 59h. 0eh-13h ethernet id after auto-load command or hardwa re reset, the rtl8139c(l)+ loads the ethernet id to idr0-idr5 of the rtl8139c(l)+'s i/o registers. 14h config0 rtl8139c(l)+ configuration regist er 0, operational registers offset 51h. 15h config1 rtl8139c(l)+ configuration regist er 1, operational registers offset 52h. 16h-17h pmc reserved. do not change this field without realtek approval. power management capabilities. pci c onfiguration space address 52h and 53h. 18h - reserved 19h config4 reserved. do not change this field without realtek approval. rtl8139c(l)+ configuration register 4, operational registers offset 5ah. 1ah-1dh phy1_parm_u reserved. do not change this field without realtek approval. phy parameter 1-u for rtl8139c. operational registers of the rtl8139c(l)+ are from 78h to 7bh. 1eh phy2_parm_u reserved. do not change this field without realtek approval. phy parameter 2-u for rtl8139c. operational register of the rtl8139c(l)+ is 80h. rtl8139c(l)+ 2001/12/06 rev.1.5 45 do not change this field without realtek approval. 1fh config_5 bit5, 3: reserved. bit7: medium1 at bmsr. medium select bit1. bit6: medium0 at bmsr. medium select bit0. bit5: pci multi-function enable. set to 1: enable pci multi-functi on capability. the rtl8139c+ can be a multi-function device with an external pci device at slave mode on the same pcb, ex. an external software modem. set to 0: disable pci multi-function capability. bit4: reserved bit2: link down power saving mode: set to 1: disable. set to 0: enable. when cable is disconnected(link down), the analog part will power down itself (phy tx part & part of twister) automatically except phy rx part and part of twister to monitor sd signal in case that cable is re-connected and link should be established again. bit1: lanwake signal enable/disable set to 1: enable lanwake signal. set to 0: disable lanwake signal. bit0: pme_status bit property set to 1: the pme_status bit can be reset by pci reset or by software if d3cold_support_pme is 0. if d3cold_support_pme=1, the pme_status bit is a sticky bit. set to 0: the pme_status bit is always a sticky bit and can only be reset by software. 20h-23h tw_parm_u reserved. do not change this field without realtek approval. twister parameter u for rtl8139c. operational registers of the rtl8139c(l)+ are 7ch-7fh. 24h-27h tw_parm_t reserved. do not change this field without realtek approval. twister parameter t for rtl8139c. operational registers of the rtl8139c(l)+ are 7ch-7fh. 28h-2bh phy1_parm_t reserved. do not change this field without realtek approval. phy parameter 1-t for rtl8139c. operational registers of the rtl8139c(l)+ are from 78h to 7bh. 2ch phy2_parm_t reserved. do not change this field without realtek approval. phy parameter 2-t for rtl8139c. operational register of the rtl8139c(l)+ is 80h. 2dh-2fh - reserved. 30h-31h cispointer reserved. do not change this field without realtek approval. cis pointer. 32h-33h checksum reserved. do not change this field without realtek approval. checksum of the eeprom content. 34h-3eh - reserved. do not change this field without realtek approval. 3fh pxe_para reserved. do not change this field without realtek approval. pxe rom code parameter. 40h-7fh vpd_data vpd data field. offset 40h is the start address of the vpd data. 80h-ffh cis_data cis data field. offset 80h is the start address of the cis data. (93c56 only). rtl8139c(l)+ 2001/12/06 rev.1.5 46 7.1 summary of eeprom registers offset name type bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00h-05h idr0 ? idr5 r/w* 51h config0 r - - - - bs2 bs1 bs0 w * - - - - - - - - 52h config1 r leds1 leds0 dvrload lwact memmap iomap vpd pmen w * leds1 leds0 dvrload lwact - - vpd pmen 58h r txfce rxfce - - - - w * txfce rxfce - - - - 63h r - - spd_set ane - - - fudup msrbmcr w * - - spd_set ane - - - fudup 59h config3 r gntdel parm_en magic linkup cardb_en clkru n_en funcreg en fbtben w * - parm_en magic linkup - - - - 5ah config4 r/w * rxfifo autoclr - - lwpme - lwptn - - 78h-7bh phy1_parm r/w ** 32 bit read write 7ch-7fh tw1_parm tw2_parm r/w ** 32 bit read write 32 bit read write 80h phy2_parm r/w ** 8 bit read write d8h config5 r/w * - - - - - ldps lanwa ke pme_st s e0h c+cr r/w - - - dac - - - - * the registers marked with type = w * can be written only if bits eem1=eem0=1. ** the registers marked with type = w ** can be written only if bits eem1=eem0=1 and config3 rtl8139c(l)+ 2001/12/06 rev.1.5 47 8. pci configuration space registers 8.1 pci bus interface the rtl8139c(l)+ implements the pci bus interface as defined in the pci local bus specifications rev. 2.2. when internal registers are being accessed, the rtl8139c(l)+ acts as a pci targ et (slave mode). when accessi ng host memory for descriptor or packet data transfer, the rtl8139c(l)+ acts as a pci bus master. all of the required pins and functions are implemented in the rtl8139c(l)+ as well as the optional pin, intab for support of interrupt requests is implemented as well. for more information, refer to the pci lo cal bus specifications rev. 2.2, december 18, 1998. 8.1.1 byte ordering the rtl8139c(l)+ is permanently configur ed to order the bytes of data on the ad[31:0] bus to conform to little-endian ordering. byte ordering affects bus mastered packet data transf ers in 32-bit mode. register information remains bit aligned (i. e. ad[31] maps to bit 31 in any register space, ad[0] maps to b it 0, etc.) when registers are accessed with 32-bit operations. bus mastered transfers of buffer descriptor information also remain bit aligned. byte orientation for receive and tr ansmit data and descriptors in sy stem memory are done as follows: 31 24 23 16 15 8 7 0 byte 3 byte 2 byte 1 byte 0 c/be[3] (msb) c/be[2] c/be[1] c/be[0] (lsb) little-endian byte ordering 8.1.2 interrupt control interrupts are performed by asynchronously asserting the intab pin. this pin is an open drain output. the source of the interrupt can be determined by reading the interrupt status register (isr). one or more bits in the isr will be set, denoting a ll currently pending interrupts. mask ing of specific interrupts can be accomplished by using the interrupt mask register (imr). this allows the system to defe r interrupt processing as needed. 8.1.3 latency timer the pci latency timer described in mxlat defines the maximum number of bus clocks that the device will hold the bus. once the device gains control of the bus and issues frameb, the latency timer will be gin counting down. if gntb is deasserted before the rtl8139c(l)+ has finished with the bus, the device will maintain ownershi p of the bus until the timer reaches zero (or has finished the bus transfer). rtl8139c(l)+ 2001/12/06 rev.1.5 48 8.1.4 32-bit data operation the rtl8139c(l)+ supports only 32-bit data access. 8.1.5 64-bit addressing the rtl8139c(l)+ supports 64-bit addressing (dual address cycle) as a bus master for transferring descriptor and packet data information. this mode can be enabled or disabled through software. 8.2 bus operation 8.2.1 target read a target read operation starts with the system generating frameb, address, and either an io read (0010b) or memory read (0110b) command. if the 32-bit address on the address bus matches the io address range specified in ioar (for i/o reads) or the memory address range specified in mem (for memory reads), the rtl8139c(l)+ will generate devselb 2 clock cycles later (medium speed). the system must tri-state the address bus, and conve rt the c/be bus to byte enables, after the address cycle. o n the 2nd cycle after the assertion of devselb, all 32-bits of data and trdyb will become valid. if irdyb is asserted at that time, trdyb will be forced high on the next clock for 1 cycle, and then tri-stated. if frameb is asserted beyond the assertion of irdyb, the rtl8139c(l)+ will s till make data available as described above, but will also issue a disconnect. that is, it will assert th e stopb signal with trdyb. stopb will remain asserted until frameb is detected as deasserted. target read operation rtl8139c(l)+ 2001/12/06 rev.1.5 49 8.2.2 target write a target write operation starts with the system genera ting frameb, address, and command (0011b or 0111b). if the upper 24 bits on the address bus match ioar (for i/o reads) or mem (for memory reads), the rtl8139c (l)+ will generate devselb 2 clock cycles later. on the 2nd cycle af ter the assertion of devselb, the device w ill monitor the irdyb signal. if irdyb is asserted at that time, the rtl8139c(l)+ will assert trdyb. on the next clock the 32-bit double word will be latched in, and trdyb will be forced high for 1 cycle and then tri-stat ed. target write operations must be 32-bits wide. if frameb is asserted beyond the assertion of irdyb, the rtl8139c(l)+ will still latch the first double word as described above, but will also issue a disconnect. that is, it will assert the stopb signal with trdyb. stopb will remain asserted until frameb is detected as deasserted. target write operation rtl8139c(l)+ 2001/12/06 rev.1.5 50 8.2.3 master read a master read operation starts with the rtl8139c(l)+ asserti ng reqb. if gntb is asserted within 2 clock cycles, frameb, address, and command will be generated 2 clocks after reqb (address and frameb for 1 cycle only). if gntb is asserted 3 cycles or later, frameb, address, and command will be generated on the clock following gntb. the device will wait for 8 cycles for the assertion of devselb. if devselb is not asserted within 8 clocks, the device will issue a master abort by asserting fram eb high for 1 cycle, and irdyb will be forced high on the following cycle. both signals will become tri-state on the cycle following their deassertion. on the clock edge after the generation of address and command, the address bus will become tri-state, and the c/be bus will contain valid byte enables. on the clock edge after frameb was asserted, irdyb will be asserted (and frameb will be deasserted if this is to be a single read operation). on the clock where both trdyb a nd devselb are detected as asserted, data will be latched in (and the byte enables will change if necessary). this will con tinue until the cycle fo llowing the deassertio n of frameb. on the clock where the second to last read cycle occurs, frameb will be forced high ( it will be tri-stated 1 cycle later). on t he next clock edge that the device detects trdyb asserted, it will fo rce irdyb high. it, too, will be tri-stated 1 cycle later. th is will conclude the read operation. the rtl8139c(l)+ will never force a wait state during a read operation. master read operation rtl8139c(l)+ 2001/12/06 rev.1.5 51 8.2.4 master write a master write operation starts with the rtl8139c(l)+ asserti ng reqb. if gntb is asserted within 2 clock cycles, frameb, address, and command will be generated 2 clocks after reqb (address and frameb for 1 cycle only). if gntb is asserted 3 cycles or later, frameb, address, and command will be generated on the clock following gntb. the device will wait for 8 cycles for the assertion of devselb. if devselb is not asserted within 8 clocks, the device will issue a master abort by asserting frameb high for 1 cycle. irdyb will be forced high on the following cycle. both signals will become tri-state on the cycle following their deassertion. on the clock edge after the generation of address and command, the data bus will become valid, and the c/be bus will contain valid byte enables. on the clock edge after frameb was assert ed, irdyb will be asserted (and frameb will be deasserted if this is to be a single read operation). on the clock where both trdyb and devselb are detected as asserted, valid data for the next cycle will become available (and the byte enables will change if necessary). this will continue un til the cycle following the deassertion of frameb. on the clock where the second to last write cycle occurs, frameb will be forced high (it will be tri-stated 1 cycle later). on the next clock edge that the device detects trdyb asserted, it w ill force irdyb high. it, too, will be tri-stated 1 cycle later . this will conclude the write operati on. the rtl8139c(l)+ will never force a wait state during a write operation. master write operation 8.2.5 configuration access configuration register accesses are similar to target reads and writes in that they ar e single data word transfers and are init iated by the system. for the system to initiate a configuration access, it must also gene rate idsel as well as the correct command (1010b or 1011b) during the address phase. th e rtl8139c(l)+ will respond as it does dur ing target operati ons. configuration reads must be 32-bits wide, but writes may access individual bytes. 8.3 packet buffering the rtl8139c(l)+ incorporates two independent fifos for tran sferring data to/from the syst em interface and from/to the network. the fifos, providing temporary storage of data freeing the host system from the real-time demands of the network. the way in which the fifos are emptied and filled is controlled by the fifo threshold values in the transmit configuration and receive configuration regi sters. these values determine how full or empty the fifos must be before the device requests the bus. additionally, there is a threshold value that determines how full the transmit fifo must be before beginning transmission. once the rtl8139c(l)+ requests the bus, it will attempt to empt y or fill the fifos as allo wed by the respective mxdma settings in the transmit configuration and receive configur ation registers. the rtl8139c(l)+ uses two diffe rent modes of buffer management for transm ission and reception of data. these two modes are c and c+. rtl8139c(l)+ 2001/12/06 rev.1.5 52 8.3.1 transmit buffer manager c mode: the host cpu initiates a transmit by storing an entire packet of data in one of the descriptors in the main memory, and those descriptors should be double-word alignment. when the entire pack et has been transferred to the tx buffer, the rtl8139c(l)+ is instructed to move the data from the tx buffer to the intern al transmit fifo in pci bus master mode. when the transmit fifo contains a complete packet or is filled to the programmed threshold level, the rtl 8139c(l)+ begins packet transmission. please refer to the realtek rtl8139 series progr amming guide for detailed information. c+ mode: the buffer management scheme used on the rtl8139c(l)+ allows quick, simple and efficient use of the frame buffer memory. the buffer management scheme uses separate buffers and descriptors for packet informa tion. this allows effective transfers of data to the transmit buffer manager by simply transferring the descriptor information to the transmit queue. the tx buffer manager dmas packet data from pci memory space and places it in th e 2kb transmit fifo, and pulls data from the fifo to send to the tx mac. multiple packets may be presen t in the fifo, allowing packets to be transmitted with minimum interframe gap. the way in which the fifo is emptied and f illed is controlled by the etth (early transmit threshold) and rxfth (rx fifo threshold) values. add itionally, once the rtl8139c(l)+ requests the bus, it will attempt to fill the fifo as allowed by the mxdma setting. the tx buffer manager process also supports priority queuing of tr ansmit packets. it handles this by drawing from four separate descriptor lists to fill the internal fifo. if packets are availa ble in the higher priority queues, they will be loaded into th e fifo before those of lower priority. 8.3.2 receive buffer manager c mode: the incoming packet is placed in the rx fifo of the rtl8139c(l)+. conc urrently, the rtl8139c(l )+ performs address filtering of multicast packets according to its hash algorithms. when the amount of data in the rx fifo reach es the level defin ed in the receive configuration re gister (rcr), the rtl8139c(l)+ re quests the pci bus to begin tran sferring the data to the rx buffer in pci bus master mode. the rx buffer should be pre-allocated and indicated in rcr befo re packet reception. all received packets stored in rx buffer, including rx header and 4-byte crc, are double-word alignment. i.e., each received packet is placed at next available double-wo rd alignment address after the last receive d packet in rx buffer. please refer to t he realtek rtl8139 series programming guide for detailed information. c+ mode: the rx buffer manager uses the same buffer management sche me as used for transmits. the rx buffer manager retrieves packet data from the rx mac and places it in the 2kb receive data fifo, and pulls da ta from the fifo for dma to pci memory space. similar to the transmit fi fo, the receive fifo is controlled by the fi fo threshold value in rxfth. this value determines the number of long words written into the fifo from the mac unit before a dma request for system memory occurs. once the rtl8139c(l)+ gets the bus, it will continue to transfer the long words from the fifo until the data in the fif o is less than one long word, or has reached the end of the packet, or the max dma bur st size is reached , as set in mxdma. 8.3.3 packet recognition the rx packet filter and recognition logic allows software to control which packet s are accepted, based on destination address and packet type. address rec ognition logic includes support for broadcast, multi cast hash, and unicast addresses. the packet recognition logic includes support for wol, pa use, and programmable pattern recognition. rtl8139c(l)+ 2001/12/06 rev.1.5 53 8.4 pci configuration space table no. name type bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00h vid r vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 01h r vid15 vid14 vid13 vid12 vid11 vid10 vid9 vid8 02h did r did7 did6 did5 did4 did3 did2 did1 did0 03h r did15 did14 did13 did12 did11 did10 did9 did8 04h command r 0 perrsp 0 mwien 0 bmen memen ioen w - perrsp - mwien - bmen memen ioen 05h r 0 0 0 0 0 0 fbtben serren w - - - - - - - serren 06h status r fbbc 0 0 newcap 0 0 0 0 07h r dperr sserr rmabt rtabt stabt dst1 dst0 dpd w dperr sserr rmabt rtabt stabt - - dpd 08h revision id r 0 0 0 0 0 0 0 0 09h pifr r 0 0 0 0 0 0 0 0 0ah scr r 0 0 0 0 0 0 0 0 0bh bcr r 0 0 0 0 0 0 1 0 0ch cls r/w 0 0 0 0 0 0 0 0 0dh ltr r ltr7 ltr6 ltr5 ltr4 ltr3 ltp2 ltr1 ltr0 w ltr7 ltr6 ltr5 ltr 4 ltr3 ltp2 ltr1 ltr0 0eh htr r 0 0 0 0 0 0 0 0 0fh bist r 0 0 0 0 0 0 0 0 10h ioar r 0 0 0 0 0 0 0 ioin w - - - - - - - - 11h r/w ioar15 ioar14 ioar13 ioar12 ioar11 ioar10 ioar9 ioar8 12h r/w ioar23 ioar22 ioar21 ioar20 ioar19 ioar18 ioar17 ioar16 13h r/w ioar31 ioar30 ioar29 ioar28 ioar27 ioar26 ioar25 ioar24 14h memar r 0 0 0 0 0 0 0 memin w - - - - - - - - 15h r/w mem15 mem14 mem13 mem12 mem11 mem10 mem9 mem8 16h r/w mem23 mem22 mem21 mem20 mem19 mem18 mem17 mem16 17h r/w mem31 mem30 mem29 mem28 mem27 mem26 mem25 mem24 18h-27h reserved 28h-2bh cisptr cardbus cis pointer 2ch svid r svid7 svid6 svid5 svid4 svid3 svid2 svid1 svid0 2dh r svid15 svid14 svid13 svid12 svid11 svid10 svid9 svid8 2eh smid r smid7 smid6 smid5 smid4 smid3 smid2 smid1 smid0 2fh r smid15 smid14 smid13 smid12 smid11 smid10 smid9 smid8 30h bmar r 0 0 0 0 0 0 0 bromen w - - - - - - - bromen 31h r bmar15 bmar14 bmar13 bmar12 bmar11 0 0 0 w bmar15 bmar14 bmar13 bmar12 bmar11 - - - 32h r/w bmar23 bmar22 bmar21 bmar20 bmar19 bmar18 bmar17 bmar16 33h r/w bmar31 bmar30 bmar29 bmar28 bmar27 bmar26 bmar25 bmar24 34h cap_ptr r 0 1 0 1 0 0 0 0 rtl8139c(l)+ 2001/12/06 rev.1.5 54 35h-3bh reserved 3ch ilr r/w irl7 ilr6 ilr5 ilr4 ilr3 ilr2 ilr1 ilr0 3dh ipr r 0 0 0 0 0 0 0 1 3eh mngnt r 0 0 1 0 0 0 0 0 3fh mxlat r 0 0 1 0 0 0 0 0 40h?4fh reserved 50h pmid r 0 0 0 0 0 0 0 1 51h nextptr r 0 0 0 0 0 0 0 0 52h pmc r aux_i_b1 aux_i_b0 dsi reserved pmeclk version 53h r pme_d3 cold pme_d3 hot pme_d2 pme_d1 pme_d0 d2 d1 aux_i_b2 54h pmcsr r 0 0 0 0 0 0 power state w - - - - - - power state 55h r pme_status - - - - - - pme_en w pme_status - - - - - - pme_en 56h?5fh reserved 60h vpdid r 0 0 0 0 0 0 1 1 61h nextptr r 0 0 0 0 0 0 0 0 62h flag vpd address r/w vpdaddr 7 vpdaddr 6 vpdadd r5 vpdadd r4 vpdadd r3 vpdadd r2 vpdadd r1 vpdadd r0 63h r/w flag vpdaddr 14 vpdadd r13 vpdadd r12 vpdadd r11 vpdadd r10 vpdadd r9 vpdadd r8 64h r/w data7 data6 data5 data 4 data3 data2 data1 data0 65h r/w data15 data14 data13 data 12 data11 data10 data9 data8 66h r/w data23 data22 data21 data 20 data19 data18 data17 data16 67h vpd data r/w data31 data30 data29 data 28 data27 data26 data25 data24 68h-ffh reserved rtl8139c(l)+ 2001/12/06 rev.1.5 55 8.5 pci configuration space functions the pci configuration space is intended for configuration, initialization, and catastrophic error handling functions. the functions of the configuration space fo r the rtl8139c(l)+ ar e described below. vid: vendor id. this field will be set to a value corresponding to pci vendor id in the external eeprom. if there is no eeprom, this field will default to a value of 10e ch which is realtek semiconductor's pci vendor id. did: device id. this field will be set to a value corresponding to pci device id in the external eeprom. if there is no eeprom, this field will default to a value of 8129h. command: the command register is a 16-bit register used to provide coarse control over a device's ability to generate and respond to pci cycles. bit symbol description 15-10 - reserved 9 fbtben fast back-to-back enable: config3 rtl8139c(l)+ 2001/12/06 rev.1.5 56 status: the status register is a 16-bit register us ed to record status information for pci bus related events. reads to this register behave normally. writes are slightly different in that bits can be reset, but not set. bit symbol description 15 dperr detected parity error: when set indicates that the rtl8139c(l)+ detected a parity error, even if parity error handling is disabled in command register perrsp bit. 14 sserr signaled system error: when set indicates that the rtl8139c(l)+ asserted the system error pin, serrb. writing a 1 clears this bit to 0. 13 rmabt received master abort: when set indicates that the rtl8139c(l)+ terminated a master transaction with master abort. writing a 1 clears this bit to 0. 12 rtabt received target abort: when set indicates that the rtl8139c(l)+ master transaction was terminated due to a target abort. writing a 1 clears this bit to 0. 11 stabt signaled target abort: set to 1 whenever the rtl8139c(l)+ terminates a transaction with target abort. writing a 1 clears this bit to 0. 10-9 dst1-0 device select timing: these bits encode the timing of devselb. they are set to 01b (medium), indicating the rtl8139c(l)+ will assert devselb two clocks after frameb is asserted. 8 dpd data parity error detected: this bit sets when the following conditions are met: ? the rtl8139c(l)+ asserts parity error(perrb pin) or it senses the assertion of perrb pin by another device. ? the rtl8139c(l)+ operates as a bus master for the operation that caused the error. ? the command register perrsp bit is set. writing a 1 clears this bit to 0. 7 fbbc fast back-to-back capable: config3 rtl8139c(l)+ 2001/12/06 rev.1.5 57 ioar: this register specifies the base io a ddress which is required to build an address map during configuration. it also specifies the number of bytes required as well as an indication that it can be mapped into io space. bit symbol description 31-8 ioar31-8 base io address: this is set by software to the base io address for the operational register map. 7-2 iosize size indication: read back as 0. this allows the pci bridge to determine that the rtl8139c(l)+ requires 256 bytes of io space. 1 - reserved 0 ioin io space indicator: read only. set to 1 by the rtl8139c(l)+ to indicate that it is capable of being mapped into io space. memar: this register specifies the base me mory address for memory accesses to th e rtl8139c(l)+ opera tional registers. this register must be initialized pr ior to accessing any of the rtl8139c(l)+ 's registers with memory access. bit symbol description 31-8 mem31-8 base memory address: this is set by software to the base address for the operational register map. 7-4 memsize memory size: these bits return 0, which indicates that the rtl8139c(l)+ requires 256 bytes of memory space. 3 mempf memory prefetchable: read only. set to 0 by the rtl8139c(l)+. 2-1 memloc memory location select: read only. set to 0 by the rtl8139c(l)+. this indicates that the base register is 32-bit wide and can be placed anywhere in the 32-bit memory space. 0 memin memory space indicator: read only. set to 0 by the rtl8139c(l)+ to indicate that it is capable of being mapped into memory space. cisptr: cardbus cis pointer. this field is valid only when cardb_en (bit3, config3) = 1. the value of this register is auto-loaded from 93c46 or 93c56 (from offset 30h-31h). - bit 2-0: address space indicator bit2-0 meaning 0 not supported. (cis begins in de vice-dependent conf iguration space.) 1-6 the cis begins in the memory address governed by one of the six base address registers. ex., if the value is 2, then the cis begins in the memory address space governed by ba se address register 2. 7 the cis begins in the expansion rom space. - bit27-3: address space offset - bit31-28: rom image number bit2-0 space type address space offset values 0 configuration space not supported. x; 1 x 6 memory space 0h value ffff fff8h. this is the offset into the memory address space governed by base address register x. adding this value to the value in the base address register gives the location of the start of the cis. for rtl8139c(l)+, the value is 100h. 7 expansion rom 0 image number fh, 0h value 0fff fff8h. this is the offset into the expansion rom address space governed by the expansion rom base register. the image number is in the uppermost nibble of the cisptr register. the value consists of the remaining bytes. for rtl8139c(l)+, the image number is 0h. this read-only register points to where th e cis begins, in one of the following spaces: i. memory space --- the cis may be in any of th e memory spaces from offs et 100h and up after being auto-loaded from 93c56. the cis is stored in 93c56 eeprom physically from offset 80h-ffh. ii. expansion rom space --- the cis is stored in expansion rom physically within the 128kb max. svid: subsystem vendor id. this field will be set to a value corresponding to pci subsystem vendor id in the external eeprom. if there is no eeprom, this fi eld will default to a value of 10ech which is realtek semiconductor's pci subsystem vendor id. rtl8139c(l)+ 2001/12/06 rev.1.5 58 smid: subsystem id. this field will be set to value corresponding to pci subsystem id in the ex ternal eeprom. if there is no eeprom, this field will default to a value of 8129h. bmar: this register specifies the base me mory address for memory accesses to th e rtl8139c(l)+ opera tional registers. this register must be initialized prior to accessi ng any rtl8139c(l)+'s regist er with memory access. bit symbol description 31-18 bmar31-18 boot rom base address 17-11 romsize these bits indicate how ma ny boot rom spaces to be supported. the relationship between config 0 rtl8139c(l)+ 2001/12/06 rev.1.5 59 8.6 the default value after power-on (rstb asserted) pci configuration space table no. name type bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00h vid r 1 1 1 0 1 1 0 0 01h r 0 0 0 1 0 0 0 0 02h did r 0 0 1 0 1 0 0 1 03h r 1 0 0 0 0 0 0 1 04h command r 0 0 0 0 0 0 0 0 w - perrsp - mwien - bmen memen ioen 05h r 0 0 0 0 0 0 0 0 w - - - - - - - serren 06h status r 0 0 0 newcap 0 0 0 0 07h r 0 0 0 0 0 0 1 0 w dperr sserr rmabt rtabt stabt - - dpd 08h revision id r 0 0 1 0 0 0 0 0 09h pifr r 0 0 0 0 0 0 0 0 0ah scr r 0 0 0 0 0 0 0 0 0bh bcr r 0 0 0 0 0 0 1 0 0ch cls r/w 0 0 0 0 0 0 0 0 0dh ltr r 0 0 0 0 0 0 0 0 w ltr7 ltr6 ltr5 ltr 4 ltr3 ltp2 ltr1 ltr0 0eh htr r 0 0 0 0 0 0 0 0 0fh bist r 0 0 0 0 0 0 0 0 10h ioar r 0 0 0 0 0 0 0 1 11h r/w 0 0 0 0 0 0 0 0 12h r/w 0 0 0 0 0 0 0 0 13h r/w 0 0 0 0 0 0 0 0 14h memar r 0 0 0 0 0 0 0 0 15h r/w 0 0 0 0 0 0 0 0 16h r/w 0 0 0 0 0 0 0 0 17h r/w 0 0 0 0 0 0 0 0 18h | 27h - reserved(all 0) 28h r 0 0 0 0 0 0 0 0 29h r 0 0 0 0 0 0 0 0 2ah r 0 0 0 0 0 0 0 0 2bh cisptr r 0 0 0 0 0 0 0 0 2ch svid r 1 1 1 0 1 1 0 0 2dh r 0 0 0 1 0 0 0 0 2eh smid r 0 0 1 0 1 0 0 1 2fh r 1 0 0 0 0 0 0 1 30h bmar r 0 0 0 0 0 0 0 0 w - - - - - - - bromen 31h r 0 0 0 0 0 0 0 0 w bmar15 bmar14 bmar13 bmar12 bmar11 - - - 32h r/w 0 0 0 0 0 0 0 0 33h r/w 0 0 0 0 0 0 0 0 rtl8139c(l)+ 2001/12/06 rev.1.5 60 34h cap-ptr r ptr7 ptr6 ptr5 ptr4 ptr3 ptr2 ptr1 ptr0 35h | 3bh - reserved(all 0) 3ch ilr r/w 0 0 0 0 0 0 0 0 3dh ipr r 0 0 0 0 0 0 0 1 3eh mngnt r 0 0 1 0 0 0 0 0 3fh mxlat r 0 0 1 0 0 0 0 0 40h | ffh - reserved(all 0) 8.7 pci power management functions the rtl8139c(l)+ is compliant to acpi (v1.0, v2.0), pci power management (rev 1.1), and device class power management reference specification (v1.0a), such as to s upport os directed power management (ospm) environment. to support this, the rtl8139c(l)+ pr ovides the following capabilities: the rtl8139c(l)+ can monitor the network for a wakeup frame, a magic packet, or a link change, and notify the system via pme# when such a packet or event arrives. then, the whole system can restore to working state to process the incoming jobs. the rtl8139c(l)+ can be isolated from the pci bus automatically with the auxiliary power circuit when the pci bus is in b3 state, i.e. the power on the pci bus is removed. when the motherboard includes a bu ilt-in rtl8139c(l)+ single-chip fast ethernet controller, th e rtl8139c(l)+ can be disabled when need ed by pulling the isolate pin low to 0v. when the rtl8139c(l)+ is in power down mode (d1 ~ d3), ? the rx state machine is stopped, and the rtl8139c(l)+ keeps monitoring the network for wakeup events such magic packet, wakeup frame, and/or link change, in order to wake up the system. when in power down mode, the rtl8139c(l)+ will not reflect the status of any incoming packets in the isr regi ster and will not receive any packets into the rx fifo. ? the fifo status and the packets which are already received into rx fifo befo re entering into power down mode, are kept by the rtl8139c(l)+ during power down mode ? the transmission is stopped. the action of pci bus master mode is stopped, as well. the tx fifo is kept. ? after restoration to a d0 state, the pci bus master mode continues to transfer the data, which is not yet moved into the tx fifo from the last break. the packet that was not transmitted completely last time is transmitted again. d3cold_support_pme bit(bit15, pmc re gister) & aux_i_b2:0 (bit8:6, pmc regi ster) in pci configuration space . if eeprom d3cold_support_pme bit(bit15, pmc) = 1, the above 4 bits depend on the existence of aux power. if eeprom d3cold_support_pme bit(bit15, pmc) = 0, the above 4 bits are all 0's. examples: 1. if eeprom d3c_support_pme = 1, if aux. power exists, then pmc in pci config sp ace is the same as eepro m pmc, i.e. if eeprom pmc = c2 f7, then pci pmc = c2 f7. if aux. power is absent, then pmc in pci config space is the same as eeprom pmc except the above 4 bits are all 0?s. i.e. if eeprom pmc = c2 f7, the pci pmc = 02 76. in this case, if wakeup support is desired when the main power is off, it is suggested that the eeprom pmc bet set to c2 f7 (rt eeprom default value). rtl8139c(l)+ 2001/12/06 rev.1.5 61 2. if eeprom d3c_support_pme = 0, if aux. power exists, then pmc in pci config sp ace is the same as eepro m pmc. i.e. if eeprom pmc = c2 77, then pci pmc = c2 77. if aux. power is absent, then pmc in pci config space is the same as eeprom pmc except the above 4 bits are all 0?s. i.e. if eeprom pmc = c2 77, the pci pmc = 02 76. in this case, if wakeup support is not desired when the main power is off, it is suggested that the eeprom pmc be set to 02 76. link wakeup occurs only when the following conditions are met: ? the linkup bit (config3#4) is set to 1, the pmen bit (config1#0) is set to 1, and the rtl8139c(l)+ is in an isolation state, or the pme# can be asserted in current power state. ? the link status is re-established. magic packet wakeup occurs only when the following conditions are met: ? the destination address of the received magic packet matches. ? the received magic packet doe s not contain a crc error. ? the magic bit (config3#5) is set to 1, the pmen bit (config1#0) is set to 1, and the rtl8139c(l)+ is in isolation state, or the pme# can be asse rted in current power state. ? the magic packet pattern matches, i.e. 6 * ffh + misc(can be none)+ 16 * did(destination id) in any part of a valid (fast) ethernet packet. wakeup frame event occurs only when the following conditions are met: ? the destination address of the received wakeup frame matches. ? the received wakeup frame does not contain a crc error. ? the pmen bit (config1#0) is set to 1. the 8-bit crc* (or 16-bit crc) of the received wakeup frame matches with the 8-bit crc* (or 16-bit crc) of the sample wakeup frame pattern received from the local machine?s os. the last masked byte** of the received wakeup frame matc hes with the last masked byte** of the sample wakeup frame pattern provided by the local machine?s os. (in long wa keup frame mode, the last mask ed byte field is replaced with the high byte of the 16-bit crc.) * 8-bit crc: this 8-bit crc logic is used to gene rate an 8-bit crc from the masked bytes of the received wakeup frame packet within offset 12 to 75. software should calculate the 8-bit power management crc for each specific sample wakeup frame and store the calculated crc in the corresponding crc re gister for the rtl8139c(l)+ to check if there is wakeup frame packet coming in. * 16-bit crc: (long wakeup frame mode, the mask bytes cover from offset 0 to 127) long wakeup frame: the rtl8139c(l)+ also supports 3 l ong wakeup frames. if the range of mask bytes of the sample wakeup frame, passed down by the os to the driv er, exceeds the range from offset 12 to 75, the related registers of wakeup frame 2 and 3 can be merged to support one long wake up frame by setting the longwf (bit0, config4). thus, the range of effective mask bytes extends from offset 0 to 127. the low byte and high byte of calculated 16-bit crc should be stored into register crc2 and lsbcrc2 respec tively. the mask bytes (16 bytes) should be stored to register wa keup2 and wakeup3. the crc3 and lsbcrc3 have no meaning in this case and should be reset to 0. so as the long wakeup frame pairs, wakeup frame 4 and 5, wake up frame 6 and 7 each make up one wakeup frame. the crc5, crc7, lsbcrc5, and lsbcrc7 have no meaning in this case and should be reset to 0, if the rtl8139c(l)+ is set to support long wakeup frame. in this case, the rtl8139c(l)+ support 5 wakeup frames, that are 2 normal wakeup frames and 3 long wakeup frames. rtl8139c(l)+ 2001/12/06 rev.1.5 62 ** last masked byte: the last byte of the masked bytes of the received wakeup frame packet within offset 12 to 75 (in 8-bit crc mode) should matches with the last byte of the masked bytes of the sample wakeup frame provided by the local machine?s os. the pme# signal is asserted only when the following are met: the pmen bit (bit0, config1) is set to 1. the pme_en bit (bit8, pm csr) in pci configuration space is set to 1. the rtl8139c(l)+ may assert pme# in current power state, or the rtl8139c(l)+ is in isolation 1 state. refer to pme_support(bit15-11) of the pmc regi ster in pci configuration space. magic packet, linkup, or wakeup frame has occurred. note: writing a 1 to the pme_status (bit 15) of pmcsr register in the pci conf iguration space will clear this bit and cause the rtl8139c(l)+ to stop asserting a pme# (if enabled). when the rtl8139c(l)+ is in power down mode, ex. d1-d3, th e io, mem, and boot rom space are all disabled. after rst# asserted, the power state must be changed to d0 if the original power state is d3 cold . there is no hardware enforced delays at rtl8139c(l)+?s power state. when in acpi mode, the rtl8139c(l)+ does not support pme from d0, due to the setting of pmc register. this setting comes from eeprom. the rtl8139c(l)+ also supports lan wake-up function. the lwake pin is used to notify the motherboard to execute wake-up process whenever the rtl8139c(l)+ recei ves a wakeup event, such as magic packet. the lwake signal is asserted according the following setting. lwpme bit (bit4, config4): 0: the lwake is asserted whenev er there is wakeup event occurs. 1: the lwake can only be asserted when the pm eb is asserted and the isolateb is low. bit1 of delay byte(offset 1fh, eeprom): 0: lwake signal is disabled. 1: lwake signal is enabled 8.8 vital product data (vpd) bit 31 of the vpd is used to issue vpd read/write command and is also a flag used to indicate whether the transfer of data between the vpd data register and the 93c46/93c56 is completed or not. 1. write vpd register: (write data to 93c46/93c56) write the flag bit to a one (at the same time the vpd address is written). when the flag bit is set to zero by the rtl8139c(l)+, the vp d data (all 4 bytes) has been transferred from the vpd data register to 93c46/93c56. 2. read vpd register: (read data from 93c46/93c56) write the flag bit to a zero at the same time the vpd address is written). when the flag bit is set to one by the rtl8139c(l)+, the vp d data (all 4 bytes) has been transferred from 93c46/93c56 to the vpd data register. rtl8139c(l)+ 2001/12/06 rev.1.5 63 9. functional description 9.1 transmit & receive operations in c mode 9.1.1 transmit the host cpu initiates a transmit by storing an entire packet of data in one of the descriptors in the main memory. those descriptors should be aligned in double-word format. when the entire packet has been transferred to the tx buffer, the rtl8139c(l)+ is instructed to move the data from the tx buffer to the internal transmit fifo in pci bus master mode. when the transmit fifo contains a complete pack et or is filled to the programmed threshol d level, the rtl8139c(l)+ begins packet transmission. please refer to the realtek rtl8139 se ries programming guide for detailed information. 9.1.2 receive the incoming packet is placed in the rtl8139c(l)+'s rx fifo. concurrently, the rtl8139c(l)+ perform s address filtering of multicast packets according to its hash algor ithms. when the amount of data in the rx fifo reaches the level defined in the receive configuration register (rcr), the rtl8139c(l)+ requests the pci bus to begin transferring th e data to the rx buffer in pci bus master mode. the rx buffer s hould be pre-allocated and indicated in rcr before packet reception. all received packets stored in rx buffer, including rx header and 4-byte crc, are double-word a lignment. i.e., each received packet is placed at next available double-wo rd alignment address after the last received p acket in rx buffer. please refer to realtek rtl8139 series programming guide for detailed information. 9.2 transmit & receive operations in c+ mode in c+ mode, the rtl8139c(l)+ supports a new descriptor-based buffe r management that will significantly lower host cpu utilization and is more suitable for server applications. the new buffer management algorithm provides capabilities of microsof t large-send offload, ip checksum offload, tcp checksum o ffload, udp checksum offload, and ieee802.1p, 802.1q vlan tagging. the rtl8139c(l)+ supports up to 64 consecutive descriptors in memory for transmit and receive separately, which means there can be 3 descriptor rings, one is a high priority transmit descriptor ring, another is a normal priority transmit descriptor ring, and the other is a recei ve descriptor ring. each descriptor ring may consis t of up to 64 4-double-word consecutive descriptors. each descriptor consists of 4 consecutive double words. th e start address of each descriptor group should be 256-byte alignment. so ftware must pre-allocate enough bu ffers and configure all descri ptor rings before transmitting and/or receiving packets. descri ptors can be chained to form a packet, in both tx and rx. please refer to the realtek rtl8139c(l)+ programming guide for detailed information. any tx buffer pointed to by one of tx descriptors should be at least 4 bytes. padding: the rtl8139c+ will automatically pa d any packet less than 64 bytes (incl uding 4 bytes crc) to 64-bytes in length (including 4-byte crc) before transmitting that packet onto network medium, when the pad bit is set to 1 in the c+cr (offset e0h) c+ command register. if a packet consists of 2 or more descriptors, then the descri ptors in command mode should have the same configuration, except eor, fs, ls bits. rtl8139c(l)+ 2001/12/06 rev.1.5 64 9.2.1 transmit the following information describes what the tx descriptor may look like, de pending on different se ttings in each tx descriptor. large-send task offload tx descriptor format (before transmitting, own=1, lgsen=1, tx command mode 0) bit 31 30 29 28 27 26 16 15 8 7 6 5 4 3 2 1 0 o w n = 1 e o r f s l s l g s e n = 1 large-send mss value (11 bits) frame_length offset 0 vlan_tag rsvd t a g c r s v d vidl prio c fi vidh offset 4 tx_buffer_address_low offset 8 tx_buffer_address_high offset 12 rtl8139c(l)+ 2001/12/06 rev.1.5 65 offset# bit# symbol description 0 31 own ownership: when set, indicates that the descriptor is owned by the nic, and the data relative to this descriptor is ready to be transmitted. when cleared, indicates that the descriptor is owned by the host system. the nic clears this bit when the relative buffer data is transmitted. in this case, own=1. 0 30 eor end of descriptor ring: when set, indicates that this is the last descriptor in the descriptor ring. when the internal transm it pointer of the nic reaches he re, the pointer will return to the first descriptor of the descriptor ring after transmitting the data relative to this descriptor. 0 29 fs first segment descriptor: when set, indicates that this is the first descriptor of a tx packet, and this descriptor is pointing to the first segment of the packet. 0 28 ls last segment descriptor: when set, indicates that this is the last descriptor of a tx packet, and this descriptor is pointing to the last segment of the packet. 0 27 lgsen tcp/ip large send operation enable: a command bit. the driver sets this bit to ask the nic to offload the large send operation. in this case, lgsen=1. 0 26-16 mss maximum segmentation size: this is a command field, 11-bits long. the driver passes large send mss to the nic through this field. 0 15-0 frame_le ngth transmit frame length: this field indicates the length in the tx buffer, in bytes, to be transmitted. 4 31-18 rsvd reserved 4 17 tagc vlan tag control bit: 1: enable. 0: disable. 1: add tag. 0x8100 (ethernet encoded tag prot ocol id, indicating that this is a ieee 802.1q vlan packet) is inserted after source address, and 2 bytes are inserted after tag protocol id from vlan_tag field in transmit descriptor. 0: packet remains unchanged when transmitting. i.e., the packet transmitted is the same as it was passed down by upper layer. 4 16 rsvd reserved 4 15-0 vlan_tag the 2-byte vlan_tag contains information, from upper layer, of user priority, canonical format indicator, and vlan id. please refer to ieee 802.1q for more vlan tag information. vidh: the high 4 bits of a 12-bit vlan id. vidl: the low 8 bits of a 12-bit vlan id. prio: 3-bit 8-level priority. cfi: canonical format indicator. 8 31-0 txbuffl low 32-bit address of transmit buffer 12 31-0 txbuffh high 32-bit address of transmit buffer rtl8139c(l)+ 2001/12/06 rev.1.5 66 normal (including ip, tcp, udp checksu m task offloads) tx descriptor format (before transmitting, own=1, lgsen=0, tx command mode 1) bit 31 30 29 28 27 26 16 15 8 7 6 5 4 3 2 1 0 o w n = 1 e o r f s l s l g s e n = 0 r s v d r s v d r s v d r s v d r s v d r s v d r s v d r s v d i p c s u d p c s t c p c s frame_length offset 0 vlan_tag rsvd t a g c r s v d vidl prio c fi vidh offset 4 tx_buffer_address_low offset 8 tx_buffer_address_high offset 12 rtl8139c(l)+ 2001/12/06 rev.1.5 67 offset# bit# symbol description 0 31 own ownership: when set, indicates that the descriptor is owned by the nic, and the data relative to this descriptor is ready to be transmitted. when cleared, indicates that the descriptor is owned by the host system. the nic clears this bit when the relative buffer data is transmitted. in this case, own=1. 0 30 eor end of descriptor ring: when set, indicates that this is the last descriptor in the descriptor ring. when the internal transm it pointer of the nic reaches he re, the pointer will return to the first descriptor of the descriptor ring after transmitting the data relative to this descriptor. 0 29 fs first segment descriptor: when set, indicates that this is the first descriptor of a tx packet, and this descriptor is pointing to the first segment of the packet. 0 28 ls last segment descriptor: when set, indicates that this is the last descriptor of a tx packet, and this descriptor is pointing to the last segment of the packet. 0 27 lgsen a command bit: tcp/ip large send operation enable. driver sets this bit to ask nic to offload large send operation. in this case, lgsen=0. 0 26-19 rsvd reserved 0 18 ipcs ip checksum offload: a command bit. driver sets this bit to ask nic to offload ip checksum. 0 17 udpcs udp checksum offload: a command bit. driver sets this bit to ask nic to offload udp checksum. 0 16 tcpcs tcp checksum offload enable: a command bit. the driver sets this bit to ask the nic to offload the tcp checksum. 0 15-0 frame_le ngth transmit frame length: this field indicates the length in the tx buffer, in bytes, to be transmitted 4 31-18 rsev reserved 4 17 tagc vlan tag control bit: 1: enable. 0: disable. 1: add tag. 0x8100 (ethernet encoded tag prot ocol id, indicating that this is a ieee 802.1q vlan packet) is inserted after source address, and 2 bytes are inserted after tag protocol id from vlan_tag field in transmit descriptor. 0: packet remains unchanged when transmitting. i.e., the packet transmitted is the same as it was passed down by upper layer. 4 16 rsev reserved 4 15-0 vlan_tag the 2-byte vlan_tag contains information, from upper layer, of user priority, canonical format indicator, and vlan id. please refer to ieee 802.1q for more vlan tag information. vidh: the high 4 bits of a 12-bit vlan id. vidl: the low 8 bits of a 12-bit vlan id. prio: 3-bit 8-level priority. cfi: canonical format indicator. 8 31-0 txbuffl low 32-bit address of transmit buffer 12 31-0 txbuffh high 32-bit address of transmit buffer rtl8139c(l)+ 2001/12/06 rev.1.5 68 tx status descriptor (after transmi tting, own=0, tx status mode) after having transmitted, the tx descriptor turns into a tx status descriptor. bit 31 30 29 28 27 26 16 15 8 7 6 5 4 3 2 1 0 o w n = 0 e o r f s l s r s v d r s v d u n f r s v d t e s o w c l n k f e x c cc3-0 frame_length offset 0 vlan_tag rsvd t a g c r s v d vidl prio c fi vidh offset 4 tx_buffer_address_low offset 8 tx_buffer_address_high offset 12 rtl8139c(l)+ 2001/12/06 rev.1.5 69 offset# bit# symbol description 0 31 own ownership: when set, indicates that the descriptor is owned by the nic. when cleared, indicates that the descriptor is owned by th e host system. the nic cl ears this bit when the relative buffer data is already transmitted. in this case, own=0. 0 30 eor end of descriptor ring: when set, indicates that this is the last descriptor in the descriptor ring. when the internal transm it pointer of the nic reaches he re, the pointer will return to the first descriptor of the descriptor ring after transmitting the data relative to this descriptor. 0 29 fs first segment descriptor: when set, indicates that this is the first descriptor of a tx packet, and this descriptor is pointing to the first segment of the packet. 0 28 ls last segment descriptor: when set, indicates that this is the last descriptor of a tx packet, and this descriptor is pointing to the last segment of the packet. 0 27-26 rsvd reserved 0 25 unf fifo underrun: a status bit. nic sets this bit to inform driver that fifo underrun had ever occurred before this packet transmitted. 0 24 rsvd reserved 0 23 tes transmit error summary: when set, indicates that at least one of the following errors has occurred: owc, exc, lnkf. this bit is valid only when the ls (last segment) bit is set. 0 22 owc out of window collision: a status bit. when set, it m eans an ?out-of-window? collision is encountered during transmission of a packet. 0 21 lnkf link failure: a status bit. the nic sets this bit to inform the driver of a link failure. 0 20 exc excessive collision: when set, indicates that the transmission was aborted due to 16 consecutive collisions. 0 19-16 cc3-0 collision counter: when own bit =0, this is a stat us field. a 4-bit collision counter, showing the total collision times before the packet was transmitted. 0 15-0 frame_le ngth transmit frame length: this field indicates the length of the tx buffer, in bytes, to be transmitted 4 31-18 rsev reserved 4 17 tagc vlan tag control bit: 1: enable. 0: disable. 1: add tag. 0x8100 (ethernet encoded tag prot ocol id, indicating that this is a ieee 802.1q vlan packet) is inserted after source address, and 2 bytes are inserted after tag protocol id from vlan_tag field in transmit descriptor. 0: packet remains unchanged when transmitting. i.e., the packet transmitted is the same as it was passed down by upper layer. 4 16 rsev reserved 4 15-0 vlan_tag the 2-byte vlan_tag contains information, from upper layer, of user priority, canonical format indicator, and vlan id. please refer to ieee 802.1q for more vlan tag information. vidh: the high 4 bits of a 12-bit vlan id. vidl: the low 8 bits of a 12-bit vlan id. prio: 3-bit 8-level priority. cfi: canonical format indicator. 8 31-0 txbuffl low 32-bit address of transmit buffer 12 31-0 txbuffh high 32-bit address of transmit buffer rtl8139c(l)+ 2001/12/06 rev.1.5 70 9.2.2 receive the following information describes what th e rx descriptor may look like, depending on different states in each rx descriptor. any rx buffer, which is pointed to by one of the rx descriptors, should be at least 4 bytes. rx command descriptor (own=1) the driver should pre-allocate rx buffers a nd configure rx descriptors be fore packet reception. the following describes what a rx descriptor may look like before packet reception. bit 31 30 29 28 19 18 17 16 15 13 12 8 7 6 5 4 3 2 1 0 o w n = 1 e o r rsvd buffer_size offset 0 vlan_tag rsvd t a v a vidl prio c fi vidh offset 4 rx_buffer_address_low offset 8 rx_buffer_address_high offset 12 offset# bit# symbol description 0 31 own ownership: when set, indicates that the descriptor is owned by the nic, and is ready to receive a packet. the own bit is set by the driver after having pre-allocated a buffer at initialization, or the host has released the buffer to the driver. in this case, own=1. 0 30 eor end of rx descriptor ring: set to 1 indicates that this descriptor is the last descriptor o f the rx descriptor ring. once the internal receive descriptor pointer of the nic reaches here, it will return to the first descriptor of the rx descriptor ring after this descriptor is used by packet reception. 0 29-13 rsvd reserved 0 12-0 buffer_size buffer size: this field indicates the receive buffe r size in bytes. although the maximum buffer size is 8k bytes/buffer, the rtl8139c(l)+ purges all data after 4k bytes if the packet is larger than 4k-bytes long. 4 31-17 rsev reserved 4 16 tava tag available: when set, the received packet is an ieee802.1q vlan tag (0x8100) available packet. 4 15-0 vlan_tag if the tag of the packet is 0x8100, the mac of the rtl8139c(l)+ extracts four bytes from the after source id, sets the tava bit to1, and moves the tag value to this field in the rx descriptor. vidh: the high 4 bits of a 12-bit vlan id. vidl: the low 8 bits of a 12-bit vlan id. prio: 3-bit 8-level priority. cfi: canonical format indicator. 8 31-0 rxbuffl low 32-bit address of receive buffer 12 31-0 rxbuffh high 32-bit address of receive buffer. rtl8139c(l)+ 2001/12/06 rev.1.5 71 rx status descriptor (own=0) when a packet is received, the rx command desc riptor turns into a rx status descriptor. bit 31 30 29 28 27 26 16 15 13 12 8 7 6 5 4 3 2 1 0 o w n = 0 e o r f s l s f a e m a r p a m b a r b o v f f o v f r w t r e s r u n t c r c pi d 1 pi d 0 ip f u d p f t c p f frame_length offset 0 vlan_tag rsvd t a v a vidl prio c fi vidh offset 4 rx_buffer_address_low offset 8 rx_buffer_address_high offset 12 offset# bit# symbol description 0 31 own ownership: when set, indicates that the descriptor is owned by the nic. when cleared, indicates that the descriptor is owned by the host system. the nic clears this bit when it has filled up this rx buffer with a packet or part of a packet. in this case, own=0. 0 30 eor end of rx descriptor ring: set to 1 indicates that this descriptor is the last descriptor o f the rx descriptor ring. when th e internal receive descriptor poi nter of the nic reaches here, it will return to the first descriptor of the rx descriptor ring after this descriptor is used by packet reception. 0 29 fs first segment descriptor: when set, indicates that this is the first descriptor of a received packet, and that this descriptor is pointing to the first segment of the packet. 0 28 ls last segment descriptor: when set, indicates that this is the last descriptor of a received packet, and this descriptor is pointing to the last segment of the packet. 0 27 fae frame alignment error: when set, indicates a frame a lignment error has occurred on the received packet. fae packets can be received only when rcr_aer is set. 0 26 mar multicast address packet received: when set, indicates that a mu lticast packet has been received. 0 25 pam physical address matched: when set, indicates that the destination address of this rx packet matches the value in the id registers of the rtl8139c(l)+. 0 24 bar broadcast address received: when set, indicates that a broadcast packet has been received. bar and mar will not be set simultaneously. 0 23 bovf buffer overflow: when set, indicates that receive buffer has b een exhausted before this packet was received. 0 22 fovf fifo overflow: when set, indicates that a fifo overflow ha s occurred before this packet was received. 0 21 rwt receive watchdog timer expired: when set, indicates that the received packet length exceeds 4096 bytes. the receive watchdog timer will expire and stop the receiving engine. (same as the long bit definition in 8139a) 0 20 res receive error summary: when set, indicates that at l east one of the following errors has occurred: crc, runt, rwt, fae. this bit is valid only when the ls (last segment) bit is set. rtl8139c(l)+ 2001/12/06 rev.1.5 72 0 19 runt runt packet: when set, indicates that the received packet length is smaller than 64 bytes. runt packets can be received only when rcr_ar is set. 0 18 crc crc error: when set, indicates that a crc erro r has occurred on the received packet. crc packets can be received only when rcr_aer is set. protocol id1, protocol id0: these 2 bits indicate the protocol type of the packet received. pid1 pid0 non-ip 0 0 tcp/ip 0 1 udp/ip 1 0 ip 1 1 0 17, 16 pid1, pid0 0 15 ipf when set, indicates ip checksum failure. 0 14 udpf when set, indicates udp checksum failure. 0 13 tcpf when set, indicates tcp checksum failure. 0 12-0 frame_length when own=0 and ls =1, it indicates the recei ved packet length including crc, in bytes. 4 31-17 rsvd reserved 4 16 tava tag available: when set, the received packet is an ieee802.1q vlan tag (0x8100) available packet. 4 15-0 vlan_t ag if the packet ?s tag is 0x8100, the rtl8139c(l)+?s mac extracts four bytes from after source id, sets tava bit to1, and moves the t ag value to this field in rx descriptor. vidh: the high 4 bits of a 12-bit vlan id. vidl: the low 8 bits of a 12-bit vlan id. prio: 3-bit 8-level priority. cfi: canonical format indicator. 8 31-0 rxbuffl low 32-bit address of receive buffer 12 31-0 rxbuffh high 32-bit address of receive buffer rtl8139c(l)+ 2001/12/06 rev.1.5 73 9.3 line quality monitor the line quality monitor function is availabl e in 100base-tx mode. it is possible to determine the amount of equalization being used by accessing certain test registers. this provides a crude indication of connected cable length. this function allows for a qui ck and simple verification of the line quality in that any significant deviation from an exp ected register value (based on a known cab le length) would indicate that the signal quality has deviated from the expected nominal case. 9.4 clock recovery module the clock recovery module (crm) is supported in both 10base-t and 100base-tx mode. the crm accepts 125mb/s mlt3 data from the equalizer. the dpll locks onto the 125mb/s data st ream and extracts a 125mhz recovered clock. the extracted and synchronized clock and data are used as required by th e synchronous receive operations. 9.5 loopback operation loopback mode is normally used to verify that the logic operations up to the ethernet cable function correctly. in loopback mod e for 100mbps, the rtl8139c(l)+ takes frames from the transmit descriptor and transmits them up to internal twister logic. the loopback function does not apply to external phyceiver. 9.6 tx encapsulation with the internal phyceiver while operating in 100base-tx mode, the rtl8139c(l)+ encapsulates the frames that it transmits accord ing to the 4b/5b code-groups table. the changes of the original packet data are listed as follows: 1. the first byte of the preamble in the mac frame is replaced with the jk symbol pair. 2. after the crc, the tr symbol pair is inserted. 9.7 collision if the rtl8139c(l)+ is not in the full-duplex mode, a collision event occurs when th e receive input is not idle while the rtl8139c(l)+ transmits. if the collision was detected during the preamble transmission, the jam pattern is transmitted after completing the preamble (including the jk symbol pair). rtl8139c(l)+ 2001/12/06 rev.1.5 74 9.8 rx decapsulation with the internal phyceiver the rtl8139c(l)+ continuously monitors th e network when reception is enabled. wh en activity is recognized it starts to process the incoming data. after detecting receive activity on the lin e, the rtl8139c(l)+ starts to process the preamble bytes based on the mode of operation. while operating in 100base-tx mode, the rtl8139c(l)+ expects the frame to start with the symbol pair jk in the first bye of the 8-byte preamble. the rtl8139c(l)+ checks the crc bytes and checks if the packet data ends with the tr symbol pair, if not, the rtl8139c(l)+ reports an crc error rsr. the rtl8139c(l)+ reports a rsr rtl8139c(l)+ 2001/12/06 rev.1.5 75 9.10 medium auto-detect (utp or mii, no boot rom interface) the following diagram describes the process the rtl8139c(l)+ uses to detect the medium used. start medium = mii mii link ok medium = utp utp link ok yes yes no no rtl8139c(l)+ 2001/12/06 rev.1.5 76 9.11 cable connection status ? for medium status from an external phyceiver (mii application enabled, no boot rom) to be reported correctly, the mlink (pin 102) and mfdup (pin 103) pins should be connected to relative pins of the external phyceiver. ? the status of link speed and duplex mode are reflected to the relative register s when the current medium is either utp or mii (mii application enabled). ? link change from current linkok medium generates an interrupt (linkchg, bit5, isr) to notify the drivers of link change event. ? force link speed function is effective only to rtl8139c(l )+?s internal phyceiver. the rtl8139c(l)+ does not support hardware access to external phy ceiver?s mii registers in mii application. the only way to force link speed of external phyceiver, is to use software generated mii timing through mii register (offset fch, when medium select is set to auto-detect or mii mode). 1. utp: same as the rtl8139 series. 2. mii: the information reflects the medium status from external phyceiver, pr ovided that the mlink and mfdup are both connected to the relative pins of the external phyceiver. link: by mlink pin 102 if mlinkp (bit3, bmcr, offset 63h) = 1, then mlink=high means mii link ok if mlinkp (bit3, bmcr, offset 63h) = 0, then mlink=low means mii link ok mlinkp can be auto-loaded from eeprom. duplex: by mfdup pin 101 if mdupp (bit2, bmcr, offset 63h) = 1, then mfdup=high means mii duplex=full if mdupp (bit2, bmcr, offset 63h) = 0, then mfdup=low means mii duplex=full mdupp can be auto-loaded from eeprom. speed: by mtxc if mtxc = 2.5mhz, then speed=10mbps. if mtxc = 25mhz, speed=100mbps. rtl8139c(l)+ 2001/12/06 rev.1.5 77 9.12 mii redundant link the following diagram shows the process used by the rtl8139c(l)+ to implement the mii redundant link feature. this feature is valid only in mii applications only. external phyceiver rtl8139c(l)+ internal phy mii mlink mfdup rj-45 rj-45 rtl8139c(l)+ 2001/12/06 rev.1.5 78 9.13 memory functions 9.13.1 memory read line (mrl) the memory read line command reads information from a longword (dword) up to cache line boundary in size into a prefetchable address space. the memory read line command is semantically identical to the memory read command except that it additionally indicates that the mast er intends to fetch a complete cache line. this command is intended to be used with bulk sequential data transfers where the memory system and th e requesting master might gain some performance advantage by reading up to a cache line boundary in response to the request, rath er than a single memory cycle. as with the memory read command, pre-fetched buffers must be i nvalidated before any synchronization ev ents are passed through this access path. the rtl8139c(l)+ performs the mrl pro cess according to the following rules: i. read accesses that reach th e cache line boundary use the memory read line (mrl) command, instead of memory read command. ii. read accesses that do not r each the cache line boundary use the memory read (mr) command. iii. the memory read line (mrl) command operates in conjunction with the memory read multiple (mrm) command. iv. the rtl8139c(l)+ will terminat e the read transaction on to th e cache line boundary when it is out of resources on the transmit dma. for example, when the transmit fifo is almost full. 9.13.2 memory read multiple (mrm) the memory read multiple command is semantically identical to the memory read command except that it additionally indicates that the master may intend to fetch more than one cache line before disconnecting. the memory controller should continue pipelining memory requests as long as frameb is asse rted. this command is intended to be used with bulk sequential data transfers where the memory system and the requesting ma ster might gain some performance advantage by sequentially reading ahead one or more additional cache line(s) when a software tr ansparent buffer is availabl e for temporary storage. the rtl8139c(l)+ performs the mrm pro cess according to the following rules: i. when the rtl8139c(l)+ reads full cache lines, it will use the memory read multiple command. ii. if the memory buffer is not cache-aligned, the rtl8139c(l)+ will use memory read line command to reach the cache line boundary first. example: assume the packet length = 1514 byte, cache line size = 16 longwords (dwords), and tx buffer start address = 64m+4 (m > 0). ;step1: memory read line (mrl) ;data: (0-3) => (4-7) => (8-11) =>???... => (56-59) (byte offset of the tx packet) ;from address: <64m+4>, <64m+8>, ???., <64m+60> (reach cache line boundary) ;step2. memory read multiple (mrm) ;data: (60-63) => (64-67) => (68-71) => ?????????.?.. => (1454-1467) ;from address: <64m+64>, <64m+68> , ??????.?., <64m+64+(16*4)*21+(16-1)*4> ;step3. memory read(mr) ;data: (1468-1471) => (1472-1475) => ???????????, => (1510-1513) ;from address:<64m+64+ (16*4)*22>,<64m+64+(16*4)*22+ 4>,..,<64m+64+(16*4)*22+42> step1: memory read multiple (mrm) data: (0-3) => (4-7) => (8-11) =>????.. => (1454-1467) from address: <64m+4>, <64m+8 >, ???., <64m+64+(16*4)*21+(16-1)*4> step2. memory read(mrl) data: (1468-1471) => (1472-1475) => ???????????, => (1510-1513) from address:<64m+64+ (16*4)*22>,<64m+64+(16*4)*22+ 4>,..,<64m+64+(16*4)*22+42> rtl8139c(l)+ 2001/12/06 rev.1.5 79 9.13.3 memory write and invalidate (mwi) the memory write and invalidate command is semantically identical to the memory write command except that it additionally guarantees a minimum transfer of one comp lete cache line. for example, the master intends to wr ite all bytes within the addressed cache line in a single pci transacti on unless interrupted by the target. note th at all byte enables must be asserted during each data phase for this command. the master may allow the transaction to cross a cache line boundary only if it intends to transfer the entir e next line as well . this command requires implementation of a configur ation register in the master indicati ng the cache line size and may only be used with linear burst ordering. it allows a memory performance optimization by invalid ating a "dirty" line in a write-back cache without requiring the actual write-back cy cle, thus shortening access time. the r tl8139c(l)+ uses the mwi command while writing full cache lines, and the memory write command while writing partial cache lines. when the following requirements are met, the rtl8139c(l)+ issues the mwi command instead of the mw command on rx dma: i. the cache line size written in the offset 0c h of the pci configuration space is 8 or 16 longwords (dwords). ii. the accessed address is cache line aligned. iii. the rtl8139c(l)+ has at l east 8/16 longwords (dwords) of data in its rx fifo. iv. the mwi (bit 4) in the pci configuration command register should be set to 1. the rtl8139c(l)+ uses the memory write (mw) command instead of mwi whenever any one of the above listed requirements fails. the rtl8139c(l)+ terminat es the wmi cycle at the end of the cach e line when a wmi cycle has started and at least one of the requirements are no longer valid. example: assume rx packet length = 1514 byte, cache line size = 16 dwords (longwords), and rx buffer start address = 64m+4 (m > 0). step1: memory write (mw) data: (0-3) => (4-7) => (8-11) => ???... => ( 56-59) (byte offset of the rx packet) to address: <64m+4>, <64m+8>, ???? ., <64m+60> (reach cache line boundary) step2. memory write and invalidate (mwi) data: (60-63) => (64-67) => (68-71) => ????????..?.... => (1454-1457) to address: <64m+64>, <64m+68> , ??????..?.., <64m+64+(16*4)*21+(16-1)*4> step3. memory write(mw) data: (1458-1461) => (1462-1465) => ????????..??... => (1512-1513) to address: <64m+64+(16*4)*22>, <64m +64+(16*4)*22+4>, , < 64m+64+(16*4)*22+42> 9.13.4 dual address cycle (dac) the dual address cycle (dac) command is used to transfer a 64-bit address to devices that support 64-bit addressing when the address is not in the low 4 gb address sp ace. the rtl8139c(l)+ is capable of perform ing dac, such that it is very competent as a network server card in a heavy-duty server with the possibility of allocating a memory buffer above the 4gb memory address space. rtl8139c(l)+ 2001/12/06 rev.1.5 80 9.14 led functions 9.14.1 10/100 mbps link monitor the link monitor senses the link integrity or if a station is down. 9.14.2 led_rx in 10/100 mbps mode, the led function is like that of the rtl8129. receiving packet? power on led = low led = high for (100 +- 10) ms led = low for (12 +- 2) ms yes no rtl8139c(l)+ 2001/12/06 rev.1.5 81 9.14.3 led_tx power on led = low led = high for (100 +- 10) ms led = low for (12 +- 2) ms yes no transmitting packet 9.14.4 led_tx+led_rx power on led = low led = high for (100 +- 10) ms led = low for (12 +- 2) ms yes no tx or rx packet? rtl8139c(l)+ 2001/12/06 rev.1.5 82 9.15 physical layer interfaces the rtl8139c(l)+ supports standard me dia independent mii for 10mbps and 100mbps applica tions. in addition, a management interface is defined for mii. 9.15.1 media independent interface (mii) the rtl8139c(l)+ supports 10mbps and 100mbps physical layer de vices through the mii as defined in the ieee 802.3 (clause 22) specifications. the mii consists of a transmit data interf ace (txen, txer, txd[3:0], and tx clk), a receive data interface (rxdv, rxer, rxd[3:0], and rx clk), 2 status signals (crs and col) and a management interface (mdc and mdio). in this mode of operation, both transmit and receive clocks are supplied by the phy. 9.15.2 mii management interface the mii management interface utilizes a co mmunication protocol similar to a serial eeprom. signaling occurs on two signals: clock (mdc) and data (mdio). this protocol provides capability for addressing up to 32 individual physical media dependent (pmd) devices which share the same serial interface, and for a ddressing up to 32 16-bit read/write registers within each pmd. the mii management protocol utilizes the following frame format: start bits (sb), opcode (op), pmd address (pa), register address (ra), line turnaround (lt) and data, as shown below. sb op pa ra lt data 2 bits 2 bits 5 bits 5 bits 2 bits 16 bits mii management frame format i. start bits are defined as <01>. ii. opcode bits are defined as <01> fo r a write access and <10> for a read access. iii. pmd address is the device address. iv. register address is address of the register within that device. v. line turnaround bits will be <10> for write accesses and w ill be rtl8139c(l)+ 2001/12/06 rev.1.5 83 10. application diagram rtl8139c(l)+ rj45 magnetics eeprom boot rom/ flash* led clk data a ddress pci interface auxiliary power (3.3v/5v) external phy & magnetics* auxiliary power (5v) rj45 * boot rom/flash and external phy can not be implemented at the same time. rtl8139c(l)+ 2001/12/06 rev.1.5 84 11. electrical characteristics 11.1 temperature limit ratings parameter minimum maximum units storage temperature -55 +125 c operating temperature 0 70 c 11.2 dc characteristics 11.2.1 supply voltage vcc = 3.0v min. to 3.6v max. symbol parameter conditions minimum maximum units v oh minimum high level output voltage i oh= -8ma 0.9 * vcc vcc v v ol maximum low level output voltage i ol= 8ma 0.1 * vcc v v ih minimum high level input voltage 0.5 * vcc vcc+0.5 v v il maximum low level input voltage -0.5 0.3 * vcc v i in input current v in= v cc or gnd -1.0 1.0 ua i oz tri-state output leakage current v out= v cc or gnd -10 10 ua i cc average operating supply current i out= 0ma, 330 ma rtl8139c(l)+ 2001/12/06 rev.1.5 85 11.3 ac characteristics 11.3.1 flash/boot rom timing md7-0 ma17-0 romcsb oeb web tcolz toh tohz tacc toolz trc tce toes twrbr flash/boot rom - read symbol description minimum typical maximum units trc read cycle 135 - - ns tce chip enable access time - - 200 ns tacc address access time - - 200 ns toes output enable access time - - 60 ns tcolz chip enable to output in low z 0 - - ns toolz output enable to output in low z 0 - - ns tohz output disable to output in high z - - 40 ns toh output hold from address, romcsb, or oeb 0 - 0 ns twrbr write recovery time before read 6 - - us flash/boot rom ? read table rtl8139c(l)+ 2001/12/06 rev.1.5 86 md7-0 ma17-0 romcsb oeb web programming program verification program command latch address & data verify command standby/vcc power-down setupmprogram command vcc power-up & standby twc twc trc tch tas tdh tghwl datao tds twp twhgl dataout =c0h dataout =40h valid data in twph twhwh1 twp tds tdh tcs tah tds tcolz twp tch tah tcs tdf tce toolz toe toh flash memory ? write symbol description minimum typical maximum units twc write cycle time 135 - - ns tas address set-up time 0 - - ns tah address hold time 60 - - ns tds data set-up time 50 - - ns tdh data hold time 10 - - ns twhgl write recovery time before read 6 - - us tghwl read recovery time before write 0 - - us tcs chip enable set-up time before write 20 - - ns tch chip enable hold time 0 - - us twp write pulse width 50 - - ns twph write pulse width high 20 - - ns twhwh1 duration of programming operation 10 - 25 us flash memory ? write table rtl8139c(l)+ 2001/12/06 rev.1.5 87 11.3.2 pci bus operation timing bus cmd 7 clk 12345 6 frameb cbe3-0 ad31-0 devselb address data cbe3-0 trdyb irdyb target read bus cmd 7 clk 12345 6 frameb cbe3-0 ad31-0 devselb address data cbe3-0 trdyb irdyb target write rtl8139c(l)+ 2001/12/06 rev.1.5 88 7 clk12345 6 frameb bus cmd cbe3-0 ad31-0 idsel address data cbe3-0 trdyb irdyb devselb configuration read 7 clk 1 2 3 4 5 6 frameb bus cmd cbe3-0 ad31-0 idsel address data cbe3-0 trdyb irdyb devselb configuration write rtl8139c(l)+ 2001/12/06 rev.1.5 89 7 clk12345 6 frameb ad31-0 address data gntb reqb data bus arbitration bus cmd 8 clk12345 6 frameb cbe3-0 ad31-0 devselb address data4 cbe3-0 trdyb irdyb 7 data1 data2 data3 memory read rtl8139c(l)+ 2001/12/06 rev.1.5 90 bus cmd 8 clk12345 6 frameb cbe3-0 ad31-0 devselb address data4 cbe3-0 trdyb irdyb 7 data1 data2 data3 memory write bus cmd 8 clk12345 6 frameb cbe3-0 ad31-0 devselb lo-addr cbe3-0 trdyb irdyb 7 data1 data2 hi-addr dual ad fast medium slow dac memory read rtl8139c(l)+ 2001/12/06 rev.1.5 91 bus cmd 8 clk12345 6 frameb cbe3-0 ad31-0 devselb lo-addr cbe3-0 trdyb irdyb 7 data1 data2 hi-addr dual ad fast medium slow dac memory write clk123456 frameb ad31-0 devselb address stopb irdyb 7 data1 data2 trdyb target initiated termination - retry rtl8139c(l)+ 2001/12/06 rev.1.5 92 clk123456 frameb devselb stopb irdyb 7 trdyb target initiated termination - disconnect clk 123456 frameb devselb stopb irdyb 7 trdyb target initiated termination - abort rtl8139c(l)+ 2001/12/06 rev.1.5 93 clk 123456 frameb devselb sub 8 irdyb fast med slow 7 master initiated termination - abort bus cmd clk123456 frameb cbe[3:0]="1000? ad31-0 perrb address cbe3-0 par serrb 7 data2 data3 8 data1 addr par data2-par data3-par data1-par parity operation - one example rtl8139c(l)+ 2001/12/06 rev.1.5 94 11.3.3 mii timing mtxd[3:0] txckl txdh txckh txckf txckr mtxc mtxe txrh txds txrd txcc mii port ? transmit symbol description minimum typical maximum units txcc mtxc cycle - 40 - ns txckr mtxc rise time - 8 - ns txckf mtxc fall time - 8 - ns txckh mtxc high time 14 - 26 ns txckl mtxc low time 14 - 26 ns txds mtxd setup - - 10 ns txdh mtxd hold 10 ns txrd mtxc rise to mtxe valid time or mtxc rise to mtxd[3:0] valid time - - 12 ns txrh mtxd hold 5 - - ns mii port ? transmit table rtl8139c(l)+ 2001/12/06 rev.1.5 95 mrxd[3:0] trckl trdh trckh txckf trckr mrxc mrxdv trdh trds trds trcc mii port ? receive symbol description minimum typical maximum units trcc mrxc cycle - 40 ns trckr mrxc rise time - 8 ns trckf mrxc fall time - 8 ns trckh mrxc high time 14 - 26 ns trckl mrxc low time 14 - 26 ns trds mrxd[3:0] setup to mrxc rise time or mrxdv setup to mrxc rise time 10 - ns trdh mrxdv hold to after mrxc rise time or mrxd[3:0] hold to after mrxc rise time 10 ns mii port ? transmit table rtl8139c(l)+ 2001/12/06 rev.1.5 96 mrxc mrxer trhf trsf mii port - receive error mtxc tchf tcsf mcol mii port - carrier sense and collision symbol description minimum typical maximum units trsf/tcsf mrxer (mcol) setup to mrxc (mtxc) fall time 10 - 20 ns trhf/tchf mrxer (mcol) hold to mrxc (mtxc) fall time 10 - 18 ns mii port - carrier sense and collision table rtl8139c(l)+ 2001/12/06 rev.1.5 97 mdio tmckl write tmckh mdc tmds tmcc tmdih read write tmdh read tmlz tmdi tmhz mii management port symbol description minimum typical maximum units tmcc mdc cycle time 50 - - ns tmckh mdc high time 25 - - ns tmckl mdc low time 25 - - ns tmds mdio set up (as output pin) 10 - - ns tmdh mdio hold (as output pin) 5 ns tmlz mdc rising clock to mdio (as input pin) low impedance - - 40 ns tmhz mdc rising clock to mdio (as input pin) high impedance - - 20 ns tmdi mdio (as input pin) valid from mdc rising edge - - 40 ns tmdih mdio (as input pin) hold from mdc rising edge 5 ns mii management port table rtl8139c(l)+ 2001/12/06 rev.1.5 98 12. mechanical dimensions notes: symbol dimension in inch dimension in mm 1. dimension d & e do not include interlead flash. min typical max min typical max 2. dimension b does not include dambar protrusion/intrusion. a - - 0.134 - - 3.40 3. contro lling dimension: millimeter a1 0.004 0.010 0.036 0.10 0.25 0.91 4. general appearance spec. should be based on final visual a2 0.102 0.112 0.122 2.60 2.85 3.10 inspection spec. b 0.005 0.009 0.013 0.12 0.22 0.32 c 0.002 0.006 0.010 0.05 0.15 0.25 d 0.541 0.551 0.561 13.75 14.00 14.25 title: 128 qfp (14x20 mm ) package outline e 0.778 0.787 0.797 19.75 20.00 20.25 -cu l/f, footprint 3.2 mm e 0.010 0.020 0.030 0.25 0.5 0.75 leadframe material: h d 0.665 0.677 0.689 16.90 17.20 17.50 approve doc. no. 530-ass-p004 h e 0.902 0.913 0.925 22.90 23.20 23.50 version 1 l 0.027 0.035 0.043 0.68 0.88 1.08 page of l 1 0.053 0.063 0.073 1.35 1.60 1.85 check dwg no. q128 - 1 y - - 0.004 - - 0.10 date nov. 4 1999 0 - 12 0 - 12 realtek semi-conductor co., ltd rtl8139c(l)+ 2001/12/06 rev.1.5 99 notes: symbol dimension in inch dimension in mm 1.dimension b does not include dambar protrusion/intrusion. min typical max min typical max 2.controlling dimension: millimeter a - - 0.067 - - 1.70 3.general appearance sp ec. should be based on final visual a1 0.000 0.004 0.008 0.00 - 0.25 inspection spec. a2 0.051 0.055 0.059 1.30 1.40 1.50 b 0.006 0.009 0.011 0.15 0.22 0.29 c 0.004 - 0.006 0.09 - 0.20 title: 128ld lqfp ( 14x20x1.4 mm*2 ) package outline d 0.541 0.551 0.561 13.75 14.00 14.25 -cu l/f, footprint 2.0 mm e 0.778 0.787 0.797 19.75 20.00 20.25 leadframe material: e 0.020 bsc 0.50 bsc approve doc. no. 530-ass-p004 h d 0.620 0.630 0.640 15.90 16.00 16.30 version 1 h e 0.855 0.866 0.877 21.70 22.00 23.30 page of l 0.016 0.024 0.031 0.45 0.60 0.75 check dwg no. lq128 - 1 l 1 0.039 ref 1.00 ref date nov. 4.1999 0 3.5 9 0 3.5 9 realtek semi-conductor co., ltd rtl8139c(l)+ 2001/12/06 rev.1.5 100 realtek semiconductor corp. headquarters 1f, no. 2, industry east road ix, science-based industrial park, hsinchu, 300, taiwan, r.o.c. tel : 886-3-5780211 fax : 886-3-5776047 www: www.realtek.com.tw |
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