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september 2003 1 document control # ml0014 rev 0.1 pin configurations v cap a 14 a 12 a 7 a 6 a 5 a 4 a 3 nc a 2 a 1 a 0 dq 0 dq 1 dq 2 v ss v ccx hsb a 13 a 8 a 9 a 11 g nc a 10 e dq 7 dq 6 dq 5 dq 4 dq 3 w 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 32 - lcc 32 - dip 32 - soic pin names a 0 - a 14 address inputs dq 0 -dq 7 data in/out e chip enable w write enable g output enable hsb hardware store busy (i/o) v ccx power (+ 5v) v cap capacitor v ss ground stk14c88 32k x 8 autostore ?nvsram quantumtrap ? cmos nonvolatile static ram features ? 25ns, 35ns and 45ns access times ? ?hands-off? automatic store with external 68 f capacitor on power down ? store to nonvolatile elements initiated by hardware, software or autostore ? ? recall to sram initiated by software or power restore ? 10ma typical i cc at 200ns cycle time ? unlimited read, write and recall cycles ? 1,000,000 store cycles to nonvolatile ele- ments (commerc ial/industrial) ? 100-year data retention in nonvolatile ele- ments (commerc ial/industrial) ? single 5v + 10% operation ? commercial, industrial and military tempera- tures ? 32-pin soic, dip and lcc packages description the simtek stk14c88 is a fast static ram with a nonvolatile element incorporated in each static memory cell. the sram can be read and written an unlimited number of time s, while independent, non- volatile data resides in the nonvolatile elements. data transfers from the sram to the nonvolatile ele- ments (the store operation) can take place auto- matically on power down. a 68 f or larger capacitor tied from v cap to ground guarantees the store operation, regardless of power-down slew rate or loss of power from ?hot swapping?. transfers from the nonvolatile elements to the sram (the recall operation) take place automatically on restoration of power. initiation of store and recall cycles can also be software controlled by entering specific read sequences. a hardware store may be initiated with the hsb pin. block diagram a 0 a 1 a 2 a 3 a 4 a 10 column i/o column dec static ram array 512 x 512 row decoder input buffers quantum trap 512 x 512 store/ recall control store recall power control a 5 a 6 a 7 a 8 a 9 a 11 a 12 a 13 a 14 dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 software detect g e w hsb v ccx v cap a 0 - a 13
stk14c88 september 2003 2 document control # ml0014 rev 0.1 absolute maximum ratings a voltage on input relative to ground . . . . . . . . . . . . . ?0.5v to 7.0v voltage on input relative to v ss . . . . . . . . . .?0.6v to (v cc + 0.5v) voltage on dq 0-7 or hsb . . . . . . . . . . . . . . . .?0.5v to (v cc + 0.5v) temperature under bias. . . . . . . . . . . . . . . . . . . . . .?55 c to 125 c storage temperature . . . . . . . . . . . . . . . . . . . . . . . .?65 c to 150 c power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1w dc output current (1 output at a time, 1s duration) . . . . . . . 15ma note a: stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at con- ditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rat- ing conditions for extended periods may affect reliability. dc characteristics (v cc = 5.0v 10%) e note b: i cc 1 and i cc 3 are dependent on output loading and cycle rate. the specified values are obtained with outputs unloaded. note c: i cc 2 and i cc 4 are the average currents required for the duration of the respective store cycles (t store ). note d: e v ih will not produce standby current levels until any nonvolatile cycle in progress has timed out. note e: v cc reference levels throughout this datasheet refer to v ccx if that is where the power supply connection is made, or v cap if v ccx is con- nected to ground. symbol parameter commercial industrial/ military units notes min max min max i cc 1 b average v cc current 97 80 70 100 85 70 ma ma ma t avav = 25ns t avav = 35ns t avav = 45ns i cc 2 c average v cc current during store 3 3 ma all inputs don?t care, v cc = max i cc 3 b average v cc current at t avav = 200ns 5v, 25c, typical 10 10 ma w (v cc ? 0.2v) all others cycling, cmos levels i cc 4 c average v cap current during autostore ? cycle 22ma all inputs don?t care i sb 1 d average v cc current (standby, cycling ttl input levels) 30 25 22 31 26 23 ma ma ma t avav = 25ns, e v ih t avav = 35ns, e v ih t avav = 45ns, e v ih i sb 2 d v cc standby current (standby, stable cmos input levels) 1.5 1.5 ma e (v cc ? 0.2v) all others v in 0.2v or (v cc ? 0.2v) i ilk input leakage current 1 1 a v cc = max v in = v ss to v cc i olk off-state output leakage current 5 5 a v cc = max v in = v ss to v cc , e or g v ih v ih input logic ?1? voltage 2.2 v cc + .5 2.2 v cc + .5 v all inputs v il input logic ?0? voltage v ss ? .5 0.8 v ss ? .5 0.8 v all inputs v oh output logic ?1? voltage 2.4 2.4 v i out = ? 4ma except hsb v ol output logic ?0? voltage 0.4 0.4 v i out = 8ma except hsb v bl logic ?0? voltage on hsb output 0.4 0.4 v i out = 3ma t a operating temperature 0 70 ?40/-55 85/125 c ac test conditions capacitance f (t a = 25 c, f = 1.0mhz) note f: these parameters are guaranteed but not tested. input pulse levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0v to 3v input rise and fall times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5ns input and output timing reference levels . . . . . . . . . . . . . . . 1.5v output load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see figure 1 symbol parameter max units conditions c in input capacitance 5 pf ? v = 0 to 3v c out output capacitance 7 pf ? v = 0 to 3v figure 1 : ac output loading 480 ohms 30 pf 255 ohms 5.0v including scope and output fixture
stk14c88 september 2003 3 document control # ml0014 rev 0.1 sram read cycles #1 & #2 (v cc = 5.0v 10%) e note g: w and hsb must be high during sram read cycles and low during sram write cycles. note h: i/o state assumes e and g < v il and w > v ih ; device is continuously selected. note i: measured 200mv from steady state output voltage. sram read cycle #1: address controlled g , h sram read cycle #2: e controlled g no. symbols parameter stk14c88-25 stk14c88-35 stk14c88-45 units #1, #2 alt. min max min max min max 1t elqv t acs chip enable access time 25 35 45 ns 2t avav g t rc read cycle time 25 35 45 ns 3t avqv h t aa address access time 25 35 45 ns 4t glqv t oe output enable to data valid 10 15 20 ns 5t axqx h t oh output hold after address change 5 5 5 ns 6t elqx t lz chip enable to output active 5 5 5 ns 7t ehqz i t hz chip disable to output inactive 10 13 15 ns 8t glqx t olz output enable to output active 0 0 0 ns 9t ghqz i t ohz output disable to output inactive 10 13 15 ns 10 t elicch f t pa chip enable to power active 0 0 0 ns 11 t ehiccl f t ps chip disable to power standby 25 35 45 ns data valid 5 t axqx 3 t avqv dq (data out) address 2 t avav 6 t elqx standby data valid 4 t glqv dq (data out) e address 2 t avav g i cc active 10 t elicch 1 1 t ehiccl 7 t ehqz 8 t glqx 1 t elqv 9 t ghqz
stk14c88 september 2003 4 document control # ml0014 rev 0.1 sram write cycles #1 & #2 (v cc = 5.0v 10%) e note j: if w is low when e goes low, the outputs remain in the high-impedance state. note k: e or w must be v ih during address transitions. note l: hsb must be high during sram write cycles. sram write cycle #1: w controlled k, l sram write cycle #2: e controlled k, l no. symbols parameter stk14c88-25 stk14c88-35 stk14c88-45 units #1 #2 alt. min max min max min max 12 t avav t avav t wc write cycle time 25 35 45 ns 13 t wlwh t wleh t wp write pulse width 20 25 30 ns 14 t elwh t eleh t cw chip enable to end of write 20 25 30 ns 15 t dvwh t dveh t dw data set-up to end of write 10 12 15 ns 16 t whdx t ehdx t dh data hold after end of write 0 0 0 ns 17 t avwh t aveh t aw address set-up to end of write 20 25 30 ns 18 t avwl t avel t as address set-up to start of write 0 0 0 ns 19 t whax t ehax t wr address hold after end of write 0 0 0 ns 20 t wlqz i, j t wz write enable to output disable 10 13 15 ns 21 t whqx t ow output active after end of write 5 5 5 ns previous data data out e address 12 t avav w 16 t whdx data in 19 t whax 13 t wlwh 18 t avwl 17 t avwh data valid 20 t wlqz 15 t dvwh high impedance 21 t whqx 14 t elwh data in 12 t avav 16 t ehdx 13 t wleh 19 t ehax 18 t avel 17 t aveh data valid 15 t dveh high impedance 14 t eleh data out e address w data in
stk14c88 september 2003 5 document control # ml0014 rev 0.1 hardware mode selection note m: hsb store operation occurs only if an sram write has been done since the last nonvolatile cycle. after the store (if any) completes, the part will go into standby mode, inhibiting all operations until hsb rises. hardware store cycle (v cc = 5.0v 10%) e note n: e and g low and w high for output behavior. note o: t recover is only applicable after t store is complete. hardware store cycle e w hsb a 13 - a 0 (hex) mode i/o power notes h x h x not selected output high z standby l h h x read sram output data active t l l h x write sram input data active x x l x nonvolatile store output high z l cc 2 m no. symbols parameter stk14c88 units notes standard alternate min max 22 t store t hlhz store cycle duration 10 ms i, n 23 t delay t hlqz time allowed to complete sram cycle 1 si, n 24 t recover t hhqx hardware store high to inhibit off 700 ns n, o 25 t hlhx hardware store pulse width 15 ns 26 t hlbl hardware store low to store busy 300 ns data valid hsb (in) data valid 25 t hlhx 23 t delay 22 t store 24 t recover high impedance 26 t hlbl high impedance dq (data out) hsb (out)
stk14c88 september 2003 6 document control # ml0014 rev 0.1 autostore ?/power-up recall (v cc = 5.0v 10%) e note p: t restore starts from the time v cc rises above v switch . note q: hsb is asserted low for 1 s when v cap drops through v switch . if an sram write has not taken place since the last nonvolatile cycle, hsb will be released and no store will take place. autostore ?/power-up recall no. symbols parameter stk14c88 units notes standard alternate min max 27 t restore power-up recall duration 550 sp 28 t store t hlhz store cycle duration 10 ms n, q 29 t vsbl low voltage trigger (v switch ) to hsb low 300 ns l 30 t delay t blqz time allowed to complete sram cycle 1 sn 31 v switch low voltage trigger level 4.0 4.5 v 32 v reset low voltage reset level 3.6 v 30 t delay 29 t vsbl power-up recall brown out no store (no sram writes) no recall (v cc did not go below v reset ) brown out autostore ? no recall (v cc did not go below v reset ) brown out autostore ? recall when v cc returns above v switch autostore ? hsb w 28 t store 27 t restore power-up recall 31 v switch 32 v reset v cc dq (data out)
stk14c88 september 2003 7 document control # ml0014 rev 0.1 software store / recall mode selection software-controlled store / recall cycle v (v cc = 5.0v 10%) e note r: the six consecutive addresses must be in the order listed. w must be high during all six consecutive cycles to enable a nonvolatile cycle. note s: while there are 15 addresses on the stk14c88, only the lower 14 are used to control software modes. note t: i/o state assumes g < v il . activation of nonvolatile cycles does not depend on state of g . note u: the software sequence is clocked with e controlled reads. note v: the six consecutive addresses must be in the order listed in the hardware mode selection table: (0e38, 31c7, 03e0, 3c1f, 303f, 0fc0) for a store cycle or (0e38, 31c7, 03e0, 3c1f, 303f, 0c63) for a recall cycle. w must be high during all six consecutive cycles. software store / recall cycle: e controlled v e w a 13 - a 0 (hex) mode i/o power notes lh 0e38 31c7 03e0 3c1f 303f 0fc0 read sram read sram read sram read sram read sram nonvolatile store output data output data output data output data output data output high z active l cc 2 r, s, t lh 0e38 31c7 03e0 3c1f 303f 0c63 read sram read sram read sram read sram read sram nonvolatile recall output data output data output data output data output data output high z active r, s, t no. symbols parameter stk14c88-25 stk14c88-35 stk14c88-45 units notes standard alternate min max min max min max 33 t avav t rc store / recall initiation cycle time 25 35 45 ns n 34 t avel t as address set-up time 0 0 0 ns u 35 t eleh t cw clock pulse width 20 25 30 ns u 36 t elax address hold time 20 20 20 ns u 37 t recall recall duration 20 20 20 s data valid high impedance address #6 address #1 data valid 33 t avav data valid dq (data e address 28 37 t store / t recall 33 t avav 34 t avel 35 t eleh 36 t elax
stk14c88 september 2003 8 document control # ml0014 rev 0.1 the stk14c88 has two separate modes of opera- tion: sram mode and nonvolatile mode. in sram mode, the memory opera tes as a standard fast static ram . in nonvolatile mode, data is transferred from sram to nonvolatile elements (the store operation) or from nonvolatile elements to sram (the recall operation). in this mode sram func- tions are disabled. noise considerations the stk14c88 is a high-speed memory and so must have a high-frequency bypass capacitor of approximately 0.1 f connected between v cap and v ss , using leads and traces that are as short as pos- sible. as with all high-speed cmos ics, normal care- ful routing of power, ground and signals will help prevent noise problems. sram read the stk14c88 performs a read cycle whenever e and g are low and w and hsb are high. the address specified on pins a 0-14 determines which of the 32,768 data bytes will be accessed. when the read is initiated by an address transition, the out- puts will be valid after a delay of t avqv ( read cycle #1). if the read is initiated by e or g , the outputs will be valid at t elqv or at t glqv , whichever is later ( read cycle #2). the data outputs will repeatedly respond to address changes within the t avqv access time with- out the need for transitions on any control input pins, and will remain valid until another address change or until e or g is brought high, or w or hsb is brought low. sram write a write cycle is performed whenever e and w are low and hsb is high. the address inputs must be stable prior to entering the write cycle and must remain stable until either e or w goes high at the end of the cycle. the data on the common i/o pins dq 0-7 will be written into the memory if it is valid t dvwh before the end of a w controlled write or t dveh before the end of an e controlled write . it is recommended that g be kept high during the entire write cycle to avoid data bus contention on common i/o lines. if g is left low, internal circuitry will turn off the output buffers t wlqz after w goes low. power-up recall during power up, or after any low-power condition (v cap < v reset ), an internal recall request will be latched. when v cap once again exceeds the sense voltage of v switch , a recall cycle will automatically be initiated and will take t restore to complete. if the stk14c88 is in a write state at the end of power-up recall , the sram data will be corrupted. to help avoid this situation, a 10k ohm resistor should be connected either between w and system v cc or between e and system v cc . software nonvolatile store the stk14c88 software store cycle is initiated by executing sequential e controlled read cycles from six specific address locations. during the store cycle an erase of the previous nonvolatile data is first performed, followed by a program of the nonvol- atile elements. the program operation copies the sram data into nonvolatile memory. once a store cycle is initiated, further input and output are dis- abled until the cycle is completed. because a sequence of read s from specific addresses is used for store initiation, it is impor- tant that no other read or write accesses inter- vene in the sequence, or the sequence will be aborted and no store or recall will take place. to initiate the software store cycle, the following read sequence must be performed: 1. read address 0e38 (hex) valid read 2. read address 31c7 (hex) valid read 3. read address 03e0 (hex) valid read 4. read address 3c1f (hex) valid read 5. read address 303f (hex) valid read 6. read address 0fc0 (hex) initiate store cycle the software sequence must be clocked with e con- trolled read s. once the sixth address in the sequence has been entered, the store cycle will commence and the chip will be disabled. it is important that read cycles and not write cycles be used in the sequence, although it is not necessary that g be low for the sequence to be valid. after the t store cycle time has been fulfilled, the sram will again be activated for read and write operation. device operation
stk14c88 september 2003 9 document control # ml0014 rev 0.1 software nonvolatile recall a software recall cycle is initiated with a sequence of read operations in a manner similar to the soft- ware store initiation. to initiate the recall cycle, the following sequence of e controlled read opera- tions must be performed: 1. read address 0e38 (hex) valid read 2. read address 31c7 (hex) valid read 3. read address 03e0 (hex) valid read 4. read address 3c1f (hex) valid read 5. read address 303f (hex) valid read 6. read address 0c63 (hex) initiate recall cycle internally, recall is a two-step procedure. first, the sram data is cleared, and second, the nonvolatile information is transferred into the sram cells. after the t recall cycle time the sram will once again be ready for read and write operations. the recall operation in no way alters the data in the nonvolatile elements. the nonvolatile data can be recalled an unlimited number of times. autostore ? operation the stk14c88 can be powered in one of three modes. during normal autostore ? operation, the stk14c88 will draw current from v ccx to charge a capacitor connected to the v cap pin. this stored charge will be used by the chip to perform a single store operation. after power up, when the voltage on the v cap pin drops below v switch , the part will automatically disconnect the v cap pin from v ccx and initiate a store operation. figure 2 shows the proper connection of capacitors for automatic store opera tion. a charge storage capacitor having a capacity of between 68 f and 220 f ( 20%) rated at 6v should be provided. in system power mode (figure 3), both v ccx and v cap are connected to the + 5v power supply without the 68 f capacitor. in this mode the autostore ? function of the stk14c88 will operate on the stored system charge as power goes down. the user must, however, guarantee that v ccx does not drop below 3.6v during the 10ms store cycle. if an automatic store on power loss is not required, then v ccx can be tied to ground and + 5v applied to v cap (figure 4). this is the autostore ? inhibit mode, in which the autostore ? function is disabled. if the stk14c88 is operated in this configuration, references to v ccx should be changed to v cap throughout this data sheet. in this mode, store operations may be triggered through software con- trol or the hsb pin. it is not permissable to change between these three options ?on the fly?. in order to prevent unneeded store operations, automatic store s as well as those initiated by externally driving hsb low will be ignored unless at least one write operation has taken place since the most recent store or recall cycle. software- initiated store cycles are performed regardless of whether a write operation has taken place. an optional pull-up resistor is shown connected to hsb . this can be used to si gnal the system that the autostore ? cycle is in progress. figure 2: autostore ? mode 1 16 32 31 17 68 f 6v, 20% 0.1 f bypass 30 + 10k ? 10k ?? figure 3: system power mode 1 16 32 31 17 30 0.1 f bypass 10k ?? 10k ? figure 4: autostore ? inhibit mode 1 16 32 31 17 0.1 f bypass 30 10k ?? 10k ? *if hsb is not used, it should be left unconnected.
stk14c88 september 2003 10 document control # ml0014 rev 0.1 if the power supply drops faster than 20 s/volt before v ccx reaches v switch , then a 2.2 ohm resistor should be inserted between v ccx and the system supply to avoid momentary excess of current between vccx and vcap. hsb operation the stk14c88 provides the hsb pin for controlling and acknowledging the store operations. the hsb pin can be used to request a hardware store cycle. when the hsb pin is driven low, the stk14c88 will conditionally initiate a store operation after t delay ; an actual store cycle will only begin if a write to the sram took place since the last store or recall cycle. the hsb pin also acts as an open drain driver that is internally driven low to indicate a busy condition while the store (initiated by any means) is in progress. sram read and write operations that are in progress when hsb is driven low by any means are given time to complete before the store operation is initiated. after hsb goes low, the stk14c88 will continue sram operations for t delay . during t delay , multiple sram read operations may take place. if a write is in progress when hsb is pulled low it will be allowed a time, t delay , to complete. however, any sram write cycles requested after hsb goes low will be inhibited until hsb returns high. the hsb pin can be used to synchronize multiple stk14c88s while using a single larger capacitor. to operate in this mode the hsb pin should be con- nected together to the hsb pins from the other stk14c88s. an external pull-up resistor to + 5v is required since hsb acts as an open drain pull down. the v cap pins from the other stk14c88 parts can be tied together and share a single capacitor. the capacitor size must be scaled by the number of devices connected to it. when any one of the stk14c88s detects a power loss and asserts hsb , the common hsb pin will cause all parts to request a store cycle (a store will take place in those stk14c88s that have been written since the last nonvolatile cycle). during any store operation, regardless of how it was initiated, the stk14c88 will continue to drive the hsb pin low, releasing it only when the store is complete. upon completion of the store operation the stk14c88 will remain disabled until the hsb pin returns high. if hsb is not used, it should be left unconnected. preventing stores the store function can be disabled on the fly by holding hsb high with a driver capable of sourcing 30ma at a v oh of at least 2.2v, as it will have to overpower the internal pull-down device that drives hsb low for 20 s at the onset of a store . when the stk14c88 is connected for autostore ? opera- tion (system v cc connected to v ccx and a 68 f capacitor on v cap ) and v cc crosses v switch on the way down, the stk14c88 will attempt to pull hsb low; if hsb doesn?t actually get below v il , the part will stop trying to pull hsb low and abort the store attempt. hardware protect the stk14c88 offers hardware protection against inadvertent store operation and sram write s dur- ing low-voltage conditions. when v cap < v switch , all externally initiated store operations and sram write s will be inhibited. autostore ? can be completely disabled by tying v ccx to ground and applying + 5v to v cap . this is the autostore ? inhibit mode; in this mode store s are only initiated by explicit re quest using either the soft- ware sequence or the hsb pin. low average active power the stk14c88 draws significantly less current when it is cycled at times longer than 50ns. figure 5 shows the relationship between i cc and read cycle time. worst-case current consumption is shown for both cmos and ttl input levels (commercial tem- perature range, v cc = 5.5v, 100% duty cycle on chip enable). figure 6 shows the same relationship for write cycles. if the chip ena ble duty cycle is less than 100%, only standby current is drawn when the chip is disabled. the overall average current drawn by the stk14c88 depends on the following items: 1) cmos vs. ttl input levels; 2) the duty cycle of chip enable; 3) the overall cycle rate for accesses; 4) the ratio of read s to write s; 5) the operating temperature; 6) the v cc level; and 7) i/o loading.
stk14c88 september 2003 11 document control # ml0014 rev 0.1 figure 5: i cc (max) reads 0 20 40 60 80 100 50 100 150 200 cycle time (ns) ttl cmos average active current (ma) figure 6: i cc (max) writes 0 20 40 60 80 100 50 100 150 200 cycle time (ns) ttl cmos average active current (ma)
stk14c88 september 2003 12 document control # ml0014 rev 0.1 ordering information temperature range blank = commercial (0 to 70c) i = industrial (-40 to 85c) m = military (-55 to 125c) access time 25 = 25ns 35 = 35ns 45 = 45ns lead finish (plastic only) blank = 85%sn/15%pb f = 100% sn (matte tin) package n = plastic 32-pin 300 mil soic w = plastic 32-pin 600 mil dip l = ceramic 32-pad lcc c = ceramic 32-pin 300 mil cdip k = ceramic 32-pin 300 mil cdip with solder dip finish stk14c88 - n f 45 i
stk14c88 september 2003 13 document control # ml0014 rev 0.1 document revision history revision date summary 0.0 december 2002 removed 20 nsec device; combined commercial, industrial and milit ary; current limit resistor added for extreme power-off slew rate. 0.1 september 2003 added lead-free lead finish

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