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| to our customers, old company name in catalogs and other documents on april 1 st , 2010, nec electronics corporation merged with renesas technology corporation, and renesas electronics corporation took over all the business of both companies. therefore, although the old company name remains in this document, it is a valid renesas electronics document. we appreciate your understanding. renesas electronics website: http://www.renesas.com april 1 st , 2010 renesas electronics corporation issued by: renesas electronics corporation ( http://www.renesas.com ) send any inquiries to http://www.renesas.com/inquiry . not recommend for new design
notice 1. all information included in this document is current as of th e date this document is issued. such information, however, is subject to change without any prior notice. before purchasing or using any renesas electronics products listed herein, please confirm the latest product information with a renesas electronics sales office. also, please pay regular and careful attention to additional and different information to be disclosed by renesas electronics such as that disclosed through our website. 2. renesas electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property ri ghts of third parties by or arising from the use of renesas electronics products or technical information described in this document . no license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property right s of renesas electronics or others. 3. you should not alter, modify, copy, or otherwise misappropriate any renesas electronics product, whether in whole or in part . 4. descriptions of circuits, software and other related information in this document are provided only to illustrate the operat ion of semiconductor products and application examples. you are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 5. when exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. you should not use renesas electronics products or the technology de scribed in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. renesas electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 6. renesas electronics has used reasonable care in preparing the information included in this document, but renesas electronics does not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or om issions from the information included herein. 7. renesas electronics products are classified according to the following three quality grades: ?standard?, ?high quality?, an d ?specific?. the recommended applications for each renesas electronics product depends on the product?s quality grade, as indicated below. you must check the quality grade of each renesas electronics product before using it in a particular application. you may not use any renesas electronics product for any application categorized as ?specific? without the prior written consent of renesas electronics. further, you may not use any renesas electronics product for any application for which it is not intended without the prior written consent of renesas electronics. renesas electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any renesas electronics product for a n application categorized as ?specific? or for which the product is not intended where you have failed to obtain the prior writte n consent of renesas electronics. the quality grade of each renesas electronics product is ?standard? unless otherwise expressly specified in a renesas electronics data sheets or data books, etc. ?standard?: computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots. ?high quality?: transportation equipment (automobiles, trains, ship s, etc.); traffic control systems; anti-disaster systems; an ti- crime systems; safety equipment; and medical equipment not specifically designed for life support. ?specific?: aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life. 8. you should use the renesas electronics products described in this document within the range specified by renesas electronics , especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas electronics shall have no liability for malfunctions o r damages arising out of the use of renesas electronics products beyond such specified ranges. 9. although renesas electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. fur ther, renesas electronics products are not subject to radiation resistance design. please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a renesas electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 10. please contact a renesas electronics sales office for details as to environmental matters such as the environmental compatibility of each renesas electronics product. please use re nesas electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of c ontrolled substances, including without limitation, the eu rohs directive. renesas electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 11. this document may not be reproduced or duplicated, in any fo rm, in whole or in part, without prior written consent of renes as electronics. 12. please contact a renesas electronics sales office if you have any questions regarding the information contained in this document or renesas electronics products, or if you have any other inquiries. (note 1) ?renesas electronics? as used in this document means renesas electronics corporation and also includes its majority- owned subsidiaries. (note 2) ?renesas electronics product(s)? means any product developed or manufactured by or for renesas electronics. not recommend for new design rev.1.0, sep.22.2 003, page 1 of 15 M61251AFP single-chip ntsc tv signal processor rej03f0078-0100z rev.1.0 sep.22.2003 description the M61251AFP is a single-chip tv-signal processor ic for the ntsc format and is ideal for use in combination with a microcomputer. processing circuits for all signals, including intermediate-frequency video and audio, video, color, the on-screen display of characters, and the deflection system are all included, and various functions are controllable via an i 2 c bus. furthermore, a reset circuit, clock circuit, and regulator are included for use with microcomputers. features ? handling of vif does not require a vco coil ? adjustment-free audio demodulator ? pll-split sif system w ith fm radio function ? supports component video-signal input ? fsc output available ? acl or abcl is selectable ? built-in horizontal oscillator ? built-in sawtooth waveform ge nerator for vertical sync ? self-diagnostic function ? built-in black-peak hold, afc2, color killer filter ? horizontal / vertical pulse output for osd ? built-in microcomputer reset circuit ? built-in microcomputer clock output ? built-in 5- and 8-v regulators M61251AFP rev.1.0, sep.22.2 003, page 2 of 15 block diagram M61251AFP rev.1.0, sep.22.2 003, page 3 of 15 pin configuration vif vco feed bac k fm direct out ext audio in vif apc filter rf agc out audio bypass vif agc filter1 vif agc filter2 intercarrier out intelligent monitor hvco feed back y sw out nc def vcc video out 5.7v reg out drive gnd chroma apc filte r video/chroma vcc drive vcc video/chroma gnd inverted fbp out p-on control 1 2 3 4 5 6 7 8 9 10 11 12 13 14 27 28 29 31 17 18 19 20 21 22 23 24 25 26 42 41 40 39 38 37 36 35 34 33 43 45 46 44 61 62 55 54 53 52 51 50 49 57 58 59 60 15 16 30 32 48 47 63 64 56 M61251AFP vif vcc sif vcc h out afc filter logic gnd fbp in aft out def gnd b out r out g out ramp out v ramp f/b v ramp cap vif in(1) sif gnd vif gnd audio out vif in(2) tv/y in vreg vcc ext/c in hi vcc limiter in x-tal 3.58 acl/abcl 8.7v reg out audio att filter cr in cb in v pulse out b in r in scl fsc out1 g in mcu reset fast blk sda mcu 5.7v reg out clock control absolute maximum, ratings symbol parameter ratings unit vcc supply voltage 6.0, 10.0 v pd power dissipation 1325 mw kt thermal derating 10.6 mw / c topr operating temperature ?20 to + 65 c tstg storage temperature ?40 to +150 c recommended operating conditions supply-voltage terminals blocks voltage pins 3 and 4 vif / sif 5.0 v pins 39 and 40 video, chroma 5.0 v pin 12 deflection/cmos (start - up vcc) 8.0 v pin 44 sif/att, deflection, rgb 8.0 v pin 42 power supply 8.7 v gnd terminals blocks pins 56 and 57 vif / sif pins 35 and 36 video, chroma pins 8 and 9 deflection, cmos M61251AFP rev.1.0, sep.22.2 003, page 4 of 15 electrical characteristics function block parameter specification (typ.) pin no. condition gain-control range 45 to 108db if amplifier input impedance 2 k ? , 5pf 63.64 video output level 1.2 vpp negative sync. i 2 c video-output gain range + / ? 0.1 vpp i 2 c: 3 bits video s / n 54 db video frequency response 6 mhz ?3db dg / dp 3% / 3deg video detector intermodulation 50 db 58 frequency 45.75 / 58.75 mhz vco iic ?vif vco adj? range + / ?4 mhz ? i 2 c: 6bit pll capture range + / ?2 mhz ? if agc if agc range 45 to 107 db ? output range 0.3 to 4.7 v rf agc i 2 c rf delay adj. range 60 to 110 db 59 i 2 c: 7bit output range 0.3 to 4.7 v sensitivity 10 mv / khz 2 below 100 khz between 100 khz and f0 between f0 and +100 khz vif aft i 2 c output over +100 khz ?i 2 c ?afto / aft1? limiter limiting sensitivity 43 db 48 fm detector pll capture range 4.5 mhz +/ ?1.0 mhz ? fm direct output level (tv) 500 mvrms input 4.5 mhz / 25 khz 100db af s/n 60 db amr 55 db af amplifier distortion (t.h.d) 1% 54 sif audio att control range tv / ext crosstalk ?70 to 0 db ?70 db 51 M61251AFP rev.1.0, sep.22.2 003, page 5 of 15 electrical characteristics (cont) function block parameter specification (typ.) pin no. condition video switch tv / ext crosstalk ?55db 31 at 5 mhz center frequency 3.58 mhz suppression at subcarrier frequency (fsc) ?30db suppression at fsc+/-100 khz ?25db suppression at fsc+/-500 khz ?10db chroma trap trap fine adjustment ? i 2 c: 2bits delay time 125 ns peak frequency for emphasis 2.5 mhz video tone control range ?2.5 to +10db ? i 2 c: 6 bits delay-time adjustment 125 / 250 / 400 / 550nsec i 2 c: 2 bits delay line delay fine adjustment 0 / 80nsec ? i 2 c: 1 bit start point 60 i re end stop 8 ire black stretch max. effect 6db (25 ire) ? gain 6db y sw out y sw lpf cut-off frequency 700 khz 31 i 2 c ?y sw lpf? : 1 video video mute mute suppression (y) ?45db 14. 15. 16 center frequency 3.58 mhz chroma bpf 2 - mhz suppression ?22 db ? acc range +6 to ?22 db acc overload chroma 169% ? fo 3.579545 mhz 14, 15, 16 fsc out 1 level - 1 1vpp pin25 clk cont : high vcxo fsc out 1 level - 2 off 29 pin25 clk cont : low apc pull - in + / ?600 hz 14, 15, 16 apc filter 1 f+4.7k//0.015 f color killer level ?45db color killer detector suppression ?40db ? tint control +/- 45deg i 2 c 7bit demodulation angle 103deg / 95deg i 2 c?c angle 95? carrier leakage ?40db chroma demodulator demodulation ratio (b - y) : (r ?y) = 1:0.55 ? M61251AFP rev.1.0, sep.22.2 003, page 6 of 15 electrical characteristics (cont) function block parameter specification (typ.) pin no. condition color control i 2 c: 7 bits max. attenuation matrix ?45db 14, 15, 16 b / w mode at i 2 c data = 0 input level digital: 1 vp-p analog: 0.7 vp-p i 2 c analog osd? osd speed (rise) 0.02 s external rgb osd speed (fall) 0.02 s 21, 22, 23 ?40 to 3db 14, 15, 16 i 2 c: 7 bits contrast control range of control external control 33 decoupling 0.1 f ?0.85 to + 0.85 v 14, 15, 16 i 2 c: 8 bits brightness control range of control external control 33 de-coupling 0.1 f drive control range of control + / -3db (r / b) 14, 16 i 2 c: 7 bits cut-off range of control + 0.9 to ?0.9 v 14, 15, 16 output pedestal voltage 2.4 v open emitter output distribution of output voltage less than 300 mw clamp ability 100% rgb rgb out output blanking voltage 0.3 v 14, 15, 16 pin 32 voltage detection 4.2 v reset polarity low reset mcu reset reset maximum sink current 4 ma 30 vreg vcc supply voltage (p-on) 8.7 v 42 output voltage 5.7 v mcu 5.7 v regout maximum output current 2.5 ma 32 output voltage 5.7 v pin 28 (power on control) = 5 v 5.7 v regout maximum output current 5 ma 49 pin 28 (power on control) = 5 v output voltage 1 8.7 v pin 28 (power on control) = 0 v output voltage 2 0 v power supply 8.7 regout maximum output current 1 ma 47 M61251AFP rev.1.0, sep.22.2 003, page 7 of 15 electrical characteristics (cont) function block parameter specification (typ.) pin no. condition 50% / 25% i 2 c ?s silicedown1? sync. separation slice level 50% / 45% ? i 2 c ?s silicedown2? horizontal vco free-running frequency 15.734 khz horizontal vco horizontal vco adjustment fh+ / ?500 khz 11 i 2 c: 3 bits +/?500 hz (normal) filter 1uf 6.2 k / 0.01 uf afci horizontal pull-in range +/?800 hz (fast) 11 range of control +/?1.6 si 2 c: 5 bits horizontal pulse timing 8.5 s horizontal phase horizontal pulse width 25 s 11 inverter fbp out output range 0.1 to 5.0 v 19 vertical free- running frequency 60 hz vertical pull - in range 55 to 67 hz vertical position adjustment 8 positions i 2 c: 3 bits vertical position step 2horizontal line / step v-ramp variable range 2 vpp +/- 0.8vpp i 2 c: 7 bits v-pulse width (pulse mode) 0.5ms deflection vertical count down v-blk width (pulse mode) 1.5ms 5 acknowledge current 5 ma scl/sda vth (high) 0.75 v scl/sda vth (low) 4.25 v i 2 c bus i 2 c bus clock frequency 100 khz 26, 27 bus table slave address = bah (write), bbh (read) a6 a5 a4 a3 a2 a1 a0 r / w 10111111 / 0 M61251AFP rev.1.0, sep.22.2 003, page 8 of 15 write table (input bytes) sub address hex bin d7 d6 d5 d4 d3 d2 d1 d0 initial (inhibited) rf felay adj 00h 00000000 0 1 0 000004 0 h (inhibited) viffreq5875 vif vcd adj 01h 00000001 0 0 1 000002 0 h video mute audio ext c. clip level trap off video t sharp abcl black stre. off take off 02h 00000010 0 0 0 000000 0 h audio mute audio att 03h 00000011 0 0 0 000000 0 h abcl gain aft defeat video tone 04h 00000100 0 0 v1 v0 v0 v0 v0 v0 20h extrgb c. clip contrast control 05h 00000101 v0 v1 v0 v0 v1 v0 v0 v0 v0 v0 v0 v0 v0 v0 v0 40h vif video out gain y/c ext y dl fine adj y dl time adj 06h 00000110 1 0 0 v0 v0 0 0 0 80h vif defeat tint control 07h 00000111 0 40h blue back color control 08h 00001000 v0 v1 v0 v0 v0 v0 v0 v0 40h hv blk off vout stop fsc free htone sw (inhibited) 09h 00001001 0 0 0 001000 4 h brightness control 0ah 00001010 v1 v0 v0 v1 v0 v0 v0 v0 v0 v0 v0 v0 v0 v0 v0 80h (inhibited) drive (r) 0bh 00001011 0 1 0 000004 0 h (inhibited) drive (b) 0ch 00001100 0 1 0 000004 0 h cut off (r) 0dh 00001101 1 0 0 000008 0 h cut off (g) 0eh 00001110 1 0 0 000008 0 h cut off (b) 0fh 00001111 1 0 0 000008 0 h white back v-free (inhibited) h vco adj 10h 00010000 0 0 1 001002 4 h (inhibited) v-size 11h 00010001 0 0 1 000002 0 h monitoring gamma control trap fine adj 12h 00010010 0 0 0 000000 0 h h-free v. 1windows ysw lpf h start service sw v shift 13h 00010011 0 0 0 000000 0 h black strech discharge black strech charge s.slice down2 s.slice down1 (inhibited) 14h 00010100 0 0 0 0 0 0 1 1 03h afc1 gain afc2 gain osd level analog osd us/jpn sw killer level 15h 00010101 0 0 0 000000 0 h vsyncdet a uto slice down fbp vth l afc2 h phase 16h 00010110 1 0 0 100009 0 h yuv sw baseband tint control 17h 00010111 0 40h test1 (inhibited) 18h 00011000 0 0 0 000000 0 h bgpfbp off test2 (inhibited) 19h 00011001 0 0 0 000000 0 h test3 (inhibited) 1ah 00011010 0 0 0 000000 0 h (inhibited) 1bh 00011011 0 0 0 000000 0 h (inhibited) 1ch 00011100 0 0 0 000000 0 h data note: v0/v1 ==> v?latch bit read table (output bytes) sub address d7 d6 d5 d4 d3 d2 d1 d0 00h 00000000 killerb (not assigned) stpetb vcoinb aft 0 aft 1 hcoinb (not assigned) M61251AFP rev.1.0, sep.22.2 003, page 9 of 15 bus table write function bit sub- address data description initial value note rf delay adjustment 7 00h d0 to d6 rf agc delay point adjustment 40h vif vco adjustment 6 10h d0 to d5 vif vco free-run frequency adjustment (vif defeat = 1, aft output: center) 20h vif frequency 58, 75 1 01h d6 if output at 45.75 / 58.75 mhz. 0: 45.75 mhz, 1: 58.75 mhz 0 vif video out gain 3 06h d5 ? d7 adjustment of output level for vif-demodulated video waveform on pin 58 80h aft defeat 1 04h d6 aft output on / off (def eat). 0: aft on (non defeat), 1: defeat 0 v i f vif defeat 1 07h d7 vif gain normal/minimum. 0: agc function, 1: defeat (minimum gain) 0 audio attenuation 7 03h d0 to d6 pin 51 audio-output level adjustment 00h audio ext 1 02h d6 switches between the internal and external- input audio signals. 0: internal, 1: external 0 s i f audio mute 1 03h d7 pin 54 audio direct output on / off (mute). 0: audio on (no mute), 1: mute 0 M61251AFP rev.1.0, sep.22.2 003, page 10 of 15 write (cont) function bit sub- address data description initial value note video tone 6 04h d0 to d5 sharpness level control 20h v latch contrast control 7 05h d0 to d6 c ontrast level control 40h v latch extrgb contrast clip 1 05h d7 ext rgb contrast lower limit clipping on/off. 0: clipping on, 1: clipping off 0 v latch c. clip level 1 02h d5 ext rgb contrast lower-limit clipping level. 0: low (20h), 1: high (40h) 0 y delay time adjustment 2 06h d0 to d1 y signal delay adjustment x0h y delay fine adjustment 1 06h d2 y signal delay fine adjustment 0 ext 1 06h d3 selects video input on pin 41 or 38. 0: pin 41, 1: pin 38 0 v latch y / c 1 06h d4 selects composite input or yc on pin 38 or 41. 0: composite, 1: y / c mode 0 v latch y sw lpf 1 13h d5 pin 31 (y sw out) output frequency characteristic. 0: flat, 1: lpf (fc = 700 khz) 0 video tone sharpness 1 02h d3 selects one of two video-tone levels (sharp or soft). 0: standard, 1: sharp 0 video mute 1 02h d7 y-signal output on / off (video mute). 0: mute off, 1: mute 0 trap off 1 02h d4 y-signal chroma trapping on / off. 0: trapping on, 1: trapping off 0 trap fine adjustment 2 12h d0 ? d1 chroma-trapping frequency fine adjustment x0h black stretch off 1 02h d1 black - stretch circuit on / off. 1: on, 1: off 0 black stretch charge 2 14h d4 ? d5 adjustment of charge - time - constant for black stretch 0xh discharge 2 14h d6 to d7 adjustment of discharge ? time - constant for black stretch 0xh v i d e o gamma control 2 12h d2 to d3 gamma-level adjustment x0h tint control 7 07h d0 to d6 hue control 40h v latch baseband tint control 7 17h d0 to d6 yuv input hue control 40h v latch yuv sw 1 17h d7 switches between yuv and other input mode 0 color control 7 08h d0 to d6 color level control 40h v latch take off 1 02h d0 chroma bpf take-off on / off, 0: bpf, 1: take-off 0 js / jpn / sw 1 15h d1 to d3 us / jpn modes, 100: us mode, 011: jpn mode 0 killer level 1 15h d0 color killer sensitivity, 0: 43 db, 1: 45 db 0 c h r o m a fsc free 1 09h d5 crystal oscillator circuit forced free-running mode. 0: off, 1: free-running 0 M61251AFP rev.1.0, sep.22.2 003, page 11 of 15 write (cont) function bit sub- address data description initial value note brightness control 8 0ah d0 to d7 br ightness level control 80h v latch drive (red) 7 0bh d0 to d6 red-output level control 40h drive (blue) 7 0ch d0 to d6 blue-output level control 40h cut-off (red) 8 0ch d0 to d7 red-output dc-level control 80h cut-off (green) 8 0eh d0 to d7 green-output dc-level control 80h cut-off (blue) 8 0fh d0 to d7 blue-output dc-level control 80h blue background 1 08h d7 blue-backgr ound screen on / off. 1: off, 1: blue background 0 white background 1 10h d7 white background on / off, 1: off, 1: white background 0 abcl 1 02h d2 abcl on/off. 0: off, 1: abcl on 0 abcl gain 1 04h d7 abcl sensitivity low / high. 0: low, 1: high 0 on-screen display level 1 15h d5 on-screen display level (70 / 90%). 0: 70%, 1: 90% 0 halftone sw 1 09h d4 halftone on / off. 0: off, 1: on 0 r g b analog on-screen display 1 15h d4 on-screen display digital / analog input. 0: digital, 1: analog 0 M61251AFP rev.1.0, sep.22.2 003, page 12 of 15 write (cont) function bit sub- address data description initial value note afc2 horizontal phase 5 16h d0 to d4 adjustment of horizontal phase of display 90h ramp stop 1 09h d6 pin 5 vout (ramp / pulse) forcible stop mode (when stopped, pin 5 is at ground level). 0: vout, 1: stopped 0 service switch 1 13h d3 vertical output on / off, 0: vertical output on, 1: vertical output off 0 horizontal start 1 13h d4 horizont al output out / stopped. 0: stopped, 1: h out 0 afc1 gain 1 15h d7 horizontal afc gain high / low. 0: low, 1: high 0 afc2 gain 1 15h d6 horizontal afc2 gain high/low. 0: high, 1: low 0 horizontal vco adjustment 3 10h d0 to d2 adjustment of horizontal vco free- running frequency 24h vertical shift 3 13h d0 to d2 adjustment of vertical ramp start timing x0h vertical size 6 11h d0 to d5 adjustment of vertical ramp amplitude 20h horizontal free 1 13h d7 horizontal output forced free-run mode on/off. 0: off, 1: horizontal free-run 0 vertical free 1 10h d6 vertical output forced free-run mode on/off. 0: off, 1: vertical free-run 0 s slice down 1 1 14h d2 sync detection slice level (50 / 30%). 0: 50%, 1: 30% 0 s slice down 2 1 14h d3 sync detection slice level (50 / 40%), 0: 50%, 1: 40% 0 auto slice down 1 16h d6 synchronous detection slice level during video period, 0: slice level remains constant, 1: slice level decreased during video period 0 fbp vth l 1 16h d5 pin 10 (fbp in) fbp slice level. 0: vth = 2 v (hblk width: narrow), 1: vth = 1 v (hblk width: wide) 0 hv blk off 1 09h d7 horizontal / vertical blanking. 0: blanking on, 1: blanking off 0 vertical sync. detection 1 16h d7 minimum width for vertical sync detection. 0: synchronous detection width = 18 us, 1: synchronous detection width = 14 us 90h one window 1 13h d6 minimum width for vertical sync detection (1 / 2 windows). 0: 2 windows, 1: 1 window 0 d e f bgpfbp off 1 19h d7 internal bgp on / off when there is no fbp input. 0: bgp on, 1: bgp off 0 M61251AFP rev.1.0, sep.22.2 003, page 13 of 15 write (cont) function bit sub- address data description initial value note monitoring 4 12h d4 to d7 pin 18 intelligent monitoring mode switch 0xh test 1 1 18h d6 to d7 reserved (test bit) 0 test 2 2 19h d6 reserved (test bit) 0 test 3 2 1ah d6 to d7 reserved (test bit) 0 M61251AFP rev.1.0, sep.22.2 003, page 14 of 15 read: killerb 1 00h d7 color killer information output; 1 when killer is off. afto 1 00h d3 aft information output (note 1) aft1 1 00h d2 aft information output (note 1) hcoinb 1 00h d1 horizontal sync detection, not synchronized = 1 vcoinb 1 00h d5 vertical sync detection, not detected = 1 stdetb 1 00h d4 station detection in tv mode, not detected = 1 note 1: aft0 / aft1, read byte: aft output aft0/aft1 M61251AFP rev.1.0, sep.22.2 003, page 15 of 15 package dimensions lqfp64-p-1414-0.8 weight(g) ? jedec code eiaj package code lead material cu alloy 64p6u-a plastic 64pin 14 14mm body lqfp ? 0.1 0.8 ? 0.2 ? ? ? ? ? ? ? symbol min nom max a a 2 b c d e h e l l 1 y b 2 dimension in millimeters h d a 1 ? ? i 2 ? ? m d 14.4 ? ? m e 14.4 0 8 0.1 0.2 1.0 0.7 0.5 0.3 16.2 15.8 14.1 13.9 16.2 15.8 14.0 14.1 13.9 14.0 16.0 16.0 0.175 0.125 0.105 0.45 0.37 0.32 1.4 0 1.7 e lp 0.45 0.95 ? ? 0.6 0.5 0.25 ? 0.75 ? ?? ?? x a3 recommended mount pad detail f mmp e h e 1 17 32 64 49 16 48 33 h d d a y b x m e f m d l 2 b 2 m e e a 1 a 2 l 1 l lp a3 c ? 2003. renesas technolo gy corp., all ri g hts reserved. printed in japan . colo p hon 1.0 keep safet y first in y our circuit desi g ns ! 1. renesas technolo gy corp. puts the maximum effort into makin g semiconductor products better and more reliable, but there is alwa y s the possibilit y that trouble m a y occur with them. trouble with semiconductors ma y lead to personal in j ur y , fire or propert y dama g e . remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placem ent of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas t echnology corp. or a third party. 2. renesas technology corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents i nformation on products at the time of publication of these materials, and are subject to change by renesas technology corp. without notice due to product improvement s or other reasons. it is therefore recommended that customers contact renesas technology corp. or an authorized renesas technology corp. product distrib utor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by renesas technology corp. by various means, including the renesas technology corp. semiconductor home page (http://www.renesas.com). 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, a nd algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corp. semiconductors are not designed or manufactured for use in a device or system that is used under ci rcumstances in which human life is potentially at stake. please contact renesas technology corp. or an authorized renesas technology corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerosp ace, nuclear, or undersea repeater use. 6. the prior written approval of renesas technolo gy corp. is necessar y to reprint or reproduce in whole or in part these materials . 7 . if these products or technolo g ies are sub j ect to the japanese export control restrictions, the y must be exported under a license from the japanese g overnment and cannot b e imported into a countr y other than the approved destination. an y diversion or reexport contrar y to the export control laws and re g ulatio n s of japan and/or the countr y of destination is prohibited . 8. please contact renesas technolo gy corp. for further details on these materials or the products contained therein . s ales strate g ic plannin g div. nippon bld g ., 2-6-2, ohte-machi, chi y oda-ku, tok y o 100-0004, japa n htt p ://www.renesas.co m renesas technology america, inc. 450 holger way, san jose, ca 95134-1368, u.s.a tel: <1> (408) 382-7500 fax: <1> (408) 382-7501 renesas technology europe limited. dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, united kingdom tel: <44> (1628) 585 100, fax: <44> (1628) 585 900 renesas technology europe gmbh dornacher str. 3, d-85622 feldkirchen, germany tel: <49> (89) 380 70 0, fax: <49> (89) 929 30 11 renesas technology hong kong ltd. 7/f., north tower, world finance centre, harbour city, canton road, hong kong tel: <852> 2265-6688, fax: <852> 2375-6836 renesas technology taiwan co., ltd. fl 10, #99, fu-hsing n. rd., taipei, taiwan tel: <886> (2) 2715-2888, fax: <886> (2) 2713-2999 renesas technology (shanghai) co., ltd. 26/f., ruijin building, no.205 maoming road (s), shanghai 200020, china tel: <86> (21) 6472-1001, fax: <86> (21) 6415-2952 renesas technology singapore pte. ltd. 1, harbour front avenue, #06-10, keppel bay tower, singapore 098632 tel: <65> 6213-0200, fax: <65> 6278-8001 renesas sales offices |
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