engineering data sheet p150 series solid state power controller 28 vdc, 1pno-with current or voltage status output up to 30 amp rating size: 69.6 x 34 x 9.65 mm description the p150 series of solid state power controllers (sspc) is rated from 2 to 30 amperes. these leach sspc's feature reliable, trouble free switching together with real short circuit protection. employing a power fet output stage, and built using thick film technology, they offer low on state resistance and low on state voltage drop. they react to fault condition and can shutdown within microseconds, if required. two status signals, derived from the load current value or voltage and from the device gate, are reported via optical isolators. designed to operate in 28 vdc systems, these devices do not require derating for any load type. they are hermetically sealed, in a metal package. features . fast acting . built-in overload and short circuit protection . load current or voltage status . fet gate status or trip status . very low voltage drop . no derating up to 105 c . trip free . fully isolated bias, control and status . no derating for non-resistive loads . exceeds mil-p-81653c requirements . very low voltage drop output stage block diagram featuring leach ? power and control solutions www.leachintl.com americas 6900 orangethorpe ave. p.o. box 5032 buena park, ca 90622 usa tel: (01) 714-736-7599 fax: (01) 714-670-1145 europe 2 rue goethe 57430 sarralbe france tel: (33) 3 87 97 31 01 fax: (33) 3 87 97 96 86 asia room 501, 5/f, the centre mark 287 - 299 queen's road central hong kong tel: (852) 2 191 3830 fax: (852) 2 389 5803 data sheets are for initial product selection and comparison. contact leach international prior to choosing a component. date of issue: 4/10 - 9 - page 1 of 6
electrical characteristics (current status) p150 series typical values are at 25 5 c input device with current status parameter symbol min. typ. max. unit notes bias on voltage v ihb 4.5 5.5 v 1,2 bias on current i ihb 10 ma 3 bias off current i ilb 1 ma 3 control voltage on v ihc 2.4 v control voltage off v ilc -0.8 0.8 v control current on i ihc 50 a 4 control current off i ilc -10 a 5 transients (bias input) v tb +50 v 6 notes: 1. bias voltage must be a step function. 2. no reverse polarity protection. 3. bias voltage is 5.0 v. 4. control voltage at 2.4 vdc. 5. control voltage at 0.4 vdc. 6. max. duration 50 ms, duty cycle 1%, repetition rate 1 hz. output parameter symbol min. typ. max. unit note load current i l 0 100 %i rated 1 on state voltage drop v ld 200 mv 2 off state line voltage v l 32 v 3 gate high voltage v ohs 2.4 v gate high current i ohs 50 a gate low voltage v ols 0.8 v gate low current i ols 0.2 ma load pick up i son 15 %i rated load drop out i soff 5 %i rated leakage current i ll 1 ma 4 transient voltage v t +50 v 5 spikes v s -600 +600 v 6 trip current i tr 110 130 145 %i rated 7 isolation voltage v iso 750 vrms insulation resistance r ins 100 1000 mw 8 notes: 1. load current is subject to thermal derating. 2. at load current i l =100% rated value. 3. reverse polarity is not blocked and may damage the sspc. 4. at v l =28v, case temperature = 105 c. 5. duration 12.5 ms max. per mil-std-704d. 6. duration 10 s max. per mil-std-704d. 7. see trip characteristics. 8. 500 vdc, 10% date of issue: 4/10 - 10 - page 2 of 6
trip characteristic p150 series timing diagram (current status) timing parameter symbol typ. max. unit note control to gate delay t 0 300 1000 s turn on delay t 1 150 200 s load current rise time t 2 30 1000 s turn on to load delay t 3 75 1000 s control to gate t 4 150 1000 s turn off delay t 5 150 200 s load current fall time t 6 20 1000 s 2 turn off to load delay t 7 400 1000 s notes: 1. all timing measurements taken at 10% and 90% points into resistive rated load. 2. current fall time from trip dependant on overload condition. date of issue: 4/10 - 11 - page 3 of 6
electrical characteristics (voltage status) p150 series typical values are at 25 5 c input device with voltage status limits unit notes parameter symbol conditions -55c to +105c (1) min max logic supply voltage v cc 4.5 5.5 vdc control voltage high v ih 2.0 vdc control voltage low v il 0.8 vdc transient pulse width = 12.5 msec max. per mil-std-704d +50 vdc 2 spikes pulse width = 10 sec max. per mil-std-704d -600 +600 vdc 2 requirements 28 vdc initialization spike voltage during of output spike at 50% amplitude shall be 100sec maximum 5 v pr 5 vdc initialization control vline = 28 vdc, vcontrol = 0 vdc, vbias = 0 to 5 vdc, rated at <1 msec 3 logic supply current i cc v cc =5.5 vdc 50 ma 4 load current continuous i load 100 %i "on" state voltage drop v o 200 mv 5 leakage current i l 1 ma status & trip voltage high v oh ioh=5ma 2.4 vdc status & trip voltage low v ol iol=1ma 0.4 vdc control current high i ih vi=2.4 vdc 50 a control current low i il vi=0.4 vdc 10 a output "on" sense voltage v on see timing diagram (voltage status) 30 70 % 5,6,7 notes: 1. unless specified otherwise, test conditions shall be at vcc=5.0 0.25vdc and vline=280.5vdc. the design shall be capable of meeting all requirements with vcc=4.5 to 5.5vdc. 2. the transient and spike requirements apply only to the 28vdc power lines. 3. the device output shall remain off when 5v bias is raised from 0 to 5vdc. 4. without any load connected to the status or trip outputs. 5. at 100% rated current. 6. rated resistive load; measurements taken between 10% and 90% points. 7. percent of actual applied vline. date of issue: 4/10 - 12 - page 4 of 6
timing diagram (voltage status) p150 series timing parameter symbol conditions -55c to +105c min. max. unit notes turn-on time t on see timing diagram 1000 sec 1,3 turn-off time t off 1000 sec 1,3 load voltage rise time t r 20 200 sec 1,3 load voltage fall time t f 200 sec 1,3 status on delay t d1 2000 sec 1 status of delay t d3 2000 sec 1 trip on delay t d2 150 sec 2 trip of delay t d4 150 sec 2 control pulse width for device reset p r 50 msec notes: 1. at 100% rated current. 2. at 250% rated current. 3. rated resistive load; measurements taken between 10% and 90% points. date of issue: 4/10 - 13 - page 5 of 6
environmental data p150 series parameter symbol min. max. unit notes operational temp. range t op -55 125 c 1,2 storage temp. range t st -55 125 c thermal resistance junction to case jc 15 c/w max. junction temperature of output stage t j(max) 150 c vibration 20 g 3 acceleration 3000 g 4 shock 1500 g 5 seal (hermetic) 7 altitude 80000 ft mtbf 1.1 hours 6 notes: 1. case temperature. 2. see thermal derating curve. 3. mil-p-883c, method 2007, test condition a; 20-2000 hz. 4. mil-p-883c, method 2001, test condition a. 5. mil-p-883c, method 2002, test condition b, 0.5 ms. 6. per mil-hbk-217e, quality level b-1, aut environment at 25c. 7. meets the leakage levels in accordance with mil-std-883, method 1014, test condition a1. thermal derating physical data (in mm) l case finish: tin plated. l terminals: gold plated. l mass: 65 grams max. this engineering data sheet is designed for initial selection and comparison of products. while every effort is made to ensure the accuracy of all data, each part number, and its application, must be controlled by a product control drawing (pcd). please contact powercom, a leach international company, for further information. date of issue: 4/10 - 14 - page 6 of 6
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