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? 2003 microchip technology inc. ds21798a-page 1 m tc1301a/b features ? dual output ldo with microcontroller reset monitor functionality: -v out1 = 1.5v to 3.3v @ 300 ma, -v out2 = 1.5v to 3.3v @ 150 ma -v reset = 2.20v to 3.20v ? output voltage and reset threshold voltage options available (see table 8-1) ? low dropout voltage: -v out1 = 104 mv @ 300 ma, typical -v out2 = 150 mv @ 150 ma, typical ? low supply current: 116 a, typical tc1301a/b with both output voltages available ? reference bypass input for low noise operation ? both output voltages stable with a minimum of 1 f ceramic output capacitor ? separate input for reset detect voltage (tc1301a) ? separate v out1 and v out2 shdn pins (tc1301b) ? reset output duration: 300 msec. typical ? power-saving shutdown mode of operation ? wake-up from shdn : 5.3 sec. typical ? small 8-pin dfn and msop package options ? operating junction temperature range: - -40c to +125c ? overtemperature and overcurrent protection applications ? cellular / gsm / phs phones ? battery operated systems ? hand-held medical instruments ? portable computers / pda?s ? linear post-regulators for smps ? pagers related literature ? an765, ?using microchip?s micropower ldos?, ds00765, microchip technology inc. ? an766, ?pin-compatible cmos upgrades to bipolar ldos?, ds00766, microchip technology inc. ? an792, ?a method to determine how much power a sot23 can dissipate in an application?, ds00792, microchip technology inc. description the tc1301a/b combines two low dropout (ldo) regulators and a microcontroller reset function into a single 8-pin msop or dfn package. both regulator outputs feature low dropout voltage, 104 mv @300ma for v out1 , 150 mv @ 150 ma for v out2 , low quiescent current consumption, 58 a each and a typical regulation accuracy of 0.5%. several fixed- output voltage and detector voltage combinations are available. a reference bypass pin is available to further reduce output noise and improve the power supply rejection ratio of both ldos. the tc1301a/b is stable over all line and load conditions with a minimum of 1 f of ceramic output capacitance and utilizes a unique compensation scheme to provide fast dynamic response to sudden line voltage and load current changes. for the tc1301a, the microcontroller reset function operates independently of both v out1 and v out2 . the input to the reset function is connected to the v det pin.the shdn2 pin is used to control the output of v out2 only. v out1 will power up and down with v in . in the case of the tc1301b, the detect voltage input of the reset function is connected internally to v out1 . both v out1 and v out2 have independent shutdown capability. additional features include an overcurrent limit and overtemperature protection that, when combined, provide a robust design for all load fault conditions. package types 8-pin dfn/msop reset shdn2 bypass gnd v det 1 2 3 45 6 7 8 v out2 v in 1 2 3 4 5 6 7 8 v out1 tc1301a reset shdn2 bypass gnd v det v out2 v in v out1 dfn8 msop8 reset shdn2 bypass gnd shdn1 1 2 3 45 6 7 8 v out2 v in 1 2 3 4 5 6 7 8 v out1 tc1301b reset shdn2 bypass gnd shdn1 v out2 v in v out1 dfn8 msop8 dual ldo with microcontroller reset function
tc1301a/b ds21798a-page 2 ? 2003 microchip technology inc. functional block diagrams typical application circuits ldo #2 2.6v@ 150 ma ldo #1 2.8v@300 ma ldo #2 2.6v@ 150 ma v in v out1 v out2 bandgap reference 1.2v shdn2 threshold detector 2.63v time delay 300 ms, typ reset v det gnd bypass tc1301a v det tc1301b v in shdn2 gnd bypass shdn1 ldo #1 2.8v@300 ma threshold detector 2.63v time delay 300 ms typ v out1 v out2 reset v out1 bandgap reference 1.2v v out1 8 4 1 2 3 reset gnd v det battery c out1 1f ceramic x5r c in 1f tc1301a c out2 1f ceramic x5r c bypass 10 nf ceramic bypass v in 7 v out2 6 shdn2 on/off control v out2 system reset 2.8v @ 300 ma 2.6v @ 150 ma 5 v out1 8 4 1 2 3 reset gnd shdn1 battery c out1 1f ceramic x5r c in 1f tc1301b 1f ceramic x5r bypass v in 7 2.7v to 4.2v v out2 6 shdn2 on/off control v out2 system reset 2.8v @ 300 ma 2.6v @ 150 ma 5 on/off control v out1 note: c bypass is optional 2.7v to 4.2v c out2
? 2003 microchip technology inc. ds21798a-page 3 tc1301a/b 1.0 electrical characteristics absolute maximum ratings ? v dd ...................................................................................6.5v maximum voltage on any pin ....... (v ss - 0.3) to (v in + 0.3)v power dissipation ..........................internally limited (note 7) storage temperature .....................................-65c to +150c maximum junction temperature, t j ........................... +150c continuous operating temperature range ..-40c to +125c esd protection on all pins, hbm, mm ..................... 4 kv, 400v ? notice: stresses above those listed under ?maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. dc characteristics electrical specifications: unless otherwise noted, v in = v r +1v, i out1 = i out2 = 100 a, c in = 4.7 f, c out1 = c out2 = 1 f, c bypass = 10 nf, shdn > v ih , t a = +25c. boldface type specifications apply for junction temperatures of -40c to +125c. parameters sym min typ max units conditions input operating voltage v in 2.7 ? 6.0 v note 1 maximum output current i out1max 300 ?? mav in = 2.7v to 6.0v (note 1) maximum output current i out2max 150 ?? mav in = 2.7v to 6.0v (note 1) output voltage tolerance (v out1 and v out2 ) v out v r -2.5 v r 0.5 v r +2.5 % note 2 temperature coefficient (v out1 and v out2 ) tcv out ?25?ppm/c note 3 line regulation (v out1 and v out2 ) ? v out / ? v in ?0.02 0.2 %/v (v r +1v) v in 6v load regulation, v out 2.5v (v out1 and v out2 ) ? v out / v out -1 0.1 +1 %i outx = 0.1 ma to i outmax (note 4) load regulation, v out < 2.5v (v out1 and v out2 ) ? v out / v out -1.5 0.1 +1.5 %i outx = 0.1 ma to i outmax (note 4) thermal regulation ? v out / ? p d ?0.04? %/w note 5 dropout voltage (note 6) v out1 2.7v v in - v out ?104 180 mv i out1 = 300 ma v out2 2.6v v in - v out ?150 250 mv i out2 = 150 ma supply current tc1301a i in(a) ?103 180 a shdn2 = v in , v det = open, i out1 = i out2 = 0 ma tc1301b i in(b) ?114 180 a shdn1 = shdn2 = v in , i out1 = i out2 = 0 ma note 1: the minimum v in has to meet two conditions: v in 2.7v and v in v r + v dropout . 2: v r is defined as the higher of the two regulator nominal output voltages (v out1 or v out2 ). 3: tcv out = ((v outmax - v outmin ) * 10 6 )/(v out * ? t). 4: regulation is measured at a constant junction temperature using low duty cycle pulse testing. load regulation is tested over a load range from 0.1 ma to the maximum specified output current. changes in output voltage due to heating effects are covered by the thermal regulation specification. 5: thermal regulation is defined as the change in output voltage at a time t after a change in power dissipation is applied, excluding load or line regulation effects. specifications are for a current pulse equal to i lmax at v in = 6v for t = 10 msec. 6: dropout voltage is defined as the input to output voltage differential at which the output voltage drops 2% below its value measured at a 1v differential. 7: the maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air (i.e., t a , t j , ja ). exceeding the maximum allowable power dissipation causes the device to initiate thermal shutdown .
tc1301a/b ds21798a-page 4 ? 2003 microchip technology inc. shutdown supply current tc1301a i in_shdn a ?58 90 a shdn2 = gnd, v det = open shutdown supply current tc1301b i in_shdn b ? 0.1 1 a shdn1 = shdn2 = gnd power supply rejection ratio psrr ? 58 ? db f 100 hz, i out1 = i out2 = 50 ma, c in = 0 f output noise en ? 830 ? nv/(hz) ? f 1khz, i out1 = i out2 = 50 ma, c in = 0 f output short-circuit current (average) v out1 i outsc ?200? mar load1 1 ? v out2 i outsc ?140? mar load2 1 ? shdn input high threshold v ih 45 ??%v in v in = 2.7v to 6.0v shdn input low threshold v il ?? 15 %v in v in = 2.7v to 6.0v wake-up time (from shdn mode), (v out2 ) t wk ?5.320 s v in = 5v, i out1 = i out2 = 30 ma, see figure 5-1 settling time (from shdn mode), (v out2 ) t s ?50? s v in = 5v, i out1 = i out2 = 50 ma, see figure 5-2 thermal shutdown die temperature t sd ?150? cv in = 5v, i out1 = i out2 = 100 a thermal shutdown hysteresis t hys ?10? cv in = 5v voltage range v det 1.0 1.2 ? 6.0 6.0 v t a = 0c to +70c t a = -40c to +125c reset threshold v th -1.4 ? +1.4 % -2.8 ? +2.8 %t a = -40c to +125c reset threshold tempco ? v th / ? t? 30 ?ppm/c v det reset delay t rpd ?180? s v det = v th to (v th - 100 mv), see figure 5-3 reset active time-out period t rpu 140 300 560 ms v det = v th - 100 mv to v th + 100 mv, i sink = 1.2 ma, see figure 5-3. reset output voltage low v ol ?? 0.2 v v det = v thmin , i sink = 1.2 ma, i sink = 100 a for v det < 1.8v, see figure 5-3 reset output voltage high v oh 0.9 v det ?? v v det > v thmax , i source = 500 a, see figure 5-3 dc characteristics (continued) electrical specifications: unless otherwise noted, v in = v r +1v, i out1 = i out2 = 100 a, c in = 4.7 f, c out1 = c out2 = 1 f, c bypass = 10 nf, shdn > v ih , t a = +25c. boldface type specifications apply for junction temperatures of -40c to +125c. parameters sym min typ max units conditions note 1: the minimum v in has to meet two conditions: v in 2.7v and v in v r + v dropout . 2: v r is defined as the higher of the two regulator nominal output voltages (v out1 or v out2 ). 3: tcv out = ((v outmax - v outmin ) * 10 6 )/(v out * ? t). 4: regulation is measured at a constant junction temperature using low duty cycle pulse testing. load regulation is tested over a load range from 0.1 ma to the maximum specified output current. changes in output voltage due to heating effects are covered by the thermal regulation specification. 5: thermal regulation is defined as the change in output voltage at a time t after a change in power dissipation is applied, excluding load or line regulation effects. specifications are for a current pulse equal to i lmax at v in = 6v for t = 10 msec. 6: dropout voltage is defined as the input to output voltage differential at which the output voltage drops 2% below its value measured at a 1v differential. 7: the maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air (i.e., t a , t j , ja ). exceeding the maximum allowable power dissipation causes the device to initiate thermal shutdown .
? 2003 microchip technology inc. ds21798a-page 5 tc1301a/b temperature specifications electrical specifications: unless otherwise indicated, all limits are specified for: v in = +2.7v to +6.0v. parameters sym min typ max units conditions temperature ranges operating junction temperature range t a -40 ? +125 c steady state storage temperature range t a -65 ? +150 c maximum junction temperature t j ? ? +150 c transient thermal package resistances thermal resistance, msop8 ja ? 208 ? c/w typical 4 layer board thermal resistance, dfn8 ja ? 41 ? c/w typical 4 layer board with vias
tc1301a/b ds21798a-page 6 ? 2003 microchip technology inc. 2.0 typical performance curves note: unless otherwise indicated, v in = v r +1v, i out1 = i out2 = 100 a, c in = 4.7 f, c out1 = c out2 = 1 f (x5r or x7r), c bypass = 0 pf, shdn1 = shdn2 > v ih , for the tc1301a, v det = v out1 , reset = open, t a = +25c. figure 2-1: quiescent current vs. input voltage. figure 2-2: shdn voltage threshold vs. input voltage. figure 2-3: quiescent current vs. junction temperature. figure 2-4: output voltage vs. input voltage. figure 2-5: output voltage vs. input voltage. figure 2-6: dropout voltage vs. output current (v out1 ). note: the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. the performance characteristics listed herein are not tested or guaranteed. in some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. 0 50 100 150 200 250 300 350 2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 5.7 6.0 input voltage (v) quiescent current (a) v out2 shdn v out2 active t j = 25c i out1 = i out2 = 0 a v out1 active tc1301b 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 2.7 3 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 5.7 6 input voltage (v) shdn threshold (v) on off 40 50 60 70 80 90 100 110 120 130 140 -40 -25 -10 5 20 35 50 65 80 95 110 125 junction temperature (c) quiescent current (a) v in = 4.2v i out1 = i out2 = 0 a v out1 active v out2 shdn v out2 active tc1301b 2.60 2.70 2.80 2.90 3.00 2.7 3 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 5.7 6 input voltage (v) output voltage (v) t j = 25c i out1 = 100 ma i out2 = 50 ma v out1 v out2 2.50 2.55 2.60 2.65 2.70 2.75 2.80 2.85 2.90 2.7 3 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 5.7 6 input voltage (v) output voltage (v) t j = +25c i out1 = 300 ma i out2 = 100 ma v out1 v out2 0.0 20.0 40.0 60.0 80.0 100.0 120.0 140.0 0 50 100 150 200 250 300 i out1 (ma) dropout voltage v out1 (mv) v r1 = 2.8v v r2 = 2.6v i out2 = 100 a t j = - 40c t j = +25c t j = +125c
? 2003 microchip technology inc. ds21798a-page 7 tc1301a/b note: unless otherwise indicated, v in = v r +1v, i out1 = i out2 = 100 a, c in = 4.7 f, c out1 = c out2 = 1 f (x5r or x7r), c bypass = 0 pf, shdn1 = shdn2 > v ih , for the tc1301a, v det = v out1 , reset = open, t a = +25c. figure 2-7: dropout voltage vs. junction temperature (v out1 ). figure 2-8: dropout voltage vs. output current (v out2 ). figure 2-9: dropout voltage vs. junction temperature (v out2 ). figure 2-10: v out1 and v out2 load regulation vs. junction temperature. figure 2-11: v out1 and v out2 line regulation vs. junction temperature. figure 2-12: v out1 vs. junction temperature. 0 20 40 60 80 100 120 140 -40 -25 -10 5 20 35 50 65 80 95 110 125 junction temperature (c) dropout voltage v out1 (mv) v r1 = 2.8v v r2 = 2.6v i out2 = 100 a i out1 = 300 ma i out1 = 100 ma i out1 = 50 ma 0 20 40 60 80 100 120 140 160 180 0 30 60 90 120 150 i out2 (ma) dropout voltage, v out2 (mv) v r1 = 2.8v v r2 = 2.6v i out1 = 100 a t j = +125c t j = +25c t j = - 40c 0 20 40 60 80 100 120 140 160 180 -40 -25 -10 5 20 35 50 65 80 95 110 125 junction temperature (c) dropout voltage v out2 (mv) v r1 = 2.8v v r2 = 2.6v i out1 = 100 a i out2 = 150 ma i out2 = 50 ma i out2 = 10 ma -0.40 -0.30 -0.20 -0.10 0.00 0.10 0.20 0.30 0.40 -40 -25 -10 5 20 35 50 65 80 95 110 125 junction temperature (125c) load regulation (%) i out2 = 0.1 ma to 150 ma i out1 = 0.1 ma to 300 ma v r1 = 2.8v v r2 = 2.6v v in = 4.2 v out2 v out1 0.000 0.005 0.010 0.015 0.020 0.025 0.030 0.035 0.040 0.045 -40 -25 -10 5 20 35 50 65 80 95 110 125 junction temperature (c) line regulation (%/v) v in = 3.8v to 6.0v v r1 = 2.8v, i out1 = 100 a v r2 = 2.6v, i out2 = 100 a v out1 v out2 2.808 2.812 2.816 2.820 2.824 2.828 2.832 -40 -25 -10 5 20 35 50 65 80 95 110 125 junction temperature (c) output voltage v out1 (v) v in = 4.2v v r1 = 2.8v v r2 = 2.6v, i out2 = 100 a i out1 = 300 ma i out1 = 100 a i out1 = 100 ma
tc1301a/b ds21798a-page 8 ? 2003 microchip technology inc. note: unless otherwise indicated, v in = v r +1v, i out1 = i out2 = 100 a, c in = 4.7 f, c out1 = c out2 = 1 f (x5r or x7r), c bypass = 0 pf, shdn1 = shdn2 > v ih , for the tc1301a, v det = v out1 , reset = open, t a = +25c. figure 2-13: v out1 vs. junction temperature. figure 2-14: v out2 vs. junction temperature. figure 2-15: v out2 vs. junction temperature. figure 2-16: i det current vs. junction temperature. figure 2-17: reset active time vs. junction temperature. figure 2-18: v det trip point vs. junction temperature. 2.808 2.816 2.824 2.832 2.840 2.848 2.856 -40 -25 -10 5 20 35 50 65 80 95 110 125 junction temperature (c) output voltage v out1 (v) v r1 = 2.8v, i out1 = 300 ma v r2 = 2.6v, i out2 = 100 a v in = 6.0v v in = 4.2v v in = 3.0v 2.615 2.620 2.625 2.630 2.635 2.640 2.645 -40 -25 -10 5 20 35 50 65 80 95 110 125 junction temperature (c) output voltage v out2 (v) v in = 4.2v v r1 = 2.8v, i out1 = 100 a v r2 = 2.6v i out2 = 150 ma i out2 = 100 a i out2 = 50 ma 2.624 2.628 2.632 2.636 2.640 2.644 -40 -25 -10 5 20 35 50 65 80 95 110 125 junction temperature (c) output voltage v out2 (v) v r1 = 2.8v, i out1 = 100 a v r2 = 2.6v, i out2 = 150 ma v in = 6.0v v in = 3.0v v in = 4.2v 0 5 10 15 20 25 30 -40 -25 -10 5 20 35 50 65 80 95 110 125 junction temperature (c) i vdet (a) v det = 6.0v v det = 4.2v v det = 3.0v v r1 = 2.8v v r2 = 2.6v 200 225 250 275 300 325 350 375 400 -40 -25 -10 5 20 35 50 65 80 95 110 125 junction temperature (c) /reset active time (ms) v in = 4.2v v r1 = 2.8v v r2 = 2.6v v det = 2.63v 2.6355 2.6360 2.6365 2.6370 2.6375 2.6380 2.6385 2.6390 2.6395 -40 -25 -10 5 20 35 50 65 80 95 110 125 junction temperature (c) v det trip point (v) v in = 4.2v v r1 = 2.8v v r2 = 2.6v v det = 2.63v
? 2003 microchip technology inc. ds21798a-page 9 tc1301a/b note: unless otherwise indicated, v in = v r +1v, i out1 = i out2 = 100 a, c in = 4.7 f, c out1 = c out2 = 1 f (x5r or x7r), c bypass = 0 pf, shdn1 = shdn2 > v ih , for the tc1301a, v det = v out1 , reset = open, t a = +25c. figure 2-19: power supply rejection ratio vs. frequency (without bypass capacitor). figure 2-20: power supply rejection ratio vs. frequency (with bypass capacitor). figure 2-21: v out1 and v out2 noise vs. frequency (without bypass capacitor). figure 2-22: v out1 and v out2 noise vs. frequency (with bypass capacitor). figure 2-23: v out1 and v out2 power up from shutdown tc1301b. figure 2-24: v out2 power up from shutdown input tc1301a. 0.01 0.1 1 10 0.01 0.1 1 10 100 1000 frequency (khz) noise (v/ ? hz) v in = 4.2v v r1 = 2.8v v r2 =2.6v i out1 = 150 ma i out2 = 100 ma c bypass = 0 nf v out1 v out2 0.001 0.01 0.1 1 10 0.01 0.1 1 10 100 1000 frequency (khz) noise (v/ ? hz) v in = 4.2v v r1 = 2.8v v r2 =2.6v i out1 = 150 ma i out2 = 100 ma c bypass = 10 nf v out1 v out2
tc1301a/b ds21798a-page 10 ? 2003 microchip technology inc. note: unless otherwise indicated, v in = v r +1v, i out1 = i out2 = 100 a, c in = 4.7 f, c out1 = c out2 = 1 f (x5r or x7r), c bypass = 0 pf, shdn1 = shdn2 > v ih , for the tc1301a, v det = v out1 , reset = open, t a = +25c. figure 2-25: v out1 and v out2 power-up from input voltage tc1301b. figure 2-26: dynamic line response. figure 2-27: 300 ma dynamic load step v out1 . figure 2-28: 150 ma dynamic load step v out2 . figure 2-29: reset power-up from v in tc1301b. figure 2-30: tc1301a reset power- down.
? 2003 microchip technology inc. ds21798a-page 11 tc1301a/b note: unless otherwise indicated, v in = v r +1v, i out1 = i out2 = 100 a, c in = 4.7 f, c out1 = c out2 = 1 f (x5r or x7r), c bypass = 0 pf, shdn1 = shdn2 > v ih , for the tc1301a, v det = v out1 , reset = open, t a = +25c. figure 2-31: reset output voltage low vs. junction temperature. figure 2-32: reset output voltage high vs. junction temperature. 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 -40 -25 -10 5 20 35 50 65 80 95 110 125 junction temperature (c) reset v ol (v) v r1 = 2.8v,v r2 = 2.6v v det = v th - 20 mv i ol = 3.2 ma i ol = 1.2 ma 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 -40 -25 -10 5 20 35 50 65 80 95 110 125 junction temperature (c) reset v oh (v) v r1 = 2.8v,v r2 = 2.6v v det = v th + 20 mv v det = 4.2v reset isource = 800 a v det = 3.0v reset isource = 500 a
tc1301a/b ds21798a-page 12 ? 2003 microchip technology inc. 3.0 tc1301a pin descriptions the descriptions of the pins are listed in table 3-1. table 3-1: tc1301a pin function table 3.1 reset output pin the push-pull output pin is used to monitor the voltage on the v det pin. if the v det voltage is less than the threshold voltage, the reset output will be held in the low state. as the v det pin rises above the threshold, the reset output will remain in the low state for 300 ms and then change to the high state, indicating that the voltage on the v det pin is above the threshold. 3.2 regulated output voltage #1 (v out1 ) connect v out1 to the positive side of the v out1 capacitor and load. it is capable of 300 ma maximum output current. v out1 output is available when v in is available; there is no pin to turn it off . see tc1301b, if on/off control of v out1 is desired. 3.3 circuit ground pin (gnd) connect gnd to the negative side of the input and output capacitor. only the ldo internal circuitry bias current flows out of this pin (200 a maximum). 3.4 reference bypass input by connecting an external 10 nf capacitor (typical) to the bypass input, both outputs (v out1 and v out2 ) will have less noise and improved power supply ripple rejection (psrr) performance. the ldo output voltage start-up time will increase with the addition of an external bypass capacitor. by leaving this pin unconnected, the start-up time w ill be minimized. 3.5 output voltage #2 shutdown (shdn2 ) on/off control is performed by connecting shdn2 to its proper level. when the input of this pin is connected to a voltage less than 15% of v in , v out2 will be off . if this pin is connected to a voltage that is greater than 45% of v in , v out2 will be turned on. 3.6 regulated output voltage #2 (v out2 ) connect v out2 to the positive side of the v out2 capacitor and load. this pin is capable of a maximum output current of 150 ma. v out2 can be turned on and off using shdn2 . 3.7 unregulated input voltage pin (v in ) connect the unregulated input voltage source to v in . if the input voltage source is located more than several inches away or is a battery, a typical input capacitance of 1 f to 4.7 f is recommended. 3.8 input pin for voltage detector (v det ) the voltage on the input of v det is compared with the preset v det threshold voltage. if the voltage is below the threshold, the reset output will be low. if the voltage is above the v det threshold, the reset output will be high after the reset time period. the i det supply current is typically 9 a at room temperature with v det =3.8v. pin no. name function 1 reset push-pull output pin that will remain low while v det is below the reset threshold and for 300 ms after v det rises above the reset threshold. 2v out1 regulated output voltage #1 capable of 300 ma. 3 gnd circuit ground pin. 4 bypass internal reference bypass pin. a 10 nf external capacitor can be used to further reduce output noise and improve psrr performance. 5 shdn2 output #2 shutdown control input. 6v out2 regulated output voltage #2 capable of 150 ma. 7v in unregulated input voltage pin. 8v det input pin for voltage detector (v det ).
? 2003 microchip technology inc. ds21798a-page 13 tc1301a/b 4.0 tc1301b pin descriptions the descriptions of the pins are listed in table 4-1. table 4-1: tc1301b pin function table 4.1 reset output pin the push-pull output pin is used to monitor the output voltage (v out1 ). if v out1 is less than the threshold voltage, the reset output will be held in the low state. as v out1 rises above the threshold, the reset output will remain in the low state for 300 ms and then change to the high state, indicating that the voltage on v out1 is above the threshold. 4.2 regulated output voltage #1 (v out1 ) connect v out1 to the positive side of the v out1 capacitor and load. it is capable of 300 ma maximum output current. for the tc1301b, v out1 can be turned on and off using the shdn1 input pin. 4.3 circuit ground pin (gnd) connect gnd to the negative side of the input and output capacitor. only the ldo internal circuitry bias current flows out of this pin (200 a maximum). 4.4 reference bypass input by connecting an external 10 nf capacitor (typical) to bypass, both outputs (v out1 and v out2 ) will have less noise and improved power supply ripple rejection (psrr) performance. the ldo output voltage start-up time will increase with the addition of an external bypass capacitor. by leaving this pin unconnected, the start-up time will be minimized. 4.5 output voltage #2 shutdown (shdn2 ) on/off control is performed by connecting shdn2 to its proper level. when this pin is connected to a voltage less than 15% of v in , v out2 will be off . if this pin is connected to a voltage that is greater than 45% of v in , v out2 will be turned on. 4.6 regulated output voltage #2 (v out2 ) connect v out2 to the positive side of the v out2 capacitor and load. this pin is capable of a maximum output current of 150 ma. v out2 can be turned on and off using shdn2 . 4.7 unregulated input voltage pin (v in ) connect the unregulated input voltage source to v in . if the input voltage source is located more than several inches away or is a battery, a typical minimum input capacitance of 1 f and 4.7 f is recommended. 4.8 output voltage #1 shutdown (shdn1 ) on/off control is performed by connecting shdn1 to its proper level. when this pin is connected to a voltage less than 15% of v in , v out1 will be off . if this pin is connected to a voltage that is greater than 45% of v in , v out1 will be turned on. pin no. name function 1 reset push-pull output pin that will remain low while v det is below the reset threshold and for 300 ms after v out1 rises above the reset threshold 2v out1 regulated output voltage #1 capable of 300 ma 3 gnd circuit ground pin 4 bypass internal reference bypass pin. a 10 nf external capacitor can be used to further reduce output noise and improve psrr performance 5 shdn2 output #2 shutdown control input 6v out2 regulated output voltage #2 capable of 150 ma 7v in unregulated input voltage pin 8 shdn1 output #1 shutdown control input
tc1301a/b ds21798a-page 14 ? 2003 microchip technology inc. 5.0 detailed description 5.1 device overview the tc1301a/b is a combination device consisting of: one 300 ma ldo regulator with a fixed output voltage, v out1 (1.5v - 3.3v), one 150 ma ldo regulator with a fixed output voltage, v out2 (1.5v - 3.3v), and a microcontroller voltage monitor/r eset (2.2v to 3.2v). for the tc1301a, the 300 ma output, v out1 is always present, independent of the level of shdn2 . the 150 ma output (v out2 ) can be turned on/off by controlling the level of shdn2 . for the tc1301b, v out1 and v out2 each have independent shutdown input pins (s hdn1 and shdn2 ) to control their respective outputs. in the case of the tc1301b, the voltage detect input of the microcontroller reset function is internally connected to the v out1 output of the device. 5.2 ldo output #1 ldo output #1 is rated for 300 ma of output current. the typical dropout voltage for v out1 = 104 mv @ 300 ma. a 1 f (minimum) output capacitor is needed for stability and should be located as close to the v out1 pin and ground as possible. 5.3 ldo output #2 ldo output #2 is rated for 150 ma of output current. the typical dropout voltage for v out2 = 150 mv. a 1 f (minimum) capacitor is needed for stability and should be located as close to the v out2 pin and ground as possible. 5.4 reset output the reset output is used to detect whether the level on the input of v det (tc1301a) or v out1 (tc1301b) is above or below a preset threshold. if the voltage detected is below the preset threshold, the reset output is capable of sinking 1.2 ma (v reset < 0.2v maximum). once the voltage being monitored is above the preset threshold, the reset output pin will transition from a logic-low to a logic-high after a 300 ms delay. the reset output is a push-pull configuration and will actively pull the reset output up to v det when not in reset . 5.5 input capacitor low input source impedance is necessary for the two ldo outputs to operate properly. when operating from batteries or in applications with long lead length (> 10 inches) between the input source and the ldo, some input capacitance is recommended. a minimum of 1.0 f to 4.7 f is recommended for most applications. when using large capacitors on the ldo outputs, larger capacitance is recommended on the ldo input. the capacitor should be placed as close to the input of the ldo as is practical. larger input capacitors will help reduce the input impedance and further reduce any high-frequency noise on the input and output of the ldo. 5.6 output capacitor a minimum output capacitance of 1 f for each of the tc1301a/b ldo outputs is necessary for stability. ceramic capacitors are recommended because of their size, cost and environmental robustness qualities. electrolytic (tantalum or aluminum) capacitors can be used on the ldo outputs as well. the equivalent series resistance (esr) requirements on the electrolytic output capacitor?s are between 0 and 2 ohms. the output capacitor should be located as close to the ldo output as is practical. ceramic materials x7r and x5r have low temperature coefficients and are well within the acceptable esr range required. a typical 1 uf x5r 0805 capacitor has an esr of 50 milli- ohms. larger ldo output capacitors can be used with the tc1301a/b to improve dynamic performance and power supply ripple rejection performance. a maximum of 10 f is recommended. aluminum electrolytic capacitors are not recommended for low temperature applications of < -25c. 5.7 bypass input the bypass pin is connected to the internal ldo reference. by adding capacitance to this pin, the ldo ripple rejection, input voltage transient response and output noise performance are all increased. a typical bypass capacitor between 470 pf to 10 nf is recommended. larger bypass capacitors can be used, but results in a longer time-period for the ldo outputs to reach their rated output voltage when started from shdn or v in . 5.8 gnd for the optimal noise and psrr performance, the gnd pin of the tc1301a/b should be tied to a quiet circuit ground. for applications that have switching or noisy inputs, tie the gnd pin to the return of the output capacitor. ground planes help lower inductance and voltage spikes caused by fast transient load currents and are recommended for applications that are subjected to fast load transients. 5.9 shdn1 / shdn2 operation the tc1301a shdn2 pin is used to turn v out2 on and off . a logic-high level on shdn2 will enable the v out2 output, while a logic-low on the shdn2 pin will disable the v out2 output. for the tc1301a, v out1 is not affected by shdn2 and will be enabled as long as the input voltage is present. the tc1301b shdn1 and shdn2 pins are used to turn v out1 and v out2 on and off . they operate independent of each other.
? 2003 microchip technology inc. ds21798a-page 15 tc1301a/b 5.10 tc1301a shdn2 timing v out1 will rise independent of the level of shdn2 for the tc1301a. figure 5-1 is used to define the wake-up time from shutdown (t wk ) and the settling time (t s ). the wake-up time is dependant upon the frequency of operation. the faster the s hdn pin is pulsed, the shorter the wake-up time will be. figure 5-1: tc1301a timing. 5.11 tc1301b shdn1 / shdn2 timing for the tc1301b, the shdn1 input pin is used to control v out1 . the shdn2 input pin is used to control v out2 , independent of the logic input on shdn1 . figure 5-2: tc1301b timing. 5.12 v det and reset operation the tc1301a/b integrates an independent voltage reset monitor that can be used for low battery input voltage detection or a microprocessor power-on reset (por) function. the input voltage for the detector is different for the tc1301a than it is for the tc1301b. for the tc1301a, the input voltage to the detector is pin 8, or the v det pin. for the tc1301b, the input voltage to the detector is internally connected to the output of ldo #1 (v out1 ). the detected voltage is sensed and compared to an internal threshold. when the voltage on the v det pin is below the threshold voltage, the reset output pin is low. when the voltage on the v det pin rises above the voltage threshold, the reset output will remain low for typically 300 ms (reset time out period). after the reset time-out period, the reset output voltage will transition from the low output state to the high output state if the detected voltage pin remains above the threshold voltage. the reset output will be driven low within 180 s of v det going below the reset voltage threshold. the reset output will remain valid for detected voltages greater than 1.2v overtemperature. 5.13 tc1301a reset timing figure 5-3 shows the reset timing waveforms for the tc1301a. this diagram is also used to define the reset active time-out period (t rpu ) and the v det reset delay time (t rpd ). figure 5-3: tc1301a reset timing. v in shdn2 v out1 v out2 t wk t s shdn2 shdn1 v in v out1 t wk t s v out2 reset time t rpd v th v det reset 1v v ol v oh
tc1301a/b ds21798a-page 16 ? 2003 microchip technology inc. 5.14 tc1301b reset timing the timing waveforms for the tc1301b reset output are shown in figure 5-4. note that the reset threshold input for the tc1301b is v out1 . the v out1 to reset threshold detector connection is made internal in the case of the tc1301b. figure 5-4: tc1301b reset timing. 5.15 device protection 5.15.1 overcurrent limit in the event of a faulted output load, the maximum current the ldo output will permit to flow is limited internally for each of the tc1301a/b outputs. the peak current limit for v out1 is typically 1.1a, while the peak current limit for v out2 is typically 0.5a. during short- circuit operation, the average current is limited to 200 ma for v out1 and 140 ma for v out2 .the v det and reset circuit will continue to operate in the event of an overcurrent on either output for the tc1301a. the voltage detect and reset circuit will continue to operate in the event of an overcurrent on v out1 (or v out2 ) for the tc1301b. in the event of an overcurrent on v out1 , the reset will detect the absence of v out1 . 5.15.2 overtemperature protection if the internal power dissipation within the tc1301a/b is excessive due to a faulted load or higher than specified line voltage, an internal temperature sensing element will prevent the junction temperature from exceeding approximately 150 c. if the junction temperature does reach 150 c, both outputs will be disabled until the junction temperature cools to approximately 140 c. the device will resume normal operation. if the internal power dissipation continues to be excessive, the device will again shut off. the v det and reset circuit will continue to operate normally during an overtemperature fault condition for both the tc1301a and tc1301b. reset time t rpd v th v out1 reset 1v v ol v oh v in
? 2003 microchip technology inc. ds21798a-page 17 tc1301a/b 6.0 application circuits/ issues 6.1 typical application the tc1301a/b is used for applications that require the integration of two ldo?s and a microcontroller reset . figure 6-1: typical application circuit tc1301a/b. 6.1.1 application input conditions 6.2 power calculations 6.2.1 power dissipation the internal power dissipation within the tc1301a/b is a function of input voltage, output voltage, output current and quiescent current. the following equation can be used to calculate the internal power dissipation for each ldo. equation in addition to the ldo pass element power dissipation, there is power dissipation within the tc1301a/b as a result of quiescent or ground current. the power dissipation as a result of the ground current can be calculated using the following equation. the v in pin quiescent current and the v det pin current are both considered. the v in current is a result of ldo quiescent current, while the v det current is a result of the voltage detector current. equation the total power dissipated within the tc1301a/b is the sum of the power dissipated in both of the ldo?s and the p(i gnd ) term. because of the cmos construction, the typical i gnd for the tc1301a/b is 116 a. operating at a maximum of 4.2v results in a power dissipation of 0.5 milli-watts. for most applications, this is small compared to the ldo pass device power dissipation and can be neglected. the maximum continuous operating junction temperature specified for the tc1301a/b is 125 c . to estimate the internal junction temperature of the tc1301a/b, the total internal power dissipation is multiplied by the thermal resistance from junction to ambient (r ja ), thermal resistance from junction to ambient, of the device. the thermal resistance from junction to ambient for the 3x3dfn8 pin package is estimated at 41 c/w. equation package type = 3x3dfn8 input voltage range = 2.7v to 4.2v v in maximum = 4.2v v in typical = 3.6v v out1 = 300 ma maximum v out2 = 150 ma maximum system reset load = 10 k ? 8 4 1 2 3 reset gnd v det battery c out1 1f ceramic x5r c in 1f tc1301a c out2 1f ceramic x5r c bypass 10 nf ceramic bypass v in 7 2.7v to 4.2v v out2 6 shdn2 on/off control v out2 system reset 2.8v @ 300 ma 1.8v 5 v out1 8 4 1 2 3 reset battery c out1 1f ceramic x5r c in 1f tc1301b c out2 1f ceramic x5r bypass v in 7 2.7v to 4.2v v out2 6 shdn2 on/off control v out2 system reset 2.8v @ 300 ma 1.8v 5 on/off control v out1 v out1 @ 150 ma gnd @ 150 ma s hdn1 p ldo v in max ) () v out min () ? () i out max ) () = p ldo = ldo pass device internal power dissipation v in(max) = maximum input voltage v out(min) = ldo minimum output voltage p ignd () v in max () i vin i vdet + () = p i(gnd) = total current in ground pin. v in(max) = maximum input voltage. i vin = current flowing in the v in pin with no output current on either ldo output. i vdet = current in the v det pin with reset loaded. t jmax () p total r ja t amax + = t j(max) = maximum continuous junction temperature. p total = total device power dissipation. r ja = thermal resistance from junction to ambient. t amax = maximum ambient temperature.
tc1301a/b ds21798a-page 18 ? 2003 microchip technology inc. the maximum power dissipation capability for a package can be calculated given the junction to ambient thermal resistance and the maximum ambient temperature for the application. the following equation can be used to determine the package maximum internal power dissipation. equation equation equation 6.3 typical application internal power dissipation, junction temperature rise, junction temperature and maximum power dissipation are calculated in the following example. the power dissipation as a result of ground current is small enough to be neglected. 6.3.1 power dissipation example device junction temperature rise the internal junction temperature rise is a function of internal power dissipation and the thermal resistance from junction to ambient for the application. the thermal resistance from junction to ambient (r ja ) is derived from an eia/jedec standard for measuring thermal resistance for small surface-mount packages. the eia/jedec specification is jesd51-7, ?high effective thermal conductivity test board for leaded surface mount packages?. the standard describes the test method and board specifications for measuring the thermal resistance from junction to ambient. the actual thermal resistance for a particular application can vary depending on many factors such as copper area and thickness. refer to an792, ?a method to determine how much power a sot32 can dissapate in your application? (ds00792), for more information regarding this subject. junction temperature estimate to estimate the internal junction temperature, the calculated temperature rise is added to the ambient or offset temperature. for this example, the worst-case junction temperature is estimated below: maximum package power dissipation at 50c ambient temperature package package type = 3x3dfn8 input voltage v in = 2.7v to 4.2v ldo output voltages and currents v out1 = 2.8v i out1 =300ma v out2 = 1.8v i out2 =150ma p dmax () t jmax () t amax () ? () r ja --------------------------------------------------- = p d(max) = maximum device power dissipation. t j(max) = maximum continuous junction temperature. t a(max) = maximum ambient temperature. r ja = thermal resistance from junction to ambient. t jrise () p dmax () r ja = t j(rise) = rise in device junction temperature over the ambient temperature. p d(max) = maximum device power dissipation. r ja = thermal resistance from junction-to-ambient. t j t jrise () t a + = t j = junction temperature. t j(rise) = rise in device junction temperature over the ambient temperature. t a = ambient temperature. maximum ambient temperature t a(max) =50c internal power dissipation internal power dissipation is the sum of the power dissipation for each ldo pass device. p ldo1(max) =(v in(max) - v out1(min) ) x i out1(max) p ldo1 = (4.2v - (0.975 x 2.8v)) x 300 ma p ldo1 = 441.0 milli-watts p ldo2 = (4.2v - (0.975 x 1.8v)) x 150 ma p ldo2 = 366.8 milli-watts p total =p ldo1 + p ldo2 p total = 807.8 milli-watts t j(rise) =p total x rq ja t jrise = 807.8 milli-watts x 41.0 c/watt t jrise = 33.1 c t j =t jrise + t a(max) t j = 83.1c 3x3dfn8 (41c/watt r ja ) p d(max) = (125c - 50c) / 41c/w p d(max) = 1.83 watts msop8 (208c/watt r ja ) p d(max) = (125c - 50c) / 208c/w p d(max) = 0.360 watts
? 2003 microchip technology inc. ds21798a-page 19 tc1301a/b 7.0 typical layout tc1301a figure 7-1: msop8 silk screen layer. when doing the physical layout for the tc1301a/b, the highest priority is placing the input and output capacitors as close to the device pins as is practical. figure 7-1 above represents a typical placement of the components when using smt0805 capacitors. figure 7-2: msop8 wiring layer. a wiring example for the tc1301a is shown. the vias represent the connection to a ground plane that is below the wiring layer. figure 7-3: dfn3x3 silk screen example. 8-lead 3x3 dfn physical layout example with bypass capacitor. figure 7-4: dfn3x3 top metal layer example. vias represent the connection to a ground plane that is below the wiring layer. 8.0 additional output voltage and threshold voltage options 8.1 output voltage and threshold voltage range table 8-1 describes the range of output voltage options available for the tc1301a/b. v out1 and v out2 can be factory preset from 1.5v to 3.3v in 100 mv increments. the v det (tc1301a) or threshold voltage (tc1301b) can be preset from 2.2v to 3.2v in 10 mv increments. table 8-1: custom output voltage and threshold voltage ranges for a listing of tc1301a/b standard parts, refer to the product identification system on page 23. v out1 v out2 v det threshold 1.5v to 3.3v 1.5v to 3.3v 2.2v to 3.2v
tc1301a/b ds21798a-page 20 ? 2003 microchip technology inc. 9.0 packaging information 9.1 package marking information x1 represents v out1 configuration: x2 represents v out2 configuration: xr represents the reset voltage range: x represents the temperature range: xx represents the device packaging: xx represents tube or tape and reel: for a listing of tc1301a/b standard parts, refer to the product identification system on page 23. 8-lead msop 31afha ywwnnn 8-lead dfn bfha yyww nnn part no. x- x1 v out1 type a/b tc1301 x2 v out2 xr reset voltage x te m p range xx package xx tube or tape & reel code v out1 code v out1 code v out1 a3.3vj2.4vs1.5v b3.2vk2.3vt1.65v c 3.1v l 2.2v u 2.85v d 3.0v m 2.1v v 2.65v e 2.9v n 2.0v w 1.85v f2.8vo1.9vx ? g2.7vp1.8vy ? h2.6vq1.7vz ? i2.5vr1.6v code v out2 code v out1 code v out2 a3.3vj2.4vs1.5v b3.2vk2.3vt1.65v c 3.1v l 2.2v u 2.85v d 3.0v m 2.1v v 2.65v e 2.9v n 2.0v w 1.85v f2.8vo1.9vx ? g2.7vp1.8vy ? h2.6vq1.7vz ? i2.5vr1.6v code voltage code voltage a2.63vj ? b2.2k ? c2.32l ? d2.5m ? e2.4n ? f2.6o ? g?p? h?q? i?r? v = -40 c to +125 c mf = 8-pin dfn (3x3) ua = 8-pin msop no designator = tube (standard) tr = tape and reel
? 2003 microchip technology inc. ds21798a-page 21 tc1301a/b 8-lead plastic micro small outline package (ua) (msop) d a a1 l c (f) a2 e1 e p b n 1 2 dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not .037 ref f footprint (reference) exceed .010" (0.254mm) per side. notes: drawing no. c04-111 *controlling parameter mold draft angle top mold draft angle bottom foot angle lead width lead thickness c b .003 .009 .006 .012 dimension limits overall height molded package thickness molded package width overall length foot length standoff overall width number of pins pitch a l e1 d a1 e a2 .016 .024 .118 bsc .118 bsc .000 .030 .193 typ. .033 min p n units .026 bsc nom 8 inches 0.95 ref - - .009 .016 0.08 0.22 0 0.23 0.40 8 millimeters* 0.65 bsc 0.85 3.00 bsc 3.00 bsc 0.60 4.90 bsc .043 .031 .037 .006 0.40 0.00 0.75 min max nom 1.10 0.80 0.15 0.95 max 8 -- - 15 5 - 15 5 - jedec equivalent: mo-187 0 - 8 5 5 - - 15 15 - - - -
tc1301a/b ds21798a-page 22 ? 2003 microchip technology inc. 8-lead plastic dual flat no lead package (mf) 3x3x1 mm body (dfn) e2 d dimensions d and e do not include mold flash or protrusions. mold flash or protrusions shall not exposed pad width exposed pad length lead length *controlling parameter lead width drawing no. c04-062 notes: exposed pad dimensions vary with paddle size. exceed .010" (0.254mm) per side. overall width d2 e2 l b d .019 .012 .007 .047 .055 .010 .118 bsc a1 number of pins standoff lead thickness overall length overall height pitch a a3 p n units a a1 e a3 dimension limits 8 .000 .001 .008 ref. .118 bsc .031 .026 bsc min inches nom top view exposed metal pad 0.48 0.26 3.00 bsc 0.30 .022 .069 .015 .096 0.23 1.20 1.39 0.55 0.37 1.75 2.45 0.02 0.80 3.00 bsc 0.20 ref. 0.65 bsc millimeters* .002 .039 0.00 min max nom 8 0.05 1.00 max bottom view 2 1 id index pin 1 e l d2 p b n 3. 4. package may have one or more exposed tie bars at ends. 1. area pin 1 visual index feature may vary, but must be located within the hatched area. 2. (note 2) tie bar (note 1) exposed 0.90 .035 (note 4) (note 4) 5. jedec equivalent: pending
? 2003 microchip technology inc. ds21798a-page 23 tc1301a/b product identification system to order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office . sales and support device: tc1301a: dual ldo with microcontroller reset function tc1301b: dual ldo with microcontroller reset function output voltage: v out1 v out2 a = 3.3v b = 3.2v c = 3.1v d = 3.0v e = 2.9v f = 2.8v g = 2.7v h = 2.6v i = 2.5v j = 2.4v k = 2.3v l = 2.2v m = 2.1v n = 2.0v o = 1.9v p = 1.8v q = 1.7v r = 1.6v s = 1.5v t = 1.65v u = 2.85v v = 2.65v w = 1.85v a=3.3v b=3.2v c=3.1v d=3.0v e=2.9v f=2.8v g=2.7v h=2.6v i=2.5v j=2.4v k=2.3v l=2.2v m=2.1v n=2.0v o=1.9v p=1.8v q=1.7v r=1.6v s=1.5v t=1.65v u=2.85v v=2.65v w=1.85v reset voltage: a = 2.63v b = 2.2v c = 2.32v d = 2.5v e = 2.4v f = 2.6v temperature range: v = -40c to +125c package: mf = dual flat, no lead (3x3 mm body), 8-lead mftr = dual flat, no lead (3x3 mm body), 8-lead (tape and reel) ua = plastic micro small outline (msop), 8-lead uatr = plastic micro small outline (msop), 8-lead (tape and reel) examples: a) tc1301a-fhavuatr:tape and reel, 8l-msop package. b) tc1301a-fhavua: 8l-msop package. c) tc1301a-fhavmftr:tape and reel, 8l-dfn package. d) tc1301a-fhavmf: 8l-dfn package. a) tc1301b-fhavmftr:tape and reel, 8l-dfn package. b) tc1301b-fhavmf: 8l-dfn package. c) tc1301b-fhavuatr:tape and reel, 8l-msop package. d) tc1301b-fhavua: 8l-msop package. tc1301 standard parts device v out1 /v out2 /reset part number tc1301a 2.8/2.6/2.63 tc1301afhavxxxx tc1301a 1.8/2.6/2.4 tc1301aphevxxxx tc1301a 2.0/2.5/2.32 tc1301anicvxxxx tc1301a 2.9/2.7/2.63 tc1301aegavxxxx tc1301a 2.9/2.8/2.63 tc1301aefavxxxx tc1301a 2.9/3.0/2.63 tc1301aedavxxxx tc1301a 2.8/2.7/2.63 tc1301afgavxxxx tc1301a 2.8/2.8/2.63 tc1301affavxxxx tc1301a 2.8/2.9/2.63 tc1301afeavxxxx tc1301a 2.8/3.0/2.63 tc1301afdavxxxx tc1301b 2.9/2.7/2.63 tc1301begavxxxx tc1301b 2.9/2.8/2.63 tc1301befavxxxx tc1301b 2.9/3.0/2.63 tc1301bedavxxxx tc1301b 2.8/2.7/2.63 tc1301bfgavxxxx tc1301b 2.8/2.8/2.63 tc1301bffavxxxx tc1301b 2.8/2.9/2.63 tc1301bfeavxxxx tc1301b 2.8/3.0/2.63 tc1301bfdavxxxx tc1301b 1.8/2.7/2.63 tc1301bpgavxxxx tc1301b 2.7/2.7/2.5 tc1301bggdvxxxx tc1301b 2.7/2.8/2.5 tc1301bgfdvxxxx tc1301b 2.85/1.85/2.6 tc1301buwfvxxxx tc1301b 2.85/1.8/2.6 tc1301bupfvxxxx tc1301b 3.3/1.8/2.63 tc1301bapavxxxx tc1301b 2.8/2.6/2.63 tc1301bfhavxxxx part no. x- x v out1 type a/b tc1301 x v out2 x reset vo lta ge x temp range xx package xx tube or tape & reel data sheets products supported by a preliminary data sheet may have an errata sheet describing minor operational differences and recommended workarounds. to determine if an errata sheet exists for a particular device, please contact one of the following: 1. your local microchip sales office 2. the microchip corporate literature center u.s. fax: (480) 792-7277 3. the microchip worldwide site (www.microchip.com) please specify which device, revision of silicon and data sheet (include literature #) you are using. customer notification system register on our web site (www.microchip.com/cn) to receive the most current information on our products.
tc1301a/b ds21798a-page 24 ? 2003 microchip technology inc. notes:
? 2003 microchip technology inc. ds21798a-page 25 information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. no representation or warranty is given and no liability is assumed by microchip technology incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. use of microchip?s products as critical components in life support systems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or otherwise, under any intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , mplab, pic, picmicro, picstart, pro mate and powersmart are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. amplab, filterlab, micro id , mxdev, mxlab, picmaster, seeval and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. application maestro, dspicdem, dspicdem.net, ecan, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, microport, migratable memory, mpasm, mplib, mplink, mpsim, pickit, picdem, picdem.net, powercal, powerinfo, powermate, powertool, rflab, rfpic, select mode, smartsensor, smartshunt, smarttel and total endurance are trademarks of microchip technology incorporated in the u.s.a. and other countries. serialized quick turn programming (sqtp) is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2003, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: ? microchip products meet the specification contained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip products in a manner outside the operating specifications contained in microchip's data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconductor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received qs-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona in july 1999 and mountain view, california in march 2002. the company?s quality system processes and procedures are qs-9000 compliant for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms, microperipherals, non-volatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001 certified.
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