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  to our customers, old company name in catalogs and other documents on april 1 st , 2010, nec electronics corporation merged with renesas technology corporation, and renesas electronics corporation took over all the business of both companies. therefore, although the old company name remains in this document, it is a valid renesas electronics document. we appreciate your understanding. renesas electronics website: http://www.renesas.com april 1 st , 2010 renesas electronics corporation issued by: renesas electronics corporation (http://www.renesas.com) send any inquiries to http://www.renesas.com/inquiry.
notice 1. all information included in this document is current as of the date this document is issued. such information, however, is subject to change without any prior notice. before purchasing or using any renesas el ectronics products li sted herein, please confirm the latest product information with a renesas electronics sales office. also , please pay regular and careful attention to additional and different information to be disclosed by rene sas electronics such as that disclosed through our website. 2. renesas electronics does not assume any liability for infringeme nt of patents, copyrights, or other intellectual property ri ghts of third parties by or arising from the use of renesas electroni cs products or techni cal information descri bed in this document . no license, express, implied or otherwise, is granted hereby under any patents, copyri ghts or other intell ectual property right s of renesas electronics or others. 3. you should not alter, modify, copy, or otherwise misappropriate any re nesas electronics product, wh ether in whole or in part . 4. descriptions of circuits, software and other related informat ion in this document are provided only to illustrate the operat ion of semiconductor products and application examples. you are fully re sponsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 5. when exporting the products or technology described in this doc ument, you should comply with the applicable export control laws and regulations and follow the proc edures required by such laws and re gulations. you should not use renesas electronics products or the technology described in this docum ent for any purpose relating to mil itary applicati ons or use by the military, including but not l imited to the development of weapons of mass de struction. renesas electronics products and technology may not be used for or incor porated into any products or systems whose manufacture, us e, or sale is prohibited under any applicable dom estic or foreign laws or regulations. 6. renesas electronics has used reasonable care in preparing th e information included in this document, but renesas electronics does not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein. 7. renesas electronics products ar e classified according to the following three quality grades: ?standard?, ?high quality?, an d ?specific?. the recommended applications for each renesas electronics product de pends on the product?s quality grade, as indicated below. you must check the qua lity grade of each renesas electronics pr oduct before using it in a particular application. you may not use any renesas electronics produc t for any application categorized as ?speci fic? without the prior written consent of renesas electronics. further, you may not use any renesas electronics product for any application for which it is not intended without the prior written consent of renesas electronics. re nesas electronics shall not be in any way liable for any damages or losses incurred by you or third partie s arising from the use of any renesas electronics product for a n application categorized as ?specific? or for which the product is not intende d where you have failed to obtain the prior writte n consent of renesas electronics. the quality grade of each renesas electronics product is ?standard? unless otherwise expressly specified in a renesas electr onics data sheets or data books, etc. ?standard?: computers; office equipmen t; communications e quipment; test and measurement equipment; audio and visual equipment; home electronic a ppliances; machine tools; personal electronic equipmen t; and industrial robots. ?high quality?: transportation equi pment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; an ti- crime systems; safety equipment; and medical equipment not specif ically designed for life support. ?specific?: aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support device s or systems), surgical im plantations, or healthcare intervention (e.g. excision, etc.), and any other applicati ons or purposes that pose a di rect threat to human life. 8. you should use the renesas electronics pr oducts described in this document within the range specified by renesas electronics , especially with respect to the maximum ra ting, operating supply voltage range, movement power volta ge range, heat radiation characteristics, installation and other product characteristics. renesas electronics shall have no liability for malfunctions o r damages arising out of the use of renesas electronics products beyond such specified ranges. 9. although renesas electronics endeavors to improve the quality and reliability of its produc ts, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate a nd malfunctions under certain use conditions. fur ther, renesas electronics products are not subject to radiation resistance design. please be sure to implement safety measures to guard them against the possibility of physic al injury, and injury or damage caused by fire in the event of the failure of a renesas electronics product, such as safe ty design for hardware and software in cluding but not limited to redundancy, fire control and malfunction prevention, appropri ate treatment for aging degradation or an y other appropriate measures. because the evaluation of microcomputer software alone is very difficult , please evaluate the safety of the final products or system manufactured by you. 10. please contact a renesa s electronics sales office for details as to environmental matters such as the environmental compatibility of each renesas electronics product. please use renesas electronics products in compliance with all applicable laws and regulations that regul ate the inclusion or use of c ontrolled substances, including wi thout limitation, the eu rohs directive. renesas electronics assumes no liability for damage s or losses occurring as a result of your noncompliance with applicable laws and regulations. 11. this document may not be reproduced or duplicated, in any form, in w hole or in part, without prio r written consent of renes as electronics. 12. please contact a renesa s electronics sales office if you have any questi ons regarding the informat ion contained in this document or renesas electroni cs products, or if you have any other inquiries. (note 1) ?renesas electronics? as used in this document means renesas electronics corporation and also includes its majority- owned subsidiaries. (note 2) ?renesas electronics product(s)? means any product developed or manufactured by or for renesas electronics.
m m m m m pd75312b m m m m m pd75304 m m m m m pd75316 m m m m m pd75304b m m m m m pd75316b m m m m m pd75306 m m m m m pd75p308 m m m m m pd75306b m m m m m pd75p316 m m m m m pd75308 m m m m m pd75p316a m m m m m pd75308b m m m m m pd75p316b m m m m m pd75312 m m m m m pd75308 4-bit single-chip microcontroller ? 1994 1989 document no. u11023ejcv0um00 (12th edition) (previous no. ieu-1263) date published april 1996 p printed in japan
notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. ms-dos is a trademark of microsoft corporation. ibm dos, pc dos, and pc/at are trademarks of ibm corporation.
the export of these products from japan is regulated by the japanese government. the export of some or all of these products may be prohibited without governmental license. to export or re-export some or all of these products from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. license needed : m pd75p308k m pd75p316ak m pd75p316bkk-t the customer must judge : m pd75304gf- -3b9 m pd75p308gf-3b9 the need for license m pd75304bgc- -3b9 m pd75312gf- -3b9 m pd75304bgf- -3b9 m pd75312bgc- -3b9 m pd75304bgk- -be9 m pd75312bgk- -be9 m pd75306gf- -3b9 m pd75316gf- -3b9 m pd75306bgc- -3b9 m pd75316bgc- -3b9 m pd75306bgf- -3b9 m pd75316bgk- -be9 m pd75306bgk- -be9 m pd75p316gf-3b9 m pd75308gf- -3b9 m pd75p316agf-3b9 m pd75308bgc- -3b9 m pd75p316bgc-3b9 m pd75308bgf- -3b9 m pd75p316bgk-be9 m pd75308bgk- -be9 the information in this document is subject to change without notice. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customer must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: standard, special, and specific. the specific quality grade applies only to devices developed based on a customer designated quality assurance program for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices in standard unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact nec sales representative in advance. anti-radioactive design is not implemented in this product. m7 94.11
major revisions in this version section description whole manual m pd75p316b has been developed. p.203 the note in figure 5-83. examples of lcd drive power supply connection (with external split resistor) has been modified and a caution has been added to this figure. p.235 the example in 6.6 v ector address sharing interrupt servicing has been modified. p.313 appendix a development tools the version of the supported os has been up-graded. p.325 appendix e revision history has been added. the mark shows major revised points.
preface intended readership this manual describes the functions of the m pd7530x/7531x products, and is intended for users technical personnel involved in the design of application systems using them. purpose the purpose of this manual is to explain to the user the hardware functions of the m pd75304, 75304b, 75306, 75306b, 75308, 75308b, 75p308, 75312, 75312b, 75316, 75316b, 75p316, 75p316a and 75p316b following the organization shown below. organization this manual is broadly organized into the following sections: ? general description ? pin functions ? architectural features and memory mapping ? internal cpu functions ? peripheral hardware functions ? interrupt functions ? standby functions ? reset functions ? prom write and verify ? instruction set using this manual readers of this manual need to have a general understanding of electricity, logical circuits and microcontrollers. ? users employing this manual for the m m m m m pd7530x/7531x products ? insofar as there are no particular functional differences between the various products, the m pd75308 is taken as the representative device for the descriptions in this manual. after checking the functional differences described in 1.3 list of functions of series products, m pd75308 can be read as the respective product name when using the manual. ? users employing this manual for the m m m m m pd75p308k, m m m m m pd75p316ak or m m m m m pd75p316bkk-t ? in those sections of this manual which apply to both prom and eprom products, the term prom is used to represent both. when using this manual for an eprom product, prom can be read as eprom. ? users who has previous experience of operating the m m m m m pd75304, 75306, 75308 and 75p308 ? read 1.3 list of functions of series products to check for differences in functions between products. ? when checking the instruction functions from mnemonic ? refer to appendix c instruction index . ? when checking the function of the particular on-chip circuit ? refer to appendix d hardware index . ? for a general understanding of the m m m m m pd7530x/7531x products. ? first read 1.1 function outline to get an understanding of the main functions, then read the manual according to the contents.
? for the electrical specifications of m m m m m pd7530x/7531x products ? refer to the separate data sheet. ? for application example of various functions of m m m m m pd7530x/7531x products ? refer to the separate application note. explanatory notes data notation : the most significant digit on left, the least significant digit on right active low notation : xxx (line above pin or signal name) memory map addresses : high-order address below, low-order address above note : description of note included in the text caution : statement drawing particular attention remark : supplementary description of text important item, emphasis : boldface notation numeric notation : binary number ................... xxxx or xxxxb decimal number ................ xxxx hexadecimal number ........ xxxxh relevant documents documents related to m m m m m pd75308 document no. brochure data sheet users manual instruction list application note application note product (fundamental) (sbi application) m pd75304 m pd75306 ic-2523 m pd75308 m pd75p308 ic-2472 m pd75312 ic-2477 m pd75316 m pd75p316 ic-2651 u11023e iem-1239 iem-1245 m pd75p316a ic-2524 (this manual) m pd75304b m pd75306b ic-2913 m pd75308b m pd75312b ic-3196 m pd75316b m pd75p316b ic-3189 documents related to whole 75x series data book 75x series vol.1 4-bit single-chip microcontroller 75x series vol.2 4-bit single-chip microcontroller selection guide 75x series if-1027
documents related to development tool document name document number hardware ie-75000-r/ie-75001-r users manual eeu-1416 ie-75000-r-em users manual eeu-1294 ep-75308gf-r users manual eeu-1301 ep-75308bgc-r users manual eeu-1406 ep-75308bgk-r users manual eeu-1408 pg-1500 users manual eeu-1335 software ra75x assembler package users manual operation eeu-1346 language eeu-1364 pg-1500 controller users manual pc-9800 series (ms-dos tm ) base eeu-1291 ibm pc series (pc dos tm ) base u10540e remark ie control programs are explained in the ie-75000-r/ie-75001-r users manual.
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C i C contents chapter 1 general description ................................................................................................ 1 1.1 function outline ................................................................................................................. 3 1.2 ordering information ......................................................................................................... 5 1.3 list of functions of series products .............................................................................. 6 1.4 block diagram .................................................................................................................. 10 1.5 pin configuration (top view) ......................................................................................... 11 chapter 2 pin functions .............................................................................................................. 15 2.1 list of pin functions ....................................................................................................... 15 2.1.1 normal operating mode ........................................................................................................ 15 2.1.2 prom mode ........................................................................................................................... 19 2.2 description of pin functions ......................................................................................... 23 2.2.1 p00 to p03 (port 0) ................................................................................................................ 23 p10 to p13 (port 1) ................................................................................................................ 23 2.2.2 p20 to p23 (port 2) ................................................................................................................ 24 p30 to p33 (port 3) ................................................................................................................ 24 p40 to p43 (port 4), p50 to p53 (port 5) ............................................................................. 24 p60 to p63 (port 6), p70 to p73 (port 7) ............................................................................. 24 2.2.3 bp0 to bp7 ............................................................................................................................. 24 2.2.4 ti0 ............................................................................................................................................ 24 2.2.5 pto0 ........................................................................................................................................ 24 2.2.6 pcl .......................................................................................................................................... 24 2.2.7 buz .......................................................................................................................................... 25 2.2.8 sck, so/sb0, si/sb1 ............................................................................................................ 25 2.2.9 int4 ......................................................................................................................................... 25 2.2.10 int0, int1 ............................................................................................................................... 25 2.2.11 int2 ......................................................................................................................................... 26 2.2.12 kr0 to kr3 ............................................................................................................................. 26 kr4 to kr7 ............................................................................................................................. 26 2.2.13 s0 to s23 ................................................................................................................................ 26 s24 to s31 .............................................................................................................................. 26 2.2.14 com0 to com3 ...................................................................................................................... 26 2.2.15 v lc0 to v lc2 ............................................................................................................................. 26 2.2.16 bias ........................................................................................................................................ 26 2.2.17 lcdcl ..................................................................................................................................... 26 2.2.18 sync ....................................................................................................................................... 26 2.2.19 x1, x2 ...................................................................................................................................... 27 2.2.20 xt1, xt2 ................................................................................................................................. 27 2.2.21 reset ..................................................................................................................................... 28 2.2.22 v dd ........................................................................................................................................... 28 2.2.23 v ss ........................................................................................................................................... 28 2.2.24 v pp ........................................................................................................................................... 28 2.2.25 md0 to md3 ............................................................................................................................ 28 2.2.26 ic ............................................................................................................................................. 28
C ii C 2.3 input/output circuits of pins ......................................................................................... 29 2.4 selection of mask option ................................................................................................ 31 2.5 treatment of unused pins .............................................................................................. 32 2.6 caution of use of p00/int4 pin and reset pin .......................................................... 33 chapter 3 features of architecture and memory map ............................................... 35 3.1 data memory bank configuration and addressing mode .......................................... 35 3.1.1 data memory bank configuration ....................................................................................... 35 3.1.2 data memory addressing mode .......................................................................................... 37 3.2 memory mapped i/o ......................................................................................................... 48 chapter 4 internal cpu function ........................................................................................... 53 4.1 program counter (pc) ..................................................................................................... 53 4.2 program memory (rom) ... ............................................................................................. 54 4.3 data memory (ram) ... ..................................................................................................... 60 4.3.1 data memory configuration ................................................................................................. 60 4.3.2 data memory bank specification ........................................................................................ 61 4.4 general register .............................................................................................................. 65 4.5 accumulator ..................................................................................................................... 66 4.6 stack pointer (sp) ............................................................................................................ 66 4.7 program status word (psw) .......................................................................................... 70 4.8 bank select register (bs) .............................................................................................. 73 chapter 5 peripheral hardware functions ...................................................................... 75 5.1 digital input/output port ................................................................................................. 75 5.1.1 types, features and configurations of digital input/output ports .................................. 77 5.1.2 input/output mode setting ................................................................................................... 81 5.1.3 digital input/output port manipulation instruction .......................................................... 82 5.1.4 digital input/output port operations ................................................................................... 85 5.1.5 integration of pull-up resistor ............................................................................................. 87 5.1.6 input/output timing of digital input/output port ............................................................... 88 5.2 clock generator circuit .................................................................................................. 90 5.2.1 clock generator circuit configuration ................................................................................ 90 5.2.2 clock generator circuit functions and operations ........................................................... 91 5.2.3 system clock and cpu clock setting ................................................................................. 99 5.2.4 clock output circuit ............................................................................................................ 101 5.3 basic interval timer ....................................................................................................... 104 5.3.1 basic interval timer configuration .................................................................................... 104 5.3.2 basic interval timer mode register (btm) ....................................................................... 105 5.3.3 basic interval timer operations ......................................................................................... 106 5.3.4 basic interval timer application examples ...................................................................... 107 5.4 watch timer .................................................................................................................... 109 5.4.1 watch timer configuration ................................................................................................. 109 5.4.2 watch mode register ........................................................................................................... 110 5.5 timer/event counter ....................................................................................................... 111 5.5.1 timer/event counter configuration .................................................................................... 111 5.5.2 basic configuration and operations of timer/event counter ........................................ 113
C iii C 5.5.3 timer/event counter mode register (tm0) and timer/event counter output enable flag (toe0) ................................................................................... 114 5.5.4 timer/event counter operating mode ............................................................................... 117 5.5.5 timer/event counter time set ............................................................................................. 118 5.5.6 precautions relating to timer/event counter application .............................................. 119 5.5.7 timer/event counter application ....................................................................................... 123 5.6 serial interface ............................................................................................................... 124 5.6.1 serial interface functions ................................................................................................... 124 5.6.2 serial interface configuration ............................................................................................ 125 5.6.3 register functions ............................................................................................................... 129 5.6.4 operation-halted mode ....................................................................................................... 138 5.6.5 3-wire serial i/o mode operation ....................................................................................... 140 5.6.6 2-wire serial i/o mode operation ....................................................................................... 150 5.6.7 sbi mode operation ............................................................................................................ 156 5.6.8 sck pin output manipulation ............................................................................................ 188 5.7 lcd controller/driver .................................................................................................... 189 5.7.1 lcd controller/driver configuration ................................................................................. 189 5.7.2 lcd controller/driver function .......................................................................................... 191 5.7.3 display mode register ........................................................................................................ 192 5.7.4 display control register ...................................................................................................... 194 5.7.5 display data memory .......................................................................................................... 195 5.7.6 common signals and segment signals ........................................................................... 197 5.7.7 lcd drive power v lc0 , v lc1 , v lc2 supply .......................................................................... 201 5.7.8 display modes ..................................................................................................................... 204 5.8 bit sequential buffer ..................................................................................................... 217 chapter 6 interrupt function ............................................................................................... 219 6.1 interrupt control circuit configurations .................................................................... 219 6.2 interrupt source t ypes and vector table ................................................................... 221 6.3 various hard ware t ypes of interrupt control circuit ............................................... 224 6.4 interrupt sequence ........................................................................................................ 233 6.5 multiinterrupt servicing control .................................................................................. 234 6.6 vector address sharing interrupt servicing .............................................................. 235 6.7 machine cycles until interrupt servicing ................................................................... 237 6.8 effective methods of using interrupts ........................................................................ 239 6.9 application of interrupts ............................................................................................... 240 chapter 7 standby function ................................................................................................... 245 7.1 standby mode setting and operation status ............................................................. 247 7.2 cancellation of standby mode ..................................................................................... 248 7.3 operation after standby mode cancellation .............................................................. 250 7.4 standby mode application ............................................................................................ 250 chapter 8 reset function ........................................................................................................ 255 chapter 9 prom writing and verification ......................................................................... 257 9.1 operating mode when writing in and verifying prom ............................................. 258 9.2 prom write procedure ................................................................................................. 259
C iv C 9.3 prom read procedure .................................................................................................. 260 9.4 erasure ............................................................................................................................ 261 chapter 10 instruction set ..................................................................................................... 263 10.1 characteristic instructions ........................................................................................... 263 10.1.1 geti instruction .................................................................................................................. 263 10.1.2 bit manipulation instruction .............................................................................................. 264 10.1.3 accumulation instruction .................................................................................................. 264 10.1.4 notation adjust instruction ................................................................................................ 265 10.1.5 skip instruction and the number of machine cycles required for skipping .............. 265 10.2 instruction set and its operation ................................................................................ 266 10.3 instruction code of each instruction .......................................................................... 276 10.4 instruction function and application .......................................................................... 281 10.4.1 transfer instruction .......................................................................................................... 281 10.4.2 table reference instruction ............................................................................................. 286 10.4.3 arithmetic operation instruction .................................................................................... 289 10.4.4 accumulator manipulation instruction .......................................................................... 292 10.4.5 increment/decrement instruction ................................................................................... 293 10.4.6 comparison instruction ................................................................................................... 294 10.4.7 carry flag manipulation instruction ............................................................................... 295 10.4.8 memory bit manipulation instruction ............................................................................. 296 10.4.9 branch instruction ............................................................................................................ 299 10.4.10 subroutine stack control instruction ............................................................................. 301 10.4.11 interrupt control instruction ............................................................................................ 306 10.4.12 input/output instruction ................................................................................................... 307 10.4.13 cpu control instruction ................................................................................................... 309 10.4.14 special instruction ............................................................................................................ 310 appendix a development tools ............................................................................................. 313 appendix b mask rom ordering procedure ..................................................................... 317 appendix c instruction index ................................................................................................. 319 c.1 instruction index (in function) ...................................................................................... 319 c.2 instruction index (in general) ....................................................................................... 321 appendix d hardware index ..................................................................................................... 323 appendix e revision history .................................................................................................... 325
C v C list of figures figure no. title page 3-1 selection of mbe = 0 mode and mbe = 1 mode .............................................................................. 36 3-2 data memory configuration and addressing range in each addressing mode ............................. 38 3-3 addressing mode ................................................................................................................................ 39 3-4 static ram address updating procedure .......................................................................................... 42 3-5 m pd75308 i/o map ............................................................................................................................. 50 4-1 program counter configuration ......................................................................................................... 53 4-2 program memory map ( m pd75304, 75304b) .................................................................................... 55 4-3 program memory map ( m pd75306, 75306b) .................................................................................... 56 4-4 program memory map ( m pd75308, 75308b, 75p308) ..................................................................... 57 4-5 program memory map ( m pd75312, 75312b) .................................................................................... 58 4-6 program memory map ( m pd75316, 75316b, 75p316, 75p316a, 75p316b) ................................... 59 4-7 data memory map ............................................................................................................................... 62 4-8 display data memory configuration .................................................................................................. 64 4-9 general register configuration (for 4-bit processing) .................................................................... 65 4-10 general register configuration (for 8-bit processing) .................................................................... 65 4-11 register pair configuration ................................................................................................................ 65 4-12 accumulator ......................................................................................................................................... 66 4-13 stack pointer format .......................................................................................................................... 66 4-14 data saved/restored by stack operation ( m pd75304, 75304b) ..................................................... 67 4-15 data saved/restored by stack operation ( m pd75306, 75306b, 75308, 75308b, 75p308) ........... 68 4-16 data saved/restored by stack operation ( m pd75312, 75312b, 75316, 75316b, 75p316, 75p316a and 75p316b) ....................................... 69 4-17 program status word format ............................................................................................................. 70 4-18 bank select register format ............................................................................................................. 73 5-1 digital port data memory address ..................................................................................................... 75 5-2 configuration of ports 0 and 1 ........................................................................................................... 78 5-3 configuration of ports 3n and 6n (n = 0 to 3) .................................................................................... 79 5-4 configuration of ports 2 and 7 ........................................................................................................... 79 5-5 configuration of ports 4 and 5 ........................................................................................................... 80 5-6 port mode register format ................................................................................................................ 81 5-7 pull-up resistor specification register group a .............................................................................. 87 5-8 input/output timing of digital input/output port ............................................................................... 88 5-9 pull-up resistor on timing by software ........................................................................................... 89 5-10 clock generator circuit block diagram ............................................................................................. 90 5-11 processor clock control register format ......................................................................................... 93 5-12 system clock control register format .............................................................................................. 94 5-13 externally mounted circuit for the main system clock oscillator circuit ........................................ 95 5-14 externally mounted circuit for subsystem clock oscillator circuit .................................................. 95 5-15 example of incorrect resonator connection circuit ......................................................................... 96 5-16 system clock/cpu clock switching ................................................................................................ 100 5-17 clock output circuit configuration ................................................................................................... 101
C vi C figure no. title page 5-18 clock output mode register format ............................................................................................... 102 5-19 remote controlled output application example ............................................................................. 103 5-20 basic interval timer configuration ................................................................................................... 104 5-21 basic interval timer mode register format .................................................................................... 105 5-22 w atch timer block diagram ............................................................................................................. 109 5-23 watch mode register format ........................................................................................................... 110 5-24 timer/event counter block diagram ................................................................................................ 112 5-25 count oper ation timing .................................................................................................................... 113 5-26 timer/event counter mode register format ................................................................................... 115 5-27 timer/event counter output enable flag format ........................................................................... 116 5-28 count operating mode operation .................................................................................................... 117 5-29 timer start error ............................................................................................................................... 119 5-30 example of sbi system configuration ............................................................................................. 125 5-31 serial interface block diagram ......................................................................................................... 126 5-32 serial operating mode register (csim) format ............................................................................. 129 5-33 serial bus interface control register (sbic) format ..................................................................... 133 5-34 configuration around shift register ................................................................................................. 136 5-35 example of 3-wire serial i/o system configuration ....................................................................... 140 5-36 3-wire serial i/o mode timing ......................................................................................................... 143 5-37 relt and cmdt operations ............................................................................................................ 144 5-38 3-wire i/o mode configuration ......................................................................................................... 145 5-39 example of 2-wire serial i/o system configuration ....................................................................... 150 5-40 2-wire serial i/o mode timing ......................................................................................................... 153 5-41 relt and cmdt operations ............................................................................................................ 154 5-42 example of sbi serial bus configuration ........................................................................................ 156 5-43 sbi tr ansfer timing .......................................................................................................................... 158 5-44 bus release signal ........................................................................................................................... 159 5-45 command signal ............................................................................................................................... 159 5-46 address .............................................................................................................................................. 160 5-47 slave selection by address .............................................................................................................. 160 5-48 command .......................................................................................................................................... 161 5-49 data ................................................................................................................................................... 161 5-50 acknowledge signal .......................................................................................................................... 162 5-51 busy signal and ready signal ......................................................................................................... 163 5-52 relt, cmdt, reld, and cmdd operation (master) ..................................................................... 168 5-53 relt, cmdt, reld, and cmdd operation (slave) ....................................................................... 169 5-54 ackt operation ................................................................................................................................ 169 5-55 acke operation ................................................................................................................................ 170 5-56 ackd operation ................................................................................................................................ 171 5-57 bsye operation ................................................................................................................................ 171 5-58 pin configuration diagram ............................................................................................................... 174 5-59 address transmission from master device to slave device (wup = 1) ....................................... 176 5-60 command transmission from master device to slave device ....................................................... 177 5-61 data t ransmission from master device to slave device ................................................................ 178 5-62 data t ransmission from slave device to master device ................................................................ 179
C vii C 5-63 example of serial bus configuration ............................................................................................... 181 5-64 read command transfer format ................................................................................................... 183 5-65 write and end command transfer format ................................................................................. 184 5-66 stop command transfer format .................................................................................................... 184 5-67 sta tus command transfer format ............................................................................................... 185 5-68 status command status format ................................................................................................... 185 5-69 reset command transfer format ................................................................................................. 186 5-70 chgmst command transfer format .............................................................................................. 186 5-71 master and slave operation in case of error generation .............................................................. 187 5-72 sck/p01 pin configuration .............................................................................................................. 188 5-73 lcd controller/driver block diagram .............................................................................................. 190 5-74 display mode register format ......................................................................................................... 192 5-75 display control register format ...................................................................................................... 194 5-76 data memory map ............................................................................................................................. 195 5-77 correspondence between display data memory and common segments ................................... 196 5-78 common signal waveform (static) .................................................................................................. 199 5-79 common signal waveform (1/2 bias modulus) ............................................................................... 199 5-80 common signal waveform (1/3 bias modulus) ............................................................................... 199 5-81 voltage and phase of common signal and segment signal ......................................................... 200 5-82 examples of lcd drive power supply connection (with on-chip division resistor) .................. 202 5-83 examples of lcd drive power supply connection (with external division resistor) .................. 203 5-84 static t ype lcd display pattern and electrode wiring .................................................................. 204 5-85 static lcd panel wiring example .................................................................................................... 205 5-86 example of static lcd drive waveforms ........................................................................................ 206 5-87 2-time-division type lcd display pattern and electrode wiring .................................................. 207 5-88 2-time-division lcd p anel wir ing example ................................................................................... 208 5-89 example of 2-time-division lcd drive waveforms (1/2 bias modulus) ........................................ 209 5-90 3-time-division type lcd display pattern and electrode wiring .................................................. 210 5-91 3-time-division lcd p anel wir ing example ................................................................................... 211 5-92 example of 3-time-division lcd drive waveforms (1/2 bias modulus) ........................................ 212 5-93 example of 3-time-division lcd drive waveforms (1/3 bias modulus) ........................................ 213 5-94 4-time-division type lcd display pattern and electrode wiring .................................................. 214 5-95 4-time-division lcd p anel wir ing example ................................................................................... 215 5-96 example of 4-time-division lcd drive waveforms (1/3 bias modulus) ........................................ 216 5-97 bit sequential buffer format ............................................................................................................ 217 6-1 interrupt control circuit block diagram ........................................................................................... 220 6-2 interr upt v ector table ........................................................................................................................ 221 6-3 ime format ........................................................................................................................................ 225 6-4 configuration of int0, int1 and int4 ............................................................................................. 227 6-5 input/output timing of noise eliminator .......................................................................................... 228 6-6 format of edge detection mode registers ..................................................................................... 229 6-7 int2, kr0 to kr7 configurations .................................................................................................... 231 6-8 interrupt servicing procedure ........................................................................................................... 233 6-9 multiinterrupt by interrupt status flag change ................................................................................ 234 figure no. title page
C viii C figure no. title page 7-1 standby mode cancellation operation ............................................................................................ 248 8-1 reset operation by reset input .................................................................................................... 255 10-1 data flow by instruction execution .................................................................................................. 286
C ix C list of t ables table no. title page 1-1 features of 75x series products ......................................................................................................... 1 2-1 list of digital input/output port pin functions .................................................................................. 15 2-2 list of pin functions except port pins ............................................................................................... 17 2-3 list of digital input/output port pin functions .................................................................................. 19 2-4 list of pin functions except port pins ............................................................................................... 21 2-5 selection of mask option .................................................................................................................... 31 2-6 treatment of unused pins .................................................................................................................. 32 3-1 addressing modes applicable for peripheral hardware operations ................................................ 48 4-1 psw flag saved/restored by stack operation ................................................................................ 70 4-2 carry flag operation instructions ...................................................................................................... 71 4-3 interrupt status flag instruction content ........................................................................................... 72 5-1 digital port types and features ......................................................................................................... 77 5-2 list of input/output pin manipulation instructions ............................................................................. 84 5-3 input/output port and pin operations ................................................................................................ 86 5-4 specification of pull-up resistor integration ..................................................................................... 87 5-5 maxi mum time required for system clock/cpu clock switching .................................................. 99 5-6 resolution and maximum time set (4.19 mhz) .............................................................................. 118 5-7 serial clock selection and use (in 3-wire serial i/o mode) .......................................................... 144 5-8 serial clock selection and use (in 2-wire serial i/o mode) .......................................................... 154 5-9 serial clock selection and use (in sbi mode) ................................................................................ 168 5-10 signals in sbi mode ......................................................................................................................... 172 5-11 maximum number of display pixels ................................................................................................ 191 5-12 common signals ............................................................................................................................... 197 5-13 lcd drive voltages (static) .............................................................................................................. 198 5-14 lcd drive voltages (1/2 bias modules) .......................................................................................... 198 5-15 lcd drive voltages (1/3 bias modulus) .......................................................................................... 198 5-16 lcd drive power supply values ...................................................................................................... 201 5-17 selection/non-selection voltages for pins s8 to s15 (static display example) ........................... 204 5-18 selection/non-selection voltages for pins s8 to s11 (2-time-division display example) ........... 207 5-19 selection/non-selection voltages for pins s12 to s14 (3-time-division display example) ......... 210 5-20 selection/non-selection voltages for pins s20 and s21 (4-time-division display example) ...... 214 6-1 interrupt source types ...................................................................................................................... 221 6-2 interrupt request flag set signal .................................................................................................... 225 6-3 ist0 and interrupt servicing status ................................................................................................. 232 7-1 each operation status in standby mode ......................................................................................... 247 7-2 wait time selection by btm ............................................................................................................ 249
C x C table no. title page 8-1 each hardware status after resetting ............................................................................................ 255 9-1 pin functions ..................................................................................................................................... 257 9-2 operating mode ................................................................................................................................. 258
1 chapter 1 general description chapter 1 general description the m pd75304, 75304b, 75306, 75306b, 75308, 75308b, 75p308, 75312, 75312b, 75316, 75316b, 75p316, 75p316a and 75p316b are 75x series products. they are 4-bit single-chip microcontrollers having an on-chip programmable lcd controller/driver and an on-chip nec standard serial bus interface, with the features of high- speed and high-performance. the features are described below. ? rom capacity : max. 16256 words x 8 bits ? ram capacity : max. 1024 words x 4 bits ? general register : max. 8 units x 4 bits ? high-speed operation : min. instruction execution time 0.95 m s ? six interrupt sources and efficient interrupt servicing ? efficient instruction system capable of operating 1/4/8-bit data ? versatile timer functions : 3 channels ? ultra low power clock operations in the standby mode (with an on-chip subsystem clock operating at power consumption level) products listed in table 1-1 are available depending on the program memory sizes and types. table 1-1. features of 75x series products product name program memory (rom) remarks m pd75304 4096 words x 8 bits mask rom m pd75304b 4096 words x 8 bits mask rom, low-voltage operation capability m pd75306 6016 words x 8 bits mask rom m pd75306b 6016 words x 8 bits mask rom, low-voltage operation capability m pd75308 8064 words x 8 bits mask rom m pd75308b 8064 words x 8 bits mask rom, low-voltage operation capability m pd75p308 8064 words x 8 bits one-time prom/eprom m pd75312 12160 words x 8 bits mask rom m pd75312b 12160 words x 8 bits mask rom, low-voltage operation capability m pd75316 16256 words x 8 bits mask rom m pd75316b 16256 words x 8 bits mask rom, low-voltage operation capability m pd75p316 16256 words x 8 bits one-time prom m pd75p316a 16256 words x 8 bits one-time prom/eprom m pd75p316b 16256 words x 8 bits one-time prom/eprom, low-voltage operation capability
2 chapter 1 general description the m pd75p308, 75p316a and 75p316b are products having an on-chip, one-time prom or eprom instead of a mask rom. the packages are provided as follows: one-time programmable : m pd75p308gf-3b9 (without a window) m pd75p316agf-3b9 (without a window) m pd75p316bgc-3b9 (without a window) m pd75p316bgk-be9 (without a window) reprogrammable : m pd75p308k (with a window) m pd75p316ak (with a window) m pd75p316bkk-t (with a window) the m pd75p316 is a product having an on-chip, one-time prom instead of a mask rom. the package is provided as follows: one-time programmable : m pd75p316gf-3b9 (without a window) applications ? electric home appliances vcr, audio equipment (such as cd players), etc. ? others telephones, cameras, sphygmomanometers, etc.
3 chapter 1 general description 1.1 function outline function outline (1/2) item function basic instructions 41 instruction cycle 0.95 m s, 1.91 m s, 15.3 m s (operating on 4.19 mhz main system clock), 122 m s (operating on 32.768 khz subsystem clock) on-chip rom ? m pd75304, 75304b : 4096 words 8 bits (rom) memory ? m pd75306, 75306b : 6016 words 8 bits (rom) ? m pd75308, 75308b : 8064 words 8 bits (rom) ? m pd75p308 : 8064 words 8 bits (prom) ? m pd75312, 75312b : 12160 words 8 bits (rom) ? m pd75316, 75316b : 16256 words 8 bits (rom) ? m pd75p316, 75p316a, 75p316b : 16256 words 8 bits (prom) ram 512 x 4 bits 1024 x 4 bits ( m pd75312b, 75316b, 75p316a, 75p316b only) general registers ? 4-bit manipulation : 8 units (x, a, b, c, d, e, h, l) ? 8-bit manipulation : 4 units (xa, bc, de, hl) accumulators ? bit accumulator (cy) ? 4-bit accumulator (a) ? 8-bit accumulator (xa) instruction set ? many bit manipulation instructions ? efficient 4-bit data operation instructions ? 8-bit data transfer instructions ? geti instruction capable of implementing any 2-byte/3-byte instruction in one byte i/o lines 40 8 cmos input software pull-up capability: 23 16 cmos input/output 8 cmos output dual-purpose as segment pins 8 n-ch open-drain 10 v withstand voltage, mask option pull-up capability note 1: 8 input/output lcd controller/driver ? segment number selection : 24, 28 and 32 segments (4 and 8 segments switchable to bit port output) ? display mode selection : static, 1/2 duty, 1/3 duty (1/2 bias), 1/3 duty (1/3 bias), 1/4 duty ? lcd drive division resistor incorporation capability by mask option supply voltage range v dd = 2.0 to 6.0 v : m pd75304b, 75306b, 75308b, 75312b, 75316b, 75p316b v dd = 2.7 to 6.0 v : m pd75304, 75306, 75308, 75312, 75316, 75p316a v dd = 5 v 5 % : m pd75p308, 75p316 note pull-up resistors by mask option are not provided for m pd75p308, 75p316, 75p316a, and 75p316b.
4 chapter 1 general description function outline (2/2) item function timer 3-channel 8-bit timer/event counter ? clock sources : 4 levels ? event count capability 8-bit basic interval timer ? reference time generation : 1.95 ms, 7.82 ms, 31.3 ms, 250 ms (operating at 4.19 mhz) ? watchdog timer application capability watch timer ? 0.5 sec. time interval generation ? count clock source : main system clock/subsystem clock switchable ? clock fast forward mode (3.9 ms time interval generation) ? buzzer output capability (2 khz) 8-bit serial interface applicable to three modes ? 3-wire serial i/o mode ? 2-wire serial i/o mode ? sbi mode ? lsb first/msb first switchable bit sequential buffer special bit manipulation memory: 16 bits ? ideal for remote control applications clock output functions timer/event counter output (pto0): selected frequency square wave output clock output (pcl): f , 524 khz, 262 khz, 65.5 khz (operating at 4.19 mhz) buzzer output (buz): 2 khz (operating at 4.19 mhz or 32.768 khz) vectored interrupts ? external : 3 ? internal : 3 test input ? external : 1 ? internal : 1 system clock ? ceramic/crystal oscillator for main system clock oscillation: 4.19430 mhz oscillation circuits ? crystal oscillator for subsystem clock oscillation: 32.768 khz standby stop/halt modes packages 80-pin plastic qfp (14 x 14 mm) : m pd75304b, 75306b, 75308b, 75312b, 75316b, 75p316b 80-pin plastic qfp (14 x 20 mm) : m pd75304, 75304b, 75306, 75306b, 75308, 75308b, 75p308, 75312, 75316, 75p316, 75p316a 80-pin plastic qfp (12 x 12 mm) : m pd75304b, 75306b, 75308b, 75312b, 75316b, 75p316b 80-pin ceramic wqfn : m pd75p308, 75p316a, 75p316b (lcc with window) note note m pd75p308, 75p316a : 14 x 20 mm m pd75p316b : 14 x 14 mm
5 chapter 1 general description 1.2 ordering information part number package on-chip rom m pd75304gf-xxx-3b9 80-pin plastic qfp (14 x 20 mm) mask rom m pd75304bgc-xxx3b9 80-pin plastic qfp (14 x 14 mm) mask rom m pd75304bgf-xxx-3b9 80-pin plastic qfp (14 x 20 mm) mask rom m pd75304bgk-xxx-be9 80-pin plastic tqfp (fine pitch) (12 x 12 mm) mask rom m pd75306gf-xxx-3b9 80-pin plastic qfp (14 x 20 mm) mask rom m pd75306bgc-xxx-3b9 80-pin plastic qfp (14 x 14 mm) mask rom m pd75306bgf-xxx-3b9 80-pin plastic qfp (14 x 20 mm) mask rom m pd75306bgk-xxx-be9 80-pin plastic tqfp (fine pitch) (12 x 12 mm) mask rom m pd75308gf-xxx-3b9 80-pin plastic qfp (14 x 20 mm) mask rom m pd75308bgc-xxx-3b9 80-pin plastic qfp (14 x 14 mm) mask rom m pd75308bgf-xxx-3b9 80-pin plastic qfp (14 x 20 mm) mask rom m pd75308bgk-xxx-be9 80-pin plastic tqfp (fine pitch) (12 x 12 mm) mask rom m pd75p308gf-8b9 80-pin plastic qfp (14 x 20 mm) one-time prom m pd75p308k 80-pin ceramic wqfn (lcc with window) eprom m pd75312gf-xxx-3b9 80-pin plastic qfp (14 x 20 mm) mask rom m pd75312bgc-xxx-3b9 80-pin plastic qfp (14 x 14 mm) mask rom m pd75312bgk-xxx-be9 80-pin plastic tqfp (fine pitch) (12 x 12 mm) mask rom m pd75316gf-xxx-3b9 80-pin plastic qfp (14 x 20 mm) mask rom m pd75316bgc-xxx-3b9 80-pin plastic qfp (14 x 14 mm) mask rom m pd75316bgk-xxx-be9 80-pin plastic tqfp (fine pitch) (12 x 12 mm) mask rom m pd75p316gf-3b9 80-pin plastic qfp (14 x 20 mm) one-time prom m pd75p316agf-3b9 80-pin plastic qfp (14 x 20 mm) one-time prom m pd75p316ak 80-pin ceramic wqfn (lcc with window) eprom m pd75p316bgc-3b9 80-pin plastic qfp (14 x 14 mm) one-time prom m pd75p316bgk-be9 80-pin plastic tqfp (fine pitch) (12 x 12 mm) one-time prom m pd75p316bkk-t 80-pin ceramic wqfn (lcc with window) eprom remark xxx indicates the rom code number.
6 chapter 1 general description 1.3 list of functions of series products (1) m m m m m pd75304, 75306, 75308, 75p308 product m pd75304 m pd75306 m pd75308 m pd75p308 item program memory ? mask rom ? mask rom ? mask rom ? eprom/one-time prom ? 000h to fffh ? 0000h to 177fh ? 0000h to 1f7fh ? 0000h to 1f7fh ? 4096 bytes ? 6016 bytes ? 8064 bytes ? 8064 bytes data memory 512 x 4 bits (banks 0 and 1: 256 x 4 bits) instruction 3-byte set branch not provided provided instructions others commonly provided program counter 12 bits 13 bits mask option ? internal pull-up resistor for ports 4 and 5 not provided ? division resistor for lcd drive power supply no. 57 pin function nc v pp supply voltage range 2.7 to 6.0 v 5 v 5 % package 80-pin plastic qfp (14 x 20 mm) ? 80-pin ceramic wqfn (lcc with window) ? 80-pin plastic qfp (14 x 20 mm)
7 chapter 1 general description (2) m m m m m pd75304b, 75306b, 75308b product m pd75304b m pd75306b m pd75308b item program memory ? mask rom ? mask rom ? mask rom ? 0000h to 0fffh ? 0000h to 177fh ? 0000h to 1f7fh ? 4096 bytes ? 6016 bytes ? 8064 bytes data memory 512 x 4 bits (banks 0 and 1: 256 x 4 bits) instruction 3-byte set branch not provided provided instructions others commonly provided program counter 12 bits 13 bits mask option ? internal pull-up resistor for ports 4 and 5 ? division resistor for lcd drive power supply no. 57 pin function nc supply voltage range 2.0 to 6.0 v package ? 80-pin plastic qfp (14 x 14 mm) ? 80-pin plastic qfp (14 x 20 mm) ? 80-pin plastic tqfp (12 x 12 mm)
8 chapter 1 general description (3) m m m m m pd75312, 75316, 75p316, 75p316a product m pd75312 m pd75316 m pd75p316 m pd75p316a item program memory ? mask rom ? mask rom ? one-time prom ? eprom/one-time prom ? 0000h to 2f7fh ? 0000h to 3f7fh ? 0000h to 3f7fh ? 0000h to 3f7fh ? 12160 bytes ? 16256 bytes ? 16256 bytes ? 16256 bytes data memory 512 x 4 bits 1024 x 4 bits (banks 0 and 1: 256 x 4 bits) (bank 0, 1, 2, 3: 256 x 4 bits) instruction 3-byte set branch provided instructions others commonly provided program counter 14 bits mask option ? internal pull-up resistor for ports 4 and 5 not provided ? division resistor for lcd drive power supply no. 57 pin function nc v pp supply voltage range 2.7 to 6.0 v 5 v 5 % 2.7 to 6.0 v package 80-pin plastic qfp (14 x 20 mm) ? 80-pin ceramic wqfn (lcc with window) ? 80-pin plastic qfp (14 x 20 mm)
9 chapter 1 general description (4) m m m m m pd75312b, 75316b, 75p316b product m pd75312b m pd75316b m pd75p316b item program memory ? mask rom ? mask rom ? one-time prom ? 0000h to 2f7fh ? 0000h to 3f7fh ? 0000h to 3f7fh ? 12160 bytes ? 16256 bytes ? 16256 bytes data memory 1024 x 4 bits (banks 0, 1, 2, 3: 256 x 4 bits) instruction 3-byte set branch provided instructions others commonly provided program counter 14 bits mask option ? internal pull-up resistor for ports 4 and 5 not provided ? division resistor for lcd drive power supply no. 57 pin function ic v pp supply voltage range 2.0 to 6.0 v package ? 80-pin plastic qfp (14 x 14 mm) ? 80-pin plastic qfp ? 80-pin plastic tqfp (12 x 12 mm) (14 x 14 mm) ? 80-pin plastic tqfp (12 x 12 mm) ? 80-pin ceramic wqfn (lcc with window)
10 chapter 1 general description 1.4 block diagram notes 1. bit length depends on the type. 2. md0 to md3 and v pp are used for prom version. cy basic interval timer intbt timer/event counter #0 intt0 watch timer intw clocked serial interface intcsi interrupt control ti0/p13 buz/p23 so/sb0/p02 si/sb1/p03 sck/p01 int1/p11 int0/p10 int2/p12 int4/p00 program note1 counter program memory (rom/prom) (memory size depends on the type) decode and control clock output control pcl/p22 clock divider fx/2 n sub main system clock generator xt1 xt2 x1 x2 stand by control data memory (ram) (memory size depends on the type) general reg. bank sp (8) reset v ss cpu clock alu port 2 4 p20-p23 port 3 4 p30-p33/ md0-md3 note2 port 4 4 p40-p43 port 5 4 p50-p53 port 6 4 p60-p63 port 0 4 p00-p03 port 1 4 p10-p13 24 s0-s23 8 s24/bp0 -s31/bp7 3 v lc0 -v lc2 lcd controller /driver sync/p31 f lcd bit seq. buffer (16) kr0/p60 -kr7/p73 pto0/p20 port 7 4 p70-p73 4 com0-com3 lcdcl/p30 bias f lcd v dd v pp note2
11 chapter 1 general description 1.5 pin configuration (top view) (1) normal operating mode (a) 80-pin plastic qfp (14 x 14 mm) 80-pin plastic tqfp (12 x 12 mm) note the ic pin is used for m pd75312b and 75316b. ic pin: internally connected. connect this pin with v dd directly. pd75304bgc - xxx - 3b9 pd75304bgk - xxx - be9 pd75306bgc - xxx - 3b9 pd75306bgk - xxx - be9 pd75308bgc - xxx - 3b9 pd75308bgk - xxx - be9 pd75312bgc - xxx - 3b9 pd75312bgk - xxx - be9 pd75316bgc - xxx - 3b9 pd75316bgk - xxx - be9 m 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 m m m m m m m 21 22 23 24 25 26 27 28 29 30 31 32 33 34 36 35 37 38 39 40 com0 com1 com2 com3 bias v lc0 v lc1 v lc2 p40 p41 p42 p43 v ss p50 p51 p52 p53 p00/int4 p01/sck p02/so/sb0 s12 s13 s14 s15 s16 s17 s18 s19 s20 s21 s22 s23 s24/bp0 s25/bp1 s26/bp2 s27/bp3 s28/bp4 s29/bp5 s30/bp6 s31/bp7 80 79 78 77 76 75 74 73 72 71 70 69 68 67 65 66 64 63 62 61 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 reset p73/kr7 p72/kr6 p71/kr5 p70/kr4 p63/kr3 p62/kr2 p61/kr1 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 p60/kr0 x2 x1 nc (ic) note xt2 xt1 v dd p33 p32 p31/sync p30/lcdcl p23/buz p22/pcl p21 p20/pto0 p13/ti0 p12/int2 p11/int1 p10/int0 p03/si/sb1 m m
12 chapter 1 general description (b) 80-pin plastic qfp (14 x 20 mm) pd75304gf - xxx - 3b9 pd75306gf - xxx - 3b9 pd75308gf - xxx - 3b9 pd75304bgf - xxx - 3b9 pd75306bgf - xxx - 3b9 pd75308bgf - xxx - 3b9 pd75312gf - xxx - 3b9 pd75316gf - xxx - 3b9 m 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 m m m m m m m 25 26 27 28 29 30 31 32 33 34 35 36 37 38 40 39 bias v lc0 v lc1 v lc2 p40 p41 p42 p43 v ss p50 p51 p52 p53 p00/int4 p01/sck p02/so/sb0 s12 s13 s14 s15 s16 s17 s18 s19 s20 s21 s22 s23 s24/bp0 s25/bp1 s26/bp2 s27/bp3 s28/bp4 s29/bp5 s30/bp6 s31/bp7 com0 com1 com2 com3 80 79 78 77 76 75 74 73 72 71 70 69 68 67 65 66 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 reset p73/kr7 p72/kr6 p71/kr5 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 p70/kr4 p63/kr3 p62/kr2 p61/kr1 p60/kr0 x2 x1 nc xt2 xt1 v dd p33 p32 p31/sync p30/lcdcl p23/buz p22/pcl p21 p20/pto0 p13/ti0 p12/int2 p11/int1 p10/int0 p03/si/sb1 p00-03 : port0 p10-13 : port1 p20-23 : port2 p30-33 : port3 p40-43 : port4 p50-53 : port5 p60-63 : port6 p70-73 : port7 bp0-7 : bit port kr0-7 : key return sck : serial clock si : serial input so : serial output sb0, 1 : serial bus 0,1 reset : reset input s0-31 : segment output 0-31 com0-3 : common output 0-3 v lc0-2 : lcd power supply 0-2 bias : lcd power supply bias control lcdcl : lcd clock sync : lcd synchronization ti0 : timer input 0 pto0 : programmable timer output 0 buz : buzzer clock pcl : programmable clock int0, 1, 4 : exter nal v ectored interrupt 0, 1, 4 int2 : exter nal t est input 2 x1, 2 : main system clock oscillation 1, 2 xt1, 2 : subsystem clock oscillation 1, 2 nc : no connection
13 chapter 1 general description (2) prom mode (a) 80-pin plastic qfp (14 x 14 mm) 80-pin plastic tqfp (12 x 12 mm) 80-pin ceramic wqfn (lcc with window) pd75p316bgc - 3b9 pd75p316bgk - be9 pd75p316bkk - t m 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20? m m 21 22 23 24 25 26 27 28 29 30 31 32 33 34 36 35 37 38 39 40 com0 com1 com2 com3 bias v lc0 v lc1 v lc2 p40 p41 p42 p43 v ss p50 p51 p52 p53 p00/int4 p01/sck p02/so/sb0 s12 s13 s14 s15 s16 s17 s18 s19 s20 s21 s22 s23 s24/bp0 s25/bp1 s26/bp2 s27/bp3 s28/bp4 s29/bp5 s30/bp6 s31/bp7 80 79 78 77 76 75 74 73 72 71 70 69 68 67 65 66 64 63 62 61 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 reset p73/kr7 p72/kr6 p71/kr5 p70/kr4 p63/kr3 p62/kr2 p61/kr1 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 p60/kr0 x2 x1 v pp xt2 xt1 v dd p33/md3 p32/md2 p31/sync/md1 p30/lcdcl/md0 p23/buz p22/pcl p21 p20/pto0 p13/ti0 p12/int2 p11/int1 p10/int0 p03/si/sb1
14 chapter 1 general description (b) 80-pin plastic qfp (14 x 20 mm) 80-pin ceramic wqfn (lcc with window) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24? pd75p308gf - 3b9 pd75p308k pd75p316gf - 3b9 pd75p316agf - 3b9 pd75p316ak m m m m 25 26 27 28 29 30 31 32 33 34 35 36 37 38 40 39 bias v lc0 v lc1 v lc2 p40 p41 p42 p43 v ss p50 p51 p52 p53 p00/int4 p01/sck p02/so/sb0 s12 s13 s14 s15 s16 s17 s18 s19 s20 s21 s22 s23 s24/bp0 s25/bp1 s26/bp2 s27/bp3 s28/bp4 s29/bp5 s30/bp6 s31/bp7 com0 com1 com2 com3 80 79 78 77 76 75 74 73 72 71 70 69 68 67 65 66 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 reset p73/kr7 p72/kr6 p71/kr5 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 p70/kr4 p63/kr3 p62/kr2 p61/kr1 p60/kr0 x2 x1 v pp xt2 xt1 v dd p33/md3 p32/md2 p31/sync/md1 p30/lcdcl/md0 p23/buz p22/pcl p21 p20/pto0 p13/ti0 p12/int2 p11/int1 p10/int0 p03/si/sb1 m p00-03 : port0 p10-13 : port1 p20-23 : port2 p30-33 : port3 p40-43 : port4 p50-53 : port5 p60-63 : port6 p70-73 : port7 bp0-7 : bit port kr0-7 : key return sck : serial clock si : serial input so : serial output sb0, 1 : serial bus 0, 1 reset : reset input md0-3 : mode 0-3 s0-31 : segment output 0-31 com0-3 : common output 0-3 v lc0-2 : lcd power supply 0-2 bias : lcd power supply bias control lcdcl : lcd clock sync : lcd synchronization ti0 : timer input 0 pto0 : programmable timer output 0 bus : buzzer clock pcl : programmable clock int0, 1, 4 : exter nal v ectored interrupt 0, 1, 4 int2 : exter nal t est input 2 x1, 2 : main system clock oscillation 1, 2 xt1, 2 : subsystem clock oscillation 1, 2 v pp : programming power supply
15 chapter 2 pin functions chapter 2 pin functions 2.1 list of pin functions 2.1.1 normal operating mode table 2-1. list of digital input/output port pin functions (1/2) pin name input/ dual- function 8-bit when reset input/output output purpose pin i/o circuit type note 1 p00 input int4 4-bit input port (port 0). x input b p01 i/o sck p01 to p03 enables to specify incorporation of f C a p02 i/o so/sb0 pull-up resistors by software in 3-bit units. f C b p03 i/o si/sb1 m C c p10 input int0 with noise elimination function x input b C c p11 int1 4-bit input port (port 1). p12 int2 this port enables to specify incorporation of p13 ti0 pull-up resistors by software in 4-bit units. p20 i/o pto0 4-bit input/output port (port 2). x input e C b p21 C this port enables to specify incorporation of p22 pcl pull-up resistors by software in 4-bit units. p23 buz p30 note 2 i/o lcdcl programmable 4-bit input/output port (port 3). x input e C b p31 note 2 sync bitwise input/output set enabled. p32 note 2 C this port enables to specify incorporation of p33 note 2 C pull-up resistors software in 4-bit units. p40-p43 note 2 i/o C n-ch open drain 4-bit input/output port (port 4). high level m bitwise pull-up resistor incorporate enabled (when pull-up (mask option). resistors are 10 v withstand in open-drain mode incorporated) or high-impedance p50-p53 note 2 i/o C n-ch open drain 4-bit input/output port (port 5). high level m bitwise pull-up resistor incorporate enabled (when pull-up (mask option). resistors are 10 v withstand in open-drain mode incorporated) or high-impedance p60 i/o kr0 programmable 4-bit input/output port (port 6). input f C a p61 kr1 bitwise input/output set enabled. p62 kr2 this port enables to specify incorporation of p63 kr3 pull-up resistors by software in 4-bit units. notes 1. circles indicate schmitt trigger inputs. 2. direct led drive enabled
16 chapter 2 pin functions table 2-1. list of digital input/output port pin functions (2/2) pin name input/ dual- function 8-bit when reset input/output output purpose pin i/o circuit type note 1 p70 i/o kr4 4-bit input/output port (port 7). input f C a p71 kr5 this port enables to specify incorporation of p72 kr6 pull-up resistors by software in 4-bit units. p73 kr7 bp0 output s24 1-bit output port (bit port). x note 2 g C c bp1 s25 also serves as the segment output pin. bp2 s26 bp3 s27 bp4 output s28 bp5 s29 bp6 s30 bp7 s31 notes 1. circles indicate schmitt trigger inputs. 2. bp0 to bp7 select v lc1 as the input source. the output level varies depending on the external circuit of bp0 to bp7 and v lc1 . example since bp0 to bp7 are interconnected through the m pd75308 as shown below, the output level of bp0 to bp7 is determined by the values of r 1 to r 3 . on on bp0 bp1 v lc1 r 1 r 3 r 2 v dd pd75308 m
17 chapter 2 pin functions table 2-2. list of pin functions except port pins pin name input/ dual- function when reset input/output output purpose pin circuit type note 1 ti0 input p13 external event pulse input pin for the timer/event input b C c counter pto0 i/o p20 timer/event counter output pin input e C b pcl i/o p22 clock output pin input e C b buz i/o p23 fixed frequency output pin (for the buzzer or system input e C b clock trimming) sck i/o p01 serial clock input/output pin input f C a so/sb0 i/o p02 serial data output pin input f C b serial bus input/output pin si/sb1 i/o p03 serial data input pin input m C c serial bus input/output pin int4 input p00 edge detect vectored interrupt input pin (valid for both input b rising and falling edge detect) int0 input p10 edge detect vectored interrupt input clock synchronous input b C c int1 p11 pin (detect edge select enabled) asynchronous int2 input p12 edge detect testable input pin asynchronous input b C c (rising edge detect) kr0-kr3 i/o p60 to p63 parallel falling edge detect testable input pin input f C a kr4-kr7 i/o p70 to p73 parallel falling edge detect testable input pin input f C a s0-s23 output C segment signal output pin note 2 g C a s24-s31 output bp0 to bp7 segment signal output pin note 2 g C c com0-com3 output C common signal output pin note 2 g C b v lc0 -v lc2 C C lcd drive power pin having on-chip dividing resistors C C (mask option) bias output output pin for cutting the externally mounted dividing note 3 C resistors lcdcl note 4 i/o p30 clock output pin for driving the externally expanded input e C b driver sync note 4 i/o p31 clock output pin for synchronizing the externally input e C b expanded driver x1, x2 input C crystal/ceramic connection pin for main system clock C C oscillation. in the case of an external clock, an input is applied to x1 and the inverse input is applied to x2. xt1 input C crystal connection pin for subsystem clock oscillation. C C in the case of an external clock, an input is applied to xt2 C xt1, and xt2 is opened. xt1 can be used as a 1-bit input (test) pin. reset input C system reset input pin C b nc note 5 C C no connection C C ic note 6 C C internally connected C C connect this pin with v dd directly. v dd C C positive power pin C C v ss C C ground potential pin C C
18 chapter 2 pin functions notes 1. circles indicate schmitt trigger inputs. 2. the following v lcx is selected as the input source for each display output. s0 to s31 : v lc1 com0 to com2 : v lc2 com3 : v lc0 each display output level varies depending on the output value and the v lcx external circuit type. example since bp0 to bp7 are interconnected through the m pd75308 as shown below, the output level of bp0 to bp7 is determined by the values of r 1 to r 3 . on on bp0 bp1 v lc1 r 1 r 3 r 2 v dd pd75308 m 3. when a dividing resistor is incorporated ... low level when a dividing resistor is not incorporated ... high impedance 4. pins reserved for future system expansion. it is currently used only as p30 and p31 pins. 5. when the printed board is shared with the m pd75p308, 75p316, 75p316a and 75p316b, connect nc pin to v dd (during emulation). 6. when m pd75312b or 75316b is used.
19 chapter 2 pin functions 2.1.2 prom mode table 2-3. list of digital input/output port pin functions pin name input/ dual- function 8-bit when reset input/output output purpose pin i/o circuit type note 1 p00 input int4 4-bit input port (port 0). x input b p01 i/o sck p01 to p03 enables to specify incorporation of f C a p02 i/o so/sb0 pull-up resistors by software in 3-bit units. f C b p03 i/o si/sb1 m C c p10 input int0 with noise elimination function x input b C c p11 int1 4-bit input port (port 1). p12 int2 this port enables to specify incorporation of p13 ti0 pull-up resistors by software in 4-bit units. p20 i/o pto0 4-bit input/output port (port 2). x input e C b p21 C this port enables to specify incorporation of p22 pcl pull-up resistors by software in 4-bit units. p23 buz p30 note 2 i/o lcdcl md0 programmable 4-bit input/output port (port 3). x input e C b p31 note 2 sync md1 bitwise input/output set enabled. this port p32 note 2 md2 enables to specify incorporation of pull-up p33 note 2 md3 resistors by software in 4-bit units. p40 to p43 note 2 i/o C n-ch open-drain 4-bit input/output port (port 4). high m C a data input/output pin (low-order 4 bits) for impedance program memory (eprom) write/verify. p50 to p53 note 2 i/o C n-ch open-drain 4-bit input/output port (port 5). high m C a data input/output pin (high-order 4 bits) for impedance program memory (eprom) write/verify. p60 i/o kr0 programmable 4-bit input/output port (port 6). input f C a p61 kr1 bitwise input/output set enabled. this port p62 kr2 enables to specify incorporation of pull-up p63 kr3 resistors by software in 4-bit units. p70 i/o kr4 4-bit input/output port (port 7). input f C a p71 kr5 this port enables to specify incorporation of p72 kr6 pull-up resistors by software in 4-bit units. p73 kr7 bp0 output s24 1-bit output port (bit port). x note 3 g C c bp1 s25 also serves as the segment output pin. bp2 s26 bp3 s27 bp4 output s28 bp5 s29 bp6 s30 bp7 s31
20 chapter 2 pin functions notes 1. circles indicate schmitt trigger inputs. 2. direct led drive enabled 3. bp0 to bp7 select v lc1 as the input source. the output level varies depending on the external circuit of bp0 to bp7 and v lc1 . example since bp0 to bp7 are interconnected through the m pd75308 as shown below, the output level of bp0 to bp7 is determined by the values of r 1 to r 3 . on on bp0 bp1 v lc1 r 1 r 3 r 2 v dd pd75308 m
21 chapter 2 pin functions table 2-4. list of pin functions except port pins pin name input/ dual- function when reset input/output output purpose pin circuit type note 1 ti0 input p13 external event pulse input pin for the timer/event C b C c counter pto0 i/o p20 timer/event counter output pin input e C b pcl i/o p22 clock output pin input e C b buz i/o p23 fixed frequency output pin (for the buzzer or system input e C b clock trimming) sck i/o p01 serial clock input/output pin input f C a so/sb0 i/o p02 serial data output pin input f C b serial bus input/output pin si/sb1 i/o p03 serial data input pin input m C c serial bus input/output pin int4 input p00 edge detect vectored interrupt input pin (valid for both C b rising and falling edge detect) int0 input p10 edge detect vectored interrupt input clock synchronous Cb C c int1 p11 pin (detect edge select enabled) asynchronous int2 input p12 edge detect testable input pin asynchronous C b C c (rising edge detect) kr0-kr3 i/o p60 to p63 testable input/output pin (parallel falling edge detect) input f C a kr4-kr7 i/o p70 to p73 testable input/output pin (parallel falling edge detect) input f C a s0-s23 output C segment signal output pin note 2 g C a s24-s31 output bp0 to bp7 segment signal output pin note 2 g C c com0-com3 output C common signal output pin note 2 g C b v lc0 -v lc2 C C lcd drive power pin C C bias C C output pin for cutting the externally mounted dividing note 3 C resistors lcdcl note 4 i/o p30 clock output pin for driving the externally expanded driver input e C b sync note 4 i/o p31 clock output pin for synchronizing the externally input e C b expanded driver x1, x2 input C crystal/ceramic connection pin for main system clock C C oscillation. in the case of an external clock, an input is applied to x1 and the inverse input is applied to x2. xt1 input C crystal connection pin for subsystem clock oscillation. C C in the case of an external clock, an input is applied to xt2 C xt1, and xt2 is opened. xt1 can be used as a 1-bit input (test) pin. reset input C system reset input pin (low level active) C b md0-md3 i/o p30 to p33 program memory (prom) write/verify mode select pin input e C b v pp C C program memory (prom) write/verify program voltage C C apply pin. connect to v dd for normal operations. apply a voltage of +12.5 v for prom write/verify. v dd C C positive power pin C C v ss C C ground potential pin C C
22 chapter 2 pin functions notes 1. circles indicate schmitt trigger inputs. 2. the following v lcx is selected as the input source for each display output. s0 to s31 : v lc1 com0 to com2 : v lc2 com3 : v lc0 each display output level varies depending on the output value and the v lcx external circuit type. example since bp0 to bp7 are interconnected through the m pd75308 as shown below, the output level of bp0 to bp7 is determined by the values of r 1 to r 3 . on on bp0 bp1 v lc1 r 1 r 3 r 2 v dd pd75308 m 3. when a dividing resistor is incorporated ... low level when a dividing resistor is not incorporated ... high impedance 4. pins reserved for future system expansion. it is currently used only as p30 and p31 pins.
23 chapter 2 pin functions 2.2 description of pin functions 2.2.1 p00 to p03 (port 0): int4, sck, so/sb0, si/sb1 multi-purpose inputs p10 to p13 (port 1): int0 to int2, t10 multi-purpose inputs 4-bit input port: input pins of ports 0 and 1 ports 0 and 1 have the following functions in addition to the input port function. (1) port 0 : vectored interrupt input (int4) serial interface input/output (sck, so/sb0, si/sb1) (2) port 1 : vectored interrupt input (int0, int1) edge detect test input (int2) external event pulse input to timer/event counter (ti0) the pins of ports 0 and 1 always serve for inputs irrespectively of the operation of the multi-purpose pins. they are schmitt trigger inputs in order not to malfunction due to noise. p10 is equipped with a noise eliminator (refer to 6.3 (3) int0, int1 and int4 hardware for details). an on-chip pull-up resistor can be specified using the software for port 0 in 3-bit units (p01 to p03) and port 1 in 4-bit units (p10 to p13). this specification can be done by operating pull-up resistor specify register group a. each pin operates as an input port when reset signal is generated.
24 chapter 2 pin functions 2.2.2 p20 to p23 (port 2): pto0, pcl, buz multi-purpose input/output p30 to p33 (port 3): lcdcl, sync, md0 to md3 note multi-purpose input/output p40 to p43 (port 4), p50 to p53 (port 5): n-ch open-drain intermediate withstand voltage (10 v) high-current output p60 to p63 (port 6), p70 to p73 (port 7): 3-state input/output 4-bit input/output port with an output latch: input/output pins of ports 2 to 7 port n (n = 2, 3, 6, 7) has the following functions in addition to the input/output port function. (1) port 2 : timer/event counter output (pto0) clock output (pcl) fixed frequency output (buz) (2) port 3 : clock output for operating the lcd externally expanded driver (lcdcl) clock output for synchronizing the lcd externally expanded driver (sync) (3) ports 6, 7 : key interrupt input (kr0 to kr3, kr4 to kr7) ports generate a high-current output and can directly drives the led. ports 4 and 5 generate a n-ch open drain intermediate withstand voltage (10 v) high-current output and can directly drives the led. input/output mode selection is set using the port mode register. port m (m = 2, 4, 5, 7) enables to set input/ output in 4-bit units. ports 3 and 6 enable to set input/output bitwise. port n enables to specify incorporation of pull-resistors by software in 4-bit units. this specification can be done by operating the pull-up resistor specify register group a (poga). ports 4 and 5 enable to specify incorporation of pull-up resistors bitwise by mask option. ports 4 and 5 and ports 6 and 7 enable in pairs to select input/output in 8-bit units. the output latch of each port is cleared when the reset signal is generated. as a result, port n is set to the input mode (output high impedance) and ports 4 and 5 are set to the high level (when a pull-up resistor is incorporated) or high impedance. note only the m pd75p308, 75p316, 75p316a and 75p316b serve as md0 to md3. 2.2.3 bp0 to bp7: lcd controller/driver segment signal output (s24 to s31) dual-purpose output 1-bit output port with an output latch: output pins of bit ports 0 to 7. they also serve as the lcd controller/driver segment signal output pins. 2.2.4 ti0: port 1 dual-purpose input external event pulse input pin of the programmable timer/event counter. ti0 serves as a schmitt trigger input. 2.2.5 pto0: port 2 dual-purpose output output pin of the programmable timer/event counter. it generates square-wave pulses. to generate the programmable timer/event counter signal, the p20 output latch is cleared (0) and the bit of the port mode register port 2 is set to the output mode (1). the output is cleared (0) by the timer start instruction. 2.2.6 pcl: port 2 dual-purpose output programmable clock output pin. it is used to supply clocks to the peripheral lsi (slave microcontroller, a/d converter, etc.). when the reset signal is generated, the clock mode register (clom) is cleared (0) and the clock is disabled for output with the result that pcl is set to the normal port operating mode.
25 chapter 2 pin functions 2.2.7 buz: port 2 dual-purpose output fixed frequency output pin. it is used to generate buzzer sound or to trim the system clock oscillation frequency by generating the fixed frequency (2.048 khz). it also serves as p23 pin and is only effective when bit 7 (wm7) of the timer mode register (wm) is set (1). when the reset signal is generated, wm7 is cleared (0) and buz is set to the normal port operating mode. 2.2.8 sck, so/sb0, si/sb1: port 0 dual-purpose 3-state input/output input/output pin for the serial interface. it operates in accordance with the setting of the serial operating mode register (csim). when the reset signal is generated, the serial interface stops operating and an input point is set. these ports serve as schmitt trigger inputs. 2.2.9 int4: port 0 dual-purpose input external vectored interrupt input pin with both rising and falling edges set to active. if the signal input to this pin changes from low to high or vice versa, an interrupt request flag is set. int4 is an asynchronous input and is acknowledged, irrespectively of the cpu operation clock, when a signal having the specified high or low-level width is input. int4 can also be used to release the stop mode and halt mode. it is a schmitt trigger input. 2.2.10 int0, int1: port 1 dual-purpose inputs they are edge detect vectored interrupt input pins. int0 has the noise elimination function. they can select the detect edge with the edge detect mode registers (im0, im1). (1) int0 (bits 0, 1 of im0) (a) rising edge active (b) falling edge active (c) both rising and falling edges active (d) external interrupt signal input disable (2) int1 (bit 0 of im1) (a) rising edge active (b) falling edge active int0 has the noise elimination function and can change the noise elimination sampling clock at two levels. the width of a signal to be acknowledged depends on the cpu operation clock. int1 is an asynchronous input and is acknowledged, irrespectively of the cpu operation clock, when the input has the specified high level width. when the reset signal is generated, im0 and im1 are cleared (0) and the rising edge active mode is selected. int1 can also be for stop mode and halt mode release, but int0 cannot. int0 and int1 are schmitt trigger inputs.
26 chapter 2 pin functions 2.2.11 int2: port 1 dual-purpose input external test input pin with both rising and falling edges set to active. if the signal input to this pin changes from low to high when int2 is selected by the edge detect mode register (im2), the internal test flag (irq2) is set. int2 is an asynchronous input and is acknowledged, irrespectively of the cpu operation clock, when the input has the specified high level width. when the reset signal is generated. im2 is cleared (0) and the test flag (irq2) is set by the rising edge input of the int2 pin. int2 can also be for stop mode and halt mode release. it is a schmitt-triggered input. 2.2.12 kr0 to kr3: port 6 dual-purpose input kr4 to kr7: port 7 dual-purpose input key interrupt input pins. kr0 to kr7 are parallel falling edge detect interrupt input pins. an interrupt format can be specified in accordance with the edge detect mode register (im2). when the reset signal is generated, the port 6/port 7 input mode is set. 2.2.13 s0 to s23 s24 to s31: bit ports 0 to 7 dual-purpose outputs segment signal output pins which can directly drive the lcd segment pin (front electrode). they activate the static method, 2 or 3-time sharing of the 1/2 bias method or 3 or 4-time sharing of the 1/3 bias method. s0 to s23 also serve as segment dedicated output pins and s24 to s31 also serve as the output pins of bit ports 0 to 7. they are switched using the display mode register (lcdm). 2.2.14 com0 to com3 common signal output pins which can directly drive the lcd common pin (rear electrode). they generate the common signal when the static method (com0, 1, 2, 3 outputs), 2-time sharing (com0, 1 outputs) or 3-time sharing (com0, 1, 2 outputs) of the 1/2 bias method, 3-time sharing (com0, 1, 2 outputs) or 4-time sharing (com0, 1, 2, 3 outputs) of the 1/3 bias method is activated. 2.2.15 v lc0 to v lc2 lcd drive power supply pin. the m pd75308 can have an on-chip dividing resistor in the v lc0 to v lc2 pins so that an lcd drive power can be supplied in accordance with each bias method without the use of an externally mounted dividing resistor (mask option). 2.2.16 bias output pin for cutting the dividing resistor. connected to the v lc0 pin to cope with various lcd drive voltages, it is used to change the resistance division ratio. along with the v lc0 to v lc2 pins or v ss pin, bias with an externally connected resistor is used to fine adjust the lcd drive power voltage values. 2.2.17 lcdcl clock output pin for driving the lcd externally expanded driver. 2.2.18 sync clock output pin for synchronizing the lcd externally expanded driver.
27 chapter 2 pin functions 2.2.19 x1, x2 crystal/ceramic connection pins for main system clock oscillation. these pins enable to input external clocks. (a) crystal/ceramic oscillation (b) external clock 2.2.20 xt1, xt2 crystal connection pin for subsystem clock oscillation. these pins enable to input external clocks. (a) crystal oscillation (b) external clock pd74hcu04 m externai clock pd75308 m x1 x2 x1 x2 v dd crystal resonator or ceramic resonator pd75308 m (4.194304 mhz typ.) v dd xt1 xt2 v dd crystal resonator (32.768 khz typ.) pd75308 m v dd externai clock pd75308 m xt1 xt2
28 chapter 2 pin functions 2.2.21 reset low level active reset input pin. reset input is an asynchronous input. when a signal having the specified low level width is input irrespectively of the operation clock, the reset signal is generated and system reset is applied before all other operations are carried out. in addition to the normal cpu initialize/start operation, this pin is used to release the standby (stop/halt) mode. reset input is a schmitt trigger input. 2.2.22 v dd positive power supply pin 2.2.23 v ss ground potential 2.2.24 v pp this pin function is only available for the m pd75p308, 75p316, 75p316a and 75p316b. this is a voltage apply pin to write/verify for the prom (program memory). for normal operations, v pp is connected to v dd directly. a voltage of +12.5 v is applied to write/verify for the prom. 2.2.25 md0 to md3: port 3 dual-purpose inputs/outputs these pin functions are only available for the m pd75p308, 75p316, 75p316a and 75p316b. they are used to select the operation mode to write/verify for the prom (program memory). 2.2.26 ic this pin function is only available for the m pd75312b and 75316b. the ic (internally connected) pin is used to set the test mode for testing the m pd75312b/75316b when shipped from nec. in normal operation, the ic pin should be directly connected to v dd , and the wiring should be kept as short as possible. if a potential difference arises between the ic pin and v dd when the routing of the wiring between the ic pin and v dd pin is long, or when external noise is applied to the ic pin, for instance, the customers program may not run correctly. ? connect the ic pin directly to the v dd pin. v dd v dd ic shorted
29 chapter 2 pin functions 2.3 input/output circuits of pins the input/output circuits of m pd75308 pins are shown in simplified form. type b type b-c type f-a type a (for type e-b) type d (for type e-b & f-a) v dd p-ch n-ch in cmos specification input buffer schmitt-triggered input with hysteresis characteristics push-pull output which can be set to output high-impedance (with both p-ch and n-ch set to off) in v dd p-ch n-ch out data output disable data output disable in/out type d type a in p-ch v dd p.u.r. enable p.u.r. type e-b v dd p.u.r. p-ch p.u.r. enable p.u.r. : pull-up resistor data output disable in/out type d type b v dd p.u.r. p-ch p.u.r. enable p.u.r. : pull-up resistor p.u.r. : pull-up resistor
30 chapter 2 pin functions type g-a type g-b type m-a type f-b type g-c v dd p-ch n-ch data output disable in/out type m v dd p.u.r. p-ch p.u.r. enable p.u.r. : pull-up resistor output disable (p) output disable (n) out v lc2 seg data v lc1 v lc0 p-ch n-ch n-ch in/out v dd p.u.r. enable mask option data output disable p.u.r. : pull-up resistor in/out data output disable n-ch p-ch n-ch p-ch n-ch out v lc2 com data v lc1 v lc0 p-ch n-ch n-ch p-ch out v lc2 seg data/bit port data v lc1 v lc0 n-ch p-ch n-ch p-ch v dd middle voltage input buffer (+10 v withstand voltage) middle voltage input buffer (+10 v withstand voltage)
31 chapter 2 pin functions 2.4 selection of mask option the following mask options are available for the pins. no mask options are available for the m pd75p308, 75p316, 75p316a and 75p316b. table 2-5. selection of mask option pin name mask option p40 to p43, p50 to p53 ? pull-up resistor available (specifiable as bit-wise) ? pull-up resistor not available (specifiable as bit-wise) v lc0 to v lc2 , bias ? dividing resistor for lcd drive power supply available (specifiable in 4-bit units) ? dividing resistor for lcd drive power supply not available (specifiable in 4-bit units) type m-c n-ch in/out p.u.r. p-ch data output disable p.u.r. : pull-up resistor v dd p.u.r. enable
32 chapter 2 pin functions 2.5 t reatment of unused pins table 2-6. treatment of unused pins pin recommended connection p00/int4 connect to v ss . p01/sck connect to v ss or v dd . p02/so/sb0 p03/si/sb1 p10/int0-p12/int2 connect to v ss . p13/ti0 p20/pto0 input state : connect to v ss or v dd . p21 output state : leave unconnected. p22/pcl p23/buz p30-p33 p40-p43 p50-p53 p60-p63 p70-p73 s0-s23 leave unconnected. s24/bp0-s31/bp7 com0-com3 v lc0 -v lc2 connect to v ss . bias connect to v ss only when none of v lc0 to v lc2 are used. leave unconnected in all other cases. xt1 connect to v ss or v dd . xt2 leave unconnected. v pp connect to v dd directly. ic
33 chapter 2 pin functions 2.6 caution of use of p00/int4 pin and reset pin this caution does not apply to the m pd75312b, 75316b, 75p316a or 75p316b. in addition to the functions shown in 2.2.9 int4 and 2.2.21 reset , the p00/int4 pin and reset pin have a function for setting the test mode in which the internal operation of the m pd75308 is tested (ic test only). when a potential greater than v dd is applied to either of these pins, the test mode is set. as a result, if noise exceeding v dd is applied during normal operation, the test mode will be entered and normal operation may be impeded. if, for example, the routing of the wiring between the p00/int4 pin and reset pin is long, the above problem may occur as the result of inter-wiring noise between these pins. therefore, wiring should be carried out so as to eliminate inter-wiring noise as far as possible. if it is not possible to eliminate noise, anti-noise measures should be taken using external parts as shown in the figures below. ? connection of diode with small v f ? connection of capacitor between between p00/int4/reset pin and v dd p00/int4/reset pin and v dd v dd v dd p00/int4, reset diode with small v f v dd v dd p00/int4, reset
34 chapter 2 pin functions [memo]
35 chapter 3 features of architecture and memory map chapter 3 features of architecture and memory map in the architecture of the 75x series used for the m pd75308, ? maximum capacity of 4k words x 4 bits (12-bit address) for the on-chip ram ? expandability of the peripheral hardware have been adopted to realize the following features: (1) data memory bank configuration (2) memory mapped i/o this chapter describes the data memory bank configuration and the memory mapped i/o. 3.1 data memory bank configuration and addressing mode 3.1.1 data memory bank configuration 512 words x 4 bits (1024 words x 4 bits note ) of static ram is included on-chip in addresses 000h through 1ffh (000h through 3ffh note ) of the data memory space. of this, addresses 1e0h through 1ffh are 32-words x 4- bit display data memory. peripheral hardware (input/output ports and timers etc.) is allocated to addresses f80h through fffh. for addressing the 12-bit address (4k words x 4 bits) data memory space, the m pd75308 has a memory bank configuration in which instructions are used to directly or indirectly specify the low-order 8-bit addresses and the memory bank is used to specify the high-order 4-bit addresses. to specify the memory bank (mb), the m pd75308 has the following two on-chip hardware units: ? memory bank enable flag (mbe) ? memory bank select register (mbs) the mbs is a register to select the memory bank and banks 0, 1 and 15 (0, 1, 2, 3 and 15 note ) can be set for the m pd75308. the mbe is a flag to determine if the memory bank selected by mbs should be validated. when mbe is 0, the selected memory bank (mb) is fixed irrespectively of the mbs as shown in figure 3-1. when mbe is 1, the data memory space can be expanded by switching the memory bank according to mbs setting. for data memory space addressing, mbe = 1 is usually set and the data memory of the memory bank specified by mbs is manipulated. to execute programming efficiently, the mbe = 0 mode or the mbe = 1 mode can be selected in each program processing. note m pd75312b, 75316b, 75p316a and 75p316b only appropriate program processing effect mbe = 0 mode ? interrupt servicing mbs save/restore is not necessary ? processing of repeating on-chip hardware mbs change is not necessary. operation and static ram operation ? subroutine processing mbs save/restore is not necessary. mbe = 1 mode ? normal program processing
36 chapter 3 features of architecture and memory map figure 3-1. selection of mbe = 0 mode and mbe = 1 mode remark ___________ : when mbe = 1, C C C C C: when mbe = 0 since the mbe is automatically saved/restored during subroutine processing, it can be changed freely during that processing operation. in the interrupt servicing operation, the mbe is automatically saved/restored, and furthermore, mbe undergoing interrupt servicing can be specified upon start of interrupt servicing by setting the interrupt vector table so that high-speed interrupt servicing operations can be carried out efficiently. when changing the mbs by executing the subroutine or interrupt servicing operation, the mbs is saved/ restored by the push/pop instruction. mbe is set by the set1/clr1 instruction. mbs is set by the sel instruction. examples 1. mbe is cleared and the memory bank is fixed. clr1 mbe ; mbe 0 2. memory bank 1 is selected. set1 mbe ; mbe 1 sel mb1 ; mbs 1 on-chip hardware operation and static ram opreation are repeated. ; mbe = 0 is set in the vector table.
set 1 mbe clr 1 mbe mbe = 1 mbe = 0 set 1 mbe mbe = 1 clr1 mbe ret reti mbe = 0 mbe = 0
37 chapter 3 features of architecture and memory map 3.1.2 data memory addressing mode in the 75x series architecture used for the m pd75308, seven addressing modes are available, as shown in figure 3-2, for efficiently addressing the data memory space for each bit length of data to be processed. (1) 1-bit direct addressing (mem.bit) in this addressing mode, the bits of the whole data memory space are directly specified by instruction operands. in the mbe = 0 mode, the memory bank (mb) is fixed to 0 when the operand specified addresses are 00h to 7fh and the mb is fixed to15 when the operand specified addresses are 80h to ffh. therefore both the 000h to 07fh data area and the f80h to fffh peripheral hardware area can be addressed in the mbe = 0 mode. in the mbe = 1 mode, mb becomes equal to mbs so that the specifiable data memory space can be expanded. this addressing mode can be used for the bit set and reset instructions (set1, clr1) and the bit test instructions (skt, skf). example test if flag1 is set, flag2 is reset, and flag3 is 0. flag1 equ 03fh.1 ; address 3fh bit 1 flag2 equ 087h.2 ; address 87h bit 2 flag3 equ 0a7h.0 ; address a7h bit 0 set1 mbe ; mbe 1 sel mb0 ; mbs 0 set1 flag1 ; flag1 1 clr1 flag2 ; flag2 0 skf flag3 ; flag3 = 0?
38 chapter 3 features of architecture and memory map figure 3-2. data memory configuration and addressing range in each addressing mode note the m pd75312b, 75316b, 75p316a, 75p316b only 000h 007h memory bank enable flag register area stack addressing addressing mode mem mem. bit @hl @h + mem. bit @de @dl fmem. bit pmem. @l mbe = 0 mbe = 1 mbe = 0 mbe = 1 data area static ram (memory bank 0) 07fh 0ffh 100h 1dfh 1e0h 1ffh 200h 2ffh 300h 3ffh f80h fb0h fbfh fc0h ff0h fffh mbs = 0 data area static ram (memory bank 1) data area display data memory (memory bank 1) data area static ram (memory bank 2) data area static ram (memory bank 3) peripheral hardware area (memory bank 15) mbs = 0 mbs = 15 mbs = 15 mbs = 1 mbs = 1 mbs = 2 mbs = 3 mbs = 1 mbs = 1 mbs = 2 mbs = 3 not incorporated : don't care note
39 chapter 3 features of architecture and memory map figure 3-3. addressing mode addressing mode format address to be specified 1-bit direct addressing mem. bit bit specified by bit of address specified by mb and mem mbe = 0, when mem = 00h to 7fh, mb = 0 when mem = 80h to ffh, mb = 15 when mbe = 1, mb = mbs 4-bit direct addressing mem address specified by mb and mem mbe = 0, when mem = 00h to 7fh, mb = 0 when mem = 80h to ffh, mb = 15 when mbe = 1, mb = mbs 8-bit direct addressing address specified by mb and mem (= even address) mbe = 0, when mem = 00h to 7fh, mb = 0 when mem = 80h to ffh, mb = 15 when mbe = 1, mb = mbs 4-bit register indirect addressing @hl address specified by mb and hl when mb = mbe?mbs @de address specified by de of memory bank 0 @dl address specified by dl of memory bank 0 8-bit register indirect addressing @hl address specified by mb and hl (with l register having an even number content) when mb = mbe?mbs bit manipulation addressing fmem.bit bit specified by bit of address specified by fmem fmem = fb0h to fbfh (interrupt related hardware) ff0h to fffh (i/o port) pmem. @l bit specified by the low-order 2 bits of l register of the address specified by the high-order 10 bits of pmem and the high-order 2 bits of l register when pmem = fc0h to fffh @h+mem. bit bit specified by bit of the address specified by mb, h and the low-order 4 bits of mem when mb = mbe?mbs stack addressing address specified by sp of memory bank 0 remark on the m pd75312b, 75316b, 75p316a, and 75p316b, mbs = 0, 1, 2, 3 or 15. otherwise, mbs = 0, 1 or 15.
40 chapter 3 features of architecture and memory map (2) 4-bit direct addressing (mem) this addressing mode enables to directly specify the whole data memory space in 4-bit units by an instruction operand. like in 1-bit direct addressing, the specifiable area is fixed to the 000h to 07fh data area and the f80h to fffh peripheral hardware area in the mbe = 0 mode. in the mbe = 1 mode, mb becomes equal to mbs and the specifiable data memory space is expanded to the whole space. this addressing mode is used for the mov, xch, incs, in and out instructions. caution as in example 1, program efficiency decreases if input/output port related data is stored in the static ram of bank 1. if the data is stored at addresses 00h to 7fh of bank 0, programming can be performed without changing mbs as in the example 2. examples 1. buff data is output to port 5. buff equ 11ah ; b uff at address 11ah set1 mbe ; mbe 1 sel mb1 ; mbs 1 mov a, buff ; a (buff) sel mb15 ; mbs 15 out port5, a ; port5 a 2. port 4 is input and is stored in data1. data1 equ 5fh ; data1 at address 5fh clr1 mbe ; mbe 0 in a, port4 ; a port4 mov data1, a ; (dat a1) a (3) 8-bit direct addressing (mem) this addressing mode enanbles to directly specify the whole data memory space in 8-bit units by an instruction operand. only even addresses can be specified by operands. 4-bit data of the operand specified address and 4- bit data of the address added by one undergo 8-bit processing in pairs with the 8-bit accumulator (xa register pair). the same memory bank as in 4-bit direct addressing is specified. this addressing mode is used for the mov, xch, in and out instructions. examples 1. 8-bit data of ports 4 and 5 are transferred to addresses 20h and 21h. data equ 020h clr1 mbe ; mbe 0 in xa, port4 ; x port 5, a port 4 mov data, xa ; (21h) x, (20h) a 2. as soon as 8-bit data input to the shift register (sio) of the serial interface is fetched, transfer data is set and transfer start is instructed. sel mb15 ; mbs 15 xch xa, sio ; xa (sio)
41 chapter 3 features of architecture and memory map (4) 4-bit register indirect addressing (@rpa) this addressing mode enables to indirectly specify the data memory space in 4-bit units with the data pointer (register pair of the general register) specified by an instruction operand. three types of data pointers are available: hl register pair which can specify the whole data memory space by specification of mb = mbe?mbs, de register pair and dl register pair which are fixed to memory bank 0 irrespectively of mbe and mbs specification. programming can be performed efficiently by selecting one of the three data pointers according to the bank of the data memory to be used. example 50h to 57h data is transferred to 110h to 117h. data1 equ 57h data2 equ 117h set1 mbe sel mb1 mov d, #data1 shr 4 mov hl, #data2 and 0ffh ; hl 17h loop: mov a, @dl ; a (dl) xch a, @hl ; a (hl) decs l ; l l C 1 br loop the addressing mode using the hl register pair as the data pointer is widely used for data transfer, arithmetic operation, comparison, input/output and other relevant operations. the addressing mode using the de/dl register pair is used for the mov and xch instructions. in combination with the increment/decrement instruction of the general register or the register pair, the address of the data memory space can be updated freely as shown in figure 3-4. example 1. 50h to 57h data is compared to 110h to 117h data. data1 equ 57h data2 equ 117h set1 mbe sel mb1 mov d, #data1 shr4 mov hl, #data2 and 0ffh loop: mov a, @dl ske a, @hl ; a = (hl)? br no ; no decs l ; yes, l l C 1 br loop 2. the 00h to ffh data memory is cleared to 0. clr1 mbe mov xa, #00h mov l, #04h loop: mov @hl, a ; (hl) a incs l ; l l + 1 br loop incs h ; h h + 1 br loop
42 chapter 3 features of architecture and memory map figure 3-4. static ram address updating procedure 0 h f h @dl 4-bit transfer decs d incs d decs l incs l @hl 4-bit manipulation decs h incs h decs l incs l direct addressing bit manipulation 4-bit transfer 8-bit transfer decs d incs d decs e incs e @h + mem. bit bit manipulation decs h incs h @de 4-bit transfer 0h fh
43 chapter 3 features of architecture and memory map (5) 8-bit register indirect addressing (@hl) this addressing mode enables to indirectly specify the whole data memory space in 8-bit units with the data pointer (hl register pair). 4-bit data of the address with bit 0 of the data pointer (l register bit 0) set to 0 and 4-bit data of the address added by one undergo 8-bit processing in pairs with the 8-bit accumulator (xa register). the specified memory bank is mb = mbe?mbs as when the hl register is specified by 4-bit register indirect addressing. this addressing mode is used for the mov, xch and ske instructions. examples 1. the counter register (t0) value of the timer/event counter 0 is checked if it is equal to data at addresses 30h and 31h. data equ 30h clr1 mbe mov hl, #data mov xa, t0 ; xa count register 0 ske a, @hl ; a = (hl)? br no incs l mov a, x ; a x ske a, @hl ; a = (hl)? 2. the 00h to ffh data memory is cleared to 0. clr1 mbe mov xa, #00h mov hl, #04h loop: mov @hl, a ; (hl) a incs l br loop incs h br loop
44 chapter 3 features of architecture and memory map (6) bit manipulation addressing this addressing mode enables to carry out bit manipulations (boolean processing, bit transfer, etc.) for each bit in the whole data memory space. while the 1-bit direct addressing mode can only be used for the bit set, reset and test instructions, the bit manipulation addressing mode enables to carry out many bit manipulations including boolean processing by the and1, or1 and xor1 instructions and test & reset by the sktclr instruction. the following three bit manipulation addressing modes are available to be selected according to the data memory address in use. (a) specific address bit direct addressing (fmem. bit) this addressing mode enables to operate the peripheral hardware frequently executing bit manipulations, such as the input/output ports and interrupt related flags, irrespectively of memory bank setting. thus, the memory addresses usable for this addressing mode are ff0h to fffh at which input/output ports are mapped and fb0h to fbfh at which interrupt related hardware is mapped. the hardware located in these two data memory areas can carry out bit manipulation by direct addressing irrespectively of mbs and mbe settings. examples 1. the timer 0 interrupt request flag (irqt0) is tested. if the flag has been set, it is cleared and p63 is reset. sktclr irqt0 ; irqt0 = 1? br no ; no clr1 port6. 3 ; yes 2. if both p30 and p41 are 1, p53 is reset. (i) set1 cy ; cy 1 and1 cy, port3. 0 ; cy ^ p30 and1 cy, port4. 1 ; cy ^ p41 skt cy ; cy = 1? br setp clr1 port5. 3 ; p53 0 setp: set1 port5. 3 ; p53 1 (ii) skt port3. 0 ; p30 = 1? br setp skt port4. 1 ; p41 = 1? br setp clr1 port5. 3 ; p53 0 setp: set1 port5. 3 ; p53 1 ? ? ? ? ? ? ? ? ? ? ? ? p30 p41 p53
45 chapter 3 features of architecture and memory map (b) specific address bit register indirect addressing (pmem. @l) this addressing mode enables to continuously operate each bit of the input/output port among the peripheral hardware by indirect register addressing. this addressing mode can be used for the fc0h to fffh data memory addresses. in this addressing mode, the high-order 10 bits of the 12 bits of the data memory address are directly specified by an operand and the low-order 2-bit address and the bit address are indirectly specified using the l register. thus, 16 bits (4 ports) can be continuously operated by l register specification. this addressing mode also enables to carry out bit manipulation irrespectively of mbe and mbs settings. example pulses are sequentially output to the bits of ports 4 to 7. p40 p41 p73 mov l, #0 loop: set1 port4. @l ; bits (l 1C0 ) of ports 4 to 7 1 clr1 port4. @l ; bits (l 1C0 ) of ports 4 to 7 0 incs l nop br loop
46 chapter 3 features of architecture and memory map (c) specific 1-bit direct addressing (@h+mem. bit) this addressing mode enables to carry out bit manipulation for the bits in the whole data memory space. in this addressing mode, the high-order 4 bits of the data memory address of the memory bank specified by mb = mbe?mbs are indirectly specified using the h register and the low-order 4-bit address and the bit address are directly specified by an operand. this addressing mode enables to carry out many bit operations for the bits in the whole data memory space. example if bit 3 (flag1) at address 30h and bit 0 (flag2) at address 31h are both 0 or 1, bit 2 (flag3) at address 32h is reset. flag1 equ 30h. 3 flag2 equ 31h. 0 flag3 equ 32h. 2 sel mb0 mov h, #flag1 shr 6 clr cy, ; cy 0 or1 cy, @h+flag1 ; cy cy | flag1 xor1 cy, @h+flag2 ; cy cy | flag2 set1 @h+flag3 ; flag3 1 skt cy ; cy = 1? clr1 @h+flag3 ; flag3 0 flag1 flag2 flag3
47 chapter 3 features of architecture and memory map (7) stack addressing this addressing mode enables to carry out save/restore operations during interrupt or subroutine servicing. in this mode, the address indicated by the stack pointer (8 bits) of data memory bank 0 is specified. this addressing mode is also used for register save/restore operations by the push/pop instruction. examples 1. the register is saved/restored by subroutine processing. sub: push xa push hl push bs ; mbs save pop bs pop hl pop xa ret 2. hl register pair contents are transferred to the de register pair. push hl pop de ; de hl 3. data is branched to the address specified by the [xabc] register. push bc push xa ret ; branched to the address xabc . . .
48 chapter 3 features of architecture and memory map 3.2 memory mapped i/o as shown in figure 3-2, the m pd75308 has a memory mapped i/o with the peripheral hardware such as input/ output ports and timers mapped at addresses f80h to fffh in the data memory space. thus, memory manipulation instructions are used instead of special instructions to control the peripheral hardware. (hardware control mnemonic is partly used to facilitate the understanding of the program.) the addressing modes listed in table 3-1 are available to operate the peripheral hardware. the display data memory mapped at addresses 1e0h to 1ffh is operated by specifying memory bank 1. table 3-1. addressing modes applicable for peripheral hardware operations applicable addressing mode applicable hardware bit manipulation direct addressing mode to be specified by mem. bit with all hardware devices capable of mbe = 0 or (mbe = 1, mbe = 15) carrying out bit manipulations direct addressing mode to be specified by fmem. bit ist0, mbe irrespectively of mbe and mbs settings iexxx, irqxxx, portn. x indirect addressing mode to be specified by pmem. @l bsbn. x irrespectively of mbe and mbs settings portn. x 4-bit manipulation direct addressing mode to be specified by mem with all hardware devices capable of mbe = 0 or (mbe = 1, mbs = 15) carrying out 4-bit manipulations register indirect addressing mode to be specified by @hl with (mbe = 1, mbs = 15) 8-bit manipulation direct addressing mode to be specified by mem all hardware devices capable of (= even address) with mbe = 0 or (mbe = 1, mbs = 15) carrying out 8-bit manipulations register indirect addressing mode to be specified by @hl (with the l register content set to even number) with mbe = 1 and mbs = 15 example clr1 mbe ; mbe = 0 set1 tm0. 3 ; timer 0 start ei ie0 ; int0 enable di ie1 ; int1 disable sktclr irq2 ; int2 request flag test and clear set1 port4. @l ; port 4 set mov x, #0 ; x = 0 is set in a, port0 ; a port 0 out port4, xa ; port 5, 4 xa
49 chapter 3 features of architecture and memory map figure 3-5 shows the i/o map of m pd75308. each item in the figure has the following meaning. ? symbol : name indicating the address of on-chip hardware can be described in the instruction operand column. ? r/w : indicates if the corresponding hardware is read/write enable. r/w : read/write enable r : only read enable w : only write enable ? no. of manipulatable bits : indicates the number of bits which can be operated when the corresponding hardware is operated. : bit manipulation enabled in 1, 4 or 8-bit units specified in the column : operation enable for part of bits. refer to the remarks column for bits which can be operated. C : bit manipulation disabled in 1, 4 or 8-bit units specified in the column ? bit manipulation addressing : indicates the applicable bit manipulation addressing mode for bit manipulations of the corresponding hardware.
50 chapter 3 features of architecture and memory map figure 3-5. m m m m m pd75308 i/o map (1/3) address hardware name (symbol) r/w no. of manipulatable bits bit manipulation remarks b3 b2 b1 b0 1 bit 4 bits 8 bits addressing f80h stack pointer (sp) r/w CC bit 0 fixed to 0 f85h basic interval timer mode register (btm) w C mem. bit only bit 3 can be operated f86h basic interval timer (bt) r CC f8ch display mode register (lcdm) w C mem. bit only bit 3 can be operated CC f8eh display control register (lcdc) w C C f98h timer mode register (wm) r/w (r) C mem. bit only bit 3 can be tested note 1 C C (w) fa0h timer/event counter 0 mode w C mem. bit only bit 3 can be operated register (tm0) C C fa2h toe0 note 2 w C C mem. bit fa4h timer/event counter 0 count r C C register (t0) fa6h timer/event counter 0 modulo w C C register (tmod0) notes 1. 1-bit manipulation: r only; 8-bit manipulation: w only 2. toe0 ... timer/event counter 0 output enable flag
51 chapter 3 features of architecture and memory map figure 3-5. m m m m m pd75308 i/o map (2/3) address hardware name (symbol) r/w no. of manipulatable bits bit manipulation remarks b3 b2 b1 b0 1 bit 4 bits 8 bits addressing fb0h 0 ist0 mbe 0 r/w (r/w) (r/w) fmem.bit 8-bit manipulation: r only cy sk2 sk1 sk0 C C (r) fb2h (ime) CCCC operation by ei/di instruction fb3h processor clock control register (pcc) w C note fb4h int0 mode register (im0) w C C bit 2 fixed to 0 fb5h int1 mode register (im1) w C bits 3, 2, 1 fixed to 0 fb6h int2 mode register (im2) w C bits 3, 2 fixed to 0 fb7h system clock control register (scc) w C bits 2, 1 fixed to 0 fb8h ie4 irq4 iebt irqbt r/w C fmem. bit fbah iew irqw r/w fbch iet0 irqt0 r/w C fbdh iecsi irqcsi r/w fbeh ie1 irq1 ie0 irq0 r/w C fbfh ie2 irq2 r/w fc0h bit sequential buffer 0 (bsb0) r/w mem. bit fc1h bit sequential buffer 1 (bsb1) r/w pmem. @l fc2h bit sequential buffer 2 (bsb2) r/w fc3h bit sequential buffer 3 (bsb3) r/w fd0h clock output mode register (clom) w C C fdch pull-up resistor specify w C C register group a (poga) note bits 3 and 2 can be manipulated at stop/halt instruction execution. remarks 1. iexxx is an interrupt enable flag. 2. irqxxx is an interrupt request flag. 3. ime is an interrupt master enable flag. C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C program status word (psw)
52 chapter 3 features of architecture and memory map figure 3-5. m m m m m pd75308 i/o map (3/3) address hardware name (symbol) r/w no. of manipulatable bits bit manipulation remarks b3 b2 b1 b0 1 bit 4 bits 8 bits addressing fe0h serial operation mode register (csim) r/w C C csie coi wup (r) (w) (w) mem. bit fe2h cmdd reld cmdt relt r/w C C mem. bit r or w varies in every bits. bsye ackd acke ackt fe4h serial i/o shift register (sio) r/w C C fe6h slave address register (sva) w C C fe8h pm33 pm32 pm31 pm30 wC C pm63 pm62 pm61 pm60 fech C pm2 C C wC C pm7 C pm5 pm4 ff0h port 0 (port 0) r C fmem. bit ff1h port 1 (port 1) r pmem. @l ff2h port 2 (port 2) r/w C ff3h port 3 (port 3) r/w ff4h port 4 (port 4) r/w ff5h port 5 (port 5) r/w ff6h kr3 kr2 kr1 kr0 r/w port 6 (port 6) ff7h kr7 kr6 kr5 kr4 r/w port 7 (port 7) notes 1. in bit manipulation, r or w varies from bit to bit. 8-bit manipulation: w only 2. kr0 to kr7 are read only. they can be specified by port 6 or port 7 in the 4-bit parallel input mode. C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C port mode register group b (pmgb) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C port mode register group a (pmga) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C sbi control register (sbic) C C C C C C C C C C C C C C C C C C C C note 2 note 2 bits 3, 2, 1 are bit-manipulatable note 1
53 chapter 4 internal cpu function chapter 4 internal cpu function 4.1 program counter (pc): 12 bits ( m m m m m pd75304, 75304b) 13 bits ( m m m m m pd75306, 75306b, 75308, 75308b, 75p308) 14 bits ( m m m m m pd75312, 75312b, 75316, 75316b, 75p316, 75p316a, 75p316b) the pc is a binary counter to hold the program memory address. the m pd75304, 75304b has a 12-bit configuration (refer to figure 4-1 (a) ). the m pd75306, 75306b, 75308, 75308b and 75p308 each have a 13-bit configuration (refer to figure 4-1 (b) ). the m pd75312, 75312b, 75316, 75316b, 75p316, 75p316a and 75p316b each have a 14-bit configuration (refer to figure 4-1 (c) ). figure 4-1. program counter configuration (a) m m m m m pd75304, 75304b (b) m m m m m pd75306, 75306b, 75308, 75308b, 75p308 (c) m m m m m pd75312, 75312b, 75316, 75316b, 75p316, 75p316a, 75p316b the program counter value is automatically incremented according to the number of bytes of the instruction each time an instruction is executed. when a branch instruction (br, brcb) is executed, immediate data or register pair content indicating the branch point address is loaded into all or some bits in the pc. when a subroutine call instruction (call, callf) is executed of a vectored interrupt is generated, the pc content (return address incremented to fetch the next instruction) is saved into the stack memory (data memory specified by the stack pointer) and the address in the jump destination is loaded. when a return instruction (ret, rets, reti) is executed, the stack memory content is set into the pc. when the reset signal is generated, the program memory content is loaded into the program counter for initialization. thus, the program can be started at any selected address. m pd75304, 75304b: pc11 to pc8 low-order 4 bits of address 000h pc7 to pc0 8 bits of address 001h m pd75306, 75306b, 75308, 75308b, 75p308: pc12 to pc8 low-order 5 bits of address 0000h pc7 to pc0 8 bits of address 0001h m pd75312, 75312b, 75316, 75316b, 75p316, 75p316a, 75p316b: pc13 to pc8 low-order 6 bits of address 0000h pc8 to pc0 8 bits of address 0001h pc11 pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 pc12 pc11 pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 pc13 pc12 pc11 pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0
54 chapter 4 internal cpu function 4.2 program memory (rom): 4096 words x 8 bits ( m m m m m pd75304, 75304b) 6016 words x 8 bits ( m m m m m pd75306, 75306b) 8064 words x 8 bits ( m m m m m pd75308, 75308b, 75p308) 12160 words x 8 bits ( m m m m m pd75312, 75312b) 16256 words x 8 bits ( m m m m m pd75316, 75316b, 75p316, 75p316a, 75p316b) the program memory is used to store the program, interrupt vector table, geti instruction reference table and table data. the mask programmable rom serves as the program memory for the m pd75304, 75304b, 75306, 75306b, 75308, 75308b, 75312, 75312b, 75316, 75316b. the prom serves as the program memory for the m pd75p308, 75p316, 75p316a and 75p316b. figures 4-2 to 4-6 show the program memory maps. addressing is performed by the program counter. table data can be referred to by the table reference instruction (movt). the address ranges which can be branched by the branch instruction and the subroutine call instruction are shown in figures 4-2 to 4-6. the relative branch instruction (br $addr) enables to branch to the [pc content C15 to C1, +2 to +16] addresses, irrespectively of block. the program memory address ranges are as follows: ? 000h to ffh : m pd75304, 75304b ? 0000h to 177fh : m pd75306, 75306b ? 0000h to 1f7fh : m pd75308, 75308b, 75p308 ? 0000h to 2f7fh : m pd75312, 75312b ? 0000h to 3f7fh : m pd75316, 75316b, 75p316, 75p316a, 75p316b special functions are assigned for the following addresses. all areas except 0000h to 0001h (000h to 001h note 1 ) can be used as the normal program memory. ? 0000h to 0001h (000h to 001h note 1 ) vector address table for writing the program status address and mbe set value when resetting. (reset can be started from any selected address.) ? 0002h to 000bh (002h to 00bh note 1 ) vector address table for writing the program start address and mbe set value by each vector interrupt. (interrupt servicing can be started from any selected address.) ? 0020h to 007fh (020h to 07fh note 1 ) table area which is referred to by geti instruction note 2 . notes 1. in the case of m pd75304, 75304b. 2. geti instruction is an instruction to realize any 2-byte/3-byte instruction or two 1-byte instructions with one byte, and can reduce the number of program bytes.
55 chapter 4 internal cpu function figure 4-2. program memory map ( m m m m m pd75304, 75304b) 7 mbe mbe mbe mbe mbe mbe 0 0 0 0 0 0 000h 002h 004h 006h 008h 00ah geti instruction reference table brcb !caddr instruction branch address br $addr instruction relative branch address (?5 to ?, +2 to +16) 020h 07fh 080h 7ffh 800h fffh 0 internal reset start address (high-order 4 bits) internal reset start address (low-order 8 bits) intbt/lnt4 start address (high-order 4 bits) intbt/lnt4 start address (low-order 8 bits) int0 start address (high-order 4 bits) int0 start address (low-order 8 bits) int1 start address (high-order 4 bits) int1 start address (low-order 8 bits) intcsi start address (high-order 4 bits) intcsi start address (low-order 8 bits) intt0 start address (high-order 4 bits) intt0 start address (low-order 8 bits) 65 address 0 0 0 0 0 0 callf !faddr instruction entry address call !addr instruction subroutine entry address branch destination address and subroutine entry address by geti instructlon 4 0 0 0 0 0 0
56 chapter 4 internal cpu function figure 4-3. program memory map ( m m m m m pd75306, 75306b) 7 mbe mbe mbe mbe mbe mbe 0 0 0 0 0 0 0000h 0002h 0004h 0006h 0008h 000ah geti instruction reference table br !addr instruction branch address br $addr instruction relative branch address (?5 to ?, +2 to +16) brcb !caddr instruction branch address brcb !caddr instruction branch address 0020h 007fh 0080h 07ffh 0800h 0fffh 1000h 177fh 0 internal reset start address (high-order 5 bits) internal reset start address (low-order 8 bits) intbt/lnt4 start address (high-order 5 bits) intbt/lnt4 start address (low-order 8 bits) int0 start address (high-order 5 bits) int0 start address (low-order 8 bits) int1 start address (high-order 5 bits) int1 start address (low-order 8 bits) intcsi start address (high-order 5 bits) intcsi start address (low-order 8 bits) intt0 start address (high-order 5 bits) intt0 start address (low-order 8 bits) 65 address 0 0 0 0 0 0 callf !faddr instruction entry address call !addr instruction subroutine entry address branch destination address and subroutine entry address by geti instructlon
57 chapter 4 internal cpu function figure 4-4. program memory map ( m m m m m pd75308, 75308b, 75p308) 7 mbe mbe mbe mbe mbe mbe 0 0 0 0 0 0 0000h 0002h 0004h 0006h 0008h 000ah geti instruction reference table br !addr instruction branch address br $addr instruction relative branch address (?5 to ?, +2 to +16) brcb !caddr instruction branch address brcb !caddr instruction branch address 0020h 007fh 0080h 07ffh 0800h 0fffh 1000h 1f7fh 0 internal reset start address (high-order 5 bits) internal reset start address (low-order 8 bits) intbt/lnt4 start address (high-order 5 bits) intbt/lnt4 start address (low-order 8 bits) int0 start address (high-order 5 bits) int0 start address (low-order 8 bits) int1 start address (high-order 5 bits) int1 start address (low-order 8 bits) intcsi start address (high-order 5 bits) intcsi start address (low-order 8 bits) intt0 start address (high-order 5 bits) intt0 start address (low-order 8 bits) 65 address 0 0 0 0 0 0 callf !faddr instruction entry address call !addr instruction subroutine entry address branch destination address and subroutine entry address by geti instructlon
58 chapter 4 internal cpu function figure 4-5. program memory map ( m m m m m pd75312, 75312b) 7 mbe mbe mbe mbe mbe mbe 0 0 0 0 0 0 0000h 0002h 0004h 0006h 0008h 000ah geti instruction reference table br !addr instruction branch address br $addr instruction relative branch address ( _ 15 to _ 1, +2 to +16) brcb !caddr instruction branch address brcb !caddr instruction branch address 0020h 007fh 0080h 07ffh 0800h 0fffh 1000h 2f7fh 0 internal reset start address (high-order 6 bits) internal reset start address (low-order 8 bits) intbt/lnt4 start address (high-order 6 bits) intbt/lnt4 start address (low-order 8 bits) int0 start address (high-order 6 bits) int0 start address (low-order 8 bits) int1 start address (high-order 6 bits) int1 start address (low-order 8 bits) intcsi start address (high-order 6 bits) intcsi start address (low-order 8 bits) intt0 start address (high-order 6 bits) intt0 start address (low-order 8 bits) 6 address callf !faddr instruction entry address call !addr instruction subroutine entry address branch destination address and subroutine entry address by geti instructlon 1fffh 2000h brcb !caddr instruction branch address
59 chapter 4 internal cpu function figure 4-6. program memory map ( m m m m m pd75316, 75316b, 75p316, 75p316a, 75p316b) 7 mbe mbe mbe mbe mbe mbe 0 0 0 0 0 0 0000h 0002h 0004h 0006h 0008h 000ah geti instruction reference table br !addr instruction branch address br $addr instruction relative branch address (?5 to ?, +2 to +16) brcb !caddr instruction branch address brcb !caddr instruction branch address 0020h 007fh 0080h 07ffh 0800h 0fffh 1000h 3f7fh 0 internal reset start address (high-order 6 bits) internal reset start address (low-order 8 bits) intbt/lnt4 start address (high-order 6 bits) intbt/lnt4 start address (low-order 8 bits) int0 start address (high-order 6 bits) int0 start address (low-order 8 bits) int1 start address (high-order 6 bits) int1 start address (low-order 8 bits) intcsi start address (high-order 6 bits) intcsi start address (low-order 8 bits) intt0 start address (high-order 6 bits) intt0 start address (low-order 8 bits) 6 address callf !faddr instruction entry address call !addr instruction subroutine entry address branch destination address and subroutine entry address by geti instructlon 1fffh 2000h brcb !caddr instruction branch address 2fffh 3000h brcb !caddr instruction branch address
60 chapter 4 internal cpu function 4.3 data memory (ram): 512 words x 4 bits ( m m m m m pd75304, 75304b, 75306, 75306b, 75308, 75308b, 75p308, 75312, 75316, 75p316) 1024 words x 4 bits ( m m m m m pd75312b, 75316b, 75p316a, 75p316b) the data memory consists of a data area and a peripheral hardware area as shown in figure 4-7. the data memory has a bank configuration, with one bank consisting of 256 words x 4 bits. the memory banks are as follows: ? memory banks 0 and 1 (data area) note ? memory bank 15 (peripheral hardware area) note memory banks 0, 1, 2 and 3 on the m pd75312b, 75316b, 75p316a, 75p316b only. 4.3.1 data memory configuration (1) data area the data area comprises static ram and is used for data storage and as stack memory during execution of subroutines and interrupts. long-term retention of memory contents is possible even on battery backup power when cpu operation is halted in standby mode. manipulation is by means of memory manipulation instructions. a 256 x 4-bit area of static ram is mapped onto each of memory banks 0 and 1 note 1 . bank 0 is mapped as a data area, but can also be used as a general register area (000h to 007h) and a stack memory area (000h to 0ffh). bank 1 is used as display data memory (1e0h to 1ffh). static ram has a 4-bit address configuration. however, it is possible to manipulate in 8-bit units using 8-bit memory manipulation instructions, and bit-wise using bit manipulation instructions note 2 . in 8-bit manipulation instructions, an even address should be specified. notes 1. memory banks 0, 1, 2 and 3 on the m pd75312b, 75316b, 75p316a and 75p316b only. 2. 8-bit manipulation is not possible on display data memory. ? general register area this area can be manipulated by either general register manipulation instructions or memory manipulation instructions. up to eight 4-bit registers can be used. any of the general registers not used by the program can be used as data area or stack area memory. ? stack memory area the stack area is set up by an instruction, and can be used as a save area during execution of a subroutine or interrupt servicing. ? display data memory area this is the area to which lcd display data is written. when driving and lcd, the data written to this display data memory area is automatically read by hardware and then displayed. any portion not used for display can be used as part of the data area.
61 chapter 4 internal cpu function (2) peripheral hardware area the peripheral hardware area is mapped onto addresses f80h through fffh of memory bank 15. this area is manipulated by memory manipulation instructions in the same way as static ram. with peripheral hardware, however, the bit units which can be manipulated vary from address to address. as data memory is not incorporated on chip for addresses not allocated to peripheral hardware, they cannot be accessed. 4.3.2 data memory bank specification the 4-bit memory bank selection register (mbs) is used to specify the memory bank (mbs = 0, 1 or 15 note ) when the memory bank enable flag (mbe) specifies that bank selection is enabled (mbe = 1). when bank specification is disabled (mbs = 0), the memory bank is automatically specified as either bank 0 or bank 15 according to the current addressing mode. addresses in the bank are addressed by 8-bit immediate data or a register pair, etc. for details of memory bank selection and addressing, refer to 3.1 data memory bank configuration and addressing mode . for the use of specific areas in the data memory, please refer to the following sections. ? general register area ............ 4.4 general register ? stack memory area ............... 4.6 stack pointer (sp) ? display data memory ............ 5.7.5 display data memory ? peripheral hardware .............. chapter 5 peripheral hardware functions note mbs = 0, 1, 2, 3 or 15 on the m pd75312b, 75316b, 75p316a and 75p316b only.
62 chapter 4 internal cpu function figure 4-7. data memory map (8 4) bank 0 007h 008h 000h 0ffh 100h 1d0h 1e0h 1ffh 200h 2ffh 300h 3ffh bank 1 bank 2 bank 3 256 4 256 4 (32 4) 256 4 256 4 data area static ram (512 4) stack area display data memory (32 4) bank 15 f80h fffh 128 4 peripheral hardware area not incorporated data area static ram (512 4) general register area note note the m pd75312b, 75316b, 75p316a, and 75p316b only
63 chapter 4 internal cpu function the data memory is indeterminate when reset. thus, initialize it to zero at the beginning of the normal program (ram clear). make sure to do so, or bugging may result. example the ram at addresses 000h to 1ffh is cleared. set1 mbe sel mb0 mov xa, #00h mov hl, #04h ramc0: mov @hl, a ; 04h to ffh clear note incs l ; l l + 1 br ramc0 incs h ; h h + 1 br ramc0 sel mb1 ramc1: mov @hl, a ; 100h to 1ffh clear incs l ; l l + 1 br ramc1 incs h ; h h + 1 br ramc1 note since the data memory at addresses 000h to 003h is used as the general register xa or hl, it is not cleared to zero.
64 chapter 4 internal cpu function figure 4-8. display data memory configuration the display data memory is manipulated in 1 or 4-bit units. caution the display data memory cannot be manipulated in 8-bit units. example the 1e0h to 1ffh display data memory is cleared. set1 mbe sel mb1 mov hl, #0e0h mov a, #00h loop: mov @hl, a ; the display data memory is cleared to 0 all at once in 4-bit units. incs l br loop incs h br loop 1f8h 1f9h 1fah 1fbh 1fch 1fdh 1feh 1ffh bp0 bp1 bp2 bp3 bp4 bp5 bp6 bp7 s24/bp0 s25/bp1 s26/bp2 s27/bp3 s28/bp4 s29/bp5 s30/bp6 s31/bp7 com0 com1 com2 com3 1e0h 1e1h 1e2h 1e3h s0 s1 s2 s3 b 0 b 1 b 2 b 3 address display data memory segment output/bit port output common signals
65 chapter 4 internal cpu function 4.4 general register: 8 x 4 bits eight 4-bit general registers (b, c, d, e, h, l, x, a) are mapped at the specific addresses of the data memory. each general register is operated in 4-bit units. bc, de, hl and xa make up register pairs to be used for 8-bit operations. dl also makes up a register pair and three pairs, de, hl and dl, can be used as the data pointer. the general register area can be accessed by addressing as a normal ram whether it is used as a register or not. figure 4-9. general register configuration (for 4-bit processing) x 01h a 00h h 03h l 02h d 05h e 04h b 07h c 06h figure 4-10. general register configuration (for 8-bit processing) xa 00h hl 02h de 04h bc 06h figure 4-11. register pair configuration 0 3 b 0 3 c 0 3 d 0 3 e 0 3 h 0 3 l 0 3 x 0 3 a
66 chapter 4 internal cpu function 4.5 accumulator the m pd75308, the a register and the xa register pair function as accumulators. 4-bit data processing instructions are executed mainly by the a register and 8-bit data processing instructions are executed mainly by the xa register pair. for execution of bit manipulation instructions, the carry flag (cy) functions as the bit accumulator. figure 4-12. accumulator cy bit accumulator a 4-bit accumulator a 8-bit accumulator x 4.6 stack pointer (sp): 8 bits the m pd75308 has a data area which functions as the stack memory (lifo format). the 8-bit register which holds the first address information of the stack area is the stack pointer (sp). the stack area is located at addresses 000h to 0ffh of memory bank 0 irrespectively of mbe and mbs settings. the sp is decremented ahead of write (save) operation for the stack memory and is incremented after read (restore) operation from the stack memory. figures 4-14 to 4-16 show the data to be saved/restored by each stack operation. the sp sets the initial value by the 8-bit memory manipulation instruction and determines the stack area. it can also read the contents from the stack area. 0 is always set for sp0. it is recommended to set the sp initial value to 00h and to use the stack area starting with the most significant address (0ffh) of data memory bank 0. since the sp content becomes indeterminate when the reset signal is generated, initialize the sp to the desired value at the beginning of the program. example sp initialize sel mb15 ; or clr1 mbe mov xa, #00h mov sp, xa ; sp 00h figure 4-13. stack pointer format sp0 f80h sp1 sp3 sp2 sp4 sp5 sp6 sp7 address sp symbol 0 1 32 4 5 6 7 fixed to 0
67 chapter 4 internal cpu function figure 4-14. data saved/restored by stack operation ( m m m m m pd75304, 75304b) (a) data saved into stack memory stack sp ?1 sp push instruction stack pc11-pc8 pc3-pc0 pc7-pc4 call and callf instructions stack interrupt sp ?2 sp ?1 sp sp ?3 pc11-pc8 pc3-pc0 pc7-pc4 sp ?2 sp ?1 sp sp ?3 sp ?4 sp ?5 mbe 0 0 0 mbe 0 0 0 cy sk2 mbe 0 sk1 sk0 ist0 0 psw sp ?2 low-order bits of register pair high-order bits of register pair sp ?4 sp ?6 stack sp + 1 sp + 2 pop instruction stack pc11-pc8 pc3-pc0 pc7-pc4 ret and rets instructions stack reti instruction sp + 2 sp + 3 sp + 4 sp + 1 pc11-pc8 pc3-pc0 pc7-pc4 sp + 4 sp + 5 sp + 6 sp + 3 sp + 2 sp + 1 mbe mbe cy sk2 mbe 0 sk1 sk0 ist0 0 psw sp sp sp low-order bits of register pair high-order bits of register pair (b) data restored from stack memory
68 chapter 4 internal cpu function figure 4-15. data saved/restored by stack operation ( m m m m m pd75306, 75306b, 75308, 75308b, 75p308) (a) data saved into stack memory (b) data restored from stack memory stack sp ?1 sp push instruction stack pc11-pc8 pc3-pc0 pc7-pc4 call and callf instructions stack interrupt sp ?2 sp ?1 sp sp ?3 pc11-pc8 pc3-pc0 pc7-pc4 sp ?2 sp ?1 sp sp ?3 sp ?4 sp ?5 mbe 0 0 pc12 mbe 0 0 pc12 cy sk2 mbe 0 sk1 sk0 ist0 0 psw sp ?2 low-order bits of register pair high-order bits of register pair sp ?4 sp ?6 stack sp + 1 sp + 2 pop instruction stack pc11-pc8 pc3-pc0 pc7-pc4 ret and rets instructions stack reti instruction sp + 2 sp + 3 sp + 4 sp + 1 pc11-pc8 pc3-pc0 pc7-pc4 sp + 4 sp + 5 sp + 6 sp + 3 sp + 2 sp + 1 mbe pc12 mbe pc12 cy sk2 mbe 0 sk1 sk0 ist0 0 psw sp sp sp low-order bits of register pair high-order bits of register pair
69 chapter 4 internal cpu function figure 4-16. data saved/restored by stack operation ( m m m m m pd75312, 75312b, 75316, 75316b, 75p316, 75p316a and 75p316b) (a) data saved into stack memory (b) data restored from stack memory stack sp ?1 sp push instruction stack pc11-pc8 pc3-pc0 pc7-pc4 call and callf instructions stack interrupt sp ?2 sp ?1 sp sp ?3 pc11-pc8 pc3-pc0 pc7-pc4 sp ?2 sp ?1 sp sp ?3 sp ?4 sp ?5 mbe 0 pc13 pc12 mbe 0 pc13 pc12 cy sk2 mbe 0 sk1 sk0 ist0 0 psw sp ?2 low-order bits of register pair high-order bits of register pair sp ?4 sp ?6 stack sp + 1 sp + 2 pop instruction stack pc11-pc8 pc3-pc0 pc7-pc4 ret and rets instructions stack reti instruction sp + 2 sp + 3 sp + 4 sp + 1 pc11-pc8 pc3-pc0 pc7-pc4 sp + 4 sp + 5 sp + 6 sp + 3 sp + 2 sp + 1 mbe pc13 pc12 mbe pc13 pc12 cy sk2 mbe 0 sk1 sk0 ist0 0 psw sp sp sp low-order bits of register pair high-order bits of register pair
70 chapter 4 internal cpu function 4.7 program status word (psw): 8 bits the program status word (psw) is configured of various flags closely related to processor operations. the psw is mapped at addresses fb0h and fb1h in the data memory space and two bits at address fb0h can be operated by a memory manipulation instruction. figure 4-17. program status word format table 4-1. psw flag saved/restored by stack operation flag saved/restored save when call and callf instructions are executed mbe is saved when the hardware is interrupted all psw bits are saved restore when ret and rets instructions are executed mbe is restored when reti instruction is executed all psw bits are restored 0 mbe ist0 0 sk0 sk1 sk2 cy cannot be operated can be operated fb0h fb1h can be operated by a dedicated instruction symbol psw address
71 chapter 4 internal cpu function (1) carry flag (cy) the carry flag is a 1-bit flag to store overflow/underflow occurrence information during execution of carry operation instructions (addc, subc). the carry flag performs the bit accumulator function which enables to carry out boolean logic operations with the bit address specified data memory and to store the operation results. carry flag operations are carried out using a dedicated instruction irrespectively of other psw bits. the carry flag becomes indeterminate if the reset signal is generated. table 4-2. carry flag operation instructions instruction (mnemonic) carry flag operation and processing carry flag operation set1 cy cy set (1) dedicated instruction clr1 cy cy clear (0) not1 cy cy content inverse skt cy skip if cy content is 1 bit boolean instruction and1 cy, mem*.bit specified bit content is and/or/xored with cy content and or1 cy, mem*.bit the result is set in cy. xor1 cy, mem*.bit interrupt servicing when interrupt servicing another psw bit and 8 bits are saved in parallel into the stack is executed memory. reti restored in parallel with another psw from the stack memory. remark mem*.bit indicates the following three bit operation addressing modes: ? fmem.bit ? pmem.@l ? @h + mem.bit example bit 3 at address 3fh is anded with p33 and the result is set in cy. set1 cy ; cy 1 clr1 mbe ; or sel mb15 skt 3fh.3 ; skip if bit 3 at address 3fh is 1. clr1 cy ; cy 0 and1 cy, port3.3 ; cy cy ^ p33 (2) skip flags 0 to 2 (sk0 to sk2) the skip flag stores the skip state. it is automatically set/reset when the cpu executes an instruction. the user cannot directly operate the skip flag as an operand. C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C
72 chapter 4 internal cpu function (3) interrupt status flag (ist0) the interrupt status flag stores the status of processing currently being executed. (refer to table 6-3 ist0 and interrupt servicing status for details.) table 4-3. interrupt status flag instruction content ist0 status of processing being executed processing content and interrupt control 0 status 0 all interrupts acknowledge enable during normal program processing 1 status 1 all interrupts acknowledge disable during interrupt servicing when an interrupt is acknowledged, the ist0 content is saved into the stack memory as part of psw and is then set to 1 automatically and is set to 0 by the reti instruction. the interrupt status flag can be operated by the memory manipulation instruction and the status of processing being executed can be changed by program control. caution when operating this flag, make sure to disable the interrupt by executing the di instruction and enable the interrupt by executing the ei instruction after operation. (4) memory bank enable flag (mbe) this is a 1-bit flag to specify the address information generate mode for the high-order 4 bits of 12 bits of the data memory address. the mbe can be set/reset by a bit manipulation instruction irrespectively of memory bank setting. example set1 mbe ; mbe 1 clr1 mbe ; mbe 0 when the mbs is set to 1, the data memory address space is expanded and all data memory spaces become addressable. when the mbs is set to 0, the data memory address space is fixed irrespectively of mbs (refer to figure 3-2 data memory configuration and addressing range in each addressing mode ). when the reset signal is generated, the content of bit 7 at address 0 of the program memory is set and is automatically initialized. when the vectored interrupt servicing is carried out, the content of bit 7 of the corresponding vector address table is set and the mbe status in interrupt service is automatically set. mbe = 0 is usually set in interrupt servicing for use with the data area of the memory bank.
73 chapter 4 internal cpu function 4.8 bank select register (bs) memory bank select register (mbs) used for memory bank specification is mapped in the bank select register (bs). the low-order 4 bits are fixed to 0. the mbs is set by the sel mbn instruction. the bs can be saved/restored in 8-bit units in the stack area by the push bs/pop bs instruction. figure 4-18. bank select register format 0 0 0 0 mbs0 mbs1 mbs2 mbs3 mbs symbol bs 0 1 2 3 4 5 6 7 (1) memory bank select register (mbs) the mbs is a 4-bit register to store the high-order 4-bit address information of the data memory address (12 bits). the memory bank to be accessed is specified by the content of this register. three memory banks, 0, 1 and 15, can be specified. note 1 the mbs is set by the sel mbn instruction (n = 0, 1, 15). note 2 the address range for mbe and mbs setting are shown in figure 3-2. when the reset signal is generated, the mbs is initialized to 0. notes 1. on the m pd75312b, 75316b, 75p316a and 75p316b only, there are 5 banks: 0, 1, 2, 3 and 15. 2. on the m pd75312b, 75316b, 75p316a and 75p316b only, n = 0, 1, 2, 3 or 15.
74 chapter 4 internal cpu function [memo]
75 chapter 5 peripheral hardware functions chapter 5 peripheral hardware functions 5.1 digital input/output port the m pd75308 has the memory mapped i/o. all input/output ports are mapped in the data memory space. bit port outputs bp0 to bp7 at addresses 1f8h to 1ffh function as output latches. bp0 to bp7 are switched in 4-bit units by bits 6 and 7 of the display mode register (lcdm) (refer to figure 5-74. display mode register format ). bits which are not used as output latches by the bit ports at 1f8h to 1ffh are used as display memory or static ram. each address can be operated in 1-bit/4-bit units. figure 5-1. digital port data memory address ff0h ff1h ff2h ff3h ff4h ff5h ff6h ff7h p03 p13 p23 p33 p43 p53 p63 p73 address 3 p02 p12 p22 p32 p42 p52 p62 p72 2 p01 p11 p21 p31 p41 p51 p61 p71 1 p00 p10 p20 p30 p40 p50 p60 p70 0 port 0 port 1 port 2 port 3 port 4 port 5 port 6 port 7 1f8h 1f9h 1fah 1fbh 1fch 1fdh 1feh 1ffh ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bp0 bp1 bp2 bp3 bp4 bp5 bp6 bp7 remark some addresses can be used as static ram. table 5-2 lists input/output port manipulation instructions. various types of control operations, including 4-bit input/output, 8-bit input/output and bit operations, can be carried out for port4 through port7. bp0 to bp7 are bitwise output ports.
76 chapter 5 peripheral hardware functions examples 1. depending on the results of p13 status test, different values are output to ports 4 and 5. skt port1. 3 ; skip if bit 3 of port 1 is 1. mov xa, #18h ; xa 18h mov xa, #14h ; xa 14h sel mb15 ; or clr1 mbe out port4, xa ; port 5, 4 xa 2. set1 port4. @l ; l register specified bit of ports 4 to 7 is set (1) 3. 1 is output to bp0. set1 mbe sel mb1 ; memory bank 1 is selected. set1 bp0 ; bp0 1
77 chapter 5 peripheral hardware functions 5.1.1 types, features and configurations of digital input/output ports the different kinds of digital input/output ports are shown in table 5-1. the configuration of each port is shown in figures 5-2 through 5-5. table 5-1. digital port types and features port function operation/features remarks (pin names) port0 4-bit input can always be read or tested regardless of dual- pins have dual purpose as int4, (p00 to p03) purpose pin operating mode. sck, so/sb0, and si/sb1. port1 pins have dual purpose as (p10 to p13) int0 to int2, and ti0. port2 4-bit input/output input or output mode can be set in 4-bit units. pins have dual purpose as pto0, (p20 to p23) pcl, and buz. port3 note 1 input or output can be set in 1-bit/4-bit units. pins have dual purpose as lcdcl, (p30 to p33) sync, and md0 to md3 note 2 port4 note 1 4-bit input/output input or output can be 8-bit data input/output bit-wise specification of on-chip (p40 to p43) (n-ch open-drain, set in 4-bit units. is possible using ports pull-up resistor is possible. port5 note 1 10 v withstand 4 and 5 as a pair. (p50 to p53) voltage) port6 4-bit input/output input or output can be 8-bit data input/output pins have dual purpose as kr0 (p60 to p63) set in 1-bit/4-bit units. is possible using ports to kr3. port7 input or output can be 6 and 7 as a pair. pins have dual purpose as kr4 (p70 to p73) set in 4-bit units. to kr7. bp0 to bp7 1-bit output bit-wise data output. switchable by software to drive capability is very small. lcd drive segment outputs s24 to s31. for cmos load drive. notes 1. direct led drive is possible. 2. port3 also functions as pins md0 through md3 on the m pd75p308, 75p316, 75p316a and 75p316b only. p10 also serves as the external vector interrupt input pin, functioning an input with a noise eliminator (refer to 6.3 v arious hard ware t ypes of interrupt control circuit for details). bp0 to bp7 also serve as lcd drive segment outputs (s24 to s31) and the outputs are switched in 4 or 8 units by bits 6 and 7 of the display mode register (lcdm). bp0 to bp7 are bitwise output ports from which bit 0 data at addresses 1f8h to 1ffh of the display data memory is output (refer to 5.7.5 display data memory ). bp0 to bp7 have an extremely low drive capability as compared to that of other ports. thus, use them to drive the cmos load. when the reset signal is generated, the output latches of ports 2 to 7 are cleared, the output buffer is turned off and the input mode is set.
78 chapter 5 peripheral hardware functions figure 5-2. configuration of ports 0 and 1 p13/ti0 p12/int2 p11/int1 p10/int0 input buffer having hysteresis characteristics noise eliminator int0 int1 int2 ti0 input buffer p03/si/sb1 p02/so/sb0 p01/sck p00/int4 int4 sck si selector csim internal bus 8 selector input buffer p01 output latch so sck bit 0 of poga p-ch v dd pull-up resistor output buffer capable of switching between push-pull output and n-ch open drain output bit 1 of poga p-ch pull-up resistor v dd f or f x /64 internal
79 chapter 5 peripheral hardware functions figure 5-3. configuration of ports 3n and 6n (n = 0 to 3) figure 5-4. configuration of ports 2 and 7 corresponding bit of port mode register group a internal bus output latch pmmn output buffer m p x pmmn = 1 pmmn = 0 input buffer m = 3, 6 n = 0e3 pmn bit m of poga v dd p-ch pull-up resistor input buffer with hysteresis characteristics note key interrupt note note port 6n only internal bus pm0 pm1 pm2 pm3 output latch corresponding bit of port mode register group b (m = 2, 7) output buffer pmm = 1 pmm = 0 mpx input buffer pmm bit m of poga pull-up resistor v dd input buffer with hysteresis characteristics note key interrupt note p-ch note port 7n only
80 chapter 5 peripheral hardware functions figure 5-5. configuration of ports 4 and 5 internal bus pm0 pm1 pm2 pm3 output latch corresponding bit of port mode register group b (m = 4, 5) open-drain output buffer pmm = 1 pmm = 0 mpx input buffer pmm v dd (mask option) pull-up resistor
81 chapter 5 peripheral hardware functions 5.1.2 input/output mode setting the input/output mode of each input/output port is set using the port mode register as shown in figure 5-6. input/output can be specified bitwise for ports 3 and 6 by port mode register group a (pmga). input/output can be specified in 4-bit units for ports 2, 4, 5 and 7 by pmgb. each port functions as an input or output port when the port mode register bit is 0 or 1, respectively. when the output mode is selected by setting the port mode register, the output latch content is simultaneously generated to the output pin. therefore, the output latch content must be rewritten as the necessary value before the output mode is set. port mode register groups a and b are set by an 8-bit memory manipulation instruction. when the reset signal is generated all bits of each port mode register are cleared to 0. as a result, the output buffer is turned off and all ports are set to the input mode. example p30, p31, p62 and p63 are used as input pins and p32, p33, p60 and p61 are used as output pins. clr1 mbe ; or sel mb15 mov xa, #3ch mov pmga, xa figure 5-6. port mode register format pm63 pm62 pm61 pm60 pm33 pm32 pm31 pm30 76543210 pmga symbol fe8h address port mode register group a pmga 0 1 pm3n pm6n input mode (output buffer off) output mode (output buffer on) p3n, p6n pin input/output specification (n = 0 to 3) symbol pm7 pm5 pm4 pm3 76543210 pmgb symbol fech address port mode register group b pmgb 0 1 input mode (output buffer off) output mode (output buffer on) port n input/output specification (n = 2, 4, 5, 7) symbol pmn ? can be 0 or 1.
82 chapter 5 peripheral hardware functions 5.1.3 digital input/output port manipulation instruction all on-chip input/output ports of the m pd75308 are mapped in the data memory space and thus all data memory manipulation instructions can be applied. table 5-2 describes instructions seemingly effective for input/output pin operations among data memory manipulation instructions, together with their application ranges. (1) bit manipulation instructions specific address bit direct addressing (fmem. bit) and specific address bit register indirect addressing (pmem. @l) can be carried out for digital input/output ports port0 to port7 and thus port bit manipulations are enabled for them irrespectively of mbe and mbs settings. example p50 is ored with p41 and the result is output to p61. set1 cy ; cy 1 and1 cy, port5. 0 ; cy cy ^ p50 or1 cy, port4. 1 ; cy cy | p41 skt cy br clrp set1 port6. 1 ; p61 1 clrp: clr1 port6. 1 ; p61 0 (2) 4-bit manipulation instruction in addition to the in/out instruction, all 4-bit memory manipulation instructions, including mov, xch, adds and incs, can be used. memory bank 15 must be selected before each 4-bit memory manipulation instruction is executed. examples 1. the accumulator content is output to port 3. sel mb15 ; or clr1 mbe out port3, a 2. data output at port 5 plus the accumulator value are output. set1 mbe sel mb15 mov hl, #port5 adds a, @hl ; a a + port5 nop mov @hl, a ; port5 a 3. whether port 4 data is larger than the accumulator value is tested. set1 mbe sel mb15 mov hl, #port4 subs a, @hl ; a < port4 br no ; no ; yes . . . . .
83 chapter 5 peripheral hardware functions (3) 8-bit manipulation instruction for ports 4 and 5 and ports 6 and 7 which can be used for 8-bit manipulation as a pair, mov/xch/ske instructions can be used in addition to the in/out instructions. memory bank 15 must be selected beforehand as with 4-bit manipulation. example the bc register pair data is output to the output port specified by the 8-bit data input from ports 4 and 5. set1 mbe sel mb15 in xa, port4 ; xa ports 5 and 4 mov hl, xa ; hl xa mov xa, bc ; xa bc mov @hl, xa ; port (l) xa
84 chapter 5 peripheral hardware functions table 5-2. list of input/output pin manipulation instructions port port port port port port port port bit port 01234567 0 C 7 in a, portn note 1 mov a, men note 3, 4 in xa, portn note 1 CC C out portn, a note 1 CC mov men, a note 3, 4 out portn.xa note 1 CC C set1 portn.bit C C set1 bpn note 3 set1 portn.@l note 2 CC C clr1 portn.bit C C clr1 bpn note 3 clr1 portn.@l note 2 CC C skt portn.bit skt bpn note 3 skt portn.@l note 2 C skf portn.bit skf bpn note 3 skf portn.@l note 2 C and1 cy, portn.bit and1 cy, @h+bpn note 3, 5 and1 cy, portn.@l note 2 C or1 cy, portn.bit or1 cy, @h+bpn note 3, 5 or1 cy, portn.@l note 2 C xor1 cy, portn.bit xor1 cy, @h+bpn note 3, 5 xor1 cy, portn.@l note 2 notes 1. mbe = 0 or (mbe = 1, mbs = 15) must be set before execution. 2. the low-order 2 bits of the address and the bit address are indirectly specified with the l register. 3. (mbe = 1, mbs = 1) must be set before execution. 4. bit 0 of accumulator a corresponds to bpn. 5. fh is written into the h register.
85 chapter 5 peripheral hardware functions 5.1.4 digital input/output port operations when a data memory manipulation instruction is carried out for the digital input/output port, port and pin operations vary depending on the input/output mode setting (refer to table 5-3 ). this is because, as is clear from the input/output port configuration, data fetched into the internal bus becomes data of each pin in the input mode and data of the output latch in the output mode. (1) operations in the input mode when a test instruction such as skt or a 4/8-bit instruction which fetches port data into the internal bus (in, out, arithmetic, and comparison instructions) is executed, data of each pin is operated. when an instruction (out and mov instructions) to transfer the accumulator content to the port in 4/8- bit units is executed, the accumulator data is latched into the output latch with the output buffer set to off. when the xch instruction is executed, each pin data is input to the accumulator and accumulator data is latched into the output latch with the output buffer set to off. when the incs instruction is executed, one is added to each pin data (4 bits) and the sum is latched into the output latch with the output buffer set to off. when the set1, clr1 or sktclr instruction intended to rewrite the data memory bitwise is executed, the output latch of the specified bit can be rewritten as specified by the instruction but the contents of the output latches of other bits become indeterminate. (2) operations in the output mode when the test instruction or an instruction to fetch port data into the internal bus in 4/8-bit units, the output latch content is operated. when an instruction to transfer the accumulator content in 4/8-bit units is executed, the output latch data is rewritten and the accumulator content is immediately output from the pin. when the xch instruction is executed, the output latch content is transferred to the accumulator. the accumulator content is latched into the output latch and is output from the pin. when the incs instruction is executed, the output latch content added by one is latched into the output latch and is output from the pin. when a bit output instruction is executed, the specified output latch bit is rewritten and is output from the pin.
86 chapter 5 peripheral hardware functions table 5-3. input/output port and pin operations instruction to be executed port and pin operations input mode output mode skt pin data test output latch data test skf and1 cy, pin data and cy operation output latch data and cy operation or1 cy, xor1 cy, in a, portn pin data transfer to the accumulator output latch data transfer to the accumulator in xa, portn mov a, @hl mov xa, @hl adds a, @hl pin data and accumulator operation output latch data and accumulator operation addc a, @hl subs a, @hl subc a, @hl and a, @hl or a, @hl xor a, @hl ske a, @hl pin data and accumulator comparison output latch data and accumulator ske xa, @hl comparison out portn, a accumulator data transfer to the output latch accumulator data transfer to the output latch out portn, xa (with the output buffer set to off) and output from the pin mov @hl, a mov @hl, xa xch a, portn pin data transfer to the accumulator and data exchange between output latch and xch xa, portn accumulator data transfer to the output latch accumulator xch a, @hl (with the output buffer set to off) xch xa, @hl incs portn pin data added by one and latched into the output latch content added by one incs @hl output latch set1 the output latch of the specified bit is output pin status is changed according to an clr1 rewritten as specified by an instruction and instruction. sktclr the output latches of all other bits remain unchanged. : indicates two addressing modes portn. bit and portn.@l. 1 1 1 1 1 1 1 1 1
87 chapter 5 peripheral hardware functions 5.1.5 integration of pull-up resistor a pull-up resistor can be integrated at each port pin of the m pd75308 (except p00 and bp0 to bp7). pull-up resistor integration can be specified for pins by using the software of mask option. the specification method for each port pin is shown in table 5-4. specification by software is performed based on the format shown in figure 5-7. specification of the internal pull-up resistor for ports 3 and 6 is effective for pins specified as in the input mode. for pins specified as in the output mode, specification of the internal pull-up register is not possible, irrespective of poga setting. table 5-4. specification of pull-up resistor integration port (pin name) specification of pull-up resistor integration poga bit port 0 (p01 to p03) note 3-bit unit specification of integration using software bit 0 port 1 (p10 to p13) 4-bit unit specification of integration using software bit 1 port 2 (p20 to p23) bit 2 port 3 (p30 to p33) bit 3 port 6 (p60 to p63) bit 6 port 7 (p70 to p73) bit 7 port 4 (p40 to p43) bitwise specification of integration using mask option C port 5 (p50 to p53) note no pull-up resistors can be integrated at p00 pin. remark pull-up resistors by mask option are not provided for m pd75p308, 75p316, 75p316a and 75p316b. figure 5-7. pull-up resistor specification register group a specification 0 no integration of pull-up resistor 1 integration of pull-up resistor 7 6 5 4 3 2 1 0 po0 po1 po3 po2 ? ? po6 po7 address poga fdch symbol port 0 (p01 to p03) port 1 (p10 to p13) port 2 (p20 to p23) port 3 (p30 to p33) port 6 (p60 to p63) port 7 (p70 to p73)
88 chapter 5 peripheral hardware functions 5.1.6 input/output timing of digital input/output port figure 5-8 shows the timing of data output to the output latch and the timing of pin data or output latch data fetch into the internal bus. figure 5-9 shows the on timing when pull-up resistor integration is specified by software. figure 5-8. input/output timing of digital input/output port (a) data fetch by 1-machine cycle instruction (d) data latch by 2-machine cycle instruction (c) data latch by 1-machine cycle instruction (b) data fetch by 2-machine cycle instruction instruction execution output latch (output pin) manipulation instruction f 0 f 1 instruction execution manipulation instruction f 3 f 0 f 1 output latch (output pin) instruction execution input timing 2 machine cycles manipulation instruction 1 machine cycle manipulation instruction instruction execution input timing
89 chapter 5 peripheral hardware functions figure 5-9. pull-up resistor on timing by software instruction execution poga pull-up resistor set instruction 2 machine cycles (mov, poga, xa)
90 chapter 5 peripheral hardware functions 5.2 clock generator circuit the clock generator circuit supplies the cpu and peripheral hardware devices with various clocks and controls the cpu operating mode. 5.2.1 clock generator circuit configuration the clock generator circuit is configured as shown in figure 5-10. figure 5-10. clock generator circuit block diagram wait release signal from bt internal bus scc0 scc3 pcc0 pcc1 halt note pcc3 pcc stop note pcc2 pcc2, pcc3 clear xt1 xt2 subsystem clock oscillator circuit x1 x2 main system clock oscillator circuit oscillation stop selector 1/8 to 1/4096 frequency divider lcd controller/driver watch timer . basic interval timer (bt) . timer/event counter . serial interface . watch timer . lcd controller/driver . int0 noise eliminator . clock output circuit s rq q r s stop f/f halt f/f 1/4 frequency divider . cpu . int0 noise eliminator . clock output circuit f standby release signal from the interrupt control circuit reset signal 4 scc selector 1/2 1/16 v dd v dd f x f xt wm. 3 note instruction execution remarks 1. f x = main system clock frequency 2. f xt = subsystem clock frequency 3. f = cpu clock 4. pcc: processor clock control resistor 5. scc: system clock control resistor 6. 1 clock cycle of f (t cy ) is 1 machine cycle.
91 chapter 5 peripheral hardware functions 5.2.2 clock generator circuit functions and operations the clock generator circuit generates various clocks and controls the cpu operation mode including the standby mode, etc. ? main system clock f x ? subsystem clock f xt ? cpu clock f ? clock for the peripheral hardware clock generator circuit operations are determined as follows by the processor clock control register (pcc) and system clock control register (scc). (a) when reset signal is generated, the lowest speed mode (15.3 m s: when operated at 4.19 mhz) is selected (pcc = 0, scc = 0) (b) with the main system clock selected, 3-level cpu clocks can be selected by pcc setting (0.95 m s, 1.91 m s, 15.3 m s: when operated at 4.19 mhz). (c) with the main system clock selected, two standby modes, stop mode and halt mode, can be used. (d) with the subsystem clock selected by scc, this circuit can operate at extremely low speeds with low current consumption (122 m s: when operated at 32.768 khz). in this case, the pcc set value has no effects on the cpu clock. (e) with the subsystem clock selected, main system clock oscillation can be stopped by scc. this circuit can be used in the halt mode but it cannot be used in the stop mode (subsystem clock oscillation cannot be stopped). (f) clocks for the peripheral hardware are supplied by dividing the main system clock. subsystem clocks can be directly supplied to the watch timer only. thus, the clock function, the function of the lcd controller operated by clocks from the watch timer and the buzzer output function can be continued even in the standby mode. (g) when the subsystem clock is selected, the watch timer and the lcd controller can continue to operate normally. all other hardware devices operate by main system clocks and thus cannot be used if the main system clock is stopped.
92 chapter 5 peripheral hardware functions (1) processor clock control register (pcc) the pcc is a 4-bit register which selects cpu clock f with low-order 2 bits and executes cpu operating mode control with high-order 2 bits (refer to figure 5-11 ). when bit 3 or 2 is set (1), the standby mode is set. when the bit is released by the standby release signal, the bit is automatically cleared and the normal operating mode is set (refer to chapter 7 standby function for details). the low-order 2 bits of the pcc are set by the 4-bit memory manipulation instruction (with the low-order 2 bits set to 0). bits 3 and 2 are set (1) by the stop and halt instructions, respectively. the stop and halt instructions can always be executed irrespectively of mbe content. the cpu clock can only be selected when the circuit is in operation with the main system clock. when the circuits operated with the subsystem clock, the low-order 2 bits of the pcc are invalidated and are fixed to f xt /4. the stop instruction is also enabled only when the circuit is in operation with the main system clock. examples 1. the machine cycle is set to 0.95 m s (4.19 mhz). sel mb15 mov a, #0011b mov pcc, a 2. the machine cycle is set to 1.63 m s (f x = 4.91 mhz) sel mb15 mov a, #0010b mov pcc, a 3. the stop mode is set. (make sure to write the nop instruction after the stop or halt instruction.) stop nop when the reset signal is generated, the pcc is cleared to 0.
93 chapter 5 peripheral hardware functions figure 5-11. processor clock control register format 3 2 1 0 cpu clock selection bit pcc0 pcc1 pcc2 pcc3 address pcc fb3h symbol when f x 4.19 mhz cpu clock frequency 1-machine cycle 0 f = f x/ 64 (65.5 khz) 0 15.3 s m 0 setting prohibited 1 ? 1 f = f x /8 (524 khz) 0 1.91 s m 1 f = f x /4 (1.05 mhz) 1 0.95 s m cpu clock frequency 1-machine cycle f = f xt /4 (8.192 khz) 122 s m when 4.19 mhz < f x 5.0 mhz cpu clock frequency 1-machine cycle 0 f = f x /64 (76.7 khz) 0 13 s m 0 setting prohibited 1 ? 1 f = f x /8 (614 khz) 0 1.63 s m 1 setting prohibited 1 ? cpu clock frequency 1-machine cycle f = f xt /4 (8.192 khz) 122 s m cpu operating mode control bit 0 normal operating mode 0 0 halt mode 1 1 stop mode 0 1 setting prohibited 1 scc = 0 when f x 4.19 mhz in parentheses scc = 1 when f xt 32.768 khz in parentheses f x : main system clock oscillator output frequency f xt : subsystem clock oscillator output frequency scc = 0 when f x 4.19 mhz in parentheses scc = 1 when f xt 32.768 khz in parentheses caution when using a value of f x such that 4.19 mhz < f x - 5 mhz, if the fastest mode: f f f f f = f x /4 (pcc1, pcc0 = 11) is set as cpu clock frequency, 1 machine cycle becomes less than 0.95 m m m m m s. thus the min. standard value 0.95 m m m m m s cannot be observed. therefore, in this case, pcc1, pcc0 = 11 cannot be set, set pcc1, pcc0 = 10 or 00. consequently, the combination of f x = 4.19 mhz, pcc1, pcc0 = 11 is the selection for the maximum cpu clock speed (1 machine cycle = 0.95 m m m m m s).
94 chapter 5 peripheral hardware functions (2) system clock control register (scc) the scc is a 4-bit register which selects the cpu clock f with the least significant bit and controls main system clock oscillation stop with the most significant bit (refer to figure 5-12 ). although scc.0 and scc.3 are located at the same data memory address, both bits cannot be changed simultaneously. thus, scc.0 and scc.3 are set by bit manipulation instructions. they are always ready for bit manipulation irrespectively of mbe content. main system clock oscillation stop by setting scc.3 is only enabled when the circuit is in operation with the subsystem clock. while the circuit is operating with the main system clock, oscillation is stopped by the stop instruction. when the reset signal is generated, the scc is cleared to 0. figure 5-12. system clock control register format cautions 1. it takes a maximum of 1/f xt to change the system clock. thus, to stop main system clock oscillation, set scc.3 following the lapse of a time longer than the machine cycle indicated in table 5-5 after the subsystem clock has been changed. 2. if oscillation is stopped by setting scc.3 when the circuit is in operation with the main system clock, the normal stop mode is not set. 3. when 1 is set to scc.3, x1 input is internally short-circuited (ground potential) to prevent the crystal oscillator circuit block from leaking. thus, when using an external clock as the main system clock, 1 should not be set to scc.3. 3210 scc3 cpu clock selection scc0 e e scc3 address scc fb7h symbol scc0 main system clock oscillation 0 main system clock 0 oscillation possible 0 subsystem clock 1 1 setting prohibited 0 1 subsystem clock 1 oscillation stop
95 chapter 5 peripheral hardware functions (3) system clock oscillator circuit the main system clock oscillator circuit oscillates with the crystal resonator (4.194304 mhz typ.) or the ceramic resonator connected to the x1 and x2 pins. external clocks can also be input to this circuit. in this case, apply the clock signal to the x1 pin and the inverse signal to the x2 pin. figure 5-13. externally mounted circuit for the main system clock oscillator circuit (a) crystal/ceramic oscillation (b) external clock x1 x2 crystal resonator or ceramic resonator pd75308 m pd75308 m x1 x2 v dd v dd external clock caution while an external clock is being input, the stop mode cannot be set. this is because x1 pin is short-circuited to v ss in the stop mode. the subsystem clock oscillator circuit oscillates with the crystal resonator (32.768 khz typ.) connected to the xt1 and xt2 pins. an external clock can be input. in this case, apply the clock signal to the xt1 pin and the inverted signal should be input to the xt2 pin. the xt1 pin status can be tested by checking bit 3 of the watch mode register (wm). figure 5-14. externally mounted circuit for subsystem clock oscillator circuit (a) crystal oscillator (b) external clock xt1 xt2 32.768 khz pd75308 m pd75308 m xt1 xt2 v dd v dd external clock
96 chapter 5 peripheral hardware functions cautions 1. when using the main system clock or subsystem clock oscillator, wiring enclosed by dotted line in figures 5-13 and 5-14 should be made as follows to avert the adverse effect of wiring capacitance. ? wires should be kept as short as possible. ? do not cross other signal lines. do not route wires close to a fluctuating high- current line. ? oscillation capacitor connection points should be always at the same electric potential as v dd . do not connect to a high-current power supply pattern. ? do not take a signal from the oscillator. note that the subsystem clock oscillator has small amplification in order to keep power consumption low. figure 5-15 shows an example of an incorrect resonator connection circuit. figure 5-15. example of incorrect resonator connection circuit (1/2) (a) excessively long connection circuit wires (b) crossed signal lines C C C C C C C C C C C C pd75308 m x1 x2 v dd v dd x1 x2 v dd v dd portn pd75308 m remark when the subsystem clock is used, read xt1 and xt2 in place of x1 and x2. also, a resistor should be inserted in series on xt2 side.
97 chapter 5 peripheral hardware functions figure 5-15. example of incorrect resonator connection circuit (2/2) (c) fluctuating high current is close to (d) current is flowing in the oscillator power the signal line supply line. (a, b and c electric potentials fluctuate) high current x1 x2 v dd v dd pd75308 m x1 x2 v dd portn c b a v dd pd75308 m high current (e) signal is taken out. (f) main system clock and subsystem clock signal lines are close and parallel to each other. x1 x2 v dd v dd pd75308 m remark when the subsystem clock is used, read xt1 and xt2 in place of x1 and x2. also, a resistor should be inserted in series on xt2 side. xt1 xt2 v dd v dd x1 x2 xt2 and x1 are wired in parallel. (see caution 2 for remedy.) pd75308 m
98 chapter 5 peripheral hardware functions cautions 2. in figure 5-15 (f), xt2 and x1 are wired in parallel. thus, crosstalk noise of x1 affects xt2, resulting in misoperation. to avoid this, it is recommended that xt2 and x1 should not be wired in parallel and that the nc pin between xt2 and x1 should be connected to v dd . in the m m m m m pd75312b/75316b, nc pin is not used, but ic pin. therefore, be sure to connect the pin to v dd directly. xt1 xt2 v dd v dd x1 x2 pd75308 m (ic) nc (4) frequency divider the frequency divider divides the main system clock oscillator output (f x ) to generate various kinds of clocks. (5) when subsystem clock is not used unless the subsystem clock need be used for power dissipation and watch operations, deal with xt1 and xt2 pins as follows. xt1 : connect to v ss and v dd . xt2 : leave unconnected however, in this situation, when the main system clock stops, a little leak current is generated from a feedback resistor in subsystem clock oscillator. this feedback resistor can be removed by mask option specification in order to prevent this leak current. in this case, also deal with xt1 and xt2 pins in the same way as above. (the mask option can be specified in ordering.)
99 chapter 5 peripheral hardware functions 5.2.3 system clock and cpu clock setting (1) time required for switching between system clock and cpu clock the system clock can be switched to the cpu clock or vice versa the low-order 2 bits of pcc and the least significant bit of scc. this switching is not executed just after the register is rewritten. the previous clock remains in operation during the specified machine cycle. thus, to stop main system clock oscillation, it is necessary to execute the stop instruction or set scc.3. table 5-5. maximum time required for system clock/cpu clock switching set value bef ore switching set v alue after switching scc pcc pcc scc0 pcc1 pcc0 scc0 pcc1 pcc0 scc0 pcc1 pcc0 scc0 pcc1 pcc0 0100000100111xx f x machine cycle 0 0 0 1-machine cycle 1-machine cycle 64 f xt (2-machine cycle) f x machine cycle 1 0 8-machine cycle 8-machine cycle 8 f xt (16-machine cycle) f x machine cycle 1 1 16-machine cycle 16-machine cycle 4 f xt (32-machine cycle) 1 x x 1-machine cycle 1-machine cycle 1-machine cycle when f x = 4.19 mhz and f xt = 32.768 khz in parentheses x: dont care caution the values of f x and f xt vary according to conditions such as variations in the resonator ambient temperature and load capacitance capacity. in particular, if f x is higher than the nomial value or f xt is lower than the nomial value, the machine cycles given by the expressions f x /64f xt , f x /8f xt and f x /4f xt in the table are greater than the machine cycles given by the nomial values of f x and f xt . therefore, when setting the wait time required for system clock/cpu clock switchover, this should be made longer than the number of machine cycles given by the nominal values of f x and f xt . remark cpu clock f is a clock supplied to the internal cpu of the m pd75308. the inverse of the clock is the minimum instruction time (defined as 1-machine cycle in this manual).
100 chapter 5 peripheral hardware functions (2) system clock/cpu clock switching procedure the system clock/cpu clock switching procedure is described in accordance with figure 5-16. figure 5-16. system clock/cpu clock switching 1 when the reset signal is generated after the wait time (31.3 ms: when operated at 4.19 mhz) securing oscillation stabilization, the cpu starts operating at the lowest speed (15.3 m s: when operated at 4.19 mhz) of the main system clock. 2 after a sufficient time has passed for the v dd pin voltage to increase up to a value enabling the highest speed operation, the pcc is rewritten and the cpu operates at the highest speed. 3 if the turning off of the commercial power supply is detected from an interrupt (which int4 can be effectively applied), scc.0 is set and is operated with the subsystem clock (the subsystem clock oscillation should be started). after the lapse of the time (32-machine cycle) required for the clock to be switched to the subsystem clock, scc.3 is set and the main system clock oscillation is stopped. 4 if the recovery of the commercial power supply is detected from an interrupt, scc.3 is cleared and main system clock oscillation is started. after the lapse of the time required for oscillation to stabilize, scc.0 is cleared and the cpu operates at the highest speed. 0.95 s on off commercial power supply v dd pin voltage reset signal system clock cpu clock internal reset operation f x = 4.19 mhz f xt = 32.768 khz f x wait (31.3 ms) f x f xt f x 15.3 s mm 122 s m 0.95 s m ( )
101 chapter 5 peripheral hardware functions 5.2.4 clock output circuit (1) clock output circuit configuration the clock output circuit is configured as shown in figure 5-17. (2) clock output circuit functions the clock output circuit generates clock pulses from the p22/pcl pin. it is used to generate remote controlled outputs or to supply the peripheral lsi with clock pulses. the following procedure is used to generate clock pulses. (a) the clock output frequency is selected. clock output is disabled. (b) 0 is written to the p22 output latch. (c) port 2 input/output mode is set to output. (d) clock output is enabled. figure 5-17. clock output circuit configuration from clock generator circuit f fx/2 3 fx/2 4 fx/2 6 selector clom3 clom1 clom0 clom 0 p22 output latch port2.2 4 internal bus port 2 input/ output mode specify bit pmgb bit 2 output buffer pcl/p22 remark when clock output enable/disable is switched, pulses having short widths are not output.
102 chapter 5 peripheral hardware functions (3) clock output mode register (clom) the clom is a 4-bit register to control clock output. it is set by the 4-bit memory manipulation instruction. it cannot be read. example cpu clock f is output from the pcl/p22 pin. sel mb15 ; or clr1 mbe mov a, #1000b mov clom, a when the reset signal is generated, the clom is cleared to 0 and clock output is disabled. figure 5-18. clock output mode register format 32 address 10 0 f output note (1.05 mhz, 524 khz, 65.5 khz) clom clom0 fd0h clom1 clom3 0 symbol f x = 4.19 mhz in parentheses 0 0 f x /2 3 output (524 khz) 1 1 f x /2 4 output (262 khz) 0 1 f x /2 6 output (65.5 khz) 1 clock output frequency select bit 0 output disable clock output enable/disable bit 1 output enable note f is a cpu clock to be selected by pcc. caution make sure to write 0 for bit 2 of clom.
103 chapter 5 peripheral hardware functions (4) example of remote controlled output application the clock output function of the m pd75308 can be applied to remote controlled output. the remote controlled output carrier frequency is selected by the clock frequency select bit of the clock output mode register. pulse output is enabled or disabled by controlling the clock output enable/disable bit using the software. when clock output enable/disable is switched, pulses having small widths are not output. figure 5-19. remote controlled output application example clom. 3 pcl pin output
104 chapter 5 peripheral hardware functions 5.3 basic interval timer the m pd75308 is equipped with an 8-bit basic interval timer and has the following functions. (a) reference timer generation (4 time intervals) (b) selection and count of wait time upon release of the standby mode (c) count content read the basic interval timer can also be used as a watchdog timer to detect a program overrun. 5.3.1 basic interval timer configuration the basic interval timer is configured as shown in figure 5-20. figure 5-20. basic interval timer configuration remark * indicates instruction execution. fx/2 5 fx/2 7 fx/2 9 fx/2 12 mpx from clock generator circuit btm3 btm2 btm1 btm0 3 4 basic interval timer (8-bit frequency divider) internal bus 8 btm set1* bt bt interrupt request flag clear wait release signal upon release of standby mode clear vectored interrupt request signal irqbt set
105 chapter 5 peripheral hardware functions 5.3.2 basic interval timer mode register (btm) the btm is a 4-bit register to control basic interval timer operations. it is set by a 4-bit memory manipulation instruction. bit 3 can be set independently by a bit manipulation instruction. examples 1. the interrupt generate interval is set to 1.95 ms (4.19 mhz). sel mb15 ; or clr1 mbe mov a, #1111b mov btm, a ; btm 1111b 2. bt and irqbt are cleared (watchdog timer application) sel mb15 ; or clr1 mbe set1 btm.3 ; btm bit 3 is set (1). when bit 3 is set (1), the basic interval timer content and the basic interval timer interrupt request flag (irqbt) are simultaneously cleared (basic interval timer start). when the reset signal is generated, the basic interval timer content is cleared to 0 and the interrupt request signal generate interval time is set to the maximum value. figure 5-21. basic interval timer mode register format 3210 btm0 btm1 btm2 btm3 address btm f85h symbol input clock specification f x /2 12 (1.02 khz) 0 f x /2 9 (8.18 khz) 1 1 f x /2 7 (32.768 khz) 0 1 f x /2 5 (131 khz) 1 all other cases setting prohibited interrupt interval time (wait time upon standby mode release) basic interval timer start control bit the basic interval timer is started (counter and interrupt request flag clear) by writing "1". when the operation starts, the basic interval timer is reset (0). 1 1 1 00 0 2 20 /f x (250 ms) 2 17 /f x (31.3 ms) 2 15 /f x (7.82 ms) 2 13 /f x (1.95 ms) e f x = 4.19 mhz in parentheses
106 chapter 5 peripheral hardware functions 5.3.3 basic interval timer operations the basic interval timer (bt) is incremented by a clock from the clock generator circuit. if the bt overflows, the interrupt request flag (irqbt) is set. the counting operation of the bt cannot be stopped. four interrupt generate intervals are available by btm setting (refer to figure 5-21 ). the bt and the irqbt can be cleared by setting btm bit 3 to (1) (interval timer start instruction). the count status of the basic interval timer (bt) can be read by an 8-bit manipulation instruction. data write operations are not permitted. caution when reading the basic interval timer count content, execute the read instruction twice to prevent unstable data from being read during count update, and compare two read results. if the two values are almost equal, use the 2nd read result. if they differ considerably from each other, carry out the instruction executions again. example bt count content read sel mb15 mov hl, #bt ; bt address set to hl loop: mov xa, @hl ; 1st read xch xa, bc ; 2nd read mov xa, @hl ske xa, bc br loop the wait function is available to stop cpu operation until the basic interval timer overflows. this function enables to establish the system clock oscillation stabilizing time upon stop mode release. the wait time after reset signal generation is fixed. when releasing the stop mode upon generation of an interrupt, the same wait time as the interval time described in figure 5-21 can be selected by btm setting. set the btm before setting the stop mode (refer to chapter 7 standby function for details).
107 chapter 5 peripheral hardware functions 5.3.4 basic interval timer application examples examples 1. basic interval timer interrupt is enabled and the interrupt generate interval is set to 1.95 ms (at 4.19 mhz operation). sel mb15 ; or clr1 mbe mov a, #1111b mov btm, a ; set and start ei ; interrupt enabled ei iebt ; bt interrupt enabled 2. watchdog timer application the program is divided into several modules which terminate processing with the bt set time, and bt and irqbt are cleared at the end of each module. if an interrupt is generated, an overrun is judged to have occurred. sel mb15 mov a, #1101b ; interval set to 7.8 ms initialization mov btm, a ; set and start ei ei iebt module 1 sel set1 mb15; or clr1 mbe btm. 3 processing completed within 7.8 ms module 2 sel set1 mb15; or clr1 mbe btm. 3 processing completed within 7.8 ms 3. wait time for releasing the stop mode upon interrupt generation is set to 7.8 ms. sel mb15 ; or clr1 mbe mov a, #1101b mov btm, a ; btm 1101b stop ; stop mode set nop
108 chapter 5 peripheral hardware functions 4. the high level width of a pulse to be input to the int4 interrupt (both edge detect) is set. (pulse width should be less than the bt set value. the bt set value should be 7.8 ms or more.) loop: mov xa, bt ; 1st read mov bc, xa ; data store mov xa, bt ; 2nd read ske a, c br loop mov a, x ske a, b br loop skt port0.0 ; p00 = 1? br aa ; no mov xa, bc ; data store in the data memory mov buff, xa clr1 flag ; data attached flag clear reti aa: mov hl, #buff mov a, c subc a, @hl incs l mov c, a mov a, b subc a, @hl mov b, a mov xa, bc mov buff, xa ; data store set1 flag ; data attached flag set reti
109 chapter 5 peripheral hardware functions 5.4 watch timer the m pd75308 is equipped with a one-channel watch timer which performs the following functions. (a) sets the test flag (irqw) at 0.5 sec time intervals. can release the standby mode by irqw. (b) can set the 0.5 sec interval by either the main system clock or the subsystem clock. (c) the time interval can be multiplied by 128 (to 3.91 ms) in the fast mode so that program debugging and inspection can be carried out efficiently. (d) can generate the fixed frequency (2.048 khz) to p23/buz pin so that a buzzer sound can be generated or the system clock oscillation frequency can be trimmed. (e) because the dividing circuit can be cleared, the watch can be started at the zero second. 5.4.1 watch timer configuration the watch timer is configured as shown in figure 5-22. figure 5-22. watch timer block diagram 8 internal bus clear dividing circuit wm p23/buz f x 128 (32.768 khz) f xt (32.768 khz) f w f w 2 7 (256hz : 3.91 ms) f w 2 14 (2 hz : 0.5 sec) p23 output latch output buffer intw irqw set signal port2.3 pmgb bit 2 from clock generator circuit selector (32.768 khz) f w 2 6 (512hz : 1.95 ms) selector port 2 input/ output mode bit test instruction wm7 0 0 0 wm3 wm2 wm1 wm0 f w 16 (2.048 khz) f lcd remark f x = 4.194304 mhz and f xt = 32.768 khz in parentheses
110 chapter 5 peripheral hardware functions 5.4.2 watch mode register the watch mode register (wm) is an 8-bit register to control the watch timer. the format is shown in figure 5-23. all bits of the watch mode register, except bit 3, are set by 8-bit manipulation instructions. bit 3 is used to test the xt1 pin input level (bit test). data cannot be written. when the reset signal is generated, all bits except bit 3 are cleared to 0. example the time is generated by the main system clock (4.19 mhz). buzzer output is enabled. clr1 mbe mov xa, #84h mov wm, xa ; wm set figure 5-23. watch mode register format count clock (f w ) select bit wm0 0 system clock divided output: is selected 1 subsystem clock: f xt is selected operating mode select bit wm1 0 normal watch mode ( : irqw is set by 0.5 sec) 1 fast watch mode ( : irqw is set by 3.91 ms) watch operation enable/disable bit wm2 0 watch operation stop (dividing circuit clear) 1 watch operation enable xt1 pin input level (enable for bit test only) wm3 0 xt1 pin input at low level 1 xt1 pin input at high level buz output enable/disable bit wm7 0 buz output disable 1 buz output enable f x 128 7 6 5 4 3 2 1 0 wm0 wm1 wm3 wm2 0 0 0 wm7 address wm f98h symbol f w 2 14 f w 2 7
111 chapter 5 peripheral hardware functions 5.5 timer/event counter 5.5.1 timer/event counter configuration the m pd75308 has a one-channel on-chip timer/event counter and is configured as shown in figure 5-24. the timer/event counter has the following functions. (a) programmable interval timer operation (b) output of square wave having any selected frequency to pt00 pin (c) event counter operation (d) output of ti0 pin input divided by n to pto0 pin (frequency divider operation) (e) serial shift clock supply to serial interface circuit (f) count state read function
112 chapter 5 peripheral hardware functions figure 5-24. timer/event counter block diagram remark * indicates instruction execution. e tm06 tm05 tm04 tm03 tm02 e e tm0 8 internal bus 8 8 modulo register (8) port1.3 mpx from clock generator circuit t13/ti0 input buffer set1* tmod0 8 comparator (8) 8 count regjster (8) t0 cp clear timer operation starts tout f/f reset match to enable flag toe0 p20 output latch port2.0 port 2 input/ output mode pgmb bit 2 p20/pto0 to serial interface output buffer intt0 (lrqt0 set signal) irqt0 clear signal reset (refer to figure 5-10 .)
113 chapter 5 peripheral hardware functions 5.5.2 basic configuration and operations of timer/event counter the timer/event counter can select various operation modes using the timer/event counter mode register (tm0). its basic configuration and operations are as follows. (1) count pulse cp is selected by tm0 setting and is input to the 8-bit count register t0. (2) t0 is a binary, 8-bit up-counter which is incremented by 1 when cp is input. when the reset signal is generated, tm0 bit 3 is set (upon timer start) or the match signal is generated, t0 is cleared to 0. t0 can be read by an 8-bit memory manipulation instruction. data cannot be written to t0. (3) modulo register tmod0 is an 8-bit register which determines the number of t0 counts. tmod0 is set by an 8-bit memory manipulation instruction. data cannot be read from tmod0. when the reset signal is generated, tmod0 is initialized to ffh. (4) the comparator compares t0 content to tmod0 content. when the contents match, the comparator generates a match signal and sets the interrupt request flag (irqt0). figure 5-25 shows the count operation timing. figure 5-25. count operation timing count pulse (cp) modulo register count register tout f/f 0 1 2 n? n 0 1 2 n? n 0 1 2 3 4 n match match reset timer start instruction (tm0 bit 3 set) irqt0 set irqt0 set
114 chapter 5 peripheral hardware functions 5.5.3 timer/event counter mode register (tm0) and timer/event counter output enable flag (toe0) the mode register (tm0) is an 8-bit register which controls the timer/event counter. its format is shown in figure 5-26. the timer mode register is set by an 8-bit memory manipulation instruction. bit 3 is a timer start bit and can be set independently. it is automatically reset (0) when the timer starts operating. examples 1. the timer is started in the cp = 4.09 khz interval timer mode. sel mb15 ; or clr1 mbe mov xa, #01001100b mov tm0, xa ; tm0 4ch 2. the timer is restarted in accordance with the timer mode register setting. sel mb15 ; or clr1 mbe set1 tm0.3 ; tm0. bit3 1 when the reset signal is generated all bits of the timer mode register are cleared to 0. the timer/event counter output enable flag (toe0) is used to enable or disable output of timer out f/f (tout f/f) state to pt00 pin. the timer out f/f (tout f/f) is an f/f which is inverted by a match signal coming from the comparator. it is reset by an instruction which sets bit 3 of the timer mode register (tm0). when the reset signal is gener ated, toe0 and the t out f/f are cleared to 0.
115 chapter 5 peripheral hardware functions figure 5-26. timer/event counter mode register format 765432 10 count operation e e tm03 tm02 tm04 tm05 tm06 e address tm0 fa0h 0 stop (count content hold) 1 count operation clear the counter and irqt0 flag by writing "1". if bit 2 has been set (1), the count operation starts. timer start instruction bit count pluse (cp) select bit tm06 count pulse (cp) tm05 tm04 0 ti0 input rising edge 00 0 ti0 input falling edge 01 1 f x /2 10 (4.09 khz) 00 1 f x /2 8 (16.4 khz) 01 1 f x /2 6 (65.5 khz) 10 1 f x /2 4 (262 khz) 11 other than above setting prohibited remark f x = 4.19 mhz in parentheses operation mode
116 chapter 5 peripheral hardware functions figure 5-27. timer/event counter output enable flag format remark (w): write only 0 disable 1 enable timer/event counter output enable flag (w) 3 toe0 address fa2h
117 chapter 5 peripheral hardware functions 5.5.4 timer/event counter operating mode the count operation stop mode or the count operating mode is set according to the mode register setting. the following operations can always be carried out irrespectively of the mode register setting. 1 ti0 pin signal input and test (p13 dual-purpose pin input test enable) 2 timer out f/f state output to pto0 3 modulo register (tmod0) set 4 count register (t0) read 5 interrupt request flag (irqt0) set/clear/test (a) count operation stop mode when tm0 bit 2 is set to 0, this mode is set. in this mode, count operations are not carried out because count pulse (cp) supply to the count register is stopped. (b) count operating mode when tm0 bit 2 is set to 1, this mode is set. in this mode, the count pulse selected by bits 4 to 6 are supplied to the count register and count operations shown in figure 5-25 are carried out. timer operation is normally started in the following sequence. 1 the number of counts is set to the modulo register (tmod0). 2 operating mode, count clock and start instruction are set to the mode register (tm0). the modulo register is set by an 8-bit data transfer instruction. caution set a value other than 0 to the modulo register. example 3fh is set to the modulo register of channel 0. sel mb15 ; or clr1 mbe mov xa, #3fh mov tmod0, xa figure 5-28. count operating mode operation mpx ti0 internal clock count register (t0) comparator modulo register (tmod0) cp tout f/f pto0 match clear intt0 (lrqt0 set signal) to serial interface
118 chapter 5 peripheral har d w are functions 5.5. 5 timer/ e vent counter time set [timer set time] (cycle) is the v alue obtained b y dividing [modulo register count + 1] b y [count pulse frequency] selected by timer mode register setting. t (sec) = n + 1 = (n + 1) ? (resolution) f cp t (sec) : timer set time (sec) f cp (hz) : count pulse frequency (hz) n : modulo register value (n 1 0) once set, the timer generates the interrupt request signal (irqt0) at the set intervals. t a b le 5-6 shows the resolution and maxi m um set time (time to be set when ffh is set to the modulo register). example t o set up a 30 ms time inte r v al (f x = 4.194304 mhz). in this case, the mode with a maximum setting time of 62.5 ms is used. this gives 30 ms = 123 = 7bh 244 m s and 7ah is set in the modulo registe r . sel mb15 mov xa, #7ah mov tmod0, xa t a b le 5-6 . resolution and maxim um time set (4.19 mhz) mod e register timer channel 0 tm06 tm05 tm04 resolution maximum se t time 1 0 0 244 m s 62.5 ms 1 0 1 61.1 m s 15.6 ms 1 1 0 15.3 m s 3.91 ms 111 3. 81 m s 977 m s . .
119 chapter 5 peripheral hardware functions 5.5.6 precautions relating to timer/event counter application (1) timer start error the time between timer start (tm0.3 set) and generation of a match signal will have a maximum error corresponding to one clock of count pulse (cp) as compared to the value calculated in 5.5.5 . this is because the count register is cleared asynchronously with the cp as shown in figure 5-29. figure 5-29. timer start error (2) cautions relating to timer start count register t0 and interrupt request flag irqt0 are normally cleared by timer start (tm0 bit 3 set). if the timer is in the operating mode and irqt0 set and timer start are carried out simultaneously, irqt0 may not be cleared. this possesses no problem when irqt0 is used as a vectored interrupt. however, if irqt0 is to be tested, a problem occurs because irqt0 is set although the timer has been started. thus, when starting the timer at the timing when irqt0 may be set, stop the timer first (by setting tm0 bit 2 to 0) and restart it, or execute the timer start twice. example timer start at the timing when irqt0 may be set sel mb15 ; or clr1 mbe mov xa, #0 mov tm0, xa ; timer stop mov xa, #4ch mov tm0, xa ; restart or sel mb15 ; or clr1 mbe set1 tm0.3 set1 tm0.3 ; restart 1 2 3 1 2 timer start timer start cp count register 0 0
120 chapter 5 peripheral hardware functions (3) count register read errors the count register content can always be read by an 8-bit data memory manipulation instruction. while this instruction is in operation, the count pulse and the count register are held from changing. thus, when ti0 input is used as the count pulse signal source, count pulses are removed by the amount corresponding to the instruction execution time (if the internal clock is used as the count pulse, this pulse removal will not occur because of synchronization with the instruction). therefore, when applying ti0 input as the count pulse and reading the count register content, it is necessary to apply a signal having a pulse width which will not lead to an incorrect count if count pulses are removed. in other words, since the count is held for one machine cycle by a read instruction, a pulse to be input to the ti0 pin must have a width larger than the one machine cycle. external clock (tl0) instruction count pulse (cp) count register read instruction count pulse changes are held by are instruction. count pulse is removed by an instruction. k e 1 k k + 1 k + 2
121 chapter 5 peripheral hardware functions (4) precaution relating to count pulse change if the count pulse is changed by rewriting the timer mode register, the specification is validated just after the execution of an instruction. a whiskered count pulse ( 1 or 2 ) may be generated as shown below depending on clock combinations for count pulse change. in such cases, the counting may become incorrect or the counter register content may be destroyed. t0 prevents it from occurring, make sure to set bit 3 of the count mode register to 1 and simultaneously restart the timer when changing the count pulse. clock a specification clock b specification rewrite instruction rewrite instruction clock a specification clock a clock b count pulse clock a specification clock b specification rewrite instruction rewrite instruction clock a specification clock a clock b count pulse 12
122 chapter 5 peripheral hardware functions (5) operations after modulo register change modulo register change is carried out upon execution of an 8-bit data memory manipulation instruction. if the modulo register changed value is smaller than the count register value, the count register continues to count till it overflows. after that, it recounts from 0. thus, the modulo register post-change value (m) is smaller than the pre-change value (n), it is necessary to first change the modulo register and then restart the timer. n cp modulo register m x ?1 count register n > x > m x 0 1 255 n rewrite instruction cp modulo register m n count register match signal match signal 01 m 0
123 chapter 5 peripheral hardware functions 5.5.7 timer/event counter application (1) timer 0 is used as an interval timer to generate interrupts at 50 ms intervals. ? with the high-order 4 bits of the mode register set to 0100b, select the maximum set time of 62.5 ms. ? set the low-order 4 bits of the mode register to 1100b. ? the modulo register set value is as follows. 50 ms = 205 = cdh 244 m s sel mb15 ; or clr1 mbe mov xa, #0cch mov tmod0, xa ; modulo set mov xa, #01001100b mov tm0, xa ; mode set and timer start ei ; interrupt enable ei iet0 ; timer interrupt enable remark in this application, ti0 pin can be used as an input pin. (2) if the number of pulses input from ti0 pin becomes 100, an interrupt is generated (with the pulse set to high active). ? with the high-order 4 bits of the mode register set to 0000, select the rising edge. ? set the low-order 4 bits of the mode register to 1100b. ? set the modulo register to 99 = 100 C 1. sel mb15 ; or clr1 mbe mov xa, #100C1 mov tmod0, xa ; modulo set mov xa, #00001100b mov tm0, xa ; mode set ei ei iet0 ; intt0 enable . .
124 chapter 5 peripheral hardware functions 5.6 serial interface 5.6.1 serial interface functions the m pd75308 incorporates a clocked 8-bit serial interface, with four modes available. the functions of these modes are outlined below. (1) operation-halted mode this mode is used when no serial transfer is to be performed, and allows power dissipation to be reduced. (2) 3-wire serial i/o mode in this mode, 8-bit data transfer is performed using three lines: the serial clock (sck), serial output (so), and serial input (si). in the 3-wire serial i/o mode simultaneous transmission and reception is possible, increasing the data transfer processing speed. either the msb or lsb can be specified as the start bit for an 8-bit data serial transfer, allowing connection to devices using either as the start bit. the 3-wire serial i/o mode allows connection to 75x series and 78k series devices and various peripheral i/o devices. (3) 2-wire serial i/o mode in this mode, 8-bit data transfer is performed using two lines: the serial clock (sck) and the serial data bus (sb0 or sb1). as the output level to the two lines can be manipulated by software, communication with multiple devices is possible. also, since software manipulation of the output level is possible for sck and sb0 (or sb1), this mode is compatible with any transfer format. it is therefore possible to eliminate the handshaking line previously required for connection to multiple devices, allowing efficient use of input/output ports.
125 chapter 5 peripheral hardware functions (4) sbi mode (serial bus interface mode) in the sbi mode, communication is performed with multiple devices by means of two lines: the serial clock (sck) and the serial data bus (sb0 or sb1). this mode conforms to the nec serial bus format. in the sbi mode, the sender can output to the serial data bus an address to select the target device for serial communication, a command which gives a directive to the target device, and actual data. the receiver can determine by hardware whether the receive data is an address, command or actual data. this function allows input/output ports to be used efficiently, as with the 2-wire serial i/o mode, and also allows the serial interface control portion of the application program to be simplified. figure 5-30. example of sbi system configuration master cpu sb0 (sb1) sck slave cpu sb0 (sb1) sck serial clock address command data address 1 #1 slave cpu sb0 (sb1) sck address n #n v dd 5.6.2 serial interface configuration the serial interface block diagram is shown in figure 5-31.
126 chapter 5 peripheral hardware functions figure 5-31. serial interface block diagram internal bus 8 8 8/4 csim selector p03/si/sb1 selector p02/so/sb0 p01/sck p01 output latch 8 shift register (sio) address comparator slave address register (sva) (8) set clr d q (8) (8) bus release/ command/ acknowledge detection circuit serial clock counter serial clock control circuit sbic relt cmdt busy/ acknowledge output circuit acke bsye ackt serial clock selector reld cmdd ackd intcsi control circuit intcsi (lrqcsi set signal) fx/2 3 fx/2 4 fx/2 6 tout f/f (from timer/event counter) external sck bit test bit manipulation bit test match signal so latch
127 chapter 5 peripheral hardware functions (1) serial operating mode register (csim) csim is an 8-bit register which specifies the serial interface operating mode, serial clock, wake-up function, etc. (see 5.6.3 (1) serial operating mode register (csim) for details.) (2) serial bus interface control register (sbic) sbic is an 8-bit register composed of bits which control the serial bus and flags which indicate various statuses of the input data from the serial bus, and is mainly used in the sbi mode. (refer to 5.6.3 (2) serial bus interface control register (sbic) for details.) (3) shift register (sio) the sio register converts 8-bit serial data to parallel data and 8-bit parallel data to serial data. it performs transmission/reception operations (shift operation) in synchronization with the serial clock. actual transmission/ reception operations are controlled by writes to the sio. (refer to 5.6.3 (3) shift register (sio) for details.) (4) so latch a latch which holds the so/sb0 and si/sb1 pin levels. can be directly controlled by software. set at the end of the 8th sck pulse in the sbi mode. (refer to 5.6.3 (2) serial bus interface control register (sbic) for details. (5) serial clock selector selects the serial clock to be used. (6) serial clock counter counts the serial clocks output and input in a transmission/reception operation, and checks that 8-bit data transmission/reception has been performed. (7) slave address register (sva), address comparator ? in sbi mode used when the m pd75308 is used as a slave device. the slave sets its own specification number (slave address value) in the sva register. the master outputs a slave address to select a specific slave. the address comparator is used to compare the slave address received from the master with the sva value, and if they match the relevant slave is determined to have been selected. ? in 2-wire serial i/o mode or sbi mode when the m pd75308 transmits as the master or slave, the sva register performs error detection. (refer to 5.6.3 (4) slave address register (sva) for details.) (8) intcsi control circuit controls interrupt generation. interrupt requests (intcsi) are generated and interrupt request flag (irqcsi) is set in the following cases (refer to figure 6-1. interrupt control circuit block diagram): ? in 3-wire and 2-wire serial i/o mode generates interrupt requests on each count of 8 serial clock cycles. ? in sbi mode when wup note = 0 ...... generates interrupt requests on each count of 8 serial clock cycles. when wup = 1 ........... generates interrupt requests when the sva and sio values match after address reception. note wup .................... wak e-up function specification bit (bit 5 of csim)
128 chapter 5 peripheral hardware functions (9) serial clock control circuit controls the supply of the serial clock to the shift register. also controls the clock output to the sck pin when the internal system clock is used. (10) busy/acknowledge output circuit, bus release/command acknowledge detection circuit performs output and detection of various control signals in the sbi mode. does not operate in the 3-wire and 2-wire serial i/o mode. (11) p01 output latch latch used for serial clock generation by software after completion of 8 serial clock cycles. set to 1 by reset input. when the internal system clock is selected as the serial clock, the p01 output latch should be set to 1.
129 chapter 5 peripheral hardware functions 5.6.3 register functions (1) serial operating mode register (csim) the format of the serial operating mode register (csim) is shown in figure 5-32. csim is an 8-bit register which specifies the serial interface operating mode, serial clock, wake-up function, etc. csim is manipulated by 8-bit memory manipulation instructions. the high-order 3 bits can be manipulated bit by bit using the individual bit names. read/write capability differs from bit to bit (refer to figure 5-32 ). bit 6 can be tested only, and data written to this bit is invalid. reset input clears this register to 00h. figure 5-32. serial operating mode register (csim) format (1/3) remark (r) : read only (w) : write only 7 6 5 4 3 2 1 0 csim0 csim1 csim3 csim2 csim4 wup coi csie address csim fe0h symbol serial clock selection bits (w) serial interface operating mode selection bits (w) wake-up function specification bit (w) signal from address comparator (r) serial interface operation enable/disable specification bit (w)
130 chapter 5 peripheral hardware functions figure 5-32. serial operating mode register (csim) format (2/3) serial clock selection bit csim1 csim0 serial clock sck pin mode 3-wire serial i/o mode sbi mode 2-wire serial i/o mode 0 0 input clock to sck pin from external source input 0 1 timer/event counter output (t0) output 10 f x /2 4 (262 khz) f x /2 6 (65.5 khz) 11 f x /2 3 (524 khz) remark ( ): when f x = 4.19 mhz serial interface operating mode selection bits (w) csim4 csim3 csim2 operating mode shift register bit order s0 pin function si pin function x 0 0 3-wire serial sio 7 to sio 0 xa so/p02 si/p03 i/o mode (transfer starting from msb) (cmos output) (input) 1 sio 0 to sio 7 xa (transfer starting from lsb) 0 1 0 sbi mode sio 7 to sio 0 xa sb0/p02 p03 input (transfer starting from msb) (n-ch open-drain i/o) 1 p02 input sb1/p03 (n-ch open-drain i/o) 0 1 1 2-wire serial sio 7 to sio 0 xa sb0/p02 p03 input i/o mode (transfer starting from msb) (n-ch open-drain i/o) 1 p02 input sb1/p03 (n-ch open-drain i/o) remark x: dont care
131 chapter 5 peripheral hardware functions figure 5-32. serial operating mode register (csim) format (3/3) wake-up function specification bit (w) wup 0 irqcsi set at end of every serial transfer in each mode. 1 used only in sbi mode. irqcsi is set only when the address received after bus release matches the slave address register data (wake-up status). sb0/sbi is high impedance. caution if wup = 1 is set during busy signal output, busy is not released. with the sbi, the busy signal is output after the busy release directive until the next fall of the serial clock (sck). when setting wup = 1, it is necessary to confirm that the sb0 (or sb1) pin has been driven high after busy is released before setting wup = 1. signal from address comparator (r) coi note clearing condition (coi = 0) setting condition (coi = 1) when slave address register (sva) and shift register when slave address register (sva) and shift register data do not match. data match. note a coi read is valid only before the start or after completion of a serial transfer. during a transfer an indeterminate value will be read. also, coi data written by an 8-bit manipulation instruction is ignored. serial interface operation enable/disable specification bit (w) shift register operation serial clock counter irqcsi flag so/sb0 and si/sb1 pins csie 0 shift operation disabled cleared retained port 0 function only 1 shift operation enabled count operation settable function in each mode and port 0 function
132 chapter 5 peripheral hardware functions remarks 1. the operating mode can be selected according to the setting of csie, csim3, and csim2. csie csim3 csim2 operating mode 0 x x operating-halted mode 1 0 x 3-wire serial i/o mode 1 1 0 sbi mode 1 1 1 2-wire serial i/o mode 2. the p01/sck pin status depends on the setting of csie, csim1 and csim0 as shown below. csie csim1 csim0 p01/sck pin status 0 0 0 input port 1 0 0 high impedance 0 1 0 high-level output 001 011 1 1 0 serial clock output (high-level output) 101 111 3. the following procedure should be used to clear csie during a serial transfer. 1 clear the interrupt enable flag to set the interrupt disable state. 2 clear csie. 3 clear the interrupt request flag. examples 1. this example selects f x /2 4 as the serial clock, generates an irqcsi serial interrupt at the end of each serial transfer, and selects the mode in which serial transfers are performed in the sbi mode with the sb0 pin as the serial data bus. sel mb15 ; or clr1 mbe mov xa, #10001010b mov csim, xa ; csim 10001010b 2. to enable serial transfers in accordance with the contents of csim. sel mb15 ; or clr1 mbe set1 csie
133 chapter 5 peripheral hardware functions (2) serial bus interface control register (sbic) the format of the serial bus interface control register (sbic) is shown in figure 5-33. sbic is an 8-bit register composed of bits which control the serial bus and flags which indicate various statuses of the input data from the serial bus, and is mainly used in the sbi mode. sbic is manipulated by bit-manipulation instructions; it cannot be manipulated by 4-bit or 8-bit memory manipulation instructions. read/write capability differs from bit to bit (refer to figure 5-33 ). reset input clears this register to 00h. caution in the 3-wire and 2-wire serial i/o modes, only the following bits can be used: ? bus release trigger bit (relt) ............. so latch setting ? command trigger bit (cmdt) ............... so latch clearing figure 5-33. serial bus interface control register (sbic) format (1/3) remark (r) : read only (w) : write only (r/w) : read/write enabled 765432 10 relt cmdt cmdd reld ackt acke ackd bsye address sbic fe2h symbol bus release trigger bit (w) command trigger bit (w) bus release detection flag (r) command detection flag (r) acknowledge trigger bit (w) acknowledge enable bit (r/w) acknowledge detection flag (r) busy enable bit (r/w)
134 chapter 5 peripheral hardware functions figure 5-33. serial bus interface control register (sbic) format (2/3) bus release trigger bit (w) relt the bus release signal (rel) trigger output control bit. the so latch is set (1) by setting this bit (relt = 1), after which the relt bit is automatically cleared (0). caution sb0 (or sb1) must not be cleared during a serial transfer. ensure that it is cleared before a transfer is started or after it is completed. command trigger bit (w) cmdt the command signal (cmd) trigger output control bit. the so latch is cleared (0) by setting this bit (cmdt = 1), after which the cmdt bit is automatically cleared (0). caution sb0 (or sb1) must not be cleared during a serial transfer. ensure that it is cleared before a transfer is started or after it is completed. bus release detection flag (r) reld clearing conditions (reld = 0) setting condition (reld = 1) 1 when a transfer start instruction is executed when the bus release signal (rel) is detected 2 when reset is input 3 when csie = 0 (refer to figure 5-32 ) 4 when sva and sio do not match when an address is received command detection flag (r) cmdd clearing conditions (cmdd = 0) setting condition (cmdd = 1) 1 when a transfer start instruction is executed when the command signal (cmd) is detected 2 when the bus release signal (rel) is detected 3 when reset is input 4 when csie = 0 (refer to figure 5-32 ) acknowledge trigger bit (w) ackt when ackt is set after the end of a transfer, ack is output in synchronization with the next sck. after the ack signal is output, ackt is automatically cleared (0). cautions 1. ackt must not be set (1) before completion of a serial transfer or during a transfer. 2. ackt cannot be cleared by software. 3. when ackt is set, acke should be reset to 0.
135 chapter 5 peripheral hardware functions figure 5-33. serial bus interface control register (sbic) format (3/3) acknowledge enable bit (r/w) acke 0 disables automatic output of the acknowledge signal (ack) (output by ackt is possible). 1 when set before end of transfer ack is output in synchronization with the 9th sck clock cycle. when set after end of transfer ack is output in synchronization with sck immediately after execution of the setting instruction. acknowledge detection flag (r) ackd clearing condition (ackd = 0) setting condition (ackd = 1) 1 when a transfer is started when the acknowledge signal (ack) is detected 2 when reset is input (synchronized with the rise of sck) busy enable bit (r/w) bsye 0 1 disabling of automatic busy signal output 2 busy signal output is stopped in synchronization with the fall of sck immediately after execution of the clearing instruction. 1 the busy signal is output in synchronization with the fall of sck following the acknowledge signal. examples 1. to output the command signal. sel mb15 ; or clr1 mbe set1 cmdt 2. to test reld and cmdd, and perform different processing according to the type of receive data. this interrupt routine is only performed when wup = 1 and there is an address match. sel mb15 skf reld ; test reld br !adrs skt cmdd ; test cmdd br !data cmd : ....................... ; command interpretation data : ....................... ; data processing adrs : ....................... ; address decoding
136 chapter 5 peripheral hardware functions (3) shift register (sio) the configuration around the shift register is shown in figure 5-34. sio is an 8-bit register which carries out parallel-to-serial conversion and performs serial transmission/reception (shift operations) in synchronization with the serial clock. a serial transfer is started by writing data to sio. in transmission, the data written to sio is output to the serial output (so) or the serial data bus (sb0/ sb1). in reception, data is read into sio from the serial input (si) or sb0/sb1. sio can be read or written to by an 8-bit manipulation instruction. if reset is input during its operation, the value of sio is indeterminate. if reset is input in the standby mode, the value of sio is retained. the shift operation stops after transmission/reception of 8 bits. figure 5-34. configuration around shift register internal bus address comparator d q set clr clk relt cmdt so iatch busy/ack shift register (sio) shift clock n-ch open-drain output sio reading and the start of a serial transfer (write) are possible at the following cases: ? when the serial interface operation enable/disable bit (csie) = 1, except when csie is set to 1 after data has been written into the shift register. ? when the serial clock has been masked after an 8-bit serial transfer. ? when sck is high. ensure that sck is high when data is written to or read from the sio register. in the 2-wire serial i/o mode and sbi mode data bus configuration, input pins and output pins have dual purposes. output pins have an n-ch open-drain configuration. therefore, in a device in which reception is to be performed henceforth ffh should be set in the sio register.
137 chapter 5 peripheral hardware functions (4) slave address register (sva) sva is an 8-bit register used by the slave to set the slave address value (its own specification number). it is a write-only register which is manipulated by an 8-bit manipulation instruction. after reset signal input, the value of sva is indeterminate. however, when reset is input in the standby mode, the value of sva is retained. the sva register has the following two functions: (a) slave address detection [in sbi mode] used when the m pd75308 is connected to the serial bus as a slave device. the master outputs to its connected slaves a slave address to select a specific slave. if these two data items (the slave address output from the master and the sva value) are found to match when compared by the address comparator, the relevant slave is determined to have been selected. at this time, bit 6 (coi) of the serial operating mode register (csim) is set to 1, when an address is received the bus release detection flag (reld) is cleared (0) if a match is not detected. irqcsi is set only when a match is detected when wup = 1. this interrupt request indicates that a communication request has been issued from the master to the m pd75308. (b) error detection [in 2-wire serial i/o mode or sbi mode] the sva performs error detection in the following cases. ? when the m pd75308 transmits addresses, commands or data as the master device. ? when the m pd75308 receives data as a slave device. (refer to 5.6.6 (6) or 5.6.7 (8) error detection for details.)
138 chapter 5 peripheral hardware functions 5.6.4 operation-halted mode the operation-halted mode is used when no serial transfer is performed, allowing power dissipation to be reduced. in this mode, the shift register does not perform shift operations and can be used as an ordinary 8-bit register. when the reset signal is input the operation-halted mode is set. the p02/so/sb0 and p03/si/sb1 pins are fixed as input ports. p01/sck can be used as an input port depending on the setting of the serial operating mode register. (1) register setting operation-halted mode setting is performed by the serial operating mode register (csim) (refer to 5.6.3 (1) serial operating mode register (csim) for the full configuration of csim). csim is manipulated by 8-bit manipulation instructions, but bit manipulation of csie is also possible. manipulation is also possible using the bit name. reset input clears csim to 00h. shading indicates bits used in the operation-halted mode. 7 6 5 4 3 2 1 0 address symbol csim0 csim1 csim3 csim2 csim4 wup coi csie csim fe0h match signal from address comparator (r) serial interface operation enable/disable specification bit (w) serial clock selection bits (w) note serial interface operating mode selection bits (w) wake-up function specification bit (w) note allow selection of p01/sck pin status. remark (r) : read only (w) : write only serial interface operation enable/disable specification bit (w) shift register operation serial clock counter irqcsi flag so/sb0 and si/sb1 pins csie 0 shift operation disabled cleared retained port 0 function only
139 chapter 5 peripheral hardware functions serial clock selection bits (w) the p01/sck pin status depends on the csim0 and csim1 settings as shown below. csim1 csim0 p01/sck pin status 0 0 high impedance 0 1 high level 10 11 the following procedure should be used to clear csie during a serial transfer. 1 clear the interrupt enable flag (iecsi) to set the interrupt disable state. 2 clear csie. 3 clear the interrupt request flag (irqcsi).
140 chapter 5 peripheral hardware functions 5.6.5 3-wire serial i/o mode operation the 3-wire serial i/o mode allows connection to the system used in the 75x series, m pd7500 series, 87ad series, etc. communication is performed using three lines: the serial clock (sck), serial output (so), and serial input (si). figure 5-35. example of 3-wire serial i/o system configuration sck master cpu sck so si si so slave cpu 3-wire serial i/o 3-wire serial i/o (1) register setting 3-wire serial i/o mode operation is set by means of the following two registers: ? serial operating mode register (csim) ? serial bus interface control register (sbic) (a) serial operating mode register (csim) when the 3-wire serial i/o mode is used, csim is set as shown below (refer to 5.6.3 (1) serial operating mode register (csim) for the full configuration of csim). csim is manipulated by 8-bit manipulation instructions. bit manipulation of bits 7, 6 and 5 is also possible. reset input clears the csim register to 00h. shading indicates bits used in the 3-wire serial i/o mode. remark (r) : read only (w) : write only 765432 10 address symbol csim0 csim1 csim3 csim2 csim4 wup coi csie csim fe0h match signal from address comparator (r) serial interface operation enable/disable specification bit (w) serial clock selection bits (w) serial interface operating mode selection bits (w) wake-up function specification bit (w)
141 chapter 5 peripheral hardware functions serial clock selection bits (w) csim1 csim0 serial clock sck pin mode 0 0 input clock to sck pin from off chip input 0 1 timer/event counter output (t0) output 10f x /2 4 (262 khz) 11f x /2 3 (524 khz) remark ( ): operating with f x = 4.19 mhz serial interface operating mode selection bits (w) csim4 csim3 csim2 shift register bit order s0 pin function si pin function x00 sio 7C0 xa so/p02 si/p03 (msb-first transfer) (cmos output) (input) 1sio 0C7 xa (lsb-first transfer) remark x: dont care wake-up function specification bit (w) wup 0 irqcsi set at end of every serial transfer signal from address comparator (r) coi note clearing condition (coi = 0) setting condition (coi = 1) when slave address register (sva) and shift register when slave address register (sva) and shift register data do not match. data match. note a coi read is valid only before the start or after completion of a serial transfer. during a transfer an indeterminate value will be read. also, coi data written by an 8-bit manipulation instruction is ignored. serial interface operation enable/disable specification bit (w) shift register operation serial clock counter irqcsi flag so/sb0 and si/sb1 pins csie 1 shift operation enabled count operation settable function in each mode and port 0 function
142 chapter 5 peripheral hardware functions (b) serial bus interface control register (sbic) when the 3-wire serial i/o mode is used, sbic is set as shown below (refer to 5.6.3 (2) serial bus interface control register (sbic) for the full configuration of sbic). sbic is manipulated by bit manipulation instruction. reset input clears the sbic register to 00h. shading indicates bits used in the 3-wire serial i/o mode. remark (w): write only bus release trigger bit (w) relt the bus release signal (rel) trigger output control bit. the so latch is set (1) by setting this bit (relt = 1), after which the relt bit is automatically cleared (0). command trigger bit cmdt the command signal (cmd) trigger output control bit. the so latch is cleared (0) by setting this bit (cmdt = 1), after which the cmdt bit is automatically cleared (0). caution bits other than relt and cmdt should not be used in the 3-wire serial i/o mode. bus release trigger bit (w) command trigger bit (w) 765432 10 relt cmdt cmdd reld ackt acke ackd bsye address sbic fe2h symbol should not be used in 3-wire serial l/o mode.
143 chapter 5 peripheral hardware functions (2) communication operation in the 3-wire serial i/o mode, data transmission/reception is performed in 8-bit units. data is transmitted/ received bit by bit in synchronization with the serial clock. shift register shift operations are performed in synchronization with the fall of the serial clock (sck). then send data is held in the so latch and output from the so pin. also, receive data input to the si pin is latched in the shift register on the rise of sck. at the end of an 8-bit transfer the operation of the shift register stops automatically and the irqcsi interrupt request flag is set. figure 5-36. 3-wire serial i/o mode timing the so pin becomes a cmos output and outputs the so latch status, and thus the so pin output status can be manipulated in accordance with the setting of the relt bit and cmdt bit. however, manipulation should not be performed during a serial transfer. the sck pin output level is controlled by manipulating the p01 output latch in the output mode (internal system clock mode) (refer to 5.6.8 sck pin output manipulation ). si sck 12345678 di7 di6 di5 di4 di3 di2 di1 di0 so do7 do6 do5 do4 do3 do2 do1 do0 irqcsi start of transfer synchronized with fall of sck end of transfer execution of instruction which writes data to sio (transfer start directive)
144 chapter 5 peripheral hardware functions (3) serial clock selection serial clock selection is performed by setting bits 0 and 1 of the serial operating mode register (csim). any of the following 4 clocks can be selected. table 5-7. serial clock selection and use (in 3-wire serial i/o mode) mode register serial clock possible timing for shift register use csim 1 csim 0 source serial clock mask r/w and ser ial tr ansfer start 0 0 external sck slave cpu 0 1 tout f/f half-duplex asynchronous transfer (software control) 10 f x /2 4 medium-speed serial transfer 11 f x /2 3 high-speed serial transfer (4) signals relt and cmdt operation is shown in figure 5-37. figure 5-37. relt and cmdt operations automatically 1 in operation-halted mode masked at end of (csie = 0) 8-bit data transfer. 2 when serial clock is masked after end of 8-bit serial transfer 3 when sck is high relt cmdt so
145 chapter 5 peripheral hardware functions (5) msb/lsb-first switching the 3-wire serial i/o mode includes a function for selecting msb-first or lsb-first transfer. figure 5-38 shows the shift register (sio) and internal bus configuration. as shown in the figure, reading/ writing can be performed by inverting the msb/lsb. msb/lsb-first switching can be specified by bit 2 of the serial operating mode register (csim). figure 5-38. 3-wire i/o mode configuration start bit switchover is implemented by switching the order in which data bits are written to the shift register (sio). the sio shift order is always the same. therefore, msb/lsb start bit switching must be performed before writing data to the shift register. 7 6 internal bus 1 0 lsb-first msb-first read/write gate si shift register (sio) read/write gate so sck dq so latch
146 chapter 5 peripheral hardware functions (6) start of transfer when the following two conditions are met a serial transfer is started by setting transfer data in the shift register (sio). ? the serial interface operation enable/disable bit (csie) = 1. ? after an 8-bit serial transfer, the internal serial clock is stopped or sck is high. caution the transfer will not be started if csie is set to 1 after data is written into the shift register. when an 8-bit transfer ends, the serial transfer stops automatically and the irqcsi interrupt request flag is set. example in the following example the data in the ram specified by the hl register is transferred to sio, and at the same time the sio data is fetched into the accumulator and the serial transfer is started. mov xa, @hl ; fetch send data from ram sel mb15 ; or clr1 mbe xch xa, sio ; exchange send data with receive data and start transfer
147 chapter 5 peripheral hardware functions (7) 3-wire serial i/o mode applications examples 1. to transfer data msb-first (master operation) using a 262 khz transfer clock (when operating at 4.19 mhz). clr1 mbe mov xa, #10000010b mov csim, xa ; transfer mode setting mov xa, tdata ; tdata is tr ansfer data storage address mov sio, xa ; transfer data setting and start of transfer caution from the second time onward, the transfer can be started by setting data in sio (mov sio, xa or xch xa, sio). sck sck so/sb0 si pd75402 m pd75308 m in this application the m pd75308 si/sb1 pin can be used for input.
148 chapter 5 peripheral hardware functions examples 2. to transmit/receive lsb-first data using an external clock (slave operation). (in this case the function for reversing the msb and lsb in shift register read/write operations is used.) main routine clr1 mbe mov xa, #84h mov csim, xa ; serial operation stopped, msb/lsb inversion mode, external clock mov xa, tdata mov sio, xa ; transfer data setting and start of transfer ei iecsi ei interrupt routine (mbe = 0) mov xa, tdata xch xa, sio ; receive data-send data, start of transfer mov rdata, xa ; receive data save reti p01/sck pd75308 m si/sb1 87ad series product so/sb0 sck so si
149 chapter 5 peripheral hardware functions examples 3. to transmit/receive data at high speed using a 524 khz transfer clock (when operating at 4.19 mhz). sck pd75308 (master) m so/sb0 si/sb1 sck si so pd75206 etc. m ... master side clr1 mbe mov xa, #10000011b mov csim, xa ; transfer mode setting mov xa, tdata mov sio, xa ; transfer data setting and start of transfer loop: sktclr irqcsi ; irqcsi test br loop mov xa, sio ; receive data fetch .....
150 chapter 5 peripheral hardware functions 5.6.6 2-wire serial i/o mode operation the 2-wire serial i/o mode allows adaptation by means of the program to any communication format. communication is basically performed using two lines: the serial clock (sck) and serial data input/output sb0 (or sb1). figure 5-39. example of 2-wire serial i/o system configuration remark (r) : read only (w) : write only sck sb0/sb1 slave cpu sck sb0/sb1 master cpu v dd 2-wire serial i/o 2-wire serial i/o (1) register setting 2-wire serial i/o mode operation can be set by means of the following two registers: ? serial operating mode register (csim) ? serial bus interface control register (sbic) (a) serial operating mode register (csim) when the 2-wire serial i/o mode is used, csim is set as shown below (refer to 5.6.3 (1) serial operating mode register (csim) for the full configuration of csim). csim is manipulated by 8-bit manipulation instructions. bit manipulation of bits 7, 6 and 5 is also possible. reset input clears the csim register to 00h. shading indicates bits used in the 2-wire serial i/o mode. 7 6 5 4 3 2 1 0 address symbol serial clock selection bits (w) csim0 csim1 csim3 csim2 csim4 wup coi csie csim fe0h serial interface operating mode selection bits (w) wake-up function specification bit (w) match signal from address comparator (r) serial interface operation enable/disable specification bit (w)
151 chapter 5 peripheral hardware functions serial clock selection bits (w) csim1 csim0 serial clock sck pin mode 0 0 input clock to sck pin from off chip input 0 1 timer/event counter output (t0) output 10f x /2 6 (65.5 khz) 11 remark ( ): operating with f x = 4.19 mhz serial interface operating mode selection bits (w) csim4 csim3 csim2 shift register bit order so pin function si pin function 011 sio 7C0 xa sb0/p02 p03 input (msb-first transfer) (n-ch open-drain input/output) 1 p02 input sb1/p03 (n-ch open-drain input/output) wake-up function specification bit (w) wup 0 irqcsi set at end of every serial transfer. signal from address comparator (r) coi note clearing condition (coi = 0) setting condition (coi = 1) when slave address register (sva) and shift register when slave address register (sva) and shift register data do not match. data match. note a coi read is valid only before the start or after completion of a serial transfer. during a transfer an indeterminate value will be read. also, coi data written by an 8-bit manipulation instruction is ignored. serial interface operation enable/disable specification bit (w) shift register operation serial clock counter irqcsi flag so/sb0 and si/sb1 pins csie 1 shift operation enabled count operation settable function in each mode and port 0 function
152 chapter 5 peripheral hardware functions (b) serial bus interface control register (sbic) when the 2-wire serial i/o mode is used, sbic is set as shown below (refer to 5.6.3 (2) serial bus interface control register (sbic) for the full configuration of sbic). sbic is manipulated by bit manipulation instructions. reset input clears the sbic register to 00h. shading indicates bits used in the 2-wire serial i/o mode. remark (w): write only bus release trigger bit (w) relt the bus release signal (rel) trigger output control bit. the so latch is set (1) by setting this bit (relt = 1), after which the relt bit is automatically cleared (0). command trigger bit cmdt the command signal (cmd) trigger output control bit. the so latch is cleared (0) by setting this bit (cmdt = 1), after which the cmdt bit is automatically cleared (0). caution bits other than relt and cmdt should not be used in the 2-wire serial i/o mode. bus release trigger bit (w) command trigger bit (w) 765432 10 relt cmdt cmdd reld ackt acke ackd bsye address sbic fe2h symbol should not be used in 2-wire serial l/o mode.
153 chapter 5 peripheral hardware functions (2) communication operation in the 2-wire serial i/o mode, data transmission/reception is performed in 8-bit units. data is transmitted/ received bit by bit in synchronization with the serial clock. shift register shift operations are performed in synchronization with the fall of the serial clock (sck). then send data is held in the so latch and output msb-first from the sb0/p02 (or sb1/p03) pin. also, receive data input from the sb0 (or sb1) pin is latched in the shift register on the rise of sck. at the end of an 8-bit transfer the operation of the shift register stops automatically and the irqcsi interrupt request flag is set. figure 5-40. 2-wire serial i/o mode timing 1 2 3 4 5 6 7 8 sck d7 d6 d5 d4 d3 d2 d1 d0 sb0/sb1 irqcsi start of transfer synchronized with fall of sck end of transfer execution of instruction which writes data to sio (transfer start directive) since the pin specified as the sb0 (or sb1) pin serial data bus is an n-ch open-drain input/output, it must be pulled high externally. also, since the n-ch transistor must be turned off during data reception, ffh is written to sio beforehand. since the sb0 (or sb1) pin outputs the so latch status, the sb0 (or sb1) pin output status can be manipulated in accordance with the setting of the relt bit and cmdt bit. however, manipulation should not be performed during a serial transfer. the sck pin output level is controlled by manipulating the p01 output latch in the output mode (internal system clock mode) (refer to 5.6.8 sck pin output manipulation ).
154 chapter 5 peripheral hardware functions (3) serial clock selection serial clock selection is performed by setting bits 0 and 1 of the serial operating mode register (csim). any of the following 3 clocks can be selected. table 5-8. serial clock selection and use (in 2-wire serial i/o mode) mode register serial clock possible timing for shift register use csim 1 csim 0 source serial clock mask r/w and ser ial tr ansfer start 0 0 external sck slave cpu 0 1 tout f/f arbitrary-speed serial transfer 10 f x /2 6 low-speed serial transfer 11 (4) signals relt and cmdt operation is shown in figure 5-41. figure 5-41. relt and cmdt operations automatically 1 in operation-halted mode masked at end of (csie = 0) 8-bit data transfer. 2 when serial clock is masked after end of 8-bit serial transfer 3 when sck is high relt cmdt sb0 (sb1) (5) start of transfer when the following two conditions are met a serial transfer is started by setting transfer data in the shift register (sio). ? the serial interface operation enable/disable bit (csie) = 1. ? after an 8-bit serial transfer, the internal serial clock is stopped or sck is high. cautions 1. the transfer will not be started if csie is set to 1 after data is written into the shift register. 2. since the n-ch transistor must be turned off during data reception, ffh should be written to sio beforehand. when an 8-bit transfer ends, the serial transfer stops automatically and the irqcsi interrupt request flag is set.
155 chapter 5 peripheral hardware functions (6) error detection in the 2-wire serial i/o mode, since the status of the serial bus sb0/sb1 pin during transmission is also written into the sio shift register of the transmitting device, transmission errors can be detected in the following ways: (a) comparison of pre-transmission and post-transmission sio data in this case, a transmission error is judged to have been generated if the two data items are different. (b) use of slave address register (sva) transmission is performed after setting the send data in the sio and sva registers. after transmission the coi bit of the serial operating mode register (csim) (the match signal from the address comparator) is tested: 1 indicates normal transmission, and 0, a transmission error. (7) 2-wire serial i/o mode applications a serial bus is configured and multiple devices connected. example to configure a system with the m pd75308 as the master and the m pd75104, m pd75402a and m pd7225g connected as slaves. in the bus configuration shown in this example connection is made via the si pin and so pin. when serial data is not output, ffh is written into the shift register beforehand and a high-level signal output to the so pin, and the output buffer is turned off to release the bus. since the m pd75402a so pin cannot be placed in the high impedance state, it should be made an open collector output by connecting a transistor as shown in the figure. then, when data is input the transistor is turned off by writing 00h to the shift register beforehand. when each microcontroller outputs data is determined in advance. the serial clock is output by the m pd75308, which is the master microcontroller, and the other slave microcontroller all operate on an external clock. pd75308 (master) m port sck pd7225g m cs sck si so/sb0 pd75402a m so pd75104 m sck si so sck si v dd
156 chapter 5 peripheral hardware functions 5.6.7 sbi mode operation the sbi (serial bus interface) is a high-speed serial interface which conforms to the nec serial bus format. the sbi is a single-master high-speed serial bus. its format includes the addition of bus configuration functions to the clocked serial bus system to enable communication to be performed with multiple devices using two signal lines. consequently, when a serial bus is configured with multiple microcontrollers and peripheral ics, it is possible to reduce the number of ports used and the amount of wiring on the substrate. the master can output to a slave on the serial data bus an address to select the target device for serial communication, a command which gives a directive to the target device, and actual data. the slave can determine by hardware whether the receive data is an address, command or actual data. this function allows the serial interface control portion of the application program to be simplified. sbi functions are incorporated in a number of devices including the 75x series, and 78k series 8-bit single- chip microcontrollers. an example of a serial bus configuration when cpus and peripheral ics with a serial interface conforming to the sbi are used is shown in figure 5-42. in the sbi the sb0 (sb1) serial data bus pin is an open-drains output and thus the data bus line is in the wired- or state. the serial data bus line requires a pull-up resistor. figure 5-42. example of sbi serial bus configuration sck sb0 (sb1) sb0 (sb1) sck sb0 (sb1) sck + v dd slave ic address n slave cpu address 2 slave cpu address 1 ? ? ? ? ? sb0 (sb1) sck master cpu ? ? ? ? ? serial data bus serial clock caution when master/slave exchange processing is performed, since serial clock line (sck) input/ output switching is performed asynchronously between master and slave, a pull-up resistor is also required for the serial clock line (sck).
157 chapter 5 peripheral hardware functions (1) sbi functions since conventional serial i/o methods have only data transfer functions, when a serial bus is configured with multiple devices connected a large number of ports and wires are required for the chip select signal, command/data differentiation, busy status recognition, etc. if these controls are performed by software, the load incurred by software is very large. with the sbi, a serial bus can be configured using only two lines: the serial clock, sck, and the serial data bus, sb0 (sb1). as a result, the number of microcontroller ports and the amount of substrate wiring can be significantly reduced. sbi functions are described below. (a) address/command/data identification function identifies serial data as an address, command or actual data. (b) chip selection by address the master performs chip selection by address transmission. (c) wake-up function a slave can identify address reception (chip selection) easily by means of the wake-up function (settable/ releasable by software). when the wake-up function is set, an interrupt (irqcsi) is generated when a matching address is received. as a result, non-selected cpus can operate without regard to serial communications even when communication with multiple devices is performed. (d) acknowledge signal (ack) control function controls the acknowledge signal used to confirm serial data reception. (e) busy signal (busy) control function controls the busy signal used to give notification of a slave busy status.
158 chapter 5 peripheral hardware functions (2) sbi definition the sbi serial data format and the meaning of the signals used are explained in the following section. serial data transmitted via the sbi is classified into three types: commands, addresses and data. serial data forms a frame using the configuration below. address, command and data timing is shown in figure 5-43. figure 5-43. sbi t ransfer timing sck sb0/sb1 sck sb0/sb1 sck sb0/sb1 8 9 9 a7 a0 ack busy c7 c0 ack busy ready 8 9 d7 d0 ack busy ready address transfer command transfer data transfer bus release signal command signal the bus release signal and command signal are output by the master. the busy signal is output by the slave. ack can be output by either the master or slave (normally output by the 8-bit data receiver). the serial clock is output by the master continuously from the start of an 8-bit data transfer until busy is released.
159 chapter 5 peripheral hardware functions (a) bus release signal (rel) the bus release signal indicates that the sb0 (sb1) line has changed from low to high when the sck line is high (when the serial clock is not being output). this signal is output by the master. figure 5-44. bus release signal sck "h" sb0 (sb1) the bus release signal indicates that the master is about to send an address to a slave. slaves incorporate hardware to detect the bus release signal. (b) command signal (cmd) the command signal indicates that the sb0 (sb1) line has changed from high to low when the sck line is high (when the serial clock is not being output). this signal is output by the master. figure 5-45. command signal sck "h" sb0 (sb1) slave incorporate hardware to detect the command signal.
160 chapter 5 peripheral hardware functions (c) address an address is 8-bit data output by the master to slaves connected to the bus line in order to select a particular slave. figure 5-46. address the 8-bit data following the bus release signal and command signal is defined as an address. in a slave this condition is detected by hardware and a check is performed by hardware to see if the 8- bit data matches the slaves own specification number (slave address). if the 8-bit data matches the slave address, that slave is determined to have been selected and communication is subsequently performed with the master until a disconnect directive is received from the master. figure 5-47. slave selection by address master slave 1 not selected slave 2 selected slave 3 not selected slave 4 not selected sends slave 2 address sck a7 a6 a5 a4 a3 a2 a1 a0 12345678 sb0 (sb1) address bus release signal command signal
161 chapter 5 peripheral hardware functions (d) command and data the master sends a command or data to the slave selected by address transmission. figure 5-48. command figure 5-49. data sck c7 c6 c5 c4 c3 c2 c1 c0 1 2 3 4 5 6 7 8 sb0 (sb1) command command signal sck d7 d6 d5 d4 d3 d2 d1 d0 1 2 3 4 5 6 7 8 sb0 (sb1) data the 8-bit data following the command signal is defined as a command. 8-bit data with no command signal is defined as data. the way in which commands and data are used can be freely decided according to the communication specifications.
162 chapter 5 peripheral hardware functions (e) acknowledge signal (ack) the acknowledge signal is used to confirm serial data reception between the sender and receiver. figure 5-50. acknowledge signal ack sck sb0 (sb1) 8 9 10 11 ack sck 8 9 sb0 (sb1) [when output in synchronization with 11th sck clock cycle] [when output in synchronization with 9th sck clock cycle] the acknowledge signal is an one-shot pulse synchronized with the fall of sck after an 8-bit data transfer. its position is arbitrary and it can be synchronized with any sck clock cycle. after 8-bit data transmission the sender checks whether the receiver has sent back an acknowledge signal. if an acknowledge signal is not returned within a specific time after data transmission, reception can be judged not to have been performed correctly.
163 chapter 5 peripheral hardware functions (f) busy signal (busy), ready signal (ready) the busy signal notifies the master that a slave is preparing for data transmission/reception. the ready signal notifies the master that a slave is ready for data transmission/reception. figure 5-51. busy signal and ready signal ack sck sb0 (sb1) 8 9 busy ready with the sbi a slave reports its busy status to the master by driving the sb0 (sb1) line low. the busy signal is output following the acknowledge signal output by the master or slave. busy signal setting/release is performed in synchronization with the fall of sck. when the busy signal is released the master automatically terminates output of the sck serial clock. when the busy signal is released and the ready signal state is entered the master can start the next transfer.
164 chapter 5 peripheral hardware functions (3) register setting sbi mode operation can be set by means of the following two registers: ? serial operating mode register (csim) ? serial bus interface control register (sbic) (a) serial operating mode register (csim) when the sbi mode is used, csim is set as shown below (refer to 5.6.3 (1) serial operating mode register (csim) for the full configuration of csim). csim is manipulated by 8-bit manipulation instructions. bit manipulation of bits 7, 6 and 5 is also possible. reset input clears the csim register to 00h. shading indicates bits used in the sbi mode. remark (r) : read only (w) : write only serial clock selection bits (w) csim1 csim0 serial clock sck pin mode 0 0 input clock to sck pin from off chip input 0 1 timer/event counter output (t0) output 10 f x /2 4 (262 khz) 11 f x /2 3 (524 khz) remark ( ): operating with f x = 4.19 mhz serial interface operating mode selection bits (w) csim4 csim3 csim2 shift register bit order so pin function si pin function 010 sio 7C0 xa sb0/p02 p03 input (msb-first transfer) (n-ch open-drain input/output) 1 p02 input sb1/p03 (n-ch open-drain input/output) 7 6 5 4 3 2 1 0 address symbol serial clock selection bits (w) csim0 csim1 csim3 csim2 csim4 wup coi csie csim fe0h serial interface operating mode selection bits (w) wake-up function specification bit (w) signal from address comparator (r) serial interface operation enable/disable specification bit (w)
165 chapter 5 peripheral hardware functions wake-up function specification bit (w) wup 0 irqcsi set at end of every serial transfer in sbi mode mask state. 1 used only in sbi mode. irqcsi is set only when the address received after bus release matches the slave address register data (wake-up status). sb0/sb1 is high impedance. caution if wup = 1 is set during busy signal output, busy is not released. with the sbi, the busy signal is output after the busy release directive until the next fall of the serial clock (sck). when setting wup = 1, it is necessary to confirm that the sb0 (or sb1) pin has been driven high after busy is released before setting wup = 1. signal from address comparator (r) coi note clearing condition (coi = 0) setting condition (coi = 1) when slave address register (sva) and shift register data when slave address register (sva) and shift do not match. register data match. note a coi read is valid only before the start or after completion of a serial transfer. during a transfer an indeterminate value will be read. also, coi data written by an 8-bit manipulation instruction is ignored. serial interface operation enable/disable specification bit (w) shift register operation serial clock counter irqcsi flag so/sb0, si/sb1 pins csie 1 shift operation enabled count operation settable function in each mode and port 0 function
166 chapter 5 peripheral hardware functions (b) serial bus interface control register (sbic) when the sbi mode is used, sbic is set as shown below (refer to 5.6.3 (2) serial bus interface control register (sbic) for the full configuration of sbic). sbic is manipulated by bit manipulation instructions. reset input clears the sbic register to 00h. shading indicates bits used in the sbi mode. bus release trigger bit (w) 7 6 5 4 3 2 1 0 relt cmdt cmdd reld ackt acke ackd bsye address sbic fe2h symbol command trigger bit (w) bus release detection flag (r) command detection flag (r) acknowledge trigger bit (w) acknowledge enable bit (r/w) acknowledge detection flag (r) busy enable bit (r/w) remark (r) : read only (w) : write only (r/w) : read/write enabled bus release trigger bit (w) relt the bus release signal (rel) trigger output control bit. the so latch is set (1) by setting this bit (relt = 1), after which the relt bit is automatically cleared (0). caution sb0 (or sb1) must not be cleared during a serial transfer. ensure that it is cleared before a transfer is started or after it is completed. command trigger bit (w) cmdt the command signal (cmd) trigger output control bit. the so latch is cleared (0) by setting this bit (cmdt = 1), after which the cmdt bit is automatically cleared (0). caution sb0 (or sb1) must not be cleared during a serial transfer. ensure that it is cleared before a transfer is started or after it is completed. bus release detection flag (r) reld clearing conditions (reld = 0) setting condition (reld = 1) 1 when a transfer start instruction is executed when the bus release signal (rel) is detected 2 when reset is input 3 when csie = 0 (refer to figure 5-32 ) 4 when sva and sio match when an address is received
167 chapter 5 peripheral hardware functions command detection flag (r) cmdd clearing conditions (cmdd = 0) setting condition (cmdd = 1) 1 when a transfer start instruction is executed when the command signal (cmd) is detected 2 when the bus release signal (rel) is detected 3 when reset is input 4 when csie = 0 (refer to figure 5-32 ) acknowledge trigger bit (w) ackt when ackt is set after the end of a transfer, ack is output in synchronization with the next sck. after the ack signal is output, ackt is automatically cleared (0). cautions 1. ackt must not be set (1) before completion of a serial transfer or during a transfer. 2. ackt cannot be cleared by software. 3. when ackt is set, acke should be reset to 0. acknowledge enable bit (r/w) acke 0 disables automatic output of the acknowledge signal (output by ackt is possible). 1 when set before end of transfer the acknowledge signal is output in synchronization with the 9th sck clock cycle. when set after end of transfer the acknowledge signal is output is synchronization with sck immediately after execution of the setting instruction. acknowledge detection flag (r) ackd clearing condition (ackd = 0) setting condition (ackd = 1) 1 when a transfer is started when the acknowledge signal (ack) is detected 2 when reset is input (synchronized with the rise of sck) busy enable bit (r/w) bsye 0 1 disabling of automatic busy signal output 2 busy signal output is stopped in synchronization with the fall of sck immediately after execution of the clearing instruction. 1 the busy signal is output in synchronization with the fall of sck following the acknowledge signal.
168 chapter 5 peripheral hardware functions (4) serial clock selection serial clock selection is performed by setting bits 0 and 1 of the serial operating mode register (csim). any of the following 4 clocks can be selected. table 5-9. serial clock selection and use (in sbi mode) mode register serial clock possible timing for shift register use csim1 csim0 source serial clock mask r/w and ser ial tr ansfer start 0 0 external sck slave cpu 0 1 tout f/f arbitrary-speed serial transfer 10 f x /2 4 medium-speed serial transfer 11 f x /2 3 high-speed serial transfer when the internal system clock is selected sck stops at 8 pulses internally, but externally the count continues until the slave is in the ready state. (5) signals the operation of signals and flags in sbic in the sbi mode are shown in figures 5-52 to 5-57, and sbi signals are listed in table 5-10. figure 5-52. relt, cmdt, reld, and cmdd operation (master) automatically 1 in operation-halted mode masked at end of (csie = 0) 8-bit data transfer. 2 when serial clock is masked after end of 8-bit serial transfer 3 when sck is high sck sb0 (sb1) relt cmdt cmdd reld sio transfer start directive
169 chapter 5 peripheral hardware functions figure 5-53. relt, cmdt, reld, and cmdd operation (slave) caution ackt must not be set before the end of a transfer. figure 5-54. ackt operation sck sb0 (sb1) ackt 6 7 8 9 d2 d1 d0 ack when set in this interval ack signal is output in 1 clock interval immediately after ackt is set. sio sck so iatch reld cmdd 1 d5 transfer start directive write to sio when address matches when address does not match relt (master) cmdt (master) 23456789 d7 d6 d4 d3 d2 d1 d0
170 chapter 5 peripheral hardware functions figure 5-55. acke operation (a) when acke = 1 on completion of transfer sck sb0 (sb1) acke when acke is set and cleared in this interval and acke = 0 on next fall of sck ack signal is not output. d2 d1 d0 (d) when acke = 1 interval is short sck sb0 (sb1) acke 1 2 7 8 9 d7 d6 d2 d1 d0 ack when acke = 1 at this point ack signal is output in 9th clock cycle. (b) when acke is set after completion of transfer sck sb0 (sb1) acke 7 8 9 d1 d0 ack 6 d2 when acke is set in this interval and acke = 1 on next fall of sck after acke is set. ack signal is output in 1 clock interval immediately afrer acke is set. (c) when acke = 0 on completion of transfer sck sb0 (sb1) acke 1 2 7 8 9 d7 d6 d2 d1 d0 when acke = 0 at this point ack signal is not output.
171 chapter 5 peripheral hardware functions figure 5-56. ackd operation (a) when ack signal is output in 9th sck clock interval sck sb0 (sb1) bsye 7 8 9 ack 6 when bsye = 1 at this point busy when bsye is reset in this interval and bsye = 0 when sck falls d2 d1 d0 figure 5-57. bsye operation ack sck sb0 (sb1) ackd 9 transfer start directive sio 7 8 d1 6 d2 d0 d6 d7 busy start of transfer (c) clearing timing when transfer start directive is given during busy state sck sb0 (sb1) ackd 7 8 9 d1 d0 ack 6 d2 transfer start directive sio start of transfer (b) when ack signal is output after 9th sck clock interval sb0 (sb1) ackd 9 sio 7 8 d1 6 d2 d0 transfer start directive start of transfer sck ack
172 chapter 5 peripheral hardware functions table 5-10. signals in sbi mode (1/2) signal name outputting definition timing chart output conditions effect on flags meaning of signal device bus release master sb0 (sb1) rising edge ? relt set ? reld set outputs next cmd signal (rel) when sck = 1 ? cmdd cleared signal and indicates send data is address. command master sb0 (sb1) falling edge ? cmdt set ? cmdd set (1) after rel signal signal (cmd) when sck = 1 output send data is address. (2) send data with no rel signal output is command. acknowledge master/ low-level signal output 1 acke = 1 ? ackd set receive completion signal (ack) slave to sb0 (sb1) in 1 sck 2 ackt set clock interval after serial receive completion. busy signal slave low-level signal output ? bsye = 1 C serial transmission/ (busy) to sb0 (sb1) after reception disabled acknowledge signal. because processing is in progress. ready signal slave high-level signal output 1 bsye = 0 C serial transmission/ (ready) to sb0 (sb1) before 2 execution of reception enabled start or after completion instruction to write of serial transfer. data to sio (transfer start directive) sck "h" sb0 (sb1) sck "h" sb0 (sb1) sck d0 ready sb0 (sb1) d0 ready sb0 (sb1) ack busy busy ack 9
chapter 5 peripheral hardware functions 173 table 5-10. signals in sbi mode (2/2) signal name outputting definition timing chart output conditions effect on flags meaning of signal device serial clock master synchronization clock execution of irqcsi set timing of signal (sck) for output of address/ instruction to write to (rise of 9th sck clock output to serial command/data, ack sio when csie = 1 cycle) note 1 data bus signal, synchronous (serial transfer start busy signal, etc. directive note 2 ) address/command/data is transferred in first 8 cycles. address master 8-bit data transferred in address value of (a7 to a0) synchronization with slave device on sck after rel signal serial bus and cmd signal output. command master 8-bit data transferred in directive message (c7 to c0) synchronization with to slave device sck after cmd signal only is output without output of rel signal. data master/ 8-bit data transferred in numeric value to (d7 to d0) slave synchronization with be processed by sck with no output of slave or master either rel signal or device. cmd signal. notes 1. when wup = 0, irqcsi is always set on the 9th rise of sck. when wup = 1, irqcsi is set on the 9th rise of sck only when an address is received and that address matches the value of the slave address register (sva). 2. when in the busy state, the transfer starts after transition to the ready state. sck sb0 (sb1) 1278910 sck sb0 (sb1) 1278 rel cmd sck sb0 (sb1) 1278 cmd sck sb0 (sb1) 1278
174 chapter 5 peripheral hardware functions (6) pin configuration the configuration of the serial clock pin (sck) and the serial data bus pin sb0 (sb1) is as shown below. (a) sck ................... pin for input/output of serial clock 1 master ........ cmos, push-pull output 2 slave .......... schmitt input (b) sb0 (sb1) ......... serial data input/output dual-purpose pin for both master and slave, output is n-ch open drain, input is schmitt input. since the serial data bus line output is n-ch open drain, an external pull-up resistor is necessary. figure 5-58. pin configuration diagram si so si so (clock input) clock output master device clock input (clock output) serial clock r l serial data bus sb0 (sb1) sb0 (sb1) n-ch open drain n-ch open drain slave device caution since the n-ch open drain must be turned off during data reception, ffh should be written to sio beforehand. it can always be turned off during transmission. however, when the wake-up function specification bit (wup) is 1, the n-ch transistor is always off, and therefore ffh need not be written to sio prior to reception.
175 chapter 5 peripheral hardware functions (7) address match detection method in the sbi mode, master address communication is used to select a specific slave and start communication. address match detection is performed by hardware. a slave address register (sva) is provided, and irqcsi is set only when the address sent from the master and the value set in sva match in the wake- up state (wup = 1). cautions 1. detection of the slave selected/non-selected state is performed by detection of a match with a slave address received after bus release (when reld = 1). an address match interrupt (irqcsi) generated when wup = 1 is normally used for this match detection. therefore, detection of selection/non-selection by slave address should be performed with wup = 1. 2. for selection/non-selection detection without using an interrupt when wup = 0, the address detection method is not used, but instead detection should be performed by transmission/reception of commands set beforehand by the program. (8) error detection in the sbi mode, since the status of the serial bus sb0/sb1 pin during transmission is also written into the sio shift register of the transmitting device, transmission errors can be detected in the following ways: (a) comparison of pre-transmission and post-transmission sio data in this case, a transmission error is judged to have been generated if the two data items are different. (b) use of slave address register (sva) transmission is performed after setting the send data in the sio and sva registers. after transmission the coi bit of the serial operating mode register (csim) (the match signal from the address comparator) is tested: 1 indicates normal transmission, and 0, a transmission error. (9) communication operation with the sbi, the master normally selects the slave device to be communicated with from among the multiple connected devices by outputting an address onto the serial bus. after the target communication device has been determined, commands and data are exchanged between the master device and slave device, thus implementing serial communication. data communication timing charts are shown in figures 5-59 through 5-62. in the sbi mode, shift register shift operations are performed in synchronization with the fall of the serial clock (sck), and send data is latched in the so latch and is output msb-first from the sb0/p02 or sb1/ p03 pin. receive data input to the sb0 (or sb1) pin is latched in the shift register on the rise of sck.
176 chapter 5 peripheral hardware functions figure 5-59. address transmission from master device to slave device (wup = 1) 1 2 3 4 5 6 7 8 9 sck pin a7 a6 a5 a4 a3 a2 a1 a0 ack busy sb0 pin program processing serial transmit operation irqcsi generation sck stop hardware operation wup ? 0 program processing cmdd set ack output hardware operation cmdt set relt set cmdt set write to sio master device processing (sending side) transfer line slave device processing (receiving side) cmdd clear cmdd set reld set serial receive operation busy output ready (when sva = sio) address busy clear busy clear ackd set irqcsi generation interrupt servicing (preparation for next serial transfer) ackt set
177 chapter 5 peripheral hardware functions figure 5-60. command transmission from master device to slave device 1 2 3 4 5 6 7 8 9 sck pin c7 c6 c5 c4 c3 c2 c1 c0 ack busy sb0 pin program processing serial transmit operation irqcsi generation sck stop hardware operation command analysis ackt set program processing ack output hardware operation cmdt set write to sio master device processing (sending side) transfer line slave device processing (receiving side) cmdd set serial receive operation busy output ready command busy clear busy clear ackd set irqcsi generation interrupt servicing (preparation for next serial transfer) sio read
178 chapter 5 peripheral hardware functions figure 5-61. data t ransmission from master device to slave device 1 2 3 4 5 6 7 8 9 sck pin d7 d6 d5 d4 d3 d2 d1 d0 ack busy sb0 pin program processing serial transmit operation irqcsi generation sck stop hardware operation ackt set program processing ack output hardware operation write to sio master device processing (sending side) transfer line slave device processing (receiving side) serial receive operation busy output ready data busy clear busy clear ackd set irqcsi generation interrupt servicing (preparation for next serial transfer) sio read
179 chapter 5 peripheral hardware functions figure 5-62. data t ransmission from slave device to master device 1 2 3 4 5 6 7 8 9 sck pin d7 d6 d5 d4 d3 d2 d1 d0 ack busy sb0 pin program processing serial receive operation irqcsi generation serial reception hardware operation program processing ackd set hardware operation sio write to ffh master device processing (receiving side) transfer line slave device processing (sending side) serial transmit operation busy output ready data busy clear write to sio ack output irqcsi generation receive data processing sio write to ffh ackt set sio read d7 d6 12 sck stop write to sio ready busy busy clear
180 chapter 5 peripheral hardware functions (10) start of transfer when the following two conditions are met a serial transfer is started by setting transfer data in the shift register (sio). ? the serial interface operation enable/disable bit (csie) = 1. ? after an 8-bit serial transfer, the internal serial clock is stopped or sck is high. cautions 1. the transfer will not be started if csie is set to 1 after data is written into the shift register. 2. since the n-ch transistor must be turned off during data reception, ffh should be written to sio beforehand. however, when the wake-up function specification bit (wup) is 1, the n-ch transistor is always off, and therefore ffh need not be written to sio prior to reception. 3. if data is written to sio when the slave is in the busy state, that data is not lost. the transfer starts when the busy state is released and the sb0 (or sb1) input becomes high (ready state). when an 8-bit transfer ends, the serial transfer stops automatically and the irqcsi interrupt request flag is set. example in the following example the data in the ram specified by the hl register is transferred to sio, and at the same time the sio data is fetched into the accumulator and the serial transfer is started. mov xa, @hl ; fetch send data from ram sel mb15 ; or clr1 mbe xch xa, sio ; exchange send data with receive data and start transfer (11) points to note concerning sbi mode (a) detection of the slave selected/non-selected state is performed by detection of a match with a slave address received after bus release (when reld = 1). an address match interrupt (irqcsi) generated when wup = 1 is normally used for this match detection. therefore, detection of selection/non-selection by slave address should be performed with wup = 1. (b) for selection/non-selection detection without using an interrupt when wup = 0, the address detection method is not used, but instead detection should be performed by transmission/reception of commands set beforehand by the program. (c) when wup is set to 1 during busy signal output, busy is not released. with the sbi, the busy signal is output following a busy release directive until the next fall of the serial clock (sck). when wup is set to 1, a check must be performed to ensure that sb0 (sb1) has been driven high after busy is released before setting wup to 1.
181 chapter 5 peripheral hardware functions (12) sbi mode applications this section introduces an example of applications in which serial data communication is performed in the sbi mode. in this application example the m pd75308 can operate as either the master cpu or a slave cpu on the serial bus. also, the master can be changed by a command. (a) serial bus configuration in the serial bus configuration in the application example given here the m pd75308 is assumed to be connected to the bus line as one of the devices on the serial bus. tw o m pd75308 pins are used: the serial data bus sb0 (p02/so) and the serial clock sck (p01). a serial bus configuration example is shown in figure 5-63. figure 5-63. example of serial bus configuration master cpu pd75308 m sb0 (sb1) sck slave cpu pd75308 m sb0 (sb1) sck address 1 slave cpu sb0 (sb1) sck address 2 slave ic sb0 (sb1) sck address n v dd
182 chapter 5 peripheral hardware functions (b) description of commands (i) command types in this application example the following commands are set. 1 read command : performs data transfer from slave to master. 2 write command : performs data transfer from master to slave. 3 end command : indicates write command completion to slave. 4 stop command : indicates write command suspension to slave. 5 status command : read slave-side status. 6 reset command : sets currently selected slave to non-selected status. 7 chgmst command : transfers mastership to slave side. (ii) communication procedure the procedure for communication between master and slave is shown below. 1 the master starts communication by sending the address of the slave it wishes to communicate with to select the slave (chip selection). the slave which receives the address returns ack and performs communication with the master (changes from non-selected to selected status). 2 communication is performed between the slave selected in 1 and the master by transferring commands and data. since command and data transfer is performed between master and slave on a one-to-one basis, the other slaves must be in the non-selected status. 3 communication is terminated when the slave changes to the non-selected status. this happens in the following cases: ? when a reset command is sent from the master the selected slave changes to non- selected status. ? when the master is changed by the chgmst command, the device which changes from master to slave assumes the non-selected status.
183 chapter 5 peripheral hardware functions (iii) command format the transfer format of each command is shown below. 1 read command this command performs a read from a slave. a variable number of data bytes between 1 and 256 can be read; the number of data bytes is specified as a parameter from the master. if 00h is specified as the number of data bytes, a 256-byte data transfer is regarded as having been specified. figure 5-64. read command transfer format read m command ack s number of data bytes m data ack s s data data 0 ack s s data data n ack s ..... remark m : output by master s : output by slave after receiving the number of data bytes, if the transmissible data is not less than that number of data bytes the slave returns ack. if there is insufficient data, ack is not returned and an error is generated. when the master receives data it sends ack to the slave for each byte received.
184 chapter 5 peripheral hardware functions 2 write, end and stop commands these commands are used to write data to a slave. a variable number of data bytes between 1 and 256 can be written: the number of data bytes is specified as a parameter from the master. if 00h is specified as the number of data bytes, a 256-byte data transfer is specified. figure 5-65. write and end command transfer format remark m : output by master s : output by slave after receiving the number of data bytes, if the receive data storage area is not less than that number of data bytes the slave returns ack. if the storage area is insufficient, ack is not returned and an error is generated. when the master has sent all the data it sends and end command. the end command informs the slave that all the data has been transferred correctly. the slave also receives an end command before all data has been received. in this case data received up to reception of the end command is valid. in data transmission, the master compares the sio contents before and after transmission to check whether the data has been correctly output to the bus. if the pre-transmission and post-transmission sio contents are different, the master sends a stop command to suspend the data transfer. figure 5-66. stop command transfer format write m command ack s number of data bytes m data ack sm data data 0 ack sm data data n ack s ..... m command end ack s data m data ack s m command ack s stop data check error generation data transfer suspended remark m : output by master s : output by slave when the slave receives the stop command, it invalidates the data byte received immediately prior to the command.
185 chapter 5 peripheral hardware functions 3 status command this command reads the currently selected slave status. figure 5-67. status command transfer format when the master receives status data it returns ack to the slave. status m data ack s s command ack s status remark m : output by master s : output by slave the format of the status byte returned by the slave is shown below. figure 5-68. status command status format 7 status 6543210 msb lsb bit indicating data transmission possible 0: no send data 1: one or more send data bytes bit indicating data reception possible 0: no receive data storage area 1: at least 1-byte receive data storage area available bit indicating error generation 0: no error 1: error generated in previous transfer bit indicating master change possible 0: master change not possible 1: master change possible all 0
186 chapter 5 peripheral hardware functions 4 reset command this command changes the currently selected slave to the non-selected status. transmission of the reset command allows all slaves to be set to the non-selected status. figure 5-69. reset command transfer format remark m : output by master s : output by slave 5 chgmst command this command passes mastership to the currently selected slave. figure 5-70. chgmst command transfer format remark m : output by master s : output by slave when the slave receives the chgmst command it determines whether it is able to accept mastership, and returns data to the master. this data is as follows: ? 0ffh : master change possible ? 00h : master change not possible when data is transferred the slave compares the pre-transfer and post-transfer contents of sio: if they do not match it does not return ack and an error is generated. when the master receives data it returns ack to the slave. if the receive data is 0ffh, it henceforth operates as a slave. after the slave sends 0ffh data and ack is returned from the master, it operates as the master. chgmst m command ack s s data ack s data m command ack s reset
187 chapter 5 peripheral hardware functions (iv) error generation operation in the event of a communication error is described below. a slave notifies the master of error generation by not returning ack. only when the slave is receiving, when an error is generated the error indication bit in the status byte is set and all executing command processing is canceled. after transmission of one byte is completed the master checks for ack from the slave. if ack is not returned from the slave within a specific time after completion of transmission an error is judged to have been generated and the master output an ack signal (as a dummy). figure 5-71. master and slave operation in case of error generation sb0 error data ack transmission completed jubges error to have been generated and suspends processing. ack wait time checks for ack from slave transfer completed start ack check master processing slave processing judges error to have been generated and outputs ack error are as follows: ? errors generated on slave side 1 error in command transfer format 2 reception of undefined command 3 insufficient data transferred in read command 4 insufficient data storage area in write command 5 data change during data transmission by a read, status or chgmst command when any of 1 through 5 occurs, ack is not returned to the master by the slave. ? errors generated on master side when data changes during write command data transmission, a stop command is sent to the slave.
188 chapter 5 peripheral hardware functions 5.6.8 sck pin output manipulation as an output latch is incorporated in the sck/p01 pin, it can be used for static output by means of software in addition to its normal serial clock function. in addition, p01 output latch manipulation allows the sck number to be set to any desired value by software (so/sb0 and si/sb1 pin control is performed by the relt and cmdt bits of sbic). the method of manipulating the sck/p01 pin is shown below. 1 the serial operating mode register (csim) is set (sck pin: output mode; serial operation: possible). while serial transfer is suspended, sck = 1. 2 the p01 output latch is manipulated by a bit manipulation instruction. example to output one sck clock cycle by software. sel mb15 ; or clr1 mbe mov xa, #00000011b ; sck (f x /2 3 ), output mode mov csim, xa clr1 0ff0h.1 ; sck/p01 0 set1 0ff0h.1 ; sck/p01 1 figure 5-72. sck/p01 pin configuration to internal circuit p01/sck p01 output latch from serial clock control circuit sck sck pin output mode address ff0h. 1 the p01 output latch is mapped onto bit 1 of address ff0h. reset signal generation sets the p01 output latch to 1. cautions 1. the p01 output latch must be set to 1 during a normal serial transfer. 2. the p01 output latch address cannot be specified as port0.1 as shown below. the address (0ff0h.1) must be written directly as the operand. however, when the instruction is executed, mbe = 0 or (mbe = 1 and msb = 15) needs to be set beforehand. clr1 port0.1 cannot be used set1 port0.1 clr1 0ff0h.1 can be used set1 0ff0h.1
189 chapter 5 peripheral hardware functions 5.7 lcd controller/driver 5.7.1 lcd controller/driver configuration the m pd75308 incorporates a display controller which generates segment signals and common signals in accordance with data in display data memory, and a segment driver and common driver which can directly drive an lcd panel. the configuration of the lcd controller/driver is shown in figure 5-73.
190 chapter 5 peripheral hardware functions figure 5-73. lcd controller/driver block diagram timing controller 8 display mode register 4 display control register 4 1f9h 3 3 2 2 1 1 0 0 s24/bp0 1f8h 3 3 2 2 1 1 0 0 s23 1e0h 3 3 2 2 1 1 0 0 s0 1feh 3 3 2 2 1 1 0 0 s30/bp6 1ffh 3 3 2 2 1 1 0 0 s31/bp7 display data memory multiplexer com3 com2 com1 com 0 v lc2 v lc1 v lc0 selector lcd drive voltage controller common driver segment driver 4 port 3 output latch 1 0 p31/ sync 8 port mode register group a 1 0 p30/ lcdcl f lcd
191 chapter 5 peripheral hardware functions 5.7.2 lcd controller/driver function the functions of the lcd controller/driver incorporated in the m pd75308 are described below. (a) generates segment signals and common signals by automatically reading display data memory using dma operations. (b) one of 5 display modes can be selected: 1 static 2 1/2 duty (2-time division) 1/2 bias 3 1/3 duty (3-time division) 1/2 bias 4 1/3 duty (3-time division) 1/3 bias 5 1/4 duty (4-time division) 1/3 bias (c) in each display mode there is a choice of 4 frame frequencies. (d) maximum of 32 segment signal outputs (s0 to s31); 4 common outputs (com0 to com3) (e) segment signal outputs (s24 to s27, s28 to s31) can be switched to output ports (bp0 to bp3, bp4 to bp7) in 4-line units. (f) on-chip division resistor available (mask option) for lcd drive power supply. ? various bias module, allowing correspondence to lcd drive voltage ? current to division resistor is cut when display is off. (g) display data memory not used for display can be used as normal data memory. (h) operation possible using subsystem clock the maximum number of pixels which can be displayed in each display mode is shown in table 5-11. table 5-11. maximum number of display pixels bias modulus time division common signal used maximum number of pixels C static com0 (com1, 2, 3) 32 (32 segment x 1 common) note 1 1/2 2 com0, 1 64 (32 segment x 2 common) note 2 3 com0, 1, 2 96 (32 segment x 3 common) note 3 1/3 3 4 com0, 1, 2, 3 128 (32 segment x 4 common) note 4 notes 1. with . shaped lcd panel, 4 digits at 8 segment signals per digit. 2. with . shaped lcd panel, 8 digits at 4 segment signals per digit. 3. with . shaped lcd panel, 10 digits at 3 segment signals per digit. 4. with . shaped lcd panel, 16 digits at 2 segment signals per digit.
192 chapter 5 peripheral hardware functions 5.7.3 display mode register the display mode register (lcdm) is an 8-bit register which specifies the display mode, lcd clock, frame frequency, segment output/bit port output selection, and display output on/off control. lcdm is set by an 8-bit memory manipulation instruction. only bit 3 (lcdm3) can be set or cleared by a bit manipulation instruction. generation of the reset signal clears all bits to 0. figure 5-74. display mode register format (1/2) display mode selection lcdm3 lcdm2 lcdm1 lcdm0 number of bias modulus time divisions 0 x x x display off note 100041/3 100131/3 101021/2 101131/2 1100 static other than above setting prohibited note all segment signals at non-selected level lcd clock selection lcdm5 lcdm4 lcdcl 00f w /2 9 (64 hz) 01f w /2 8 (128 hz) 10f w /2 7 (256 hz) 11f w /2 6 (512 hz) caution lcdcl is supplied only when the watch timer is operating. when the lcd controller is used, bit 2 of the watch mode register wm should be set (1) 7 6 5 4 3 2 1 0 lcdm0 lcdm1 lcdm3 lcdm2 lcdm4 lcdm5 lcdm6 lcdm7 address lcdm f8ch symbol
193 chapter 5 peripheral hardware functions figure 5-74. display mode register format (2/2) segment output/bit port output switchover specification lcdm7 lcdm6 s24 to s27 s28 to s31 number of segment outputs number of bit port outputs 0 0 segment output segment output 32 0 0 1 segment output bit port output 28 4 1 0 bit port output segment output 28 4 1 1 bit port output bit port output 24 8 frame frequency (hz) lcdcl f w /2 9 f w /2 8 f w /2 7 f w /2 6 display duty (64 hz) (128 hz) (256 hz) (512 hz) static 64 128 256 512 1/2 32 64 128 256 1/3 21 43 85 171 1/4 16 32 64 128 remark when f w = 32.768 khz f w : input clock to watch timer (f x /128 or f xt )
194 chapter 5 peripheral hardware functions 5.7.4 display control register the display control register (lcdc) performs the following lcd drive control functions. ? enabling/disabling common and segment outputs ? cutting current to division resistor for lcd drive power supply ? enabling/disabling output of synchronization clock (lcdcl) and synchronization signal (sync) to controller/ driver for external segment signal extension the lcdc register is set by a 4-bit memory manipulation instruction. generation of the reset signal clears (0) the entire display control register figure 5-75. display control register format display output status of lcdc0 and lcdm3 lcdc0 0 1 lcdm3 x 0 1 com0 to com3 outputs l (display off) outputs common signal outputs common signal corresponding to display corresponding to display mode. mode. s0 to s23 outputs l. (display off) outputs segment signal outputs segment signal corresponding to display corresponding to display s24 to s31 segment mode. (non-selected level mode. (display off) specification pins output, display off) s24 to s32 bit port outputs contents of bit 0 of outputs contents of bit 0 of outputs contents of bit 0 of specification pins corresponding display data corresponding display data corresponding display data memory. (bit port function) memory. (bit port function) memory. (bit port function) power supply to division off (high impedance) note on (high level) note on (high level) note resistor (bias pin output) note items in parentheses apply when split resistor for lcd drive power supply is not incorporated. lcdcl and sync signal output enable/disable bit lcdc2 0 lcdcl and sync signal output disabled 1 lcdcl and sync signal output enabled caution lcdcl and sync signal outputs are provided for future system expansion. at present these signal outputs should be disabled. 3 2 1 0 lcdc0 0 0 lcdc2 address lcdc f8eh symbol
195 chapter 5 peripheral hardware functions 5.7.5 display data memory display data memory is mapped onto addresses 1e0h through 1ffh. display data memory is a memory area which the lcd controller/driver reads by dma operations irrespective of cpu operation. the lcd controller controls segment signals according to the data in display data memory. when s24 through s31 are used as bit ports, the content of bit 0 of the data written into addresses 1f8h to 1ffh of display data memory is output from each bit port output pin. the area which is not used as lcd display ports can be used as ordinary data memory. display data memory can be manipulated bit by bit or in 4-bit units. it cannot be manipulated in 8-bit units. the correspondence between each bit of display data memory and segment outputs and bit port outputs is shown in figure 5-77. figure 5-76. data memory map 000h 100h 0ffh 200h 1ffh 300h 2ffh 3ffh 1e0h data memory 256 4 224 4 32 4 256 4 256 4 display data memory bank 0 bank 1 bank 2 note bank 3 note note banks 2 and 3 are provided on the m pd75312b, 75316b, 75p316a, 75p316b only.
196 chapter 5 peripheral hardware functions figure 5-77. correspondence between display data memory and common segments 1f8h 1f9h 1fah 1fbh 1fch 1fdh 1feh 1ffh bp0 bp1 bp2 bp3 bp4 bp5 bp6 bp7 s24/bp0 s25/bp1 s26/bp2 s27/bp3 s28/bp4 s29/bp5 s30/bp6 s31/bp7 com0 com1 com2 com3 1e0h 1e1h 1e2h 1e3h s0 s1 s2 s3 b 0 b 1 b 2 b 3 address display data memory segment outputs/bit port outputs common signals
197 chapter 5 peripheral hardware functions 5.7.6 common signals and segment signals a picture element of the lcd panel is illuminated when the potential difference between the corresponding common signal and segment signal reaches or exceeds a preset voltage (lcd drive voltage v lcd ). when the potential difference falls to less than v lcd or 0 v, the picture element is extinguished. since deterioration results from adding a dc voltage to the common signal and segment signal, the lcd panel is driven by an ac voltage. (1) common signals common signals have the selection timing order shown in table 5-12 corresponding to the assigned number of time divisions, with repeated operation of these performed as one cycle. in the static mode, the same signal is output for com0, 1, 2, and 3. in the case of two time divisions, the com2 and com3 pins should be left open; with 3 time divisions, the com3 pin should be left unconnected. table 5-12. common signals common number of signals com0 com1 com2 com3 time divisions static 2 leave unconnected leave unconnected 3 leave unconnected 4 (2) segment signals segment signals are carried on 32 lines corresponding to 32 locations of the display data area (1e0h to 1ffh) in data memory. bits 0 through 3 of each location are automatically read in synchronization with com0 through com3 selection timing respectively, then if the value of the bit is 1 conversion to the selection voltage is performed, and if 0 conversion to the non-selection voltage is performed, for output from the segment pins (s0 through s31). from the above, confirmation is made of the combination of lcd panel front electrode (corresponding to the segment signal) and rear electrode (corresponding to the common signal) used to form a display pattern, then bit data corresponding one-to-one with the pattern to be displayed is written into the display data area. as the following bits of the display area are not accessed, they can be used for purpose other than display: bits 1/2/3 in the static system, bits 2/3 in the 2-time-division system, and bit 3 in the 3-time- division system.
198 chapter 5 peripheral hardware functions (3) common signal and segment signal output waveforms the voltage levels shown in tables 5-13 through 5-15 are output in the common signals and segment signals. the +v lcd /Cv lcd illumination voltage results only when both reach the selection voltage; other combinations result in the extinguished voltage. table 5-13. lcd drive v oltages (static) common segment signal selection non-selection signal com0 sn v lc0 /v ss v ss /v lc0 v ss /v lc0 +v lcd /Cv lcd 0 v/0 v table 5-14. lcd drive voltages (1/2 bias modulus) common segment signal selection non-selection signal comm sn v lc0 /v ss v ss /v lc0 selection v ss /v lc0 +v lcd /Cv lcd 0 v/0 v non-selection v lc1 = v lc2 +1/2v lcd /C1/2v lcd C1/2v lcd /+1/2v lcd table 5-15. lcd drive voltage (1/3 bias modulus) common segment signal selection non-selection signal comm sn v lc0 /v ss v lc2 /v lc1 selection v ss /v lc0 +v lcd /Cv lcd +1/3v lcd /C1/3v lcd non-selection v lc1 /v lc2 +1/3v lcd /C1/3v lcd C1/3v lcd /+1/3v lcd
199 chapter 5 peripheral hardware functions figures 5-78 through 5-80 show the common signal waveforms, and figure 5-81 shows the voltage and phase of the common signal and the segment signal. figure 5-78. common signal waveform (static) v lc0 v ss (static) v lcd com0 t f = t t : 1 lcdcl cycle t f : frame cycle figure 5-79. common signal waveform (1/2 bias modulus) v lc0 v ss (3-time-divisions) v lcd v lc1, 2 comm t f = 3 t t : 1 lcdcl cycle t f : frame cycle v lc0 v ss (2-time-divisions) v lcd v lc1, 2 comm t f = 2 t v lc0 v lc1 v lc2 v ss v lcd comm (4-time-divisions) t f = 4 t t : 1 lcdcl cycle t f : frame cycle v lc0 v lc1 v lc2 v ss v lcd comm (3-time-divisions) t f = 3 t figure 5-80. common signal waveform (1/3 bias modulus)
200 chapter 5 peripheral hardware functions figure 5-81. voltage and phase of common signal and segment signal (a) 1/3 bias modulus (b) 1/2 bias modulus v lc0 v lc1 v lc2 v ss common signal v lcd v lc0 v lc1 v lc2 v ss v lcd segment signal selection non-selection t: 1 lcdcl cycle t t v lc0 v lc1, 2 v ss v lcd v lc0 v ss v lcd selection non-selection t t v lc1, 2 (c) static display mode v lc0 v ss common signal v lc0 segment signal selection non-selection t t v lcd v lcd v ss
201 chapter 5 peripheral hardware functions 5.7.7 lcd drive power v lc0 , v lc1 , v lc2 supply in the m pd75308, a division resistor can be incorporated within pins v lc0 through v lc2 for the lcd drive power supply, allowing lcd drive power corresponding to each bias modulus to be supplied without an external division resistor. there is also a bias pin corresponding to the various lcd drive voltages; the bias pin and the v lc0 pin are connected externally. the values shown in the following table are supplied as appropriate lcd drive power for the static, 1/2 and 1/3 bias modulus modes. table 5-16. lcd drive power supply values lcd bias modulus no bias 1/2 1/3 drive power (static display mode) v lc0 v lcd v lcd v lcd v lc1 2/3v lcd 1/2v lcd note1 2/3v lcd v lc2 1/3v lcd 1/3v lcd v ss 0 v0 v0 v notes 1. in 1/2 bias mode, the v lc1 and v lc2 pins must be connected externally. 2. when bias pin and v lc0 pin are open, v lcd = 3/5v dd (it is necessary to incorporate division resistor by mask option). when bias pin and v lc0 pin are connected, v lcd = v dd . figures 5-82 and 5-83 show lcd drive power supply examples based on table 5-16. also, the current flowing in the division resistor can be cut by clearing (0) bit 0 (lcdc0) of the display control register. on/off control of this lcd power supply is also effective in preventing the lcd clock from being stopped by a stop command (when the system clock has been selected) and a dc voltage from being applied to the lcd when the watch timer is operating by means of the main system clock. in other words, by clearing (0) bit 0 (lcdc0) of the display control register and setting all lcd drive power supplies to the same potential, v ss , directly before execution of the stop instruction, it is possible to prevent the occurrence of a potential difference between the lcd electrodes even if the lcd clock stops. when the watch timer is operated by means of a subsystem clock, continuous lcd display is possible.
202 chapter 5 peripheral hardware functions figure 5-82. examples of lcd drive power supply connection (with on-chip division resistor) (a) 1/3 bias modulus and static display mode (b) 1/2 bias modulus (example of v dd = 5 v, v lcd = 3 v) (example of v dd = 5 v, v lcd = 5 v) (c) 1/3 bias modulus and static display mode (example of v dd = 5 v, v lcd = 5 v) lcdc0 v dd 2r r v lc0 bias pin r v lc1 r v lc2 v ss v lcd v lcd = 3/5 v dd pd75308 m lcdc0 v dd 2r r v lc0 bias pin r v lc1 r v lc2 v ss v lcd v lcd = v dd pd75308 m lcdc0 v dd 2r r v lc0 r v lc1 r v lc2 v ss v lcd v lcd = v dd pd75308 m bias pin
203 chapter 5 peripheral har d w are functions figure 5-83 . examples of lcd drive p o wer supply connection (with external division resistor) (a ) static display mode note (b ) static display mode (example o f v d d = 5 v , v lcd = 5 v ) (exampl e o f v dd = 5 v , v lc d = 3 v ) cautio n t o turn off the lcd panel , c lear lcdm3 to issue a non-select signal. lcdc0 v dd v lc0 bias pin v lc1 v lc2 v ss v lcd v lcd = v dd pd75308 m lcdc0 v dd 2r 3r v lc0 bias pin v lc1 v lc2 v ss v lcd v lcd = 3/5 v dd pd75308 m note lcdc0 should always be set to 1 (including when in standby mode). if lcdc0 is set to off while lcd display is performed, a dc voltage is applied to the lcd panel. (c ) 1/2 bias modulus (d ) 1/3 bias modulus ( v dd = 5 v , v lc d = 2. 5 v ) ( v dd = 5 v , v lc d = 3 v ) lcdc0 v dd 2r r v lc0 bias pin v lc1 r v lc2 v ss v lcd v lcd = 1/2 v dd pd75308 m lcdc0 v dd 2r r v lc0 bias pin r v lc1 r v lc2 v ss v lcd v lcd = 3/5 v dd pd75308 m
204 chapter 5 peripheral hardware functions 5.7.8 display modes (1) static display example figure 5-85 shows the connection between a static type 4-digit lcd panel with the display pattern shown in figure 5-84, and the m pd75308s segment signals (s0 to s31) and common signal (com0). the display example is 123.4, and the contents of the display data memory (addresses 1e0h through 1ffh) correspond to this value. here, the second digit 3. ( .) is considered for the sake of explanation. in accordance with the display pattern in figure 5-84, using the com0 common signal timing, the selection and non-selection voltages shown in table 5-17 must be output to pins s8 through s15. table 5-17. selection/non-selection voltages for pins s8 to s15 (static display example) segment s8 s9 s10 s11 s12 s13 s14 s15 common com0 selection selection selection selection non-selection selection non-selection selection from this it can be seen that it is only necessary to set up 11110101 in bit 0 of the display data memory addresses (1e8h through 1efh) corresponding to s8 through s15. the lcd drive waveforms for s11, s12 and com0 are shown in figure 5-86. it can be seen that when s11 reaches the selection voltage in synchronization with com0 selection timing, a +v lcd /Cv lcd (lcd illumination level) ac square wave is generated. as the same waveform is output to com1 through com3 as to com0, the drive performance can be increased by connecting com0 through com3. figure 5-84. static type lcd display pattern and electr ode wiring seg n + 3 seg n + 7 com0 seg n + 2 seg n + 5 seg n + 1 seg n seg n + 4 seg n + 6
205 chapter 5 peripheral hardware functions figure 5-85. static lcd p anel wiring example 0 x x x 1 x x x 1 x x x 0 x x x 1 x x x 1 x x x 0 x x x 0 x x x 1 x x x 1 x x x 1 x x x 1 x x x 0 x x x 1 x x x 0 x x x 1 x x x 0 x x x 0 x x x 1 x x x 1 x x x 0 x x x 0 x x x 1 x x x 1 x x x 0 x x x 1 x x x 1 x x x 0 x x x 0 x x x 0 x x x 0 x x x 0 x x x s0 s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 s12 s13 s14 s15 s16 s17 s18 s19 s20 s21 s22 s23 s24 s25 s26 s27 s28 s29 s30 s31 1e0h 1 2 3 4 5 6 7 8 9 a b c d e f 1f0h 1 2 3 4 5 6 7 8 9 a b c d e 1ffh bit0 bit1 bit2 bit3 com3 com2 com1 com0 timing strobe pd75308 m can be shorted lcd panel data memory address
206 chapter 5 peripheral hardware functions figure 5-86. example of static lcd drive waveforms v lc0 v ss com0 t f v lc0 v ss s11 v lc0 v ss s12 + v lcd 0 com0 ?s11 ?v lcd + v lcd 0 com0 ?s12 ?v lcd
207 chapter 5 peripheral hardware functions (2) 2-time-division display example figure 5-88 shows the connection between a 2-time-division type 8-digit lcd panel with the display pattern shown in figure 5-87, and the m pd75308s segment signals (s0 to s31) and common signals (com0 and com1). the display example is 123456.78, and the contents of the display data memory (addresses 1e0h through 1ffh) correspond to this value. here, the third digit 6. ( .) is considered for the sake of explanation. in accordance with the display pattern in figure 5-87, using the com0 and com1 common signal timing, the selection and non-selection voltages shown in table 5-18 must be output to pins s8 through s11. table 5-18. selection/non-selection voltages for pins s8 to s11 (2-time-division display example) segment s8 s9 s10 s11 common com0 selection non-selection selection selection com1 selection selection selection selection from this it can be seen that it is only necessary to set up, for example xx10 in the display data memory (address 1e9h) corresponding to s9. an example of the lcd drive waveforms between s9 and each common signal is shown in figure 5-89. it can be seen that when s9 reaches the selection voltage in synchronization with com1 selection timing, a +v lcd /Cv lcd (lcd illumination level) ac square wave is generated. figure 5-87. 2-time-division type lcd display pattern and electr ode wiring com0 com1 s n + 1 s n s n + 2 s n + 3
208 chapter 5 peripheral hardware functions figure 5-88. 2-time-division lcd p anel wiring example 1 0 x x 1 1 x x 1 1 x x 1 1 x x 1 0 x x 1 0 x x 1 1 x x 0 0 x x 1 1 x x 0 1 x x 1 1 x x 1 1 x x 1 0 x x 0 1 x x 1 1 x x 0 1 x x 1 0 x x 1 1 x x 1 0 x x 0 0 x x 1 0 x x 1 1 x x 0 1 x x 0 1 x x 0 0 x x 1 1 x x 0 1 x x 1 1 x x 1 0 x x 1 0 x x 0 0 x x 0 0 x x s0 s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 s12 s13 s14 s15 s16 s17 s18 s19 s20 s21 s22 s23 s24 s25 s26 s27 s28 s29 s30 s31 1e0h 1 2 3 4 5 6 7 8 9 a b c d e f 1f0h 1 2 3 4 5 6 7 8 9 a b c d e 1ffh bit0 bit1 bit2 bit3 com3 com2 com1 com0 timing strobe pd75308 m lcd panel data memory address open open remark x: as this is a 2-time-division display, any data can be stored here at all times.
209 chapter 5 peripheral hardware functions figure 5-89. example of 2-time-division lcd drive waveforms (1/2 bias modulus) v lc0 v lc1, 2 v ss com0 t f v lc0 v lc1, 2 v ss com1 v lc0 v lc1, 2 v ss s9 com0 ?s9 + v lcd + 1/2 v lcd 0 ?1/2 v lcd ?v lcd com1 ?s9 + v lcd + 1/2 v lcd 0 ?1/2 v lcd ?v lcd
210 chapter 5 peripheral hardware functions (3) 3-time-division display example figure 5-91 shows the connection between a 3-time-division type 10-digit lcd panel with the display pattern shown in figure 5-90, and the m pd75308s segment signals (s0 to s29) and common signals (com0 to com2). the display example is 123456.7890, and the contents of the display data memory (addresses 1e0h through 1fdh) correspond to this value. here, the fifth digit 6. ( .) is considered for the sake of explanation. in accordance with the display pattern in figure 5-90, using the com0, com1 and com2 common signal timings, the selection and non- selection voltages shown in table 5-19 must be output to pins s12 through s14. table 5-19. selection/non-selection voltages for pins s12 to s14 (3-time-division display example) segment s12 s13 s14 common com0 non-selection selection selection com1 selection selection selection com2 selection selection non-selection from this it can be seen that it is only necessary to set up x110 in the display data memory (address 1ech) corresponding to s12. the lcd drive waveforms between s12 and each common signal are shown in figure 5-92 (1/2 bias modulus) and 5-93 (1/3 bias modulus). it can be seen that when s12 is at the selection voltage in synchronization with com1 selection timing, a +v lcd /Cv lcd (lcd illumination level) ac square wave is generated. figure 5-90. 3-time-division type lcd display pattern and electr ode wiring com1 seg n + 1 seg n + 2 seg n com0 com2
211 chapter 5 peripheral hardware functions figure 5-91. 3-time-division lcd p anel wiring example 1 1 0 x 1 0 1 x 1 1 x' x 1 1 0 x 1 1 0 x 1 0 x' x 1 1 0 x 1 1 1 x 1 1 x' x 1 1 0 x 1 0 0 x 1 0 x' x 0 1 1 x 1 1 1 x 1 1 x' x 0 1 0 x 1 1 1 x 1 0 x' x 1 1 0 x 0 1 0 x 1 0 x' x 1 1 0 x 1 1 1 x 0 0 x' x 1 0 0 x 1 1 1 x 0 1 x' x 1 1 0 x 0 0 0 x 0 0 x' x s0 s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 s12 s13 s14 s15 s16 s17 s18 s19 s20 s21 s22 s23 s24 s25 s26 s27 s28 s29 1e0h 1 2 3 4 5 6 7 8 9 a b c d e f 1f0h 1 2 3 4 5 6 7 8 9 a b c d e 1ffh bit0 bit1 bit2 bit3 com3 com2 com1 com0 timing strobe pd75308 m lcd panel data memory address open remark x : as there is no segment corresponding to the lcd panel, any data can be stored here. x : as this is a 3-time-division display, any data can be stored here at all times.
212 chapter 5 peripheral hardware functions figure 5-92. example of 3-time-division lcd drive waveforms (1/2 bias modulus) v lc0 v lc1, 2 v ss com0 t f v lc0 v lc1, 2 v ss com1 v lc0 v lc1, 2 v ss com2 v lc0 v lc1, 2 v ss s12 + v lcd + 1/2 v lcd 0 com0 e s12 e 1/2 v lcd e v lcd + v lcd + 1/2 v lcd 0 e 1/2 v lcd e v lcd + v lcd + 1/2 v lcd 0 e 1/2 v lcd e v lcd com1 e s12 com2 e s12
213 chapter 5 peripheral hardware functions figure 5-93. example of 3-time-division lcd drive waveforms (1/3 bias modulus) v lc0 com0 v lc1 v lc2 v ss t f v lc0 com1 v lc1 v lc2 v ss v lc0 com2 v lc1 v lc2 v ss v lc0 s12 v lc1 v lc2 v ss + v lcd com0 ?s12 + 1/3 v lcd 0 ?1/3 v lcd ?v lcd + v lcd com1 ?s12 + 1/3 v lcd 0 ?1/3 v lcd ?v lcd + v lcd com2 ?s12 + 1/3 v lcd 0 ?1/3 v lcd ?v lcd
214 chapter 5 peripheral hardware functions (4) 4-time-division display example figure 5-95 shows the connection between a 4-time-division type 16-digit lcd panel with the display pattern shown in figure 5-94, and the m pd75308s segment signals (s0 to s31) and common signals (com0 to com3). the display example is 123456.7890123456, and the contents of the display data memory (addresses 1e0h through 1ffh) correspond to this value. here, the 11th digit 6. ( .) is considered for the sake of explanation. in accordance with the display pattern in figure 5-94, using the com0 through com3 common signal timings, the selection and non- selection voltages shown in table 5-20 must be output to pins s20 and s21. table 5-20. selection/non-selection voltages for pins s20 and s21 (4-time-division display example) segment s20 s21 common com0 selection selection com1 non-selection selection com2 selection selection com3 selection selection from this it can be seen that it is only necessary to set up 1101 in the display data memory (address 1f4h) corresponding to s20. the lcd drive waveforms between s20 and the com0 and com1 common signals are shown in figure 5-96 (for simplicity, waveforms to com2 and com3 are omitted). it can be seen that when s20 reaches the selection voltage in synchronization with com0 selection timing, a +v lcd /Cv lcd (lcd illumination level) ac square wave is generated. figure 5-94. 4-time-division type lcd display pattern and electr ode wiring com0 com1 com2 com3 seg n seg n + 1
215 chapter 5 peripheral hardware functions figure 5-95. 4-time-division lcd p anel wiring example 1 0 1 0 1 1 1 1 1 0 1 0 1 1 0 1 0 1 1 0 1 1 0 0 1 1 1 0 0 1 0 1 1 1 0 0 0 1 1 1 0 1 1 0 0 0 0 0 1 1 1 0 1 0 1 1 1 1 1 0 1 1 0 0 1 1 1 0 1 1 1 1 1 1 1 0 1 0 0 0 1 0 1 1 1 1 1 1 1 0 1 0 1 1 0 1 0 1 1 0 1 1 0 0 1 1 1 0 0 1 0 1 1 1 0 0 0 1 1 1 s0 s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 s12 s13 s14 s15 s16 s17 s18 s19 s20 s21 s22 s23 s24 s25 s26 s27 s28 s29 s30 s31 1e0h 1 2 3 4 5 6 7 8 9 a b c d e f 1f0h 1 2 3 4 5 6 7 8 9 a b c d e 1ffh bit0 bit1 bit2 bit3 com3 com2 com1 com0 timing strobe pd75308 m lcd panel data memory address 0 1 1 0 0 0 0 0
216 chapter 5 peripheral hardware functions figure 5-96. example of 4-time-division lcd drive waveforms (1/3 bias modulus) v lc0 com0 v lc1 v lc2 v ss t f v lc0 com1 v lc1 v lc2 v ss v lc0 com2 v lc1 v lc2 v ss v lc0 com3 v lc1 v lc2 v ss + v lcd com0 ?s20 + 1/3 v lcd 0 ?1/3 v lcd ?v lcd + v lcd com1 ?s20 + 1/3 v lcd 0 ?1/3 v lcd ?v lcd v lc0 s20 v lc1 v lc2 v ss
217 chapter 5 peripheral hardware functions 5.8 bit sequential buffer ... 16 bits the bit sequential buffer is special data memory for bit manipulations. in particular, bit manipulation by sequential modification of the address and bit specification is facilitated, making this facility useful for bit-wise processing of data comprising many bits. this data memory consists of 16 bits; bit manipulation instruction pmem.@l addressing can be used, and indirect bit specification is possible by means of the l register. in this case, processing can proceed while moving the specified bits sequentially by simply incrementing or decrementing the l register within the program loop. figure 5-97. bit sequential buffer format remark in pmem. @l addressing, the specification bit corresponding to the l register is moved. data manipulation is also possible using direct addressing. a combination of 1-bit, 4-bit, or 8-bit direct addressing and pmem. @l addressing can be used for continuous input or continuous output of 1-bit data, etc. in the case of 8-bit manipulation, the high-order and low-order 8 bits are handled separately by specifying bsb0 and bsb2. example to serially output two 16-bit data in buff 1, 2 from bit 0 of port 3. clr1 mbe mov xa, buff1 mov bsb0, xa ; set bsb0, 1 mov xa, buff2 mov bsb2, xa ; set bsb2, 3 mov l, #0 loop0: skt bsb0, @l ; test specified bit of bsb br loop1 nop ; dummy (timing adjustment) set1 port3.0 ; set bit 0 of port 3 br loop2 loop1: clr1 port3.0 ; clear bit 0 of port 3 nop ; dummy (timing adjustment) nop loop2: incs l ; l l + 1 br loop0 ret 3 2 1 0 bsb3 fc3h l = f l = c 3 2 1 0 bsb2 l = b l = 8 3 2 1 0 bsb1 l = 7 l = 4 3 2 1 0 bsb0 l = 3 l = 0 fc2h fc1h fc0h incs l decs l l register symbol address bit
218 chapter 5 peripheral hardware functions [memo]
219 chapter 6 interrupt function chapter 6 interrupt function the m pd75308 contains 6 vectored interrupt sources and 2 testable inputs, thus making various applications possible. the m pd75308 interrupt control circuit has the following characteristics, making extremely high-speed interrupt servicing possible. (a) can control enabling or disabling of reception, based on the interrupt master enable flag (ime) and interrupt enable flag (iexxx). (b) can arbitrarily set the interrupt servicing start address and the mbe to interrupt servicing, based on the vector table (actual interrupt service program starts earlier.) (c) can test and clear (can confirm the occurrence of an interrupt by means of the software) the interrupt request flag (irqxxx) (d) can cancel (can select the cancellation source by the interrupt enable flag) the standby mode (stop, halt) by means of the interrupt request. 6.1 interrupt control circuit configurations the interrupt control circuit configurations are shown in figure 6-1. each hardware is mapped in the data memory space.
220 chapter 6 interrupt function figure 6-1. interrupt control circuit block diagram internal bus interrupt enable flag (iexxx) irqbt irq4 irq0 irq1 irqcsi irqt0 irqw irq2 213 im2 im1 im0 double edge detection circuit edge detection circuit noise eliminator edge detection circuit int4 /p00 int0 /p10 int1 /p11 int bt intcsi intt0 intw selector rising edge detection circuit falling edge detection circuit int2 /p12 kr0/p60 kr7/p73 ... im2 ime ist0 vrqn priority control circuit vector table address generation circuit standby release signal decoder
221 chapter 6 interrupt function 6.2 interrupt source t ypes and vector table the interrupt source types and the interrupt vector table are shown in table 6-1 and figure 6-2 respectively. table 6-1. interrupt source types interrupt source internal/ interrupt vectored interrupt request signal external order note 1 (vector table address) intbt (basic time interval signal from basic interval timer) internal 1 vrq1 (0002h) int4 (both rising and falling edge detections are valid) external int0 (rising or falling detection edge selection) external 2 vrq2 (0004h) int1 external 3 vrq3 (0006h) intcsi (serial data transmission end signal) internal 4 vrq4 (0008h) intt0 (match signal between the programmable timer/ internal 5 vrq5 (000ah) counters count register and the module register) int2 note 3 (rising edge detection of the input to the int2 pin external testable input signal and falling edge detection of either of the inputs to (set irq2 and irqw.) kr0 to kr7) note 2 intw note 3 (signal from the watch timer) internal notes 1. the interrupt order means the order of priority given to multiple interrupt requests. 2. for details of int2, please refer to 6.3 (4) int2 and key interrupt 0 to 7 (kr0 to kr7) hardware . 3. this is a test source. it is affected by an interrupt enable flag in the same way as an interrupt source, but does not generate a vectored interrupt. figure 6-2. interrupt v ector table (1/2) (a) in the case of m m m m m pd75304, 75304b address 002h mbe 0 0 0 intbt/int4 start address (high-order 4 bits) intbt/int4 start address (low-order 8 bits) 004h mbe 0 0 0 int0 start address (high-order 4 bits) int0 start address (low-order 8 bits) 006h mbe 0 0 0 int1 start address (high-order 4 bits) int1 start address (low-order 8 bits) 008h mbe 0 0 0 intcsi start address (high-order 4 bits) intcsi start address (low-order 8 bits) 00ah mbe 0 0 0 intt0 start address (high-order 4 bits) intt0 start address (low-order 8 bits)
222 chapter 6 interrupt function figure 6-2 . interrupt v ector t a b l e (2/2) (b) in the case of mm mm m pd75306, 75306b, 75308, 75308b and 75p308 address 002h mbe 0 0 intbt/int4 start address (high-order 5 bits) intbt/int4 start address (low-order 8 bits) 004h mbe 0 0 int0 start address (high-order 5 bits) int0 start address (low-order 8 bits) 006h mbe 0 0 int1 start address (high-order 5 bits) int1 start address (low-order 8 bits) 008h mbe 0 0 intcsi start address (high-order 5 bits) intcsi start address (low-order 8 bits) 00ah mbe 0 0 intt0 start address (high-order 5 bits) intt0 start address (low-order 8 bits) (c) in the case of mm mm m pd75312, 75312b, 75316, 75316b, 75p316, 75p316a and 75p316b address 002h mbe 0 intbt/int4 start address (high-order 6 bits) intbt/int4 start address (low-order 8 bits) 004h mbe 0 int0 start address (high-order 6 bits) int0 start address (low-order 8 bits) 006h mbe 0 int1 start address (high-order 6 bits) int1 start address (low-order 8 bits) 008h mbe 0 intcsi start address (high-order 6 bits) intcsi start address (low-order 8 bits) 00ah mbe 0 intt0 start address (high-order 6 bits) intt0 start address (low-order 8 bits) in the table above, the interrupt order indicates the order of executing the interrupts when multiple interrupt requests occur simultaneously or when multiple interrupt requests are held. the interrupt servicing start address and the set value of the mbe in the interrupt servicing are written in the v ector table . the vector ta b le is set according to the assem b ler directi v e (ventn). example intbt/int4 vector table setting vent1 mbe = 0 , rbe = 0 , g o t ob t ---- 1234 1 v ector table of address 0002 2 mbe setting in interrupt servicing routine 3 make sure to set 0 for rbe. 4 symbol indicating the start address of the interrupt servicing routine
223 chapter 6 interrupt function cautions 1. the vector table address set by the ventn (n = 1 to 5) instruction is 2n. 2. in the ventn instruction, make sure to set 0 for rbe. example vector table setting of intbt/int4 and intt0 vent1 mbe = 0, rbe = 0, gotobt vent5 mbe = 0, rbe = 0, gotot0
224 chapter 6 interrupt function 6.3 v arious hard ware t ypes of interrupt control circuit (1) interrupt request flag and interrupt enable flag there are eight interrupt request flags (irqxxx) corresponding to interrupt sources (interrupt: 6, test: 2), as follows. int0 interrupt request flag (irq0) int1 interrupt request flag (irq1) int2 interrupt request flag (irq2) int4 interrupt request flag (irq4) bt interrupt request flag (irqbt) serial interface interrupt request flag (irqcsi) timer/event counter interrupt request flag (irqt0) watch timer interrupt request flag (irqw) the interrupt request flag is set (1) when the interrupt request occurs, and then cleared automatically (0) when the interrupt servicing is executed. however, the irqbt and the irq4 differ in their clearance operations because they share the same vector table (refer to 6.6 v ector address sharing interrupt servicing ). there are eight interrupt enable flags (iexxx) corresponding to interrupt request flags, as follows. int0 interrupt enable flag (ie0) int1 interrupt enable flag (ie1) int2 interrupt enable flag (ie2) int4 interrupt enable flag (ie4) bt interrupt enable flag (iebt) serial interface interrupt enable flag (iecsi) timer/event counter interrupt enable flag (iet0) watch timer interrupt enable flag (iew) the interrupt enable flag is provided for each interrupt request flag. an interrupt is enabled if the contents are 1 but disabled if 0. if the interrupt request flag is set and the interrupt enable flag is enabling the interrupt, the vectored interrupt request (vrqn) is generated. this signal is used even in the release of the standby mode. the interrupt request flag and the interrupt enable flag are operated by the bit manipulation instruction and 4-bit memory manipulation instruction. in the case of the bit manipulation instruction, direct operations are always possible regardless of the mbe setting. the interrupt enable flag is operated by the ei iexxx instruction and the di iexxx instruction. normally, the sktclr instruction is used in the interrupt request flag test. example ei ie0 ; enable int0 di ie1 ; disable int1 sktclr irqcsi ; if irqcsi is 1, the interrupt request flag is skipped and cleared if the interrupt request flag is set by the instruction, even if no interrupt has occurred, the vectored interrupt is executed as if the interrupt has occurred. the interrupt request flag and the interrupt enable flag are cleared (0) by the occurrence of the reset signal, thus disabling all the interrupts.
225 chapter 6 interrupt function table 6-2. interrupt request flag set signal interrupt interrupt request flag set signal interrupt request flag enable flag irqbt set with basic time interval signal by basic interval timer iebt irq4 set by either the rising or the falling edge detection of the int4/p00 pin input signal ie4 irq0 set by the edge detection of the int0/p10 pin input signal. the detection edge is select by ie0 the int0 mode register (im0). irq1 set by the edge detection of the int1/p11 pin input signal. the detection edge is selected ie1 by the int1 mode register (im1). irqcsi set by the serial data transmission operation end signal of the serial interface. iecsi irqt0 set by the match signal from the timer/event counter #0. iet0 irqw set by the signal from the watch timer. iew irq2 set by the rising edge detection of the int2/p12 pin input signal or the falling edge ie2 detection of either of the inputs to kr0/p60 to kr7/p73 pins (2) interrupt master enable flag (ime) the interrupt master enable flag specifies enabling/disabling of acknowledgment of all interrupts. ime is set (1) and reset (0) by the ei and di instructions respectively. when a reset signal is generated this flag is cleared to 0, and acknowledgement of all interrupts is disabled. figure 6-3. ime format interrupt master enable flag (ime) 3 ime address fb2h 0 all interrupts are disabled, and vectored interrupts are not initiated. 1 interrupt enabling/disabling is controlled by the corresponding interrupt enable flag.
226 chapter 6 interrupt function (3) int0, int1 and int4 hardware (a) the configuration of int0 is shown in figure 6-4 (a). this pin is an external interrupt input for which rising or falling edge detection can be selected int0 has a function for noise elimination by means of a sampling clock (refer to figure 6-5 input/ output timing of noise eliminator ). the noise eliminator eliminates as noise any pulse less than two sampling clock cycles note in width. however, a pulse that is at least one sampling clock cycle in width may be acknowledged as an interrupt signal depending on the timing at which sampling is performed (refer to figure 6-5 2 (a) ). a pulse that is two sampling clock cycles or more in width can definitely be acknowledged as an interrupt signal. int0 has two sampling clocks, f and f x /64, either of which can be selected and used. the selection is made by edge detection mode register bit 3 (im03) (refer to figure 6-6 (a) ). selection of the detected edge is performed by an edge detection mode register bit 0 (im00) and bit 1(im01). the format of im0 is shown in figure 6-6(a). im0 is set by a 4-bit manipulation instruction. generation of the reset signal clears all bits to 0 and selects the rising edge specification. note when sampling clock is f :2t cy when sampling clock is f x /64 : 128/f x cautions 1. int0 does not operate in the standby mode since sampling is performed by the clock. 2. because the int0/p10 pin is internally connected to a noise eliminator even when it is used as a port pin, input a pulse with a width of 2 cycles or more of the sampling clock to this pin. (b) the configuration of int1 is shown in figure 6-4(b). this pin is an external interrupt input for which rising or falling edge detection can be selected. selection of the detected edge is performed by an edge detection mode register (im1). the format of im1 is shown in figure 6-6(b). im1 is set by a bit manipulation instruction. generation of the reset signal clears all bits to 0 and selects the rising edge specification. (c) the configuration of int4 is shown in figure 6-4(c). this pin is an external interrupt input which is capable of both rising and falling edge detection.
227 chapter 6 interrupt function figure 6-4. configuration of int0, int1 and int4 (a) int0 hardware internal bus 4 im0 noise eliminator int0/p10 selector f f x /64 im03 edge detection circuit int0 (irq0 set signal) im01, im00 detection edge specification sampling clock selection input buffer f 2 (b) int1 hardware (c) int4 hardware internal bus 4 im1 detection edge specification input buffer edge detection circuit int1 (irq1 set signal) im10 int1/p11 internal bus input buffer both edge detection circuit int4 (irq4 set signal) int4/p00
228 chapter 6 interrupt function figure 6-5. input/output timing of noise eliminator eliminated as noise eliminated as noise t smp t smp t smp t smp t smp less than sampling cycle (t smp ) int0 shaped output int0 shaped output int0 shaped output int0 shaped output 1 to 2 times sampling cycle (a) (b) more than twice sampling cycle "l" "l" 1 2 3 h h l l l l h l h h l l l l remark t smp = t cy or 64/f x
229 chapter 6 interrupt function figure 6-6. format of edge detection mode registers (a ) int0 edge detection mode register (im0) cautio n since an interrupt request flag may be set when an edge detection mode register is modified, interrupts should be enabled after first disabling interrupts, then modifying the mode register and clearing the interrupt request flag with the clr1 instruction. when f x /64 is selected as the sampling clock by modifying im0, the interrupt request flag must be cleared after the elapse of 16 machine cycles following mode register modification. (b ) int1 edge detection mode register (im1) 3 2 1 0 im10 0 0 0 address im1 fb5h 0 rising edge specification 1 falling edge specification (c ) int2 edge detection mode register (im2) im20 im21 0 0 im2 fb6h im21 int2 interrupt source im20 0 int2 pin input rising edge specification 0 0 1 1 any krx pin input falling edge specification 0 1 1 kr4 to kr7 (4 pins) kr2 to kr7 (6 pins) kr0 to kr7 (8 pins) interrupt input pin int2 (1 pin) 3210 im0 0 im0 1 0 im03 address im 0 fb4h symbol 0 rising edge specificatio n 0 0 falling edge specificatio n 1 1 rising and falling edge specificatio n 0 1 ignored (interrupt request flag is not set. ) 1 0 1 f x /64 ( 15.3 s: 4.19 mhz operation ) f ( 0.95, 1.91, 15.3 s: 4.19 mhz operation ) edge detection specification sampling clock m m
230 chapter 6 interrupt function (4) int2 and key interrupt 0 to 7 (kr0 to kr7) hardware the configurations of int2 and kr0 through kr7 are shown in figure 6-7. there are two irq2 sets as follows, either of which can be selected by the edge detection mode register (im2). (a) int2 pin input rising edge detection irq2 is set when the rising edge of the int2 pin input is detected. (b) falling edge detection in input of any of pins kr0 to kr7 (key interrupt) pins to be used for interrupt input are selected by the edge detection mode register (im2) from kr0 to kr7. irq2 is set when a falling edge is detected in the input of any of the pins. caution when a low-level signal is input on at least one of the pins selected as falling edge detection pins, irq2 is not set even if a falling edge is input on another pin. the format of im2 is shown in figure 6-6(c). im2 is set by a 4-bit manipulation instruction. generation of the reset signal clears all bits to 0, selecting the int2 rising edge specification.
231 chapter 6 interrupt function figure 6-7. int2, kr0 to kr7 configurations kr7/p73 kr6/p72 kr5/p71 kr4/p70 kr3/p63 kr2/p62 kr1/p61 kr0/p60 int2/p12 internal bus 4 im2 falling edge detection circuit rising edge detection circuit selector int2 (lrq2 set signal) input buffer 2 im21, im20
232 chapter 6 interrupt function (5) interrupt status flag the interrupt status flag (ist0) shows the status of the processing currently being executed by the cpu and is included in the psw. as shown in table 6-3, the interrupt priority control circuit controls multiinterrupts, based on the contents of the flag. because ist0 can be changed by the 4-bit manipulation instruction or the bit manipulation instruction, it can also perform multiinterrupts by changing the status in execution. ist0 can be operated in terms of bit at all times regardless of the mbe setting. before operating ist0, make sure to disable the interrupt by executing the di instruction; after operation, make sure to enable the interrupt by executing the ei instruction. when receiving the interrupt, ist0 is saved in the stack memory together with other psws and then is automatically set to 1. when the reti instruction has been executed, the original ist0 value (0) is restored. when occurrence of the reset signal, the flag contents are cleared (0). table 6-3. ist0 and interrupt servicing status ist0 processing status cpu processing contents receivable interrupt request after receiving interrupt in execution ist0 0 status 0 normal program being processed all interrupt reception enabled 1 1 status 1 interrupt being serviced all interrupt reception disabled C
233 chapter 6 interrupt function 6.4 interrupt sequence if an interrupt occurs, it is serviced in the procedure shown in figure 6-8. figure 6-8. interrupt servicing procedure notes 1. ist0: interrupt status flag (psws bit 2; refer to table 6-3 ) 2. store, in each vector table, the interrupt service program start address and the mbe set value in starting the interrupt. interrupt (intxxx) occurs irqxxx set iexxx set? corresponding vrqn occur hold until iexxx is set no yes ime = 1 hold until ime is set no yes hold until servicing in execution is ended save pc and psw contents in the stack memory. set to pc and mbe the data note 2 in the vector table corresponding to the started vrqn. change ist0 contents to 1. reset the received irqxxx. (however, if the interrupt source shares the same vector address, refer to 6.6 .) jump to interrupt service program servicing start address yes no ist0 = 0 note 1
234 chapter 6 interrupt function 6.5 multiinterrupt servicing control the m pd75308 is capable of multiinterrupt in the following method. as table 6-3 shows, multiinterrupts are made possible by changing the interrupt status flag with the program, that is, by changing the interrupt servicing program ist0 to 0, and the status 0. ist0 is changed with the interrupt disabled by the di instruction beforehand. figure 6-9. multiinterrupt by interrupt status flag change interrupt enable interrupt occur interrupt disable ist0 change interrupt enable interrupt occur status 1 status 0 status 0 status 1 normal processing (status 0) single interrupt multiinterrupt
235 chapter 6 interrupt function 6.6 vector ad dress sharing interrupt servicing as intbt and int4 interrupt sources share the same vector table, the interrupt source is selected as shown below. (1) when using the interrupts only on one side between the two interrupt source types that share the vector table, set (1) the interrupt enable flag of the interrupt source needed and clear (0) the other interrupt enable flag. in this case, the interrupt request is generated by the interrupt source of the enabled (iexxx = 1) side, and once received, its interrupt request flag is reset. (2) when using the interrupts of both sides set (1) both of the interrupt enable flags that correspond to the two interrupt source types. in this case, the logical sum of the interrupt request flags of the two interrupt source types becomes the interrupt request. in this case, even if the interrupt request has been received by setting the interrupt request flag of one side or both sides, the request flag of either side is not reset. therefore, in this case, it is necessary to determine, by using the service routine, which interrupt source the interrupt is from. it is performed by executing the di instruction at the beginning of the service routine and checking the interrupt request flag with the sktclr instruction. when this interrupt request flag has been tested and cleared, if the request flags of both sides are set, even if the flag of one side is cleared, the interrupt request remains. if ist0 is cleared, the remaining interrupt request starts the multiinterrupt servicing. remark when only the interrupts of one side are enabled, the source of the interrupt occurred being clear, the interrupt request flag is reset by the hardware when receiving the interrupt. on the other hand, when the interrupts of both sides are enabled, either of the interrupt sources that have occurred is unclear and therefore the interrupt request flag cannot be reset by the hardware. consequently, the interrupt request flag is checked by the software to determine the interrupt source. flag resetting is performed by the software. example when giving priority to int4 di sktclr irq4 ; irq4 = 1? br vsubbt eireti: ei int4 processing routine reti vsubbt: sktclr irqbt ; irqbt = 1? note br eireti ; irqbt v irq4 = 0 br eireti intbt processing routine . . . . . .
236 chapter 6 interrupt function . . . . . . note be sure to also test interrupts that do not take precedence. otherwise, interrupt servicing is not executed as expected. the reason for this is as follows: example (if only interrupt that takes precedence is tested) main routine vector routine vent1 mbe = 0, rbe = 0, vsub4 vsub4: sktclr1 irq4 br vsubbt int4 nop int4 processing routine clr1 irq4 reti vsubbt: clr1 irqbt irqbt processing routine reti if the edge of int4 is generated while the nop instruction in the above main routine is executed, the cpu starts interrupt servicing. because nop is a one-machine cycle instruction, however, the cpu first executes the clr1 irq4 instruction and then starts the interrupt vector routine (refer to 6.7 machine cycles until interrupt servicing ). the vector routine tests irq4 by executing the sktclr1 irq4 instruction. however, because irq4 = 0, execution jumps to vsubbt. as a result, the irqbt processing routine is executed. for this reason, be sure to also test interrupts that do not take precedence. . . . . . . . . . . . .
237 chapter 6 interrupt function 6.7 machine cycles until interrupt servicing on the m pd75308, the number of machine cycles executed from the time the interrupt request flag (irqn) is set until the interrupt routine program is executed is as follows. (1) when irqn is set during execution of an interrupt control instruction when the irqn flag is set during execution of an interrupt control instruction, the interrupt routine program is executed after 3 machine cycles of interrupt servicing have been performed following execution of the next instruction. a b c d interrupt control instruction a : irqn set b : execution of next instruction (between 1 and 3 machine cycles depending on the instruction) c : interrupt servicing (3 machine cycles) d : execution of interrupt routine remarks 1. an interrupt control instruction is an instruction which manipulates instruction related hardware (data memory fb x address). these comprise the di instruction and the ei instruction. 2. the 3 machine cycles of interrupt servicing represent the time for stack manipulation on acknowledgement of the interrupt, etc. cautions 1. in the case of consecutive interrupt control instructions, the interrupt routine program is executed after 3 machine cycles of interrupt servicing have been performed following execution of the next instruction after the last interrupt control instruction executed. 2. if the di instruction is executed when irqn is set (a in figure above) or subsequently, the set irqn interrupt request is held pending until the next ei instruction is executed.
238 chapter 6 interrupt function (2) when irqn is set during execution of an instruction other than those in (1). (a) when irqn is set in the last machine cycle of the instruction being executed in this case, the interrupt routine program is executed after 3 machine cycles of interrupt servicing have been performed following execution of the next instruction after the instruction being executed. a b c d instruction except for interrupt control a : irqn set b : execution of next instruction (between 1 and 3 machine cycles depending on the instruction) c : interrupt servicing (3 machine cycles) d : execution of interrupt routine caution when the next instruction is an interrupt control instruction, the interrupt routine program is executed after 3 machine cycles of interrupt servicing have been performed following execution of the next instruction after the last interrupt control instruction executed. when the interrupt control instruction executed after the instruction by which the irqn flag is set is a di instruction, the interrupt request by which irqn was set is held pending. (b) when irqn is set before the last machine cycle of the instruction being executed in this case, the interrupt routine program is executed after 3 machine cycles of interrupt servicing have been performed following the instruction being executed. c d a instruction except for interrupt control a : irqn set c : interrupt servicing (3 machine cycles) d : execution of interrupt routine
239 chapter 6 interrupt function 6.8 effective methods of using interrupts the interrupt function can be used effectively as follows: (1) in the interrupt servicing routine, make mbe = 0. the 00h to 7fh address is given priority for allocation of the data memory used in the interrupt servicing routine. thus, if mbe = 0 is specified in the interrupt vector table, it is possible to program without recognizing the memory bank. if the program is obliged to use the memory bank 1, the memory bank select register is saved by the push bs instruction and then memory bank 1 is selected. (2) use the software interrupt in debugging even if the interrupt request flag is set by the instruction, the system operates in the same manner as when the interrupt has occurred. irregular or simultaneous interrupts can be debugged effectively by using the instruction to set the interrupt request flag.
240 chapter 6 interrupt function 6.9 application of interrupts when using the interrupt function, first of all set the main program as follows. 1 set the interrupt enable flag to be used (ie iexxx instruction) 2 when using int0 and int1, select the active edge. (set im0 and im1.) 3 set (ei instruction) the interrupt master enable flag (ime). in the interrupt servicing program, mbe is set by the vector table. the reti instruction is used for restoration from the interrupt servicing program. (1) interrupt enable/disable reset . . . 1 ei ie0 ei iet0 2 ei . . . . . . 3 di ie0 . . . . . . 4 di . . . . . . . . . . . . . . . . 5 interrupt disable int0, intt0 enable intt0 enable interrupt disable
1 all the interrupts are disabled by the reset signal. 2 set the interrupt enable flag by the ei iexxx instruction. at this stage, all the interrupts are still disabled. 3 set the interrupt master enable flag by the ei instruction. at this stage, int0 and intt0 are enabled. 4 the interrupt enable flag is cleared and int0 is disabled by the di iexxx instruction. 5 all the interrupts are disabled by the di instruction.
241 chapter 6 interrupt function (2) example of using intbt, int0 (falling edge active) and intt0: no multiinterrupts reset int0 4 mov mov clr1 2 a, #1 im0, a irq0 ei ei ei ei . . . . . . . . . . . . . . . . . . . . . . . . . iebt ie0 iet0 3 status 0 status 0 status 1 reti 5 ; mbe = 0
1 1 all the interrupts are disabled and the status is made 0 by the reset signal. 2 set int0 to falling edge active. 3 interrupt enable by ei and ei iexxx instructions. 4 start the int0 interrupt servicing program by int0 falling. the status is changed to 1 and all the interrupts are disabled. 5 restored from the interrupt by the reti instruction. the status is returned to 0 and the interrupt is enabled.
242 chapter 6 interrupt function (3) execution of hold interrupt Cinterrupt input during interrupt disablingC reset ei ie0 . . . . . . . . . . . . ei . . . . . . . . . . . . . . . . . . . . ei iecsi . . . . . . . . . . . . . . . . . . . . 2 1 int0 4 3 intcsi reti reti
1 even if int0 is set during disabling, the request flag is held. 2 int0 processing program starts at the moment of interrupt enabling by the ei instruction. 3 same as 1 . 4 intcsi processing program starts at the moment intcsi in hold is enabled.
243 chapter 6 interrupt function (4) execution of interrupts in hold reset ei iet0 ei ie0 ei . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . int0 intt0 1 2 reti reti
1 when int0 and intt0 occur simultaneously (during execution of the same instruction). int0 earlier in the interrupt order is executed earlier (intt0 is held). 2 using the reti instruction, start the intt0 processing program in hold if the int0 processing program is ended.
244 chapter 6 interrupt function (5) enable two multiinterrupts C intt0 and int0 enable multiinterrupts. intcs1 and int4 enable single interruptC reset intcsi 1 ei ei ei ei ei iet0 ie0 iecsi ie4 status 0 status 0 status 0 status 1 intt0 3 reti 4 status 1 status 0 ei ei reti 5 iecsi ie4 di clr1 di di ei 2 ist0 iecsi ie4
1 start the intcsi processing program by the occurrence of the interrupt intcsi which does not enable multiinterrupts. the status is 1. 2 by clearing ist0, the status is made 0. disable intcsi and int4 which do not enable multiinterrupts. 3 with the occurrence of intt0 which enables multiinterrupts, the multiinterrupt is executed, the status is made 1 and all the interrupts are disabled. 4 the status is returned to 0 by ending the intt0 processing. 5 enable and restore intcsi and int4 that have been disabled.
245 chapter 7 standby function chapter 7 standby function the m pd75308 has a standby function which allows the system power consumption to be reduced. the standby function comprises two modes: ? stop mode ? halt mode the function of these modes is described below. (1) stop mode this mode stops the main system clock oscillation circuit and halts the entire system. the power consumption of the cpu is thus considerably reduced. since low-voltage (v dd = up to 2 v) data memory retention is also possible, this mode is useful for retaining data memory contents at an ultra-low consumption current. as the m pd75308 stop mode can be released by an interrupt request, intermittent operation is also possible. however, since a wait period is required to secure the oscillation stabilization time when the stop mode is released, the halt mode should be selected when it is necessary for servicing to start immediately in response to an interrupt request. (2) halt mode in the halt mode the cpu operation clock is stopped, but the system clock oscillation circuit continues to operate. although this mode cannot reduce the consumption current as much as the stop mode, it is effective when wanting to start servicing immediately in response to an interrupt request, or when wanting to perform intermittent operation such as clock operation. in both modes, all register, flag and data memory contents immediately prior to setting the standby mode are retained. as the input/output port output latch and output buffer status are also retained, the input/output port status is processed beforehand to minimize the consumption current of the entire system. precautions concerning the use of these modes are given as follows.
246 chapter 7 standby function precautions: 1. the stop mode can be used only when the main system clock operating (the subsystem clock oscillation cannot be stopped). the halt mode can be used in either the main system or subsystem clock operation status. 2. if the lcd controller/driver and watch timers operation clock are at main system clock f x and if it is set to the stop mode, its operation is stopped. therefore, when continuing the operation, it is necessary to switch the operation clock over to the subsystem clock f xt before setting the stop mode. 3. changeover of the standby mode, the cpu clock and the system clock can achieve effective low- consumption current and low-voltage operations. however, as shown in 5.2.3 system clock and cpu clock setting, it takes time in either case from the selection of a new clock by operating the control register until the start of the operation with the newly-replaced clock. therefore, when combining the clock changeover function and the standby mode, set to the standby mode after the time required for the changeover has elapsed. 4. when the standby mode is used, input/output ports should be handled so as to minimize the consumption current. in particular, input ports should not be left open; either a low level or high level should be input without fail.
247 chapter 7 standby function 7.1 standby mode setting and operation status table 7-1. each operation status in standby mode stop mode halt mode set instruction stop instruction halt instruction system clock when setting settable only in main system clock settable either in main system clock or in subsystem clock operation clock generation circuit stop only main system clock oscillation stop only cpu clock f (oscillation status continues) basic interval timer stop operation operable only with main system clock oscillation (irqbt is set at the standard time interval). serial interface operable only when selecting external operable with main system clock oscillation sck input for serial clock or when the external sck input is selected as the serial clock. timer/event counter operable only when ti0 pin input is operable with main system clock oscillation specified for count clock or when the ti0 pin input is specified for the count clock. watch timer operable when f xt is selected for the operable count clock lcd controller operable only when f xt is selected for operable lcdcl external interrupt int1, 2 and 4 are operable. only int0 is inoperable. cpu stop operation cancellation signal interrupt request signal or reset input interrupt request signal or reset input from the operable hardware which is from the operable hardware which is enabled by the interrupt enable flag enabled by the interrupt enable flag use the stop instruction to set the stop mode, and the halt instruction to set the halt mode. (the stop instruction and the halt instruction respectively set pccs bit 3 and bit 2.) make sure to write the nop instruction after the stop and halt instructions. when changing cpus operation clock by pccs low-order 2 bits, there is sometimes a time lapse from pcc rewriting to cpu clock change. therefore, when changing the operation clock before the standby mode and the cpu clock after standby mode cancellation, set the standby mode after the machine cycles necessary for cpu clock change have elapsed since pcc rewriting. in the standby mode, data is maintained in all the registers and the data memory, such as general registers, flags, mode registers, output latches which stop operations during standby mode. cautions 1. when set to the stop mode, the x1 input is internally short circuited to v ss (gnd potential) to restrict the leakage of the crystal oscillation circuit unit. consequently, please do not use the stop mode in the system which uses an external clock for the main system clock. 2. before setting the standby mode, the interrupt request flag should be reset beforehand. when there is an interrupt source where both the interrupt request flag and interrupt enable flag are set, the standby mode is released as soon as it is entered (refer to figure 6-1. interrupt control circuit block diagram). however, if the stop mode is set, the halt mode is entered immediately after stop instruction execution and the operating mode is restored after waiting for the btm register set time.
248 chapter 7 standby function 7.2 cancellation of standby mode both the stop mode and the halt mode are canceled by the occurrence of the interrupt request signal note enabled by the interrupt enable flag and the reset input. the cancellation operation of each mode is shown in figure 7-1. note int0 is not included. figure 7-1. standby mode cancellation operation (1/2) (a) stop mode cancellation by reset input rest signal clock halt instruction operating mode halt mode wait (31.3 ms: in 4.19 mhz operation) operating mode oscillation (b) stop mode cancellation by occurrence of interrupt remark the dotted line indicates the case in which the interrupt request which canceled the standby was received (ime = 1). (c) halt mode cancellation by reset input clock stop instruction operating mode stop mode oscillation oscillation stop halt mode oscillation wait (about 31.3 ms: in 4.19 mhz operation) operating mode rest signal standby release signal clock stop instruction operating mode stop mode oscillation oscillation stop halt mode oscillation wait (time set by btm) operating mode
249 chapter 7 standby function figure 7-1. standby mode cancellation operation (2/2) (d) halt mode cancellation by occurrence of interrupt remark the dotted line indicates the case in which the interrupt request which canceled the standby was received (ime = 1). when the stop mode has been canceled by the occurrence of the interrupt, the wait time is determined by setting the btm (refer to table 7-2 ). the time for settlement of the oscillation varies depending on the vibrator type used and the power voltage at the time of stop mode cancellation. therefore, select the wait time according to the use situation, and set the btm before setting the stop mode. table 7-2. w ait time selection by btm btm3 btm2 btm1 btm0 w ait time note ( ) is when f x = 4.19 mhz C000 about 2 20 /f x (about 250 ms) C011 about 2 17 /f x (about 31.3 ms) C101 about 2 15 /f x (about 7.82 ms) C111 about 2 13 /f x (about 1.95 ms) other than above setting prohibited note this time does not include the time from stop mode cancellation to oscillation start. caution the wait time in stop mode cancellation does not include the time (a in the diagram below) from stop mode cancellation to clock oscillation start whether by reset input or by occurrence of interrupt. v ss stop mode cancellation x1 pin's voltage waveform a standby release signal clock halt instruction operating mode halt mode operating mode oscillation
250 chapter 7 standby function 7.3 operation after standby mode cancellation (1) execute the normal reset operation if the standby mode was canceled by reset input. (2) when canceled by occurrence of the interrupt request, whether to perform the vectored interrupted or not when the cpu has restarted the instruction execution is determined by the contents of the interrupt enable flag (ime). (a) when ime = 0 after standby mode cancellation, restart the execution from the instruction (nop instruction) following the setting of the standby mode. the interrupt request flag is maintained. (b) when ime = 1 after standby mode cancellation, the vectored interrupt is executed after executing two instructions following the standby mode set instruction. however, if the standby mode was canceled by intw and int2 (testable input), operate the system in the same manner as in (a) because the vectored interrupt does not occur here. 7.4 standby mode application the standby mode is used according to the following procedures: 1 detect the standby mode set factor such as power disconnection with the interrupt input or the port input (int4 is effective in detecting power disconnection). 2 process the input/output port (so that the consumption current is minimized). in particular, input ports should not be left open; either a low level or high level should be input without fail. 3 specify the interrupt that cancels the standby mode. (int4 is effective for this. clear the interrupt enable flag not canceling the standby mode.) 4 specify the operation after cancellation. (operate the ime depending on whether to perform interrupt servicing or not.) 5 specify the cpu clock after cancellation. (when changing the clock, let the machine cycles required until standby mode setting claps.) 6 select the wait time in cancellation. 7 set the standby mode (stop, halt instructions) furthermore, the standby mode can realize low-consumption current and low-voltage operation by combining with the system clock changeover function.
251 chapter 7 standby function (1) example of stop mode application (f x = 4.19 mhz operation) ? set the stop mode by int4s falling edge input and cancel it by the rising edge input. (intbt is not used.) ? all the input/output ports shall be of high impedance (when pins are handled externally to reduce the consumption current in high impedance). ? interrupts used in the program shall be int0 and intt0, provided that these are not used in stop cancellation. ? enable the interrupt even after cancellation. ? after cancellation, the system shall be started by the cpu clock at the lowest speed, which will then be changed over to high speed after 31.3 ms. ? the wait time in cancellation shall be about 31.3 ms. ? after cancellation, wait another 31.3 ms for power safety. and check the p00/int4 pin twice and eliminate the chattering. 0 v v dd p00/int4 cpu operation stop instruction int4 int4 31.3 ms operating mode stop mode halt mode (wait) low-speed operation high-speed operation v dd pin voltage 31.3 ms
252 chapter 7 standby function (int4 processing program, mbe = 0) vsub4: skt port0.0 ; p00 = 1? br pdown ; power down set1 btm.3 ; power on wait: skt irqbt ; 31.3 ms wait br wait skt port0.0 ; chattering check br pdown mov a, #0011b mov pcc, a ; high-speed mode mov xa, #xxh ; port mode register set mov pmgm, xa ei ie0 ei iet0 reti pdown: mov a, #0 ; lowest speed mode mov pcc, a mov xa, #00h mov lcdm, xa ; lcd display off mov lcdc, a mov pmga, xa ; input/output port high impedance mov pmgb, xa di ie0 ; int0, intt0 disable di iet0 mov a, #1011b mov btm, a ; wait time = 31.3 ms nop stop ; stop mode set nop reti . .
253 chapter 7 standby function (2) halt mode application (f x = 4.19 mhz, f xt = 32.768 khz operation) ? changeover to the subsystem clock at int4s falling. ? stop main system clocks oscillation and set to the halt mode. ? operate intermittently at the interval of 0.5 sec during the standby mode. ? changeover again to the main system clock at int4s rising. ? intbt shall not be used. p00/int4 0 v v dd v dd pin voltage int4 int4 operating mode cpu operation intermittent operation (halt mode + iow-speed operation) operating mode (low-speed) 250 ms operating mode (high-speed) . . . . . . . . . . (initialization) mov a, #0011b mov pcc, a ; high-speed mode mov xa, #05h mov wm, xa ; main system clock ei ie4 ei iew ei ; interrupt enable (main routine) skt port0.0 ; power ok? halt ; power-down mode nop ; power ok? sktclr irqw ; is there 0.5 sec flag? br main ; no call watch ; watch subroutine main :
254 chapter 7 standby function (int4 processing routine) vint4: skt port0.0 ; power ok?, mbe = 0 br pdown clr1 scc.3 ; main system clock oscillation start mov a, #1000b mov btm, a wait1: skt irqbt ; 250 ms wait br wait1 skt port0.0 ; chattering check br pdown clr1 scc.0 ; changeover to main system clock reti pdown: mov xa, #00h mov lcdm, xa ; lcd display off mov lcdc, a set1 scc.0 ; changeover to subsystem clock mov a, #5 wait2: incs a ; 32 or more machine cycles wait note (35 machine cycles) br wait2 set1 scc.3 ; main system clock oscillation stop reti note refer to 5.2.3 system clock and cpu clock setting for system clock/cpu clock switchover. caution before changing the system clock from the main system clock to the subsystem clock, wait until the subsystem clocks oscillation settles.
255 chapter 8 reset function chapter 8 reset function the m pd75308 is reset by the reset input, and each hardware is initialized as shown in table 8-1. reset operation timing is shown in figure 8-1. figure 8-1. reset operation by reset input table 8-1. each hardware status after resetting (1/2) hardware reset input during reset input during standby mode operation program counter (pc) m pd75304, 75304b set the low-order 4 bits of the same as left 0000h address of the program memory to pc11 to pc8, and the contents of the 0001h address to pc7 to pc0. m pd75306, 75306b, 75308, set the low-order 5 bits of the same as left 75308b, 75p308 0000h address of the program memory to pc12 to pc8, and the contents of the 0001h address to pc7 to pc0. m pd75312, 75312b, 75316, set the low-order 6 bits of the same as left 75316b, 75p316, 75p316a, 0000h address of the program 75p316b memory to pc13 to pc8, and the contents of the 0001h address to pc7 to pc0. psw carrying flag (cy) retained undefined skip flag (sk0 to sk2) 0 0 interrupt status flag (ist0) 0 0 bank enable flag (mbe) set bit 7 of the 0000h address of same as left the program memory to the mbe. stack pointer (sp) undefined undefined data memory (ram) retained note undefined general register (x, a, h, l, d, e, b, c) retained undefined bank selection register (mbs) 0 0 note the data of the 0f8h to 0fdh address of the data memory is made indefinite by reset input. reset input halt mode operation mode or standby mode internal reset operation operating mode wait (31.3 ms: in 4.19 mhz operation)
256 chapter 8 reset function table 8-1. each hardware status after resetting (2/2) hardware reset input during reset input during stand-by mode operation basic interval counter (bt) undefined undefined timer mode register (btm) 0 0 timer/event counter (t0) 0 0 counter module register (tmod0) ffh ffh mode register (tm0) 0 0 toe0, t out f/f 0, 0 0, 0 watch timer mode register (wm) 0 0 serial shift register (sio) retained undefined interface operating mode register (csim) 0 0 sbi control register (sbic) 0 0 slave address register (sva) retained undefined clock generation processor clock control register (pcc) 0 0 circuit and clock system clock control register (scc) 0 0 output circuit clock output mode register (clom) 0 0 lcd controller display mode register (lcdm) 0 0 display control register (lcdc) 0 0 interrupt function interrupt request flag (irqxxx) reset (0) reset (0) interrupt enable flag (iexxx) 0 0 interrupt master enable flag (ime) 0 0 int0, 1 and 2 mode register (im0, 1, 2) 0, 0, 0 0, 0, 0 digital port output buffer off off output latch clear (0) clear (0) i/o mode register (pmga, b) 0 0 pull-up resistor specification register (poga) 00 bit sequential buffer (bsb0 to bsb3) retained undefined pin status p00 to p03, p10 to p13, p20 to p23, input same as left p30 to p33, p60 to p63, p70 to p73 p40 to p43, p50 to p53 ? in integrated pull-up same as left resistor: high level ? in open drain: high impedance s0 to s31, com0 to com3 note same as left bias ? in integrated split resistor: same as left low level ? when split resistor is not integrated: high impedance note each display output selects the following v lcx as the input source. s0 to s31 : v lc1 com0 to com2 : v lc2 com3 : v lc0 however, each display output level changes depending on each display output and v lcx s external circuit.
257 chapter 9 prom writing and verification chapter 9 prom writing and verification the program memory integrated in the m pd75p308 and 75p316a is one-time prom or eprom. the program memory integrated in the m pd75p316 and 75p316b is one-time prom. the memory capacity is as follows. ? m pd75p308 : 8064 words x 8 bits ? m pd75p316 : 16256 words x 8 bits ? m pd75p316a : 16256 words x 8 bits ? m pd75p316b : 16256 words x 8 bits for writing in and verifying this prom, pins as shown in table 9-1 are used. there is no address input. instead, the addresses are updated by inputting the clock from the x1 pin. table 9-1. pin functions pin name functions x1, x2 inputs the address updating clock when writing in and verifying the prom, and inputs in the x2 pin its reversed signal. md0 to md3 selects the operating mode when writing in and verifying prom. p40 to p43 (low-order 4 bits) inputs/outputs the 8-bit data when writing in and verifying prom. p50 to p53 (high-order 4 bits) v dd applies the power voltage. applies 5 v 5 % in normal operation. note applies +6 v when writing in and verifying prom. v pp applies the voltage when writing in and verifying prom (normally, v dd potential). note on the m pd75p316a only, 2.7 v to 6.0 v is applied in normal operation. cautions 1. in the m m m m m pd75p308k and 75p316ak equipped with the erase window, seal it up with a light blocking cover film except when erasing the prom contents. 2. the one-time ver sions m m m m m pd75p308gf, 75p316gf, 75p316agf, 75p316bgc and 75p316bgk are not equipped with the erase window, and so the prom contents cannot be erased by ultraviolet rays.
258 chapter 9 prom writing and verification 9.1 operating mode when writing in and verifying prom the m pd75p308, 75p316, 75p316a and 75p316b turn to the prom write/verify mode when +6 v is applied to the v dd pin and +12.5 v to the v pp pin. this mode is turned to the following operating modes by input signals to the md0 to md3 pins. table 9-2. operating mode operating mode specification operating mode v pp v dd md0 md1 md2 md3 +12.5 v +6 v h l h l program memory address 0 clear l h h h write mode l l h h verify mode h x h h program inhibit mode remark x: l or h
259 chapter 9 prom writing and verification 9.2 prom write procedure the prom write procedure is as follows. high speed writing is possible. (1) pull down the unused pin to v ss through the resistance. the x1 pin is at low level. (2) supply 5 v to pins v dd and v pp . (3) 10 m s wait (4) 0 clear mode of the program memory address (5) supply +6 v to v dd , and +12.5 v to v pp . (6) program inhibit mode (7) write data in the 1 ms write mode. (8) program inhibit mode (9) verify mode. if written, move to (10). if not written repeat (7) to (9). (10) additional writing of (write time in (7) to (9): x) x 1 ms (11) program inhibit mode (12) by inputting 4 pulses to the x1 pin, update the program memory address (+1). (13) repeat (7) to (12) to the last address. (14) 0 clear mode of the program memory address (15) change the voltage of pins v dd and v pp to 5 v. (16) power off procedures (2) to (12) are shown in the diagram below. v pp v dd v pp v dd + 1 v dd v dd x1 p40-p43 p50-p53 md0 (p30) md1 (p31) md2 (p32) md3 (p33) data input data output data input write verify additional write address increment repeat x times
260 chapter 9 prom writing and verification 9.3 prom read procedure the prom read procedure is as follows. reads are performed in the verify mode. (1) pull down the unused pin to v ss through the resistance. the x1 pin is at low level. (2) supply 5 v to pins v dd to v pp . (3) 10 m s wait (4) 0 clear mode of the program memory address (5) supply +6 v to v dd , and +12.5 v to v pp . (6) program inhibit mode (7) if the clock pulse is input to the verify mode x1 pin, the data of 1 address is output in sequence at the cycle of four pulses. (8) program inhibit mode (9) 0 clear mode of the program memory address (10) change the voltage of pins v dd and v pp to 5 v. (11) power off procedures (2) to (9) are shown in the diagram below. v pp v dd v pp v dd + 1 v dd v dd x1 p40-p43 p50-p53 md0 (p30) md1 (p31) md2 (p32) md3 (p33) data output data output "l"
261 chapter 9 prom writing and verification 9.4 erasure the data programmed into the m pd75p308k and 75p316ak can be erased by irradiation with ultraviolet rays through the window in the top. erasure is possible using ultraviolet rays with a wavelength of approximately 250 nm. the total amount of irradiation required for total erasure is 15 w?s/cm 2 (ultraviolet ray intensity x erasure time). when using a commercially available ultraviolet lamp (254 nm wavelength, 12 mw/cm 2 intensity), erasure can be performed in approximately 15 to 20 minutes. cautions 1. memory contents may also be erased by prolonged exposure to direct sunlight or light from a fluorescent lamp. to protect the memory contents, the window should be masked with a light-screening cover film. the light-screening cover film which nec provides with its uv eprom products should be used for this purpose. 2. during erasure, the distance between the ultraviolet lamp and the m m m m m pd75p308k/75p316ak should be no more than 2.5 cm. remark a longer exposure time may be necessary due to deterioration of the ultraviolet lamp or dirt etc. on the package window.
262 chapter 9 prom writing and verification [memo]
263 chapter 10 instruction set chapter 10 instruction set the m pd75308 instruction set is a version revised and improved from the instruction set of the m pd7500 series, which is a forerunner of the 75x series. the new rennovative instruction set, still maintaining the continuity of the m pd7500 series, has the following characteristics. (1) bit manipulation instruction applicable in various ways (2) effective 4-bit manipulation instruction (3) 8-bit data transfer instruction (4) geti instruction to shorten the program size (5) accumulation instruction and notation adjust instruction that improve program effects (6) table reference instruction suitable to continuous reference (7) 1-byte relative branch instruction (8) nec standard mnemonics arranged for easy understanding for addressing mode applicable in operating the data memory, refer to chapter 3 features of architecture and memory map . 10.1 characteristic instructions characteristic instructions in the m pd75308 instruction set will be overviewed below. 10.1.1 geti instruction the geti instruction converts into 1-byte instructions the following. (a) all-space subroutine call instruction (b) all-space branch instruction (c) arbitrary 2-byte, 2 machine cycle instruction (however, the brcb and callf instructions are excluded.) (d) combination of two 1-byte instructions in the geti instruction, refer to the table addressed by 0020h to 007fh in the program memory and execute the referred 2-byte data as the instruction for (a) to (d). therefore, as many as 48 instructions for (a) to (d) can be converted to 1-byte instructions. if the frequently used (a) to (d) instructions are converted to 1-byte by the geti instruction, the number of program bytes can be shortened substantially.
264 chapter 10 instruction set 10.1.2 bit manipulation instruction the m pd75308s bit manipulation can be performed by various instructions as shown below. (a) bit set : set1 mem. bit set1 mem. bit* (b) bit clear : clr1 mem. bit clr1 mem. bit* (c) bit test : skt mem. bit skt mem. bit* (d) bit test : skf mem. bit skf mem. bit* (e) bit test and clear : sktclr mem. bit* (f) boolean arithmetic operation : and1 cy, mem. bit* or1 cy, mem. bit* xor1 cy, mem. bit* remark mem. bit* is the bit address indicated by the bit manipulation addressing (fmem. bit, pmem. @l, @h + mem. bit). especially, all the bit manipulation instructions described above can be applied to the input/output port, thus making its operation extremely effective. 10.1.3 accumulation instruction the m pd75308 is prepared with the following two types of accumulation instructions. (a) mov a, #n4 or mov xa, #n8 (b) mov hl, #n8 accumulation indicates that each of these two instruction types is placed in a continuous address. example a0 : mov a, #0 a1 : mov a, #1 xa7 : mov xa, #07 as the example above shows, in a series of accumulation instructions, if the address to be initially executed is a0, the following two instructions are replaced by the nop instruction to be executed, and if the address to be initially executed is a1, the following one instruction is replaced by the same instruction. in other words, only the initially executed instruction is valid, and all the other instructions following this are processed as nop instructions. by using this accumulation instruction, constants can be effectively set to the accumulator (a register, register pair xa) and to the data pointer (register pair hl).
265 chapter 10 instruction set 10.1.4 notation adjust instruction in some applications, the results of 4-bit data additions or subtractions (performed in binary numerals) are converted to decimal numerals, or it is necessary to adjust them to hexa numerals as in time. therefore, the m pd75308 instruction set is prepared with the notation adjust instruction to arbitrarily adjust the 4-bit data addition or subtraction result to a notation. (a) notation adjust in addition assume that the notation value desired to be adjusted is m. based on the combinations of adds a, #16Cm addc a, @hl ; a, cy a + (hl) + cy adds a, #m the accumulator and the memory (hl) are added and the added result is adjusted in the m-notation. the overflow is left behind in the carry flag. if carry occurs as the result of executing the addc a, @hl instruction, skip the adds a, #n4 instruction that follows. if carry does not occur, the adds a, #n4 instruction is executed. at this time, this instructions skip function is disabled and so, even if carry occurs as the result of addition, the following instruction is not skipped. thus, the program can be written after the adds a, #n4 instruction. example the accumulator and the memory are added decimally. adds a, #6 addc a, @hl ; a, cy a + (hl) + cy adds a, #10 (b) notation adjust in subtraction assume that the notation value desired to be adjusted is m. the memory (hl) is subtracted from the accumulator, based on the combinations of subc a, @hl adds a, #m and the result is adjusted in the m-notation. the underflow is left behind in the carry flag. if borrow does not turn up as the result of executing the subc a, @hl instruction, skip the following adds a, #n4 instruction. if borrow turns up, the adds a, #n4 instruction is executed. at this time, this instructions skip function is disabled and so, even if carry turns up as the result of addition, the following instruction is not skipped. thus, the program can be written after the adds a, #n4 instruction. 10.1.5 skip instruction and the number of machine cycles required for skipping the m pd75308s instruction set is made to judge conditions and then organize programs by means of skip. skip is the function of executing the following instruction by skipping one instruction when the skip instruction (instruction with skip conditions) is executed and skip conditions are satisfied. when skip has occurred, the number of machine cycles required for skipping is as follows. (a) if the instruction (instruction to be skipped) following the skip instruction is a 3-byte instruction (two types: br !addr instruction and call !addr instruction): 2 machine cycles (b) if the instruction is other than (a): 1 machine cycle . . .
266 chapter 10 instruction set 10.2 instruction set and its operation (1) operand expression form and description method describe the operand in each instructions operand column according to the method of describing the instructions operand expression form. (refer to ra75x assembler package users manual-language (eeu-1364) for details.) if there are multiple description methods, select one of them. english letters in capital and codes +, C are the key words, and write them as they are. in the case of immediate data, describe the appropriate numeric value or label. the abbreviations of various types of registers and flags written in figure 3-5 can be described as labels on behalf of mem, fmem, pmem and bit, etc. (however, there are limits to the labels that fmem and pmem can describe. for details, refer to table 3-1. addressing modes applicable for peripheral hardware operations and figure 3-5. m m m m m pd75308 i/o map .) expression format description method reg x, a, b, c, d, e, h, l reg1 x, b, c, d, e, h, l rp xa, bc, de, hl rp1 bc, de, hl rp2 bc, de rpa hl, de, dl rpal de, dl n4 4-bit immediate data or label n8 8-bit immediate data or label mem note 1 8-bit immediate data or label bit 2-bit immediate data or label fmem fb0h to fbfh, ff0h to fffh immediate data or label pmem fc0h to fffh immediate data or label addr, m pd75304, 75304b 000h to fffh immediate data or label caddr m pd75306, 75306b 0000h to 177fh immediate data or label m pd75308, 75308b, 75p308 0000h to 1f7fh immediate data or label m pd75312, 75312b 0000h to 2f7fh immediate data or label m pd75316, 75316b, 75p316, 75p316a, 75p316b 0000h to 3f7fh immediate data or label faddr 11-bit immediate data or label taddr 20h to 7fh immediate data (provided that bit 0 = 0) or label portn port0 to port7 iexxx iebt, iecsi, iet0, ie0, ie1, ie2, ie4, iew mbn mb0, mb1, mb15 note 2 notes 1. only even-number addresses can be described in mem in 8-bit data processing. 2. on the m pd75312b, 75316b, 75p316a 75p316b only: mb0, mb1, mb2, mb3 and mb15.
267 chapter 10 instruction set (2) common examples in explaining operations a : a register; 4-bit accumulator b : b register; 4-bit accumulator c : c register; 4-bit accumulator d : d register; 4-bit accumulator e : e register; 4-bit accumulator h : h register; 4-bit accumulator l : l register; 4-bit accumulator x : x register; 4-bit accumulator xa : register pair (xa); 8-bit accumulator bc : register pair (bc) de : register pair (de) dl : register pair (dl) hl : register pair (hl) pc : program counter sp : stack pointer cy : carry flag; bit accumulator psw : program status word mbe : memory bank enable flag portn : port n (n = 0 to 7) ime : interrupt master enable flag iexxx : interrupt enable flag mbs : memory bank selection register pcc : processor clock control register ? : address bit delimit (xx) : contents addressed by xx xxh : hexadecimal data
268 chapter 10 instruction set (3) explanation of symbols in the addressing area column *1 mb = mbe?mbs (mbs = 0, 1, 15) note *2 mb = 0 *3 mbe = 0 : mb = 0 (00h-7fh) mb = 15 (80h-ffh) data memory mbe = 1 : mb = mbs (mbs = 0, 1, 15) note addressing *4 mb = 15, fmem = fb0h-fbfh, ff0h-fffh *5 mb = 15, pmem = fc0h-fffh *6 m pd75304, 75304b addr = 000h-fffh m pd75306, 75306b addr = 0000h-177fh m pd75308, 75308b, 75p308 addr = 0000h-1f7fh m pd75312, 75312b addr = 0000h-2f7fh m pd75316, 75316b, 75p316, addr = 0000h-3f7fh 75p316a, 75p316b *7 addr = (current pc) C 15 to (current pc) C 1, (current pc) + 2 to (current pc) + 16 *8 m pd75304, 75304b caddr = 000h-fffh m pd75306, 75306b caddr = 0000h-0fffh (pc 12 = 0) 1000h-177fh (pc 12 = 1) program memory m pd75308, 75308b, 75p308 caddr = 0000h-0fffh (pc 12 = 0) addressing 1000h-1f7fh (pc 12 = 1) m pd75312, 75312b caddr = 0000h-0fffh (pc 13 = 0, pc 12 = 0) 1000h-1fffh (pc 13 = 0, pc 12 = 1) 2000h-2f7fh (pc 13 = 1, pc 12 = 0) m pd75316, 75316b, 75p316, caddr = 0000h-0fffh (pc 13 = 0, pc 12 = 0) 75p316a, 75p316b 1000h-1fffh (pc 13 = 0, pc 12 = 1) 2000h-2fffh (pc 13 = 1, pc 12 = 0) 3000h-3f7fh (pc 13 = 1, pc 12 = 1) *9 faddr = 0000h-07ffh *10 faddr = 0020h-007fh note on the m pd75312b, 75316b, 75p316a and 75p316b only, mbs = 0, 1, 2, 3 or 15. remarks 1. mb indicates the accessible memory bank. 2. in *2, mb = 0 regardless of mbe and mbs. 3. in *4 and *5, mb = 15 regardless of mbe and mbs. 4. each of *6 to *10 indicates the addressable area.
269 chapter 10 instruction set (4) explanation of machine cycle columns s indicates the number of machine cycles required for the skip-attached instruction to do skipping. the value of the s varies as follows. ? when not skipping .............................................................................................................................. s = 0 ? if the instruction to be skipped is a 1- or 2-byte instruction ........................................................... s = 1 ? if the instruction to be skipped is a 3-byte instruction (br !addr, call !addr instruction) ......... s = 2 caution the geti instruction is skipped at 1 machine cycle. 1 machine cycle corresponds to cpu clock f s 1 cycle portion (= t cy ), and, by setting the pcc, three kinds of time be selected (refer to 5.2.2 (1) processor clock control register (pcc) ). (5) explanation of representative products in operation column the products shown in the operation column ( m pd75304, 75308, 75316) represent the following products. m pd75034 m pd75304, 75304b m pd75308 m pd75306, 75306b, 75308, 75308b, 75p308 m pd75316 m pd75312, 75312b, 75316, 75316b, 75p316, 75p316a, 75p316b
270 chapter 10 instruction set instruction mnemonic operand number machine operation addressing skip group of bytes cycle area condition transfer mov a, #n4 1 1 a n4 accumulation a instructions reg1, #n4 2 2 reg1 n4 xa, #n8 2 2 xa n8 accumulation a hl, #n8 2 2 hl n8 accumulation b rp2, #n8 2 2 rp2 n8 a, @hl 1 1 a (hl) *1 a, @rpa1 1 1 a (rpa1) *2 xa, @hl 2 2 xa (hl) *1 @hl, a 1 1 (hl) a*1 @hl, xa 2 2 (hl) xa *1 a, mem 2 2 a (mem) *3 xa, mem 2 2 xa (mem) *3 mem, a 2 2 (mem) a*3 mem, xa 2 2 (mem) xa *3 a, reg 2 2 a reg xa, rp 2 2 xa rp reg1, a 2 2 reg1 a rp1, xa 2 2 rp1 xa xch a, @hl 1 1 a (hl) *1 a, @rpa1 1 1 a (rpa1) *2 xa, @hl 2 2 xa (hl) *1 a, mem 2 2 a (mem) *3 xa, mem 2 2 xa (mem) *3 a, reg1 1 1 a reg1 xa, rp 2 2 xa rp table reference movt xa, @pcde 1 3 ? m m m m m pd75304 instructions xa (pc 11C8 + de) rom ? m m m m m pd75308 xa (pc 12C8 + de) rom ? m m m m m pd75316 xa (pc 13C8 + de) rom xa, @pcxa 1 3 ? m m m m m pd75304 xa (pc 11C8 + xa) rom ? m m m m m pd75308 xa (pc 12C8 + xa) rom ? m m m m m pd75316 xa (pc 13C8 + xa) rom arithmetic adds a, #n4 1 1+s a a + n4 carry operation a, @hl 1 1+s a a + (hl) *1 carry instructions addc a, @hl 1 1 a, cy a + (hl) + cy *1 subs a, @hl 1 1+s a a C (hl) *1 borrow subc a, @hl 1 1 a, cy a C (hl) C cy *1 and a, #n4 2 2 a a ^ n4 a, @hl 1 1 a a ^ (hl) *1
271 chapter 10 instruction set instruction mnemonic operand number machine operation addressing skip group of bytes cycle area condition arithmetic or a, #n4 2 2 a a v n4 operation a, @hl 1 1 a a v (hl) *1 instructions xor a, #n4 2 2 a a v n4 a, @hl 1 1 a a v (hl) *1 rorc a 1 1 cy a 0 , a 3 cy, a nC1 a n not a 2 2 a a increment/ incs reg 1 1+s reg reg + 1 reg = 0 decrement @hl 2 2+s (hl) (hl) + 1 *1 (hl) = 0 instruction mem 2 2+s (mem) (mem) + 1 *3 (mem) = 0 decs reg 1 1+s reg reg C 1 reg = fh comparison ske reg, #n4 2 2+s skip if reg = n4 reg = n4 instructions @hl, #n4 2 2+s skip if (hl) = n4 *1 (hl) = n4 a, @hl 1 1+s skip if a = (hl) *1 a = (hl) a, reg 2 2+s skip if a = reg a = reg carry flag set1 cy 1 1 cy 1 manipulation clr1 cy 1 1 cy 0 instructions skt cy 1 1+s skip if cy = 1 cy = 1 not1 cy 1 1 cy cy memory bit set1 mem.bit 2 2 (mem. bit) 1*3 manipulation fmem. bit 2 2 (fmem. bit) 1*4 instructions pmem. @l 2 2 (pmem 7C2 + l 3C2 . bit(l 1C0 )) 1*5 @h + mem. bit 2 2 (h + mem 3C0 .bit) 1*1 clr1 mem. bit 2 2 (mem. bit) 0*3 frmem. bit 2 2 (fmem. bit) 0*4 pmem. @l 2 2 (pmem 7C2 + l 3C2 .bit(l 1C0 )) 0*5 @h + mem. bit 2 2 (h + mem 3C0 . bit) 0*1 skt mem. bit 2 2+s skip if (mem. bit) = 1 *3 (mem. bit) = 1 fmem. bit 2 2+s skip if (fmem. bit) = 1 *4 (fmem. bit) = 1 pmem. @l 2 2+s skip if (pmem 7C2 + l 3C2 . bit(l 1C0 )) = 1 *5 (pmem. @l) = 1 @h + mem. bit 2 2+s skip if (h + mem 3C0 .bit) = 1 *1 (pmem. @l) = 1 skf mem. bit 2 2+s skip if (mem. bit) = 0 *3 (mem. bit) = 0 fmem. bit 2 2+s skip if (fmem. bit) = 0 *4 (fmem. bit) = 0 pmem. @l 2 2+s skip if (pmem 7C2 + l 3C2 .bit(l 1C0 )) = 0 *5 (pmem. @l) = 0 @h + mem. bit 2 2+s skip if (h + mem 3C0 .bit) = 0 *1 (@h + mem. bit) = 0 sktclr fmem. bit 2 2+s skip if (fmem. bit) = 1 and clear *4 (fmem. bit) = 1 pmem. @l 2 2+s skip if (pmem 7C2 C l 3C2 .bit(l 1C0 )) = 1 *5 (pmem. @l) = 1 and clear @h + mem. bit 2 2+s skip if (h + mem 3C0 .bit) = 1 and clear * 1 (@h + mem. bit) = 1 and1 cy, fmem. bit 2 2 cy cy ^ (fmem. bit) * 4 cy, pmem. @l 2 2 cy cy ^ (pmem 7C2 + l 3C2 .bit(l 1C0 )) * 5 cy, @h + mem. bit 2 2 cy cy ^ (h + mem 3C0 .bit) * 1 or1 cy, fmem. bit 2 2 cy cy v (fmem. bit) * 4 cy, pmem. @l 2 2 cy cy v (pmem 7C2 + l 3C2 .bit(l 1C0 )) * 5 cy, @h + mem. bit 2 2 cy cy v (h + mem 3C0 . bit) * 1 accumulator manipulation instructions
272 chapter 10 instruction set instruction mnemonic operand number machine operation addressing skip group of bytes cycle area condition memory bit xor1 cy, fmem. bit 2 2 cy cy v (fmem. bit) *4 manipulation cy, pmem. @l 2 2 cy cy v (pmem 7C2 + l 3C2 . bit(l 1C0 )) *5 instructions cy, @h + mem. bit 2 2 cy cy v (h + mem 3C0 . bit) *1 branch br addr C C ? m m m m m pd75304 *6 instructions pc 110 addr (using the assembler, select a more adequate instruction from between brcb !caddr and br $addr.) ? m m m m m pd75308 pc 120 addr (using the assembler, select the most adequate instruction from among br !addr, brcb !caddr and br $addr.) ? m m m m m pd75316 pc 130 addr (using the assembler, select the most adequate instruction from among br !addr, brcb !caddr and br $addr.) !addr 3 3 ? m m m m m pd75308 *6 pc 12C0 addr ? m m m m m pd75316 pc 13C0 addr $addr 1 2 ? m m m m m pd75304 *7 pc 11C0 addr ? m m m m m pd75308 pc 12C0 addr ? m m m m m pd75316 pc 13C0 addr brcb !caddr 2 2 ? m m m m m pd75304 *8 pc 11C0 caddr 11C0 ? m m m m m pd75308 pc 12C0 pc 12 + caddr 11C0 ? m m m m m pd75316 pc 13C0 pc 13 , pc 12 + caddr 11C0 subroutine call !addr 3 3 ? m m m m m pd75304 *6 stack control (spC4) (spC1) (spC2) pc 11C0 instructions (spC3) mbe, 0, 0, 0 pc 11C0 addr, sp spC4 ? m m m m m pd75308 (spC4) (spC1) (spC2) pc 11C0 (spC3) mbe, 0, 0, pc 12 pc 12C0 addr, sp spC4 ? m m m m m pd75316 (spC4) (spC1) (spC2) pc 11C0 (spC3) mbe, 0, pc 13 , pc 12 pc 13C0 addr, sp spC4
273 chapter 10 instruction set instruction mnemonic operand number machine operation addressing skip group of bytes cycle area condition subroutine callf !faddr 2 2 ? m m m m m pd75304 *9 stack control (spC4) (spC1) (spC2) pc 11C0 instructions (spC3) mbe, 0, 0, 0 sp spC4 ? m m m m m pd75308 (spC4) (spC1) (spC2) pc 11C0 (spC3) mbe, 0, 0, pc 12 pc 12C0 00, faddr sp spC4 ? m m m m m pd75316 (spC4) (spC1) (spC2) pc 11C0 (spC3) mbe, 0, pc 13 , pc 12 pc 13C0 000, faddr sp spC4 ret 1 3 ? m m m m m pd75304 mbe, x, x, x (sp+1) pc 11C0 (sp) (sp+3) (sp+2) pc 11C0 0, faddr sp sp+4 ? m m m m m pd75308 mbe, x, x, pc 12 (sp+1) pc 11C0 (sp) (sp+3) (sp+2) sp sp+4 ? m m m m m pd75316 mbe, x, pc 13 , pc 12 (sp+1) pc 11C0 (sp) (sp+3) (sp+2) sp sp+4 rets 1 3+s ? m m m m m pd75304 unconditional mbe, x, x, x (sp+1) pc 11C0 (sp) (sp+3) (sp+2) sp sp+4 then skip unconditionally ? m m m m m pd75308 mbe, x, x, pc 12 (sp+1) pc 11C0 (sp) (sp+3) (sp+2) sp sp+4 then skip unconditionally ? m m m m m pd75316 mbe, x, pc 13 , pc 12 (sp+1) pc 11C0 (sp) (sp+3) (sp+2) sp sp+4 then skip unconditionally reti 1 3 ? m m m m m pd75304 mbe, x, x, x (sp+1) pc 11C0 (sp) (sp+3) (sp+2) psw (sp+4) (sp+5), sp sp + 6 ? m m m m m pd75308 mbe, x, x, pc 12 (sp+1) pc 11C0 (sp) (sp+3) (sp+2) psw (sp+4) (sp+5), sp sp + 6 ? m m m m m pd75316 mbe, x, pc 13 , pc 12 (sp+1) pc 11C0 (sp) (sp+3) (sp+2) psw (sp+4) (sp+5), sp sp + 6
274 chapter 10 instruction set instruction mnemonic operand number machine operation addressing skip group of bytes cycle area condition subroutine push rp 1 1 (spC1) (spC2) rp, sp spC2 stack control bs 2 2 (spC1) mbs,(spC2) 0,sp spC2 instructions pop rp 1 1 rp (sp+1) (sp), sp sp+2 bs 2 2 mbs (sp+1), sp sp+2 interrupt ei 2 2 ime 1 control iexxx 2 2 iexxx 1 instructions di 2 2 ime 0 iexxx 2 2 iexxx 0 input/output in note 1 a, portn 2 2 a portn (n = 0C7 ) instructions xa, portn 2 2 xa portn+1, portn (n = 4, 6 ) out note 1 portn, a 2 2 portn a (n = 2C7 ) portn, xa 2 2 portn+1, portn xa (n = 4, 6 ) cpu control halt 2 2 set halt mode (pcc. 2 1) instructions stop 2 2 set stop mode (pcc. 3 1) nop 1 1 no operation special sel mbn 2 2 mbs n (n = 0, 1, 15) note 2 instructions geti taddr 1 3 ? m m m m m pd75304 *10 ? for table defined by tbr instruction pc 11C0 (taddr) 3C0 + (taddr+1) ? for table defined by tcall instruction (spC4) (spC1) (spC2) pc 11C0 (spC3) mbe, 0, 0, 0 pc 11C0 (taddr) 3C0 + (taddr+1) sp spC4 ? for table other than the above depends on the (taddr) (taddr+1) instruction instruction execution referenced ? m m m m m pd75308 ? for table defined by tbr instruction pc 12C0 (taddr) 4C0 + (taddr+1) ? for table defined by tcall instruction (spC4) (spC1) (spC2) pc 11C0 (spC3) mbe, 0, 0, pc 12 pc 12C0 (taddr) 4C0 + (taddr+1) sp spC4 ? for table other than the above depends on the (taddr) (taddr+1) instruction instruction execution referenced notes 1. when an in/out instruction is executed, it is necessary to set mbe = 0, or mbe = 1 and mbs = 15. 2. for the m pd75312b, 75316b, 75p316a and 75p316b only, n = 0, 1, 2, 3 or 15. remark the tbr and tcall instructions are assembler directives for geti instruction table definition. C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C
275 chapter 10 instruction set instruction mnemonic operand number machine operation addressing skip group of bytes cycle area condition special geti taddr 1 3 ? m m m m m pd75316 instructions ? for table defined by tbr instruction pc 13C0 (taddr) 5C0 + (taddr+1) ? for table defined by tcall instruction (spC4) (spC1) (spC2) pc 11C0 (spC3) mbe, 0, pc 13 , pc 12 pc 13C0 (taddr) 5C0 + (taddr+1) sp spC4 ? for table other than the above depends on the (taddr) (taddr+1) instruction instruction execution referenced note for the m pd75312b, 75316b, 75p316a and 75p316b only, n = 0, 1, 2, 3 or 15. remark the tbr and tcall instructions are assembler directives for geti instruction table definition. C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C
276 chapter 10 instruction set 10.3 instruction code of each instruction (1) explanation of instruction code symbol r 2 r 1 r 0 reg 000a 001x 010l 011h reg 1 0 0 e reg1 101d 110c 111b q 2 q 1 q 0 addressing p 2 p 1 reg-pair 001 @hl 00 xa 100 @de @rpa1 @rpa 0 1 hl rp 101 @dl 10 de rp2 rp1 11 bc n 3 n 2 n 1 n 0 iexxx 0000 iebt 0010 iew 0100 iet0 0101 iecsi 0110 ie0 0111 ie2 1000 ie4 1110 ie1 in : immediate data to n4 and n8 dn : immediate data to mem bn : immediate data to bit nn : immediate data to n and iexxx tn : immediate data to taddr x 1/2 an : immediate data to [relative address distance (2 to 16) to branch destination address] C 1 sn : immediate data to the complement 1 of [relative address distance (15 to 1) to branch destination address]
277 chapter 10 instruction set (2) instruction code of bit manipulation addressing the in the operand column indicates that there are the following three addressing types for this purpose: ? fmem. bit ? pmem. @l ? @h + mem. bit the instruction codes second b yte corresponding to the addressing above is as follows: *1 instruction code second byte accessible bit fmem. bit 1 0 b 1 b 0 f 3 f 2 f 1 f 0 bit that can operate fb0h to fbfh 11b 1 b 0 f 3 f 2 f 1 f 0 bit that can operate ff0h to fffh pmem. @l 0100g 3 g 2 g 1 g 0 bit that can operate fc0h to fffh @h + mem. bit 0 0 b 1 b 0 d 3 d 2 d 1 d 0 bit that can operate the accessible memory bank bn : immediate data to bit fn : immediate data to fmem (indicates low-order 4 bits of the address) gn : immediate data to pmem (indicates bit 5 to 2 of the address) dn : immediate data to mem (indicates low-order 4 bits of the address) *1 *2
278 chapter 10 instruction set istruction group mnemonic operand instruction code b 1 b 2 b 3 transfer mov a, #n4 0111i 3 i 2 i 1 i 0 instruction reg1, #n4 10011010i 3 i 2 i 1 i 0 1r 2 r 1 r 0 rp, #n8 10001p 2 p 1 1i 7 i 6 i 5 i 4 i 3 i 2 i 1 i 0 a, @rpa 11100q 2 q 1 q 0 xa, @hl 1010101000011000 @hl, a 11101000 @hl, xa 1010101000010000 a, mem 10100011d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 xa, mem 10100010d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 mem, a 10010011d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 mem, xa 10010010d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a, reg 1001100101111r 2 r 1 r 0 xa, rp 1010101001011p 2 p 1 0 reg1, a 1001100101110r 2 r 1 r 0 rp1, xa 1010101001010p 2 p 1 0 xch a, @rpa 11101q 2 q 1 q 0 xa, @hl 1010101000010001 a, mem 10110011d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 xa, mem 10110010d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a, reg1 11011r 2 r 1 r 0 xa, rp 1010101001000p 2 p 1 0 table reference movt xa, @pcde 11010100 instruction xa, @pcxa 11010000 arithmetic adds a, #n4 0110i 3 i 2 i 1 i 0 operation a, @hl 11010010 instructions addc a, @hl 10101001 subs a, @hl 10101000 subc a, @hl 10111000 and a, #n4 100110010011i 3 i 2 i 1 i 0 a, @hl 10010000 or a, #n4 100110010100i 3 i 2 i 1 i 0 a, @hl 10100000 xor a, #n4 100110010101i 3 i 2 i 1 i 0 a, @hl 10110000 rorc a 10011000 not a 1001100101011111 increment/ incs reg 11000r 2 r 1 r 0 decrement @hl 1001100100000010 instruction mem 10000010d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 decs reg 11001r 2 r 1 r 0 accumulator manipulation instructions
279 chapter 10 instruction set istruction group mnemonic operand instruction code b 1 b 2 b 3 comparison ske reg, #n4 10011010i 3 i 2 i 1 i 0 0r 2 r 1 r 0 instructions @hl, #n4 100110010110i 3 i 2 i 1 i 0 a, @hl 10000000 a, reg 1001100100001r 2 r 1 r 0 carry flag set1 cy 11100111 manipulation clr1 cy 11100110 instruction skt cy 11010111 not1 cy 11010110 memory bit set1 mem. bit 1 0 b 1 b 0 0101d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 manipulation 10011101 instructions clr1 mem. bit 1 0 b 1 b 0 0100d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 10011100 skt mem. bit 1 0 b 1 b 0 0111d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 10111111 skf mem. bit 1 0 b 1 b 0 0110d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 10111110 sktclr 10011111 and1 cy, 10101100 or1 cy, 10101110 xor1 cy, 10111100 branch br !addr ? m m m m m pd75308 instructions 10101011000 addr ? m m m m m pd75316 1010101100 addr $addr 0000a 3 a 2 a 1 a 0 1111s 3 s 2 s 1 s 0 brcb !caddr 0101 caddr subroutine stack call !addr ? m m m m m pd75304 control 101010110100 addr instructions ? m m m m m pd75308 10101011010 addr ? m m m m m pd75316 1010101101 addr callf !faddr 01000 faddr ret 11101110 rets 11100000 reti 11101111 push rp 01001p 2 p 1 1 bs 1001100100000111 pop rp 01001p 2 p 1 0 bs 1001100100000110 *1 *1 *1 *1 *1 *1 *1 *1 *2 *2 *2 *2 *2 *2 *2 *2
280 chapter 10 instruction set istruction group mnemonic operand instruction code b 1 b 2 b 3 input/output in a, portn 101000111111n 3 n 2 n 1 n 0 instructions xa, portn 101000101111n 3 n 2 n 1 n 0 out portn, a 100100111111n 3 n 2 n 1 n 0 portn, xa 100100101111n 3 n 2 n 1 n 0 interrupt control ei 1001110110110010 instructions iexxx 1001110110n 5 11n 2 n 1 n 0 di 1001110010110010 iexxx 1001110010n 5 11n 2 n 1 n 0 cpu control halt 1001110110100011 instructions stop 1001110110110011 nop 01100000 special sel mbn 100110010001n 3 n 2 n 1 n 0 instructions geti taddr 0 0 t 5 t 4 t 3 t 2 t 1 t 0
281 chapter 10 instruction set 10.4 instruction function and application 10.4.1 t ransfer instruction mov a, #n4 function: a n4, n4 = i 3-0 : 0h to fh transfers the 4-bit immediate data n4 to register a (4-bit accumulator). this has the accumulation effect (group a). if the mov a, #n4 or mov xa, #n8 instruction is entered after this, the accumulation instructions following the executed instruction are processed as nop. application example: 1 set 0bh to the accumulator mov a, #0bh 2 select the data to be output to port 3 from among 0 to 2. a0 : mov a, #0 a1 : mov a, #1 a2 : mov a, #2 out port3, a mov reg1, #n4 function: reg1 n4, n4 = i 3C0 : 0h to fh transfers the 4-bit immediate data n4 to register reg1 (x, h, l, d, e, b, c). mov rp, #n8 function: rp n8, n8 = i 7C0 : 00h to ffh transfers the 8-bit immediate data n8 to register pair rp (xa, hl, de, bc). when xa or hl is specified as rp, the accumulation effect is generated. the accumulation effect includes group a (mov a, #n4 instruction and mov xa, #n8 instruction) and group b (mov hl, #n8 instruction). if instructions of the same group are entered in a row, accumulation instructions following the executed instruction are processed as nop. application example: set 5fh to register pair de. mov de, #5fh
282 chapter 10 instruction set mov a, @rpa function: a (rpa) transfers the contents of the data memory addressed by register pair rpa (hl, de, dl) to register a. mov xa, @hl function: a (hl), x (hl + 1) transfers the contents of the data memory addressed by register pair hl to register a, and transfers the contents of the next address of the memory to register x. however, if the contents of register l are in an odd number, the address whose lowest bit is ignored is specified. application example: transfer the data of addresses 3eh and 3fh to register pair xa mov hl, #3eh mov xa, @hl mov @hl, a function: (hl) a transfers the contents of register a to the data memory addressed by register pair hl. mov @hl, xa function: (hl) a, (hl + 1) x transfers the contents of register a to the data memory addressed by register pair hl, and transfers the contents of register x to the next address of the memory. however, if the contents of register l is in an odd number, the address whose lowest bit is ignored is specified. mov a, mem function: a (mem), mem = d 7C0 : 00h to ffh transfers the contents of the data memory addressed by 8-bit immediate data mem to register a.
283 chapter 10 instruction set mov xa, mem function: a (mem), x (mem + 1) mem = d 7C0 : 00h to ffh transfers the contents of the data memory addressed by 8-bit immediate data mem to register a, and transfers the contents of the next address to register x. addresses in an even number can be specified by mem. application example: transfer the data of addresses 40h and 41h to register pair xa. mov xa, 40h mov mem, a function: (mem) a, mem = d 7C0 : 00h to ffh transfers the contents of register a to the data memory addressed by 8-bit immediate data mem. mov mem, xa function: (mem) a, (mem + 1) x mem = d 7C0 : 00h to ffh transfers the contents of register a to the data memory addressed by 8-bit immediate data mem, and transfers the contents of register x to the next address of the memory. addresses in an even number can be specified by mem. mov a, reg function: a reg transfers the contents of register reg (x, a, h, l, d, e, b, c) to register a. mov xa, rp function: xa rp transfers the contents of register pair rp (xa, hl, de, bc) to register pair xa. mov reg1, a function: reg1 a transfers the contents of register reg1 (x, h, l, d, e, b, c) to register a.
284 chapter 10 instruction set mov rp1, xa function: rp1 xa transfers the contents of register pair xa to register pair rp1 (hl, de, bc). xch xa, mem function: a (mem), x (mem + 1) mem = d 7C0 : 00h to ffh exchanges the contents of register a with those of the data memory addressed by 8-bit immediate data mem, and exchanges the contents of register x with those of the next address of the memory. addresses in an even number can be specified by mem. xch a, reg1 function: a reg1 exchanges the contents of register a with those of register reg1 (x, h, l, d, e, b, c). xch xa, rp fucntion: xa rp exchanges the contents of register pair xa with those of register pair rp (xa, hl, de, bc). xch a, @rpa function: a (rpa) exchanges the contents of register a with those of the data memory addressed by register pair rpa (hl, de, dl). application example: exchanges the data of addresses 20h to 2fh of the data memory with those of addresses 30h to 3fh. sel mb0 mov d, #2 mov hl, #30h loop: xch a, @hl ; a (3x) xch a, @dl ; a (2x) xch a, @hl ; a (3x) incs l ; l l + 1 br loop
285 chapter 10 instruction set xch xa, @hl function: a (hl), x (hl + 1) exchanges the contents of register a with those of the data memory addressed by register pair hl, and exchanges the contents of register x with those of the next address of the memory. however, if the contents of register l are in an odd number, the address whose lowest bit is ignored is specified. xch a, mem function: a (mem), mem = d 7C0 : 00h to ffh exchanges the contents of register a with those of the data memory addressed by 8-bit immediate data mem.
286 chapter 10 instruction set 10.4.2 table ref erence instruction movt xa, @pcde function: ? if m pd75304, 75304b xa rom (pc 11C8 + de) ? if m pd75306, 75306b, 75308, 75308b, 75p308 xa rom (pc 12C8 + de) ? if m pd75312, 75312b, 75316, 75316b, 75p316, 75p316a, 75p316b xa rom (pc 13C8 + de) transfers the high-order bit of the program counter (pc) and the low-order 4 bits of the table data (rom) in the program memory addressed by the contents of register pair de to register a, and the high-order 4 bits to register x. the high-order bit of the table address is determined by the contents of the program counter (pc) when executing this instruction. in the table area, it is necessary to program necessary data beforehand with the assembler directive (db instruction). the program counter is not affected by the execution of this instruction. this instruction is valid when referring to the table data more than once in a row. figure 10-1. data flow by instruction execution (1/2) (a) if m m m m m pd75304, 75304b pc 12 ? 12 8 d 3? 7 4 e 3? 3 0 x 3 0 a 3 0 table data h 7 4 table data l 3 0 table address program memory (b) if m m m m m pd75306, 75306b, 75308, 75308b, 75p308 pc 11 ? 11 8 d 3? 7 4 e 3? 3 0 x 3 0 a 3 0 table data h 7 4 table data l 3 0 table address program memory
287 chapter 10 instruction set figure 10-1. data flow by instruction execution (2/2) (c) if m m m m m pd75312, 75312b, 75316, 75316b, 75p316, 75p316a, 75p316b pc 13 ? 13 8 d 3? 7 4 e 3? 3 0 x 3 0 a 3 0 table data h 7 4 table data l 3 0 table address program memory precaution: normally, the movt xa, @pcde instruction reference the table data of the page from which the instruction is located. however, if the instruction is located in address xxffh, it does not reference the table data of this page but that of the next page. 7 0 02ffh 0300h page 3 page 2 program memory a for example, if the movt xa, @pcde instruction is located in a as shown in the diagram above, the table data specified by the contents of the register pair de not of page 2 but of page 3 is transferred to register pair xa.
288 chapter 10 instruction set application example: transfers the 16-byte data of addresses xxf0h to xxffh of the program memory to addresses 30h to 4fh the data memory. sub: sel mb0 mov hl, #30h ; hl 30h mov de, #0f0h ; de f0h loop: movt xa, @pcde ; xa table data mov @hl, xa ; (hl) xa incs hl ; hl hl + 2 incs hl incs e ; e e + 1 br loop ret org xxf0h db xxh, xxh, ... ; table data movt xa, @pcxa function: ? if m pd75304, 75304b xa rom (pc 11C8 + xa) ? if m pd75306, 75306b, 75308, 75308b, 75p308 xa rom (pc 12C8 + xa) ? if m pd75312, 75312b, 75316, 75316b, 75p316, 75p316a, 75p316b xa rom (pc 13C8 + xa) transfers the high-order bit of the program counter (pc) and the low-order 4 bits of the table data in the program memory addressed by the contents of register pair xa to register a, and the high-order 4 bits to register x. the high-order bit of the table address is determined by the contents of the program counter (pc) when executing this instruction. in the table area, it is necessary to program necessary data beforehand with the assembler directive (db instruction). the program counter (pc) is not affected by the execution of this instruction. precaution: as with movt xa, @pcde, if the instruction is located in address xxffh, the table data of the next page is transferred.
289 chapter 10 instruction set 10.4.3 arithmetic operation instruction adds a, #n4 function: a a + n4; skip if carry. n4 = i 3C0 : 0h to fh adds binary 4-bit immediate data n4 to the contents of register a. if carry turns up as the result of the addition, skip one instruction that follows. the carry flag is not affected in this case. if instructions addc a, @hl and subc a, @hl are combined, they turn into the notation adjust instruction (refer to 10.1.4 notation adjust instruction ). adds a, @hl function: a a + (hl); skip if carry. adds binarily the contents of the data memory addressed by register pair hl to the contents of register a. if carry occurs as the result of the addition, skip one instruction that follows. the carry flag is not affected in this case. addc a, @hl function: a, cy a + (hl) + cy adds binarily the contents of the data memory addressed by register pair hl, including the carry flag, to the contents of register a. if carry turns up as the result of the addition, the carry flag is set. if carry does not occur, the carry flag is reset. if the adds, #n4 instruction is entered after this instruction and if carry occurs in the latter instruction, the former instruction is skipped. if carry does not occur, the adds a, #n4 instruction is executed, and a function which disables the adds a, #n4 instructions skip function is generated. thus, these instructions can be combined to be utilized in the notation adjust (refer to 10.1.4 notation adjust instruction ). subc a, @hl function: a, cy a C (hl) C cy subtracts the contents of the data memory addressed by register pair hl, including the carry flag, from the contents of register a. if borrow occurs as the result, the carry flag is set. if borrow does not occur, the carry flag is reset. if the adds, #n4 instruction is entered after this instruction and if borrow does not occur in the latter instruction, the former instruction is skipped. if borrow occurs, the adds a, #n4 instruction is executed, and a function which disables the adds a, #n4 instructions skip function is generated. thus, these instructions can be combined to be utilized in the notation adjust (refer to 10.1.4 notation adjust instruction ).
290 chapter 10 instruction set subs a, @hl function: a a C (hl); skip if borrow subtracts the contents of the data memory addressed by register pair hl from the contents of register a. if borrow occurs as the result, skip one instruction that follows. the carry flag is not affected in this case. and a, #n4 function: a a ^ n4, n4 = i 3C0 : 0h to fh operates and on the contents of register a and 4-bit immediate data n4. sets the result to register a. application example: sets the high-order 2 bits of the accumulator to 0. and a, #0011b and a, @hl function: a a ^ (hl) operates and on the contents of register a and those of the data memory addressed by register pair hl. sets the result to register a. or a, #n4 function: a a v n4, n4 = i 3C0 : 0h to fh operates or on the contents of register a and 4-bit immediate data n4. sets the result to register a. application example: sets the low-order 3 bits of the accumulator to 1. or a, #0111b or a, @hl function: a a v (hl) operates or on the contents of register a and those of the data memory addressed by register pair hl.
291 chapter 10 instruction set xor a, #n4 function: a a v n4, n4 = i 3C0 : 0h to fh operates exclusive or on the contents of register a and 4-bit immediate data n4. sets the result to regiser a. application example: reverse the highest bit of the accumulator. xor a, #1000b xor a, @hl function: a a v (hl) operates exclusive or on the contents of register a and those of the data memory addressed by register pair hl.
292 chapter 10 instruction set 10.4.4 accumulator manipulation instruction rorc a function: cy a 0 , a nC1 a n , a 3 cy (n = 1 - 3) rotates the contents of register a (4-bit accumulator), including the carry flag, to the right 1 bit after another. not a function: a a takes the complement of 1 (reverse each bit) of register a (4-bit accumulator). 0 cy 0 3 1 2 0 1 1 0 a before execution 1 0010 after execution rorc a . . . .
293 chapter 10 instruction set 10.4.5 increment/decrement instruction incs reg function: reg reg + 1; skip if reg = 0 increments the contents of register reg (x, a, h, l, d, e, b, c). if reg = 0 as the result, the following one instruction is skipped. incs @hl function: (hl) (hl) + 1; skip if (hl) = 0 increments the contents of the data memory addressed by register pair hl. if the contents of the data memory becomes 0 as the result, the following one instruction is skipped. incs mem function: (mem) (mem) + 1; skip if (mem) = 0, mem = d 7C0 : 00h to ffh increments the contents of the data memory addressed by 8-bit immediate data mem. if the contents of the data memory becomes 0, the following one instruction is skipped. decs reg function: reg reg C 1; skip if reg = fh decrements the contents of register reg (x, a, h, l, d, e, b, c). if reg = fh as the result, the following one instruction is skipped.
294 chapter 10 instruction set 10.4.6 comparison instruction ske reg, #n4 function: skip if reg = n4, n4 = i 3C0 : 0h to fh skips the following one instruction if the contents of register reg (x, a, h, l, d, e, b, c) are equal to 4- bit immediate data n4. ske @hl, #n4 function: skip if (hl) = n4, n4 = i 3C0 : 0h to fh skips the following one instruction if the contents of the data memory addressed by register pair hl are equal to 4-bit immediate data n4. ske a, @hl function: skip if a = (hl) skips the following one instruction if the contents of register a are equal to the contents of the data memory addressed by register pair hl. ske a, reg function: skip if a = reg skips the following one instruction if the contents of register a are equal to the contents of register reg (x, a, h, l, d, e, b, c).
295 chapter 10 instruction set 10.4.7 carry flag manipulation instruction set1 cy function: cy 1 sets the carry flag. clr1 cy function: cy 0 clears the carry flag. skt cy function: skip if cy = 1 skips the following one instruction if the carry flag is 1. not1 cy function: cy cy reverses the carry flag; to 1 if 0, and to 0 if 1.
296 chapter 10 instruction set 10.4.8 memory bit manipulation instruction set1 mem. bit function: (mem. bit) 1, mem = d 7C0 : 00hCffh, bit = b 1C0 : 0C3 sets the bit which is specified by 2-bit immediate data bit of the address which is indicated by 8-bit immediate data mem. set1 fmem. bit set1 pmem. @l set1 @h + mem. bit function: (bit specified by the operand) 1 sets the bit of the data memory specified by bit manipulation addressing (fmem. bit, pmem. @l, @h + mem. bit). clr1 mem. bit function: (mem. bit) 0, mem = d 7C0 : 00hCffh, bit = b 1C0 : 0C3 clears the bit which is specified by 2-bit immediate data bit of the address which is indicated by 8-bit immediate data mem. clr1 fmem. bit clr1 pmem. @l clr1 @h + mem. bit function: (bit specified by the operand) 0 clears the bit of the data memory specified by bit manipulation addressing (fmem. bit, pmem. @l, @h + mem. bit). skt mem. bit function: skip if (mem. bit) = 1 mem = d 7C0 : 00hCffh, bit = b 1C0 : 0C3 skips the following one instruction if the bit specified by the 2-bit immediate data bit of the address indicated by 8-bit immediate data mem is 1.
297 chapter 10 instruction set skt fmem. bit skt pmem. @l skt @h + mem. bit function: skip if (bit specified by operand) = 1 skips the following one instruction if the bit of the data memory specified by the bit manipulation addressing (fmem. bit, pmem. @l, @h + mem. bit) is 1. skf mem. bit function: skip if (mem. bit) = 0 mem = d 7C0 : 00hCffh, bit = b 1C0 : 0C3 skips the following one instruction if the bit specified by 2-bit immediate data bit of the address indicated by 8-bit immediate data mem is 0. skf fmem. bit skf pmem. @l skf @h + mem. bit function: skip if (bit specified by operand) = 0 skips the following one instruction if the data memory bit specified by the bit manipulation addressing (fmem. bit, pmem. @l, @h + mem. bit) is 0. sktclr fmem. bit sktclr pmem. @l sktclr @h + mem. bit function: skip if (bit specified by operand) = 1 then clear if the data memory bit specified by the bit manipulation addressing (fmem. bit, pmem. @l, @h + mem. bit) is 1, the following one instruction is skipped and the bit is cleared to 0. and1 cy, fmem. bit and1 cy, pmem. @l and1 cy, @h + mem. bit function: cy cy ^ (bit specified by operand) operates and on the contents of the carry flag and those of the data memory specified by the bit manipulation addressing (fmem. bit, pmem. @l, @h + mem. bit), and then sets the result to the carry flag.
298 chapter 10 instruction set or1 cy, fmem. bit or1 cy, pmem. @l or1 cy, @h + mem. bit function: cy cy v (bit specified by operand) operates or on the contents of the carry flag and those of the bit of the data memory specified by the bit manipulation addressing (fmem. bit, pmem. @l, @h + mem. bit), and then sets the result to the carry flag. xor1 cy, fmem. bit xor1 cy, pmem. @l xor1 cy, @h + mem. bit function: cy cy v (bit specified by operand) operates exclusive or on the contents of the carry flag and those of the bit of the data memory specified by the bit manipulation addressing (fmem. bit, pmem. @l, @h + mem. bit), and then sets the result to the carry flag.
299 chapter 10 instruction set 10.4.9 branch instruction br addr function: ? if m pd75304, 75304b pc 11C0 addr: addr = 000h to fffh ? if m pd75306, 75306b, 75308, 75308b, 75p308 pc 12C0 addr: addr = 0000h to 177fh ( m pd75306, 75306b) addr = 0000h to 1f7fh ( m pd75308, 75308b, 75p308) ? if m pd75312, 75312b, 75316, 75316b, 75p316, 75p316a, 75p316b pc 13C0 addr: addr = 0000h to 2f7fh ( m pd75312, 75312b) addr = 0000h to 3f7fh ( m pd75316, 75316b, 75p316, 75p316a, 75p316b) branches to the address addressed by immediate data addr. this instruction is the assemblers directive, and is replaced by the assembler during assembly by the most adequate instruction among instruction br !addr, brcb !caddr and br $addr. however, the m pd75304, 75304b does not have the br !addr instruction. br !addr function: ? if m pd75306, 75306b, 75308, 75308b, 75p308, pc 12C0 addr: addr = 0000h to 1f7fh ( m pd75306, 75306b) addr = 0000h to 1f7fh ( m pd75308, 75308b, 75p308) ? if m pd75312, 75312b, 75316, 75316b, 75p316, 75p316a, 75p316b, pc 13C0 addr: addr = 0000h to 2f7fh ( m pd75312, 75312b) addr = 0000h to 3f7fh ( m pd75316, 75316b, 75p316, 75p316a, 75p316b) the immediate data addr is transferred to the program counter (pc) and then is branched to the address addressed by pc. branching can be done to the entire space of the program memory. however, the m pd75304, 75304b does not have the br !addr instruction. br $addr function: pc addr, addr = (pc C 15) to (pc C1), (pc + 2) to (pc + 16) this is the relative branch instruction with the branch range of (C15 to C1 and +2 to +16) from the current address. it is not affected by the page boundary or the block boundary.
300 chapter 10 instruction set brcb !caddr function: pc 11C0 caddr, caddr = a 11C0 : 000h to fffh branches to the address in which the program counters low-order 12 bits (pc 11C0 ) are replaced by 12- bit immediate data caddr (a 11C0 ). the m pd75304, 75304bs program counter consists of 11 bits, and so branching can be done by this instruction to the entire space. the m pd75306, 75306b, 75308, 75308b, 75p308 cannot change pc 12 , and so branching is done within the block. the m pd75312, 75312b, 75316, 75316b, 75p316, 75p316a, 75p316b cannot change pc 13 and pc 12 , and so branching is done within the block. precaution: the brcb !caddr instruction normally branches within the block in which this instruction exists. however, if the 1st byte is located in address 0ffeh or 0fffh, it does not branch in block 0 but in block 1. if the brcb !caddr instruction is located in a or b in the diagram above, it does not branch in block 0 but in block 1. tbr addr function: this is the assembler directive to define the geti instruction table. it is used when replacing the 3-byte br instruction with the geti instruction. the branch destination address of the 3-byte br instruction is described in addr. for details, refer to ra75x assembler package users manual-language (eeu-1364) . 7 0 0fffh 1000h block 1 block 0 program memory 0ffeh a b
301 chapter 10 instruction set 10.4.10 subroutine stack control instruction call !addr function: ? if m pd75304, 75304b (sp C 1) pc 7C4 , (sp C 2) pc 3C0 , (sp C 3) mbe, 0, 0, 0, (sp C 4) pc 11C8 , pc 11C0 addr sp (sp C 4) addr = a 11C0 : 000h to fffh ? if m pd75306, 75306b, 75308, 75308b, 75p308 (sp C 1) pc 7C4 , (sp C 2) pc 3C0 , (sp C 3) mbe, 0, 0, pc 12 , (sp C 4) pc 12C8 , pc 12C0 addr, sp (sp C 4) addr = a 12C0 : 0000h to 177fh ( m pd75306, 75306b) 0000h to 1f7fh ( m pd75308, 75308b, 75p308) ? if m pd75312, 75312b, 75316, 75316b, 75p316, 75p316a, 75p316b (sp C 1) pc 7C4 , (sp C 2) pc 3C0 , (sp C 3) mbe, 0, pc 13 , pc 12 , (sp C 4) pc 13C8 , pc 13C0 addr, sp (sp C 4) addr = a 13C0 : 0000h to 2f7fh ( m pd75312, 75312b) 0000h to 3f7fh ( m pd75316, 75316b, 75p316, 75p316a, 75p316b) branches to the address addressed by the immediate data addr after saving the contents of the program counter (pc: return address) and the mbe to the data memory (stack) addressed by the stack pointer (sp) and decrementing the stack pointer (sp). branching is done to the entire space of the program memory.
302 chapter 10 instruction set callf !faddr function: ? if m pd75304, 75304b (sp C 1) pc 7C4 , (sp C 2) pc 3C0 , (sp C 3) mbe, 0, 0, 0, (sp C 4) pc 11C8 , sp (sp C 4), pc (0, a 10C0 ) faddr = a 10C0 : 000h to 7ffh ? if m pd75306, 75306b, 75308, 75308b, 75p308 (sp C 1) pc 7C4 , (sp C 2) pc 3C0 , (sp C 3) mbe, 0, 0, pc 12 , (sp C 4) pc 12C8 , sp (sp C 4), pc (00, a 10C0 ) faddr = a 10C0 : 000h to 7ffh ? if m pd75312, 75312b, 75316, 75316b, 75p316, 75p316a, 75p316b (sp C 1) pc 7C4 , (sp C 2) pc 3C0 , (sp C 3) mbe, 0, pc 13 , pc 12 , (sp C 4) pc 13C8 , sp (sp C 4), pc (000, a 10C0 ) faddr = a 10C0 : 000h to 7ffh branches to the address addressed by the 11-bit immediate data faddr after saving the contents of the program counter (pc; return address) and the mbe to the data memory (stack) addressed by the stack pointer (sp) and decrementing the sp. the range that can be called is limited to addresses 000h to 7ffh (0 to 2047). tcall addr function: this is the assembler directive to define the geti instruction table. it is used when replacing the 3-byte call instruction with the geti instruction. the call address of the 3-byte call instruction is described in addr. for details, refer to ra75x assembler package users manual-language (eeu-1364) .
303 chapter 10 instruction set ret function: ? if m pd75304, 75304b pc 11C8 (sp), mbe, x, x, x, (sp + 1), pc 3C0 (sp + 2), pc 7C4 (sp + 3), sp (sp + 4) ? if m pd75306, 75306b, 75308, 75308b, 75p308 pc 11C8 (sp), mbe, x, x, pc 12 (sp + 1), pc 3C0 (sp + 2) pc 7C4 (sp + 3), sp (sp + 4) ? if m pd75312, 75312b, 75316, 75316b, 75p316, 75p316a, 75p316b pc 11C8 (sp), mbe, x, pc 13 , pc 12 (sp + 1), pc 3C0 (sp + 2), pc 7C4 (sp + 3), sp (sp + 4) restores the contents of the data memory (stack) addressed by the stack pointer (sp) in the program counter (pc) and the memory bank enable flag (mbe) and then increments the contents of the sp. precaution: the program status word (psw) is not restored other than in the mbe. rets function: ? if m pd75304, 75304b pc 11C8 (sp), mbe, x, x, x (sp + 1), pc 3C0 (sp + 2), pc 7C4 (sp + 3), sp (sp + 4), then skip unconditionally ? if m pd75306, 75306b, 75308, 75308b, 75p308 pc 11C8 (sp), mbe, x, x, pc 12 (sp + 1), pc 3C0 (sp + 2), pc 7C4 (sp + 3), sp (sp + 4), then skip unconditionally ? if m pd75312, 75312b, 75316, 75316b, 75p316, 75p316a, 75p316b pc 11C8 (sp), mbe, x, pc 13 , pc 12 (sp + 1), pc 3C0 (sp + 2), pc 7C4 (sp + 3), sp (sp + 4), then skip unconditionally restores the contents of the data memory (stack) addressed by the stack pointer (sp) in the program counter (pc) and the memory bank enable flag (mbe), increments the contents of the sp and then skips unconditionally. precaution: the program status word (psw) is not restored other than in the mbe.
304 chapter 10 instruction set reti function: ? if m pd75304, 75304b pc 11C8 (sp), mbe, x, x, x (sp + 1), pc 3C0 (sp + 2), pc 7C4 (sp + 3), psw l (sp + 4), psw h (sp + 5), sp (sp + 6) ? if m pd75306, 75306b, 75308, 75308b, 75p308 pc 11C8 (sp), mbe, x, x, pc 12 (sp + 1), pc 3C0 (sp + 2) pc 7C4 (sp + 3), psw l (sp + 4), psw h (sp + 5) sp (sp + 6) ? if m pd75312, 75312b, 75316, 75316b, 75p316, 75p316a, 75p316b pc 11C8 (sp), mbe, x, pc 13 , pc 12 (sp + 1), pc 3C0 (sp + 2) pc 7C4 (sp + 3), psw l (sp + 4), psw h (sp + 5) sp (sp + 6) restores the contents of the data memory (stack) addressed by the stack pointer (sp) in the program counter (pc) and the program status word (psw) and then increments the sp. it is used when returning from interrupt servicing routine. push rp function: (sp C 1) rp h , (sp C 2) rp l , sp sp C 2 saves the contents of the register pair rp (xa, hl, de, bc) to the data memory (stack) addressed by the stack pointer (sp) and then decrements the sp. the upper part (rp h : x, h, d, b) of the register pair is saved to the stack addressed by (sp C 1), and the lower part (rp l : a, l, e, c) to the stack addressed by (sp C 2). push bs function: (sp C 1) mbs, (sp C 2) 0, sp sp C 2 saves the contents of the memory bank selection register (mbs) to the data memory (stack) addressed by the stack pointer (sp) and then decrements the sp. pop rp function: rp l (sp), rp h (sp + 1), sp sp + 2 returns the contents of the data memory (stack) addressed by the stack pointer (sp) to register pair rp (xa, hl, de, bc) and then increments the sp. the contents of (sp) are restored in the lower part (rp l : a, l, e, c) of the register pair, and the contents of (sp + 1) are restored in the upper part (rp h : x, h, d, b).
305 chapter 10 instruction set pop bs function: mbs (sp + 1), sp sp + 2 returns the contents of the data memory (stack) addressed by the stack pointer (sp) to the memory bank selection register (mbs) and then increments the sp.
306 chapter 10 instruction set 10.4.11 interrupt control instruction ei function: ime 1 sets (1) the interrupt mask enable flag and enables the interrupt. whether the interrupt is received or not is controlled by each interrupt enable flag. ei iexxx function: iexxx 1, xxx = n 5 , n 2C0 sets (1) the interrupt enable flag (iexxx) and puts the interrupt to reception status. (xxx = bt, csi, t0, 0, 1, 2, 4, w) di function: ime 0 resets (0) the interrupt mask enable flag and disables all the interrupts regardless of the contents of each interrupt enable flag. di iexxx function: iexxx 0, xxx = n 5 , n 2C0 resets (0) the interrupt enable flag (iexxx) and disables the reception of the interrupt. (xxx = bt, csi, t0, 0, 1, 2, 4, w)
307 chapter 10 instruction set 10.4.12 input/output instruction in a, portn function: a portn, n = n 3C0 : 0C7 transfers the contents of the port specified by portn (n = 0 to 7) to register a. precaution: when executing this instruction, it is necessary to set mbe = 0 or (mbe = 1 and mbs = 15). only 0 to 7 can be specified to n. by specifying the input/output mode, the output latch data (output mode) or the pin data (input mode) is incorporated. in xa, portn function: a portn, x portn + 1, n = n 3C0 : 4, 6 transfers the contents of the port specified by portn (n = 4, 6) to register a, and the contents of the next port to register x. precaution: only 4 or 6 can be specified as n. when executing this instruction, it is necessary to set mbe = 0 or (mbe = 1 and mbs = 15). by specifying the input/output mode, the output latch data (output mode) or the pin data (input mode) is incorporated. out portn, a function: portn a, n = n 3C0 : 2C7 transfers the contents of register a to the output latch of the port specified by portn (n = 2C7). precaution: when executing this instruction, it is necessary to set mbe = 0 or (mbe = 1 and mbs = 15). only 2 to 7 can be specified to n.
308 chapter 10 instruction set out portn, xa function: portn a, portn + 1 x, n = n 3C0 : 4, 6 transfers the contents of register a to the output latch of the port specified by portn (n = 4, 6) and the contents of register x to the output latch of the next port. precaution: when executing this instruction, it is necessary to set mbe = 0 or (mbe = 1 and mbs = 15). only 4 or 6 can be specified as n.
309 chapter 10 instruction set 10.4.13 cpu control instruction halt function: pcc. 2 1 sets the halt mode. (this instruction sets bit 2 of the processor clock control register.) precaution: make one instruction following the halt instruction a nop instruction. stop function: pcc. 3 1 sets the stop mode. (this instruction sets bit 3 of the processor clock control register.) precaution: make one instruction following the stop instruction a nop instruction. nop function: uses up 1 machine cycle without doing anything.
310 chapter 10 instruction set 10.4.14 special instruction sel mbn function: mbs n, n = n 3C0 : 0, 1, 15 note transfers 4-bit immediate data n to the memory bank selection register (mbs). only 0, 1 and 15 (on the m pd75312b, 75316b, 75p316a, 75p316b: 0, 1, 2, 3, and 15 can be specified as n. note on the m pd75312b, 75316b, 75p316a, 75p316b only, n = n 3C0 : 0, 1, 2, 3, 15. geti taddr function: taddr = t 5C0 , 0: 20hC7fh (i) if tbr instruction ? if m m m m m pd75304, 75304b pc 11C0 (taddr) 3C0 + (taddr + 1) ? if m m m m m pd75306, 75306b, 75308, 75308b, 75p308 pc 12C0 (taddr) 4C0 + (taddr + 1) ? if m m m m m pd75312, 75312b, 75316, 75316b, 75p316, 75p316a, 75p316b pc 13C0 (taddr) 5C0 + (taddr + 1) (ii) if tcall instruction ? if m m m m m pd75304, 75304b (sp C 4) (sp C 1) (sp C 2) pc 11C0 (sp C 3) mbe, 0, 0, 0 pc 11C0 (taddr) 3C0 + (taddr + 1) sp (sp C 4) ? if m m m m m pd75306, 75306b, 75308, 75308b, 75p308 (sp C 4) (sp C 1) (sp C 2) pc 11C0 (sp C 3) mbe, 0, 0, pc 12 pc 12C0 (taddr) 4C0 + (taddr + 1) sp (sp C 4) ? if m m m m m pd75312, 75312b, 75316, 75316b, 75p316, 75p316a, 75p316b (sp C 4) (sp C 1) (sp C 2) pc 11C0 (sp C 3) mbe, 0, pc 13 , pc 12 pc 13C0 (taddr) 5C0 + (taddr + 1) sp (sp C 4) (iii) if other than tbr or tcall instructions, executes the instruction whose instruction code is (taddr) (taddr + 1).
311 chapter 10 instruction set refers to the 2-byte data in the program memory address specified by (taddr), (taddr + 1) and executes it as the instruction. the range of reference table is 0020h to 007fh, and data is written in beforehand. if the 1-byte or 2- byte instruction is used, data is written in mnemonic as it is. if the 3-byte branch instruction or 3-byte call instruction is used, data is written by the assembler directive (tbr, tcall). addresses that can be specified as taddr are only in even numbers. precaution: 2-byte instructions that can be set in the reference table are limited to the 2-machine cycle instructions (brcb and callf instruction excluded). when setting two 1-byte instructions, combinations are limited as shown below. 1st byte instruction 2nd byte instruction mov a, @hl incs l mov @hl, a decs l xca a, @hl incs h decs h incs hl mov a, @de incs e xch a, @de decs e incs d decs d incs de mov a, @dl incs l xch a, @dl decs l incs d decs d as pc cannot be incremented during geti instruction execution, continues processing from the address following the geti instruction after executing the reference instruction. if the instruction preceding the geti instruction has the skip function, the geti instruction is skipped in the same manner as other 1-byte instructions. also, if the instruction referenced by the geti instruction has the skip function, the instruction immediately following the geti instruction is skipped. if an instruction with accumulation effect is referenced by the geti instruction, it is executed as follows. ? if the instruction immediately preceding the geti instruction has also the accumulation effect of the same group, the accumulation effect is removed if the geti instruction is executed and the referenced instruction is not skipped. ? if the instruction immediately following the geti instruction has also the accumulation effect, the accumulation generated by the referenced instruction is valid and the following instruction is skipped.
312 chapter 10 instruction set application example: replace mov hl, #00h mov xa, #0ffh call sub1 b sub2 with the geti instruction. code0 cseg ient hl00 : mov hl, #00h xaff : mov xa, #0ffh csub1 : tcall sub1 bsub2 : tbr sub2 geti hl00 ; mov hl, #00h geti bsub2 ; br sub2 geti csub1 ; call sub1 geti xaff ; mov xa, #0ffh ..... ..... ..... ..... .....
313 appendix a development tools appendix a development tools the following development tools are available for system development using the m pd75308. language processor ra75x relocatable assembler host machine part number os distribution media (product name) pc-9800 series ms-dos 3.5-inch 2hd m s5a13ra75x (ver. 3.30 to ver. 6.2 note ) 5-inch 2hd m s5a10ra75x ibm pc/at tm refer to os of ibm pc . 3.5-inch 2hc m s7b13ra75x or its compatible machine 5-inch 2hc m s7b10ra75x prom writing t ools hardware pg-1500 this prom programmer allows programming, in stand-alone mode or via operation from a host machine, of a single-chip microcontroller with on-chip prom by connection of the board provided and a separately available programmer adapter. programming of a typical prom of between 256 and 1m bits is also possible. pa-75p308gf prom programmer adapter for m pd75p308, 75p316, 75p316a used for connection to the pa-75p308k pg-1500. pa-75p316bgc prom programmer adopter for m pd75p316b, used for connection to the pg-1500. pa-75p316bgk software pg-1500 connects pg-1500 and host machine via a serial and parallel interface, and controls the controller pg-1500 on the host machine. host machine part number os distribution media (product name) pc-9800 series ms-dos 3.5-inch 2hd m s5a13pg1500 (ver. 3.30 to ver. 6.2 note ) 5-inch 2hd m s5a10pg1500 ibm pc/at refer to os of ibm pc . 3.5-inch 2hd m s7b13pg1500 or its compatible machine 5-inch 2hc m s7b10pg1500 note ver. 5.00 or later provides a task swap function, but this function cannot be used in combination with this software. remark operation of the relocatable assembler and pg-1500 controller is assured only on the host machines and operating system quoted above.
314 appendix a development tools debugging t ools in-circuit emulators (ie-75000-r and ie-75001-r) are available as m pd75308 debugging tools. the system configuration is shown below. hardware ie-75000-r note 1 the ie-75000-r is an in-circuit emulator for performing hardware and software debugging in the development of application systems using the 75x series. the ie-75000-r is used in combination with an emulation probe. efficient debugging can be performed by connecting the ie-75000-r to a host machine and prom programmer. ie-75000-r-em emulation board for evaluating application systems that use the 75x series. used in combination with the ie-75000-r or ie-75001-r. incorporated in the ie-75000-r. ie-75001-r note 2 the ie-75001-r is an in-circuit emulator for performing hardware and software debugging in the development of application systems using the 75x series. the ie-75001-r is used in combination with the separately available ie-75000-r-em emulation board and emulation probe. efficient debugging can be performed by connecting the ie-75001-r to a host machine and prom programmer. ep-75308gf-r emulation probe for the m pd75308gf. connected to the ie-75000-r, or to the ie-75001-r and ie-75000-r-em. ev-9200g-80 an 80-pin conversion socket (ev-9200g-80) is also provided to simplify connection to the user system. ep-75308bgc-r emulation probe for the m pd75308bgc. connected to the ie-75000-r, or to the ie-75001-r and ie-75000-r-em. ev-9200gc-80 an 80-pin conversion socket (ev-9200gc-80) is also provided to simplify connection to the user system. ep-75308bgk-r emulation probe for the m pd75308bgk. connected to the ie-75000-r, or to the ie-75001-r and ie-75000-r-em. ev-9500gk-80 an 80-pin conversion socket (ev-9500gk-80) is also provided to simplify connection to the user system. software ie control connects the ie-75000-r or ie-75001-r to the host machine via rs-232-c or centronics program i/f interface, and controls the ie-75000-r or ie-75001-r on the host machine. host machine part number os distribution media (product name) pc-9800 series ms-dos 3.5-inch 2hd m s5a13ie75x (ver. 3.30 to ver. 6.2 note ) 5-inch 2hd m s5a10ie75x ibm pc/at refer to os of ibm pc . 3.5-inch 2hc m s7b13ie75x or its compatible machine 5-inch 2hc m s7b10ie75x notes 1. maintenance product 2. ie = 75000-r-em is sold separately. 3. ver. 5.00 or later provides a task swap function, but this function cannot be used in combination with this software. remark operation of the ie control program is assured only on the host machines and operating system quoted above.
315 appendix a development tools os of ibm pc the following os is supported as the os for ibm pc. os version pc dos ver. 3.1 to ver. 6.3 j6.1/v note to j6.3/v note ms-dos ver. 5.0 to ver. 6.22 5.0/v note to 6.2/v note ibm dos j5.02/v note note only the english mode is supported. caution ver. 5.00 or later provides a task swap function, but this function cannot be used in combination with this software.
316 appendix a development tools in-circuit emulator ie-75000-r ie-75001-r note 1 ie-75000-r-em ie control program host machine pc-9800 series lbm pc/at (symbolic debugging capability) rs-232-c prom programmer pg-1500 + programmer adapter pa-75p308gf pa-75p308k pa-75p316bgc pa-75p316bgk emulation probe ep-75308gf-r ep-75308bgc-r ep-75308bgk-r pd75p308 pd75p316 pd75p316a pd75p316b m user system centronics l/f notes note 2 pg-1500 controller on-chip prom products m m m ie-75000-r-em is not incorporated in ie-75001-r (sold separately). ev-9200g-80 ev-9200gc-80 ev-9500gk-80 development tool configuration relocatable assembler 1. 2.
317 appendix b mask rom ordering procedure appendix b mask rom ordering procedure on completion of the m pd75308 program, the following procedure should be used to order the mask rom. 1 mask rom order reservation please notify your sales agent or nec sales department of your intention to order a mask rom. 2 creation of order medium the medium for a mask rom order is uveprom or a 3.5 or 5-inch ibm format floppy disk (outside japan only). when uveprom is used for the order, three uv-eproms with identical contents should be prepared (in the case of products with a mask option, the mask option data should be submitted on a mask option information sheet). 3 necessary documentation when ordering a mask rom, the following documents should be filled out. a. mask rom order form b. mask rom order check sheet c. mask option information sheet (only required for mask option products) 4 ordering the media created in 2 and documentation filled out in 3 should be submitted to the agent or nec sales department by the order reservation date. caution for details, please refer to the technical document rom code ordering procedure (iem- 1366).
318 appendix b mask rom ordering procedure [memo]
319 appendix c instruction index appendix c instruction index c.1 instruction index (in function) [transfer instructions] mov a, #n4 ............................................... 281 mov reg 1, #n4 ......................................... 281 mov rp, #n8 .............................................. 281 mov a, @rpa ............................................ 282 mov xa, @hl .......................................... 282 mov @hl, a ............................................. 282 mov @hl, xa .......................................... 282 mov a, mem ............................................. 282 mov xa, mem ........................................... 283 mov mem, a ............................................. 283 mov mem, xa ........................................... 283 mov a, reg ................................................ 283 mov xa, rp ............................................... 283 mov reg1, a .............................................. 283 mov rp1, xa ............................................. 284 xch a, @rpa ............................................ 284 xch xa, @hl .......................................... 285 xch a, mem ............................................. 285 xch xa, mem ........................................... 284 xch a, reg1 .............................................. 284 xch xa, rp ............................................... 284 [table reference instructions] movt xa, @pcde ..................................... 286 movt xa, @pcxa ..................................... 286 [arithmetic instructions] adds a, #n4 ............................................... 289 adds a, @hl ............................................. 289 addc a, @hl ............................................. 289 subs a, @hl ............................................. 290 subc a, @hl ............................................. 289 and a, #n4 ............................................... 290 and a, @hl ............................................. 290 or a, #n4 ............................................... 290 or a, @hl ............................................. 290 xor a, #n4 ............................................... 291 xor a, @hl ............................................. 291 [accumulator manipulation instructions] rorc a ........................................................ 292 not a ........................................................ 292 [increment/decrement instructions] incs reg ..................................................... 293 incs @hl .................................................. 293 incs mem .................................................. 293 decs reg ..................................................... 293 [comparison instructions] ske reg, #n4 ............................................ 294 ske @hl, #n4 ......................................... 294 ske a, @hl ............................................. 294 ske a, reg ................................................ 294 [carry flag manipulation instructions] set1 cy ..................................................... 295 clr1 cy ..................................................... 295 skt cy ..................................................... 295 not1 cy ..................................................... 295 [memory bit manipulation instructions] set1 mem. bit ........................................... 296 set1 fmem. bit .......................................... 296 set1 pmem. @l ........................................ 296 set1 @h + mem. bit ................................ 296 clr1 mem. bit ........................................... 296 clr1 fmem. bit .......................................... 296 clr1 pmem. @l ........................................ 296 clr1 @h + mem. bit ................................ 296 skt mem. bit ........................................... 296 skt fmem. bit .......................................... 297 skt pmem. @l ........................................ 297 skt @h + mem. bit ................................ 297 skf mem. bit ........................................... 297 skf fmem. bit .......................................... 297
320 appendix c instruction index skf pmem. @l ........................................ 297 skf @h + mem. bit ................................ 297 sktclr fmem. bit .......................................... 297 sktclr pmem. @l ........................................ 297 sktclr @h + mem. bit ................................ 297 and1 cy, fmem. bit ................................... 297 and1 cy, pmem. @l ................................. 297 and1 cy, @h + mem. bit ......................... 297 or1 cy, fmem. bit ................................... 298 or1 cy, pmem. @l ................................. 298 or1 cy, @h + mem. bit ......................... 298 xor1 cy, fmem. bit ................................... 298 xor1 cy, pmem. @l ................................. 298 xor1 cy, @h + mem. bit ......................... 298 [branch instructions] br addr ................................................... 299 br !addr .................................................. 299 br $addr ................................................. 299 brcb !caddr ................................................ 300 tbr addr ................................................... 300 call !addr .................................................. 301 callf !faddr ................................................ 302 tcall addr ................................................... 302 ret .......................................................... 303 rets .......................................................... 303 reti .......................................................... 304 push rp ....................................................... 304 push bs ..................................................... 304 pop rp ....................................................... 304 pop bs ..................................................... 305 [interrupt control instructions] ei .......................................................... 306 ei iexxx ................................................. 306 di .......................................................... 306 di iexxx ................................................. 306 [input/output instructions] in a, portn ......................................... 307 in xa, portn ...................................... 307 out portn, a ......................................... 307 out portn, xa ...................................... 308 [cpu control instructions] halt .......................................................... 309 stop .......................................................... 309 nop .......................................................... 309 [special instructions] sel mbn ................................................... 310 geti taddr .................................................. 310
321 appendix c instruction index c.2 instruction index (in general) [a] addc a, @hl ............................................. 289 adds a, #n4 ............................................... 289 adds a, @hl ............................................. 289 and a, #n4 ............................................... 290 and a, @hl ............................................. 290 and1 cy, fmem. bit ................................... 297 and1 cy, pmem. @l ................................. 297 and1 cy, @h + mem. bit ......................... 297 [b] br addr ................................................... 299 br !addr .................................................. 299 br $addr ................................................. 299 brcb !caddr ................................................ 300 [c] call !addr .................................................. 301 callf !faddr ................................................ 302 clr1 cy ..................................................... 296 clr1 fmem. bit .......................................... 296 clr1 mem. bit ........................................... 296 clr1 pmem. @l ........................................ 296 clr1 @h + mem. bit ................................ 296 [d] decs reg ..................................................... 293 di .......................................................... 306 di iexxx ................................................. 306 [e] ei .......................................................... 306 ei iexxx ................................................. 306 [g] geti taddr .................................................. 310 [h] halt .......................................................... 309 [i] in a, portn ......................................... 307 in xa, portn ...................................... 307 incs mem .................................................. 293 incs reg ..................................................... 293 incs @hl .................................................. 293 [m] mov a, mem ............................................. 282 mov a, reg ................................................ 283 mov a, #n4 ............................................... 281 mov a, @rpa ............................................ 282 mov mem, a ............................................. 283 mov mem, xa ........................................... 283 mov reg1, a .............................................. 283 mov reg1, #n4 .......................................... 281 mov rp, #n8 .............................................. 281 mov rp1, xa ............................................. 284 mov xa, mem ........................................... 283 mov xa, rp ............................................... 284 mov xa, @hl .......................................... 282 mov @hl, a ............................................. 282 mov @hl, xa .......................................... 282 movt xa, @pcde ..................................... 286 movt xa, @pcxa ..................................... 288 [n] nop .......................................................... 309 not a ........................................................ 292 not1 cy ..................................................... 295 [o] or a, #n4 ............................................... 290 or a, @hl ............................................. 290 or1 cy, fmem. bit ................................... 298 or1 cy, pmem. @l ................................. 298 or1 cy, @h + mem. bit ......................... 298 out portn, a ......................................... 307 out portn, xa ...................................... 308
322 appendix c instruction index [p] pop bs ..................................................... 305 pop rp ....................................................... 304 push bs ..................................................... 304 push rp ....................................................... 304 [r] ret .......................................................... 303 reti .......................................................... 304 rets .......................................................... 303 rorc a ........................................................ 292 [s] sel mbn ................................................... 310 set1 cy ..................................................... 295 set1 fmem. bit .......................................... 296 set1 mem. bit ........................................... 296 set1 pmem. @l ........................................ 296 set1 @h + mem. bit ................................ 296 ske a, reg ................................................ 294 ske a, @hl ............................................. 294 ske reg, #n4 ............................................ 294 ske @hl, #n4 ......................................... 294 skf fmem. bit .......................................... 297 skf mem. bit ........................................... 297 skf pmem. @l ........................................ 297 skf @h + mem. bit ................................ 297 skt cy ..................................................... 295 skt fmem. bit .......................................... 297 skt mem. bit ........................................... 296 skt pmem. @l ........................................ 297 skt @h + mem. bit ................................ 297 sktclr fmem. bit .......................................... 297 sktclr pmem. @l ........................................ 297 sktclr @h + mem. bit ................................ 297 stop .......................................................... 309 subc a, @hl ............................................. 289 subs a, @hl ............................................. 290 [t] tbr addr ................................................... 300 tcall addr ................................................... 302 [x] xch a, @rpa ............................................ 284 xch a, mem ............................................. 285 xch a, reg1 .............................................. 284 xch xa, @hl .......................................... 285 xch xa, mem ........................................... 284 xch xa, rp ............................................... 284 xor a, #n4 ............................................... 291 xor a, @hl ............................................. 291 xor1 cy, fmem. bit ................................... 298 xor1 cy, pmem. @l ................................. 298 xor1 cy, @h + mem. bit ......................... 298
323 appendix d hardware index appendix d hardware index [a] ackd ........................................................................ 135 acke ........................................................................ 135 ackt ........................................................................ 134 [b] bp0 to bp7 ................................................................ 75 bsb0 to bsb3 ......................................................... 217 bsye ........................................................................ 135 bt ............................................................................. 104 btm .......................................................................... 105 [c] clom ....................................................................... 102 cmdd ....................................................................... 134 cmdt ....................................................................... 134 coi............................................................................ 141 csie ......................................................................... 138 csim ......................................................................... 139 cy ............................................................................... 71 [i] ie0 ............................................................................. 224 ie1 ............................................................................. 224 ie2 ............................................................................. 224 ie4 ............................................................................. 224 iebt .......................................................................... 224 iecsi ........................................................................ 224 iet0 .......................................................................... 224 iew ........................................................................... 224 im0 ............................................................................ 229 im1 ............................................................................ 229 im2 ............................................................................ 229 ime............................................................................ 229 irq0 ......................................................................... 224 irq1 ......................................................................... 224 irq2 ......................................................................... 224 irq4 ......................................................................... 224 irqbt ....................................................................... 224 irqcsi ..................................................................... 224 irqt0 ....................................................................... 224 irqw ........................................................................ 224 ist0 ............................................................................ 72 [k] kr0 to kr7 .............................................................. 230 [l] lcdc ........................................................................ 194 lcdm ........................................................................ 192 [m] mbe ..................................................................... 35, 72 mbs ..................................................................... 35, 73 [p] pc ............................................................................... 53 pcc ............................................................................ 92 pmga, pmgb ............................................................ 81 poga ......................................................................... 87 port0 to port7 ...................................................... 75 psw ............................................................................ 70 [r] reld ........................................................................ 134 relt ......................................................................... 134 [s] sbic ......................................................................... 133 scc ............................................................................ 94 sio ............................................................................ 134 sk0 to sk2 ................................................................ 71 sp ............................................................................... 66 sva ........................................................................... 137
324 appendix d hardware index [t] t0 .............................................................................. 113 toe0 ........................................................................ 114 tm0 ........................................................................... 114 tmod0 ..................................................................... 113 [w] wm ............................................................................ 110 wup.......................................................................... 141
325 appendix e revision history appendix e revision history the following shows the revision history of this manual. chapter indicates the chapter of the previous edition. edition revision chapter 11th edition the m pd75p316bkk-t has been added to the applicable products. whole manual the m pd75312b and 75316b have been developed. the pa-75p316bgc, pa-75p316bgk have been developed. ms-dos ver. 5.00/5.00a for the pc-9800 series has been supported. 2.2.26 ic has been added. chapter 2 pin functions 2.6 caution of use of p00/int4 pin and reset pin has been added. figure 5-3. configuration of port 3n and 6n (n = 0 to 3) has been chapter 5 peripheral modified. hardware functions figure 5-4. configuration of ports 2 and 7 has been modified. figure 5-10. clock generator circuit block diagram has been modified and a note has been added to the figure. 5.2.2 (4) frequency divider has been added. 5.2.2 (5) when subsystem clock is not used has been added. a note has been added to table 5-5. maximum time required for system clock/cpu clock switching . a note has been added to table 6-1. interrupt source types . chapter 6 interrupt 6.3 (3) int0, int1 and int4 hardware has been modified. function precautions have been added to chapter 7 standby function . chapter 7 stand-by a note has been added to 7.4 standby mode application . function a note has been added to 7.4 (1) example of stop mode application . 12th edition the m pd75p316b has been developed. whole manual the note in figure 5-83. example of lcd drive power supply chapter 5 peripheral connection (with external split resistor) has been modified and a caution hardware functions has been added to this figure. the example in 6.6 v ector address sharing interrupt servicing has chapter 6 interrupt been modified. function the version of the supported os has been up-graded. appendix a development tools
326 appendix e revision history [memo]
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