View K9F5608R0D-JIB00_6869076.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

flash memory 1 k9f5608b0d k9f5608r0d k9f5608u0d k9f5608x0d * samsung electronics reserves the right to c hange products or specification without notice. information in this document is provided in relation to samsung products, and is subject to change without notice. nothing in this document shall be construed as granting any license, express or implied, by estoppel or otherwise, to any intellectual property rights in samsung products or technology. all information in this document is provided on as "as is" basis without guarantee or warranty of any kind. 1. for updates or additional information about samsu ng products, contact your nearest samsung office. 2. samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply.
flash memory 2 k9f5608b0d k9f5608r0d k9f5608u0d document title 32m x 8 bit nand flash memory revision history the attached datasheets are prepared and approved by samsung el ectronics. samsung el ectronics co., ltd. reserve the right to change the specifications. sams ung electronics will evaluate and reply to y our requests and questions about device. if you h ave any questions, please contact the samsung branch office near you. revision no. 0.0 0.1 0.2 1.0 1.1 1.2 remark advance advance preliminary final history initial issue 1. leaded package devices are eliminated 1. lockpre pin mode is eliminated 1. 2.65v -> 2.7v part changed. 2. leaded package devices are deleted. draft date may 16th. 2005 aug. 11th. 2005 oct. 17th. 2005 oct. 30th. 2005 dec. 30th 2005 may. 23th 2006 note : for more detailed features and specifications in cluding faq, please refer to samsung?s flash web site. http://www.samsung.com/products /semiconductor/flash/technicalinfo/datasheets.htm
flash memory 3 k9f5608b0d k9f5608r0d k9f5608u0d general description features ? voltage supply - 1.8v device(k9f5608r0d) : 1.65~1.95v - 2.7v device(k9f5608b0d) : 2.5~2.9v - 3.3v device(k9f5608u0d) : 2.7 ~ 3.6 v ? organization - memory cell array -(32m + 1024k)bit x 8 bit - data register - (512 + 16)bit x 8bit ? automatic program and erase - page program -(512 + 16)byte - block erase : - (16k + 512)byte ? page read operation - page size - (512 + 16)byte - random access : 15 s(max.) - serial page access : 50ns(min.) ? fast write cycle time - program time : 200 s(typ.) - block erase time : 2ms(typ.) 32m x 8 bit nand flash memory ? command/address/data multiplexed i/o port ? hardware data protection - program/erase lockout during power transitions ? reliable cmos floating-gate technology - endurance : 100k program/erase cycles - data retention : 10 years ? command register operation ? intelligent copy-back ? unique id for copyright protection ? package - k9f5608 b (u)0d-pcb0/pib0 48 - pin tsop i (12 x 20 / 0.5 mm pitch)- pb-free package - k9f5608x0d-jcb0/jib0 63- ball fbga ( 9 x 11 /0.8mm pitch , width 1.0 mm) - pb-free package - k9f5608u0d-fcb0/fib0 48 - pin wsop i (12x17x0.7mm)- pb-free package * k9f5608u0d-f(wsopi ) is the same device as k9f5608u0d-p(tsop1) except package type. offered in 32mx8bit , the k9f5608x0d is 256m bit with spare 8m bit capacity. the device is offered in 1.8v, 2.7v, 3.3v vcc. i ts nand cell provides the most cost-effective solution for the so lid state mass storage market. a program operation can be perfor med in typical 200 s on a 528-byte page and an erase operation can be performed in typical 2ms on a 16k-byte block. data in the page can be read out at 50ns cycle time per byte. the i/o pins serve as the ports for address and data input/output as well as comm and input. the on-chip write control automates all program and er ase functions includi ng pulse repetition, where required, and in ternal verification and margining of data. even the write- intensive systems can take advantage of the k9f5608x0d s extended reliability of 100k program/erase cycles by providing ecc(error corr ecting code) with real time mapping-out algorithm. the k9f5608x0d is an optimum solution for large nonvolatile storage applications such as solid state file storage and other por table applications requiring non-volatility. product list part number vcc range organization pkg type k9f5608r0d-j 1.65 ~ 1.95v x8 fbga k9f5608b0d-p 2.5 ~ 2.9v tsop1 k9f5608b0d-j fbga k9f5608u0d-p 2.7 ~ 3.6v tsop1 k9f5608u0d-j fbga k9f5608u0d-f wsop1
flash memory 4 k9f5608b0d k9f5608r0d k9f5608u0d pin configuration (tsop1) k9f5608b(u)0d-pcb0/pib0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 n.c n.c n.c n.c n.c n.c r/b re ce n.c n.c vcc vss n.c n.c cle ale we wp n.c n.c n.c n.c n.c n.c n.c n.c n.c i/o7 i/o6 i/o5 i/o4 n.c n.c n.c vcc vss n.c n.c n.c i/o3 i/o2 i/o1 i/o0 n.c n.c n.c n.c package dimensions 48-pin lead/lead free plastic thin small out-line package type(i) 48 - tsop1 - 1220f unit :mm/inch 0.787 0.008 20.00 0.20 #1 #24 0.16 +0.07 -0.03 0.008 +0.003 -0.001 0.50 0.0197 #48 #25 0.488 12.40 max 12.00 0.472 0.10 0.004 max 0.25 0.010 () 0.039 0.002 1.00 0.05 0.002 0.05 min 0.047 1.20 max 0.45~0.75 0.018~0.030 0.724 0.004 18.40 0.10 0~8 0.010 0.25 typ 0.125 +0.075 0.035 0.005 +0.003 -0.001 0.50 0.020 () 0.20 +0.07 -0.03
flash memory 5 k9f5608b0d k9f5608r0d k9f5608u0d 63-ball fbga (measured in millimeters) package dimensions 9.00 0.10 #a1 side view top view 1.00(max.) 0.45 0.05 4321 a b c d g bottom view 11.00 0.10 63- ? 0.45 0.05 0.80 x7= 5.60 11.00 0.10 0.80 x 5= 4.00 0.80 0.25(min.) 0.10max b a 2.80 2.00 9.00 0.10 (datum b) (datum a) 0.20 m a b ? 0.80 0.80 x11= 8.80 0.80 x 9= 7.20 65 9.00 0.10 e f h k9f5608x0d-jcb0/jib0 r/b /we /ce vss ale /wp /re cle nc nc nc nc vcc nc nc i/o0 i/o1 nc nc vccq i/o5 i/o7 vss i/o6 i/o4 i/o3 i/o2 vss nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c 3456 1 2 a b c d g e f h top view pin configuration (fbga) 2.00
flash memory 6 k9f5608b0d k9f5608r0d k9f5608u0d pin configuration (wsop1) k9f5608u0d-fcb0/fib0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 n.c n.c dnu n.c n.c n.c r/b re ce dnu n.c vcc vss n.c dnu cle ale we wp n.c n.c dnu n.c n.c n.c n.c dnu n.c i/o7 i/o6 i/o5 i/o4 n.c dnu n.c vcc vss n.c dnu n.c i/o3 i/o2 i/o1 i/o0 n.c dnu n.c n.c package dimensions 48-pin lead plastic very very thin small out-line package type (i) 48 - wsop1 - 1217f unit :mm 15.40 0.10 #1 #24 0.20 +0.07 -0.03 0.16 +0.07 -0.03 0.50typ (0.50 0.06) #48 #25 0.10 +0.075 -0.035 17.00 0.20 0 ~ 8 0.45~0.75 12.00 0.10 0.58 0.04 0.70 max (0.01min) 12.40max
flash memory 7 k9f5608b0d k9f5608r0d k9f5608u0d pin description note : connect all v cc and v ss pins of each device to common power supply outputs. do not leave v cc or v ss disconnected. pin name pin function i/o 0 ~ i/o 7 data inputs/outputs the i/o pins are used to input command, address and data, and to output data during read operations. the i/ o pins float to high-z when the chip is deselected or when the outputs are disabled. cle command latch enable the cle input controls the activating path for comma nds sent to the command register. when active high, commands are latched into the command register through the i/o ports on the rising edge of the we signal. ale address latch enable the ale input controls the activating path for addres s to the internal address registers. addresses are latched on the rising edge of we with ale high. ce chip enable the ce input is the device selection control. when the device is in the busy state, ce high is ignored, and the device does not return to standby mode in program or erase operation. regarding ce control during read operation, refer to ?page read? section of device operation. re read enable the re input is the serial data-out control, and when acti ve drives the data onto t he i/o bus. data is valid trea after the falling edge of re which also increments the inter nal column address counter by one. we write enable the we input controls writes to the i/o port. comm ands, address and data are latched on the rising edge of the we pulse. wp write protect the wp pin provides inadvertent write/erase protection during power tra nsitions. the internal high voltage generator is reset when the wp pin is active low. r/b ready/busy output the r/b output indicates the status of the device operation. when low, it indicates that a program, erase or random read operation is in process and returns to hi gh state upon completion. it is an open drain output and does not float to high-z condition when the ch ip is deselected or when outputs are disabled. vcc q output buffer power vcc q is the power supply for output buffer. vcc q is internally connected to vcc, thus should be biased to vcc. vcc power v cc is the power supply for device. vss ground n.c no connection lead is not internally connected. dnu do not use leave it disconnected
flash memory 8 k9f5608b0d k9f5608r0d k9f5608u0d 512byte 16 byte figure 1-1. k9f5608x0d functional block diagram figure 2-1. k9f5608x0d array organization note : column address : starting address of the register. 00h command(read) : defines the starting address of the 1st half of the register. 01h command(read) : defines the starting address of the 2nd half of the register. * a 8 is set to "low" or "high" by the 00h or 01h command. * the device ignores any additional in put of address cycles than required. i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 1st cycle a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 2nd cycle a 9 a 10 a 11 a 12 a 13 a 14 a 15 a 16 3rd cycle a 17 a 18 a 19 a 20 a 21 a 22 a 23 a 24 v cc x-buffers 256m + 8m bit command nand flash array (512 + 16)byte x 65536 y-gating page register & s/a i/o buffers & latches latches & decoders y-buffers latches & decoders register control logic & high voltage generator global buffers output driver v ss a 9 - a 24 a 0 - a 7 command ce re we wp i/0 0 i/0 7 v cc/ v ccq v ss a 8 1st half page register (=256 bytes) 2nd half page register (=256 bytes) 64k pages (=2,048 blocks) 512 byte 8 bit 16 byte 1 block =32 pages = (16k + 512) byte i/o 0 ~ i/o 7 1 page = 528 byte 1 block = 528 byte x 32 pages = (16k + 512) byte 1 device = 528bytes x 32pages x 2048 blocks = 264 mbits column address row address (page address) page register cle ale
flash memory 9 k9f5608b0d k9f5608r0d k9f5608u0d product introduction the k9f5608x0d is a 264mbit(276,824,064 bit) memory organized as 65,536 rows(pages) by 528 columns. spare eight columns are located from column address of 512~527. a 528-byte data register is connected to memory cell arrays accommodating data transfe r between the i/o buffers and memory during page read and page program operations.the memory array is made up of 16 cells that are serially connected to form a nand structure. each of the 16 cells resides in a different page. a block consists of two nan d struc- tured strings. a nand structure consists of 16 cells. total 135168 nand cells reside in a block. the array organization is show n in figure 2-1. the program and read operations are executed on a p age basis, while the erase operati on is executed on a block basi s. the memory array consists of 2048 separately erasable 16k-byte blocks. it indicates that the bi t by bit erase operation is pro hibited on the k9f5608x0d. the k9f5608x0d has addresses multiplexed into 8 i/os. this schem e dramatically reduces pin coun ts while providing high perfor- mance and allows systems upgrades to future densities by mainta ining consistency in system boar d design. command, address and data are all written through i/o s by bringing we to low while ce is low. data is latched on the rising edge of we . command latch enable(cle) and address latch enable(ale) are used to multiple x command and address respectively , via the i/o pins. some com- mands require one bus cycle. for example, reset command, read co mmand, status read command, etc require just one cycle bus. some other commands like page program and copy-back program and block erase, require two cycles: one cycle for setup and the other cycle for execution. the 32m-byte physical space requires 24 addresses, thereby requiring th ree cycles for word-level add ress- ing: column address, low row address and high row address, in that order. page read and page program need the same three address cycles following the r equired command input. in block erase operation, how ever, only the two row address cycles are use d. device operations are selected by writing specific commands into the command register . table 1 defines the specific commands of the k9f5608x0d. the device includes one block siz ed otp(one time programmable), which can be used to increase system security or to provide identification capabilities. detailed informat ion can be obtained by contact with samsung. table 1. command sets caution : any undefined command inputs are prohibited except for above command set of table 1. function 1st. cycle 2nd. cycle acceptable command during busy read 1 00h/01h - read 2 50h - read id 90h - reset ffh - o page program 80h 10h copy-back program 00h 8ah block erase 60h d0h read status 70h - o
flash memory 10 k9f5608b0d k9f5608r0d k9f5608u0d recommended operating conditions (voltage reference to gnd, k9f5608x0d-xcb0 : t a =0 to 70 c, k9f5608x0d-xib0 : t a =-40 to 85 c) parameter symbol k9f5608r0d(1.8v) k9f5608b0d(2.7v) k9f5608u0d(3.3v) unit min typ. max min typ. max min typ. max supply voltage v cc 1.65 1.8 1.95 2.5 2.7 2.9 2.7 3.3 3.6 v supply voltage v ccq 1.65 1.8 1.95 2.5 2.7 2.9 2.7 3.3 3.6 v supply voltage v ss 0000 00000 v absolute maximum ratings note : 1. minimum dc voltage is -0.6v on input/output pins. during tran sitions, this level may undershoo t to -2.0v for periods <30ns. maximum dc voltage on input/output pins is v cc, +0.3v which, during transitions, may overshoot to v cc +2.0v for periods <20ns. 2. permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rati ng conditions for extended peri ods may affect reliability. parameter symbol rating unit voltage on any pin relative to v ss v in/out -0.6 to + 4.6 v v cc -0.6 to + 4.6 v ccq -0.6 to + 4.6 temperature under bias k9f5608x0d-xcb0 t bias -10 to +125 c k9f5608x0d-xib0 -40 to +125 storage temperature k9f5608x0d-xcb0 t stg -65 to +150 c k9f5608x0d-xib0 short circuit current ios 5 ma
flash memory 11 k9f5608b0d k9f5608r0d k9f5608u0d dc and operating characteristics (recommended operating conditions otherwise noted.) note : v il can undershoot to -0.4v and v ih can overshoot to v cc +0.4v for durations of 20 ns or less. parameter symbol test conditions k9f5608x0d unit 1.8v 2.7v 3.3v min typ max min typ max min typ max operat- ing current sequential read i cc 1 trc=50ns, ce =v il i out =0ma - 8 20 - 10 20 - 10 20 ma program i cc 2 - - 8 20 - 10 20 - 10 25 erase i cc 3 - - 8 20 - 10 20 - 10 25 stand-by current(ttl) i sb 1ce =v ih , wp =0v/v cc --1-- 1--1 stand-by cur- rent(cmos) i sb 2ce =v cc -0.2, wp =0v/v cc - 10 50 - 10 50 - 10 50 a input leakage current i li v in =0 to vcc(max) - - 10 - - 10 - - 10 output leakage current i lo v out =0 to vcc(max) - - 10 - - 10 - - 10 input high voltage v ih* i/o pins vcc q -0.4 - v ccq +0.3 v ccq -0.4 - v ccq +0.3 2.0 - v ccq +0.3 v except i/o pins v cc -0.4 - v cc +0.3 v cc -0.4 - v cc +0.3 2.0 - v cc +0.3 input low voltage, all inputs v il* - -0.3 - 0.4 -0.3 - 0.5 -0.3 - 0.8 output high voltage level v oh k9f5608r0d :i oh =-100 a k9f5608b0d :i oh =-100 a k9f5608u0d :i oh =-400 a v ccq -0.1 -- v ccq -0.4 --2.4-- output low voltage level v ol k9f5608r0d :i ol =100ua k9f5608b0d :i ol =100 a k9f5608u0d :i ol =2.1ma - - 0.1 - - 0.4 - - 0.4 output low current(r/b )i ol (r/b ) k9f5608r0d :v ol =0.1v k9f5608b0d :v ol =0.1v k9f5608u0d :v ol =0.4v 34 - 34 - 810-ma
flash memory 12 k9f5608b0d k9f5608r0d k9f5608u0d capacitance ( t a =25 c, v cc =1.8v/2.7v/3.3v, f=1.0mhz) note : capacitance is periodically sampled and not 100% tested. item symbol test condition min max unit input/output capacitance c i/o v il =0v - 10 pf input capacitance c in v in =0v - 10 pf valid block note : 1. the device may include invalid blocks when first shipped. additional inva lid blocks may develop while being used. the number of valid blo cks is pre- sented with both cases of invalid blocks c onsidered. invalid blocks are defined as blocks that contain one or more bad bits . do not erase or program factory-marked bad blocks. refer to the attached technical notes for a appropriate management of invalid blocks. 2. the 1st block, which is placed on 00h block address, is guaranteed to be a valid block, does not require error correction u p to 1k program/erase cycles. 3. minimum 1004 valid blocks are guaranteed fo r each contiguous 128mb memory space. parameter symbol min typ. max unit valid block number n vb 2013 - 2048 blocks ac test condition (k9f5608x0d-xcb0 :ta=0 to 70 c, k9f5608x0d-xib0:ta=-40 to 85 c k9f5608r0d : vcc=1.65v~1.95v , k9f5608b0d : vcc=2.5v ~2.9v , k9f5608u0d : vcc=2.7v~3.6v unless otherwise noted) parameter k9f5608r0d k9f5608b0d k9f5608u0d input pulse levels 0v to vcc q 0v to vcc q 0.4v to 2.4v input rise and fall times 5ns 5ns 5ns input and output timing levels vcc q /2 vcc q /2 1.5v k9f5608r0d:output load (vcc q :1.8v +/-10%) k9f5608b0d:output load (vcc q :2.7v +/-10%) k9f5608u0d:output load (vcc q :3.0v +/-10%) 1 ttl gate and cl=30pf 1 ttl gate and cl=30pf 1 ttl gate and cl=50pf k9f5608u0d:output load (vcc q :3.3v +/-10%) - - 1 ttl gate and cl=100pf mode selection note : 1. x can be v il or v ih. 2. wp should be biased to cmos high or cmos low for standby. cle ale ce we re wp mode hl l h x read mode command input l h l h x address input(3clock) hl l h h write mode command input l h l h h address input(3clock) l l l h h data input l l l h x data output l l l h h x during read(busy) on k9f5608u0d_p,f or k9f5608b0d_p xx x x h x during read(busy) on the devices except on k9f5608u0d_p,f or k9f5608b0d_p x x x x x h during program(busy) x x x x x h during erase(busy) x x (1) x x x l write protect xx h x x 0v/vcc (2) stand-by
flash memory 13 k9f5608b0d k9f5608r0d k9f5608u0d program/erase characteristics parameter symbol min typ max unit program time t prog - 200 500 s number of partial program cycles in the same page main array nop --2cycles spare array - - 3 cycles block erase time t bers -23ms ac timing characteristics for command / address / data input note : 1. if tcs is set less than 10ns, twp must be minimum 35ns, otherwise, twp may be minimum 25ns. parameter symbol min max unit cle setup time t cls 0-ns cle hold time t clh 10 - ns ce setup time t cs 0-ns ce hold time t ch 10 - ns we pulse width t wp 25 (1) -ns ale setup time t als 0-ns ale hold time t alh 10 - ns data setup time t ds 20 - ns data hold time t dh 10 - ns write cycle time t wc 50 - ns we high hold time t wh 15 - ns address to data loading time t adl 100 - ns
flash memory 14 k9f5608b0d k9f5608r0d k9f5608u0d ac characteristics for operation note : 1. k9f5608r0d trea = 35ns. 2. if reset command(ffh) is written at ready state, the device goes into busy for maximum 5us. 3. the time to ready depends on the value of the pull-up resistor tied r/b pin. 4. to break the sequential read cycle, ce must be held high for longer time than tceh. parameter symbol min max unit data transfer from cell to register t r -15 s ale to re delay t ar 10 - ns cle to re delay t clr 10 - ns ready to re low t rr 20 - ns re pulse width t rp 25 - ns we high to busy t wb - 100 ns read cycle time t rc 50 - ns re access time t rea - 30/35 (1) ns ce access time t cea -45ns re high to output hi-z t rhz -30ns ce high to output hi-z t chz -20ns re or ce high to output hold t oh 15 - ns re high hold time t reh 15 - ns output hi-z to re low t ir 0-ns we high to re low t whr 60 - ns device resetting time (read/program/erase) t rst - 5/10/500 (2) s symbol min max uni k9f5608u0d-p,f or k9f5608b0d--p only last re high to busy(at sequential read) t rb - 100 ns ce high to ready(in case of interception by ce at read) t cry - 50 +tr(r/b ) (3) ns ce high hold time(at the last serial read) (4) t ceh 100 - ns
flash memory 15 k9f5608b0d k9f5608r0d k9f5608u0d nand flash technical notes identifying initial invalid block(s) initial invalid block(s) all device locations are erased(ffh ) except locations where the initial invalid bl ock(s) information is written prior to shippi ng. the initial invalid block(s) status is defined by the 6th byte in the spare area. samsung makes sure that either the 1st or 2nd pag e of every initial invalid block has non-ffh data at the column address of 517. since the initial invalid bl ock information is also erasa ble in most cases, it is impossible to recover the information once it has been erased. therefore, the system must be able to recognize the initial invalid block(s) based on the initial invalid block information and create the initial invalid block table via the following su ggested flow chart(figure 3). any intentional erasure of the initial invalid block information is prohibited. * check "ffh" at the column address figure 3. flow chart to create initial invalid block table. start set block address = 0 check "ffh" ? increment block address last block ? end no yes yes create (or update) no initial 517of the 1st and 2nd page in the block invalid block(s) table initial invalid blocks are defined as blocks that contain one or more initial in valid bits whose reliability is not guaranteed by samsung. the information regarding the initial invalid block(s) is so call ed as the initial invalid block information. devices with init ial invalid block(s) have the same quality leve l as devices with all valid bl ocks and have the same ac and dc characteristics. an initial i nvalid block(s) does not affect the performance of valid block(s) because it is isolated fr om the bit line and the common source line by a select transistor. the system design must be able to mask out the invalid block(s) via address mapping. the 1st block, which is placed on 00h block address, is guaranteed to be a valid block, does not require error correction up to 1k program/erase cycle s.
flash memory 16 k9f5608b0d k9f5608r0d k9f5608u0d nand flash technical notes (continued) program flow chart start i/o 6 = 1 ? i/o 0 = 0 ? no * write 80h write address write data write 10h read status register program completed or r/b = 1 ? program error yes no yes error in write or read operation within its life time, the additional inva lid blocks may develop with nand flash memory . refer to the qualification report for t he actual data.the following possible failure modes shoul d be considered to implement a highly reli able system. in the case of status rea d fail- ure after erase or program, block replacement should be done. be cause program status fail during a page program does not affec t the data of the other pages in the same block, block replac ement can be executed with a page-sized buffer by finding an erased empty block and reprogramming the current target data and copying the rest of the replaced block. in case of read, ecc must be employed. to improve the efficiency of memory space, it is recommended that the read or verification failure due to single bit error be reclaimed by ecc without any block replacement. the said additi onal block failure rate does no t include those reclaimed blocks. failure mode detection and countermeasure sequence write erase failure status read after erase --> block replacement program failure status read after program --> block replacement read single bit failure verify ecc -> ecc correction ecc : error correcting code --> hamming code etc. example) 1bit correction & 2bit detection : if program operation results in an error, map out the block including the page in error and copy the * target data to another block.
flash memory 17 k9f5608b0d k9f5608r0d k9f5608u0d erase flow chart start i/o 6 = 1 ? i/o 0 = 0 ? no * write 60h write block address write d0h read status register or r/b = 1 ? erase error yes no : if erase operation results in an error, map out the failing block and replace it with another block. * erase completed yes read flow chart start verify ecc no write 00h write address read data ecc generation reclaim the error page read completed yes nand flash technical notes (continued) block replacement * step1 when an error happens in the nth page of the bl ock ?a? during erase or program operation. * step2 copy the nth page data of the block ?a? in the buffer memory to the nth page of another free block. (block ?b?) * step3 then, copy the data in the 1st ~ (n-1)th page to the same location of the block ?b?. * step4 do not further erase block ?a? by creating an ?i nvalid block? table or other appropriate scheme. buffer memory of the controller. 1st block a block b (n-1)th nth (page) 1 2 { 1st (n-1)th nth (page) { an error occurs.
flash memory 18 k9f5608b0d k9f5608r0d k9f5608u0d samsung nand flash has three address pointer commands as a substitute for the two most significant column addresses. ?00h? command sets the pointer to ?a? area(0~255byte), ?01h? command sets the pointer to ?b? area(256~511byte), and ?50h? command set s the pointer to ?c? area(512~527byte). with these commands, t he starting column address can be set to any of a whole page(0~527byte). ?00h? or ?50h? is sustained until another address pointer command is inputted. ?01h? command, however, is effe ctive only for one operation. after any operation of read, program, eras e, reset, power_up is executed once with ?01h? command, the address pointer returns to ?a? area by itself. to program data st arting from ?a? or ?c? area, ?00h? or ?50h? command must be in putted before ?80h? command is written. a complete read operation prior to ?80h? command is not necessary. to program data starting fr om ?b? area, ?01h? command must be inputt ed right before ?80h? command is written. 00h (1) command input sequence for programming ?a? area address / data input 80h 10h 00h 80h 10h address / data input the address pointer is set to ?a? area(0~255), and sustained 01h (2) command input sequence for programming ?b? area address / data input 80h 10h 01h 80h 10h address / data input ?b?, ?c? area can be programmed. it depends on how many data are inputted. ?01h? command must be rewritten before every program operation the address pointer is set to ?b? area(256~512), and will be reset to ?a? area after every program operation is executed. 50h (3) command input sequence for programming ?c? area address / data input 80h 10h 50h 80h 10h address / data input only ?c? area can be programmed. ?50h? command can be omitted. the address pointer is set to ?c? area(512~527), and sustained ?00h? command can be omitted. it depends on how many data are inputted. ?a?,?b?,?c? area can be programmed. pointer operation of k9f5608x0d(x8) table 2. destination of the pointer command pointer position area 00h 01h 50h 0 ~ 255 byte 256 ~ 511 byte 512 ~ 527 byte 1st half array(a) 2nd half array(b) spare array(c) "a" area 256 byte (00h plane) "b" area (01h plane) "c" area (50h plane) 256 byte 16 byte "a" "b" "c" internal page register pointer select commnad (00h, 01h, 50h) pointer figure 4. block diagram of pointer operation
flash memory 19 k9f5608b0d k9f5608r0d k9f5608u0d system interface using ce don?t-care. ce we t wp t ch t cs start add.(3cycle) 80h data input ce cle ale we data input ce don?t-care 10h for an easier system interface, ce may be inactive during the data-loading or se quential data-reading as shown below. the internal 528byte page registers are utilized as seperat e buffers for this operation and the system design gets more flexible. in additio n, for voice or audio applications whic h use slow cycle time on the or der of u-seconds, de-activating ce during the data-loading and read- ing would provide si gnificant savings in power consumption. start add.(3cycle) 00h ce cle ale we data output(sequential) ce don?t-care r/b t r re t cea out t rea ce re i/o 0 ~ 7 figure 6. program operation with ce don?t-care. figure 7. read operation with ce don?t-care. on k9f5608u0d_p,f or k9f5608b0d_p i/ox i/ox ce must be held low during tr t oh
flash memory 20 k9f5608b0d k9f5608r0d k9f5608u0d ce we cle ale i/ox ao~a7 t cls t cs t wc t wp t als t ds t dh t alh t als t wh t wc t wp t ds t dh t alh t als t wh t wp t ds t dh t alh command latch cycle ce we cle ale i/ox command address latch cycle t cls t cs t clh t ch t wp t als t alh t ds t dh a17~a24 a9~a16 note : 1. i/o8~15 must be set to "0" during command or address input. i/o8~15 are used only for data bus. device i/o data i/ox data in/out k9f5608x0d(x8 device) i/o 0 ~ i/o 7 ~528byte t ch
flash memory 21 k9f5608b0d k9f5608r0d k9f5608u0d input data latch cycle ce cle we din 0 din 1 din n ale t als t clh t wc t ch t ds t dh t ds t dh t ds t dh t wp t wh t wp t wp sequential out cycle after read (cle=l, we =h, ale=l) re ce r/b dout dout dout t rc t rea t rr t oh t rea t reh t rea t oh t rhz* notes : transition is measured 200mv from steady state voltage with load. this parameter is sampled and not 100% tested. i/ox i/ox t rhz* t chz* t rp
flash memory 22 k9f5608b0d k9f5608r0d k9f5608u0d t chz t oh status read cycle ce we cle re i/ox 70h status output t clr t clh t cs t wp t ch t ds t dh t rea t ir t oh t oh t whr1 t cea t cls read1 operation (read one page) ce cle r/b we ale re busy read a0~a7 a9~a16 a17~a24 dout n dout n+1 dout n+2 dout n+3 column address page(row) address t wb t ar t r t rc t rr dout m t wc m = 528 , read cmd = 00h or 01h t rhz t ceh t rb t cry n address cmd 1) 1) notes : 1) is only valid on k9f5608u0d_p,f or k9f5608b0d_p i/ox on k9f5608u0d_p,f or k9f5608b0d_p ce must be held low during tr t rhz t chz t oh
flash memory 23 k9f5608b0d k9f5608r0d k9f5608u0d read1 operation (intercepted by ce ) ce cle r/b we ale re busy dout n dout n+1 dout n+2 dout n+3 page(row) address address column t wb t ar t chz t r t rr t rc read2 operation (read one page) ce cle r/b we ale re 50h dout dout n+m m address n+m dout n+m+1 selected row start address m n m t ar t r t wb t rr a 0 ~a 3 are valid address & a 4 ~a 7 are don t care n = 512, m = 16 n address cmd read i/ox i/ox col. add row add1 row add2 col. add row add1 row add2 on k9f5608u0d_p,f or k9f5608b0d_p ce must be held low during tr on k9f5608u0d_p,f or k9f5608b0d_p ce must be held low during tr t oh
flash memory 24 k9f5608b0d k9f5608r0d k9f5608u0d page program operation ce cle r/b we ale re 80h 70h i/o 0 din n din din 10h m n+1 sequential data input command column address page(row) address 1 up to m data serial input program command read status command i/o 0 =0 successful program i/o 0 =1 error in program t prog t wb t wc t wc t wc m = 528 byte n address sequential row read operation (only for on k9f5608u0d_p,f or k9f5608b0d_p ) ce cle r/b i/ox we ale re 00h m output dout n dout n+1 dout n+2 dout 527 dout 0 dout 1 dout 2 dout 527 m+1 output n busy busy ready i/ox col. add row add1 row add2 col. add row add1 row add2 t adl
flash memory 25 k9f5608b0d k9f5608r0d k9f5608u0d block erase operation (erase one block) ce cle r/b we ale re 60h auto block erase erase command read status command i/o 0 =1 error in erase d0h 70h i/o 0 busy t wb t bers i/o 0 =0 successful erase page(row) address t wc setup command copy-back program operation ce cle r/b we ale re 00h 70h i/o 0 8ah column address page(row) address program command read status command i/o 0 =0 successful program i/o 0 =1 error in program t prog t wb t wc a 0 ~a 7 a 17 ~a 24 a 9 ~a 16 column address page(row) address busy t wb t r busy i/ox i/ox col. add row add1 row add2 a9~a16 a17~a24
flash memory 26 k9f5608b0d k9f5608r0d k9f5608u0d manufacture & device id read operation ce cle we ale re 90h read id command maker code device code 00h t rea address. 1cycle t ar i/ox ech device device device code* k9f5608r0d 35h k9f5608b0d 75h k9f5608u0d 75h code*
flash memory 27 k9f5608b0d k9f5608r0d k9f5608u0d device operation page read upon initial device power up, the device defaults to read1 mode. this operation is also initiated by writing 00h to the command regis- ter along with three address cycles. once the command is latched, it does not need to be written for the following page read op era- tion. two types of operations are ava ilable : random read, serial page read. the random read mode is enabled when the page address is changed. t he 528 byte of data within the selected page are transferre d to the data registers in less than 15 s(t r ). the system controller can detect the comple tion of this data transfe r(tr) by analyzing the output of r/b pin. once the data in a page is loaded into the registers, they may be read out in 50ns c ycle time by sequentially pulsing re . high to low transitions of the re clock output the data starting from the selected column address up to the last column address. the way the read1 and read2 commands work is like a pointer set to either the main area or the spare area. addresses a 0~ a 3 set the starting address of the spare area while addresses a 4 ~a 7 are ignored . the read1 command is needed to move the pointer back to the main area. figures 8,9 show typi cal sequence and timings for each read operation. sequential row read is available only on k9f5608u0d_p,f or k9f5608b0d_p : after the data of last column address is clocked out, the next page is automatically selected for sequential row read. waiting 15 s again allows reading the selected page. the sequent ial row read operation is terminated by bringing ce high. unless the operation is aborted, the page address is automatically incremented for s equential row read as in read1 operation and spare sixteen bytes of each page may be sequentially read. the sequential read 1 and 2 operations are allowed only within a block and after the last page of a block being readout, the sequential read operation must be terminated by bringing ce high. when the page address moves onto the next block, read command and address must be given. figures 8-1, 9-1 show typical seq uence and timings for sequential row read operation. figure8. read1 operation start add.(3cycle) 00h a 0 ~ a 7 & a 9 ~ a 24 data output(sequential) (00h command) data field spare field ce cle ale r/b we re t r main array (01h command) data field spare field 1st half array 2st half array note: 1) after data access on 2nd half array by 01h command, the start pointer is automatically moved to 1st half array (00h) at next cycle. i/ox on k9f5608u0d_p,f or k9f5608b0d_p ce must be held low during tr 1)
flash memory 28 k9f5608b0d k9f5608r0d k9f5608u0d figure 9. read2 operation 50h data output(sequential) spare field ce cle ale r/b we start add.(3cycle) re t r main array data field spare field figure 8-1. sequential row read1 operation (only for k9f5608u0d_p,f or k9f5608b0d_p ) 00h 01h a 0 ~ a 7 & a 9 ~ a 24 i/ox r/b start add.(3cycle) data output data output data output 1st 2nd nth (528 byte) (528 byte) t r t r t r (00h command) data field spare field (01h command) data field spare field 1st half array 2nd half array 1st 2nd nth 1st half array 2nd half array 1st 2nd nth block a 4 ~ a 7 don?t care i/ox on k9f5608u0d_p,f or k9f5608b0d_p ce must be held low during tr
flash memory 29 k9f5608b0d k9f5608r0d k9f5608u0d figure 9-1. sequential row read2 operation (only for k9f5608u0d_p,f or k9f5608b0d_p ) 50h a 0 ~ a 3 & a 9 ~ a 24 i/ox r/b start add.(3cycle) data output data output data output 2nd nth (16byte) (16byte) data field spare field 1st block (a 4 ~ a 7 : don t care) 1st t r t r t r nth
flash memory 30 k9f5608b0d k9f5608r0d k9f5608u0d page program the device is programmed basically on a page basis, but it does allow multiple partia l page programing of a byte/word or consec utive bytes/words up to 528, in a single page program cycle. the num ber of consecutive partial page programming operation within the same page without an intervening erase operation should not exceed 2 for main array and 3 for spare array. the addressing may b e done in any random order in a block. a page program cycle consists of a serial data loading period in which up to 528 bytes of data may be loaded into the page register, followed by a non-volatile programming period where the loaded data is programmed into th e appropriate cell. about the pointer operation, please refer to the attached technical notes. the serial data loading period begins by inputting the serial da ta input command(80h), followed by the three cycle address inpu t and then serial data loading. the words other than those to be programmed do not need to be loaded.the page program confirm com- mand(10h) initiates the programming process. writing 10h alone wi thout previously entering the serial data will not initiate th e pro- gramming process. the internal write contro ller automatically executes the algorithms and timings necessary for program and ver ify, thereby freeing the system controller for other tasks. once the program process starts, the read status register command may be entered, with re and ce low, to read the status register. the system contro ller can detect the completion of a program cycle by mon- itoring the r/b output, or the status bit(i/o 6) of the status register. only the read status command and reset command are valid while programming is in progress. when the page program is comple te, the write status bit(i/o 0) may be checked(figure 10). the internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. the command register remains i n read status command mode until another valid command is written to the command register. figure 10. program operation 80h r/b address & data input i/o 0 pass 10h 70h fail t prog copy-back program the copy-back program is configured to qui ckly and efficiently rewrite data stored in one page within the array to another page within the same array without utilizing an external memory. since t he time-consuming sequently-reading and its re-loading cycles are removed, the system performance is improved. the benefit is es pecially obvious when a portion of a block is updated and the res t of the block also need to be copied to the new ly assigned free block. the operation for performing a copy-back is a sequential exe cution of page-read without burst-reading cycle and copying-program with the address of de stination page. a normal read operation with "00h" command with the address of the source page moves the whole 528bytes data into the internal buffer. as soon as the flash returns to ready state, copy-back programming command "8ah" may be given with three address cycles of target page followed. the data stored in the internal buffer is then programmed directly in to the memory cells of the destination page. once the copy-bac k pro- gram is finished, any additional partial page programming into th e copied pages is prohibited before erase. since the memory ar ray is internally partitioned into two different pl anes, copy-back program is allowed only within the same memory plane. thus, a14, th e plane address, of source and destination page address must be the same. "when there is a program-failure at copy-back opera- tion, error is reported by pass/fail status. but if the soure page has a bit error for charge loss, accumulated copy-back operations could also accumulate bit errors. for this reason, two bit ecc is recommended for copy-back operation." figure 11. copy-back program operation 00h r/b add.(3cycles) i/o 0 pass 8ah 70h fail t prog add.(3cycles) t r source address destination address i/ox i/ox
flash memory 31 k9f5608b0d k9f5608r0d k9f5608u0d figure 12. block erase operation block erase the erase operation is done on a block basis. block address loading is acco mplished in two cycles initiated by an erase setup c om- mand(60h). only address a 14 to a 24 is valid while a 9 to a 13 is ignored. the erase confirm co mmand(d0h) following the block address loading initiates the internal erasing proc ess. this two-step sequence of setup foll owed by execution command ensures that memo ry contents are not accidentally erased due to external noise conditions. at the rising edge of we after the erase confirm command input, the internal writ e controller handles erase and erase-verify. when the erase operation is completed, the write status bit( i/o 0) may be checked. figure 12 details the sequence. 60h block add. : a 9 ~ a 24 r/b address input(2cycle) i/o 0 pass d0h 70h fail t bers read status the device contains a status register which may be read to find out whether program or erase operation is completed, and whethe r the program or erase operation is comple ted successfully. after writing 70h command to the command register, a read cycle outpu ts the content of the status register to the i/o pins on the falling edge of ce or re , whichever occurs last. this two line control allows the system to poll the progress of each device in multiple memory connections even when r/b pins are common-wired. re or ce does not need to be toggled for updated status. refer to table 4 fo r specific status register definitions. the command register remains in status read mode until further commands are issued to i t. therefore, if the status re gister is read during a random read cycle, a read command(00h or 50h) should be given before sequential page read cycle. table4. read status register definition i/o # status definition i/o 0 program / erase "0" : successful program / erase "1" : error in program / erase i/o 1 reserved for future use "0" i/o 2 "0" i/o 3 "0" i/o 4 "0" i/o 5 "0" i/o 6 device operation "0" : busy "1" : ready i/o 7 write protect "0" : protected "1" : not protected i/ox
flash memory 32 k9f5608b0d k9f5608r0d k9f5608u0d figure 13. read id operation ce cle ale re we 90h 00h address. 1cycle maker code device code t cea t ar t rea read id the device contains a product identificati on mode, initiated by writing 90h to the command register, followed by an address inp ut of 00h. two read cycles sequentially output the manufacture c ode(ech), and the device code respectively. the command register remains in read id mode until further commands are issued to it. figure 13 shows the operation sequence. t whr1 figure 14. reset operation reset the device offers a reset feature, executed by writing ffh to the command register. when the device is in busy state during ran dom read, program or erase mode, the reset operation will abort thes e operations. the contents of memory cells being altered are no longer valid, as the data will be partially programmed or eras ed. the command register is cleared to wait for the next command, and the status register is cleared to value c0h when wp is high. refer to table 5 for device st atus after reset operation. if the device is already in reset state a new reset command will not be accepted by the command register. the r/b pin transitions to low for trst after the reset command is written. refer to figure 14 below. table5. device status after power-up after reset operation mode read 1 waiting for next command ffh r/b t rst ech device i/ox i/ox code* device device code* k9f5608r0d 35h k9f5608b0d 75h k9f5608u0d 75h
flash memory 33 k9f5608b0d k9f5608r0d k9f5608u0d ready/busy the device has a r/b output that provides a hardware method of indica ting the completion of a page program, erase and random read completion. the r/b pin is normally high but transitions to low after pr ogram or erase command is written to the command reg- ister or random read is started after address loading. it return s to high when the internal controller has finished the operati on. the pin is an open-drain driver thereby allowing two or more r/b outputs to be or-tied. because pull-up resistor value is related to tr(r/b ) and current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(fig 15). its va lue can be determined by the following guidance. v cc r/b open drain output device gnd rp figure 15. rp vs tr ,tf & rp vs ibusy ibusy busy ready vcc voh tf tr vol c l 1.8v device - v ol : 0.1v, v oh : vcc q -0.1v 3.3v device - v ol : 0.4v, v oh : 2.4v 2.7v device - v ol : 0.4v, v oh : vcc q -0.4v
flash memory 34 k9f5608b0d k9f5608r0d k9f5608u0d tr,tf [s] ibusy [a] rp(ohm) ibusy tr @ vcc = 3.3v, ta = 25 c , c l = 100pf 1k 2k 3k 4k 100n 200n 300n 3m 2m 1m 100 tf 200 300 400 3.6 3.6 3.6 3.6 2.4 1.2 0.8 0.6 rp(min, 1.8v part) = v cc (max.) - v ol (max.) i ol + i l = 1.85v 3ma + i l where i l is the sum of the input currents of all devices tied to the r/b pin. rp value guidance rp(max) is determined by maxi mum permissible limit of tr rp(min, 3.3v part) = v cc (max.) - v ol (max.) i ol + i l = 3.2v 8ma + i l tr,tf [s] ibusy [a] rp(ohm) ibusy tr @ vcc = 1.8v, ta = 25 c , c l = 30pf 1k 2k 3k 4k 100n 200n 300n 3m 2m 1m 30 tf 60 90 120 1.7 1.7 1.7 1.7 1.7 0.85 0.57 0.43 tr,tf [s] ibusy [a] rp(ohm) ibusy tr @ vcc = 2.7v, ta = 25 c , c l = 30pf 1k 2k 3k 4k 100n 200n 300n 3m 2m 1m 30 tf 60 90 120 2.3 2.3 2.3 2.3 2.3 1.1 0.75 0.55 rp(min, 2.7v part) = v cc (max.) - v ol (max.) i ol + i l = 2.5v 3ma + i l
flash memory 35 k9f5608b0d k9f5608r0d k9f5608u0d the device is designed to offer protection from any involuntary program/erase duri ng power-transitions. an internal voltage det ector disables all functions whenever vcc is below about 1.1v(1.8v device), 1.8v(2.7v device), 2v(3.3v device). wp pin provides hard- ware protection and is recommended to be kept at v il during power-up and power-down and recovery time of minimum 10 s is required before internal circuit gets ready for any command se quences as shown in figure 16. the two step command sequence for program/erase provides additional software protection. figure 16. ac waveforms for power transition v cc wp high 1.8v device : ~ 1.5v we data protection & power up sequence 3.3v device : ~ 2.5v 1.8v device : ~ 1.5v 3.3v device : ~ 2.5v 10 s 2.7v device : ~ 2.0v 2.7v device : ~ 2.0v

▲Up To Search▲

Price & Availability of K9F5608R0D-JIB00

	To Download K9F5608R0D-JIB00 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .