View K9K1208U0C-DIB00_6867739.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

flash memory 1 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c k9k1216q0c k9k1208q0c document title 64m x 8 bit , 32m x 16 bit nand flash memory revision history the attached datasheets are prepared and approved by samsung electronics. samsung electronics co., ltd. reserve the right to change the specifications. samsung electronics will evaluate and reply to your requests and questions about device. if you ha ve any questions, please contact the samsung branch office near you. revision no. 0.0 1.0 2.0 2.1 2.2 2.3 2.4 2.5 remark advance preliminary preliminary history initial issue. 1.pin assignment of tbga dummy ball is changed. (before) dnu --> (after) n.c 2. add the rp vs tr ,tf & rp vs ibusy graph for 1.8v device (page 34) 3. add the data protection vcc guidence for 1.8v device - below about 1.1v. (page 35) 4. add the specification of block lock scheme.(page 29~32) 5. pin assignment of tbga a3 ball is changed. (before) n.c --> (after) vss 1. the maximum operating current is changed. read : icc1 20ma-->30ma program : icc2 20ma-->40ma erase : icc3 20ma-->40ma the min. vcc value 1.8v devices is changed. k9k12xxq0c : vcc 1.65v~1.95v --> 1.70v~1.95v pb-free package is added. k9k1208u0c-hcb0,hib0 k9k1208q0c-hcb0,hib0 k9k1216u0c-hcb0,hib0 k9k1216q0c-hcb0,hib0 errata is added.(front page)-k9k12xxq0c twc twp trc treh trp trea tcea specification 45 25 50 15 25 30 45 relaxed value 60 40 60 20 40 40 55 1. max. thickness of tbga packge is changed. 0.09 0.10 (before) --> 1.10 0.10 (after) 2. new definition of the number of invalid blocks is added. ( minimum 1004 valid blocks are guaranteed for each contiguous 128mb memory space. ) 1. the guidence of lockpre pin usage is changed. don?t leave it n.c. not using lock mechanism & power-on auto- read, connect it vss.(before) --> not using lock mechanism & power-on auto-read, connect it vss or leave it n.c(after) 2. 2.65v device is added. 3. note is added. (vil can undershoot to -0.4v and vih can overshoot to vcc +0.4v for durations of 20 ns or less.) draft date sep. 12th 2002 jan. 3rd 2003 jan. 17th 2003 mar. 5th 2003 mar. 13rd 2003 mar. 17th 2003 apr. 4th 2003 jul. 4th 2003 note : for more detailed features and specifications including faq, please refer to samsung?s flash web site. http://www.samsung.com/products/semiconductor/flash/technicalinfo/datasheets.htm
flash memory 2 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c k9k1216q0c k9k1208q0c revision history the attached datasheets are prepared and approved by samsung electronics. samsung electronics co., ltd. reserve the right to change the specifications. samsung electronics will evaluate and reply to your requests and questions about device. if you ha ve any questions, please contact the samsung branch office near you. revision no. 2.6 remark history 1. trea value of 1.8v device is changed. k9k12xxq0c : trea 30ns --> 35ns 2. errata is deleted. draft date aug. 20th. 2003 note : for more detailed features and specifications including faq, please refer to samsung?s flash web site. http://www.samsung.com/products/semiconductor/flash/technicalinfo/datasheets.htm document title 64m x 8 bit , 32m x 16 bit nand flash memory
flash memory 3 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c k9k1216q0c k9k1208q0c general description features voltage supply - 1.8v device(k9k12xxq0c) : 1.70~1.95v - 2.65v device(k9f12xxd0c) : 2.4~2.9v - 3.3v device(k9k12xxu0c) : 2.7 ~ 3.6 v organization - memory cell array - x8 device(k9k1208x0c) : (64m + 2048k)bit x 8 bit - x16 device(k9k1216x0c) : (32m + 1024 k)bit x 16bit - data register - x8 device(k9k1208x0c) : (512 + 16)bit x 8bit - x16 device(k9k1216x0c) : (256 + 8)bit x16bit automatic program and erase - page program - x8 device(k9k1208x0c) : (512 + 16)byte - x16 device(k9k1216x0c) : (256 + 8)word - block erase : - x8 device(k9k1208x0c) : (16k + 512)byte - x16 device(k9k1216x0c) : ( 8k + 256)word page read operation - page size - x8 device(k9k1208x0c) : (512 + 16)byte - x16 device(k9k1216x0c) : (256 + 8)word - random access : 10 m s(max.) - serial page access : 50ns(min.) 64m x 8 bit / 32m x 16 bit nand flash memory fast write cycle time - program time : 200 m s(typ.) - block erase time : 2ms(typ.) command/address/data multiplexed i/o port hardware data protection - program/erase lockout during power transitions reliable cmos floating-gate technology - endurance : 100k program/erase cycles - data retention : 10 years command register operation intelligent copy-back unique id for copyright protection package - k9k12xxx0c-dcb0/dib0 63- ball tbga ( 9 x 11 /0.8mm pitch , width 1.2 mm) - k9k12xxx0c-hcb0/hib0 63- ball tbga ( 9 x 11 /0.8mm pitch , width 1.2 mm) - pb-free package offered in 64mx8bit or 32mx16bit, the k9k12xxx0c is 512m bit with spare 16m bit capacity. the device is offered in 1.8v, 2.65v, 3.3v vcc. its nand cell provides the most cost-effective solution for the solid state mass storage market. a program operation can be performed in typical 200 m s on the 528-byte(x8 device) or 264-word(x16 device) page and an erase operation can be performed in typical 2ms on a 16k-byte(x8 device) or 8k-word(x16 device) block. data in the page can be read out at 50ns cycle time per b yte (x8 device) or word(x16 device). the i/o pins serve as the ports for address and data input/output as well as command input. t he on-chip write control automates all program and erase functions including pulse repetition, where required, and internal verific ation and margining of data. even the write-intensive systems can take advantage of the k9k12xxx0c s extended reliability of 100k pro- gram/erase cycles by providing ecc(error correcting code) with real time mapping-out algorithm. the k9k12xxx0c is an optimum solution for large nonvolatile storage applications such as solid state file storage and other port able applications requiring non-volatility. product list. part number vcc range organization pkg type k9k1208q0c-d,h 1.70 ~ 1.95v x8 tbga k9k1216q0c-d,h x16 k9k1208d0c-d,h 2.4 ~ 2.9v x8 k9k1216d0c-d,h x16 k9k1208u0c-d,h 2.7 ~ 3.6v x8 k9k1216u0c-d,h x16
flash memory 4 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c k9k1216q0c k9k1208q0c k9k12xxx0c-dcb0,hcb0/dib0,hib0 x16 x8 pin configuration (tbga) 63-ball tbga (measured in millimeters) package dimensions 9.00 0.10 #a1 side view top view 1 . 1 0 0 . 1 0 0.45 0.05 4 3 2 1 a b c d g bottom view 1 1 . 0 0 0 . 1 0 63- ? 0.45 0.05 0 . 8 0 x 7 = 5 . 6 0 1 1 . 0 0 0 . 1 0 0.80 x5= 4.00 0.80 0 . 3 2 0 . 0 5 0.08max b a 2 . 8 0 2.00 9.00 0.10 (datum b) (datum a) 0.20 m a b ? 0 . 8 0 0 . 8 0 x 1 1 = 8 . 8 0 0.80 x9= 7.20 6 5 9.00 0.10 e f h (top view) (top view) r/b /we /ce vss ale /wp /re cle nc nc nc nc vcc nc nc i/o0 i/o1 nc nc vccq i/o5 i/o7 vss i/o6 i/o4 i/o3 i/o2 vss nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc lockpre nc nc n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c r/b /we /ce vss ale /wp /re cle i/o7 i/o5 i/o12 io14 vcc i/o10 i/o8 i/o1 i/o9 i/o0 i/o3 vccq i/o6 i/o15 vss i/o13 i/o4 i/o11 i/o2 vss nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc lockpre nc nc 3 4 5 6 1 2 a b c d g e f h 3 4 5 6 1 2 a b c d g e f h
flash memory 5 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c k9k1216q0c k9k1208q0c pin description note : connect all v cc and v ss pins of each device to common power supply outputs. do not leave v cc or v ss disconnected. pin name pin function i/o 0 ~ i/o 7 (k9k1208x0c) i/o 0 ~ i/o 15 (k9k1216x0c) data inputs/outputs the i/o pins are used to input command, address and data, and to output data during read operations. the i/o pins float to high-z when the chip is deselected or when the outputs are disabled. i/o8 ~ i/o15 are used only in x16 organization device. since command input and address input are x8 oper- ation, i/o8 ~ i/o15 are not used to input command & address. i/o8 ~ i/o15 are used only for data input and output. cle command latch enable the cle input controls the activating path for commands sent to the command register. when active high, commands are latched into the command register through the i/o ports on the rising edge of the we signal. ale address latch enable the ale input controls the activating path for address to the internal address registers. addresses are latched on the rising edge of we with ale high. ce chip enable the ce input is the device selection control. when the device is in the busy state, ce high is ignored, and the device does not return to standby mode in program or erase operation. regarding ce control during read operation, refer to ?page read? section of device operation . re read enable the re input is the serial data-out control, and when active drives the data onto the i/o bus. data is valid trea after the falling edge of re which also increments the internal column address counter by one. we write enable the we input controls writes to the i/o port. commands, address and data are latched on the rising edge of the we pulse. wp write protect the wp pin provides inadvertent write/erase protection during power tra nsitions. the internal high voltage generator is reset when the wp pin is active low. when lockpre is a logic high and wp is a logic low, the all blocks go to lock state. r/ b ready/busy output the r/ b output indicates the status of the device operation. when low, it indicates that a program, erase or random read operation is in process and returns to high state upon completion. it is an open drain output and does not float to high-z condition when the chip is deselected or when outputs are disabled. vcc q output buffer power vcc q is the power supply for output buffer. vcc q is internally connected to vcc, thus should be biased to vcc. vcc power v cc is the power supply for device. vss ground n.c no connection lead is not internally connected. dnu do not use leave it disconnected lockpre lock mechanism & power-on auto-read enable to enable and disable the lock mechanism and power on auto read. when lockpre is a logic high, block lock mode and power-on auto-read mode are enabled, and when lockpre is a logic low, block lock mode and power-on auto-read mode are disabled. power-on auto-read mode is available only on 3.3v device(k9k12xxu0c) not using lock mechanism & power-on auto-read, connect it vss or leave it n.c
flash memory 6 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c k9k1216q0c k9k1208q0c 512byte 16 byte figure 1-1. k9k1208x0c (x8) functional block diagram figure 2-1. k9k1208x0c (x8) array organization v cc x-buffers 512m + 16m bit command nand flash array (512 + 16)byte x 131072 y-gating page register & s/a i/o buffers & latches latches & decoders y-buffers latches & decoders register control logic & high voltage generator global buffers output driver v ss a 9 - a 25 a 0 - a 7 command ce re we wp i/0 0 i/0 7 v cc/ v ccq v ss a 8 1st half page register (=256 bytes) 2nd half page register (=256 bytes) 128k pages (=4,096 blocks) 512 byte 8 bit 16 byte 1 block =32 pages = (16k + 512) byte i/o 0 ~ i/o 7 1 page = 528 byte 1 block = 528 byte x 32 pages = (16k + 512) byte 1 device = 528bytes x 32pages x 4,096 blocks = 528 mbits page register cle ale column address row address (page address) note : column address : starting address of the register. 00h command(read) : defines the starting address of the 1st half of the register. 01h command(read) : defines the starting address of the 2nd half of the register. * a 8 is set to "low" or "high" by the 00h or 01h command. * l must be set to "low". * the device ignores any additional input of address cycles than reguired. i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 1st cycle a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 2nd cycle a 9 a 10 a 11 a 12 a 13 a 14 a 15 a 16 3rd cycle a 17 a 18 a 19 a 20 a 21 a 22 a 23 a 24 4th cycle a 25 *l *l *l *l *l *l *l
flash memory 7 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c k9k1216q0c k9k1208q0c 256word 8 word figure 2-2. k9k1216x0c (x16) array organization page register (=256 words) 64k pages (=2,048 blocks) 256 word 16 bit 8 word 1 block =32 pages = (8k + 256) word i/o 0 ~ i/o 15 1 page = 264 word 1 block = 264 word x 32 pages = (8k + 256) word 1 device = 264words x 32pages x 4096 blocks = 528 mbits page register figure 1-2. k9k1216x0c (x16) functional block diagram v cc x-buffers 512m + 16m bit command nand flash array (256 + 8)word x 131072 y-gating page register & s/a i/o buffers & latches latches & decoders y-buffers latches & decoders register control logic & high voltage generator global buffers output driver v ss a 9 - a 25 a 0 - a 7 command ce re we wp i/0 0 i/0 15 v cc/ v ccq v ss cle ale note : column address : starting address of the register. * l must be set to "low". * the device ignores any additional input of address cycles than reguired. i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o8 to 15 1st cycle a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 l* 2nd cycle a 9 a 10 a 11 a 12 a 13 a 14 a 15 a 16 l* 3rd cycle a 17 a 18 a 19 a 20 a 21 a 22 a 23 a 24 l* 4th cycle a 25 l* l* l* l* l* l* l* l* column address row address (page address)
flash memory 8 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c k9k1216q0c k9k1208q0c product introduction the k9k12xxx0c is a 528mbit(553,648,218 bit) memory organized as 131,072 rows(pages) by 528(x8 device) or 264(x16 device) columns. spare eight columns are located from column address of 512~527(x8 device) or 256~263(x16 device). a 528-byte(x8 device) or 264-word(x16 device) data register is connected to memory cell arrays accommodating data transfer between the i/o buf f- ers and memory during page read and page program operations. the memory array is made up of 16 cells that are serially con- nected to form a nand structure. each of the 16 cells resides in a different page. a block consists of two nand structured stri ngs. a nand structure consists of 16 cells. total 135168 nand cells reside in a block. the array organization is shown in figure 2-1,2- 2. the program and read operations are executed on a page basis, while the erase operation is executed on a block basis. the memory array consists of 4096 separately erasable 16k-byte(x8 device) or 8k-word(x16 device) blocks. it indicates that the bit by bit erase operation is prohibited on the k9k12xxx0c. the k9k12xxx0c has addresses multiplexed into 8 i/os(x16 device case : lower 8 i/os). k9k1216x0c allows sixteen bit wide data transport into and out of page registers. this scheme dramatically reduces pin counts while providing high performance and allow s systems upgrades to future densities by maintaining consistency in system board design. command, address and data are all writte n through i/o s by bringing we to low while ce is low. data is latched on the rising edge of we . command latch enable(cle) and address latch enable(ale) are used to multiplex command and address respectively, via the i/o pins. some commands require one bus cycle. for example, reset command, read command, status read command, etc require just one cycle bus. some other com- mands like page program and copy-back program and block erase, require three cycles: one cycle for setup and the other cycle for execution. the 32m-byte(x8 device) or 16m-word(x16 device) physical space requires 25 addresses(x8 device) or 24 addresses(x16 device), thereby requiring four cycles for word-level addressing: column address, low row address and high row address, in that order. page read and page program need the same four address cycles following the required command input. in block erase operation, however, only the three row address cycles are used. device operations are selected by writing specific c om- mands into the command register. table 1 defines the specific commands of the k9k12xxx0c. the device includes one block sized otp(one time programmable), which can be used to increase system security or to provide identification capabilities. detailed information can be obtained by contact with samsung. table 1. command sets note : 1. the 01h command is available only on x8 device(k9k1208x0c). caution : any undefined command inputs are prohibited except for above command set of table 1. function 1st. cycle 2nd. cycle acceptable command during busy read 1 00h/01h (1) - read 2 50h - read id 90h - reset ffh - o page program 80h 10h copy-back program 00h 8ah block erase 60h d0h read status 70h - o
flash memory 9 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c k9k1216q0c k9k1208q0c recommended operating conditions (voltage reference to gnd, k9k12xxx0c-dcb0,hcb0 : t a =0 to 70 c, k9k12xxx0c-dib0,hib0 : t a =-40 to 85 c) parameter symbol k9k12xxq0c(1.8v) k9k12xxd0c(2.65v) k9k12xxu0c(3.3v) unit min typ. max min typ. max min typ. max supply voltage v cc 1.70 1.8 1.95 2.4 2.65 2.9 2.7 3.3 3.6 v supply voltage v ccq 1.70 1.8 1.95 2.4 2.65 2.9 2.7 3.3 3.6 v supply voltage v ss 0 0 0 0 0 0 0 0 0 v absolute maximum ratings note : 1. minimum dc voltage is -0.6v on input/output pins. during transitions, this level may undershoot to -2.0v for periods <30ns. maximum dc voltage on input/output pins is v cc, +0.3v which, during transitions, may overshoot to v cc +2.0v for periods <20ns. 2. permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended perio ds may affect reliability. parameter symbol rating unit 1.8v device 3.3v/2.65v device voltage on any pin relative to v ss v in/out -0.6 to + 2.45 -0.6 to + 4.6 v v cc -0.2 to + 2.45 -0.6 to + 4.6 v ccq -0.2 to + 2.45 -0.6 to + 4.6 temperature under bias k9k12xxx0c-dcb0,hcb0 t bias -10 to +125 c k9k12xxx0c-dib0,hib0 -40 to +125 storage temperature k9k12xxx0c-dcb0,hcb0 t stg -65 to +150 c k9k12xxx0c-dib0,hib0 short circuit current ios 5 ma
flash memory 10 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c k9k1216q0c k9k1208q0c dc and operating characteristics (recommended operating conditions otherwise noted.) note : v il can undershoot to -0.4v and v ih can overshoot to v cc +0.4v for durations of 20 ns or less. parameter symbol test conditions k9k12xxx0c unit 1.8v 2.65v 3.3v min typ max min typ max min typ max operat- ing current sequential read i cc 1 trc=50ns, ce =v il i out =0ma - 10 20 - 10 20 - 10 30 ma program i cc 2 - - 10 20 - 10 20 - 10 40 erase i cc 3 - - 10 20 - 10 20 - 10 40 stand-by current(ttl) i sb 1 ce =v ih , wp =0v/v cc - - 1 - - 1 - - 1 stand-by current(cmos) i sb 2 ce =v cc -0.2, wp =0v/v cc - 10 50 - 10 50 - 10 50 m a input leakage current i li v in =0 to vcc(max) - - 10 - - 10 - - 10 output leakage current i lo v out =0 to vcc(max) - - 10 - - 10 - - 10 input high voltage v ih* i/o pins v ccq -0.4 - v ccq +0.3 v ccq -0.4 - v ccq +0.3 2.0 - v ccq +0.3 v except i/o pins v cc -0.4 - vcc +0.3 v cc -0.4 - v cc +0.3 2.0 - v cc +0.3 input low voltage, all inputs v il* - -0.3 - 0.4 -0.3 - 0.5 -0.3 - 0.8 output high voltage level v oh k9k12xxq0c :i oh =-100 m a k9k12xxd0c :i oh =-100 m a k9k12xxu0c :i oh =-400 m a v ccq -0.1 - - v ccq -0.4 - - 2.4 - - output low voltage level v ol k9k12xxq0c :i ol =100ua k9k12xxd0c :i ol =100 m a k9k12xxu0c :i ol =2.1ma - - 0.1 - - 0.4 - - 0.4 output low current(r/ b ) i ol (r/ b ) k9k12xxq0c :v ol =0.1v k9k12xxd0c :v ol =0.1v k9k12xxu0c :v ol =0.4v 3 4 - 3 4 - 8 10 - ma
flash memory 11 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c k9k1216q0c k9k1208q0c capacitance ( t a =25 c, v cc =1.8v/2.65v/3.3v, f=1.0mhz) note : capacitance is periodically sampled and not 100% tested. item symbol test condition min max unit input/output capacitance c i/o v il =0v - 20 pf input capacitance c in v in =0v - 20 pf valid block note : 1. the device may include invalid blocks when first shipped. additional invalid blocks may develop while being used. the number of valid bloc ks is pre- sented with both cases of invalid blocks considered. invalid blocks are defined as blocks that contain one or more bad bits . do not erase or program factory-marked bad blocks . refer to the attached technical notes for a appropriate management of invalid blocks. 2. the 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block, does not require error correct ion. 3. minimum 1004 valid blocks are guaranteed for each contiguous 128mb memory space. parameter symbol min typ. max unit valid block number n vb 4026 - 4096 blocks ac test condition (k9k12xxx0c-dcb0,hcb0 :ta=0 to 70 c, k9k12xxx0c-dib0,hcb0 :ta=-40 to 85 c k9k12xxq0c : vcc=1.70v~1.95v , k9k12xxd0c : vcc=2.4v~2.9v , k9k12xxu0c : vcc=2.7v~3.6v unless otherwise noted) parameter k9k12xxq0c k9k12xxd0c k9k12xxu0c input pulse levels 0v to vcc q 0v to vcc q 0.4v to 2.4v input rise and fall times 5ns 5ns 5ns input and output timing levels vcc q /2 vcc q /2 1.5v k9k12xxq0c:output load (vcc q :1.8v +/-10%) k9k12xxd0c:output load (vcc q :2.65v +/-10%) k9k12xxu0c:output load (vcc q :3.0v +/-10%) 1 ttl gate and cl=30pf 1 ttl gate and cl=30pf 1 ttl gate and cl=50pf k9k12xxu0c:output load (vcc q :3.3v +/-10%) - - 1 ttl gate and cl=100pf mode selection note : 1. x can be v il or v ih. 2. wp should be biased to cmos high or cmos low for standby. cle ale ce we re pre wp mode h l l h x x read mode command input l h l h x x address input(4clock) h l l h x h write mode command input l h l h x h address input(4clock) l l l h x h data input l l l h x x data output l l l h h x x during read(busy) on the devices x x x x x x h during program(busy) x x x x x x h during erase(busy) x x (1) x x x x l write protect x x h x x 0v/v cc (2 0v/v cc (2) stand-by
flash memory 12 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c k9k1216q0c k9k1208q0c ac characteristics for operation parameter symbol min max unit data transfer from cell to register t r - 10 m s ale to re delay t ar 10 - ns cle to re delay t clr 10 - ns ready to re low t rr 20 - ns re pulse width t rp 25 - ns we high to busy t wb - 100 ns read cycle time t rc 50 - ns ce access time t cea - 45 ns k9k12xxq0c re access time t rea - 35 ns k9k12xxu0c 30 re high to output hi-z t rhz - 30 ns ce high to output hi-z t chz - 20 ns re or ce high to output hold t oh 15 - re high hold time t reh 15 - ns output hi-z to re low t ir 0 - ns we high to re low t whr1 60 - ns we high to re low in block lcok mode t whr2 100 - ns device resetting time (read/program/erase) t rst - 5/10/500 (1) m s ac timing characteristics for command / address / data input note : 1. if tcs is set less than 10ns, twp must be minimum 35ns, otherwise, twp may be minimum 25ns. parameter symbol min max unit cle set-up time t cls 0 - ns cle hold time t clh 10 - ns ce setup time t cs 0 .- ns ce hold time t ch 10 - ns we pulse width t wp 25 (1) - ns ale setup time t als 0 - ns ale hold time t alh 10 - ns data setup time t ds 20 - ns data hold time t dh 10 - ns write cycle time t wc 45 - ns we high hold time t wh 15 - ns program/erase characteristics parameter symbol min typ max unit program time t prog - 200 500 m s dummy busy time for the lock or lock-tight block t lbsy - 5 10 m s number of partial program cycles in the same page main array nop - - 2 cycles spare array - - 3 cycles block erase time t bers - 2 3 ms
flash memory 13 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c k9k1216q0c k9k1208q0c nand flash technical notes identifying invalid block(s) invalid block(s) invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by samsung. the i nfor- mation regarding the invalid block(s) is so called as the invalid block information. devices with invalid block(s) have the same quality level as devices with all valid blocks and have the same ac and dc characteristics. an invalid block(s) does not affect the perf or- mance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. the system d esign must be able to mask out the invalid block(s) via address mapping. the 1st block, which is placed on 00h block address, is fully guar- anteed to be a valid block, does not require error correction. all device locations are erased(ffh) except locations where the invalid block(s) information is written prior to shipping. the i nvalid block(s) status is defined by the 6th byte(x8 device) or 1st word(x16 device) in the spare area. samsung makes sure that either the 1st or 2nd page of every invalid block has non-ffh(x8 device) or non-ffffh(x16 device) data at the column address of 517(x8 device) or 256 and 261(x16 device). since the invalid block information is also erasable in most cases, it is impossible to rec over the information once it has been erased. therefore, the system must be able to recognize the invalid block(s) based on the original invalid block information and create the invalid block table via the following suggested flow chart(figure 3). any intentional e rasure of the original invalid block information is prohibited. * check "ffh" at the column address figure 3. flow chart to create invalid block table. start set block address = 0 check "ffh" ? increment block address last block ? end no yes yes create (or update) no invalid block(s) table of the 1st and 2nd page in the block 517(x8 device) or 256 and 261(x16 device)
flash memory 14 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c k9k1216q0c k9k1208q0c nand flash technical notes (continued) program flow chart start i/o 6 = 1 ? write 00h i/o 0 = 0 ? no * if ecc is used, this verification write 80h write address write data write 10h read status register write address wait for tr time verify data no program completed or r/b = 1 ? program error yes no yes * program error yes : if program operation results in an error, map out the block including the page in error and copy the target data to another block. * operation is not needed. error in write or read operation within its life time, the additional invalid blocks may develop with nand flash memory. refer to the qualification report for th e actual data.the following possible failure modes should be considered to implement a highly reliable system. in the case of status read fail- ure after erase or program, block replacement should be done. because program status fail during a page program does not affect the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased empty block and reprogramming the current target data and copying the rest of the replaced block. to improve the efficiency of mem- ory space, it is recommended that the read or verification failure due to single bit error be reclaimed by ecc without any block replacement. the said additional block failure rate does not include those reclaimed blocks. failure mode detection and countermeasure sequence write erase failure status read after erase --> block replacement program failure status read after program --> block replacement read back ( verify after program) --> block replacement or ecc correction read single bit failure verify ecc -> ecc correction ecc : error correcting code --> hamming code etc. example) 1bit correction & 2bit detection
flash memory 15 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c k9k1216q0c k9k1208q0c erase flow chart start i/o 6 = 1 ? i/o 0 = 0 ? no * write 60h write block address write d0h read status register or r/b = 1 ? erase error yes no : if erase operation results in an error, map out the failing block and replace it with another block. * erase completed yes read flow chart start verify ecc no write 00h write address read data ecc generation reclaim the error page read completed yes nand flash technical notes (continued) block replacement * step1 when an error happens in the nth page of the block ?a? during erase or program operation. * step2 copy the nth page data of the block ?a? in the buffer memory to the nth page of another free block. (block ?b?) * step3 then, copy the data in the 1st ~ (n-1)th page to the same location of the block ?b?. * step4 do not further erase block ?a? by creating an ?invalid block? table or other appropriate scheme. buffer memory of the controller. 1st block a block b (n-1)th nth (page) 1 2 { ~ 1st (n-1)th nth (page) { ~ an error occurs.
flash memory 16 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c k9k1216q0c k9k1208q0c 00h (1) command input sequence for programming ?a? area address / data input 80h 10h 00h 80h 10h address / data input the address pointer is set to ?a? area(0~255), and sustained 01h (2) command input sequence for programming ?b? area address / data input 80h 10h 01h 80h 10h address / data input ?b?, ?c? area can be programmed. it depends on how many data are inputted. ?01h? command must be rewritten before every program operation the address pointer is set to ?b? area(256~51 1 ), and will be reset to ?a? area after every program operation is executed. 50h (3) command input sequence for programming ?c? area address / data input 80h 10h 50h 80h 10h address / data input only ?c? area can be programmed. ?50h? command can be omitted. the address pointer is set to ?c? area(512~527), and sustained ?00h? command can be omitted. it depends on how many data are inputted. ?a?,?b?,?c? area can be programmed. pointer operation of k9k1208x0c(x8) table 2. destination of the pointer command pointer position area 00h 01h 50h 0 ~ 255 byte 256 ~ 511 byte 512 ~ 527 byte 1st half array(a) 2nd half array(b) spare array(c) "a" area 256 byte (00h plane) "b" area (01h plane) "c" area (50h plane) 256 byte 16 byte "a" "b" "c" internal page register pointer select commnad (00h, 01h, 50h) pointer figure 4. block diagram of pointer operation samsung nand flash has three address pointer commands as a substitute for the two most significant column addresses. ?00h? command sets the pointer to ?a? area(0~255byte), ?01h? command sets the pointer to ?b? area(256~511byte), and ?50h? command sets the pointer to ?c? area(512~527byte). with these commands, the starting column address can be set to any of a whole page(0~527byte). ?00h? or ?50h? is sustained until another address pointer command is inputted. ?01h? command, however, is effec tive only for one operation. after any operation of read, program, erase, reset, power_up is executed once with ?01h? command, the address pointer returns to ?a? area by itself. to program data starting from ?a? or ?c? area, ?00h? or ?50h? command must be inp utted before ?80h? command is written. a complete read operation prior to ?80h? command is not necessary. to program data starting fro m ?b? area, ?01h? command must be inputted right before ?80h? command is written.
flash memory 17 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c k9k1216q0c k9k1208q0c samsung nand flash has two address pointer commands as a substitute for the most significant column address. ?00h? command sets the pointer to ?a? area(0~255word), and ?50h? command sets the pointer to ?b? area(256~263word). with these commands, the starting column address can be set to any of a whole page(0~263word). ?00h? or ?50h? is sustained until another address pointer com- mand is inputted. to program data starting from ?a? or ?b? area, ?00h? or ?50h? command must be inputted before ?80h? command is written. a complete read operation prior to ?80h? command is not necessary. 00h (1) command input sequence for programming ?a? area address / data input 80h 10h 00h 80h 10h address / data input the address pointer is set to ?a? area(0~255), and sustained 50h (2) command input sequence for programming ?b? area address / data input 80h 10h 50h 80h 10h address / data input only ?b? area can be programmed. ?50h? command can be omitted. the address pointer is set to ?b? area(256~263), and sustained ?00h? command can be omitted. it depends on how many data are inputted. ?a?,?b? area can be programmed. pointer operation of k9k1216x0c(x16) table 3. destination of the pointer command pointer position area 00h 50h 0 ~ 255 word 256 ~ 263 word main array(a) spare array(b) "a" area 256 word (00h plane) "b" area (50h plane) 8 word "a" "b" internal page register pointer select command (00h, 50h) pointer figure 5. block diagram of pointer operation
flash memory 18 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c k9k1216q0c k9k1208q0c system interface using ce don?t-care. ce we t wp t ch t cs start add.( 4 cycle) 80h data input ce cle ale we data input ce don?t-care ? ? 10h for an easier system interface, ce may be inactive during the data-loading or sequential data-reading as shown below. the internal 528byte(x8 device), 264word(x16 device) page registers are utilized as seperate buffers for this operation and the system design gets more flexible. in addition, for voice or audio applications which use slow cycle time on the order of u-seconds, de-activat ing ce during the data-loading and reading would provide significant savings in power consumption. start add.( 4 cycle) 00h ce cle ale we data output(sequential) ce don?t-care ? r/ b t r re figure 6. program operation with ce don?t-care. figure 7. read operation with ce don?t-care. i/ox i/ox t cea out t rea ce re i/o 0 ~ 15 t oh
flash memory 19 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c k9k1216q0c k9k1208q0c command latch cycle ce we cle ale i/ox command t cls t cs t clh t ch t wp t als t alh t ds t dh note : 1. i/o8~15 must be set to "0" during command or address input. i/o8~15 are used only for data bus. device i/o data i/ox data in/out k9k1208x0c(x8 device) i/o 0 ~ i/o 7 ~528byte k9k1216x0c(x16 device) i/o 0 ~ i/o 15 1) ~264word address latch cycle ce we cle ale i/o x a0~a7 t cls t cs t wc t wp t als t ds t dh t alh t als t wh t wc t wp t ds t dh t alh t als t wh t wc t wp t ds t dh t alh t als t wh t alh t ds t dh t wp a9~a16 a17~a24 a25 t ch
flash memory 20 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c k9k1216q0c k9k1208q0c input data latch cycle ce cle we din 0 din 1 din n ale t als t clh t wc t ch t ds t dh t ds t dh t ds t dh t wp t wh t wp t wp serial access cycle after read (cle=l, we =h, ale=l) re ce r/ b dout dout dout t rc t rea t rr t oh t rea t reh t rea t oh t rhz* ? ? ? ? ? ? ? notes : transition is measured 200mv from steady state voltage with load. this parameter is sampled and not 100% tested. i/ox i/ox t rhz* t chz* t rp
flash memory 21 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c k9k1216q0c k9k1208q0c status read cycle ce we cle re i/ox 70h status output t clr t clh t cs t wp t ch t ds t dh t rea t ir t oh t oh t whr 1 t cea t cls t rhz t chz t chz t oh read1 operation (read one page) x8 device : m = 528 , read cmd = 00h or 01h x16 device : m = 264 , read cmd = 00h 1) ce cle r/ b i/o x we ale re busy 00h or 01h a 0 ~ a 7 a 9 ~ a 16 a 17 ~ a 24 dout n dout n+1 dout n+2 column address page(row) address t wb t ar t r t rc t rhz t rr dout m t wc ? ? ? a 25 n address t oh
flash memory 22 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c k9k1216q0c k9k1208q0c read1 operation (intercepted by ce ) ce cle r/ b i/o x we ale re busy 00h or 01h a 0 ~ a 7 a 9 ~ a 16 a 17 ~ a 24 dout n dout n+1 dout n+2 page(row) address address column t wb t ar t chz t r t rr t rc a 25 t oh read2 operation (read one page) ce cle r/ b i/o x we ale re 50h a 0 ~ a 7 a 9 ~ a 16 a 17 ~ a 24 dout n+m m address n+m t ar t r t wb t rr a 0 ~a 3 : valid address a 4 ~a 7 : don t care ? ? a 25 selected row start address m 512 16
flash memory 23 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c k9k1216q0c k9k1208q0c page program operation ce cle r/ b i/o x we ale re 80h 70h i/o 0 din n din 10h 527 a 0 ~ a 7 a 17 ~ a 24 a 9 ~ a 16 sequential data input command column address page(row) address 1 up to 528 byte data serial input program command read status command i/o 0 =0 successful program i/o 0 =1 error in program t prog t wb t wc t wc t wc ? ? ? a 25 ?
flash memory 24 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c k9k1216q0c k9k1208q0c copy-back program operation ce cle r/ b i/o x we ale re 00h 70h i/o 0 8ah a 0 ~a 7 a 17 ~a 24 a 9 ~a 16 column address page(row) address read status command i/o 0 =0 successful program i/o 0 =1 error in program t prog t wb t wc ? a 0 ~a 7 a 17 ~a 24 a 9 ~a 16 column address page(row) address busy t wb t r busy ? a 25 a 25 10h copy-back data input command block erase operation (erase one block) ce cle r/ b i/o x we ale re 60h a 17 ~ a 24 a 9 ~ a 16 auto block erase setup command erase command read status command i/o 0 =1 error in erase doh 70h i/o 0 busy t wb t bers i/o 0 =0 successful erase page(row) address t wc ? a 25
flash memory 25 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c k9k1216q0c k9k1208q0c manufacture & device id read operation ce cle we ale re 90h read id command maker code device code 00h t rea address. 1cycle t ar i/ox ech device device device code* k9k1208q0c 36h k9k1208d0c 76h k9k1208u0c 76h k9k1216q0c xx46h k9k1216d0c xx56h k9k1216u0c xx56h code*
flash memory 26 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c k9k1216q0c k9k1208q0c device operation page read upon initial device power up, the device defaults to read1 mode. this operation is also initiated by writing 00h to the command regis- ter along with three address cycles. once the command is latched, it does not need to be written for the following page read ope ra- tion. two types of operations are available : random read, serial page read. the random read mode is enabled when the page address is changed. the 528 bytes(x8 device) or 264 words(x16 device) of data within the selected page are transferred to the data registers in less than 10 m s(t r ). the system controller can detect the completion of this data transfer(tr) by analyzing the output of r/ b pin. once the data in a page is loaded into the registers, they may be read out in 50ns cycle time by sequentially pulsing re . high to low transitions of the re clock output the data starting from the selected column address up to the last column address[column 511/ 527(x8 device) 255 /263(x16 device) depending on the state of gnd input pin]. the way the read1 and read2 commands work is like a pointer set to either the main area or the spare area. the spare area of 512 ~527 bytes(x8 device) or 256~263 words(x16 device) may be selectively accessed by writing the read2 command with gnd input pin low. addresses a 0~ a 3 (x8 device) or a 0~ a 2 (x16 device) set the starting address of the spare area while addresses a 4 ~a 7 are ignored in x8 device case or a 3~ a 7 must be "l" in x16 device case. the read1 command is needed to move the pointer back to the main area. figures 8, 9 show typical sequence and timings for each read operation. figure 8. read1 operation start add.( 4 cycle) 00h x8 device : a 0 ~ a 7 & a 9 ~ a 2 5 data output(sequential) (00h command) data field spare field ce cle ale r/ b we re t r main array (01h command) data field spare field 1st half array 2st half array note: 1) after data access on 2nd half array by 01h command, the start pointer is automatically moved to 1st half array (00h) at next cycle. 01h command is only available on x8 device(k9k1208x0c). i/ox x16 device : a 0 ~ a 7 & a 9 ~ a 2 5 1)
flash memory 27 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c k9k1216q0c k9k1208q0c figure 9. read2 operation 50h data output(sequential) spare field ce cle ale r/ b we start add.( 4 cycle) re t r x8 device : a 0 ~ a 3 & a 9 ~ a 25 main array data field spare field x16 device : a 0 ~ a 2 & a 9 ~ a 25 x8 device : a 4 ~ a 7 don?t care x16 device : a 3 ~ a 7 are "l" i/ox
flash memory 28 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c k9k1216q0c k9k1208q0c page program the device is programmed basically on a page basis, but it does allow multiple partial page programing of a byte/word or consecu tive bytes/words up to 528 (x8 device) or 264 (x16 device) , in a single page program cycle. the number of consecutive partial page program- ming operation within the same page without an intervening erase operation should not exceed 2 for main array and 3 for spare ar ray. the addressing may be done in any random order in a block. a page program cycle consists of a serial data loading period in whic h up to 528 bytes (x8 device) or 264 words (x16 device) of data may be loaded into the page register, followed by a non-volatile program- ming period where the loaded data is programmed into the appropriate cell. about the pointer operation, please refer to the atta ched technical notes. the serial data loading period begins by inputting the serial data input command(80h), followed by the three cycle address input and then serial data loading. the words other than those to be programmed do not need to be loaded.the page program confirm com- mand(10h) initiates the programming process. writing 10h alone without previously entering the serial data will not initiate the pro- gramming process. the internal write controller automatically executes the algorithms and timings necessary for program and veri fy, thereby freeing the system controller for other tasks. once the program process starts, the read status register command may be entered, with re and ce low, to read the status register. the system controller can detect the completion of a program cycle by mon- itoring the r/ b output, or the status bit(i/o 6) of the status register. only the read status command and reset command are valid while programming is in progress. when the page program is complete, the write status bit(i/o 0) may be checked(figure 10). the internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. the command register remains in read status command mode until another valid command is written to the command register. figure 10. program operation 80h r/ b address & data input i/o 0 pass 10h 70h fail t prog copy-back program the copy-back program is configured to quickly and efficiently rewrite data stored in one page within the array to another page within the same array without utilizing an external memory. since the time-consuming sequently-reading and its re-loading cycles are removed, the system performance is improved. the benefit is especially obvious when a portion of a block is updated and the rest of the block also need to be copied to the newly assigned free block. the operation for performing a copy-back is a sequential exec ution of page-read without burst-reading cycle and copying-program with the address of destination page. a normal read operation with "00h" command with the address of the source page moves the whole 528bytes/264words(x8 device:528bytes, x16 device:264words) data into the internal buffer. as soon as the flash returns to ready state, copy-back programming command "8ah" may be given with three address cycles of target page followed. the data stored in the internal buffer is then programmed direct ly into the memory cells of the destination page. once the copy-back program is finished, any additional partial page programming into t he copied pages is prohibited before erase. since the memory array is internally partitioned into four different planes, copy-back program is allowed only within the same memory plane. thus, a14 and a25, the plane address, of source and destination page address must be the same. figure 11. copy-back program operation 00h r/ b add.( 4 cycles) i/o 0 pass 8ah 70h fail t prog add.( 4 cycles) t r source address destination address i/ox i/ox
flash memory 29 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c k9k1216q0c k9k1208q0c figure 12. block erase operation block erase the erase operation is done on a block basis. block address loading is accomplished in three cycles initiated by an erase setup com- mand(60h). only address a 14 to a 25 is valid while a 9 to a 13 is ignored. the erase confirm command(d0h) following the block address loading initiates the internal erasing process. this two-step sequence of setup followed by execution command ensures that memor y contents are not accidentally erased due to external noise conditions. at the rising edge of we after the erase confirm command input, the internal write controller handles erase and erase-verify. when the erase operation is completed, the write status bit(i/o 0) may be checked. figure 12 details the sequence. 60h block add. : a 9 ~ a 2 5 r/ b address input( 3 cycle) i/o 0 pass d0h 70h fail t bers read status the device contains a status register which may be read to find out whether program or erase operation is completed, and whether the program or erase operation is completed successfully. after writing 70h command to the command register, a read cycle output s the content of the status register to the i/o pins on the falling edge of ce or re , whichever occurs last. this two line control allows the system to poll the progress of each device in multiple memory connections even when r/ b pins are common-wired. re or ce does not need to be toggled for updated status. refer to table 4 for specific status register definitions. the command register remains in status read mode until further commands are issued to it. therefore, if the status register is read during a random r ead cycle, a read command(00h or 50h) should be given before serial access cycle. table4. read status register definition i/o # status definition i/o 0 program / erase "0" : successful program / erase "1" : error in program / erase i/o 1 reserved for future use "0" i/o 2 "0" i/o 3 "0" i/o 4 "0" i/o 5 "0" i/o 6 device operation "0" : busy "1" : ready i/o 7 write protect "0" : protected "1" : not protected i/o 8~15 not use don?t care i/ox
flash memory 30 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c k9k1216q0c k9k1208q0c figure 13. read id operation ce cle ale re we 90h 00h address. 1cycle maker code device code t cea t ar t rea read id the device contains a product identification mode, initiated by writing 90h to the command register, followed by an address inpu t of 00h. two read cycles sequentially output the manufacture code(ech), and the device code respectively. the command register remains in read id mode until further commands are issued to it. figure 13 shows the operation sequence. t whr 1 figure 14. reset operation reset the device offers a reset feature, executed by writing ffh to the command register. when the device is in busy state during rand om read, program or erase mode, the reset operation will abort these operations. the contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. the command register is cleared to wait for the next command, and the status register is cleared to value c0h when wp is high. refer to table 5 for device status after reset operation. if the device is already in reset state a new reset command will not be accepted by the command register. the r/ b pin transitions to low for trst after the reset command is written. refer to figure 14 below. table5. device status after power-up after reset operation mode read 1 waiting for next command ffh r/ b t rst ech device i/ox i/ox device device code* k9k1208q0c 36h k9k1208d0c 76h k9k1208u0c 76h k9k1216q0c xx46h k9k1216d0c xx56h k9k1216u0c xx56h code*
flash memory 31 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c k9k1216q0c k9k1208q0c block lock mode is enabled while lockpre pin state is high, which is to offer protection features for nand flash data. the block lock mode is divided into unlock, lock, lock-tight operation. consecutive blocks protects data by allowing those blocks to be lo cked or lock-tighten with no latency. this block lock scheme offers two levels of protection. the first allows software control(comma nd input method) of block locking that is useful for frequently changed data blocks, while the second requires hardware control( wp low pulse input method) before locking can be changed that is useful for protecting infrequently changed code blocks. the followings summarized the locking functionality. - all blocks are in a locked state on power-up. unlock sequence can unlock the locked blocks. - the lock-tight command locks blocks and prevents from being unlocked. and lock-tight state can be returned to lock state only by hardware control( wp low pulse input). block lock mode - command sequence: lock block command(2ah) - all blocks default to locked by power-up and hardware control( wp low pulse input) - partial block lock is not available; lock block operation is based on all block unit - unlocked blocks can be locked by using the lock block command, and a lock block?s status can be changed to unlock or lock-tig ht using the appropriate commands 1. block lock operation 1) lock > in high state of lockpre pin, block lock mode and power on auto read are enabled, otherwise it is regarded as nand flash without lockpre pin. ce cle we 2a h lock command i/ox wp
flash memory 32 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c k9k1216q0c k9k1208q0c - command sequence: lock-tight block command(2ch) - lock-tighten blocks offer the user an additional level of write protection beyond that of a regular lock block. a block that is lock- tighten can?t have it?s state changed by software control, only by hardware control( wp low pulse input); unlocking multi area is not available - only locked blocks can be lock-tighten by lock-tight command. 3) lock-tight - command sequence: unlock block command(23h) + start block address + command(24h) + end block address - unlocked blocks can be programmed or erased. - an unlocked block?s status can be changed to the locked or lock-tighten state using the appropriate commands. - only one consecutive area can be released to unlock state from lock state; unlocking multi area is not available. - start block address must be nearer to the logical lsb(least significant bit) than end blcok address. - one block is selected for unlocking block when start block address is same as end block address. 2) unlock ce cle we ale 23 h unock command add.1 start block address 3cycles i/ox 24h add.2 end block address 3 cycles unlock command ce cle we 2c h lock-tight command i/ox wp wp add.3 add.1 add.2 add.3
flash memory 33 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c k9k1216q0c k9k1208q0c program/erase operation(in locked or lock-tighten block) on the program or erase operation in locked or lock-tighten block, busy state holds 1~10 m s( t lbsy) 60h(80h) r/ b address(&data input) d0h(10h) t lbsy i/ox locked or lock-tighten block address unlock lock lock-tight power-up wp x = h & unlock block command (23h) + start block address + command (24h) + end block address block lock reset wp x = l (>100ns) block lock reset wp x = l (>100ns) wp x = h & lock block command (2ah) wp x = h & lock-tight block command (2ch) unlock unlock figure 15. state diagram of block lock lock-tight lock-tight block command (2ch) lock lock lock lock lock-tight wp x = h & wp x = h & unlock block command (23h) + start block address + command (24h) + end block address
flash memory 34 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c k9k1216q0c k9k1208q0c block lock status can be read on a block basis, which may be read to find out whether designated block is available to be pro- grammed or erased. after writing 7ah command to the command register. and block address to be checked, a read cycle outputs the content of the block lock status register to the i/o pins on the falling edge of ce or re , whichever occurs last. this two line control allows the system to poll the progress of each device in multiple memory connections even when r /b pins are common-wired. re or ce does not need to be toggled for updated status. blcok lock status read is prohibited while the device is busy state. refer to table 6 for specific status register definitions. the command register remains in block lock status read mode until fur ther commands are issued to it. in high state of lockpre pin, write protection status can be checked by block lock status read(7ah) while in low state by status read(70h). 2. block lock status read ce cle we ale re 7 a h read block lock block lock status add.1 block address 3cycle i/ox dout add.2 table6. block lock status register definitions status command wp t whr2 add.3 io7~io3 io2 ( unlock) io1(lock) io0(lock-tight) read 1) block case x 0 1 0 read 2) block case x 1 1 0 read 3) block case x 0 0 1 read 4 ) block case x 1 0 1 (1)lock (2)unlock (3)lock-tight (4)unlock (1)lock (3)lock-tight (1)lock (2)unlock (3)lock-tight
flash memory 35 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c k9k1216q0c k9k1208q0c power-on auto-read the device is designed to offer automatic reading of the first page without command and address input sequence during power-on. an internal voltage detector enables auto-page read functions when vcc reaches about 1.8v. lockpre pin controls activation of auto- page read function. auto-page read function is enabled only when lockpre pin is logic high state . serial access may be done after power-on without latency. power-on auto read mode is available only on 3.3v device(k9k12xxu0c). figure 16. power-on auto-read (3.3v device only) v cc ce cle i/o x ale re we 1st ~ 1.8v pre r/ b 2nd 3rd .... n th ? ? ? ? ? ? ? t r ? ?
flash memory 36 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c k9k1216q0c k9k1208q0c ready/ busy the device has a r/ b output that provides a hardware method of indicating the completion of a page program, erase and random read completion. the r/ b pin is normally high but transitions to low after program or erase command is written to the command regis- ter or random read is started after address loading. it returns to high when the internal controller has finished the operation. the pin is an open-drain driver thereby allowing two or more r/ b outputs to be or-tied. because pull-up resistor value is related to tr(r/ b ) and current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(fig 17). its value c an be determined by the following guidance. v cc r/ b open drain output device gnd rp figure 17. rp vs tr ,tf & rp vs ibusy ibusy busy ready vcc voh tf tr vol c l 1.8v device - v ol : 0.1v, v oh : vcc q -0.1v 3.3v device - v ol : 0.4v, v oh : 2.4v 2.65v device - v ol : 0.4v, v oh : vcc q -0.4v
flash memory 37 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c k9k1216q0c k9k1208q0c t r , t f [ s ] i b u s y [ a ] rp(ohm) ibusy tr @ vcc = 3.3v, ta = 25 c , c l = 100pf 1k 2k 3k 4k 100n 200n 300n 3m 2m 1m 100 tf 200 300 400 3.6 3.6 3.6 3.6 2.4 1.2 0.8 0.6 rp(min, 1.8v part) = v cc (max.) - v ol (max.) i ol + s i l = 1.85v 3ma + s i l where i l is the sum of the input currents of all devices tied to the r/ b pin. rp value guidance rp(max) is determined by maximum permissible limit of tr rp(min, 3.3v part) = v cc (max.) - v ol (max.) i ol + s i l = 3.2v 8ma + s i l t r , t f [ s ] i b u s y [ a ] rp(ohm) ibusy tr @ vcc = 1.8v, ta = 25 c , c l = 30pf 1k 2k 3k 4k 100n 200n 300n 3m 2m 1m 30 tf 60 90 120 1.7 1.7 1.7 1.7 1.7 0.85 0.57 0.43 rp(min, 2.65v part) = v cc (max.) - v ol (max.) i ol + s i l = 2.5v 3ma + s i l t r , t f [ s ] i b u s y [ a ] rp(ohm) ibusy tr @ vcc = 2.65v, ta = 25 c , c l = 30pf 1k 2k 3k 4k 100n 200n 300n 3m 2m 1m 30 tf 60 90 120 2.3 2.3 2.3 2.3 2.3 1.1 0.75 0. 5 5
flash memory 38 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c k9k1216q0c k9k1208q0c the device is designed to offer protection from any involuntary program/erase during power-transitions. an internal voltage dete ctor disables all functions whenever vcc is below about 1.1v(1.8v device), 1.8v(2.65v device), 2v(3.3v device). wp pin provides hard- ware protection and is recommended to be kept at v il during power-up and power-down and recovery time of minimum 10 m s is required before internal circuit gets ready for any command sequences as shown in figure 18. the two step command sequence for program/erase provides additional software protection. figure 18. ac waveforms for power transition v cc wp high ? ? 1.8v device : ~ 1.5v we data protection & power up sequence 3.3v device : ~ 2.5v 1.8v device : ~ 1.5v 3.3v device : ~ 2.5v 10 m s ? ? 2.65v device : ~ 2.0v 2.65v device : ~ 2.0v

▲Up To Search▲

Price & Availability of K9K1208U0C-DIB00

	To Download K9K1208U0C-DIB00 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .