mitsubishi lsis m5m5v108cfp,vp,rv,kv,kr -70hi, -10hi, -70xi, -10xi 1048576-bit(131072-word by 8-bit)cmos static ram mitsubishi electric nc : no connection description features type name access time (max) active (max) stand-by (max) power supply current the m5m5v108cfp,vp,rv,kv,kr are a 1048576-bit cmos static ram organized as 131072 word by 8-bit which are fabricated using high-performance quadruple-polysilicon and double metal cmos technology. the use of thin film transistor (tft) load cells and cmos periphery result in a high density and low power static ram. they are low standby current and low operation current and ideal for the battery back-up application. the m5m5v108cvp,rv,kv,kr are packaged in a 32-pin thin small outline package which is a high reliability and high density surface mount device(smd). two types of devices are available. m5m5v108cvp,kv(normal lead bend type package), m5m5v108crv,kr(reverse lead bend type package).using both types of devices, it becomes very easy to design a printed circuit board. package application small capacity memory units low stand-by current 0.1? (typ.) directly ttl compatible : all inputs and outputs easy memory expansion and power down by s 1 ,s 2 data hold on +2v power supply three-state outputs : or - tie capability oe prevents data contention in the i/o bus common data i/o m5m5v108cfp,vp,rv,kv,kr-70hi 9.6? 70ns 5ma 100ns 70ns 100ns 2.7~3.6v 24? (1mhz) v cc m5m5v108cfp 32pin 525mil sop m5m5v108cvp,rv 32pin 8 x 20 mm tsop m5m5v108ckv,kr 32pin 8 x 13.4 mm tsop 1 m5m5v108cfp,vp,rv,kv,kr-10hi m5m5v108cfp,vp,rv,kv,kr-70xi m5m5v108cfp,vp,rv,kv,kr-10xi 2 2 16 15 14 13 1 12 11 10 9 8 7 6 5 4 3 2 pin configuration (top view) nc a 16 a 14 a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 dq 1 dq 2 dq 3 gnd v cc a 15 s 2 w a 13 a 8 a 9 a 11 oe a 10 s 1 dq 8 dq 7 dq 6 dq 5 dq 4 a 11 a 9 a 8 a 13 w s 2 a 15 v cc nc a 16 a 14 a 12 a 7 a 6 a 5 a 4 oe a 10 s 1 dq 8 dq 7 dq 6 dq 5 dq 4 gnd dq 3 dq 2 dq 1 a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 11 a 2 a 0 oe a 1 a 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 17 18 19 20 32
mitsubishi lsis m5m5v108cfp,vp,rv,kv,kr -70hi, -10hi, -70xi, -10xi 1048576-bit(131072-word by 8-bit)cmos static ram mitsubishi electric function block diagram the operation mode of the m5m5v108c series are determined by a combination of the device control inputs s 1 ,s 2 ,w and oe. each mode is summarized in the function table. a write cycle is executed whenever the low level w overlaps with the low level s 1 and the high level s 2 . the address must be set up before the write cycle and must be stable during the entire cycle. the data is latched into a cell on the trailing edge of w,s 1 or s 2 , whichever occurs first,requiring the set-up and hold time relative to these edge to be maintained. the output enable input oe directly controls the output stage. setting the oe at a high level, the output stage is in a high-impedance state, and the data bus contention problem in the write cycle is eliminated. a read cycle is executed by setting w at a high level and oe at a low level while s 1 and s 2 are in an active state(s 1 =l,s 2 =h). when setting s 1 at a high level or s 2 at a low level, the chip are in a non-selectable mode in which both reading and writing are disabled. in this mode, the output stage is in a high- impedance state, allowing or-tie with other chips and memory expansion by s 1 and s 2 . the power supply current is reduced as low as the stand-by current which is specified as i cc3 or i cc4 , and the memory data can be held at +2v power supply, enabling battery back-up operation during power failure or power-down operation in the non- selected mode. s 1 s 2 w oe mode dq i cc l l h h h h l h non selection write read high-impedance din dout active stand-by non selection high-impedance high-impedance active active stand-by function table l h l x h x x x x l x x 2
mitsubishi lsis m5m5v108cfp,vp,rv,kv,kr -70hi, -10hi, -70xi, -10xi 1048576-bit(131072-word by 8-bit)cmos static ram mitsubishi electric absolute maximum ratings capacitance symbol parameter test conditions pf pf unit max 6 10 typ min limits v i =gnd, v i =25mvrms, f=1mhz v o =gnd,v o =25mvrms, f=1mhz input capacitance output capacitance c i c o parameter supply voltage input voltage output voltage power dissipation operating temperature storage temperature unit v v v mw ? ? conditions with respect to gnd ta=25? 700 ?40~85 ?65~150 ratings symbol v cc dc electrical characteristics (ta=?40~85?, vcc=2.7~3.6v, unless otherwise noted) symbol parameter v v v max typ limits min test conditions unit v ? ?0.3*~4.6 ?0.3*~vcc + 0.3 (ta=?40~85?, unless otherwise noted) 0~vcc * ?.0v in case of ac ( pulse width 30ns ) note 1: direction for current flowing into an ic is positive (no mark). 2: typical value is vcc = 3v, ta = 25? ma * ?.0v in case of ac ( pulse width 30ns ) ? ? ma v vcc + 0.3 0.6 2.0 ?.3* 2.4 0.33 stand-by current 0.4 ? active supply current active supply current vcc ?0.5 ? 35 v ih v il v oh1 v oh2 v ol i i i o i cc1 i cc2 i cc3 i cc4 high-level input voltage low-level input voltage high-level output voltage 1 high-level output voltage 2 low-level output voltage input current output current in off-state stand-by current i oh = ?0.5ma i oh = ?0.05ma i ol = 2ma v i =0~vcc s 1 =v ih or s 2 =v il or oe=v ih v i/o =0~v cc s 1 =v il ,s 2 =v ih , other inputs=v ih or v il output-open(duty 100%) 1) s 2 0.2v other inputs=0~v cc 2) s 1 3 v cc ?.2v, s 2 3 v cc ?.2v other inputs=0~v cc s 1 =v ih or s 2 =v il , other inputs=0~v cc ~25? (max 4.6) 3 ~40? ~70? ~25? ~40? ~70? -hi -xi 1.2 3.6 12 0.6 1.8 4.8 30 5 70ns 100ns 1mhz v i v o p d t opr t stg ~85? ~85? 24 9.6 ?
mitsubishi lsis m5m5v108cfp,vp,rv,kv,kr -70hi, -10hi, -70xi, -10xi 1048576-bit(131072-word by 8-bit)cmos static ram mitsubishi electric (2) read cycle (3) write cycle symbol parameter t cr read cycle time address access time unit ns ns ns ns ns ns ns ns ns ns ns ns symbol parameter unit ns ns ns ns ns ns ns ns ns ns ns ns ns max min min max limits t a(s1) t a(s2) t a(oe) t dis(s1) t dis(s2) t dis(oe) t en(s1) t en(s2) t en(oe) t v(a) t a(a) limits -10hi,-10xi ac electrical characteristics (ta=?40~85?, unless otherwise noted ) (1) measurement conditions chip select 1 access time chip select 2 access time output enable access time output disable time after s 1 high output disable time after s 2 low output disable time after oe high output enable time after s 1 low output enable time after s 2 high output enable time after oe low data valid time after address 70 70 70 35 25 25 25 70 10 10 5 10 100 100 100 50 35 35 35 100 10 10 5 10 write cycle time write pulse width address setup time address setup time with respect to w chip select 1 setup time chip select 2 setup time data setup time data hold time write recovery time output disable time from w low output disable time from oe high output enable time from w high output enable time from oe low 35 35 100 75 0 85 85 85 40 0 0 5 5 25 25 70 55 0 65 65 65 30 0 0 5 5 v cc 2.7~3.6v input pulse level v ih =2.2v,v il =0.4v input rise and fall time 5ns reference level v oh =v ol =1.5v output loads fig.1, c l =30pf c l =5pf (for t en ,t dis ) transition is measured ?500mv from steady state voltage. (for t en ,t dis ) ................................. ............... ............. ..... ................... including scope and jig 1ttl c l dq fig.1 output load min max -70hi,-70xi max min t cw t w(w) t su(a) t su(a-wh) t su(s1) t su(s2) t su(d) t h(d) t rec(w) t dis(w) t dis(oe) t en(w) t en(oe) -10hi,-10xi -70hi,-70xi 4
mitsubishi lsis m5m5v108cfp,vp,rv,kv,kr -70hi, -10hi, -70xi, -10xi 1048576-bit(131072-word by 8-bit)cmos static ram mitsubishi electric t en (w) read cycle write cycle (w control mode) (4) timing diagrams data valid (note 3) (note 3) t a(a) t a (s1) t v (a) t a (s2) t en (s2) t dis (s1) t dis (s2) t a (oe) t en (oe) t dis (oe) (note 3) (note 3) (note 3) (note 3) t cr t h (d) t su (d) dq 1~8 s 1 t su (s1) s 2 oe t su (s2) t su (a-wh) t en(oe) t dis (oe) (note 3) (note 3) (note 3) (note 3) w t w (w) t rec (w) t su (a) t dis (w) t cw t en (s1) w = "h" level a 0~16 dq 1~8 s 1 s 2 oe a 0~16 stable data in 5
mitsubishi lsis m5m5v108cfp,vp,rv,kv,kr -70hi, -10hi, -70xi, -10xi 1048576-bit(131072-word by 8-bit)cmos static ram mitsubishi electric write cycle ( s 1 control mode) write cycle (s 2 control mode) t su (s1) (note 3) (note 3) t rec (w) t h (d) t cw (note 5) (note 3) (note 3) t su (a) (note 4) t su (d) t h (d) t cw (note 5) (note 3) (note 3) t su (s2) t rec (w) t su (a) (note 4) (note 3) (note 3) t su (d) data in stable data in stable dq 1~8 s 1 s 2 w a 0~16 dq 1~8 s 1 s 2 w a 0~16 note 3: hatching indicates the state is "don't care". 4: writing is executed while s 2 high overlaps s 1 and w low. 5: when the falling edge of w is simultaneously or prior to the falling edge of s 1 or rising edge of s 2 , the outputs are maintained in the high impedance state. 6: don't apply inverted phase signal externally when dq pin is output mode. 6
mitsubishi lsis m5m5v108cfp,vp,rv,kv,kr -70hi, -10hi, -70xi, -10xi 1048576-bit(131072-word by 8-bit)cmos static ram mitsubishi electric v cc = 3v 1) s 2 0.2v, other inputs = 0~3v 2) s 1 3 v cc ?.2v, s 2 3 v cc ?.2v other inputs = 0~3v (ta=?40~85?, unless otherwise noted) 0.2v t rec (pd) 2.7v s 2 0.2v (3) power down characteristics s 1 control mode s 2 control mode power down characteristics (1) electrical characteristics power down set up time power down recovery time (2) timing requirements (ta=?40~85?, unless otherwise noted ) t su (pd) t rec (pd) symbol parameter ns max typ limits min test conditions unit 0 5 ms 2.7v t su (pd) 0.2v 2.2v t su (pd) 2.7v 2.7v 2.2v t rec (pd) s 1 3 v cc - 0.2v v cc s 1 v cc s 2 symbol parameter v v max typ limits min test conditions unit ? v 2 0.2 v cc (pd) v i (s1) v i (s2) i cc (pd) power down supply voltage chip select input s 1 chip select input s 2 power down supply current 2.0 7 ~25? ~40? ~70? ~25? ~40? ~70? -hi -xi 1 3 10 0.5 1.5 4 v 0.6 vcc(pd) 2.7v vcc(pd) vcc(pd)<2.7v ~85? ~85? 20 8 ?
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