4 3 2 26 inverting input direct input offset adjust reference hold 27 32, 33 7, 35, 37 data valid digital ground analog ground 25 23 10 24 6 start convert bit 1 (msb) bit 14 (lsb) out-of-range +2.4v reference outpu t +12v a C5v a +5v a +5v d 39 38 36 34 timing and control sampling a/d non-inverting input 75 ? 523 ? 0.01f 5k ? 1 fine gain adjust 5 input amplifier 30 31 a1 correlated double sampler a? features ? ? ? ? ? 14-bit resolution ? ? ? ? ? 10mpps throughput rate (14-bits) ? ? ? ? ? functionally complete ? ? ? ? ? very low noise ? ? ? ? ? excellent signal-to-noise ratio ? ? ? ? ? edge triggered ? ? ? ? ? small, 40-pin, tdip package ? ? ? ? ? low power, 800mw typical ? ? ? ? ? low cost ? ? ? ? ? programmable analog bandwidth general description the adcds-1410 is an application-specific video signal processor designed for electronic-imaging applications that employ ccd's (charge coupled devices) as their photodetector. the adcds-1410 incorporates a "user configurable" input amplifier, a cds (correlated double sampler) and a sampling a/d converter in a single package, providing the user with a complete, high performance, low- cost, low-power, integrated solution. the key to the adcds-1410's performance is a unique, high- speed, high-accuracy cds circuit, which eliminates the effects of residual charge, charge injection and "kt/c" noise on the ccd's output floating capacitor, producing a "valid video" output signal. the adcds-1410 digitizes this resultant "valid video" signal using a high-speed, low-noise sampling a/d converter. the adcds-1410 requires only the rising edge of start convert pulse to initiate its conversion process. additional features of the adcds-1410 include gain adjust, offset adjust, precision +2.4v reference, and a programmable analog bandwidth function. figure 1. adcds-1410 functional block diagram 1 fine gain adjust 40 no connect 2 offset adjust 39 +12v 3 direct input 38 C5va 4 inverting input 37 analog ground 5 non-inverting input 36 +5va 6 +2.4v ref. output 35 analog ground 7 analog ground 34 +5vd 8 no connect 33 digital ground 9 no connect 32 digital ground 10 bit 14 (lsb) 31 a1 11 bit 13 30 a 12 bit 12 29 no connect 13 bit 11 28 no connect 14 bit 10 27 data valid 15 bit 9 26 reference hold 16 bit 8 25 start convert 17 bit 7 24 out-of-range 18 bit 6 23 bit 1 (msb) 19 bit 5 22 bit 2 20 bit 4 21 bit 3 input/output connections pin function pin function ? ? datel, inc., mansfield, ma 02048 (usa) ? tel: (508) 339-3000, (800) 233-2765 fax: (508) 339-6356 ? email: sales@datel.com ? internet: www.datel.com adcds-1410 14-bit, 10 megapixels/second imaging signal processor advanced product data ? ? a subsidiar y of c&d technologies
adcds-1410 2 ? ? analog input min. typ. max. units input voltage range (externally configurable) 0.350 2.8 volts p-p input resistance 5000 ohm input capacitance 10 pf digital inputs logic levels logic 1 +3.5 volts logic 0 +.80 volts logic loading logic 1 +10 ua logic 0 C10 ua digital outputs logic levels logic 1 (ioh = .5ma) +2.4 volts logic 1 (ioh = 50a) +4.5 volts logic 0 (iol = 1.6ma) +0.4 volts logic 0 (iol = 50ua) +0.1 volts internal reference voltage (fine gain adjust pin (1) grounded) +25c 2.35 2.4 2.45 volts 0 to 70c 2.35 2.4 2.45 volts C55 to +125c 2.35 2.4 2.45 volts external current 1.0 ma static performance differential nonlinearity (histogram, 98khz) +25c C0.90 0.5 +.90 lsb 0 to 70c C0.90 0.5 +.90 lsb C55 to +125c C1.0 0.6 +1.0 lsb integral nonlinearity +25c 2.5 lsb 0 to 70c 2.5 lsb C55 to +125c 2.5 lsb guaranteed no missing codes 0 to 70c 14 lsb C55 to +125c 14 lsb dc noise +25c 1.0 1.6 lsb 0 to 70c 1.0 2.0 lsb C55 to +125c 1.25 2.5 lsb offset error +25c 0.6 1.25 %fsr 0 to 70c 0.6 1.25 %fsr C55 to +125c 0.6 1.45 %fsr gain error +25c 1.00 2.8 %fsr 0 to 70c 1.35 2.8 %fsr C55 to +125c 1.35 2.8 %fsr parameters min. typ. max. units +12v supply (pin 32) 0 +14 volts C5v supply (pin 31) C0.3 +6.5 volts +5v supply (pin 28, 29) 0 C6.5 volts digital input (pin 23, 24) C0.3 vdd+0.3v volts analog input (pin 3,4,5) C5 +5 volts lead temperature (10 seconds) 300 c absolute maximum ratings functional specifications t he following specifications apply over the operating temperature range, under the following conditions: vcc=+12v, +vdd=+5v, vee=C5v, fin=98khz, sample rate= 10msps. dynamic performance min. typ. max. units reference hold aquisition time 40 ns droop @ +25c 25 mv/us @ C55 to +125c 100 mv/us peak harmonic (sfdr) (cdd-in, input on pin (3) input @ 98khz) @ +25 c C76 db @ 0 to +70c C76 db @ C55 to +125c C74 db peak harmonic (sfdr) (input on pin (5) input @ 98khz) @ +25 c C76 db @ 0 to +70c C76 db @ C55 to +125c C74 db total harmonic distortion (cdd-in, input on pin (3) input @ 98khz) @ +25 c C75 db @ 0 to +70c C75 db @ C55 to +125c C74 db (input on pin (5) input @ 98khz) @ +25 c C76 db @ 0 to +70c C76 db @ C55 to +125c C74 db signal-to-noise ratio without distortion (cdd-in, input on pin (3) input @ 98khz) @ +25 c 73 75 db @ 0 to +70c 73 75 db @ C55 to +125c 70 73 db (input on pin (5) input @ 98khz) @ +25 c 73 75 db @ 0 to +70c 73 75 db @ C55 to +125c 70 73 db signal-to-noise ratio with distortion (cdd-in, input on pin (3) input @ 98khz) @ +25 c 71 db @ 0 to +70c 71 db @ C55 to +125c 70 db (input on pin (5) input @ 98khz) @ +25 c 71 db @ 0 to +70c 71 db @ C55 to +125c 70 db signal timing conversion rate C55 to +125c 10 msps conversion time 100 nsec start convert pulse width 50 nsec power requirements power supply range +12v supply +11.4 +12.0 +12.6 volts +5v supply +4.75 +5.0 +5.25 volts C5v supply C4.75 C5.0 C5.25 volts ? ? a subsidiar y of c&d technologies
adcds-1410 3 ? ? technical notes 1. obtaining fully specified performance from the adcds-1410 requires careful attention to pc-card layout and power supply decoupling. the device's analog and digital grounds are connected to each other internally. depending on the level of digital switching noise in the overall ccd system, the performance of the adcds-1410 may be improved by connecting all ground pins (7,32,33,35, 37) to a large analog ground plane beneath the package. the use of a single +5v analog supply for both the +5v a (pin 36) and +5v d (pin 34) may also be beneficial. 2. bypass all power supplies to ground with a 4.7f tantalum capacitor in parallel with a 0.1f ceramic capacitor. locate the capacitors as close to the package as possible. 3. if using the suggested offset and gain adjust circuits (figure 3 & 5), place them as close to the adcds-1410's package as possible. 4. a0 and a1 (pins 30, 31) should be bypassed with 0.1f capacitors to ground to reduce susceptibility to noise. adcds-1410 modes of operation the input amplifier stage of the adcds-1410 provides the designer with a tremendous amount of flexibility. the architecture of the adcds-1410 allows its input-amplifier to be configured in any of the following configurations: ? direct mode (ac coupled) ? non-inverting mode ? inverting mode when applying inputs which are less than 2.8vp-p, a coarse gain adjustment (applying an external resistor to pin 4) must be performed to ensure that the full scale video input signal (saturated signal) produces a 2.8vp-p signal at the input- amplifier's output (v out ). in all three modes of operation, the video portion of the signal at the cds input (i.e. input-amplifier's v out ) must be more negative than its associated reference level and v out should not exceed 2.8v dc. the adcds-1410 achieves it specified accuracies without the need for external calibration. if required, the device's small figure 2a. figure 2b. 4 3 5 75 ? 523 ? v in no connect v out = 2.8vp-p 5k ? 0.01f rext 4 3 5 75 ? 523 ? v in no connect v out = 2.8vp-p 5k ? 0.01f rext figure 2c. 4 3 5 75 ? 523 ? v in no connect v out = 2.8vp-p 5k ? 0.01f power requirements min. typ. max. units power supply current +12v supply +20 +26 ma power supply current +5v supply +65 +70 ma C5v supply C50 C55 ma power dissipation 0.7 0.99 w atts power supply rejection (5%) @ +25c 0.02 0.03 % fsr/ % v environmental operating temperature range adcds-1410 0 +70 c ADCDS-1410EX C55 +125 c storage temperature C65 +150 c package type 40-pin, tdip weight 16.10 grams initial offset and gain errors can be reduced to zero using the fine gain adjust (pin1) and offset adjust (pin 2) features. direct mode (ac coupled) this is the most common input configuration as it allows the adcds-1410 to interface directly to the output of the ccd with a minimum amount of analog "front-end" circuitry. this mode of operation is used with full-scale video input signals from 0.350vp-p to 2.8vp-p. figure 2a. describes the typical configuration for applications using a video input signal with a maximum amplitude of 0.350vp-p. the coarse gain of the input amplifier is determined from the following equation: v out = 2.8vp-p = v in *(1+(523/75)), with all internal resistors having a 1% tolerance. additional fine gain adjustment can be accomplished using the fine gain adjust (pin 1 see figure 5). figure 2b. describes the typical configuration for applications using a video input signal with an amplitude greater than 0.350vp-p and less than 2.8vp-p. using a single external series resistor (see figure 4.), the coarse gain of the adcds- 1410 can be set, with additional fine gain adjustments being made using the fine gain adjust function (pin 1 see figure 5). the coarse gain of the input amplifier can be determined from the following equation: v out = 2.8vp-p = v in *(1+(523/(75+rext))), with all internal resistors having a 1% tolerance. ? ? ? ???
adcds-1410 4 ? ? inverting mode the inverting mode of operation can be used in applications where the analog input to the adcds-1410 has a video input signal whose amplitude is more positive than its associated reference level. the adcds-1410s correlated double sampler (i.e. input amplifier's v out ) requires that the video signal's amplitude be more negative than its reference level at all times (see timing diagram for details). using the adcds-1410 in the inverting mode allows the designer to perform an additional signal inversion to correct for any analog "front end" pre-processing that may have occurred prior to the adcds-1410. figure 2e. describes the typical configuration for applications using a video input signal with a maximum amplitude of 0.350vp-p. additional fine gain adjustments can be made using the fine gain adjust function (pin 1). the coarse gain of this circuit can be determined from the following equation: v out = 2.8vp-p = Cv in *(523/75), with all internal resistors having a 1% tolerance. figure 2f. describes the typical configuration used in applications needing to invert video input signals whose amplitude is greater than 0.350vp-p. using a single external series resistor (see figure 4.), the initial gain of the adcds- 1410 can be set, with additional fine gain adjustments being made using the fine gain adjust function (pin 1). the coarse gain of this circuit can be determined from the following equation: v out = 2.8vp-p = Cv in *(523/75+rext), with all internal resistors having a 1% tolerance. figure 4. coarse gain adjustment plot non-inverting mode the non-inverting mode of the adcds-1410 allows the designer to either attenuate or add non-inverting gain to the video input signal. this configuration also allows bypassing the adcds-1410's internal coupling capacitor, allowing the user to provide an external capacitor of appropriate value. figure 2c. describes the typical configuration for applications using video input signals with amplitudes greater than 0.350vp-p and less than 2.8vp-p (with common mode limit of 2.5v dc). using a single external series resistor (see figure 4.), the coarse gain of the adcds-1410 can be set with additional fine gain adjustments being made using the fine gain adjust function (pin 1 see figure 5). the coarse gain of the circuit can be determined from the following equation: v out = 2.8vp-p = v in *(1+(523/(75+rext))), with all internal resistors having a 1% tolerance. figure 2d. describes the typical configuration for applications using a video input signal whose amplitude is greater than 2.8vp-p. using a single external series resistor (rext 1) in conjunction with the internal 5k (1%) resistor to ground, an attenuation of the input signal can be achieved. additional fine gain adjustments being made using the fine gain adjust function (pin 1). the coarse gain of this circuit can be determined from the following equation: v out = 2.8vp-p = [v in *(5000/(rext1+5000))]* [1+(523/(75+rext2))], with all internal resistors having a 1% tolerance. figure 2d. figure 2e. 4 3 5 75 ? 523 ? no connect v out = 2.8vp- p 5k ? 0.01f rext1 v in rext2 4 3 5 75 ? 523 ? no connect v out = 2.8vp-p 5k ? 0.01f Cv in 4 3 5 75 ? 523 ? no connect v out = 2.8vp- p 5k ? 0.01f C v in rext figure 2f. figure 3. offset adjustment circuit ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
adcds-1410 5 ? ? figure 6. offset adjustment vs. external series resistor offset adjustment vs. external series resistor 10 100 1000 10000 0 5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60 k external series resistor (ohm's) lsb's of adjustment figure 5. fine gain adjustment circuit external series resistor value ( ohms ) 0.01 0.1 1 10 100 0 5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k offset adjustment sensitivity external series resistor vs . output variation (lsb's) output variation (lsb's) peak-peak variation at potentiometer 1mv 10mv 100mv figure 7. offset adjustment sensitivity offset adjustment manual offset adjustment for the adcds-1410 can be accomplished using the adjustment circuit shown in figure 3. a software controlled d/a converter can be substituted for the 20k ? potentiometer. the offset adjustment feature allows the user to adjust the offset/dark current level of the adcds-1410 until the output bits are 00 0000 0000 0000 and the lsb flickers between 0 and 1. offset adjust should be performed before gain adjust to avoid interaction. the adcds-1410's offset adjustment is dependent on the value of the external series resistor used in the offset adjust circuit (figure 3). the offset adjustment graph (figure 6) illustrates the typical relationship between the external series resistor value and its offset adjustment capability utilizing 5v supplies. offset adjustment sensitivity it should be noted that with increasing amounts of offset adjustment (smaller values of external series resistors), the adcds-1410 becomes more susceptible to power supply noise or voltage variations seen at the wiper of the offset potentiometer. for example: external 50k ? ? ? ? ? resistor: 1. 10mv of noise or voltage variation at the potentiometer will produce 0.25lsb's of output variation. 2. 100mv of noise or voltage variation at the potentiometer will produce 2.5lsb's of output variation. the offset adjustment sensitivity graph (figure 7) illustrates the offset adjustment sensitivity over a wide range of external resistor and noise values. if a large offset voltage is required, it is recommended that a very low noise external reference be used in the offset adjust circuit in place of power supplies. the adcds-1410's +2.4v reference output could be configured to provide the reference voltage for this type of application. fine gain adjustment fine gain adjustment (pin 1) is provided to compensate for the tolerance of the external coarse gain resistor (rext) and/ or the unavailability of exact coarse gain resistor (rext) values. note, the fine gain adjustment will not change the expected input amplifier's full scale v out (2.8vp-p.) instead, the gain of the adcds-1410's internal a/d is adjusted allowing the actual input amplifier's full scale v out to produce an output code of all ones (11 1111 1111 1111). fine gain adjustment for the adcds-1410 is accomplished using the adjustment circuit shown below (figure 5). a software controlled d/a converter can be substituted for the 20k ? potentiometer. the fine gain adjust circuit ensures that the video input signal (saturated signal) will be properly scaled to obtain the desired full scale digital output of 11 1111 1111 1111, with the lsb flickering between 0 and 1. fine gain adjust should be performed following the offset adjust ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ???
adcds-1410 6 ? ? table 1. out-of-range conditions table 2. output coding out over under i nput of range msb range range si gnal 0 0 0 0 in range 0 1 0 0 in range 1 0 0 1 underrrange 1 1 1 0 overrange notes: ? input amplifier v out = (video signal - reference level) ? the video portion of the differential signal (input-amplifier's v out ) must be more negative than its associated reference level and v out should not exceed 2.8v dc. video signal-reference signal > C2.80000 >full scale C1lsb 11 1111 1111 1111 1 C2.80000 full scale C1lsb 11 1111 1111 1111 0 C2.10000 3/4fs 11 0000 0000 0000 0 C1.40000 1/2fs 10 0000 0000 0000 0 C0.70000 1/4fs 01 0000 0000 0000 0 C0.35000 1/8fs 00 1000 0000 0000 0 C0.000171 1 lsb 00 0000 0000 0001 0 0 0 00 0000 0000 0000 0 video signal-reference signal <0 ? <0 00 0000 0000 0000 1 input amplifier v out , ? ? ? ? ? (volts p-p) scale digital output out-of-range output coding the adcds-1410's output coding is straight binary as indicated in table 2. the table shows the relationship between the output data coding and the difference between the reference signal voltage and its corresponding video signal voltage. (these voltages are referred to the output of the adcds-1410's input amplifier's v out ). programmable analog bandwidth function when interfacing to ccd arrays with very high-speed "read- out" rates, the adcds-1410's input stage must have sufficient analog bandwidth to accurately reproduce the output signals of the ccd array. the amount of analog bandwidth determines how quickly and accurately the "reference hold" and the "cds output" signals will settle. if only a single analog bandwidth was offered, the adcds-1410's bandwidth would be set to acquire and digitize ccd output signals to 14-bit accuracy, at maximum conversion rate of 10mhz (100ns see figure 11. for details). applications not requiring the maximum conversion rate would be forced to use the full analog bandwidth at the possible expense of noise performance. the adcds-1410 avoids this situation by offering a fully programmable analog bandwidth function. the adcds-1410 allows the user to "bandwidth limit" the input stage in order to realize the highest level of noise performance for the application being considered. table 3. describes how to select the appropriate reference hold "aquisition time" and cds output "settling time" needed for a particular application. each of the selections listed in table 3. have been optimized to provide only enough analog bandwidth to acquire a full scale input step, to 14-bit accuracy, in a single conversion. increasing the analog bandwidth (using a faster settling and acquisition time) would only serve to potentially increase the amount of noise at the adcds-1410's output. the adcds- 1410 uses a two bit digital word to select four different analog bandwidths for the adcds-1410's input stage (see table 3. for details). msb out-of-range "overrange" "underrange" figure 8. overrange/ underrange circuit to avoid interaction. the fine gain adjust provides 256 codes of adjust when 5v supplies are used for the fine gain adjust circuit. out-of-range indicator the adcds-1410 provides a digital out-of-range output signal (pin 24) for situations when the video input signal (saturated signal) is beyond the input range of the internal a/d converter. the digital output bits and the out-of-range signal correspond to a particular sampled video input voltage, with both of these signals having a common pipeline delay. using the circuit described in figure 8., both overrange and underrange conditions can be detected (see table 1). when combined with a d/a converter, digital detection and orrection can be performed for both the gain and offset errors. ? ? a subsidiar y of c&d technologies
adcds-1410 7 ? ? table 3. programmable analog bandwidth reference hold cds output a0 a1 adcds-1410 maximum "aquisition time" "settling time" (pin 30) (pin 31) conversion rate C3db bw 40ns 40ns 0 0 10mhz 14mhz 80ns 80ns 1 0 5mhz 10mhz 150ns 150ns 0 1 3mhz 5mhz 300ns 300ns 1 1 1.2mhz 3mhz note: see figure 11. for timing details timing the adcds-1410 requires two independently operated signals to accurately digitize the analog output signal from the ccd array. ? reference hold (pin 26) ? start convert (pin 25) the "reference hold" signal controls the operation of an internal sample-hold circuit. a logic "1" places the sample- hold into the hold mode, capturing the value of the ccd's figure 9. adcds-1410 connection diagram reference signal. the reference hold signal allows the user to control the exact moment when the sample-hold is placed into the "hold" mode. for optimal performance the sample- hold should be placed into the "hold" mode once the reference signal has fully settled from all switching transients to the desired accuracy (user defined). once the reference signal has been "held" and the video portion of the ccd's analog output signal appears at the adcds-1410's input, the adcds-1410's correlated double sampler produces a "cds output" signal (see figure 11.) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ???????? ????????????????????
mechanical dimensions inches (mm) ordering information operating 40-pin model temperature range p ackage adcds-1410 0 to 70c tdip ADCDS-1410EX C55 to 125c tdip datel, inc. 11 cabot boulevard, mansfield, ma 02048-1151 tel: (508) 339-3000 (800) 233-2765 fax: (508) 339-6356 internet: www.datel.com email: sales@datel.com datel makes no representation that the use of its products in the circuits described herein, or the use of other technical info rmation contained herein, will not infringe upon existing or future patent rights. the descriptions contained herein do not imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. specifications are s ubject to change without notice. the datel logo is a registered datel, inc. trademark. datel (uk) ltd. tadley, england tel: (01256)-880444 datel s.a.r.l. montigny le bretonneux, france tel: 01-34-60-01-01 datel gmbh munchen, germany tel: 89-544334-0 datel kk tokyo, japan tel: 3-3779-1031, osaka tel: 6-6354-2025 ds-0525 12/02 ? ? iso 9001 i so 9001 ? ? ? ? ? ? ? ? ? ? adcds-1405 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? adcds-1410 8 ? ? figure 11. adcds-1410 timing diagram figure 10. reference hold timing which is the difference between the "held" reference level and its associated video level. when the "cds output" signal has settled to the desired accuracy (user defined), the a/d conversion process can be initiated with the rising edge of a single start convert (pin 25) signal. once the a/d conversion has been initiated, reference hold (pin 26) can be placed back into the "acquisition" mode in order to begin aquiring the next reference level. for optimal performance the adcds-1410's internal sample-hold should be placed back into the "aquisition" mode (reference hold to logic "0") during the ccd's "reference quiet time" ("reference quiet time" is defined as the period when the ccd's reference signal has settled from all switching transients to the desired accuracy (see figure 10.)). placing the sample-hold back into the "aquisition" mode during the "reference quiet time" prevents the adcds-1410's internal amplifiers from unecessarily tracking (reproducing) the large switching transients that occur during the ccd's reset to reference transition. ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ???????? ???????????????????
mechanical dimensions inches (mm) ordering information operating 40-pin model temperature range p ackage adcds-1410 0 to 70c tdip ADCDS-1410EX C55 to 125c tdip datel, inc. 11 cabot boulevard, mansfield, ma 02048-1151 tel: (508) 339-3000 (800) 233-2765 fax: (508) 339-6356 internet: www.datel.com email: sales@datel.com datel makes no representation that the use of its products in the circuits described herein, or the use of other technical info rmation contained herein, will not infringe upon existing or future patent rights. the descriptions contained herein do not imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. specifications are s ubject to change without notice. the datel logo is a registered datel, inc. trademark. datel (uk) ltd. tadley, england tel: (01256)-880444 datel s.a.r.l. montigny le bretonneux, france tel: 01-34-60-01-01 datel gmbh munchen, germany tel: 89-544334-0 datel kk tokyo, japan tel: 3-3779-1031, osaka tel: 6-6354-2025 ds-0525 12/02 ? ? iso 9001 i so 9001 ? ? ? ? ? ? ? ? ? ? adcds-1405 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? a subsidiar y of c&d technologies ds-0525 03/05 datel makes no representation that the use of its products in the circuits described herein, or the use of other technical information contained herein, will not infringe upon existing or future patent rights. the descriptions contained herein do not imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. speci?cations are subject to change without notice. the datel logo is a registered datel, inc. trademark. datel (uk) ltd. tadley, england tel: (01256)-880444 internet: www.datel-europe.com e-mail: datel.ltd@datel.com datel s.a.r.l . montigny le bretonneux, france tel: 01-34-60-01-01 internet: www.datel-europe.com e-mail: datel.sarl@datel.com datel gmbh mnchen, germany tel: 89-544334-0 internet: www.datel-europe.com e-mail: datel.gmbh@datel.com datel kk tokyo, japan tel: 3-3779-1031, osaka tel: 6-6354-2025 internet: www.datel.co.jp email: salestko@datel.co.jp, salesosa@datel.co.jp datel china shanghai, china tel: 011-86-51317131 e -mail: davidx@datel.com datel, inc. 11 cabot boulevard, mans?eld, ma 0204 8 -1151 tel: (508) 339-3000 (800) 233-2765 fax: (508) 339-6356 www.datel.com email: sales@datel.com www.cdpowerelectronics.com iso 9001 registered ? ? a subsidiar y of c&d technologies adcds-1410
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