1 industrial temperature range idt74sstv16859 13-bit to 26-bit registered buffer with sstl i/o november 2008 2008 integrated device technology, inc. dsc-5947/9 c idt74sstv16859 industrial temperature range functional block diagram 13-bit to 26-bit registered buffer with sstl i/o description: the sstv16859 is a 13-bit to 26-bit registered buffer designed for 2.3v- 2.7v v dd and supports low standby operation. all data inputs and outputs are sstl_2 level compatible with jedec standard for sstl_2. reset is an lvcmos input since it must operate predictably during the power-up phase. reset , which can be operated independent of clk and clk , must be held in the low state during power-up in order to ensure predictable outputs (low state) before a stable clock has been applied. reset , when in the low state, will disable all input receivers, reset all registers, and force all outputs to a low state, before a stable clock has been applied. with inputs held low and a stable clock applied, outputs will remain low during the low-to-high transition of reset . applications: ? ideally suited for dimm ddr registered applications features: ? 2.3v to 2.7v operation ? sstl_2 class ii style data inputs/outputs ? differential clk input ? reset control compatible with lvcmos levels ? latch-up performance exceeds 100ma ? esd >2000v per mil-std-883, method 3015; >200v using machine model (c = 200pf, r = 0) ? available in 56 pin vfqfpn and 64 pin tssop packages the idt logo is a registered trademark of integrated device technology, inc. 51 48 49 45 35 r 1d c1 16 q 1a reset clk clk v ref d 1 to 12 other channels 32 q 1b
2 industrial temperature range idt74sstv16859 13-bit to 26-bit registered buffer with sstl i/o pin configurations tssop top view function table (1) input reset clk clk d q outputs h
3 industrial temperature range idt74sstv16859 13-bit to 26-bit registered buffer with sstl i/o pin description pin names description q 1 - q 13 data output gnd ground v ddq output-stage drain power voltage v dd logic power voltage reset asynchronous reset input - resets registers and disables data and clock differential input recievers v ref input reference voltage clk positive master clock input clk negative master clock input d 1 - d 13 data input - clocked in on the crossing of the rising edge of clk and the falling edge of clk center pad ground (mlf package only) symbol parameter test conditions min. typ. max. unit v ik control inputs v dd = 2.3v, i i = ?
4 industrial temperature range idt74sstv16859 13-bit to 26-bit registered buffer with sstl i/o operating characteristics, t a = 25oc (1) symbol parameter min. typ. (1) max. unit v dd supply voltage v ddq ? 2.7 v v ddq output supply voltage 2.3 2.5 2.7 v v ref reference voltage (v ref = v ddq /2) 1.15 1.25 1.35 v v tt termination voltage v ref ? 40mv v ref v ref + 40mv v v i input voltage 0 ? v dd v v ih ac high-level input voltage data inputs v ref + 310mv ? ? v v il ac low-level input voltage data inputs ? ? v ref ? 310mv v v ih dc high-level input voltage data inputs v ref + 150mv ? ? v v il dc low-level input voltage data inputs ? ? v ref ? 150mv v v ih high-level input voltage reset 1.7 ? ? v v il low-level input voltage reset ? ? 0.7 v v icr common-mode input range clk, clk 0.97 ? 1.53 v v i (pp) peak-to-peak input voltage clk, clk 360 ? ? mv i oh high-level output current ? ? ? 20 ma i ol low-level output current ? ? 20 t a operating free-air temperature ? 40 ? +85 c note: 1. the reset input of the device must be held at v dd or gnd to ensure proper device operation. switching characteristics over recommended free-air operating range (unless otherwise noted) v dd = 2.5v 0.2v symbol parameter min max. unit f max 200 ? m h z t pd clk and clk to q 1.1 2.8 ns t phl reset to q ? 5 ns timing requirements over recommended operating free-air temperature range v dd = 2.5v 0.2v symbol parameter min. max. unit clock clock frequency ? 200 mhz tw pulse duration, clk, clk high or low 2.5 ? ns t act differential inputs active time (1) ?22ns t inact differential inputs inactive time (2) ?22ns t su setup time, fast slew rate (3, 5) data before clk
5 industrial temperature range idt74sstv16859 13-bit to 26-bit registered buffer with sstl i/o test circuits and waveforms (v dd = 2.5v 0.2v) voltage waveforms - pulse duration notes: 1. c l includes probe and jig capacitance. 2. i dd tested with clock and data inputs held at v dd or gnd, and i o = 0ma. 3. all input pulses are supplied by generators having the following characteristics: prr load circuit voltage waveforms - setup and hold times voltage waveforms - propagation delay times voltage waveforms - propagation delay times voltage and current waveforms inputs active and inactive times timing input v icr v i(pp) t plh t phl output v oh v ol v icr v tt v tt v oh v ol v ih v il t phl v dd /2 v tt lvcmos reset input output v ref v ih v il v ref input t w v ref v ih v il v ref input v icr v i(pp) t su t n timing input from output under test v tt r l =50
6 industrial temperature range idt74sstv16859 13-bit to 26-bit registered buffer with sstl i/o ordering information corporate headquarters for sales: san jose, ca 95138 fax: 408-284-2775 www.idt.com xx xx x xx package device type temp. range pa nl thin shrink small outline package thermally enhanced plastic very fine pitch quad flat no lead package 74 13-bit to 26-bit registered buffer with sstl i/o ?40c to +85c sstv 859 16 xx family double-density
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