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| the hm53461/hm53462 is a 262,144-bit multiport memory equipped with a 64 k-word 4- bit dynamic ram port and a 256-word 4-bit serial access memory (sam) port. the sam port is connected to an internal 1,024-bit data register through a 256-word 4-bit serial read or write access control. in the read transfer cycle, the memory cell data is transferred from a selected word line of the ram port to the data register. the ram port has a write mask capability in addition to the conventional operation mode. write bit selection out of four data bits can be achieved. the hitachi 2 m cmos process achieves a fast serial access operation and low power dissipation. all inputs and outputs, including clocks, are ttl compatible. in hm53462, the ram port has logic operation capability. by using this function, logic operation between memory data and input data can be done in one cycle. features multiport organization (ram; 64 k-word 4-bit and sam; 256 word 4-bit) double layer polysilicon/polycide n-well cmos process single 5 v ( 10%) low power active: ram: 380 mw max sam: 220 mw max standby: 40 mw max. access time ram: 100 ns/120 ns/150 ns sam: 40 ns/40 ns/60 ns cycle time random read or write cycle time (ram): 190 ns/220 ns/260 ns serial read or write cycle time (sam): 40 ns/40 ns/60 ns ttl compatible 256 refresh cycles: 4 ms refresh function ras -only refresh cas -before- ras refresh hidden refresh data transfer operation (between ram and sam) fast serial access operation asynchronized with ram port (except data transfer cycle) real time read transfer capability write mask mode capability logic operation capability between din and dout (hm53462 series) sam organization can be changed to 1024 1 (hm53462 series) ordering information access type no. time package HM53461P-10 100 ns hm53461p-12 120 ns hm53461p-15 150 ns hm53461zp-10 100 ns hm53461zp-12 120 ns hm53461zp-15 150 ns hm53461jp-10 100 ns hm53461jp-12 120 ns hm53461jp-15 150 ns hm53462p-10 100 ns hm53462p-12 120 ns hm53462p-15 150 ns hm53462zp-10 100 ns hm53462zp-12 120 ns hm53462zp-15 150 ns hm53462jp-10 100 ns hm53462jp-12 120 ns hm53462jp-15 150 ns 300-mil, 24-pin plastic soj (cp-24d) 28-pin plastic zip (zp-24) 400-mil, 24-pin plastic dip (dp-24a) 24-pin plastic soj (cp-24d) 24-pin plastic zip (zp-24) 400-mil, 24-pin plastic dip (dp-24a) 1 hm53461 series, hm53462 series 65,536-word 4-bit multiport cmos video ram
2 hm53461, hm53462 series hm53461, hm53462 series pin arrangement pin description pin name function a0?7 address inputs i/o1?/o4 ram port data input/output si/o1?i/o4 sam port data input/output ras row address strobe cas column address strobe sc serial clock we write enable dt / oe data transfer/output enable soe sam port enable v cc power supply v ss ground 1 i/o3 3 soe 5 si/o4 7sc 9 si/o2 11 i/o1 13 we 15 a6 17 a4 19 a7 21 a2 23 a0 i/o4 2 si/o3 4 v ss 6 si/o1 8 dt/oe 10 i/o2 12 ras 14 a5 16 v cc 18 a3 20 a1 22 cas 24 (bottom view) hm53461zp series hm53462zp series (top view) sc si/o1 si/o2 dt , oe i/o1 i/o2 we ras a6 a5 a4 v cc v ss si/o4 si/o3 soe i/o4 i/o3 cas a0 a1 a2 a3 a7 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 hm53461p/jp series hm53462p/jp series 3 hm53461, hm53462 series hm53461, hm53462 series block diagram i/o1 i/o2 i/o3 i/o4 i/o buffer y decoder 64 k memory array x decoder pointer 256 data register si/o buffer si/o1 si/o2 si/o3 si/o4 vbb generator sc clock generator soe clock generator transfer control oe clock generator dt/oe soe sc we cas ras ai write mask control we clock generator cas clock generator ras clock generator x address buffer y address buffer refresh address counter ras cas i/o buffer y decoder 64 k memory array pointer 256 data register si/o buffer i/o buffer y decoder 64 k memory array pointer 256 data register si/o buffer i/o buffer y decoder 64 k memory array pointer 256 data register si/o buffer hm53461 series 4 hm53461, hm53462 series hm53461, hm53462 series block diagram (cont) absolute maximum ratings voltage on any pin relative to v ss : ? v to +7 v power supply voltage relative to v ss : ?.5 v to +7 v operating temperature, ta (ambient): 0? to +70? storage temperature: ?5? to +125? short circuit output current: 50 ma power dissipation: 1 w recommended dc operating conditions (ta = 0 to +70?) *1 parameter symbol min typ max unit supply voltage v cc 4.5 5.0 5.5 v input high voltage v ih 2.2 6.0 v input low voltage v il ?.5 *2 0.8 v notes: 1. all voltages refernced to v ss . 2. ?.0 v for pulse wideth 10 ns. mask register we 2 3 4 logic operation unit dout 1 2 3 4 memory array 256 256 din dout dt sc si/o1 si/o1 2 3 4 by-4 mode 256 4 (normal mode) by-1 mode (1024 4) other si/o (2e4) are in high-z state p s din 1 1 of 256 selector 256 bit data register data transfer control hm53462 series 5 hm53461, hm53462 series hm53461, hm53462 series dc characteristics (ta = 0 to +70?, v cc = 5 v 10%, v ss = 0 v) sam port hm53461-10 hm53461-12 hm53461-15 ram port symbol standby active hm53462-10 hm53462-12 hm53462-15 unit i cc1 o x 70 60 50 ma i cc7 x o 110 100 80 ma i cc2 ox7 7 7 ma i cc8 x o 40 40 30 ma i cc3 o x 60 50 40 ma i cc9 x o 100 90 70 ma i cc4 o x 50 40 35 ma i cc10 x o 90 80 65 ma i cc5 o x 60 50 40 ma i cc11 x o 100 90 70 ma i cc6 o x 75 65 55 ma i cc12 x o 115 105 85 ma parameter symbol min max unit input leakage i li ?0 10 a output leakage i lo ?0 10 a output high voltage i oh = ? ma v oh 2.4 v output low voltage i ol = 4.2 ma v ol 0.4 v data transfer current ras , cas cycling t rc = min. cbr refresh current ras cycling t rc = min. page mode current ras = v il , cas cycling, t pc = min. ras only refresh current, cas = v ih , ras cycling, t rc = min. standby current ras , cas = v ih operating current ras, cas cycling t rc = min. 6 hm53461, hm53462 series hm53461, hm53462 series input/output capacitance parameter symbol typ max unit address ci 1 ? pf clocks ci 2 ? pf i/o, si/o c i/o ? pf electrical characteristics and recommended ac operating conditions (ta = 0 to +70?, v cc = 5 v 10%, v ss = 0 v) *1, 10, 11 hm53461-10 hm53461-12 hm53461-15 hm53462-10 hm53462-12 hm53462-15 parameter symbol min max min max min max unit note random read or t rc 190 220 260 ns write cycle time read-modify-write t rwc 260 300 355 ns cycle time page mode cycle time t pc 70 85 105 ns access time from ras t rac 100 120 150 ns 2, 3 access time from cas t cac 50 60 75 ns 3, 4 output buffer turn off t off1 25 30 40ns5 delay referenced to cas transition time (rise and fall) t t 350350 350ns6 ras precharge time t rp 80 90 100 ns ras pulse width t ras 100 10000 120 10000 150 10000 ns cas pulse width t cas 50 10000 60 10000 75 10000 ns ras to cas delay time t rcd 25 50 25 60 30 75 ns 7 ras hold time t rsh 50 60 75 ns cas hold time t csh 100 120 150 ns cas to ras t crp 10 10 10 ns precharge time 7 hm53461, hm53462 series hm53461, hm53462 series electrical characteristics and recommended ac operating conditions (ta = 0 to +70?, v cc = 5 v 10%, v ss = 0 v) *1, 10, 11 (cont) hm53461-10 hm53461-12 hm53461-15 hm53462-10 hm53462-12 hm53462-15 parameter symbol min max min max min max unit note row address setup time t asr 0 0 0 ns row address hold time t rah 15 15 20 ns column address setup time t asc 00 0 ns column address hold time t cah 20 20 25 ns write command setup time t wcs 0 0 0 ns 8 write command hold time t wch 25 25 30 ns write command pulse width t wp 15 20 25 ns write command to t rwl 35 40 45 ns ras lead time write command to t cwl 35 40 45 ns cas lead time data-in setup time t ds 0 0 0 ns 9 data-in hold time t dh 25 25 30 ns 8, 9 read command setup time t rcs 0 0 0 ns read command hold time t rch 0 0 0 ns read command hold time t rrh 10 10 10 ns referenced to ras refresh period t ref ? 4 4 ns ras pulse width t rws 170 10000 200 10000 245 10000 ns (read-modify-write cycle) cas to we delay t cwd 85 100 125 ns 8 cas setup time t csr 10 10 10 ns ( cas -before- ras refresh) cas hold time t chr 20 25 30 ns ( cas -before- ras refresh) 8 hm53461, hm53462 series hm53461, hm53462 series electrical characteristics and recommended ac operating conditions (ta = 0 to +70?, v cc = 5 v 10%, v ss = 0 v) *1, 10, 11 (cont) hm53461-10 hm53461-12 hm53461-15 hm53462-10 hm53462-12 hm53462-15 parameter symbol min max min max min max unit note ras precharge to t rpc 10 10 10 ns cas hold time cas precharge time t cp 10 15 20 ns access time from oe t oac 30 35 40ns output buffer turn-off t off2 25 30 40ns delay referenced to oe oe to data-in delay time t odd 25 30 40 ns oe hold time referenced t oeh 10 15 20 ns to we data-in to cas delay time t dzc 0 0 0 ns data-in to oe delay time t dzo 0 0 0 ns oe to ras delay time t ord 35 40 45 ns serial clock cycle time t scc 40 40 60 ns access time from sc t sca 40 40 60ns10 access time from soe t sea 25 30 40ns10 sc pulse width t sc 10 10 10 ns sc precharge width t scp 10 10 10 ns serial data-out hold t soh 10 10 10 ns time after sc high serial output buffer turn t sez 25 25 30ns off delay from soe serial data-in setup time t sis 0 0 0 ns serial data-in hold time t sih 15 20 25 ns dt to ras setup tune t dts 0 0 0 ns dt to ras hold time t rdh 80 90 110 ns (read transfer cycle) 9 hm53461, hm53462 series hm53461, hm53462 series electrical characteristics and recommended ac operating conditions (ta = 0 to +70?, v cc = 5 v 10%, v ss = 0 v) *1, 10, 11 (cont) hm53461-10 hm53461-12 hm53461-15 hm53462-10 hm53462-12 hm53462-15 parameter symbol min max min max min max unit note dt to ras hold time t dth 15 15 20 ns dt to cas hold time t cdh 20 30 45 ns last sc to dt delay time t sdd 5 5 10 ns first sc to dt hold time t sdh 25 25 30 ns dt to ras delay time t dtr 10 10 10 ns we to ras setup time t ws 0 0 0 ns we to ras hold time t wh 15 15 20 ns i/o to ras setup time t ms 0 0 0 ns i/o to ras hold time t mh 15 15 20 ns serial output buffer turn t srz 10 50 10 60 10 75 ns off delay from ras sc to ras setup time t srs 30 40 45 ns ras to sc delay time t srd 25 30 35 ns serial data input delay t sid 50 60 75 ns time from ras serial data input to t szd 0 0 0 ns dt delay time soe to ras setup time t es 0 0 0 ns soe to ras hold time t eh 15 15 20 ns serial write enable t sws 0 0 0 ns setup time serial write enable t swh 35 35 55 ns hold time serial write disable t swis 0 0 0 ns setup time electrical characteristics and recommended ac operating conditions (ta = 0 to +70?, v cc = 5 v 10%, v ss = 0 v) *1, 10, 11 (cont) hm53461-10 hm53461-12 hm53461-15 hm53462-10 hm53462-12 hm53462-15 parameter symbol min max min max min max unit note serial write disable t swih 35 35 55 ns hold time dt to sout in low-z t dlz 5 10 10 ns delay time notes: 1. ac measurements assume t t = 5 ns. 2. assumes that t rcd t rcd (max). if t rcd is greater than the maximum recommended value shown in this table, t rac exceeds the value shown. 3. measured with a load circuit equivalent to two ttl loads and 100 pf. 4. assumes that t rcd 3 t rcd (max). 5. t off (max) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 6. v ih (min) and v il (max) are reference levels for measuring the timing of input signals. also, transition times are measured between v ih and v il . 7. operation with the t rcd (max) limit ensures that t rac (max) can be met. t rcd (max) is specified as a reference point only. if t rcd is greater than the specified t rcd (max) limit, then access time is controlled exclusively by t cac . 8. t wcs and t cwd are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only if t wcs 3 t wcs (min), the cycle is an early write cycle, and the data out pin will remain open circuit (high impedance) throughout the entire cycle. if t cwd 3 t cwd (min), the cycle is a read/write and the data output will contain data read from the selected cell. if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 9. these parameters are referenced to cas leading edge in early write cycle and to we leading edge in delayed write or read-modify-write cycles. 10. measured with a load circuit equivalent to two ttl and 50 pf. 11. an initial pause of 100 s is required after power-up. then execute at least eight initialization cycles (hm53461 series). after power-up, pause for more than 100 s and execute at least 8 initialization cycles. then execute at least one logic reset cycle including write mask reset (on the falling edge of ras , we = low and i/o1?/o4 = high and execute one or more transport cycles for initiation of the sam port (hm53462 series). 12. after a read transfer cycle, the first sam must be read out before the cas falling edge in the succeeding read transfer cycle. when sam is not read out after a read transfer cycle or when sam read out is not used as valid data, the restriction mentioned above is not required. 10 hm53461, hm53462 series hm53461, hm53462 series 11 hm53461, hm53462 series hm53461, hm53462 series timing waveforms read cycle t ras t rc t rcd t rsh t csh t crp t rp t cas row t rah t asr t asc t cah t rrh t rcs t rch t cac t off1 t rac t dzc t oac t ord t dth t off2 t dts t dzo ras cas address we dt/oe i/o (output) i/o (input) do not care column valid dout 12 hm53461, hm53462 series hm53461, hm53462 series early write cycle t ras t rc t rcd t rsh t csh t crp t rp t cas ras cas row column address t rah t asc t cah t asr * we t wh t wcs t wch t ws t wp * valid din i/o (input) t mh t ds t dh t ms high z t dth t dts i/o (output) dt/oe do not care note: when we is high, all the data on the i/o can be written into the cell. when we is low, the data on the i/o are not written except when i/o is high at the falling edge of ras . 13 hm53461, hm53462 series hm53461, hm53462 series delayed write cycle t ras t rc t rp t rcd t rsh t crp t cas t csh t asr t asc t rah t ws t wp t wch t cah t rwl t cwl t wh t dts t mh t ms t ds t dh valid din note high-z ras cas address we dt/oe i/o (output) i/o (input) do not care row column t oeh note note: when we is high, all the data on i/o1ei/o4 can be written into the memory cell. when we is low, the data on i/os are not written except when i/o = high at the falling edge of ras . 14 hm53461, hm53462 series hm53461, hm53462 series read modify write cycle do not care t rws t rwc t rp t csh t cas t crp t rcd t crp t asr t rah t rsh t cah t asc row column t wh t ws t rcs t cwl t rwl t wp t cwd t ms t dzc t dh t rac t cac t dzo t oeh t oac t dts ras cas address we dt/oe i/o (output) i/o (input) valid din t dth t off2 t mh valid dout note note t ds t odd note: when we is high, all the data on i/o1ei/o4 can be written into the memory cell. when we is low, the data on i/os are not written except when i/o = high at the falling edge of ras . 15 hm53461, hm53462 series hm53461, hm53462 series page mode read cycle t dts t ras t rc t rp t rsh t pc t csh t cas t crp t cas t cas t cp t rah t asr t cah t asc t cah t asc t cah t rrh t rch t rch t rch t rcs t rac t cac t off1 t cac t off1 t cac t off1 valid dout t dzc t dzc t dzc t off2 t dzo t oac t off2 t oac t dzo do not care ras cas address we dt/oe i/o (output) i/o (input) t rcd t asc t rcs t rcs valid dout t dth t dzo t oac t off2 row col- umn col- umn col- umn valid dout 16 hm53461, hm53462 series hm53461, hm53462 series page mode write cycle (early write) t ras t rc t rp t csh t pc t rsh t rcd t cas t cp t cas t cas t asr t rah t asc t cah t asc t cah t asc t cah t ws t wh t wcs t wch t wcs t wch t wcs t wch t ms t wp t mh t dh t ds t wp t ds t dh t wp t ds t dh valid din valid din high-z t dth t dts do not care ras cas address we dt/oe i/o (output) i/o (input) row note note valid din col- umn col- umn col- umn note: when we is high, all the data on i/o1ei/o4 can be written into the memory cell. when we is low, the data on i/os are not written except when i/o = high at the falling edge of ras . t crp 17 hm53461, hm53462 series hm53461, hm53462 series page mode write cycle (delayed write) t ras t rc t csh t rsh t rp t rcd t cas t pc t cas t cas t crp t cp t cah t asc t rah t cah t ws t wh t cwl t wp t cwl t wp t rwl t cwl t cah t wp column t ms t mh t ds t dh t dh t ds t ds t dh high-z t oeh t dts ras cas address we dt/oe i/o (input) i/o (output) do not care t ash t asc row col- umn col- umn t asc note note valid din valid din valid din note: when we is high, all the data on i/o1ei/o4 can be written into the memory cell. when we is low, the data on i/os are not written except when i/o = high at the falling edge of ras . 18 hm53461, hm53462 series hm53461, hm53462 series ras-only refresh cycle t crp t ras t rc t rp t rpc t asr t rah row t off1 t dts t dth do not care ras cas address dt/oe i/o (output) i/o (input) 19 hm53461, hm53462 series hm53461, hm53462 series cas-before-ras refresh cycle (hm53461 series) t rp t rc t ras t rp t rpc t csr t chr t crp do not care ras cas address we dt/oe i/o (input) i/o (output) high-z 20 hm53461, hm53462 series hm53461, hm53462 series cas-before-ras refresh (hm53462 series) t rp t rc t ras t rp t rpc t csr t chr t crp t ws t wh high-z do not care ras cas address we dt/oe i/o (input) i/o (output) 21 hm53461, hm53462 series hm53461, hm53462 series hidden refresh cycle (hm53461 series) t ras t rc t rp t rp t rc t rsh t ras t rcd t crp t chr t crp t rah t asc t asr t cah t rcs t rrh t ord t off1 valid dout t rac t cac t oac t dth t dts t off2 high-z t dzo t dzc do not care ras cas address we dt/oe i/o (output) i/o (input) row column 22 hm53461, hm53462 series hm53461, hm53462 series hidden refresh cycle (hm53462 series) t ras t rc t rp t rp t rc t rsh t ras t rcd t crp t chr t crp t rah t asc t asr t cah t rsc t rrh t ord t off1 valid dout t rac t cac t oac t dth t dts t off2 high-z t dzo t dzc do not care ras cas address we dt/oe i/o (output) i/o (input) t wh t ws row column 23 hm53461, hm53462 series hm53461, hm53462 series read transfer cycle (1) *1, 2 t ras t rc t rp t rsh t rcd t crp t cas t cah sam start add t asc t asr t rah *3 row t csh t wh t ws t dtr high-z t cdh t sdh t dth t rdh t dts t sdd t scc t scp t sc t soh t sca high-z new row previous row do not care ras cas address we dt/oe i/o (output) i/o (input) sc si/o (input) si/o (output) valid sout valid sout valid sout valid sout notes: 1. in the case that the previous data transfer cycle was read transfer. 2. assume that soe is low. 3. cas and sam start address need not be supplied every cycle, only when it is desired to change to a new sam start address. 24 hm53461, hm53462 series hm53461, hm53462 series read transfer cycle (2) *1, 2 t ras t rc t rp t rsh t rcd t crp t cas t cah sam start add t asc t asr t rah *3 row t csh t wh t ws t dtr high-z t cdh t dth t rdh t dts t sc t scp t scc t sca t soh t sc t sih t sis t szd valid sout valid sin do not care inhibit rising transient ras cas address we dt/oe i/o (output) i/o (input) sc si/o (input) si/o (output) t srs t sdh t dlz notes: 1. in the case that the previous data transfer cycle was write transfer or pseudo transfer. 2. assume that soe is low. 3. cas and sam start address need not be supplied every cycle, only when it is desired to change to a new sam start address. 25 hm53461, hm53462 series hm53461, hm53462 series psuedo transfer cycle t rp t rc t ras t rcd t rsh t crp t cas t rah * t asc t asr row t cah sam start add t csh t ws t wh t dts t dth t eh t es t srd t scp t scc t sc t sih t sis t srs t sid valid sin t srz t soh do not care inhibit rising transient ras cas address we dt/oe si/o (output) si/o (input) soe sc t sc note: cas and sam start address need not be supplied every cycle, only when it is desired to change to a new sam start address. 26 hm53461, hm53462 series hm53461, hm53462 series write transfer cycle t rp t rc t ras t rcd t rsh t crp t cas t rah * t asc t asr row t cah sam start add t ws t wh t dts t dth t srd t scp t scc t sc t sih t sis t sc valid sin do not care inhibit rising transient t es t eh t srs t sih t sis valid sin valid sin high-z ras cas address we dt/oe si/o (output) si/o (input) soe sc t csh note: cas and sam start address need not be supplied every cycle, only when it is desired to change to a new sam start address. 27 hm53461, hm53462 series hm53461, hm53462 series serial read cycle serial write cycle t ras t dth t dts t sc t sc t scc t scc t scc t scp t scp t scp t sea t soh t sca t sca t sca t sez t sc valid sout valid sout valid sout do not care ras sc dt/oe si/o (output) soe t ras t dth t dts t scc t scc t scc t scp t scp t scp t sih t sis t sis t sih do not care ras sc dt/oe si/o (output) soe t sws t swih t swh t swis t sc t sc t sc t sc valid sout valid sout 28 hm53461, hm53462 series hm53461, hm53462 series ac characteristics (logic operation mode) (hm53462 series) parameter symbol min max min max min max unit write cycle time t frc 230 265 310 ns ras pulse width in write cycle t rfs 140 10000 165 10000 200 10000 ns cas pulse width in write cycle t cfs 80 10000 95 10000 105 10000 ns cas hold time in write cycle t fcsh 140 165 200 ns ras hold time in write cycle t frsh 80 95 105 ns page mode cycle time (write cycle) t fpc 100 120 135 ns cas hold time t fchr 90 100 120 ns (logic operation set/reset cycle) cas hold time from ras precharge t psch 10 10 10 ns (x4 to x1 set cycle) logic code (fc0?c3 are ax0?x3 in logic operation set cycle) (hm53462 series) logic fc3 fc2 fc1 fc0 symbol write data description 0000 0 zero 0001 and1 di mi 0010 and2 di mi 0011 x4 to x1 sam organization changes to 1024 1 0100 and3 di mi 0101 through di logic operation mode reset 0110 eor di mi + di mi 0111 or1 di + mi 1000 nor di mi 1001 enor di mi + di mi 1010 inv1 di 1011 or2 di + mi 1100 inv2 mi 1101 or3 di + mi 1110 nand di + mi di = external data-in 1111 1 one mi = the data of the memory cell 29 hm53461, hm53462 series hm53461, hm53462 series logic operation set/reset cycle (with cas before ras refresh) (hm53462 series) t dh t ds t wh t ws t rah t asr t fchr t csr t rpc t ras t rp t psch ras cas address we dt/oe i/o (output) i/o (input) do not care t crp high-z *2 *1 t rp t rc notes: 1. logic code a0?3 (a4?7: don't care) 2. write mask data 30 hm53461, hm53462 series hm53461, hm53462 series logic operation mode early write cycle (hm53462 series) t rfs t frc t rcd t frsh t fcsh t crp t rp t cfs ras cas row address t rah t asc t cah t asr we t wh t wcs t wch t ws t wp * valid din i/o (input) t mh t ds t dh t ms high-z t dth t dts i/o (output) dt/oe do not care column * note: when we is high, all data on the i/o can be written into the cell. when we is low, the data on the i/o are not written except when i/o is high at the falling edge of ras . 31 hm53461, hm53462 series hm53461, hm53462 series delayed write cycle (hm53462 series) t rfs t frc t rp t rcd t frsh t crp t cfs t fcsh t asr t asc t rah t ws t wp t wch t cah t rwl t cwl t wh t mh t ms t ds t dh valid din * high-z ras cas address we dt/oe i/o (output) i/o (input) do not care row column t oeh t dts * note: when we is high, all data on i/o1ei/o4 can be written into the memory cell. when we is low, the data on the i/o are not written except when i/o is high at the falling edge of ras . 32 hm53461, hm53462 series hm53461, hm53462 series page mode write cycle (delayed write) (hm53462 series) t rfs t frc t fcsh t frsh t rp t rcd t cfs t fpc t cfs t cfs t crp t cp t cah t asc t rah t cah t ws t wh t cwl t wp t cwl t wp t rwl t cwl t cah t wp column t ms t mh t ds t dh t dh t ds t ds t dh high-z t oeh t dts ras cas address we dt/oe i/o (input) i/o (output) do not care t asr row col- umn t asc * * valid din valid din valid din column t asc note: when we is high all data on the i/o can be written into the cell. when we is low, the data on the i/o are not written except when i/o is high at the falling edge of ras . 33 hm53461, hm53462 series hm53461, hm53462 series page mode write cycle (early write) (hm53462 series) t rfs t frc t rp t fcsh t fpc t frsh t rcd t cfs t cp t cfs t cfs t asr t rah t asr t cah t asc t cah t asc t cah t ws t wh t wcs t wch t wcs t wch t wcs t wch t ms t wp t mh t dh t ds t wp t ds t dh t wp t ds t dh valid din valid din high-z t dth t dts do not care ras cas address we dt/oe i/o (output) i/o (input) t crp row column * * valid din column note: when we is high, all data on the i/o can be written into the cell. when we is low, the data on the i/o are not written except when i/o is high at the falling edge of ras . 34 hm53461, hm53462 series hm53461, hm53462 series hm53462 series description logic operation mode hm53462 has an internal logic operation unit which makes a process of graphics simple. the logic is determined in the logic operation set/reset cycle, and the operation is executed in every write cycle succeeding to the logic operation set/reset cycle. in this mode the internal read-modify-write operation is executed and the cell data is converted into the new data given by the logic operation between din and the old cell data. logic operation set/reset cycle a logic operation set/reset cycle is performed by bringing cas and we low when ras falls (figure 1). the logic code and the bits to be masked are determined respectively by a 0? 3 state and i/01?/04 state at the falling edge of ras . furthermore, in this cycle the cas -before- ras refresh operation is executed also. in the case of executing the conventional cas -before- ras refresh operation, we must be high when ras falls. logic code: the logic code is shown in the following logic code table. when power is turned on, at least one logic reset cycle including write mask reset is required to initialize logic code. if the logic code is (a 3, a 2, a 1, a 0) = (0, 0, 1, 1), the sam organization is changed converter (figure 2). in the case that the sam organization is changed to 1,024 1, one data transfer cycle is needed to initialize the sam selector. once the sam organization is changed to 1024 1, this code is maintained unless power is turned off. write mask: hm53462 has two kinds of mask registers (register 1, 2). register 1 is set by bringing we low at the falling edge of ras during the write cycle, and the mask data is available only in this cycle. register 2 is set by level of i/o in the logic operation set/reset cycle, and the mask data is available until the next logic operation set/reset cycle. if register 1 is set during the current logic operation mode, the mask data of the register is preferred (that of register 2 is ignored) and the logic becomes ?hrough?only in this cycle (figure 3). 35 hm53461, hm53462 series hm53461, hm53462 series figure 1 logic operation set/reset cycle logic code (fc0?c3 are ax0?x3 in logic operation set cycle) logic fc3 fc2 fc1 fc0 symbol write data description 0000 0 zero 0001 and1 di mi 0010 and2 di mi 0011 x4 to x1 sam organization changes to 1024 1 0100 and3 di mi 0101 through di logic operation mode reset 0110 eor di mi + di mi 0111 or1 di + mi 1000 nor di mi 1001 enor di mi + di mi 1010 inv1 di 1011 or2 di + mi do not care ras cas address we dt/oe i/o l l fc0?c3 mask register 2 36 hm53461, hm53462 series hm53461, hm53462 series logic code (fc0?c3 are ax0?x3 in logic operation set cycle) (cont) logic fc3 fc2 fc1 fc0 symbol write data description 1100 inv2 mi 1101 or3 di + mi 1110 nand di + mi di = external data-in 1111 1 one mi = the data of the memory cell figure 2 shift method of sam data by-4 mode (sam organization: 256 4) si/o1 si/o2 si/o3 si/o4 a b c d e f g h i + 1 serial i/o sam data register t scc sc si/o1 si/o2 si/o3 si/o4 a b c d e f g h 37 hm53461, hm53462 series hm53461, hm53462 series by-1 mode (sam organization: 1024 1) figure 3 example of logic operation mode ras cas we i/o1 i/o2 i/o3 i/o4 logic l l logic operation set reset cycle write cycle write cycle write cycle write cycle h h h l h h h h 0 write masked masked 1 write and1 masked 1 write 0 write masked through masked masked 1 write 0 write 1 write masked masked 0 write and1 and1 mask register 2 is set i/o2, i/o3: masked. assume that the logic is set to and1. mask register 1 is set and valid only in this cycle. i/o1, i/o4: masked. t scc sc si/o1 si/o2 si/o3 si/o4 abcde high-z high-z high-z |
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