k6x4016t3f family cmos sram revision 2.0 march 2005 1 document title 256kx16 bit low power and low voltage cmos static ram revision history revision no 0.0 0.1 1.0 2.0 remark preliminary preliminary final final history initial draft revised - added commercial product - deleted 44-tsop2-400r package type. - added 55ns product(@ 3.0v~3.6v) finalized - changed i cc (operating power supply current) from 4ma to 2ma - changed i cc 1(average operating current) from 4ma to 3ma - changed i cc 2(average operating current) from 40ma to 25ma - changed i sb 1(standby current(cmos), commercial) from 15 a to 10 a - changed i sb 1(standby current(cmos), industrial) from 20 a to 10 a - changed i sb 1(standby current(cmos), automotive) from 30 a to 20 a - changed i dr (data retention current, commercial) from 15 a to 10 a - changed i dr (data retention current, industrial) from 20 a to 10 a - changed i dr (data retention current, automotive) from 30 a to 20 a revised - changed i sb 1 of automotive product from 20 a to 30 a - changed i dr of automotive product from 20 a to 30 a - added lead free products draft date july 29, 2002 december 2, 2002 august 8, 2003 march 27, 2005 the attached datasheets are provided by samsung electronics. sa msung electronics co., ltd. reserve the right to change the spec ifications and products. samsung electronics will answer to your questions about device. if you have any questions, please contact the samsung branch offices.
k6x4016t3f family cmos sram revision 2.0 march 2005 2 256kx16 bit low power and low voltage cmos static ram general description the k6x4016t3f families are fabricated by samsung s advanced cmos process techno logy. the families support var- ious operating temperature range and have 44-tsop2 pack- age type for user flexibility of s ystem design. the families also support low data retention voltage for battery back-up operation with low data retention current. features ? process technology: full cmos ? organization: 256k x16 ? power supply voltage: 2.7~3.6v ? low data retention voltage: 2v(min) ? three state outputs ? package type: 44-tsop2-400f pin description name function name function cs chip select input vcc power oe output enable input vss ground we write enable input lb lower byte (i/o 1~8 ) a 0 ~a 17 address inputs ub upper byte (i/o 9~16 ) i/o 1 ~i/o 16 data input/output nc no connection product family 1. this parameter is measured with 30pf test load (vcc=3.0~3.6v). 2. the parameter is measured with 30pf test load. product family operating temperature vcc range speed(ns) power dissipation pkg type standby (i sb1 , max) operating (i cc2 , max) k6x4016t3f-b commercial(0~70 c) 2.7~3.6v 55 1) /70 2) /85ns 10 a 25ma 44-tsop2-400f k6x4016t3f-f industrial(-40~85 c) 10 a k6x4016t3f-q automotive(-40~125 c) 70 2) /85ns 30 a a4 a3 a2 a1 a0 cs i/oi i/o2 i/o3 i/o4 vcc vss i/o5 i/o6 i/o7 i/o8 we a17 a16 a15 a14 a5 a6 a7 oe ub lb i/o16 i/o15 i/o14 i/o13 vss vcc i/o12 i/o11 i/o10 i/o9 nc a8 a9 a10 44-tsop2 forward 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 a13 a12 a11 samsung electronics co., ltd. reserves the right to change products and specifications without notice. functional block diagram clk gen. row select we oe ub cs i/o 1 ~i/o 8 data cont data cont data cont lb i/o 9 ~i/o 16 vcc vss precharge circuit. memory array i/o circuit column select control logic row addresses column addresses
k6x4016t3f family cmos sram revision 2.0 march 2005 3 product list 1. operating voltage range is 3.0~3.6v 2. lf : lead free product commercial products(0~70 c) industrial products(-40~85 c) automotive products(-40~125 c) part name function part name function part name function k6x4016t3f-tb55 1) k6x4016t3f-tb70 k6x4016t3f-tb85 k6x4016t3f-ub55 1) k6x4016t3f-ub70 k6x4016t3f-ub85 44-tsop2-f, 55ns, ll 44-tsop2-f, 70ns, ll 44-tsop2-f, 85ns, ll 44-tsop2-f, 55ns, ll, lf 44-tsop2-f, 70ns, ll, lf 44-tsop2-f, 85ns, ll, lf k6x4016t3f-tf55 1) k6x4016t3f-tf70 k6x4016t3f-tf85 k6x4016t3f-uf55 1) k6x4016t3f-uf70 k6x4016t3f-uf85 44-tsop2-f, 55ns, ll 44-tsop2-f, 70ns, ll 44-tsop2-f, 85ns, ll 44-tsop2-f, 55ns, ll, lf 44-tsop2-f, 70ns, ll, lf 44-tsop2-f, 85ns, ll, lf k6x4016t3f-tq70 k6x4016t3f-tq85 k6x4016t3f-uq70 k6x4016t3f-uq85 44-tsop2-f, 70ns, l 44-tsop2-f, 85ns, l 44-tsop2-f, 70ns, l, lf 44-tsop2-f, 85ns, l, lf absolute maximum ratings 1) 1. stresses greater than those listed under "absolute maximum rati ngs" may cause permanent damage to the device. functional ope ration should be restricted to recommended operating condition. exposure to absolut e maximum rating conditions for extended periods may affect reliability. item symbol ratings unit remark voltage on any pin relative to vss v in ,v out -0.2 to v cc +0.3(max. 3.9v) v - voltage on vcc supply relative to vss v cc -0.2 to 3.9 v - power dissipation p d 1.0 w - storage temperature t stg -65 to 150 c- operating temperature t a 0 to 70 c k6x4016t3f-b -40 to 85 k6x4016t3f-f -40 to 125 k6x4016t3f-q functional description 1. x means don t care. (must be in low or high state) cs oe we lb ub i/o 1~8 i/o 9~16 mode power h x 1) x 1) x 1) x 1) high-z high-z deselected standby lhh x 1) x 1) high-z high-z output disabled active l x 1) x 1) h h high-z high-z output disabled active l l h l h dout high-z lower byte read active l l h h l high-z dout upper byte read active l l h l l dout dout word read active l x 1) l l h din high-z lower byte write active l x 1) l h l high-z din upper byte write active l x 1) l l l din din word write active
k6x4016t3f family cmos sram revision 2.0 march 2005 4 recommended dc operating conditions 1) note: 1. commercial product: t a =0 to 70 c, otherwise specified. industrial product: t a =-40 to 85 c, otherwise specified. automotive product: t a =-40 to 125 c, otherwise specified. 2. overshoot: v cc +2.0v in case of pulse width 30ns. 3. undershoot: -2.0v in case of pulse width 30ns. 4. overshoot and undershoot are sampled, not 100% tested. item symbol min typ max unit supply voltage vcc 2.7 3.0 / 3.3 3.6 v ground vss 0 0 0 v input high voltage v ih 2.2 - vcc+0.2 2) v input low voltage v il -0.2 3) -0.6v capacitance 1) (f=1mhz, t a =25 c) 1. capacitance is sampled, not 100% tested item symbol test condition min max unit input capacitance c in v in =0v - 8 pf input/output capacitance c io v io =0v - 10 pf dc and operating characteristics item symbol test conditions min typ max unit input leakage current i li v il =vss to vcc -1 - 1 a output leakage current i lo cs =v ih or oe =v ih or we =v il v io =vss to vcc -1 - 1 a operating power supply current i cc i io =0ma, cs =v il , v in =v il or v ih , read - - 2 ma average operating current i cc1 cycle time=1 s, 100% duty, i io =0ma cs 0.2v, v in 0.2v or v in vcc-0.2v --3ma i cc2 cycle time=min 2) , 100% duty, i io =0ma, cs =v il, v in =v ih or v il --25ma output low voltage v ol i ol =2.1ma - - 0.4 v output high voltage v oh i oh =-1.0ma 2.4 - - v standby current(ttl) i sb cs =v ih , other inputs=v il or v ih --0.3ma standby current(cmos) i sb1 cs vcc-0.2v, other inputs=0~vcc k6x4016t3f-b - -10 a k6x4016t3f-f - -10 a k6x4016t3f-q - - 30 a
k6x4016t3f family cmos sram revision 2.0 march 2005 5 c l 1 ) 1.including scope and jig capacitance ac operating conditions test conditions ( test load and input/output reference) input pulse level: 0.4 to 2.2v input rising and falling time: 5ns input and output reference voltage: 1.5v output load(see right): c l =100pf+1ttl c l =30pf+1ttl data retention characteristics item symbol test condition min typ max unit vcc for data retention v dr cs vcc-0.2v 2.0 - 3.6 v data retention current i dr vcc=3.0v, cs vcc-0.2v k6x4016t3f-b -- 10 a k6x4016t3f-f 10 a k6x4016t3f-q 30 a data retention set-up time t sdr see data retention waveform 0- - ms recovery time t rdr 5- - ac characteristics ( v cc =2.7~3.6v, commercial product: t a =0 to 70 c, industrial product: t a =-40 to 85 c, automotive product: t a =-40 to 125 c ) 1. voltage range is 3.0v~3.6v for commercial and industrial product. parameter list symbol speed bins units 55ns 1 ) 70ns 85ns min max min max min max read read cycle time t rc 55 - 70 - 85 - ns address access time t aa -55-70-85ns chip select to output t co -55-70-85ns output enable to valid output t oe -25-35-40ns lb , ub valid to data output t ba -25-35-40ns chip select to low-z output t lz 10 - 10 - 10 - ns output enable to low-z output t olz 5-5-5-ns lb , ub enable to low-z output t blz 5-5-5-ns output hold from address change t oh 10 - 10 - 10 - ns chip disable to high-z output t hz 020025025ns oe disable to high-z output t ohz 020025025ns lb , ub disable to high-z output t bhz 020025025ns write write cycle time t wc 55 - 70 - 85 - ns chip select to end of write t cw 45 - 60 - 70 - ns address set-up time t as 0-0-0-ns address valid to end of write t aw 45 - 60 - 70 - ns write pulse width t wp 40 - 55 - 60 - ns write recovery time t wr 0-0-0-ns write to output high-z t whz 020025025ns data to write time overlap t dw 25 - 30 - 35 - ns data hold from write time t dh 0-0-0-ns end write to output low-z t ow 5-5-5-ns lb , ub valid to end of write t bw 45 - 60 - 70 - ns
k6x4016t3f family cmos sram revision 2.0 march 2005 6 address data out previous data valid data valid timing diagrams timing waveform of read cycle(1) (address controlled , cs =oe =v il , we =v ih , ub or/and lb =v il ) timing waveform of read cycle(2) (we =v ih ) data valid high-z t rc cs address ub , lb oe data out t aa t rc t oh t oh t aa t co t ba t oe t olz t blz t lz t ohz t bhz t hz notes (read cycle) 1. t hz and t ohz are defined as the time at which the outputs achieve the o pen circuit conditions and are not referenced to output voltage levels. 2. at any given temperature and voltage condition, t hz (max.) is less than t lz (min.) both for a given devic e and from device to device interconnection.
k6x4016t3f family cmos sram revision 2.0 march 2005 7 timing waveform of write cycle(2) (cs controlled) address cs data valid ub , lb we data in data out high-z high-z t wc t cw(2) t aw t bw t wp(1) t dh t dw t wr(4) t as(3) timing waveform of write cycle(1) (we controlled) address cs data undefined ub , lb we data in data out t wc t cw(2) t wr(4) t aw t bw t wp(1) t as(3) t dh t dw t whz t ow high-z high-z data valid
k6x4016t3f family cmos sram revision 2.0 march 2005 8 address cs data valid ub , lb we data in data out high-z high-z timing waveform of write cycle(3) (ub , lb controlled) notes (write cycle) 1. a wri t e occurs during the overlap(t wp ) of low cs and low we . a write begins when cs goes low and we goes low with asserting ub or lb for single byte operation or simultaneously asserting ub and lb for double byte operation. a write ends at the earliest transition when cs goes high and we goes high. the t wp is measured from the beginning of write to the end of write. 2. t cw is measured from the cs going low to the end of write. 3. t as is measured from the address valid to the beginning of write. 4. t wr is measured from the end of write to the address change. t wr is applied in case a write ends with cs or we going high. t wc t cw(2) t bw t wp(1) t dh t dw t wr(4) t aw data retention wave form cs controlled v cc 2.7v 2.2v v dr cs gnd data retention mode cs v cc - 0.2v t sdr t rdr t as(3)
k6x4016t3f family cmos sram revision 2.0 march 2005 9 unit: millimeter(inch) package dimensions 44 pin thin small outline package type ii (400f) 0.002 #1 0.05 #22 #44 #23 0.35 0.10 0.014 0.004 0.80 0.0315 min. 0.047 1.20 max. 0.741 18.81 max. 18.41 0.10 0.725 0.004 11.76 0.20 0.463 0.008 + 0 . 1 0 - 0 . 0 5 0.50 + 0 . 0 0 4 - 0 . 0 0 2 0 . 1 5 0 . 0 0 6 0.020 10.16 0.400 0.10 0.004 0~8 0.45 ~0.75 0.018 ~ 0.030 0.25 ( ) 0.010 ( ) 0.805 0.032 ( ) max 1.00 0.10 0.039 0.004
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