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[ak4645a] ms0986-e-00 2008/07 - 1 - general description the ak4645a is a stereo codec with a built-i n microphone-amplifier and headphone-amplifier. the ak4645a features analog mixi ng circuit that allows easy interf acing in mobile phone and portable a/v player designs. the ak4645a is available in a 32pin qfn (4mm x 4mm), utilizing less board space than competitive offerings. features 1. recording function ? 4 stereo input selector ? stereo mic input (full-di fferential or single-ended) ? stereo line input ? mic amplifier (+32db/+26db/+20db or 0db) ? digital alc (automatic level control) (+36db ? 54db, 0.375db step, mute) ? adc performance: s/(n+d): 83db, dr, s/n: 86db (mic-amp=+20db) s/(n+d): 88db, dr, s/n: 95db (mic-amp=0db) ? wind-noise reduction filter ? stereo separation emphasis ? programmable eq 2. playback function ? digital de-emphasis filter (tc= 50/15(s, fs=32khz, 44.1khz, 48khz) ? bass boost ? soft mute ? digital volume (+12db ( (115.0db, 0.5db step, mute) ? digital alc (automatic level control) (+36db ? 54db, 0.375db step, mute) ? stereo separation emphasis ? programmable eq ? stereo line output - performance: s/(n+d): 88db, s/n: 92db ? stereo headphone-amp - s/(n+d): 65db@7.5mw, s/n: 90db - output power: 70mw@16 (hvdd=5v), 62mw@16 (hvdd=3.3v) - pop noise free at power on/off ? analog mixing: 4 stereo input 3. power management 4. master clock: external clock mode ? frequencies: 256fs, 384fs, 512fs or 1024fs (mcki pin) 5. sampling rate: ? ext master/slave mode: 7.35khz 48khz (256fs), 7.35khz 48khz (384fs), 7.35khz 26khz (512fs), 7.35khz 13khz (1024fs) 6. p i/f: 3-wire serial, i 2 c bus (ver 1.0, 400khz fast-mode) 7. master/slave mode 8. audio interface format: msb first, 2?s complement ? adc: 16bit msb justified, i 2 s, dsp mode ? dac: 16bit msb justified, 16bit lsb justified, 16-24bit i 2 s, dsp mode stereo codec with mic/hp- a mp ak4645 a
[ak4645a] ms0986-e-00 2008/07 - 2 - 9. ta = ? 30 85 c 10. power supply: ? avdd, dvdd: 2.6 3.5v (typ. 3.3v) ? hvdd: 2.6 5.25v (typ. 3.3v/5.0v) ? tvdd (digital i/o): 1.6 3.5v (typ. 3.3v) 11. package: 32pin qfn (4mm x 4mm, 0.4mm pitch) 12. register compatible with ak4644 block diagram mic power supply mic-amp a/d wind-noise reduction stereo separation hpf pmadl or pmmicl pmadr or pmmicr pmadl or pmadr audio i/f d/a datt smute pmdac pmhpl pmhpr internal mic external mic line in stereo line out headphone alc bass boost pmmin mpwr lin1/in1 ? rin1/in1+ lin2/in2+ rin2/in2 ? hpl hpr mutet hvdd hvss avdd a vss vcom dvdd pdn bick lrck sdto sdti mcki pmlo lout/lop rout/lon alc tvdd stereo separation hpf min/lin3 * rin3 pmmp pmainr2 pmainl2 pmainr4 line in lin4/in4+ rin4/in4 ? pmainl3 pmainr3 pmainl4 control register csn/cad0 cclk/scl cdti/sda i2c figure 1. block diagram
[ak4645a] ms0986-e-00 2008/07 - 3 - ordering guide AK4645AEZ ? 30 +85 c 32pin qfn (0.4mm pitch) akd4645a evaluation board for ak4645a pin layout lin4 / in4+ rout / lon lout / lop min / lin3 rin2 / in2 ? lin2 / in2+ lin1 / in1 ? rin1 / in1+ rin4 / in4 ? mutet hpl hpr hvdd hvss testo mcki mpwr vcom a vss a vdd rin3 i2c pdn csn / cad0 tvdd dvdd bick lrck sdto sdti cdti / sda cclk / scl a k4645a top view 25 26 27 28 29 30 31 32 24 23 22 1 16 15 14 13 12 11 10 9 21 20 19 18 17 2 3 4 5 6 7 8 compatibility with ak4643/44 1. function function ak4643 ak4644 ak4645a digital i/o of p i/f 2.6 to 3.6v ? 1.6 to 3.5v analog mixing for playback 3 stereo ? 4 stereo input selector for recording 3 stereo ? 4 stereo hp-amp hi-z setting for wired or no ? yes pll 11.2896/12/12.288/ 13.5/24/27mhz ? no speaker-amp yes no ? receiver-amp yes ? no package 32qfn (5mm x 5mm, 0.5mm pitch) ? 32qfn (4mm x 4mm, 0.4mm pitch)
[ak4645a] ms0986-e-00 2008/07 - 4 - 2. pin pin# ak4643 ak4644 ak4645a 16 dvss ? tvdd 18 mcko mcko testo 19 spn test1 hvss 20 spp test2 hvdd 21 hvdd ? hpr 22 hvss ? hpl 23 hpr ? mutet 24 hpl ? rin4 / in4 ? 25 mutet ? lin4 / in4+ 26 rout/rcn ? rout/lon 27 lout/rcp ? lout/lop 3. register (difference from ak4644) addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h power management 1 0 pmvcm pmmin 0 pmlo pmdac 0 pmadl 01h power management 2 hpz hpmtn pmhpl pmhpr m/s 0 0 0 02h signal select 1 0 0 0 dacl 0 pmmp 0 mgain0 03h signal select 2 lovl lops mgain1 0 0 minl 0 0 04h mode control 1 0 0 0 0 bcko 0 dif1 dif0 05h mode control 2 0 0 fs3 msbs bckp fs2 fs1 fs0 06h timer select dvtm wtm2 ztm1 ztm0 wtm1 wtm0 rfst1 rfst0 07h alc mode control 1 0 0 alc zelmn lmat1 lmat0 rgain0 lmth0 08h alc mode control 2 ref7 ref6 ref5 ref4 ref3 ref2 ref1 ref0 09h lch input volume control ivl7 ivl6 ivl5 ivl4 ivl3 ivl2 ivl1 ivl0 0ah lch digital volume control dvl7 dvl6 dvl5 dvl4 dvl3 dvl2 dvl1 dvl0 0bh alc mode control 3 rgain1 lmth1 0 0 0 0 vbat 0 0ch rch input volume control ivr7 ivr6 ivr5 ivr4 ivr3 ivr2 ivr1 ivr0 0dh rch digital volume control dvr7 dvr6 dvr5 dvr4 dvr3 dvr2 dvr1 dvr0 0eh mode control 3 0 loop sm ute dvolc bst1 bst0 dem1 dem0 0fh mode control 4 0 0 0 0 ivolc hpm minh dach 10h power management 3 inr1 inl1 hpg mdif2 mdif1 inr0 inl0 pmadr 11h digital filter select gn1 gn0 0 fil1 eq fil3 0 0 12h fil3 co-efficient 0 f3a7 f3a6 f3a5 f3a4 f3a3 f3a2 f3a1 f3a0 13h fil3 co-efficient 1 f3as 0 f3a13 f3a12 f3a11 f3a10 f3a9 f3a8 14h fil3 co-efficient 2 f3b7 f3b6 f3b5 f3b4 f3b3 f3b2 f3b1 f3b0 15h fil3 co-efficient 3 0 0 f3b13 f3b12 f3b11 f3b10 f3b9 f3b8 16h eq co-efficient 0 eqa7 eqa6 e qa5 eqa4 eqa3 eqa2 eqa1 eqa0 17h eq co-efficient 1 eqa15 eqa1 4 eqa13 eqa12 eqa11 eqa10 eqa9 eqa8 18h eq co-efficient 2 eqb7 eqb6 eq b5 eqb4 eqb3 eqb2 eqb1 eqb0 19h eq co-efficient 3 0 0 eqb13 eqb12 eqb11 eqb10 eqb9 eqb8 1ah eq co-efficient 4 eqc7 eqc6 eq c5 eqc4 eqc3 eqc2 eqc1 eqc0 1bh eq co-efficient 5 eqc15 eqc14 e qc13 eqc12 eqc11 eqc10 eqc9 eqc8 1ch fil1 co-efficient 0 f1a7 f1a6 f1a5 f1a4 f1a3 f1a2 f1a1 f1a0 1dh fil1 co-efficient 1 f1as 0 f1a13 f1a12 f1a11 f1a10 f1a9 f1a8 1eh fil1 co-efficient 2 f1b7 f1b6 f1b5 f1b4 f1b3 f1b2 f1b1 f1b0 1fh fil1 co-efficient 3 0 0 f1b13 f1b12 f1b11 f1b10 f1b9 f1b8 20h power management 4 pmainr4 pmainl4 pmainr3 pmainl3 pmainr2 pmainl2 pmmicr pmmicl 21h mode control 5 0 0 micr3 micl3 l4dif mix ain3 lodif 22h lineout mixing select lom lom3 rinr4 linl4 rinr3 linl3 rinr2 linl2 23h hp mixing select 0 hpm3 rinh4 linh4 rinh3 linh3 rinh2 linh2 24h reserved 0 0 0 0 0 0 0 0 these bits are added in the ak4645a.
[ak4645a] ms0986-e-00 2008/07 - 5 - pin/function no. pin name i/o function 1 mpwr o mic power supply pin 2 vcom o common voltage output pin, 0.45 x avdd bias voltage of adc inputs and dac outputs. 3 avss - analog ground pin 4 avdd - analog power supply pin, 2.6 3.5v 5 rin3 i rch analog input 3 pin (ain3 bit = ?1?) 6 i2c i control mode select pin ?h?: i 2 c bus, ?l?: 3-wire serial 7 pdn i power-down mode pin ?h?: power-up, ?l?: power-down, reset and initializes the control register. csn i chip select pin (i2c pin = ?l?: 3-wire serial mode) 8 cad0 i chip address 1 select pin (i2c pin = ?h?: i 2 c bus mode) cclk i control data clock pin (i2c pin = ?l?: 3-wire serial mode) 9 scl i control data clock pin (i2c pin = ?h?: i 2 c bus mode) cdti i control data input pin (i2c pin = ?l?: 3-wire serial mode) 10 sda i/o control data input pin (i2c pin = ?h?: i 2 c bus mode) 11 sdti i audio serial data input pin 12 sdto o audio serial data output pin 13 lrck i/o input / output channel clock pin 14 bick i/o audio serial data clock pin 15 dvdd - digital power supply pin, 2.6 3.5v 16 tvdd - digital i/o power supply pin, 1.6 3.5v 17 mcki i external master clock input pin 18 testo o test pin this pin must be open. 19 hvss - headphone amp ground pin 20 hvdd - headphone amp power supply pin 21 hpr o rch headphone-amp output pin 22 hpl o lch headphone-amp output pin 23 mutet o mute time constant control pin connected to hvss pin with a cap acitor for mute time constant. rin4 i rch analog input 4 pin (l4dif bit = ?0?: single-ended input) 24 in4 ? i negative line input 4 pin (l4dif bit = ?1?: full-differential input) lin4 i lch analog input 4 pin (l4dif bit = ?0?: single-ended input) 25 in4+ i positive line input 4 pin (l4d if bit = ?1?: full-differential input) rout o rch stereo line output pin (lodif bit = ?0?: single-ended stereo output) 26 lon o negative line output pin (lodif bit = ?1?: full-differential mono output) lout o lch stereo line output pin (lodif bit = ?0?: single-ended stereo output) 27 lop o positive line output pin (lodif b it = ?1?: full-differential mono output) min i mono signal input pin 28 lin3 i lch analog input 3 pin rin2 i rch analog input 2 pin (mdif2 bit = ?0?: single-ended input) 29 in2 ? i microphone negative input 2 pin (mdif2 bit = ?1?: full-differential input) lin2 i lch analog input 2 pin (mdif2 bit = ?0?: single-ended input) 30 in2+ i microphone positive input 2 pin (mdi f2 bit = ?1?: full-differential input) lin1 i lch analog input 1 pin (mdif1 bit = ?0?: single-ended input) 31 in1 ? i microphone negative input 1 pin (mdif1 bit = ?1?: full-differential input) rin1 i rch analog input 1 pin (mdif1 bit = ?0?: single-ended input) 32 in1+ i microphone positive input 1 pin (mdi f1 bit = ?1?: full-differential input) note 1. all input pins except analog input pins (min/lin3, lin1, rin1, lin2, rin2, rin3, rin4, lin4) must not be left floating. note 2. avdd or avss voltage must be input to i2c pin.
[ak4645a] ms0986-e-00 2008/07 - 6 - handling of unused pin the unused i/o pins must be processed appropriately as below. classification pin name setting analog mpwr, rin3, hpr, hpl, mutet, rin4/in4 ? , lin4/in4+, rout/lop, lout/lon, min/lin3, rin2/in2 ? , lin2/in2+, lin1/in1 ? , rin1/in1+ these pins must be open. testo this pin must be open. digital mcki this pin must be connected to hvss. absolute maximum ratings (avss=hvss=0v; note 3 , note 4 ) parameter symbol min max units power supplies: analog avdd ? 0.3 6.0 v digital dvdd ? 0.3 6.0 v digital i/o tvdd ? 0.3 6.0 v headphone-amp hvdd ? 0.3 6.0 v input current, any pin except supplies iin - 10 ma analog input voltage ( note 5 ) vina ? 0.3 avdd+0.3 v digital input voltage ( note 6 ) vind ? 0.3 tvdd+0.3 v ambient temperature (powered applied) ta ? 30 85 c storage temperature tstg ? 65 150 c note 3. all voltages with respect to ground. note 4. avss and hvss must be connected to the same analog ground plane. note 5. i2c, rin4/in4 ? , lin4/in4+, min/lin3, rin3, rin2/in2 ? , lin2/in2+, lin1/in1 ? , rin1/in1+ pins note 6. pdn, csn/cad0, cclk/scl, cd ti/sda, sdti, lrck, bick, mcki pins pull-up resistors at sda and scl pins should be connected to (tvdd+0.3)v or less voltage. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guara nteed at these extremes. recommended operating conditions (avss=hvss=0v; note 3 ) parameter symbol min typ max units power supplies analog avdd 2.6 3.3 3.5 v ( note 7 ) digital dvdd 2.6 3.3 3.5 v digital i/o tvdd 1.6 3.3 3.5 v hp-amp hvdd 2.6 3.3 / 5.0 5.25 v difference avdd ? dvdd ? 0.3 0 +0.3 v difference tvdd-dvdd - 0 +0.3 v note 3. all voltages with respect to ground. note 7. the power-up sequence between avdd, dvdd, tvdd a nd hvdd is not critical. pdn pin must be held to ?l? upon power-up. pdn pin must be set to ?h? after all power supplies are powered-up. the ak4645a must be operated by the recommended power-up/down sequence shown in ?system design (grounding and power supply decoupling)? to avoid the pop noise at line output and headphone output. when one of power supplies is partially powered off, the power supply current at power-down mode may be increased. all the power supplies should be powered off when the power supply is powered off. * akemd assumes no responsibility for the usag e beyond the conditions in this datasheet.
[ak4645a] ms0986-e-00 2008/07 - 7 - analog characteristics (ta=25 c; avdd=dvdd=tvdd=hvdd=3.3v; avss=hvss= 0v; fs=44.1khz, bick=64fs; signal frequency=1khz; 16bit data; measurement frequency=20hz 20khz; unless otherwise specified) parameter min typ max units mic amplifier: lin1/rin1/lin2/rin2/lin4/rin4 pins & lin3/rin3 pins (ain3 bit = ?1?); mdif1=mdif2 bits = ?0? (single-ended inputs) mgain1-0 bits = ?00? 40 60 80 k input resistance mgain1-0 bits = ?01?, ?10?or ?11? 20 30 40 k mgain1-0 bits = ?00? - 0 - db mgain1-0 bits = ?01? - +20 - db mgain1-0 bits = ?10? - +26 - db gain mgain1-0 bits = ?11? - +32 - db mic amplifier: in1+/in1 ? /in2+/in2 ? pins; mdif1 = mdif2 bits = ?1? (full-differential input) maximum input voltage ( note 8 ) mgain1-0 bits = ?01? - - 0.228 vpp mgain1-0 bits = ?10? - - 0.114 vpp mgain1-0 bits = ?11? - - 0.057 vpp mic power supply: mpwr pin output voltage ( note 9 ) 2.22 2.47 2.72 v load resistance 0.5 - - k load capacitance - - 30 pf adc analog input characteristics: lin1/rin1/lin2/rin2/lin4/rin4 pins & lin3/rin3 pins (ain3 bit = ?1?) adc ivol, ivol=0db, alc=off resolution - - 16 bits ( note 11 ) 0.168 0.198 0.228 vpp input voltage ( note 10 ) ( note 12 ) 1.68 1.98 2.28 vpp ( note 11 , lin1/rin1/lin2/rin2) 71 83 - dbfs ( note 11 , lin3/rin3/lin4/rin4) - 83 - dbfs ( note 12 , except for lin3/rin3) - 88 - dbfs s/(n+d) ( ? 1dbfs) ( note 12 , lin3/rin3) - 72 - dbfs ( note 11 ) 76 86 - db d-range ( ? 60dbfs, a-weighted) ( note 12 ) - 95 - db ( note 11 ) 76 86 - db s/n (a-weighted) ( note 12 ) - 95 - db ( note 11 ) 75 90 - db interchannel isolation ( note 12 ) - 100 - db ( note 11 ) - 0.1 0.8 db interchannel gain mismatch ( note 12 ) - 0.1 0.8 db note 8. the voltage difference between in1/2+ and in1/2 ? pins. ac coupling capacitor should be inserted in series at each input pin. full-differential mic i nput is not available at mgain1-0 b its = ?00?. maximum input voltage of in1+, in1 ? , in2+ and in2 ? pins are proportional to avdd voltage, respectively. vin = 0.069 x avdd (max)@mgain1-0 bits = ?01?, 0.035 x avdd (max)@mgain1-0 bits = ?10?, 0.017 x avdd (max)@mgain1-0 bits = ?11?. when the signal larger than above value is input to in1+, in1 ? , in2+ or in2 ? pin, adc does not operate normally. note 9. output voltage is proportional to avdd voltage. vout = 0.75 x avdd (typ) note 10. input voltage is proportional to avdd voltage. vin = 0.06 x avdd (typ)@mgain1-0 bits = ?01? (+20db), vin = 0.6 x avdd(typ)@mgain1-0 bits = ?00? (0db) note 11. mgain1-0 bits = ?01? (+20db) note 12. mgain1-0 bits = ?00? (0db)
[ak4645a] ms0986-e-00 2008/07 - 8 - parameter min typ max units dac characteristics: resolution - - 16 bits stereo line output characteristics: dac lout/rout pins, alc=off, i vol=0db, dvol=0db, lovl bit = ?0?, lodif bit = ?0?, r l =10k (single-ended); unless otherwise specified. output voltage ( note 13 ) lovl bit = ?0? 1.78 1.98 2.18 vpp lovl bit = ?1? 2.25 2.50 2.75 vpp s/(n+d) ( ? 3dbfs) 78 88 - dbfs s/n (a-weighted) 82 92 - db interchannel isolation 80 100 - db interchannel gain mismatch - 0.1 0.5 db load resistance 10 - - k load capacitance - - 30 pf mono line output characteristics: dac lop/lon pins, alc=off, ivol= 0db, dvol=0db, lovl bit = ?0?, lodif bit = ?1?, r l =10k for each pin (full-differential) output voltage ( note 14 ) lovl bit = ?0? 3.52 3.96 4.36 vpp lovl bit = ?1? - 5.00 - vpp s/(n+d) ( ? 3dbfs) 78 88 - dbfs s/n (a-weighted) 85 95 - db load resistance (lop/lon pins, respectively) 10 - - k load capacitance (lop/lon pins, respectively) - - 30 pf note 13. output voltage is proportional to avdd voltage. vout = 0.6 x avdd (typ)@lovl bit = ?0?. note 14. output voltage is proportional to avdd voltage. vout = (lop) ? (lon) = 1.2 x avdd (typ)@lovl bit = ?0?.
[ak4645a] ms0986-e-00 2008/07 - 9 - parameter min typ max units headphone-amp characteristics: dac hpl/hpr pins, alc=off, ivol= 0db, dvol=0db, vbat bit = ?0?; unless otherwise specified. output voltage ( note 15 ) hpg bit = ?0?, 0dbfs, hvdd=3.3v, r l =22.8 1.58 1.98 2.38 vpp hpg bit = ?1?, 0dbfs, hvdd=5v, r l =100 2.40 3.00 3.60 vpp hpg bit = ?1?, 0dbfs, hvdd=3.3v, r l =16 (po=62mw) - 1.0 - vrms hpg bit = ?1?, 0dbfs, hvdd=5v, r l =16 (po=70mw) - 1.06 - vrms s/(n+d) hpg bit = ?0?, ? 3dbfs, hvdd=3.3v, r l =22.8 57 67 - dbfs hpg bit = ?1?, ? 3dbfs, hvdd=5v, r l =100 - 75 - dbfs hpg bit = ?1?, 0dbfs, hvdd=3.3v, r l =16 (po=62mw) - 20 - dbfs hpg bit = ?1?, 0dbfs, hvdd=5v, r l =16 (po=70mw) - 65 - dbfs ( note 16 ) 80 90 - db s/n (a-weighted) ( note 17 ) - 90 - db ( note 16 ) 65 75 - db interchannel isolation ( note 17 ) - 80 - db ( note 16 ) - 0.1 0.8 db interchannel gain mismatch ( note 17 ) - 0.1 0.8 db load resistance 16 - - c1 in figure 2 - - 30 pf load capacitance c2 in figure 2 - - 300 pf note 15. output voltage is proportional to avdd voltage. vout = 0.6 x avdd(typ)@hpg bit = ?0 ?, 0.91 x avdd(typ)@hpg bit = ?1?. note 16. hpg bit = ?0?, hvdd=3.3v, r l =22.8 . note 17. hpg bit = ?1?, hvdd=5v, r l =100 . hpl/hpr pin hp-amp 47 f c1 16 c2 6.8 0.22 f 10 measurement point figure 2. headphone-amp output circuit
[ak4645a] ms0986-e-00 2008/07 - 10 - parameter min typ max units mono input: min pin (ain3 bit = ?0?; external input resistance=20k ) maximum input voltage ( note 18 ) - 1.98 - vpp gain ( note 19 ) min ? lout/rout lovl bit = ?0? ? 4.5 0 +4.5 db lovl bit = ?1? - +2 - db min ? hpl/hpr hpg bit = ?0? ? 24.5 ? 20 ? 15.5 db hpg bit = ?1? - ? 16.4 - db stereo input: lin2/rin2/lin4/rin4 pins; lin3/rin3 pins (ain3 bit = ?1?) maximum input voltage ( note 20 ) - 1.98 - vpp gain lin/rin ? lout/rout lovl bit = ?0? ? 4.5 0 +4.5 db lovl bit = ?1? - +2 - db lin/rin ? hpl/hpr hpg bit = ?0? ? 4.5 0 +4.5 db hpg bit = ?1? - +3.6 - db full-differential mono input: in4+/ ? pins (l4dif bit = ?1?) maximum input voltage ( note 21 ) - 3.96 - vpp gain in4+/ ? ? lout/rout lovl bit = ?0? ? 10.5 ? 6 ? 1.5 db (lodif bit = ?0?) lovl bit = ?1? - ? 4 - db in4+/ ? ? lop/lon lovl bit = ?0? ? 4.5 0 +4.5 db (lodif bit = ?1?, note 22 ) lovl bit = ?1? - +2 - db in4+/ ? ? hpl/hpr hpg bit = ?0? ? 10.5 ? 6 ? 1.5 db hpg bit = ?1? - ? 2.4 - db power supplies: power-up (pdn pin = ?h?) all circuit power-up: avdd+dvdd+tvdd ( note 23 ) - 12 18 ma hvdd: hp-amp normal operation no output ( note 24 ) - 3 4.5 ma power-down (pdn pin = ?l?) ( note 25 ) avdd+dvdd+tvdd+hvdd - 1 100 a note 18. maximum voltage is in proportion to both avdd and external input resistance (rin). vin = 0.6 x avdd x rin / 20k (typ). note 19. the gain is in inverse proportion to external input resistance. note 20. maximum input voltage is proportional to avdd voltage. vout = 0.6 x avdd (typ). note 21. maximum input voltage is proportional to avdd voltage. vout = (in4+) ? (in4 ? ) = 1.2 x avdd (typ). the signals with same amplitude and inverted phase should be input to in4+ and in4 ? pins, respectively. note 22. vout = (lop) ? (lon) at lodif bit = ?1?. note 23. when ext slave mode (m/s = bit = ?0?, mcki = 12.288mhz), pmvcm = pmadl = pmadr = pmdac = pmlo = pmhpl = pmhpr = pmmin = pmmp = ?1?: avdd=9ma (typ), dvdd=3ma (typ ), tvdd=0.03ma (typ). note 24. when pmadl = pmadr = pmdac = pmlo = pmhpl = pmhpr = pmvcm = pmmin bits = ?1? note 25. all digital input pins are fixed to tvdd or hvss.
[ak4645a] ms0986-e-00 2008/07 - 11 - power consumption for each operation mode condtions: ta=25 c; avdd=dvdd=tvdd=hvdd=3.3v; avss=hvss=0v; fs =44.1khz, external slave mode, bick=64fs; 1khz, 0dbfs input; headphone = no output. power management bit 00h 01h 10h 20h mode pmvcm pmmin pmlo pmdac pmadl pmhpl pmhpr pmadr pmmicl pmmicr pmainl2 pmainr2 pmainl3 pmainr3 pmainl4 pmainr4 avdd [ma] dvdd [ma] tvdd [ma] hvdd [ma] total power [mw] all power-down 0 0 0 0 0 0 0 000000000 0 0 0 0 0 dac ? lineout 1 0 1 1 0 0 0 000000000 3.2 1.8 0.03 0.2 17.2 dac ? hp 1 0 0 1 0 1 1 000000000 2.6 1.8 0.03 3.0 24.5 lin2/rin2 ? hp 1 0 0 0 0 1 1 000110000 1.9 0 0 3.0 16.2 lin2/rin2 ? adc 1 0 0 0 1 0 0 100000000 5.5 1.6 0.03 0.2 24.2 lin1 (mono) ? adc 1 0 0 0 1 0 0 000000000 3.5 1.5 0.03 0.2 17.3 lin2/rin2 ? adc & dac ? hp 1 0 0 1 1 1 1 100000000 7.1 2.7 0.03 3.0 42.3 table 1. power consumption for each operation mode (typ)
[ak4645a] ms0986-e-00 2008/07 - 12 - filter characteristics (ta=25 c; avdd=dvdd=2.6 3.5v; tvdd=1.6 3.5v; hvdd=2.6 5.25v; fs=44.1khz; dem=off; fil1=fil3=eq=off) parameter symbol min typ max units adc digital filter (decimation lpf): passband ( note 26 ) 0.16db pb 0 - 17.3 khz ? 0.66db - 19.4 - khz ? 1.1db - 19.9 - khz ? 6.9db - 22.1 - khz stopband sb 26.1 - - khz passband ripple pr - - 0.1 db stopband attenuation sa 73 - - db group delay ( note 27 ) gd - 19 - 1/fs group delay distortion gd - 0 - s adc digital filter (hpf): ( note 28 ) frequency response ( note 26 ) ? 3.0db fr - 0.9 - hz ? 0.5db - 2.7 - hz ? 0.1db - 6.0 - hz dac digital filter (lpf): passband ( note 26 ) 0.1db pb 0 - 19.6 khz ? 0.7db - 20.0 - khz ? 6.0db - 22.05 - khz stopband sb 25.2 - - khz passband ripple pr - - 0.01 db stopband attenuation sa 59 - - db group delay ( note 27 ) gd - 25 - 1/fs dac digital filter (lpf) + scf: frequency response: 0 20.0khz fr - 1.0 - db dac digital filter (hpf): ( note 28 ) frequency response ( note 26 ) ? 3.0db fr - 0.9 - hz ? 0.5db - 2.7 - hz ? 0.1db - 6.0 - hz boost filter: ( note 29 ) min 20hz fr - 5.76 - db 100hz - 2.92 - db 1khz - 0.02 - db mid 20hz fr - 10.80 - db 100hz - 6.84 - db 1khz - 0.13 - db max 20hz fr - 16.06 - db 100hz - 10.54 - db frequency response 1khz - 0.37 - db note 26. the passband and stopband frequencies scale with fs (system sampling rate). for example, dac is pb=0.454*fs (@ ? 0.7db). each response refers to that of 1khz. note 27. the calculated delay time caused by digital filtering. this time is from the input of analog signal to setting of the 16-bit data of both channels from the input register to the output register of the adc. this time includes the group delay of the hpf. for the dac, this time is from setting the 16-bit data of both channels from the input register to the output of analog signal. group delay of dac part is 25/fs(typ) at pmadl=pmadr bits = ?0?. note 28. when pmadl bit = ?1? or pmadr bit = ?1?, the hpf of adc is enabled but the hpf of dac is disabled. when pmadl=pmadr bits = ?0?, pmdac bit = ?1?, th e hpf of dac is enabled but the hpf of adc is disabled. note 29. these frequency responses scale with fs. if a high-leve l signal is input, the analog output clips to the full-scale at low frequency.
[ak4645a] ms0986-e-00 2008/07 - 13 - dc characteristics (ta=25 c; avdd=dvdd=2.6 3.5v; tvdd=1.6 3.5v; hvdd=2.6 5.25v) parameter symbol min typ max units high-level input voltage 2.2v tvdd 3.5v vih 70 % tvdd - - v 1.6v tvdd<2.2v vih 75 % tvdd - - v low-level input voltage 2.2v tvdd 3.5v vil - - 30 % tvdd v 1.6v tvdd<2.2v vil - - 25 % tvdd v high-level output voltage (iout= ? 200 a) voh tvdd ? 0.2 - - v low-level output voltage (except sda pin: iout=200 a) vol - - 0.2 v (sda pin: iout=3ma) vol - - 0.4 v input leakage current iin - - 10 a switching characteristics (ta=25 c; avdd=dvdd=2.6 3.5v;or 3.3v tvdd=1.6 3.5v; hvdd=2.6 5.25v or avdd=dvdd=3.3v; c l =20pf; unless otherwise specified) parameter symbol min typ max units external slave mode mcki input timing frequency 256fs 384fs fclk fclk 1.8816 2.8224 - - 12.288 18.432 mhz mhz 512fs fclk 3.7632 - 13.312 mhz 1024fs fclk 7.5264 - 13.312 mhz pulse width low tclkl 0.4/fclk - - ns pulse width high tclkh 0.4/fclk - - ns lrck input timing frequency 256fs 384fs fs fs 7.35 7.35 - - 48 48 khz khz 512fs fs 7.35 - 26 khz 1024fs fs 7.35 - 13 khz dsp mode: pulse width high tlrckh tbck ? 60 - 1/fs ? tbck ns except dsp mode: duty cycle duty 45 - 55 % bick input timing period tbck 312.5 - - ns pulse width low tbckl 130 - - ns pulse width high tbckh 130 - - ns external master mode mcki input timing frequency 256fs 384fs fclk fclk 1.8816 2.8224 - - 12.288 18.432 mhz mhz 512fs fclk 3.7632 - 13.312 mhz 1024fs fclk 7.5264 - 13.312 mhz pulse width low tclkl 0.4/fclk - - ns pulse width high tclkh 0.4/fclk - - ns lrck output timing frequency fs 7.35 - 48 khz dsp mode: pulse width high tlrckh - tbck - ns except dsp mode: duty cycle duty - 50 - % bick output timing period bcko bit = ?0? tbck - 1/(32fs) - ns bcko bit = ?1? tbck - 1/(64fs) - ns duty cycle dbck - 50 - %
[ak4645a] ms0986-e-00 2008/07 - 14 - parameter symbol min typ max units audio interface timing (dsp mode) master mode lrck ? ? to bick ? ? ( note 30 ) tdbf 0.5 x tbck ? 40 0.5 x tbck 0.5 x tbck + 40 ns lrck ? ? to bick ? ? ( note 31 ) tdbf 0.5 x tbck ? 40 0.5 x tbck 0.5 x tbck + 40 ns bick ? ? to sdto (bckp bit = ?0?) tbsd ? 70 - 70 ns bick ? ? to sdto (bckp bit = ?1?) tbsd ? 70 - 70 ns sdti hold time tsdh 50 - - ns sdti setup time tsds 50 - - ns slave mode lrck ? ? to bick ? ? ( note 30 ) tlrb 0.4 x tbck - - ns lrck ? ? to bick ? ? ( note 31 ) tlrb 0.4 x tbck - - ns bick ? ? to lrck ? ? ( note 30 ) tblr 0.4 x tbck - - ns bick ? ? to lrck ? ? ( note 31 ) tblr 0.4 x tbck - - ns bick ? ? to sdto (bckp bit = ?0?) tbsd - - 80 ns bick ? ? to sdto (bckp bit = ?1?) tbsd - - 80 ns sdti hold time tsdh 50 - - ns sdti setup time tsds 50 - - ns audio interface timing (r ight/left justified & i 2 s) master mode bick ? ? to lrck edge ( note 32 ) tmblr ? 40 - 40 ns lrck edge to sdto (msb) (except i 2 s mode) tlrd ? 70 - 70 ns bick ? ? to sdto tbsd ? 70 - 70 ns sdti hold time tsdh 50 - - ns sdti setup time tsds 50 - - ns slave mode lrck edge to bick ? ? ( note 32 ) tlrb 50 - - ns bick ? ? to lrck edge ( note 32 ) tblr 50 - - ns lrck edge to sdto (msb) (except i 2 s mode) tlrd - - 80 ns bick ? ? to sdto tbsd - - 80 ns sdti hold time tsdh 50 - - ns sdti setup time tsds 50 - - ns note 30. msbs, bckp bits = ?00? or ?11?. note 31. msbs, bckp bits = ?01? or ?10?. note 32. bick rising edge must not occur at the same time as lrck edge.
[ak4645a] ms0986-e-00 2008/07 - 15 - parameter symbol min typ max units control interface timing (3-wire serial mode) cclk period tcck 200 - - ns cclk pulse width low tcckl 80 - - ns pulse width high tcckh 80 - - ns cdti setup time tcds 40 - - ns cdti hold time tcdh 40 - - ns csn ?h? time tcsw 150 - - ns csn edge to cclk ? ? ( note 34 ) tcss 50 - - ns cclk ? ? to csn edge ( note 34 ) tcsh 50 - - ns control interface timing (i 2 c bus mode): ( note 33 ) scl clock frequency fscl - - 400 khz bus free time between transmissions tbuf 1.3 - - s start condition hold time (prior to first clock pulse) thd:sta 0.6 - - s clock low time tlow 1.3 - - s clock high time thigh 0.6 - - s setup time for repeated start condition tsu:sta 0.6 - - s sda hold time from scl falling ( note 35 ) thd:dat 0 - - s sda setup time from scl rising tsu:dat 0.1 - - s rise time of both sda and scl lines tr - - 0.3 s fall time of both sda and scl lines tf - - 0.3 s setup time for stop condition tsu:sto 0.6 - - s capacitive load on bus cb - - 400 pf pulse width of spike noise suppressed by input filter tsp 0 - 50 ns power-down & reset timing pdn pulse width ( note 36 ) tpd 150 - - ns pmadl or pmadr ? ? to sdto valid ( note 37 ) tpdv - 1059 - 1/fs note 33. i 2 c is a registered trademark of philips semiconductors. note 34. cclk rising edge must not occur at the same time as csn edge. note 35. data must be held long enough to bridge the 300ns-transition time of scl. note 36. the ak4645a can be reset by the pdn pin = ?l?. note 37. this is the count of lrck ? ? from the pmadl or pmadr bit = ?1?.
[ak4645a] ms0986-e-00 2008/07 - 16 - timing diagram lrck 1/fclk mcki tclkh tclkl vih vil 1/fs tlrckh tlrckl 50%tvdd duty = tlrckh x fs x 100 tlrckl x fs x 100 bick tbck tbckh tbckl 50%tvdd dbck = tbckh / tbck x 100 tbckl / tbck x 100 figure 3. clock timing (ext master mode) lrck bick 50%tvdd sdto 50%tvdd tbsd dbck tdbf 50%tvdd tlrckh tbck msb bick 50%tvdd (bckp = "0") (bckp = "1") tsds sdti vil tsdh vih figure 4. audio interface timing (ext ma ster mode, dsp mode, msbs = ?0?)
[ak4645a] ms0986-e-00 2008/07 - 17 - lrck bick 50%tvdd sdto 50%tvdd tbsd dbck tdbf 50%tvdd tlrckh tbck msb bick 50%tvdd (bckp = "1") (bckp = "0") tsds sdti vil tsdh vih figure 5. audio interface timing (ext ma ster mode, dsp mode, msbs = ?1?) lrck 50%tvdd bick 50%tvdd sdto 50%tvdd tbsd tsds sdti vil tsdh vih tblr tbckl tlrd figure 6. audio interface timing (ext master mode, except dsp mode)
[ak4645a] ms0986-e-00 2008/07 - 18 - 1/fclk mcki tclkh tclkl vih vil 1/fs lrck vih vil tbck bick tbckh tbckl vih vil tlrckh tlrckl duty = tlrckh x fs x 100 tlrckl x fs x 100 figure 7. clock timing (ext slave mode) lrck bick sdto 50%tvdd tbsd tsds sdti vil tsdh vih tlrb tlrckh msb msb vil vih vil vih bick vil vih (bckp = "0") (bckp = "1") figure 8. audio interface timing (ext slave mode, dsp mode; msbs = ?0?)
[ak4645a] ms0986-e-00 2008/07 - 19 - lrck bick sdto 50%tvdd tbsd tsds sdti vil tsdh vih tlrb tlrckh msb msb vil vih vil vih bick vil vih (bckp = "1") (bckp = "0") figure 9. audio interface timing (ext slave mode, dsp mode, msbs = ?1?) lrck vih vil tblr bick vih vil tlrd sdto 50%tvdd tlrb tbsd tsds sdti vil tsdh vih msb figure 10. audio interface timing (e xt slave mode, except dsp mode)
[ak4645a] ms0986-e-00 2008/07 - 20 - csn vih vil tcss cclk tcds vih vil cdti vih tcckh tcckl tcdh vil c1 c0 r/w tcck tcsh figure 11. write command input timing csn vih vil tcsh cclk vih vil cdti vih tcsw vil d1 d0 d2 tcss figure 12. write data input timing
[ak4645a] ms0986-e-00 2008/07 - 21 - stop start start stop thigh thd:dat sda scl tbuf tlow tr tf tsu:dat vih vil thd:sta tsu:sta vih vil tsu:sto tsp figure 13. i 2 c bus mode timing pmadl bit or pmadr bit tpdv sdto 50%tvdd figure 14. power down & reset timing 1 tpd pdn vil figure 15. power down & reset timing 2
[ak4645a] ms0986-e-00 2008/07 - 22 - operation overview system clock there are the following two clock modes to interface with external devices ( table 2 and table 3 ). mode m/s bit figure ext slave mode 0 figure 16 ext master mode 1 figure 17 table 2. clock mode setting (x: don?t care) mode mcki pin bick pin lrck pin ext slave mode selected by fs1-0 bits input ( 32fs) input (1fs) ext master mode selected by fs1-0 bits output (selcted bybcko bit) output (1fs) table 3. clock pins state in clock mode master mode/slave mode the m/s bit selects either master or sl ave mode. m/s bit = ?1? selects master m ode and ?0? selects slave mode. when the ak4645a is powered-down (pdn pin = ?l?) and exits reset st ate, the ak4645a is in slave mode. after exiting reset state, the ak4645a goes to master mode by changing m/s bit = ?1?. when the ak4645a is in master mode, lrck and bick pins are floating state until m/s bit becomes ?1?. lrck and bick pins of the ak4645a should be pulled-down or pulled-up by the resistor (about 100k ) externally to avoid the floating state. m/s bit mode 0 slave mode (default) 1 master mode table 4. select master/slave mode
[ak4645a] ms0986-e-00 2008/07 - 23 - ext slave mode (m/s bit = ?0?) the master clock is input from the mcki pin for adc and dac. this mode is compatible with i/f of the normal audio codec. the clocks required to operate are mcki (256fs, 384fs, 512fs or 1024fs), lrck (fs) and bick ( 32fs). the master clock (mcki) should be synchronized with lrck. th e phase between these clocks does not matter. the input frequency of mcki is selected by fs1-0 bits ( table 5 ). mode fs3-2 bits fs1 bit fs0 bit mcki input frequency sampling frequency range 0 don?t care 0 0 256fs 7.35khz 48khz (default) 1 don?t care 0 1 1024fs 7.35khz 13khz 2 don?t care 1 0 384fs 7.35khz 48khz 3 don?t care 1 1 512fs 7.35khz 26khz table 5. mcki frequency at ext slave mode (m/s bit = ?0?) the s/n of the dac at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise. the out-of-band noise can be improved by using higher freque ncy of the master clock. the s/n of the dac output through lout/rout pins at fs=8khz is shown in table 6 . mcki s/n (fs=8khz, 20khzlpf + a-weighted) 256fs 83db 384fs 83db 512fs 93db 1024fs 93db table 6. relationship between mcki and s/n of lout/rout pins the external clocks (mcki, bick and lrck) should always be present whenever the adc or dac is in operation (pmadl bit = ?1?, pmadr bit = ?1? or pmdac bit = ?1?). if these clocks are not provided, the ak4645a may draw excess current and it is not possible to ope rate properly because utilizes dynamic refre shed logic internally. if the external clocks are not present, the adc and dac should be in the power-down mode (pmadl=pmadr=pmdac bits = ?0?). ak4645a dsp or p mcki bick lrck sdto sdti bclk lrck sdti sdto 1fs 32fs mclk 256fs, 384fs, 512fs or 1024fs figure 16. ext slave mode
[ak4645a] ms0986-e-00 2008/07 - 24 - ext master mode (m/s bit = ?1?) the ak4645a becomes ext master mode by setting m/s bit = ?1?. master clock is input from the mcki pin for adc and dac. the clock required to operate is mcki (256fs, 384fs, 512fs or 1024fs). the input frequency of mcki is selected by fs1-0 bits ( table 7 ). mode fs3-2 bits fs1 bit fs0 bit mcki input frequency sampling frequency range 0 don?t care 0 0 256fs 7.35khz 48khz (default) 1 don?t care 0 1 1024fs 7.35khz 13khz 2 don?t care 1 0 384fs 7.35khz 48khz 3 don?t care 1 1 512fs 7.35khz 26khz table 7. mcki frequency at ext master mode (m/s bit = ?1?) the s/n of the dac at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise. the out-of-band noise can be improved by using higher freque ncy of the master clock. the s/n of the dac output through lout/rout pins at fs=8khz is shown in table 8 . mcki s/n (fs=8khz, 20khzlpf + a-weighted) 256fs 83db 384fs 83db 512fs 93db 1024fs 93db table 8. relationship between mcki and s/n of lout/rout pins mcki should always be present whenever the adc or dac is in operation (pmadl bit = ?1?, pmadr bit = ?1? or pmdac bit = ?1?). if mcki is not provided, the ak4645a may draw excess current and it is not possible to operate properly because utilizes dynamic refreshed logic internally. if mcki is not pr esent, the adc and dac should be in power-down mode (pmadl=pmadr=pmdac bits = ?0?). ak4645a dsp or p mcki bick lrck sdto sdti bclk lrck sdti sdto 1fs 32fs or 64fs mclk 256fs, 384fs, 512fs or 1024fs figure 17. ext master mode bcko bit bick output frequency 0 32fs (default) 1 64fs table 9. bick output frequency at master mode
[ak4645a] ms0986-e-00 2008/07 - 25 - system reset upon power-up, the ak4645a must be reset by bringing the pdn pi n = ?l?. this ensures that all internal registers reset to their initial values. the adc enters an initialization cycle when the pmadl or pmadr bit is changed from ?0? to ?1? at pmdac bits is ?0?. the initialization cycle time is 1059/fs=24ms@fs=44.1khz. during the initialization cycle, the adc digital data of both channels is forced to output a 2?s compliment, ?0? data. the adc output reflects the analog input signal after the initialization cycle is completed. when pmdac bit is ?1?, the adc does not require an initialization cycle. the dac enters an initialization cycle when the pmdac bit is changed from ?0? to ?1? at pmadl and pmadr bits are ?0?. the initialization cycle time is 1059/fs=24ms@fs=44.1khz. during the initialization cycl e, the dac input digital data of both channels are internally forced to a 2?s compliment, ?0?. the dac output reflects the digital input data after the initialization cycle is completed. when pmadl or pmadr bit is ?1?, the dac does not require an initialization cycle. audio interface format four types of data formats are available a nd are selected by setting the dif1-0 bits ( table 10 ). in all modes, the serial data is msb first, 2?s complement format. audio interface format s can be used in both master and slave modes. lrck and bick are output from the ak4645a in master mode, but must be input to the ak4645a in slave mode. mode dif1 bit dif0 bit sdto (adc) sdti (dac) bick figure 0 0 0 dsp mode dsp mode 32fs table 11 1 0 1 msb justified lsb justified 32fs figure 22 2 1 0 msb justified msb justified 32fs figure 23 (default) 3 1 1 i 2 s compatible i 2 s compatible 32fs figure 24 table 10. audio interface format in modes 1, 2 and 3, the sdto is clocked out on the falling edge (? ?) of bick and the sdti is latched on the rising edge (? ?). in modes 0 (dsp mode), the audio i/f timing is changed by bckp and msbs bits ( table 11 ). dif1 dif0 msbs bckp audio interface format figure 0 0 0 msb of sdto is output by the rising edge (? ?) of the first bick after the rising edge (? ?) of lrck. msb of sdti is latched by the falling edge (? ?) of the bick just after the output timing of sdto?s msb. figure 18 (default) 0 1 msb of sdto is output by the falling edge (? ?) of the first bick after the rising edge (? ?) of lrck. msb of sdti is latched by the rising edge (? ?) of the bick just after the output timing of sdto?s msb. figure 19 1 0 msb of sdto is output by next rising edge (? ?) of the falling edge (? ?) of the first bick after the rising edge (? ?) of lrck. msb of sdti is latched by the falling edge (? ?) of the bick just after the output timing of sdto?s msb. figure 20 0 1 1 msb of sdto is output by next falling edge (? ?) of the rising edge (? ?) of the first bick after the rising edge (? ?) of lrck. msb of sdti is latched by the rising edge (? ?) of the bick just after the output timing of sdto?s msb. figure 21 table 11. audio interface format in mode 0 if 16-bit data that adc outputs is converted to 8-bit data by removing lsb 8-bit, ? ? 1? at 16bit data is converted to ? ? 1? at 8-bit data. and when the dac playbacks this 8-bit data, ? ? 1? at 8-bit data will be converted to ? ? 256? at 16-bit data and this is a large offset. this offset can be removed by addi ng the offset of ?128? to 16-bit data before converting to 8-bit data.
[ak4645a] ms0986-e-00 2008/07 - 26 - lrck bick ( 32fs ) sdto(o) 15 0 1 8 9 11 12 14 15 16 17 24 25 27 26 30 31 0 0 15 5 8 7 1 43 10 13 2 6 0 15 5 87 1 4 3 2 6 29 26 0 2 14 14 18 bick ( 64fs ) sdto(o) 15 0 1 14 15 17 18 30 31 32 33 46 47 49 50 62 63 15 2 1 16 0 15 21 0 48 15:msb, 0:lsb 1/fs 2 14 14 34 lch lch rch rch sdti(i) 0 15 5 8 7 1 432 6 0 15 5 87 1 4 3 2 60 14 14 lch rch sdti(i) 15 2 1 0 15 210 14 14 lch rch lrck (master) (slave) figure 18. mode 0 timing (bckp = ?0?, msbs = ?0?) rch lch bick ( 32fs ) sdto(o) 15 0 1 8 9 11 12 14 15 16 17 24 25 27 26 30 31 0 0 15 5 8 7 1 43 10 13 2 6 0 15 5 87 1 4 3 2 6 29 26 0 2 14 14 18 bick ( 64fs ) sdto(o) 15 0 1 14 15 17 18 30 31 32 33 46 47 49 50 62 63 15 2 1 16 0 15 21 0 48 15:msb, 0:lsb 1/fs 2 14 14 34 lch rch sdti(i) 0 15 5 8 7 1 432 6 0 15 5 87 1 4 3 2 60 14 14 lch rch sdti(i) 15 2 1 0 15 210 14 14 lch rch lrck lrck (master) (slave) figure 19. mode 0 timing (bckp = ?1?, msbs = ?0?)
[ak4645a] ms0986-e-00 2008/07 - 27 - bick ( 32fs ) sdto(o) 15 0 1 8 9 11 12 14 15 16 17 24 25 27 26 30 31 0 0 15 5 8 7 1 43 10 13 2 6 0 15 5 87 1 4 3 2 6 29 26 0 2 14 14 18 bick ( 64fs ) sdto(o) 15 0 1 14 15 17 18 30 31 32 33 46 47 49 50 62 63 15 2 1 16 0 15 21 0 48 15:msb, 0:lsb 1/fs 2 14 14 34 lch lch rch rch sdti(i) 0 15 5 8 7 1 432 6 0 15 5 87 1 4 3 2 60 14 14 lch rch sdti(i) 15 2 1 0 15 210 14 14 lch rch lrck lrck (master) (slave) figure 20. mode 0 timing (bckp = ?0?, msbs = ?1?) rch lch bick ( 32fs ) sdto(o) 15 0 1 8 9 11 12 14 15 16 17 24 25 27 26 30 31 0 0 15 5 8 7 1 43 10 13 2 6 0 15 5 87 1 4 3 2 6 29 26 0 2 14 14 18 bick ( 64fs ) sdto(o) 15 0 1 14 15 17 18 30 31 32 33 46 47 49 50 62 63 15 2 1 16 0 15 21 0 48 15:msb, 0:lsb 1/fs 2 14 14 34 lch rch sdti(i) 0 15 5 8 7 1 432 6 0 15 5 87 1 4 3 2 60 14 14 lch rch sdti(i) 15 2 1 0 15 210 14 14 lch rch lrck lrck (master) (slave) figure 21. mode 0 timing (bckp = ?1?, msbs = ?1?)
[ak4645a] ms0986-e-00 2008/07 - 28 - lrck bick(32fs) sdto(o) sdti(i) 0 15 14 15 14 110 13 13 23 7 76543 210 6543 10 2 9 1112131415 0 12 3 15 14 13 1 0 15 15 76543 210 10 9 1112131415 bick(64fs) 0 116 2 3 17 18 31 0 1 2 3 1 0 16 17 18 31 sdto(o) sdti(i) 15 14 13 don't care 10 1 15 15 210 15 0 15 14 15 14 don't care 15:msb, 0:lsb lch data rch data 15 14 13 76543 10 2 15 14 13 10 figure 22. mode 1 timing lrck bick(32fs) sdto(o) sdti(i) 0 15 14 15 14 110 13 13 23 7 76543 210 6543 10 2 9 1112131415 0 12 3 15 14 13 1 0 15 15 76543 210 10 9 1112131415 bick(64fs) 0 116 2 3 17 18 31 0 1 2 3 1 0 16 17 18 31 sdto(o) sdti(i) 15 14 13 don't care 1 15 15 15 0 15 14 15 14 don't care 15:msb, 0:lsb lch data rch data 13 10 13 10 15 15 14 13 76543 10 2 15 14 13 10 figure 23. mode 2 timing
[ak4645a] ms0986-e-00 2008/07 - 29 - lrck bick(32fs) sdto(o) sdti(i) 0 15 14 15 14 110 23 7 76543 210 6543 10 2 9 1112131415 0 12 3 15 14 1 0 76543 210 10 9 1112131415 bick(64fs) 0 116 2 3 17 18 31 0 1 2 3 1 0 16 17 18 31 sdto(o) sdti(i) 15 14 don't care 2 15 1 15 15 15 don't care 15:msb, 0:lsb lch data rch data 14 21 14 21 8 8 8 0 0 0 0 0 15 14 76543 210 8 15 14 21 0 figure 24. mode 3 timing mono/stereo mode pmadl, pmadr and mix bits set mono/stereo adc operation. when mix bit = ?1?, eq and fil3 bits should be set to ?0?. alc operation (alc bit = ?1?) or digital volume operation (alc bit = ?0?) is applied to the data in table 12 . pmadl bit pmadr bit mix bit adc lch data adc rch data 0 0 x all ?0? all ?0? (default) 0 1 x rch input signal rch input signal 1 0 x lch input signal lch input signal 0 lch input signal rch input signal 1 1 1 (l+r)/2 (l+r)/2 table 12. mono/stereo adc operation (x: don?t care) digital high pass filter the ak4645a has a digital high pass filter for dc offset cancellation. the cut-off freque ncy of the hpf is 0.9hz (@fs=44.1khz) and scales with sampling rate (fs). when pmadl bit = ?1? or pmadr bit = ?1?, the hpf of adc is enabled but the hpf of dac is disabled. when pmadl=pm adr bits = ?0?, pmdac bit = ?1?, the hpf of dac is enabled but the hpf of adc is disabled.
[ak4645a] ms0986-e-00 2008/07 - 30 - mic/line input selector the ak4645a has input selector for mic-amp. when mdif1 and mdif2 bits are ?0?, inl1-0 and inr1-0 bits select lin1/lin2/lin3/lin4 and rin1/rin2/rin3/rin4, respectively. when mdif1 and mdif2 bits are ?1?, lin1, rin1, lin2 and rin2 pins become in1 ? , in1+, in2+ and in2 ? pins respectively. in this case, full-differential input is available ( figure 26 ). when full-differential input is used, the signal must not be input to the pins marked by ?x? in table 14 . mdif1 bit mdif2 bit inl1 bit inl0 bit inr1 bit inr0 bit lch rch 0 0 0 0 0 0 lin1 rin1 (default) 0 0 0 0 0 1 lin1 rin2 0 0 0 0 1 0 lin1 rin3 0 0 0 0 1 1 lin1 rin4 0 0 0 1 0 0 lin2 rin1 0 0 0 1 0 1 lin2 rin2 0 0 0 1 1 0 lin2 rin3 0 0 0 1 1 1 lin2 rin4 0 0 1 0 0 0 lin3 rin1 0 0 1 0 0 1 lin3 rin2 0 0 1 0 1 0 lin3 rin3 0 0 1 0 1 1 lin3 rin4 0 0 1 1 0 0 lin4 rin1 0 0 1 1 0 1 lin4 rin2 0 0 1 1 1 0 lin4 rin3 0 0 1 1 1 1 lin4 rin4 0 1 0 0 0 0 lin1 in2+/ ? 0 1 1 0 0 0 lin3 in2+/ ? 0 1 1 1 0 0 lin4 in2+/ ? 1 0 0 0 0 1 in1+/ ? rin2 1 0 0 0 1 0 in1+/ ? rin3 1 0 0 0 1 1 in1+/ ? rin4 1 1 0 0 0 0 in1+/ ? in2+/ ? others n/a n/a table 13. mic/line in path select register pin ain3 bit mdif1 bit mdif2 bit lin1 in1 ? rin1 in1+ lin2 in2+ rin2 in2 ? min lin3 rin3 lin4 in4+ rin4 in4 ? 0 0 0 o o o o o - o o 0 0 1 o x o o o - o x 0 1 0 o o x o o - x o 0 1 1 o o o o o - x x 1 0 0 o o o o o o o o 1 0 1 o x o o o x o x 1 1 0 o o x o x o x o 1 1 1 o o o o x x x x table 14. handling of mic/line input pins (? -?: n/a; ?x?: signal should not be input.)
[ak4645a] ms0986-e-00 2008/07 - 31 - lin1/in1 ? pin a dc lch rin1/in1+ pin inl1-0 bits mdif1 bit rin2/in2 ? pin a dc rch lin2/in2+ pin inr1-0 bits mdif2 bit ak4645a min/lin3 pin rin3 pin lineout, hp-amp mic-amp mic-amp micl3 bit micr3 bit pmainl3 bit pmainr3 bit pmainl2 bit pmainr2 bit pmainl4 bit pmainr4 bit lin4/in4+ pin rin4/in4 ? pin figure 25. mic/line input selector in1 ? pin in1+ pin mpwr pin ak4645a mic-amp 1k 1k a/d sdto pin figure 26. connection example for full-differential mic input (mdif1/2 bits = ?1?) in case that in1+/ ? pins are used as full-differential mic input and lin2/rin2 pins are used as stereo line input, it is recommended that the following two modes are se t by register setting according to each case. mdif1 bit mdif2 bit inl1 bit inl0 bit inr1 bit inr0 bit lch rch 1 0 0 0 0 1 in1+/ ? rin2 0 0 0 1 0 1 lin2 rin2 table 15. mic/line in path select example
[ak4645a] ms0986-e-00 2008/07 - 32 - mic gain amplifier the ak4645a has a gain amplifier for microphone input. the gain of mic-amp is selected by the mgain1-0 bits ( table 16 ). the typical input impedance is 60k (typ)@mgain1-0 bits = ?00? or 30k (typ)@mgain1-0 bits = ?01?, ?10? or ?11?. mgain1 bit mgain0 bit input gain 0 0 0db 0 1 +20db (default) 1 0 +26db 1 1 +32db table 16. mic input gain mic power when pmmp bit = ?1?, the mpwr pin supplies power for the microphone. this output voltage is typically 0.75 x avdd and the load resistance is minimum 0.5k . in case of using two sets of stereo mic, the load resistance is minimum 2k for each channel. capacitor must not be connected directly to mpwr pin ( figure 27 ). pmmp bit mpwr pin 0 hi-z (default) 1 output table 17. mic power mpwr pin figure 27. mic block circuit
[ak4645a] ms0986-e-00 2008/07 - 33 - digital eq/hpf/lpf the ak4645a performs wind-noise reduction filter, stereo separation emphasis, gain compensation and alc (automatic level control) by digital domain for a/d converted data ( figure 28 ). fil1, fil3 and eq blocks are iir filters of 1 st order. the filter coefficient of fil3, eq and fil1 blocks can be set to any value. refer to the section of ?alc operation? about alc. when only dac is powered-up, digital eq/hpf/lpf circuit operates at playback path. when only adc is powered-up or both adc and dac are powered-up, digital eq/hpf/lpf circuit operates at recording path. even if the path is switched from recording to playback, the register setting of f ilter coefficient at recording remains. therefore, fil3, eq, fil1 and gn1-0 bits should be set to ?0? if digital eq/hpf/lpf is not used for playback path. pmadl bit, pmadr bit pmdac bit loop bit status digital eq/hpf/lpf 0 x power-down power-down (default ) ?00? 1 x playback playback path ?01?, ?10? or ?11? 0 x recording recording path 0 recording & playback recording path 1 1 recording monitor playback recording path note 38. stereo separation emphasis circuit is effective only at stereo operation. table 18. digital eq/hpf/lpf cirtcuit setting (x: don?t care) fil3 coefficient also sets the attenua tion of the stereo separation emphasis. the combination of gn1-0 bit ( table 19 ) and eq coefficient set the compensation gain. fil1 and fil3 blocks become hpf when f1as and f3as b its are ?0? and become lpf when f1as and f3as bits are ?1?, respectively. when eq and fil1 bits are ?0?, eq and fil1 blocks become ?through? (0db). when fil3 bit is ?0?, fil3 block become ?mute?. when each filter coefficient is changed, each filter should be set to ?through? (?mute? in case of fil3). when mix bit = ?1?, only fil1 is available. in this case, eq and fil3 bits should be set to ?0?. fil3 fil1 eq gain alc gn1-0 +24/+12/0db an y co e ffi ci e n t f1a13-0 f1b13-0 f1as an y coefficient f3a13-0 f3b13-0 f3as an y coefficient eqa15-0 eqb13-0 eqc15-0 +12db 0db 0db -10db mu te (set by fil3 coefficient) wind-noise reduction stereo separation emphasis gain compensation figure 28. digital eq/hpf/lpf gn1 gn0 gain 0 0 0db (default) 0 1 +12db 1 x +24db table 19. gain select of gain block (x: don?t care)
[ak4645a] ms0986-e-00 2008/07 - 34 - [filter coefficient setting] 1) when fil1 and fil3 are set to ?hpf? fs: sampling frequency fc: cut-off frequency f: input signal frequency k: filter gain [db] (filter gain of should be set to 0db.) register setting fil1: f1as bit = ?0?, f1a[13:0] bits =a, f1b[13:0] bits =b fil3: f3as bit = ?0?, f3a[13:0] bits =a, f3b[13:0] bits =b (msb=f1a13, f1b13, f3a13, f3b 13; lsb=f1a0, f1b0, f3a0, f3b0) a = 10 k/20 x 1 / tan ( fc/fs) 1 + 1 / tan ( fc/fs) b = 1 ? 1 / tan ( fc/fs) 1 + 1 / tan ( fc/fs) , transfer function amplitude phase h(z) = a 1 ? z ? 1 1 + bz ? 1 m(f) = a 2 ? 2cos (2 f/fs) 1 + b 2 + 2bcos (2 f/fs) (f) = tan ? 1 (b+1)sin (2 f/fs) 1 - b + (b ? 1)cos (2 f/fs) 2) when fil1 and fil3 are set to ?lpf? fs: sampling frequency fc: cut-off frequency f: input signal frequency k: filter gain [db] (filter gain of fil1 should be set to 0db.) register setting fil1: f1as bit = ?1?, f1a[13:0] bits =a, f1b[13:0] bits =b fil3: f3as bit = ?1?, f3a[13:0] bits =a, f3b[13:0] bits =b (msb=f1a13, f1b13, f3a13, f3b 13; lsb=f1a0, f1b0, f3a0, f3b0) a = 10 k/20 x 1 1 + 1 / tan ( fc/fs) b = 1 ? 1 / tan ( fc/fs) 1 + 1 / tan ( fc/fs) , transfer function amplitude phase h(z) = a 1 + z ? 1 1 + bz ? 1 m(f) = a 2 + 2cos (2 f/fs) 1 + b 2 + 2bcos (2 f/fs) (f) = tan ? 1 (b ? 1)sin (2 f/fs) 1 + b + (b+1)cos (2 f/fs)
[ak4645a] ms0986-e-00 2008/07 - 35 - 3) eq fs: sampling frequency fc 1 : pole frequency fc 2 : zero-point frequency f: input signal frequency k: filter gain [db] (maximum +12db) register setting eqa[15:0] bits =a, eqb[13:0] bits =b, eqc[15:0] bits =c (msb=eqa15, eqb13, eqc15; lsb=eqa0, eqb0, eqc0) a = 10 k/20 x 1 + 1 / tan ( fc 2 /fs) 1 + 1 / tan ( fc 1 /fs) b = 1 ? 1 / tan ( fc 1 /fs) 1 + 1 / tan ( fc 1 /fs) , c =10 k/20 x 1 ? 1 / tan ( fc 2 /fs) 1 + 1 / tan ( fc 1 /fs) , transfer function amplitude phase h(z) = a + cz ? 1 1 + bz ? 1 m(f) = a 2 + c 2 + 2accos (2 f/fs) 1 + b 2 + 2bcos (2 f/fs) (f) = tan ? 1 (ab ? c)sin (2 f/fs) a + bc + (ab+c)cos (2 f/fs) [translation the filter coefficient calculate d by the equations above fro m real number to binary code (2?s complement)] x = (real number of filter coefficient calculated by the equations above) x 2 13 x should be rounded to integer, and then should be translated to binary code (2?s complement). msb of each filter coefficient se tting register is sine bit. [filter coefficient setting example] 1) fil1 block example: hpf, fs=44.1khz, fc=100hz f1as bit = ?0? f1a[13:0] bits = 01 1111 1100 0110 f1b[13:0] bits = 10 0000 0111 0100 2) eq block example: fs=44.1khz, fc 1 =300hz, fc 2 =3000hz, gain=+8db gain[db] +8db fc 1 fc 2 frequency eqa[15:0] bits = 0000 1001 0110 1110 eqb[13:0] bits = 10 0001 0101 1001 eqc[15:0] bits = 1111 1001 1110 1111
[ak4645a] ms0986-e-00 2008/07 - 36 - alc operation the alc (automatic level control) is operated by alc bl ock when alc bit is ?1?. when only dac is powered-up, alc circuit operates at playback path. when only adc is powered-up or both adc and dac are powered-up, alc circuit operates at recording path. pmadl bit, pmadr bit pmdac bit loop bit status digital eq/hpf/lpf 0 x power-down power-down (default) ?00? 1 x playback playback path 0 x recording recording path 0 recording & playback recording path ?01?, ?10? or ?11? 1 1 recording monitor playback recording path table 20. alc setting (x: don?t care) 1. alc limiter operation during the alc limiter operation, when either lch or rch exceeds the alc limiter detection level ( table 21 ), the ivl and ivr values (same value) are attenuated automatically by the amount defined by the alc limiter att step ( table 22 ). the ivl and ivr are then set to the same value for both channels. when zelmn bit = ?0? (zero cross detec tion is enabled), the ivl and ivr valu es are changed by alc limiter operation at the individual zero crossing points of lch and rch or at the zero crossing timeout. ztm1-0 bits set the zero crossing timeout period of both alc lim iter and recovery operation ( table 23 ). when zelmn bit = ?1? (zero cross detection is disabled), ivl and ivr values are immediately (period: 1/fs) changed by alc limiter operation. attenuation step is fixed to 1 step regardless of the setting of lmat1-0 bits. the attenuation operation is executed c ontinuously until the input signal level becomes alc limiter detection level ( table 21 ) or less. after completing the attenuate operation, unless alc bit is changed to ?0?, the operation repeats when the input signal level exceeds lmth1-0 bits. lmth1 lmth0 alc limier detection level alc recovery waiting counter reset level 0 0 alc output ? 2.5dbfs ? 2.5dbfs > alc output ? 4.1dbfs (default) 0 1 alc output ? 4.1dbfs ? 4.1dbfs > alc output ? 6.0dbfs 1 0 alc output ? 6.0dbfs ? 6.0dbfs > alc output ? 8.5dbfs 1 1 alc output ? 8.5dbfs ? 8.5dbfs > alc output ? 12dbfs table 21. alc limiter detection leve l / recovery counter reset level zelmn lmat1 lmat0 alc limiter att step 0 0 1 step 0.375db (default) 0 1 2 step 0.750db 1 0 4 step 1.500db 0 1 1 8 step 3.000db 1 x x 1step 0.375db table 22. alc limiter att step (x: don?t care) zero crossing timeout period ztm1 ztm0 8khz 16khz 44.1khz 0 0 128/fs 16ms 8ms 2.9ms (default) 0 1 256/fs 32ms 16ms 5.8ms 1 0 512/fs 64ms 32ms 11.6ms 1 1 1024/fs 128ms 64ms 23.2ms table 23. alc zero crossing timeout period
[ak4645a] ms0986-e-00 2008/07 - 37 - 2. alc recovery operation the alc recovery operation waits for the wtm2-0 bits ( table 24 ) to be set after completing the alc limiter operation. if the input signal does not exceed ?alc r ecovery waiting counter reset level? ( table 21 ) during the wait time, the alc recovery operation is executed. the ivl and ivr values are automatically incremen ted by rgain1-0 bits ( table 25 ) up to the set reference level ( table 26 ) with zero crossing detection which timeout period is set by ztm1-0 bits ( table 23 ). then the ivl and ivr are set to the same value for both channels. the alc recove ry operation is executed at a period set by wtm2-0 bits. when zero cross is detected at both channels during the wait period set by wtm2-0 bits, the alc recovery operation waits until wtm2-0 pe riod and the next recovery operation is executed. if ztm1-0 is longer than wtm2-0 and no zero crossing occurs, the alc recovery operation is executed at a period set by ztm1-0 bits. for example, when the current ivol value is 30h and rgain1 -0 bits are set to ?01?, ivol is changed to 32h by the auto limiter operation and then the input signal level is ga ined by 0.75db (=0.375db x 2). when the ivol value exceeds the reference level (ref7-0), the ivol values are not increased. when ?alc recovery waiting counter reset level (lmth1-0) output signal < alc limiter detection level (lmth1-0)? during the alc recovery operation, the waiting timer of alc recovery operation is reset. when ?alc recovery waiting counter reset level (lmth1-0) > output signal?, the waiting timer of alc recovery operation starts. the alc operation corresponds to the impulse noise. when the impulse noise is input, the alc recovery operation becomes faster than a normal recovery operation (fast rec overy operation). when large noise is input to microphone instantaneously, the quality of small level in the large noise can be improved by this fast recovery operation. the speed of fast recovery operation is set by rfst1-0 bits ( table 27 ). alc recovery operation waiting period wtm2 wtm1 wtm0 8khz 16khz 44.1khz 0 0 0 128/fs 16ms 8ms 2.9ms (default) 0 0 1 256/fs 32ms 16ms 5.8ms 0 1 0 512/fs 64ms 32ms 11.6ms 0 1 1 1024/fs 128ms 64ms 23.2ms 1 0 0 2048/fs 256ms 128ms 46.4ms 1 0 1 4096/fs 512ms 256ms 92.9ms 1 1 0 8192/fs 1024ms 512ms 185.8ms 1 1 1 16384/fs 2048ms 1024ms 371.5ms table 24. alc recovery operation waiting period rgain1 rgain0 gain step 0 0 1 step 0.375db (default) 0 1 2 step 0.750db 1 0 3 step 1.125db 1 1 4 step 1.500db table 25. alc recovery gain step
[ak4645a] ms0986-e-00 2008/07 - 38 - ref7-0 gain(db) step f1h +36.0 f0h +35.625 efh +35.25 : : e2h +30.375 e1h +30.0 (default) e0h +29.625 : : 03h ? 53.25 02h ? 53.625 01h ? 54.0 0.375db 00h mute table 26. reference level at alc recovery operation rfst1 bit rfst0 bit recovery speed 0 0 4 times (default) 0 1 8 times 1 0 16times 1 1 n/a table 27. fast recovery speed setting
[ak4645a] ms0986-e-00 2008/07 - 39 - 3. example of alc operation table 28 shows the examples of the alc setting for mic recording. fs=8khz fs=44.1khz register name comment data operation data operation lmth1-0 limiter detection level 01 ? 4.1dbfs 01 ? 4.1dbfs zelmn limiter zero crossing det ection 0 enable 0 enable ztm1-0 zero crossing timeout period 01 32ms 11 23.2ms wtm2-0 recovery waiting period *wtm2-0 bits should be the same or longer data as ztm1-0 bits. 001 32ms 011 23.2ms ref7-0 maximum gain at recovery operation e1h +30db e1h +30db ivl7-0, ivr7-0 gain of ivol e1h +30db e1h +30db lmat1-0 limiter att step 00 1 step 00 1 step rgain1-0 recovery gain step 00 1 step 00 1 step rfst1-0 fast recovery speed 00 4 times 00 4 times alc alc enable 1 enable 1 enable table 28. example of the alc setting the following registers should not be changed during the al c operation. these bits should be changed after the alc operation is finished by alc bit = ?0? or pmadl=pmadr bits = ?0?. ? lmth1-0, lmat1-0, wtm2-0, ztm1-0, rgain1-0, ref7-0, zelmn, rfst1-0 manual mode * the value of ivol should be the same or smaller than ref?s wr (ztm1-0, wtm2-0, rfst1-0) wr (ref7-0) wr (ivl/r7-0) wr (lmat1-0, rgain0, zelmn, lmth0; alc= ?1?) example: limiter = zero crossing enable recovery cycle = 32ms@8khz zero crossing timeout period = 32ms@8khz limiter and recovery step = 1 fast recovery speed = 4 step gain of ivol = +30db maximum gain = +30.0db limiter detection level = ? 4.1dbfs alc bit = ?1? (1) addr=06h, data=14h (2) addr=08h, data=e1h (5) addr=07h, data=21h (3) addr=09h&0ch, data=e1h alc operation wr (rgain1, lmth1) (4) addr=0bh, data=00h note : wr : write figure 29. registers set-up sequence at alc operation
[ak4645a] ms0986-e-00 2008/07 - 40 - input digital volume (manual mode) the input digital volume becomes manual mode when alc bit is ?0?. this mode is used in the case shown below. 1. after exiting reset state, set-up the registers for the alc operation (ztm1-0, lmth1-0 and etc) 2. when the registers for the alc operation (limiter period, recovery period and etc) are changed. for example; when the change of the sampling frequency. 3. when ivol is used as a manual volume. ivl7-0 and ivr7-0 bits set the gain of the volume control ( table 29 ). the ivol value is changed at zero crossing or timeout. zero crossing timeout period is set by ztm1-0 bits. if ivl7-0 or ivr7-0 bits are written during pmadl=pmadr bits = ?0?, ivol operation starts with the written values at the end of the adc initialization cycle after pmadl or pmadr bit is changed to ?1?. even if the path is switched from recording to playback, th e register setting of ivol remains. therefore, ivl7-0 and ivr7-0 bits should be set to ?91h? (0db). ivl7-0 ivr7-0 gain (db) step f1h +36.0 f0h +35.625 efh +35.25 : : e2h +30.375 e1h +30.0 (default) e0h +29.625 : : 03h ? 53.25 02h ? 53.625 01h ? 54 0.375db 00h mute table 29. input digital volume setting
[ak4645a] ms0986-e-00 2008/07 - 41 - when writing to the ivl7-0 and ivr7-0 b its continuouslly, the control register shoul d be written by an interval more than zero crossing timeout. if not, ivl and ivr are not changed since zero crossing counter is reset at every write operation. if the same register value as the previous write operation is written to ivl and ivr, zero crossing counter is not reset. therefore, ivl and ivr can be written by an interval less than zero crossing timeout. a lc bit a lc status disable enable disable ivl7-0 bits e1h(+30db) ivr7-0 bits c6h(+20db) internal ivl e1h(+30db) e1(+30db) --> f1(+36db) e1(+30db) internal ivr c6h(+20db) e1(+30db) --> f1(+36db) c6h(+20db) (1) (2) figure 30. ivol value during alc operation (1) the ivl value becomes the st art value if the ivl and ivr are different when the alc starts. the wait time from alc bit = ?1? to alc operation start by ivl7-0 bits is at most recovery time (wtm2-0 bits) plus zerocross timeout period (ztm1-0 bits). (2) writing to ivl and ivr registers (09h and 0ch) is ignored during alc operation. after alc is disabled, the ivol changes to the last written data by zero crossing or timeout. when alc is enable d again, alc bit should be set to ?1? by an interval more than zero crossi ng timeout period after alc bit = ?0?.
[ak4645a] ms0986-e-00 2008/07 - 42 - de-emphasis filter the ak4645a includes the digital de-emphasis filter (tc = 50/15 s) by iir filter. setting the dem1-0 bits enables the de-emphasis filter ( table 30 ). dem1 dem0 mode 0 0 44.1khz 0 1 off (default) 1 0 48khz 1 1 32khz table 30. de-emphasis control bass boost function the bst1-0 bits control the amount of low frequency boost applied to the dac output signal ( table 31 ). if the bst1-0 bits are set to ?01? (min level), use a 47 f capacitor for ac-coupling. if the booste d signal exceeds full scale, the analog output clips to the full scale. figure 31 shows the boost frequency response at ?20db signal input. boost filter (fs=44.1khz) -25 -20 -15 -10 -5 0 10 100 1000 10000 frequency [hz] level [db] max mid min figure 31. bass boost frequency response (fs=44.1khz) bst1 bst0 mode 0 0 off (default) 0 1 min 1 0 mid 1 1 max table 31. bass boost control
[ak4645a] ms0986-e-00 2008/07 - 43 - digital output volume the ak4645a has a digital output volume (256 levels, 0.5db step, mute). the volume can be set by the dvl7-0 and dvr7-0 bits. the volume is included in front of the dac block. the input data of dac is changed from +12 to ?115db or mute. when the dvolc bit = ?1?, the dvl7-0 bits control both lch and rch attenuation levels. when the dvolc bit = ?0?, the dvl7-0 bits control lch level and dvr7-0 b its control rch level. this volume has a soft transition function. the dvtm bit sets the transition time between set values of dvl/r7-0 bits as either 1061/fs or 256/fs ( table 33 ). when dvtm bit = ?0?, a soft transition between the set values occurs (1062 levels). it takes 1061/fs (=24ms@fs=44.1khz) from 00h (+12db) to ffh (mute). dvl/r7-0 gain step 00h +12.0db 01h +11.5db 02h +11.0db : : 18h 0db (default) : : fdh ? 114.5db feh ? 115.0db 0.5db ffh mute ( ? ) table 32. digital volume code table transition time between dvl/r7-0 bits = 00h and ffh dvtm bit setting fs=8khz fs=44.1khz 0 1061/fs 133ms 24ms (default) 1 256/fs 32ms 6ms table 33. transition time setting of digital output volume
[ak4645a] ms0986-e-00 2008/07 - 44 - soft mute soft mute operation is performed in the digital domain. when the smute bit goes to ?1?, the output signal is attenuated by ? (?0?) during the cycle set by the dvtm bit. when the smute bit is returned to ?0?, the mute is cancelled and the output attenuation gradually changes to the value set by the dvl/r7-0 bits during the cycle set of the dvtm bit. if the soft mute is cancelled within the cycle set by the dvtm bit after starting the operation, the attenuation is discontinued and returned to the value set by the dvl/r7-0 bits. the soft mute is effective for changing the signal source without stopping the signal transmission ( figure 32 ). smute bit a ttenuation dvtm bit dvl/r7-0 bits - dvtm bit gd gd (1) (2) (3) a nalog output figure 32. soft mute function (1) the output signal is attenuated until ? (?0?) by the cycle set by the dvtm bit. (2) analog output corresponding to digital input has group delay (gd). (3) if the soft mute is cancelled within the cycle set by the dvtm bit, the attenuation is discounted and returned to the value set by the dvl/r7-0 bits.
[ak4645a] ms0986-e-00 2008/07 - 45 - analog mixing: stereo input (lin2/rin2/lin 4/rin4, ain3 bit = ?1?: lin3/rin3 pins) when pmainl2=pmainr2 bits = ?1?, lin2 and rin2 pins can be used as stereo line input for analog mixing. when linh2 and rinh2 bits are set to ?1?, the input signal from the lin2/rin2 pins is output to headphone-amp. when linl2/rinr2 bits are set to ?1?, the input signal from the lin2/rin2 pins is output to the stereo line output amplifier. when pmainl4=pmainr4 bits = ?1?, lin4 and rin4 pins can be used as stereo line input for analog mixing. when linh4 and rinh4 bits are set to ?1?, the input signal from the lin4/rin4 pins is output to headphone-amp. when linl4/rinr4 bits are set to ?1?, the input signal from the lin4/rin4 pins is output to the stereo line output amplifier. when the analog mixing is used, a/d converter is also available if pmadl or pmadr bit is ?1?. in this case, the input resistance of lin2/rin2/lin4/rin4 pins becomes 30k (typ) at mgain1-0 bits = ?00? and 20k (typ) at mgain1-0 bits = ?01?, ?10? or ?11?, respectively. when ain3 bit = ?1?, min and vcoc pins becomes lin3 and rin3 pins, respectively. when pmainl3=pmainr3 bits = ?1?, lin3 and rin3 pins can be used as stereo line input for analog mixing. when pmmicl=pmmicr=micl3=micr3 bits = ?1?, analog mixing source is changed from lin3/rin3 iput to mic-amp output signal. when the linh3 and rinh3 bits are set to ?1?, the input signal from the lin3/rin3 pins is output to headphone-amp. when the linl3/rinr3 bits are set to ?1?, the input signal from the lin3/rin3 pins is output to the stereo line output amplifier. when the analog mixing is used, a/d converter is also available if pmadl or pmadr bit is ?1?. when the analog mixing is used at micl3=micr3 bits = ?0?, the input resistance of lin3/rin3 pins becomes 30k (typ) at mgain1-0 bits = ?00? and 20k (typ) at mgain1-0 bits = ?01?, ?10? or ?11?, respectively. when the analog mixing is used at micl3=micr3 bits = ?1?, the input resistance of lin3/rin3 pins becomes 60k (typ) at mgain1-0 bits = ?00? and 30k (typ) at mgain1-0 bits = ?01?, ?10? or ?11?, respectively. table 34 , table 35 and table 36 show the typical gain. lin1/in1 ? pin a dc lch rin1/in1+ pin inl1-0 bits mdif1 bit rin2/in2 ? pin a dc rch lin2/in2+ pin inr1-0 bits mdif2 bit ak4645a min/lin3 pin rin3 pin lineout, hp-amp mic-amp mic-amp micl3 bit micr3 bit pmainl3 bit pmainr3 bit pmainl2 bit pmainr2 bit pmainl4 bit pmainr4 bit lin4/in4+ pin rin4/in4 ? pin figure 33. analog mixing circuit (stereo input)
[ak4645a] ms0986-e-00 2008/07 - 46 - pmainl2 bit pmainr2 bit lout/lop pin, rout/lon pin linl2/rinr2 hpl, hpr pins linh2/rinh2 lin2/rin2 figure 34. analog mixing circuit (lin2/rin2) pmainl4 bit pmainr4 bit lout/lop pin, rout/lon pin linl4/rinr4 hpl, hpr pins linh4/rinh4 lin4/rin4 figure 35. analog mixing circuit (lin4/rin4) pmainl3 bit pmainr3 bit lout/lop pin, rout/lon pin linl3/rinr3 hpl, hpr pins linh3/rinh3 lin3/rin3 figure 36. analog mixing circuit (lin3/rin3) lovl bit lin2/rin2/lin3/rin3/lin4/rin4 ? lout/rout 0 0db (default) 1 +2db table 34. lin2/rin2/lin3/rin3/lin4/rin4 input ? lout/rout output gain (typ) lovl bit lin2/rin2/lin3/rin3/lin4/rin4 ? lop/lon 0 0db (default) 1 +2db table 35. lin2/rin2/lin3/rin3/lin4/rin4 input ? lop/lon output gain (typ) hpg bit lin2/rin2/lin3/rin3/lin4/rin4 ? hpl/hpr 0 0db (default) 1 +3.6db table 36. lin2/rin2/lin3/rin3/lin4/rin4 input ? headphone-amp output gain (typ)
[ak4645a] ms0986-e-00 2008/07 - 47 - analog mixing: full-differentical m ono input (l4dif bit = ?1?: in4+/in4 ? pins) when l4dif bit = ?1?, lin4 and rin4 pins becomes in4+ and in4 ? pins, respectively. when pmainl4 bit = ?1?, in4+ and in4 ? pins can be used as full-differentinal mono line input for analog mixing. when the linh4 and rinh4 bits are set to ?1?, the input signal from the in4+/in4 ? pins is output to headphone-amp. when the linl4/rinr4 bits are set to ?1?, the input signal from the in4+/in4 ? pins is output to the stereo line output amplifier. table 37 , table 38 and table 39 show the typical gain. input signa l amplitude is defined as (in4+) ? (in4 ? ). lin4/in4+ pin mic-amp lch rin4/in4 ? pin l4dif bit ak4645a lineout, hp-amp pmainl4 bit pmainr4 bit mic-amp rch figure 37. full-differential mono analog mixing circuit lovl bit in4+/in4 ? ? lout/rout 0 ? 6db (default) 1 ? 4db table 37. in4+/in4 ? input ? lout/rout output gain (typ) lovl bit in4+/in4 ? ? lop/lon 0 0db (default) 1 +2db table 38. in4+/in4 ? input ? lop/lon output gain (typ) hpg bit in4+/in4 ? ? hpl/hpr 0 ? 6db (default) 1 ? 2.4db table 39. in4+/in4 ? input ? headphone-amp output gain (typ)
[ak4645a] ms0986-e-00 2008/07 - 48 - analog mixing: mono input (ain3 bit = ?0?: min pin) when ain3 bit = ?0?, the min pin is used as mono input for analog mixing. when the pmmin bit is set to ?1?, the mono input is powered-up. when the minh bit is set to ?1?, the input signal from the min pin is output to headphone-amp. when the minl bit is set to ?1?, the input signal from the min pin is output to the stereo line output amplifier. the external resister ri adjusts the signal level of min input. table 40 , table 41 and table 42 show the typical gain example at r i = 20k . this gain is in inverse proportion to r i . min ri lout/lop pin, rout/lon pin minl hpl, hpr pin minh figure 38. block diagram of min pin lovl bit min ? lout/rout 0 0db (default) 1 +2db table 40. min input ? lout/rout output gain (typ) at r i = 20k lovl bit min ? lop/lon 0 +6db (default) 1 +8db table 41. min input ? lop/lon output gain (typ) at r i = 20k hpg bit min ? hpl/hpr 0 ? 20db (default) 1 ? 16.4db table 42. min input ? headphone-amp output gain (typ) at r i = 20k
[ak4645a] ms0986-e-00 2008/07 - 49 - stereo line output (lout/rout pins) when dacl bit is ?1?, lch/rch signal of dac is output from the lout/rout pins which is single-ended. when dacl bit is ?0?, output signal is muted and lout/rout pins output vcom voltage. the load impedance is 10k (min.). when the pmlo=lops bits = ?0?, the stereo line output enters power-down mode and the output is pulled-down to avss by 100k (typ). when the lops bit is ?1 ?, stereo line output enters power-save mode. pop noise at power-up/down can be reduced by changing pmlo bit at lops bit = ?1?. in this case, output signal line should be pulled-down to avss by 20k after ac coupled as figure 40 . rise/fall time is 300ms(max) at c=1 f and avdd=3.3v. when pmlo bit = ?1? and lops bit = ?0 ?, stereo line output is in normal operation. lovl bit set the gain of stereo line output. when lom bit = ?1?, dac output signal is output to lout and rout pins as (l+r)/2 mono signal. when lom3 bit = ?1?, the signal selected by micl3 and micr3 bits (lin3/rin3 inputs or mic-amp outputs) to lout and rout pins as (l+r)/2 mono signal. dac ?dacl? lout pin rout pin ?lovl? figure 39. stereo line output lops pmlo mode lout/rout pin 0 0 power-down pull-down to avss (default) 1 normal operation normal operation 1 0 power-save fall down to avss 1 power-save rise up to vcom table 43. stereo line output mode select (x: don?t care) lovl gain output voltage (typ) 0 0db 0.6 x avdd (default) 1 +2db 0.757 x avdd table 44. stereo line output volume setting lout rout 1 f 220 20k figure 40. external circuit for stereo line output (in case of using pop reduction circuit)
[ak4645a] ms0986-e-00 2008/07 - 50 - pmlo bit lo p s bit lout, rout pins (1) (2) norm al output (3) (4) (5) (6) 300 m s 300 m s figure 41. stereo line output control sequence (in case of using pop reduction circuit) (1) set lops bit = ?1?. stereo line out put enters the power-save mode. (2) set pmlo bit = ?1?. stereo line output exits the power-down mode. lout and rout pins rise up to vcom voltage. rise time is 200ms (max 300ms) at c=1 f and avdd=3.3v. (3) set lops bit = ?0? after lout and rout pins rise up. stereo line output exits the power-save mode. stereo line output is enabled. (4) set lops bit = ?1?. stereo line output enters power-save mode. (5) set pmlo bit = ?0?. stereo line output enters power-down mode. lout and rout pins fall down to avss. fall time is 200ms (max 300ms) at c=1 f and avdd=3.3v. (6) set lops bit = ?0? after lout and rout pins fall down. stereo line output exits the power-save mode.
[ak4645a] ms0986-e-00 2008/07 - 51 - when ain3 bit = ?0?, dacl, minl, linl2, rinr2, linl4 and rinr4 bits controls each path switch. min path mixing gain is 0db(typ)@lovl bit = ?0? when the external input resistance is 20k . lin2, rin2, lin4, rin4 and dac pathe?s mixing gains are 0db(typ)@lovl bit = ?0?. lin4 pin 0db m i x linl4 bit min pin 0db minl bit 0db dacl bit dac lch lout pin lin2 pin 0db linl2 bit figure 42. lout mixing circuit (ain3 bit = ?0?, lovl bit = ?0?) rin4 pin 0db m i x rinr4 bit min pin 0db minl bit 0db dacl bit dac rch rout pin rin2 pin 0db rinr2 bit figure 43. rout mixing circuit (ain3 bit = ?0?, lovl bit = ?0?)
[ak4645a] ms0986-e-00 2008/07 - 52 - when ain3 bit = ?1?, dacl, linl2, rinr2, linl3, rinr 3, linl4, rinr4, micl3 and micr3 bits controls each path switch. all pathe?s mixing gains are 0db(typ)@lovl bit = ?0?. lin4 pin 0db m i x linl4 bit lin3 pin 0db linl3 bit 0db dacl bit lout pin micl3 bit lin1 pin mic-amp lch dac lch lin2 pin 0db linl2 bit figure 44. lout mixing circuit (ain3 bit = ?1?, lovl bit = ?0?) rin4 pin 0db m i x rinr4 bit rin3 pin 0db rinr3 bit 0db dacl bit rout pin micr3 bit rin1 pin mic-amp rch dac rch rin2 pin 0db rinr2 bit figure 45. rout mixing circuit (ain3 bit = ?1?, lovl bit = ?0?)
[ak4645a] ms0986-e-00 2008/07 - 53 - full-differential mono line output (lop/lon pins) when lodif bit = ?1?, lout/rout pins become lop/lon pins, respectively. lch/rch signal of dac or lin2/rin2/lin3/rin3/lin4/rin4 is output from the lop/lon pins which is full-differential as (l+r)/2 signal. the load impedance is 10k (min) for lop and lon pins, respectively. when the pmlo bit = ?0?, the mono line output enters power-down mode and the output is hi-z. when the pmlo bit is ?1? and lops bit is ?1?, mono line output enters power-save mode. pop noise at power-up/down can be reduced by changing pmlo bit at lops bit = ?0?. when pmlo bit = ?1? and lops bit = ?0?, mono line output enters in normal operation. lovl bit set the gain of mono line output. when l4dif=lodif bits = ?1?, full-differential output signal is as follows: (lop) ? (lon) = (in4+) ? (in4 ? ). dac ?dacl? lop pin lon pin ?lovl? figure 46. mono line output pmlo lops mode lop lon 0 x power-down hi-z hi-z 1 power-save hi-z vcom/2 (default) 1 0 normal operation normal operation normal operation table 45. mono line output mode setting (x: don?t care) lovl gain output voltage (typ) 0 +6db 1.2 x avdd (default) 1 +8db 1.5 x avdd table 46. mono line ou tput volume setting pmlo bit lops bit lop pin lon pin vcom vcom hi-z hi-z hi-z hi-z figure 47. power-up/power-down timing for mono line output
[ak4645a] ms0986-e-00 2008/07 - 54 - when ain3 bit = ?0?, dacl, minl, linl2, rinr2, linl4 and rinr4 bits controls each path switch. min path mixing gain is +6db(typ)@lovl bit = ?0? when the external input resistance is 20k . lin2, rin2, lin4, rin4 and dac pathes mixing gain is 0db(typ)@lovl bit = ?0?. lin4 pin 0db m i x linl4 bit min pin 0db rinr4 bit +6db minl bit dac lch lop/n pin rin4 pin 0db dacl bit 0db dacl bit dac rch lin2 pin 0db linl2 bit 0db rinr2 bit rin2 pin figure 48. mono line output mixing circuit (ain3 bit = ?0?, lovl bit = ?0?) when ain3 bit = ?1?, dacl, linl2, rinr2, linl3, rinr 3, linl4, rinr4, micl3 and micr3 bits controls each path switch. all pathe?s mixing gains are 0db(typ)@lovl bit = ?0?. lin4 pin 0db m i x linl4 bit lin3 pin 0db linl3 bit 0db dacl bit lop/n pin micl3 bit lin1 pin mic-amp lch dac lch 0db dacl bit dac rch lin2 pin 0db linl2 bit rin4 pin 0db rinr4 bit rin3 pin 0db rinr3 bit micr3 bit rin1 pin mic-amp rch rin2 pin 0db rinr2 bit figure 49. mono line output mixing circuit (ain3 bit = ?1?, lovl bit = ?0?)
[ak4645a] ms0986-e-00 2008/07 - 55 - headphone output power supply voltage for the headphone-amp is supplie d from the hvdd pin and centered on the hvdd/2 voltage at vbat bit = ?0?. the load resistance is 16 (min). hpg bit selects the output voltage ( table 47 ). when hpm bit = ?1?, dac output signal is output to hpl and hpr pins as (l+r)/2 mono signal. when hpm3 bit = ?1?, the signal selected by micl3 and micr3 bits (lin3/rin3 inputs or mic-amp outputs) to hpl and hpr pins as (l+r)/2 mono signal. hpg bit 0 1 output voltage [vpp] 0.6 x avdd 0.91 x avdd table 47. headphone-amp output voltage when the hpmtn bit is ?0?, the common voltage of headphone-amp falls and the outputs (hpl and hpr pins) go to ?l? (hvss). when the hpmtn bit is ?1 ?, the common voltage rises to hvdd/2 at vbat bit = ?0?. a capacitor between the mutet pin and ground reduces pop noise at power-up. rise/fall time constant is in proportional to hvdd voltage and the capacitor at mutet pin. [example]: a capacitor between the mutet pin and ground = 1.0 f, hvdd=3.3v: rise/fall time constant: = 100ms(typ), 250ms(max) time until the common goes to hvss when hpmtn bit = ?1? ? ?0?: 500ms(max) when pmhpl and pmhpr bits are ?0?, the headphone-amp is powered-down, and the outputs (hpl and hpr pins) go to ?l? (hvss). pmhpl bit, pmhpr bit (1) (2) (4) (3) hpmtn bit hpl pin, hpr pin figure 50. power-up/power-down timing for headphone-amp (1) headphone-amp power-up (pmhpl, pmhpr b it = ?1?). the outputs are still hvss. (2) headphone-amp common voltage rises up (hpmtn bit = ?1?). common voltage of headphone-amp is rising. (3) headphone-amp common voltage falls down (hpmtn bit = ?0?). common voltage of headphone-amp is falling. (4) headphone-amp power-down (pmhpl, pmhpr bit = ?0?). the outputs are hvss. if the power supply is switched off or headphone-amp is powered-down before the common voltage goes to hvss, some pop noise occurs. when boost=off, the cut-off frequency (fc) of headphone-amp depends on the external resistor and capacitor. this fc can be shifted to lower freque ncy by using bass boost function. table 48 shows the cut off frequency and the output power for various resistor/capacitor combinations. the headphone impedance r l is 16 . output powers are shown at hvdd = 3.0, 3.3 and 5.0v. the output voltage of headphone is 0.6 x avdd (vpp) @hpg bit = ?0? and 0.91 x avdd (vpp) @hpg bit = ?1?. when an external resistor r is smaller than 12 , put an oscillation prevention circuit (0.22 f 20% capacitor and 10 ? 20% resistor) because it has the possi bility that headphone-amp oscillates.
[ak4645a] ms0986-e-00 2008/07 - 56 - ak4645a hp-amp 16 headphone 10 0.22 c r figure 51. external circuit example of headphone output power [mw]@0dbfs hpg bit r [ ] c [ f] fc [hz] boost =off fc [hz] boost =min @fs=44.1khz hvdd=3.0v avdd=3.0v hvdd=3.3v avdd=3.3v hvdd=5v avdd=3.3v 220 45 17 0 100 100 43 25.3 30.6 30.6 100 70 28 6.8 47 149 78 12.5 15.1 15.1 100 50 19 0 16 47 106 47 6.3 7.7 7.7 220 45 17 0 100 100 43 51 ( note 40 ) 62 ( note 40 ) 70 22 62 25 1 100 10 137 69 1.1 1.3 1.3 note 39. output power at 16 load. note 40. output signal is clipped. table 48. external circuit example when hvdd is directly supplied from the battery in a mobile phone system, rf noise may influences headphone output performance. when vbat bit is set to ?1?, hp-amp psrr for the noise applied to hvdd is reduced. in this case, hp-amp common voltage is 0.64 x avdd (typ). when avdd is 3.3v, common voltage is 2.1v. therefore, when hvdd voltage becomes lower than 4.2v, th e output signal will be clipped easily. vbat bit 0 1 common voltage [v] 0.5 x hvdd 0.64 x avdd table 49. hp-amp common voltage when pmvcm=pmhpl=pmhpr bits = ?0? and hpz bit = ?1?, hp-amp is powered-down and hpl/r pins are pulled-down to hvss by 200k (typ). in this setting, it is available to connect hp-amp of ak4645a and external single supply hp-amp by ?wired or?. in this mode, power supply current is 20 a(typ). pmvcm pmhpl/r hpmtn hpz mode hpl/r pins x 0 x 0 power-down & mute hvss (default) 0 0 x 1 power-down pull-down by 200k 1 1 0 x mute hvss 1 1 1 x normal operation normal operation table 50. hp-amp mode setting (x: don?t care)
[ak4645a] ms0986-e-00 2008/07 - 57 - hpl pin hpr pin headphone ak4645a a nothe r hp-amp figure 52. wired or with external hp-amp when ain3 bit = ?0?, dach, minh, linh2, rinh2, li nh4 and rinh4 bits controls each path switch. min path mixing gain is ? 20db(typ)@hpg bit = ?0? when the external input resistance is 20k . lin2, rin2, lin4, rin4 and dac pathes mixing gain is 0db(typ)@hpg bit = ?0?. lin4 pin 0db m i x linh4 bit min pin ? 20db minh bit 0db dach bit dac lch hpl pin lin2 pin 0db linh2 bit figure 53. hpl mixing circuit (ain3 bit = ?0?, hpg bit = ?0?) rin4 pin 0db m i x rinh4 bit min pin minh bit 0db dach bit dac rch hpr pin rin2 pin 0db rinh2 bit ? 20db figure 54. hpr mixing circuit (ain3 bit = ?0?, hpg bit = ?0?)
[ak4645a] ms0986-e-00 2008/07 - 58 - when ain3 bit = ?1?, dach, linh2, rinh2, linh3, rinh3 , linh4, rinh4, micl3 and micr3 bits controls each path switch. all pathe?s mixing gains are 0db(typ)@hpg bit = ?0?. lin4 pin 0db m i x linh4 bit lin3 pin 0db linh3 bit 0db dach bit hpl pin micl3 bit lin1 pin mic-amp lch dac lch lin2 pin 0db linh2 bit figure 55. hpl mixing circuit (ain3 bit = ?1?, hpg bit = ?0?) rin4 pin 0db m i x rinh4 bit rin3 pin 0db rinh3 bit 0db dach bit hpr pin micr3 bit rin1 pin mic-amp rch dac rch rin2 pin 0db rinh2 bit figure 56. hpr mixing circuit (ain3 bit = ?1?, hpg bit = ?0?)
[ak4645a] ms0986-e-00 2008/07 - 59 - serial control interface (1) 3-wire serial control mode (i2c pin = ?l?) internal registers may be written by usi ng the 3-wire p interface pins (csn, ccl k and cdti). the data on this interface consists of a 1-bit chip address (fixed to ?1?), read/write (fixed to ?1?), register address (msb first, 6bits) and control data (msb first, 8bits). each bit is clocked in on the rising edge (? ?) of cclk. address and data are latched on the 16th cclk rising edge (? ?) after csn falling edge(? ?). csn should be set to ?h? once after 16 cclks for each address. clock speed of cclk is 5mhz (max). the value of internal registers are initialized by pdn pin = ?l?. csn cclk 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 cdti c1 a5 a2 a3 a1 a0 a4 d7 d6 d5 d4 d3 d2 d1 d0 r/w c1: chip address; fixed to ?1? r/w: read/write (?1?: write, ?0?: read); fixed to ?1? a5-a0: register address d7-d0: control data ?1? ?1? clock, ?h? or ?l? clock, ?h? or ?l? ?h? or ?l? ?h? or ?l? figure 57. serial control i/f timing
[ak4645a] ms0986-e-00 2008/07 - 60 - (2) i 2 c-bus control mode (i2c pin = ?h?) the ak4645a supports the fast-mode i 2 c-bus (max: 400khz). pull-up resistors at sda and scl pins should be connected to (tvdd+0.3)v or less voltage. (2)-1. write operations figure 58 shows the data transfer sequence for the i 2 c-bus mode. all commands are preceded by start condition. a high to low transition on the sda line while scl is high indicates start condition ( figure 64 ). after the start condition, a slave address is sent. this address is 7 bits long followed by the eighth bit that is a data direction bit (r/w). the most significant six bits of the slave address are fixed as ?001001?. the next bit is cad0 (device address bit). this bit identifies the specific device on the bus. the hard-wired input pin (cad0 pin) sets these device address bits ( figure 59 ). if the slave address matches that of the ak4645a, th e ak4645a generates an acknowledge and the operation is executed. the master must generate the acknowledge-relate d clock pulse and release the sda line (high) during the acknowledge clock pulse ( figure 65 ). r/w bit value of ?1? indicates that the r ead operation is to be executed. ?0? indicate that the write operation is to be executed. the second byte consists of the control register address of the ak4645a. the format is msb first, and those most significant 2-bits are fixed to zeros ( figure 60 ). the data after the second byte contains control data. the format is msb first, 8bits ( figure 61 ). the ak4645a generates an acknowledge after each byte has been received. a data transfer is always terminated by stop condition generated by the master. a low to high transition on the sda line while scl is high defines stop condition ( figure 64 ). the ak4645a can perform more than one byte write operati on per sequence. after receiving the third byte the ak4645a generates an acknowledge and awaits the next data. the master can transmit more than one byte instead of terminating the write cycle after the first data byte is transferred. after r eceiving each data packet the inte rnal 6-bit address counter is incremented by one, and the next data is automatically taken into the next addr ess. if the address exceeds 24h prior to generating stop condition, the address c ounter will ?roll over? to 00h and the previous data will be overwritten. the data on the sda line must remain stable during the high period of the clock. high or low state of the data line can only change when the clock signal on the scl line is low ( figure 66 ) except for the start and stop conditions. sda slave address s s t a r t r/w="0" a c k sub address(n) a c k data(n) a c k data(n+1) a c k a c k data(n+x) a c k p s t o p figure 58. data transfer sequence at the i 2 c-bus mode 0 0 1 0 0 1 cad0 r/w (those cad1/0 should match with cad1/0 pins) figure 59. the first byte 0 0 a5 a4 a3 a2 a1 a0 figure 60. the second byte d7 d6 d5 d4 d3 d2 d1 d0 figure 61. byte structure after the second byte
[ak4645a] ms0986-e-00 2008/07 - 61 - (2)-2. read operations set the r/w bit = ?1? for the read operation of the ak4645a. after transmission of data, the master can read the next address?s data by generating an acknowledge instead of terminating the write cycle. after receiving each data packet the internal 6-bit address counter is incremented by one, and the ne xt data is automatically taken into the next address. if the address exceeds 24h prior to generating a stop condition, the a ddress counter will ?roll over? to 00h and the data of 00h will be read out. the ak4645a supports two basic read operations: current address read and random address read. (2)-2-1. current address read the ak4645a contains an internal address counter that maintains the address of the last word accessed, incremented by one. therefore, if the last access (either a read or write) were to address ?n ?, the next current read operation would access data from the address ?n+1?. after receiving the slave address with r/w bit set to ?1?, the ak4645a generates an acknowledge, transmits 1-byte of data to the address set by the internal address counter and increments the internal address counter by 1. if the master doe s not generate an acknowledge but inst ead generates stop condition, the ak4645a ceases transmission. sda slave address s s t a r t r/w="1" a c k a c k data(n+1) a c k data(n+2) a c k a c k data(n+x) a c k p s t o p data(n) figure 62. current address read (2)-2-2. random address read the random read operation allows the master to access any memo ry location at random. prior to issuing the slave address with the r/w bit set to ?1?, the master must first perform a ?dummy? write operation. the master issues a start request, a slave address (r/w bit = ?0?) and then the register address to read. after the register address is acknowledged, the master immediately reissues the start request and the slave address with the r/w bit set to ?1?. the ak4645a then generates an acknowledge, 1 byte of data and increments the internal a ddress counter by 1. if the master does not generate an acknowledge but instead generates stop c ondition, the ak4645a ceases transmission. sda slave address s s t a r t r/w="0" a c k a c k a c k data(n) a c k data(n+x) a c k p s t o p sub address(n) s slave address r/w="1" s t a r t data(n+1) a c k a c k figure 63. random address read
[ak4645a] ms0986-e-00 2008/07 - 62 - scl sda stop condition start condition s p figure 64. start and stop conditions scl from master acknowledge data output by transmitter data output by receiver 1 9 8 start condition not acknowledge clock pulse for acknowledgement s 2 figure 65. acknowledge on the i 2 c-bus scl sda data line stable; data valid change of data allowed figure 66. bit transfer on the i 2 c-bus
[ak4645a] ms0986-e-00 2008/07 - 63 - register map addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h power management 1 0 pmvcm pmmin 0 pmlo pmdac 0 pmadl 01h power management 2 hpz hpmtn pmhpl pmhpr m/s 0 0 0 02h signal select 1 0 0 0 dacl 0 pmmp 0 mgain0 03h signal select 2 lovl lops mgain1 0 0 minl 0 0 04h mode control 1 0 0 0 0 bcko 0 dif1 dif0 05h mode control 2 0 0 fs3 msbs bckp fs2 fs1 fs0 06h timer select dvtm wtm2 ztm1 ztm0 wtm1 wtm0 rfst1 rfst0 07h alc mode control 1 0 0 alc zelmn lmat1 lmat0 rgain0 lmth0 08h alc mode control 2 ref7 ref6 ref5 ref4 ref3 ref2 ref1 ref0 09h lch input volume control ivl7 ivl6 ivl5 ivl4 ivl3 ivl2 ivl1 ivl0 0ah lch digital volume control dvl7 dvl6 dvl5 dvl4 dvl3 dvl2 dvl1 dvl0 0bh alc mode control 3 rgain1 lmth1 0 0 0 0 vbat 0 0ch rch input volume control ivr7 ivr6 ivr5 ivr4 ivr3 ivr2 ivr1 ivr0 0dh rch digital volume control dvr7 dvr6 dvr5 dvr4 dvr3 dvr2 dvr1 dvr0 0eh mode control 3 0 loop sm ute dvolc bst1 bst0 dem1 dem0 0fh mode control 4 0 0 0 0 ivolc hpm minh dach 10h power management 3 inr1 inl1 hpg mdif2 mdif1 inr0 inl0 pmadr 11h digital filter select gn1 gn0 0 fil1 eq fil3 0 0 12h fil3 co-efficient 0 f3a7 f3a6 f3a5 f3a4 f3a3 f3a2 f3a1 f3a0 13h fil3 co-efficient 1 f3as 0 f3a13 f3a12 f3a11 f3a10 f3a9 f3a8 14h fil3 co-efficient 2 f3b7 f3b6 f3b5 f3b4 f3b3 f3b2 f3b1 f3b0 15h fil3 co-efficient 3 0 0 f3b13 f3b12 f3b11 f3b10 f3b9 f3b8 16h eq co-efficient 0 eqa7 eqa6 e qa5 eqa4 eqa3 eqa2 eqa1 eqa0 17h eq co-efficient 1 eqa15 eqa1 4 eqa13 eqa12 eqa11 eqa10 eqa9 eqa8 18h eq co-efficient 2 eqb7 eqb6 eq b5 eqb4 eqb3 eqb2 eqb1 eqb0 19h eq co-efficient 3 0 0 eqb13 eqb12 eqb11 eqb10 eqb9 eqb8 1ah eq co-efficient 4 eqc7 eqc6 eq c5 eqc4 eqc3 eqc2 eqc1 eqc0 1bh eq co-efficient 5 eqc15 eqc14 e qc13 eqc12 eqc11 eqc10 eqc9 eqc8 1ch fil1 co-efficient 0 f1a7 f1a6 f1a5 f1a4 f1a3 f1a2 f1a1 f1a0 1dh fil1 co-efficient 1 f1as 0 f1a13 f1a12 f1a11 f1a10 f1a9 f1a8 1eh fil1 co-efficient 2 f1b7 f1b6 f1b5 f1b4 f1b3 f1b2 f1b1 f1b0 1fh fil1 co-efficient 3 0 0 f1b13 f1b12 f1b11 f1b10 f1b9 f1b8 20h power management 4 pmainr4 pmainl4 pmainr3 pmainl3 pmainr2 pmainl2 pmmicr pmmicl 21h mode control 5 0 0 micr3 micl3 l4dif mix ain3 lodif 22h lineout mixing select lom lom3 rinr4 linl4 rinr3 linl3 rinr2 linl2 23h hp mixing select 0 hpm3 rinh4 linh4 rinh3 linh3 rinh2 linh2 24h reserved 0 0 0 0 0 0 0 0 note 41. pdn pin = ?l? resets the registers to their default values. note 42. unused bits must contain a ?0? value.
[ak4645a] ms0986-e-00 2008/07 - 64 - register definitions addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h power management 1 0 pmvcm pmmin 0 pmlo pmdac 0 pmadl default 0 0 0 0 0 0 0 0 pmadl: mic-amp lch and adc lch power management 0: power-down (default) 1: power-up when the pmadl or pmadr bit is changed from ?0 ? to ?1?, the initialization cycle (1059/fs=24ms @44.1khz) starts. after initializing, digital data of the adc is output. pmdac: dac power management 0: power-down (default) 1: power-up pmlo: stereo line out power management 0: power-down (default) 1: power-up pmmin: min input power management 0: power-down (default) 1: power-up pmmin or pmainl3 bit should be set to ?1? for playback. pmvcm: vcom power management 0: power-down (default) 1: power-up when any blocks are powered-up, th e pmvcm bit must be set to ?1?. pmvcm bit can be set to ?0? only when all power management bits of 00h, 01h, 02h, 10h, 20h and mcko bits are ?0?. each block can be powered-down respectivel y by writing ?0? in each bit of this a ddress. when the pdn pin is ?l?, all blocks are powered-down regardless of setting of this address. in this case, register is initialized to the default value. when all power management bits are ?0? in the 00h, 01h, 02h, 10h and 20h addresses and mcko bit is ?0?, all blocks are powered-down. the register values remain unchanged. power supply current is 20 a(typ) in this case. for fully shut down (typ. 1 a), the pdn pin should be ?l?. when neither adc nor dac are used, external clocks may not be present. when adc or dac is used, external clocks must always be present.
[ak4645a] ms0986-e-00 2008/07 - 65 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h power management 2 hpz hpmtn pmhpl pmhpr m/s 0 0 0 default 0 0 0 0 0 0 0 0 m/s: master / slave mode select 0: slave mode (default) 1: master mode pmhpr: headphone-amp rch power management 0: power-down (default) 1: power-up pmhpl: headphone-amp lch power management 0: power-down (default) 1: power-up hpmtn: headphone-amp mute control 0: mute (default) 1: normal operation hpz: headphone-amp pull-down control 0: shorted to gnd (default) 1: pulled-down by 200k (typ) addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h signal select 1 0 0 0 dacl 0 pmmp 0 mgain0 default 0 0 0 0 0 0 0 1 mgain1-0: mic-amp gain control ( table 16 ) mgain1 bit is d5 bit of 03h. pmmp: mpwr pin power management 0: power-down: hi-z (default) 1: power-up dacl: switch control from dac to line output 0: off (default) 1: on when pmlo bit is ?1?, dacl bit is enabled. when pmlo bit is ?0?, the lout/rout pins go to avss.
[ak4645a] ms0986-e-00 2008/07 - 66 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 03h signal select 2 lovl lops mgain1 0 0 minl 0 0 default 0 0 0 0 0 0 0 0 minl: switch control from min pin to stereo line output 0: off (default) 1: on when pmlo bit is ?1?, minl bit is enabled. when pmlo bit is ?0?, the lout/rout pins go to avss. mgain1: mic-amp gain control ( table 16 ) lops: stereo line ou tput power-save mode 0: normal operation (default) 1: power-save mode lovl: stereo line output gain select ( table 44 and table 46 ) 0: 0db/+6db (default) 1: +2db/+8db addr register name d7 d6 d5 d4 d3 d2 d1 d0 04h mode control 1 0 0 0 0 bcko 0 dif1 dif0 default 0 0 0 0 0 0 1 0 dif1-0: audio interface format ( table 10 ) default: ?10? (left jutified) bcko: bick output frequency select at master mode ( table 9 ) addr register name d7 d6 d5 d4 d3 d2 d1 d0 05h mode control 2 0 0 fs3 msbs bckp fs2 fs1 fs0 default 0 0 0 0 0 0 0 0 fs3-0: mcki frequency select ( table 5 ) fs3-0 bits select mcki frequency. bckp: bick polarity at dsp mode ( table 11 ) ?0?: sdto is output by the rising edge (? ?) of bick and sdti is latched by the falling edge (? ?). (default) ?1?: sdto is output by the falling edge (? ?) of bick and sdti is latched by the rising edge (? ?). msbs: lrck polarity at dsp mode ( table 11 ) ?0?: the rising edge (? ?) of lrck is half clock of bick before the channel change. (default) ?1?: the rising edge (? ?) of lrck is one clock of bick before the channel change.
[ak4645a] ms0986-e-00 2008/07 - 67 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 06h timer select dvtm wtm2 ztm 1 ztm0 wtm1 wtm0 rfst1 rfst0 default 0 0 0 0 0 0 0 0 rfst1-0: alc first recovery speed ( table 27 ) default: ?00?(4times) wtm2-0: alc recovery waiting period ( table 24 ) default: ?000? (128/fs) ztm1-0: alc limiter/recovery operation zero crossing timeout period ( table 23 ) default: ?00? (128/fs) dvtm: digital volume transition time setting ( table 33 ) 0: 1061/fs (default) 1: 256/fs this is the transition time between dvl/r7-0 bits = 00h and ffh. addr register name d7 d6 d5 d4 d3 d2 d1 d0 07h alc mode control 1 0 0 alc zelmn lmat1 lmat0 rgain0 lmth0 default 0 0 0 0 0 0 0 0 lmth1-0: alc limiter detection level / recovery counter reset level ( table 21 ) default: ?00? lmth1 bit is d6 bit of 0bh. rgain1-0: alc recovery gain step ( table 25 ) default: ?00? rgain1 bit is d7 bit of 0bh. lmat1-0: alc limiter att step ( table 22 ) default: ?00? zelmn: zero crossing detection en able at alc limiter operation 0: enable (default) 1: disable alc: alc enable 0: alc disable (default) 1: alc enable addr register name d7 d6 d5 d4 d3 d2 d1 d0 08h alc mode control 2 ref7 ref6 ref5 ref4 ref3 ref2 ref1 ref0 default 1 1 1 0 0 0 0 1 ref7-0: reference value at alc recovery operation. 0.375db step, 242 level ( table 26 ) default: ?e1h? (+30.0db)
[ak4645a] ms0986-e-00 2008/07 - 68 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 09h lch input volume control ivl7 iv l6 ivl5 ivl4 ivl3 ivl2 ivl1 ivl0 0ch rch input volume control ivr7 ivr6 ivr5 ivr4 ivr3 ivr2 ivr1 ivr0 default 1 1 1 0 0 0 0 1 ivl7-0, ivr7-0: input digital volume; 0.375db step, 242 level ( table 29 ) default: ?e1h? (+30.0db) addr register name d7 d6 d5 d4 d3 d2 d1 d0 0ah lch digital volume control dvl7 dvl6 dvl5 dvl4 dvl3 dvl2 dvl1 dvl0 0dh rch digital volume control dvr7 dvr6 dvr5 dvr4 dvr3 dvr2 dvr1 dvr0 default 0 0 0 1 1 0 0 0 dvl7-0, dvr7-0: output digital volume ( table 32 ) default: ?18h? (0db) addr register name d7 d6 d5 d4 d3 d2 d1 d0 0bh alc mode control 3 rgain1 lmth1 0 0 0 0 vbat 0 default 0 0 0 0 0 0 0 0 vbat: hp-amp common voltage ( table 49 ) 0: 0.5 x hvdd (default) 1: 0.64 x avdd lmth1: alc limiter detection level / recovery counter reset level ( table 21 ) rgain1: alc recovery gain step ( table 25 ) addr register name d7 d6 d5 d4 d3 d2 d1 d0 0eh mode control 3 0 loop sm ute dvolc bst1 bst0 dem1 dem0 default 0 0 0 1 0 0 0 1 dem1-0: de-emphasis frequency select ( table 30 ) default: ?01? (off) bst1-0: bass boost function select ( table 31 ) default: ?00? (off) dvolc: output digital volu me control mode select 0: independent 1: dependent (default) when dvolc bit = ?1?, dvl7-0 bits control both lch and rch volume level, while register values of dvl7-0 bits are not written to dvr7-0 bits. when dvol c bit = ?0?, dvl7-0 bits control lch level and dvr7-0 bits control rch level, respectively. smute: soft mute control 0: normal operation (default) 1: dac outputs soft-muted loop: digital loopback mode 0: sdti dac (default) 1: sdto dac
[ak4645a] ms0986-e-00 2008/07 - 69 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 0fh mode control 4 0 0 0 0 ivolc hpm minh dach default 0 0 0 0 1 0 0 0 dach: switch control from dac to headphone-amp 0: off (default) 1: on minh: switch control from min pin to headphone-amp 0: off (default) 1: on hpm: headphone-amp mono output select 0: stereo (default) 1: mono when the hpm bit = ?1?, dac output signal is output to lch and rch of the headphone-amp as (l+r)/2. ivolc: input digital volume control mode select 0: independent 1: dependent (default) when ivolc bit = ?1?, ivl7-0 bits control both lch and rch volume level, while register values of ivl7-0 bits are not written to ivr7-0 bits. when ivolc bit = ?0?, ivl7-0 bits control lch level and ivr7-0 bits control rch level, respectively. addr register name d7 d6 d5 d4 d3 d2 d1 d0 10h power management 3 inr1 inl1 hpg mdif2 mdif1 inr0 inl0 pmadr default 0 0 0 0 0 0 0 0 pmadr: mic-amp lch and adc rch power management 0: power-down (default) 1: power-up inl1-0: adc lch input source select ( table 13 ) default: 00 (lin1 pin) inr1-0: adc rch input source select ( table 13 ) default: 00 (rin1 pin) mdif1: single-ended / full-differential input select 1 0: single-ended input (lin1/rin1 pins: default) 1: full-differential input (in1+/in1 ? pins) mdif1 bit selects the input type of pins #32 and #31. mdif2: single-ended / full-differential input select 2 0: single-ended input (lin2/rin2 pins: default) 1: full-differential input (in2+/in2 ? pins) mdif2 bit selects the input type of pins #30 and #29. hpg: headphone-amp gain select ( table 47 ) 0: 0db (default) 1: +3.6db
[ak4645a] ms0986-e-00 2008/07 - 70 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 11h digital filter select gn1 gn0 0 fil1 eq fil3 0 0 default 0 0 0 0 0 0 0 0 gn1-0: gain select at gain block ( table 19 ) default: ?00? fil3: fil3 (stereo separation emphasis filter) coefficient setting enable 0: disable (default) 1: enable when fil3 bit is ?1?, the settings of f3a13-0 and f3b13- 0 bits are enabled. when fi l3 bit is ?0?, fil3 block is off (mute). eq: eq (gain compensation filter) coefficient setting enable 0: disable (default) 1: enable when eq bit is ?1?, the settings of eqa15-0, eqb13-0 and eqc15-0 bits are enabled. when eq bit is ?0?, eq block is through (0db). fil1: fil1 (wind-noise reduction filter) coefficient setting enable 0: disable (default) 1: enable when fil1 bit is ?1?, the settings of f1a13-0 and f1b13- 0 bits are enabled. when fi l1 bit is ?0?, fil1 block is through (0db). addr register name d7 d6 d5 d4 d3 d2 d1 d0 12h fil3 co-efficient 0 f3a7 f3a6 f3a5 f3a4 f3a3 f3a2 f3a1 f3a0 13h fil3 co-efficient 1 f3as 0 f3a13 f3a12 f3a11 f3a10 f3a9 f3a8 14h fil3 co-efficient 2 f3b7 f3b6 f3b5 f3b4 f3b3 f3b2 f3b1 f3b0 15h fil3 co-efficient 3 0 0 f3b13 f3b12 f3b11 f3b10 f3b9 f3b8 16h eq co-efficient 0 eqa7 eqa6 e qa5 eqa4 eqa3 eqa2 eqa1 eqa0 17h eq co-efficient 1 eqa15 eqa1 4 eqa13 eqa12 eqa11 eqa10 eqa9 eqa8 18h eq co-efficient 2 eqb7 eqb6 eq b5 eqb4 eqb3 eqb2 eqb1 eqb0 19h eq co-efficient 3 0 0 eqb13 eqb12 eqb11 eqb10 eqb9 eqb8 1ah eq co-efficient 4 eqc7 eqc6 eq c5 eqc4 eqc3 eqc2 eqc1 eqc0 1bh eq co-efficient 5 eqc15 eqc14 e qc13 eqc12 eqc11 eqc10 eqc9 eqc8 1ch fil1 co-efficient 0 f1a7 f1a6 f1a5 f1a4 f1a3 f1a2 f1a1 f1a0 1dh fil1 co-efficient 1 f1as 0 f1a13 f1a12 f1a11 f1a10 f1a9 f1a8 1eh fil1 co-efficient 2 f1b7 f1b6 f1b5 f1b4 f1b3 f1b2 f1b1 f1b0 1fh fil1 co-efficient 3 0 0 f1b13 f1b12 f1b11 f1b10 f1b9 f1b8 default 0 0 0 0 0 0 0 0 f3a13-0, f3b13-0: fil3 (stereo separati on emphasis filter) coefficient (14bit x 2) default: ?0000h? f3as: fil3 (stereo separation emphasis filter) select 0: hpf (default) 1: lpf eqa15-0, eqb13-0, eqc15-c0: eq (gain compen sation filter) coefficient (14bit x 2 + 16bit x 1) default: ?0000h? f1a13-0, f1b13-b0: fil1 (wind-noise reduction filter) coefficient (14bit x 2) default: ?0000h? f1as: fil1 (wind-noise reduction filter) select 0: hpf (default) 1: lpf
[ak4645a] ms0986-e-00 2008/07 - 71 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 20h power management 4 pmainr4 pmainl4 pmainr3 pmainl3 pmainr2 pmainl2 pmmicr pmmicl default 0 0 0 0 0 0 0 0 pmmicl: mic-amp lch power management 0: power down (default) 1: power up pmmicr: mic-amp rch power management 0: power down (default) 1: power up pmainl2: lin2 mixing circuit power management 0: power down (default) 1: power up pmainr2: rin2 mixing circuit power management 0: power down (default) 1: power up pmainl3: lin3 mixing circuit power management 0: power down (default) 1: power up pmainr3: rin3 mixing circuit power management 0: power down (default) 1: power up pmainl4: lin4 mixing circuit power management 0: power down (default) 1: power up pmainr4: rin4 mixing circuit power management 0: power down (default) 1: power up
[ak4645a] ms0986-e-00 2008/07 - 72 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 21h mode control 5 0 0 micr3 micl3 l4dif mix ain3 lodif default 0 0 0 0 0 0 0 0 lodif: lineout select 0: single-ended stereo line output (lout/rout pins) (default) 1: full-differential mono line output (lop/lon pins) ain3: analog mixing select 0: mono input (min pin) (default) 1: stereo input (lin3/rin3 pins) mix: mono recording 0: stereo (default) 1: mono: (l+r)/2 l4dif: line input type select 0: stereo single-ended input: lin4/rin4 pins (default) 1: mono full-differential input: in4+/ ? pins micl3: switch control from mic-amp lch to analog output 0: lin3 input signal is selected. (default) 1: mic-amp lch output signal is selected. micr3: switch control from mic-amp rch to analog output 0: rin3 input signal is selected. (default) 1: mic-amp rch output signal is selected.
[ak4645a] ms0986-e-00 2008/07 - 73 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 22h lineout mixing select lom lom3 rinr4 linl4 rinr3 linl3 rinr2 linl2 default 0 0 0 0 0 0 0 0 linl2: switch control from lin2 pin to stereo line output (without mic-amp) 0: off (default) 1: on rinr2: switch control from rin2 pin to stereo line output (without mic-amp) 0: off (default) 1: on linl3: switch control from lin3 pin (or mic-amp lch) to stereo line output 0: off (default) 1: on rinr3: switch control from rin3 pin (or mic-amp lch) to stereo line output 0: off (default) 1: on linl4: switch control from lin4 pin to stereo line output (without mic-amp) 0: off (default) 1: on rinr4: switch control from rin4 pin to stereo line output (without mic-amp) 0: off (default) 1: on lom3: mono mixing from mic-amp (or lin3/rin3) to stereo line output 0: stereo mixing (default) 1: mono mixing lom: mono mixing from dac to stereo line output 0: stereo mixing (default) 1: mono mixing
[ak4645a] ms0986-e-00 2008/07 - 74 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 23h hp mixing select 0 hpm3 ri nh4 linh4 rinh3 linh3 rinh2 linh2 default 0 0 0 0 0 0 0 0 linh2: switch control from lin2 pin to headphone output (without mic-amp) 0: off (default) 1: on rinh2: switch control from rin2 pin to headphone output (without mic-amp) 0: off (default) 1: on linh3: switch control from lin3 pin (or mic-amp lch) to headphone output 0: off (default) 1: on rinh3: switch control from rin3 pin (or mic-amp lch) to headphone output 0: off (default) 1: on linh4: switch control from lin4 pin to headphone output (without mic-amp) 0: off (default) 1: on rinh4: switch control from rin4 pin to headphone output (without mic-amp) 0: off (default) 1: on hpm3: mono mixing from mic-amp (or lin3/rin3) to headphone output 0: stereo mixing (default) 1: mono mixing
[ak4645a] ms0986-e-00 2008/07 - 75 - system design figure 67 and figure 68 shows the system connection diagram for the ak4645a. an evaluation board [akd4645] is available which demonstrates the optimum layout, power supply arrangements and measurement results. lin4 rout lout min rin2 lin2 lin1 rin1 rin4 mutet hpl hpr hvdd hvss testo mcki mpwr vcom a vss a vdd rin3 i2c pdn csn tvdd dvdd bick lrck sdto sdti cdti cclk a k4645a top view 25 26 27 28 29 30 31 32 24 23 22 1 16 15 14 13 12 11 10 9 21 20 19 18 17 2 3 4 5 6 7 8 2.2 k 2.2 k 2.2 k 2.2 k external mic internal mic 1u 0.1u 2.2u 0.1u 6.8 47u 6.8 47u 10 0.22u 10 0.22u power supply 2.6 3.6v 0.1u 0.1u 10 dsp p speaker headphone mono in 10u analog ground digital ground power supply 1.6 3.6v 0.1u line in external spk-amp notes: - avss and hvss of the ak4645a must be distributed separately from the ground of external controllers. - all digital input pins must not be left floating. - when the ak4645a is used at master mode, lrck and bick pins are floating before m/s bit is changed to ?1?. therefore, 100k around pull-up resistor must be connected to lrck and bick pins of the ak4645a. - 0.1 f ceramic capacitor must be attached to each supply pins. the type of other capacitors is not critical. - when dvdd is supplied from avdd via 10 series resistor, the capacitor larger than 0.1 f must not be connected between dvdd and the ground. figure 67. typical connection diagram (ain3 bit = ?0?, mic input)
[ak4645a] ms0986-e-00 2008/07 - 76 - rout lout rin2 lin2 lin1 rin1 testo mcki mpwr vcom a vss a vdd i2c pdn csn dvdd bick lrck sdto sdti cdti cclk a k4645a top view 25 26 27 28 29 30 31 32 24 23 22 1 16 15 14 13 12 11 10 9 21 20 19 18 17 2 3 4 5 6 7 8 0.1u 2.2u 0.1u dsp p line out analog ground digital ground 1u 1u 200 200 lin4 rin4 mutet hpl hpr hvdd hvss tvdd 1u 6.8 47u 10 0.22u 10 0.22u power supply 2.6 3.6v 0.1u 10 headphone 10u 20k 20k power supply 1.6 3.6v 0.1u line in 0.1u lin3 rin3 line in 6.8 47u notes: - avss and hvss of the ak4645a msut be distributed separately from the ground of external controllers. - all digital input pins must not be left floating. - when the ak4645a is used at master mode, lrck and bick pins are floating before m/s bit is changed to ?1?. therefore, 100k around pull-up resistor must be connected to lrck and bick pins of the ak4645a. - 0.1 f ceramic capacitor should be attached to each supply pins. the type of other capacitors is not critical. - when dvdd is supplied from avdd via 10 series resistor, the capacitor larger than 0.1 f must not be connected between dvdd and the ground. figure 68. typical connection diagram (ain3 bit = ?1?, line input)
[ak4645a] ms0986-e-00 2008/07 - 77 - 1. grounding and power supply decoupling the ak4645a requires careful attention to power supply and grounding arrangements. avdd, dvdd, tvdd and hvdd are usually supplied from the system?s analog supply. if avdd, dvdd, tvdd and hvdd are supplied separately, the power-up sequence is not critical. the pdn pin must be held to ?l? upon power-up. the pdn pin must be set to ?h? after all power supplies are powered-up. in case that pop noise have to be avoided at line output and headphone output, the ak4645a should be operated by the following recommended power-up/down sequence. 1) power-up - the pdn pin must be held to ?l? upon power-up. the ak4645a must be reset by bringing pdn pin ?l? for 150ns or more. - in case that the power supplies are separated in two or more groups, the power supply including tvdd should be powered on at first. regarding the relationship between dvdd and hvdd, the power supply including dvdd should be powered on prior to the power supply including hvdd. 2) power-down - each power supplies must be powered o ff after the pdn pin is set to ?l?. - in case that the power supplies are separated in two or more groups, the power supply including tvdd should be powered off at last. regarding the relationship between dvdd and hvdd, the power supply including hvdd should be powered off prior to the power supply including dvdd. avss and hvss of the ak4645a must be connected to the analog ground plane. system analog ground and digital ground must be connected together near to where the supplies are brought onto the printed circuit board. decoupling capacitors should be as near to the ak4645a as possible, with the small value ceramic capacitor being the nearest. 2. voltage reference vcom is a signal ground of this chip. a 2.2 f electrolytic capacitor in parallel with a 0.1 f ceramic capacitor attached to the vcom pin eliminates the effects of high frequency noise. no load current may be drawn from the vcom pin. all signals, especially clocks, should be kept away from the vcom pin in order to avoid unwanted coupling into the ak4645a. 3. analog inputs the mic, line and min inputs are single-ended. the input signal range scales with nominally at 0.06 x avdd vpp(typ) @mgain1-0 bits = ?01?, 0.03 x avdd vpp(typ) @mgain1-0 bits = ?10?, 0.015 x avdd vpp(typ) @mgain1-0 bits = ?11? or 0.6 x avdd vpp(typ) @mgain1-0 bits = ?00? for the mic/line input and 0.6 x avdd vpp (typ) for the min input, centered around the internal common voltage (0.45 x avdd). usually the input signal is ac coupled using a capacitor. the cut-off frequency is fc = (1/2 rc). the ak4645a can accept input voltages from avss to avdd. 4. analog outputs the input data format for the dac is 2?s complement. th e output voltage is a positive full scale for 7fffh(@16bit) and a negative full scale for 8000h(@16bit). the ideal output is vcom voltage for 0000h(@16bit). stereo line output is centered at 0.45 x avdd. the headphone-amp output is centered at hvdd/2.
[ak4645a] ms0986-e-00 2008/07 - 78 - control sequence clock set up when adc or dac is powered-up, the clocks must be supplied. 1. 1. ext slave mode (1) power supply pdn pin pmvcm bit (addr:00h, d6) (2) (3) lrck pin bick pin (4) input (4) mcki pin input example: audio i/f format: msb justified (adc and dac) input mcki frequency: 256fs sampling frequency: 44.1khz (1) power supply & pdn pin = ?l? ? ?h? (3) addr:00h, data:40h (2) addr:04h, data:02h addr:05h, data:00h mcki, bick and lrck input figure 69. clock set up sequence (4) (1) after power up, pdn pin = ?l? ? ?h?. ?l? time of 150ns or more is needed to reset the ak4645a. the ak4645a should be operated by the recommended power-up/down sequence shown in ?system design (grounding and power supply decoupling)? to avoi d pop noise at line output and headphone output. (2) dif1-0 and fs1-0 bits must be set during this period. (3) power up vcom: pmvcm bit = ?0? ? ?1? vcom should first be powered up be fore the other block operates. (4) normal operation starts after the mcki, lrck and bick are supplied.
[ak4645a] ms0986-e-00 2008/07 - 79 - 2. ext master mode (1) power supply pdn pin pmvcm bit (addr:00h, d6) (3) (4) lrck pin bick pin (2) mcki pin input m/s bit (addr:01h, d3) output example: audio i/f format: msb justified (adc and dac) input mcki frequency: 256fs sampling frequency: 44.1khz (1) power supply & pdn pin = ?l? ? ?h? (4) addr:00h, data:40h (3) addr:04h, data:02h addr:05h, data:00h addr:01h, data:08h bick and lrck output (2) mcki input figure 70. clock set up sequence (5) (1) after power up, pdn pin = ?l? ? ?h?. ?l? time of 150ns or more is needed to reset the ak4645a. the ak4645a must be operated by the recommended power-up/down sequence shown in ?system design (grounding and power supply decoupling)? to avoid the pop noise at line output and headphone output. (2) mcki should be input. (3) after dif1-0 and fs1-0 bits are set, m/s bit mu st be set to ?1?. then lrck and bick are output. (4) power up vcom: pmvcm bit = ?0? ? ?1? vcom should first be powered up be fore the other block operates.
[ak4645a] ms0986-e-00 2008/07 - 80 - mic input recording (stereo) fs3-0 bits (addr:05h, d5&d2-0) mic control (addr:02h, d2-0) pmadl/r bits (addr:00h&10h, d0) adc internal state 0,010 0,000 001 101 power down initialize normal state power down 1059 / fs (1) (2) (7) alc state alc enable alc disable alc disable (5) alc control 1 (addr:06h) 00h 3ch (3) alc control 2 (addr:08h) e1h e1h (4) alc control 3 (addr:0bh) 00h 00h (8) (6) alc control 4 (addr:07h) 07h 21h 01h (9) example: audio i/f format:msb justified (adc & dac) sampling frequency:44.1khz pre mic amp:+20db mic power on alc setting:refer to table 34 alc bit=?1? (2) addr:02h, data:05h (3) addr:06h, data:3ch (1) addr:05h, data:27h (4) addr:08h, data:e1h (5) addr:0bh, data:00h (7) addr:00h, data:41h addr:10h, data:01h recording (8) addr:00h, data:40h addr:10h, data:00h (6) addr:07h, data:21h (9) addr:07h, data:01h figure 71. mic input recording sequence this sequence is an example of alc setting at fs=44.1khz. if the parameter of the alc is changed, please refer to ? figure 29. registers set-up sequence at alc operation? at first, clocks must be supplied according to ?clock set up? sequence. (1) set up a sampling frequency (fs3-0 bit). (2) set up mic input (addr: 02h) (3) set up timer select for alc (addr: 06h) (4) set up ref value for alc (addr: 08h) (5) set up lmth1 and rgain1 bits (addr: 0bh) (6) set up lmth0, rgain0, lmat1-0 and alc bits (addr: 07h) (7) power up mic and adc: pmadl = pmadr bits = ?0? ?1? the initialization cycle time of adc is 1059/fs=24ms@fs=44.1khz. after the alc bit is set to ?1? and mic&adc block is powered-up, the alc operation starts from ivol default value (+30db). the time of offset voltage going to ?0? after the adc initialization cycle depends on both the time of analog input pin going to the common voltage and the time constant of the offset cancel digital hpf. this time can be shorter by using the following sequence: at first, pmvcm and pmmp bits must set to ?1?. then, the adc should be powered-up. the wait time to power-up the adc should be longer than 4 times of the time constant that is determined by the ac coupling capacitor at analog input pin and the internal input resistance 60k(typ). (8) power down mic and adc: pmadl = pmadr bits = ?1? ?0? when the registers for the alc operation are not change d, alc bit may be keeping ?1?. the alc operation is disabled because the mic&adc block is powered-down. if the registers for the alc operation are also changed when the sampling frequency is changed, it should be done after the ak4645a goes to the manual mode (alc bit = ?0?) or mic&adc block is powered-down (pmadl=pmadr bits = ?0?). ivol gain is not reset when pmadl=pmadr bits = ?0?, and then ivol operation starts from the setting value when pmadl or pmadr bit is changed to ?1?. (9) alc disable: alc bit = ?1? ?0?
[ak4645a] ms0986-e-00 2008/07 - 81 - headphone-amp output fs3-0 bits (addr:05h, d5&d2-0) dvl/r7-0 bits (addr:0ah&0dh, d7-0) pmhpl/r bits (addr:01h, d5-4) hpmtn bit (addr:01h, d6) hpl/r pins 0,010 0,000 18h 28h normal output (1) bst1-0 bits (addr:0eh, d3-2) 00 10 00 (3) (5) (12) pmdac bit (addr:00h, d2) (6) (11) (7) (9) (8) (10) ivl/r7-0 bits (addr:09h&0ch, d7-0) e1h 91h (4) pmmin bit (addr:00h, d5) dach bit (addr:0fh, d0) (2) (13) exam ple : sam pling frequency: 44.1khz d v o lc bit = ?1?(default) digital volum e level: ? 8db bass boost level: middle de-em phases response: off s oft m ute tim e: 256/fs (1) addr:05h, data:27h (5) addr:0ah&0dh, data 28h (6) addr:00h, data 64h playback (3) addr:0eh, data 19h (9) addr:01h, data 39h (1 0 ) a d d r:0 1h , d a ta 0 9 h (7) addr:01h, data 39h (8) addr:01h, data 79h (1 1 ) a d d r:0 0h , d a ta 4 0 h (12) addr:0eh, data 00h (4) addr:09h&0ch, data 91h (2) a ddr:0f h , d ata 09h (13) addr:0fh, data 08h figure 72. headphone-amp output sequence at first, clocks must be supplied according to ?clock set up? sequence. (1) set up a sampling frequency (fs3-0 bits). (2) set up the path of ?dac hp-amp?: dach bit = ?0? ?1? (3) set up the low frequency boost level (bst1-0 bits) (4) set up the input digital volume (addr: 09h and 0ch) when pmadl = pmadr bits = ?0?, ivl7-0 and ivr7-0 bits must be set to ?91h?(0db). (5) set up the output digital volume (addr: 0ah and 0dh) when dvolc bit is ?1? (default), dvl 7-0 bits set the volume of both channels. after dac is powered-up, the digital volume changes from default value (0db) to the register setting value by the soft transition. (6) power up dac and min-amp: pmdac = pmmin bits = ?0? ?1? the dac enters an initialization cycle that starts when the pmdac bit is changed from ?0? to ?1? at pmadl and pmadr bits are ?0?. the initialization cy cle time is 1059/fs=24ms@fs=44.1khz. during the initialization cycle, the dac input digita l data of both channels are internally forced to a 2's compliment, ?0?. the dac output reflects the digital i nput data after the initialization cy cle is complete. when pmadl or pmadr bit is ?1?, the dac does not require an initialization cycle. when alc bit is ?1?, alc is disable (alc gain is set by ivl/r7-0 bits) during an intialization cycle (1059/fs=24ms@fs=44.1khz). after the initialization cycle, alc operation starts from the gain set by ivl/r7-0 bits. (7) power up headphone-amp: pmhpl = pmhpr bits = ?0? ?1? output voltage of headphone-amp is still hvss. (8) rise up the common voltage of headphone-amp: hpmtn bit = ?0? ?1? the rise time depends on hvdd and the capacitor valu e connected with the mutet pin. when hvdd=3.3v and the capacitor value is 1.0 f, the time constant is r = 100ms(typ), 250ms(max). (9) fall down the common voltage of headphone-amp: hpmtn bit = ?1? ?0? the fall time depends on hvdd and the capacitor value connected with the mutet pin. when hvdd=3.3v and the capacitor value is 1.0 f, the time constant is f = 100ms(typ), 250ms(max). if the power supply is powered-off or headphone-amp is powered-down before the common voltage goes to gnd, pop noise occurs. it takes twice of f that the common voltage goes to gnd. (10) power down headphone-amp: pmhpl = pmhpr bits = ?1? ?0? (11) power down dac and min-amp: pmdac = pmmin bits = ?1? ?0? (12) off the bass boost: bst1-0 bits = ?00? (13) disable the path of ?dac hp-amp?: dach bit = ?1? ?0?
[ak4645a] ms0986-e-00 2008/07 - 82 - stereo line output fs3-0 bits (addr:05h, d5&d2-0) dvl/r7-0 bits (addr:0ah&0dh, d7-0) pmdac bit (addr:00h, d2) pmlo bit (addr:00h, d3) 0,010 0,000 18h 28h lout pin rout pin (1) (4) (5) (2) dacl bit (addr:02h, d4) (10) normal output (7) lops bit (addr:03h, d6) (6) >300 ms (8) (9) >300 ms (11) ivl/r7-0 bits (addr:09h&0ch, d7-0) e1h 91h (3) pmmin bit (addr:00h, d5) example: audio i/f format :msb justified (adc & dac) sampling frequency: 44.1khz digital volume: ? 8db lovl=minl bits = ?0? (1) addr:05h, data:27h (2) addr:02h, data:10h (4) addr:0ah&0dh, data:28h (5) addr:03h, data:40h (6) addr:00h, data:6ch (7) addr:03h, data:00h playback (8) addr:03h, data:40h (9) addr:00h, data:40h (10) addr:02h, data:00h (11) addr:03h, data:00h (3) addr:09h&0ch, data:91h figure 73. stereo lineout sequence at first, clocks must be supplied according to ?clock set up? sequence. (1) set up the sampling frequency (fs3-0 bits). (2) set up the path of ?dac ? stereo line amp?: dacl bit = ?0? ? ?1? (3) set up the input digital volume (addr: 09h and 0ch) when pmadl = pmadr bits = ?0?, ivl7-0 and ivr7-0 bits must be set to ?91h?(0db). (4) set up the output digital volume (addr: 0ah and 0dh) when dvolc bit is ?1? (default), dvl 7-0 bits set the volume of both channels. after dac is powered-up, the digital volume changes from default value (0db) to the register setting value by the soft transition. (5) enter power-save mode of stereo line amp: lops bit = ?0? ? ?1? (6) power-up dac, min-amp and stereo line-amp: pmdac = pmmin = pmlo bits = ?0? ?1? the dac enters an initialization cycle that starts when the pmdac bit is changed from ?0? to ?1? at pmadl and pmadr bits are ?0?. the initialization cy cle time is 1059/fs=24ms@fs=44.1khz. during the initialization cycle, the dac input digita l data of both channels are internally forced to a 2's compliment, ?0?. the dac output reflects the digital i nput data after the initialization cycl e is completed. when pmadl or pmadr bit is ?1?, the dac does not require an initialization cycle. when alc bit is ?1?, alc is disable (alc gain is set by ivl/r7-0 bits) during an intialization cycle (1059/fs=24ms@fs=44.1khz). after the initialization cycle, alc operation starts from the gain set by ivl/r7-0 bits. lout and rout pins rise up to vcom voltage after pm lo bit is changed to ?1?. rise time is 300ms(max) at c=1 f and avdd=3.3v. (7) exit power-save mode of ster eo line-amp: lops bit = ?1? ? ?0? lops bit should be set to ?0? after lout and rout pi ns rise up. stereo line-amp goes to normal operation by setting lops bit to ?0?. (8) enter power-save mode of stereo line-amp: lops bit: ?0? ? ?1? (9) power-down dac, min-amp and stereo line-amp: pmdac = pmmin = pmlo bits = ?1? ?0? lout and rout pins fall down to avss. fall time is 300ms(max) at c=1 f and avdd=3.3v. (10) disable the path of ?dac ? stereo line-amp?: dacl bit = ?1? ? ?0? (11) exit power-save mode of ster eo line-amp: lops bit = ?1? ? ?0? lops bit should be set to ?0? after lout and rout pins fall down.
[ak4645a] ms0986-e-00 2008/07 - 83 - stop of clock master clock can be stopped when adc and dac are not in operation. 1. ext slave mode external lrck input (1) external bick input (1) external mcki input (1) example audio i/f format: msb justified (adc & dac) input mcki frequency: 1024fs sampling frequency: 44.1khz (1) stop the external clocks figure 74. clock stopping sequence (4) (1) stop the external mcki, bick and lrck clocks. 2. ext master mode lrck output bick output external mcki input (1) "h" or "l" "h" or "l" example audio i/f format: msb justified (adc & dac) input mcki frequency: 1024fs sampling frequency: 44.1khz (1) stop the external mcki figure 75. clock stopping sequence (5) (1) stop mcki clock. bick and lrck are fixed to ?h? or ?l?. power down power supply current can be shut down (typ. 20 a) by stopping clocks and setting pmvcm bit = ?0? after all blocks except for vcom are powered-down. power supply current can also be shut down (typ. 1 a) by stopping clocks and setting the pdn pin = ?l?. when the pdn pin = ?l?, the registers are initialized.
[ak4645a] ms0986-e-00 2008/07 - 84 - package 32pin qfn (unit: mm) 2.4 0.1 0.4 0.18 0.05 0.00 min 0.05 max 0.65 max 2.4 0.1 1 9 16 25 4.0 0.1 4.0 0.1 0.45 0.10 a b 0.05 m 0.08 8 32 17 24 pin #1 id exposed pad 0.40 0.10 0.22 0.05 c0.3 note) the exposed pad on the bottom surface of the p ackage must be open or connected to the ground. material & lead finish package molding compound: epoxy lead frame material: cu lead frame surface treatme nt: solder (pb free) plate
[ak4645a] ms0986-e-00 2008/07 - 85 - marking 4645a x xxx 1 xxxx: date code (4 digit) pin #1 indication revision history date (yy/mm/dd) revision reason page contents 08/07/31 00 first edition important notice z these products and their specifications are subject to change without notice. when you consider any use or application of these produc ts, please make inquiries the sales office of asahi kasei emd corporation (akemd) or authorized distributors as to current status of the products. z akemd assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. z any export of these products, or devices or systems containi ng them, may require an export license or other official approval under the law and regulations of the country of e xport pertaining to customs and tariffs, currency exchange, or strategic materials. z akemd products are neither intended nor au thorized for use as critical components note1) in any safety, life support, or other hazard related device or system note2) , and akemd assumes no responsibility for such use, except for the use approved with the express written consent by representative director of akemd. as used here: note1) a critical component is one whose failure to func tion or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. note2) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fi elds, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z it is the responsibility of the buyer or distributor of akemd pr oducts, who distributes, dis poses of, or otherwise places the product with a third party, to notify such third party in advance of the above cont ent and conditions, and the buyer or distributor agrees to assume any and all re sponsibility and liability for and hold akemd harmless from any and all claims arising from the use of said product in the absence of such notification.

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