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nju - 1 - mpeg-2 image processor general description the nju28001 is mpeg-2/dvd video decoding ic. it de-multiplexes mpeg-2 as well as dvd system (program) streams and holds them in its external dram. it decodes mpeg-2 compressed video and outputs digital video (in ntsc or pal format) along with sub picture data while retrieving navigation data. in addition to these basic mpeg-2/dvd de-multiplexing and decoding functions, the nju28001 also supports a number of advanced features for the next generation products. it includes vbr operation, time stamp processing (for synchronization), error concealment and ff/fr modes. since mpeg-2 and dvd are widely used in digital video application, the nju28001 forms a central core in decoder systems such as dvd player, digital tv, stb, computer multimedia system, etc. features single 3.3v power supply single 27mhz input clock bit stream processor iso13818-1 mpeg-2 program stream de-multiplexing iso11172-1 mpeg-1 system stream de-multiplexing supports dvd program stream de-multiplexing including private_stream_1 supports vbr operation supports css audio decoding 16bit linear pcm decoding extraction of audio data in pes layer or elementary layer video decoder decodes iso13818-2 mpeg-2 (mp@ml) decodes iso11172-2 mpeg-1 constrained parameter video stream supports fast fw, fast reverse, skip/repeat frame, freeze in field/frame and slow fw video display controller outputs digital video in ntsc or pal format built-in osd, caption and subpicture decoder c-mos technology package outline qfp144 package outline preliminary NJU28001F
- 2 - nju 142 144 143 141 140 139 138 137 134 136 135 133 132 131 130 129 126 128 127 125 124 123 122 121 118 120 119 117 116 115 114 113 112 111 110 109 vcoin cpout lpfen pllv ss tstn pllsel_1 pllsel_2 counter dq_8 v dd v ss dq_7 dq _ 6 dq_5 dq_4 dq_3 dq_2 v dd v ss dq_1 dq_0 ba0 ba1 we1/ a_12 cas1/ a_11 v dd v ss a_10 a_9 a_8 a_7 a_6 v dd v ss a_5 a_4 NJU28001F 39 37 38 4 0 4 1 4 2 4 3 4 4 4 7 4 5 4 6 4 8 4 9 50 51 52 55 53 54 56 57 58 59 60 63 61 62 64 65 66 67 68 69 70 71 72 v ss rd intr v dd d_0 d_1 d_2 d_3 v ss d_4 d_5 v dd d_6 d_7 ha_0 ha_1 v ss ha_2 ha_3 v dd ha_4 ha_5 ha_6 ha_7 v ss pdi_0 pdi_1 v dd pdi_2 pdi_3 pdi_4 pdi_5 pdi_6 pdi_7 v ss v dd 1 2 3 4 5 6 7 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 8 pllv ss rb pllv dd td v ss ref v dd dq_10 dq_11 ras1 ras0 cas0 test v dd clk81 v ss we0 dq_12 dq_13 dq_14 dq_15 v ss v dd asck areq sd_0 sd_1 sd_2 sd_3 v ss v dd aclk fs/ ws waitz cs dq_9 a_3 a_2 a_1 a_0 v dd v ss tn pi po mema memb v dd v ss reset scan_en fp hs cref blank v dd v ss pd_7 pd_6 pd_5 pd_4 pd_3 pd_2 v dd v ss pd_1 pd_0 dsos dclk dreq dvalid iddp 108 107 106 105 104 103 102 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 101 pin configuration
- 3 - nju block diagram dac or audio decoder sdram sdram interface bitstream parser css mpeg video decoding core subpicture decoder osd processor av sync. module audio i/f, lpcm display processor bitstream dve video data blender
- 4 - nju terminal description 1 no symbols input/output function 35 waitz output this signal indicates busy. when the output is low, it indicates the readiness of data while the host attempts to read it. 60 59 58 57 54 53 52 51 ha_7 (msb) ha_6 ha_5 ha_4 ha_3 ha_2 ha_1 ha_0 (lsb) input mpu data, address input 50 49 46 45 44 43 42 41 d_7 (msb) d_6 d_5 d_4 d_3 d_2 d_1 d_0 (lsb) input/output mpu data, parallel input/output 36 cs input chip select 37 rd input read/write strobe 38 intr output interrupt 74 dreq output it output becomes high when any of the following conditions happen: [1] the on-chip channel buffer fifo is full ,[2] the dram channel is full, this signal is de-asserted. 73 dvalid input dvalid is an input pin that takes a signal which defines the validity of incoming coded data(on pdi_7 to pdi_0) at the rising of the dclk pin input signal. the polarity of the input signal is programmable. 75 dclk input channel data clock input 76 dsos input dsos is an input pin that takes a signal which indicates the start of the sector. 70 69 68 67 66 65 62 61 pdi_7 (msb) pdi_6 pdi_5 pdi_4 pdi_3 pdi_2 pdi_1 pdi_0 (lsb) input channel decode data input
- 5 - nju terminal description 2 no symbol input/output function 22 21 20 19 10 9 8 134 133 132 131 130 129 126 125 124 dq_15 (msb) dq_14 dq_13 dq_12 dq_11 dq_10 dq_9 dq_8 dq_7 dq_6 dq_5 dq_4 dq_3 dq_2 dq_1 dq_0 (lsb) input/output sdram data input / output 117 116 115 114 113 110 109 108 107 106 105 a_10 (msb) a_9 a_8 a_7 a_6 a_5 a_4 a_3 a_2 a_1 a_0 (lsb) output sdram address data 16 clk81 output sdram clock data output 123 ba0 output sdram setting data for bank0 12 ras0 output ras0 13 cas0 output cas0 18 we0 output we0 122 ba1 output sdram setting data for bank1 11 ras1 output ras1 118 cas1/a_11 output this is the drive cas1 (or a_11) pin on sdram chip # 1 in 16 mbit x 2 configuration. in 64 mbit-2bank and 64mbit- 4bank configuration s, this pin serves as a11 of sdram chip. 121 we1/a_12 output this is the drive we1(or a_12) pin on sdram chip #1 in 16 mbit x 2 configuration in 64 mbit-2bank configuration, this pin serves as a12 of sdram chip. 86 85 84 83 82 81 78 77 pd_7 (msb) pd_6 pd_5 pd_4 pd_3 pd_2 pd_1 pd_0 (lsb) output digital video encoder data
- 6 - nju terminal description 3 no symbol input/output function 89 blank output the blank pin output signal becomes high during the video blanking period. 90 cref output the cref pin output becomes high when cb data is on pd7 to pd_0 pins. else it outputs low when cr data is on pd7 to pd_0. 91 hs input hs is an input pin which takes horizontal sync from dve. 92 fs input the fp pin takes the field parity signal from a dve. 30 29 28 27 sd_3 sd_2 sd_1 sd_0 output output output output audio data. 34 fs/ws output the fs/fw pin outputs frame sync or word sync signal to the device which receives audio data. 25 asck input audio data input clock. 26 areq input the areq pin takes an audio data request signal. 33 aclk input audio data input clock. 94 reset input reset 6ref input system clock(27mhz) 2rb input the rd is the pin which takes the pll loopfilter adj bias signal. 3pllv dd input analog v dd for pll 1 141 pllv ss analog v ss for pll 138 139 pllsel_2 pllsel_1 input pllsel_2,pllsel_1 are pin which takes the pll mode control signal. 143 lpfen input lpfen is a pin that takes a signal which enables the low pass filter in pll. 144 cpout input cpout is charge pump output pin for the external loop filter. 137 counter output counter pll counter output signal 142 vcoin input vcoin is the vco input pin for the external loop ffilter. 4 15 24 32 40 48 56 64 72 80 88 96 104 112 120 128 136 v dd this is the power pin : 3.3v
- 7 - nju terminal description 4 no symbol input/output function 5 17 23 31 39 47 55 63 71 79 87 95 103 111 119 127 135 v ss this is the ground : 0v terminal description 5 (not used by user) no symbol input/output function 7 td input during the normal mode, this pin must be the ground : 0v. 14 test output during the normal mode, this pin must be ?open?. 93 scan_en input 97 memb input 98 mema input during the normal mode, this pin must be the ground : 0v. 99 po output during the normal mode, this pin must be ?open?. 100 pi input during the normal mode, this pin must be the ground : 0v. 101 iddp input 102 tn input during the normal mode, this pin must be v dd : 3.3v. 140 tstn input during the normal mode, this pin must be the ground : 0v.
- 8 - nju function overview nju28001 contains ninemain processing modules: css processor, bitstream paser, sdram controller, video decoder, osd processor, video display processor, sub picture processor, audio video syncronizer, and audio i/f-lpcm decoder. for its proper operations, each module needs to be programmed by the external controller. the incoming bitstream is fed to css modules first. if the bitstream is a dvd stream, dvd authentication process must be achieved between external host system and nju28001 . and css descrambling must be enabled. otherwise it shall be set bypass mode. the output of css is fed to the bitstream parsing modules where an appropriate packet data are filtered out and sent to the external sdram. the mpeg video decoder is in charge of decoding mpeg video stream and reconstructs video image into the area in sdram. the sub-picture unit decodes data in subpicture stream and the decode image is send out to dve after blended with the main decode video data. osd processor decodes a osd packet data stored in sdram. the display processor is in charge of displaying the decoded video image in sdram. it closely communicates the mpeg video decoding core to ensure synchronization of display with the video decoding activities. also it controls the rest of display related modules: subpicture and osd. audio data extracted from the primary input bitstream is pass to the external audio decoder. if the bitstream is the lpcm data, the built in lpcm decoder can unpack it and sends out max 8 channels of lpcm data stream to d/a converters. (1) sdram interface nju28001 can suports four sdram configulation: 1x16mbit, 2x16mbit, 1 x 64mbit, 1x 64mbit(2bank). for example, a ntsc video decoding system with 16mbit external sdram configulation (2) bitstream processor the most primitive bitstream is a mpeg video elementary stream. to take this stream, it is required to opening channel 1 path. if an incoming bitstream is mpeg1 system or mpeg2 program stream, the nju28001 parses its pes syntax. if stream id options are provided only matching video and/ or audio stream are fed to channel 1 and 2 in sdram. in case of the dvd bitstream, video pes packets are fed to channel 1, one of audio stream is fed to channel 2. and subpicture and navigation streams are fed to channel 3 and 4 respectively. (3) video decoding when enough amount of bitstream is accumulated in the video bitstream data area, decoding operation is issuued by the external controller. down to the macro block layer, the micro controller processes the decoding operations. a picture is reconstructed by macroblock. since the decoded image must be displayed, the video decode unit operates synchronuslly to the display processor. while the decoding operation is in progress, nju28001 may receive a trick mode command such as freeze display or skip display. when it occurs, depending on the type of each command, the video decoding unit will take a special operation. (4) audio bitstram processing and decoding nju28001 contains an audio bitstream interfacing and lpcm decoding processor. when the direct read of the coded audio bitstream is selected by programming parameters, coded data interface module fetches the audio data in dram sends it out in nju28001 ?s serial data format. if lpcm decoding is selected, the bitstream is fetched from sdram, decoded and sending out in i 2 s or eiaj format. (5) system synchronization one unique feature of nju28001 is automatic of elementary bitstream from a system. it is acheived by vpes unit. the vpes unit extracts pts time stamp embedded in pes packet header. the extracted pts information is fed to sync unit which keeps track of pts value and picture. (6) video display nju28001 operates its display as slave to the external digital video encoder. it receives horizontal sync(hs) and vertical sync(vs) signals. depending on the type of signal (ntsc or pal), all parameters must be defined accordingly. (7) sub-picture data display to enable display of subpicture data host must be bit 4 of reg to high. with sp-palette information coded in pci of navigation data, the external host can program a color map register table inside sp contrpller otherwise the default values will be used.
- 9 - nju hardware interface (1) host bus interface ? 8-bit data bus (d7:0) ? 8-bit address bus(ha7:0) ? chip select(cs) ? read/write control(rd) ? interrupt(intr) ? wait state indication for read cycle(wait) (2) bitstream interface the bitstream input interface is an 8-bit data port with 4 control signals. nju28001 support up to 23mbps channel input rate. (3) video interface video interface has an 8-bit nju28001 dve hs fp pdi [ 7:0 ] 27mhz nju28001 cd/dvd chan dec dreq dvalid dclk pdi[7:0] sos nju28001 host cs rd intr d[7:0] ha [ 7:0 ] wait
- 10 - nju (4) audio interface 1. type 1 : coded data audio interface 2. type 2 : linear pcm audio interface nju28001 dac a clk ( 256fs/384fs areq fsws sd asck in case of using dac vss nju28001 audio decoder a clk areq fsws sd asck in case of using audio decoder
- 11 - nju (5) sdram interface nju28001 support single 16mbits sdram, double 16mbits sdram and single 64mbits sdram of both 2-bank and 4-bank types. nju28001 sdram clk cke(v dd ) dqm(gnd) ba0 cs(gnd) ras0,we0,cas0 a[10:0] dq[15:0] nju28001 sdram clk cke(v dd ) dqm(gnd) ba1,ba0 cs(gnd) ras0,we0,cas0 a[11:0] dq[15:0] 64mbitdram x 1 (4banks) nju28001 sdram clk cke(v dd ) dqm(gnd) ba0 cs ( gnd ) ras0,we0,cas0 a[12:0] dq[15:0] 64mbitdram x 1(2banks) 16mbit dram x 1
- 12 - nju (6) pll interface nju28001 has pll circuitry to generate an 81mhz sdram clock. a loop filter is controlled by the ?lpfen? pin. if this pin is low, the internal loop filter is used. in this case ?rb? pin should be connected to vdd via a register. nju28001 27mhz ttlclock r v dd r r ? ? ref rb vcoin cpout lpfin r
- 13 - nju programming registers [ control commands (registers) table ] name address r/w description reset state note 00h data chain reg[7:0] 00h 01h data chain reg[15:8] 00h 02h data chain reg[23:16] 00h 03h data chain reg[31:24] 00h 04h data chain reg[39:32] 00h 05h data chain reg[47:40] 00h 06h data chain reg[55:48] 00h data chain registers 07h r/w data chain reg[63:56] 00h name address r/w description reset state note code data input 08h r/w code data input control register 17h general control registers 09h w general control register 00h 0ah interrupt register 0 00h 0bh interrupt register 1 00h interrupt registers 0ch r/w interrupt register 2 00h 10h memory partition register 0 00h 11h memory partition register 1 00h 12h memory partition register 2 00h 13h memory partition register 3 00h 14h memory status register 1 00h 15h navigation data status register 00h 16h r/w memory data transfer register 0000b 17h buffer ram write address register 0000b 18h w buffer ram read address register 0000b memory programming and s/dram access registers 19h r/w memory configuration register 00h 20h w css command register 000b 21h r css status register 000b 22h w css data write register 00h 23h r css data read register 00h 24h w channel open control register 0000b 25h w bitstream selection register 0100011b 26h w video stream id register 0000b 27h w audio stream id register 00000b bitstream programming registers 28h w subpicture stream id register 00000b
- 14 - nju name address r/w description reset state note 30h r/w sync unit control register 0000000b 31h w sync unit status 0 register 00h av synchronization programming registers 32h w sync unit status 1 register 000000b 40h w video display control register 0 0110b 41h w video display control register 1 000b 42h w video display control register 2 00b 43h w video display control register 3 00000b 44h w video display control register 4 00h 45h w video display control register 5 80h 46h w video display control register 6 00h 47h w video display control register 7 a8h 48h w video display control register 8 00h 49h w video display control register 9 00h 4ah w video display control register a 00h 4bh w trick mode command register 1 00h 4ch w trick mode command register 2 00h 4dh w trick mode command register 3 00h 4eh r/w subpicture status register 1 00h video programming registers 4fh w subpicture status register 2 00b 50h w audio stream processor register 1 4ah 51h w audio stream processor register 2 0000b audio programming registers 52h r audio stream processor register 3 20h 60h w vpes debugging register t.b.d 61h r/w apes debugging register 1 23h 62h w apes debugging register 2 000b 63h r nbit status register -- 64h r/w uc debugging register 00h 65h w display debugging register 00h 66h w module reset register 00h 67h w module reset register 000b 68h w uc debugging register 0b debugging registers 69h w sdc debugging register 1 00000b
- 15 - nju absolute maximum ratings (ta=25 c) parameter symbol ratings unit supply voltage v dd -0.3 to +3.6 v input voltage v in -0.3 to +3.6 v output voltage v out -0.3 to +3.6 v operating temperature t opr -20 to +75 c storage temperature t stg -55 to +120 c dc characteristics parameter symbol condition min typ max unit supply voltage v dd v dd 3.15 3.45 v supply current i dd v dd , v dd =3.45v, f osc =27mhz 350 ma high-level input voltage v ih 2.0 v dd v high-level output voltage v oh i oh =-0.4ma 2.4 v low-level output voltage v ol i ol =2ma 0.4 v [caution] the specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. the application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights.

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