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SCG9800 8-bit microcontroller score concept semiconductor ltd. 1 sept 2000 SCG9800 microcontroller specification feature summary technology ? cmos technology. cpu ? 8-bit cpu core. ? 128 powerful and easy-to-use instruction set. memory ? internal ram: 240 x 8 ? memory is organized as 16k-byte page. ? external memory access of up to 1m x 8, can be both rom and ram. i/o structure ? memory mapped i/o structure. oscillation frequency ? rc oscillator for the main system clock up to 4mhz, instruction cycle ~0.5us. ? subsystem clock frequency of 32.768khz for real time timer. power down ? stop mode (stop main and subsystem clock to core) ? sleep mode (stop main system clock only) interrupts ? 2 timer interrupts. ? 1 real time interrupt. ? 1 external event interrupt. ? 1 software interrupt. i/o ports ? 1 8-bit programmable i/o port. ? 1 2-bit output port. timer ? 2 8-bit pre-scalar auto reload timers which can be cascaded to form one 16-bit timer. ? 1 real time timer. ? 1 watch dog timer. operating voltage ? 2.4v to 5.5v.
SCG9800 8-bit microcontroller score concept semiconductor ltd. 2 sept 2000 function overview program memory map ram area: address description $00-$0f h/w registers and i/os $10-$ff data memory and stack figure 1. memory map in ram area external rom area: physical address description $0000-$3fff page 0 program reset address at $0000 $4000-$7fff page 1 $8000-$bfff page 2 $c000-$ffff page 3 software interrupt at $ffc0 external interrupt at $ffd0 timer 1 interrupt at $ffe0 timer 0/rtc interrupt at $fff0 : : $7c000-$7ffff page 31 : : $fc000-$fffff page 63 figure 2. memory map in external rom area ~ ~ ~ ~
SCG9800 8-bit microcontroller score concept semiconductor ltd. 3 sept 2000 cpu core an 8-bit accumulator based cpu core can directly address up to 64 x 16k byte addressing space. most of the instructions are executed in two cycles. instruction is generally one byte and will have an extra byte for some addressing modes. cpu registers: program counter (pc) the 14-bit program counter stores address for instruction fetch during program execution. it makes up a page size of 16k bytes. together with the program page register (ipage), it becomes a 20-bit address that can access up to 1,048,576 bytes. when the cpu resets, the content of the ipage:pc will be 00:0000. if interrupt occurs, the type of interrupt will then determine its content. pc will automatically be incremented to the next instruction after an instruction fetch. table 1. different types of interrupt interrupt ipage:pc timer 0 / rtc interrupt 3h:3ff0h timer 1 interrupt 3h:3fe0h external interrupt 3h:3fd0h software interrupt 3h:3fc0h page register (page) an 8-bit page register is used to change the program flow. the most significant two bits are always set to zero. data bank register (bank) an 8-bit bank register is used to access data memory. the most significant two bits are always set to zero. program page register (ipage) an 8-bit program page register is combined with pc for instruction fetch. the most significant two bits are always set to zero. accumulator (a) an 8-bit accumulator is used for arithmetic, logical and data movement operation. temporary register (b) an 8-bit temporarily storage is used for accumulator. index registers (x, y) these two 8-bit registers can be used for general registers and index registers of the indirect addressing mode. they can also be used as pointer for table read and memory write instructions.
SCG9800 8-bit microcontroller score concept semiconductor ltd. 4 sept 2000 stack register (sp) an 8-bit stack register (sp) stores the address for stack operation. after cpu resets, the value is $00. the sp has to be initialized at $ff by software. this means the stack frame starts from the highest address memory location. program status (ps) this is an 8-bit program status register. however only 4-bit is used for controlling alu operations and instruction execution sequences. program status bit 76543210 figure 3. 8-bit program status carry flag (c) whenever there is a carry or borrow occurs after an arithmetic operation, carry flag is set to 1. otherwise, it is cleared to 0. besides, the ?rotate? instructions can also change the carry flag which value is a bit shifted out of the specified source operand. executing single instruction of ?setc? or ?clrc? can also alter this flag. upon returning from an interrupt service routine, this flag will be restored. zero flag (z) for arithmetic and logical operations, zero flag will be set to 1 if the result is zero. besides, for operation that involves moving source operand to accumulator, zero flag will also be set to 1 if the content of the source operand is zero. upon returning from an interrupt service routine, this flag will be restored. sign flag (n) sign flag stores the most significant bit of a result after the following operations: - a. arithmetic b. logic c. move from source operand to accumulator this flag will also be restored upon returning from an interrupt service routine. reserved sign zero carry interrupt mask
SCG9800 8-bit microcontroller score concept semiconductor ltd. 5 sept 2000 interrupt mask flag (i) the flag will be set to 1 when entering an interrupt service routine. by that time, all other interrupt events will be pending. after exiting from the interrupt service routine, this interrupt mask flag will be cleared to 0. then interrupt handling will be resumed. memory by connecting pad_ext_addr to high, external memory access of 512k bytes is allowed. in addition, setting bit5 of the internal register tcong will expand memory access to another 512k bytes. this extra external memory block can be ram or rom. for this rom-less chip, memory is arranged in 16k-byte page size each. therefore, there can have 32 pages for 512k bytes of memory space. regarding the instruction pointer, it is organized as ipage:pc for instruction fetch. change of program flow between pages is by modifying the page register and then followed by executing a jmp or call instruction. these two instructions will load the page register to ipage and change the content in pc for long jmp or call instruction. it does not need to change the page register if it is a short jmp/call (i.e. jmp/call within page) because the page register is normally the same as the ipage register. to exit a subroutine, long or short return type must be specified for long or short call respectively. the microcontroller has 240 bytes internal ram data storage of address $10-$ff. this area includes stack frame and data memory. the stack frame is usually initialized at the highest ram address location, i.e. $ff. oscillation circuits main system and subsystem oscillation circuitry generates the internal clock signal for the cpu and other hardware timings. the main system clock uses the rc oscillation source. the operating frequency is up to 4 mhz. this clock is for the cpu and the two timers. the subsystem clock is for the real time signals. it uses a 32.768 khz crystal. it has to be tied to a voltage level, either high or low, if the real time timer and the watch dog timer are not used. power down the microcontroller supports power down mode for saving power. executing a stop instruction will stop both main system and subsystem clock to the core to save most of the microcontroller power. to enter sleep mode, execute a sleep instruction will stop the system clock only. only an external interrupt will release the microcontroller from stop mode if external interrupt enable bit is set to 1. for sleep mode, the microcontroller will be awoken every 0.5 sec or by the external interrupt if corresponding enable bit is set to 1.
SCG9800 8-bit microcontroller score concept semiconductor ltd. 6 sept 2000 interrupts the microcontroller has 2 timer interrupts, one real time interrupt, one external event interrupt and one software interrupt. when interrupt occurs, the content of pc, ipage and ps are pushed onto the stack in sequence. and then, the corresponding interrupt vector is loaded into ipage:pc. upon executing a rti instruction, the registers are popped out of the stack in the reversed order. the preference of interrupt priority is timer 0 / rtc interrupt, timer 1 interrupt and then external interrupt. i/o ports the microcontroller has one 2-bit output port and one software-controllable 8-bit i/o port. for i/o port 0, there is a pull-low resistor when it is configured in input mode, and this resistor is disabled when it is in output mode. for port 5, it is a 2-bit output port only. remark: port 4 bit3 can be an output if the chip is not configured as 8m bits external memory access via setting bit6 of the internal register tcong. timers the microcontroller has two programmable 8-bit timers (t0 and t1) for system timing. it has also a real time timer and a watch dog timer when subsystem clock is employed. all the timers can be enabled or disabled by configuring an internal register, tcong. at cpu resets, all of them are disabled. t0 and t1 are up-counters and can be configured as either two 8-bit pre-scalar auto reload timer or as a 16-bit pre-scalar auto reload timer. the timer overflow flag will be set if the timer overflows. then an interrupt will be generated if the corresponding interrupt enable bit is set to 1. the real time timer provides 0.5 sec interrupt for rtc functions. watch dog timer will overflow in ~1 sec and then will reset the cpu.
SCG9800 8-bit microcontroller score concept semiconductor ltd. 7 sept 2000 block diagram figure 4. block diagram of SCG9800 timer0 timer1 osc rtc watch dog internal ram 240x8 data bus address bus & control xtal interrupt control b x y sp ps pc ipage bank a page control alu d[7:0] p0 a[18:0] cpu core p43/a19 p5 p0 output latch p5 output latch p43 a19 sel mux rd wr cs1 cs2
SCG9800 8-bit microcontroller score concept semiconductor ltd. 8 sept 2000 pin descriptions table 2. pin description pin name type description pad type 1 a0 o/p address bus pad type 2 2 a1 o/p address bus pad type 2 3 a2 o/p address bus pad type 2 4 a3 o/p address bus pad type 2 5 a4 o/p address bus pad type 2 6 a5 o/p address bus pad type 2 7 a6 o/p address bus pad type 2 8 a7 o/p address bus pad type 2 9 vdd power supply voltage 10 vss power ground 11 d0 i/o data bus pad type 1 12 d1 i/o data bus pad type 1 13 d2 i/o data bus pad type 1 14 d3 i/o data bus pad type 1 15 d4 i/o data bus pad type 1 16 d5 i/o data bus pad type 1 17 d6 i/o data bus pad type 1 18 d7 i/o data bus pad type 1 19 p50 o/p port 5 pad type 2 20 p51 o/p port 5 pad type 2 21 - 22 - 23 p00 i/o port 0 pad type 1 24 p01 i/o port 0 pad type 1 25 p02 i/o port 0 pad type 1 26 vdd power supply voltage 27 vss power ground 28 p03 i/o port 0 pad type 1 29 p04 i/o port 0 pad type 1 30 p05 i/o port 0 pad type 1 31 p06 i/o port 0 pad type 1 32 p07 i/o port 0 pad type 1 33 ext_addr i/p external address pad type 4 34 test_rom i/p test pin, no connection pad type 4 35 vss power ground 36 vdd power supply voltage 37 reset i/p reset pin pad type 3 38 ext_int i/p external interrupt pin pad type 4 39 clk32i i/p 32.768khz rtc pad type 6
SCG9800 8-bit microcontroller score concept semiconductor ltd. 9 sept 2000 pin name type description pad type 40 clk320 o/p 32.768khz rtc pad type 6 41 test i/p test pin, no connection pad type 4 42 p_clk_0 o/p rc oscillator output pad type 6 43 p_clk i/p rc oscillator for the main system clock pad type 5 44 a15 i/o address bus pad type 1 45 a14 i/o address bus pad type 1 46 a13 i/o address bus pad type 1 47 a12 i/o address bus pad type 1 48 a11 i/o address bus pad type 1 49 a10 i/o address bus pad type 1 50 a9 i/o address bus pad type 1 51 a8 i/o address bus pad type 1 52 vss power ground 53 vdd power supply voltage 54 cs2 o/p chip select 2 pad type 2 55 cs1 o/p chip select 1 pad type 2 56 wr o/p write signal pad type 2 57 rd o/p read signal pad type 2 58 p43/a19 o/p port 4 bit3/ address bus bit19 pad type 2 59 a18 o/p address bus pad type 2 60 a17 o/p address bus pad type 2 61 a16 o/p address bus pad type 2
SCG9800 8-bit microcontroller score concept semiconductor ltd. 10 sept 2000 schmitt input tristate control bond pad data in data out output enable figure 5. pad type 1 (bi-directional pad) tristate control data out output enable bond pad figure 6. pad type 2 (output pad) schmitt input reset figure 7. pad type 3 ( reset )
SCG9800 8-bit microcontroller score concept semiconductor ltd. 11 sept 2000 schmitt input int figure 8. pad type 4 (external interrupt) rc circuitry test clock out enable test=0 test=1 rc pad figure 9. pad type 5 (rc oscillation pad) 32.768 khz 10m ? 47pf 47pf clk32i clk32o figure 10. pad type 6 (clock circuit)
SCG9800 8-bit microcontroller score concept semiconductor ltd. 12 sept 2000 control registers summary table 3. summary of control registers hex mnemonic control registers name r/w 00h p0dir port 0 direction control register w 01h p0pull port 0 pull-low control register w 02h p0rw port 0 read/write port r/w 03h p1dir port 1 direction control register w 04h p1rw port 1 read/write port r/w 05h p2w port 2 output port w 06h - - - 07h p4w port 4 output port w 08h p5w port 5 output port w 09h tcong timer configuration port w 0ah intr interrupt control register w 0bh tflag timer flag status register/watch-dog reset r/w 0ch t0val timer 0 preset value register w 0dh t1val timer 1 preset value register w 0eh - - - 0fh - - - descriptions p0dir and p1dir bit 76543210 r/w wwwwwwww figure 11. port 0 and port 1 direction control registers p0pull bit 76543210 r/w wwwwwwww figure 12. port 0 pull-low control register 0: input mode (default) 1: output mode 0: pull-low resistor disable (default) 1: pull-low resistor enable
SCG9800 8-bit microcontroller score concept semiconductor ltd. 13 sept 2000 p0rw and p1rw bit 76543210 r/w r/w r/w r/w r/w r/w r/w r/w r/w figure 13. port 0 and port 1 read/write port p2w bit 76543210 r/w wwwwwwww figure 14. port 2 output port write to output latch write to output latch. read from input pin. read value of output pin will be the output latch value.
SCG9800 8-bit microcontroller score concept semiconductor ltd. 14 sept 2000 tcong bit 76543210 r/w - - - wwwww figure 15. timer configuration port 000 : disable t0 and t1 0x1 : enable t0 01x : enable t1 1xx : cascade t0:t1 as 16-bit timer real time timer 0 : disable 1 : enable (0.5s interrupt) watch dog timer 0 : disable 1 : enable (~1s) reserved external memory access mode, emm (see below) external memory access, em 0 : disable (default) 1 : enable external memory access mode, emm with external memory access enabled, i.e. em set, external memory ext-addr emm size chip select 004m-bit cs1 012m-bit cs1 2m-bit cs2 104m bit cs1 4m bit cs2 118m bit cs1
SCG9800 8-bit microcontroller score concept semiconductor ltd. 15 sept 2000 intr bit 76543210 r/w-----www figure 16. interrupt control register tflag bit 76543210 r/w----rrrr figure 17. timer flag status register/watch-dog reset t0/rtc (half second) interrupt 0 : disable 1 : enable t1 interrupt 0 : disable 1 : enable external interrupt 0 : disable 1 : enable reserved 0 : t0 not overflow 1 : t0 overflow 0 : t1 not overflow 1 : t1 overflow 0 : not half second 1 : half secon d clk32i input reserved note : read will reset all flags. any write operation to tflag will reset the watch dog timer.
SCG9800 8-bit microcontroller score concept semiconductor ltd. 16 sept 2000 t0val and t1val bit 76543210 r/w wwwwwwww figure 18. timer 0 and timer 1 preset value register write timer 0 and timer 1 preset value value counter clock system frequency timer 1 2 = for either t0 or t1, maximum counter value = 255 minimum frequency 7840hz for t0:t1, maximum counter value = 65535 minimun frequency 30hz
SCG9800 8-bit microcontroller score concept semiconductor ltd. 17 sept 2000 instruction summary there are 128 instructions. all instructions are one or two byte instructions. the followings are the notations used: a accumulator b b register ccarry bit z zero bit n negative bit x x index register y y index register sp stack pointer register (sp) stack bank data bank register page page register ipage the page register for pc19-pc14 pc program counter pc13-0 ps program status i interrupt flag (x) ram pointed by x (y) ram pointed by y label a 8-bit ram/register label (label) ram pointed by the label addr14 a 14-bit address addr 8 a 8-bit address #constant a 8-bit constant
SCG9800 8-bit microcontroller score concept semiconductor ltd. 18 sept 2000 instruction set 1. adc a code 0100 0000 operation a + a + c a flags n, z, c 2. adc x code 0100 0010 operation x + a + c a flags n, z, c 3. adc y code 0100 0011 operation y + a + c a flags n, z, c 4. adc (x) code 0100 0110 operation (x) + a + c a flags n, z, c 5. adc (y) code 0100 0111 operation (y) + a + c a flags n, z, c 6. adc label code 0100 0100 zzzz zzzz operation (zzzz zzzz)+a+c a flags n, z, c 7. adc #constant code 0100 0001 zzzz zzzz operation zzzz zzzz +a+c a flags n, z, c 8. and a code 0100 1000 operation a a a flags n,z 9. and x code 0100 1010 operation x a a flags n,z 10. and y code 0100 1011 operation y a a flags n,z 11. and (x) code 0100 1110 operation (x) a a flags n,z 12. and (y) code 0100 1111 operation (y) a a flags n,z 13. and label code 0100 1100 zzzz zzzz operation (zzzz zzzz) a a flags n,z 14. and #constant code 0100 1001 zzzz zzzz operation zzzz zzzz a a flags n,z 15. bra addr8 code 0011 0010 zzzz zzzz operation zzzz zzzz pc0-7 flags -----
SCG9800 8-bit microcontroller score concept semiconductor ltd. 19 sept 2000 16. call addr14 code 11zz zzzz zzzz zzzz operation pc (sp);sp-2 sp addr14 pc[13:0] if page ipage ipage (sp);sp-1 sp page ipage flags ----- 17. clr a code 0010 1000 operation 0 a flags n,z 18. clr x code 0010 1010 operation 0 x flags ----- 19. clr y code 0010 1011 operation 0 y flags ----- 20. clr (x) code 0010 1110 operation 0 (x) flags ----- 21. clr (y) code 0010 1111 operation 0 (y) flags ----- 22. clr label code 0010 1100 operation 0 (zzzz zzzz) flags ----- 23. clrc code 0110 0001 operation 0 c flags c 24. cmp code 0000 0001 zzzz zzzz operation a ? zzzz zzzz flags z 25. cmp label code 0000 0101 zzzz zzzz operation a ? (zzzz zzzz) flags z 26. cpmx #constant code 0000 1001 zzzz zzzz operation (x) ? zzzz zzzz flags z 27. cpmx label code 0000 1101 zzzz zzzz operation (x) ? zzzz zzzz flags z 28. cpx #constant code 0001 0001 zzzz zzzz operation x ? zzzz zzzz flags z 29. cpx label code 0001 0101 zzzz zzzz operation x ? (zzzz zzzz) flags z 30. cpy #constant code 0001 1001 zzzz zzzz operation y ? zzzz zzzz flags z 31. cpy label code 0001 1101 zzzz zzzz operation y ? (zzzz zzzz) flags z
SCG9800 8-bit microcontroller score concept semiconductor ltd. 20 sept 2000 32. dec a code 0110 1000 operation a ? 1 a flags n, z, c 33. dec x code 0110 1010 operation x ? 1 x flags n, z, c 34. dec y code 0110 1011 operation y ? 1 y flags n, z, c 35. dec (x) code 0110 1110 operation (x) ? 1 (x) flags n, z, c 36. dec (y) code 0110 1111 operation (y) ? 1 (y) flags n, z, c 37. dec label code 0110 1100 zzzz zzzz operation (zzzz zzzz)-1 (zzzzzzzz) flags n, z, c 38. eor x code 0101 1010 operation x ? a a flags n, z 39. eor y code 0101 1011 operation y ? a a flags n, z 40. eor (x) code 0101 1110 operation (x) ? a a flags n, z 41. eor (y) code 0101 1111 operation (y) ? a a flags n, z 42. eor label code 0101 1100 zzzz zzzz operation (zzzz zzzz) ? a a flags n, z 43. eor #constant code 0101 1001 zzzz zzzz operation zzzz zzzz ? a a flags n, z 44. inc a code 0110 0000 operation a + 1 a flags n, z, c 45. inc x code 0110 0010 operation x + 1 x flags n, z, c 46. inc y code 0110 0011 operation y + 1 y flags n, z, c 47. inc (x) code 0110 0110 operation (x) + 1 x flags n, z, c 48. inc (y) code 0110 0111 operation (y) + 1 y flags n, z, c
SCG9800 8-bit microcontroller score concept semiconductor ltd. 21 sept 2000 49. inc label code 0110 0100 zzzz zzzz operation (zzzz zzzz) + 1 (zzzz zzzz) flags n, z, c 50. int code 0011 0110 operation pc low (sp), sp-1 sp pchigh (sp), sp-1 sp ipage (sp), sp-1 sp ps (sp), sp-1 sp 1 i 3fc0h pc 3 ipage,page flags i 51. ja code 0111 0001 operation a pc[7:0] flags ----- 52. jump addr14 code 10zz zzzz zzzz zzzz operation addr14 pc[13:0] if page ipage page ipage flags ----- 53. mov a, x code 0000 0010 operation a x flags ----- 54. mov a, y code 0000 0011 operation a y flags ----- 55. mov a, (x) code 0000 0110 operation a (x) flags ----- 56. mov a, (y) code 0000 0111 operation a (y) flags ----- 57. mov a label code 0000 0100 zzzz zzzz operation a (zzzz zzzz) flags ----- 58. mov x, a code 0001 0000 operation x a flags n, z 59. mov x, y code 0001 0011 operation x y flags ----- 60. mov x, (y) code 0001 0111 operation x (y) flags ----- 61. mov x, label code 0001 0100 zzzz zzzz operation x (zzzz zzzz) flags ----- 62. mov y, a code 0001 1000 operation y a flags n, z
SCG9800 8-bit microcontroller score concept semiconductor ltd. 22 sept 2000 63. mov y, x code 0001 1010 operation y x flags ----- 64. mov y, (x) code 0001 1110 operation y (x) flags ----- 65. mov y, label code 0001 1100 zzzz zzzz operation y (zzzz zzzz) flags ----- 66. mov (x), a code 0011 0000 operation (x) a flags n, z 67. mov (x), y code 0011 0011 operation (x) y flags ----- 68. mov (x), (y) code 0011 0111 operation (x) (y) flags ----- 69. mov (x), label code 0011 0100 zzzz zzzz operation (x) (zzzz zzzz) flags ----- 70. mov (y), a code 0011 1000 operation (y) a flags n, z 71. mov (y), x code 0011 1010 operation (y) x flags ----- 72. mov (y), (x) code 0011 1110 operation (y) (x) flags ----- 73. mov (y), label code 0011 1100 zzzz zzzz operation (y) (zzzz zzzz) flags ----- 74. mov label, a code 0010 0000 zzzz zzzz operation (zzzz zzzz) a flags n, z 75. mov label, x code 0010 0010 zzzz zzzz operation (zzzz zzzz) x flags ----- 76. mov label, y code 0010 0011 zzzz zzzz operation (zzzz zzzz) y flags ----- 77. mov label, (x) code 0010 0110 zzzz zzzz operation (zzzz zzzz) (x) flags ----- 78. mov label, (y) code 0010 0111 zzzz zzzz operation (zzzz zzzz) (y) flags ----- 79. mov #constant, a code 0000 1000 zzzz zzzz operation zzzz zzzz a flags n, z
SCG9800 8-bit microcontroller score concept semiconductor ltd. 23 sept 2000 80. mov #constant, x code 0000 1010 zzzz zzzz operation zzzz zzzz x flags ----- 81. mov #constant, y code 0000 1011 zzzz zzzz operation zzzz zzzz y flags ----- 82. mov #constant, (x) code 0000 1110 zzzz zzzz operation zzzz zzzz (x) flags ----- 83. mov #constant, (y) code 0000 1111 zzzz zzzz operation zzzz zzzz (y) flags ----- 84. nop code 0000 0000 operation no operation flags ----- 85. or x code 0101 0010 operation x v a a flags n, z 86. or y code 0101 0011 operation y v a a flags n, z 87. or (x) code 0101 0110 operation (x) v a a flags n, z 88. or (y) code 0101 0111 operation (y) v a a flags n, z 89. or label code 0101 0100 zzzz zzzz operation (zzzz zzzz)v a a flags n, z 90. or #constant code 0101 0001 zzzz zzzz operation zzzz zzzzv a a flags n, z 91. pop code 0011 1111 operation sp+1 sp (sp) a flags ----- 92. pshpage code 0110 1101 operation page (sp); sp-1 sp flags ----- 93. push code 0110 1001 operation a (sp),sp-1 sp flags ----- 94. rol a code 0111 0000 operation c a c flags n, z, c 95. rol x code 0111 0010 operation c x c flags n, z, c 96. rol y code 0111 0011 operation c y c flags n, z, c
SCG9800 8-bit microcontroller score concept semiconductor ltd. 24 sept 2000 97. rol (x) code 0111 0110 operation c (x) c flags n, z, c 98. rol (y) code 0111 0111 operation c (y) c flags n, z, c 99. rol label code 0111 0100 zzzz zzzz operation c (zzzz zzzz) c flags n, z, c 100. rom a code 0111 1101 operation rom (bank,x,a) a flags ----- 101. rom y code 0111 1001 operation rom (bank,x,y) a flags ----- 102. romdbl code 0001 1001 operation rom (bank,x,y) b rom (bank,x,y+1) a flags ----- 103. ror a code 0111 1000 operation c a c flags n, z, c 104. ror x code 0111 1010 operation c x c flags n, z, c 105. ror y code 0111 1011 operation c y c flags n, z, c 106. ror (x) code 0111 1110 operation c (x) c flags n, z, c 107. ror (y) code 0111 1111 operation c (y) c flags n, z, c 108. ror label code 0111 1100 zzzz zzzz operation c (zzzz zzzz) c flags n, z, c 109. rti code 0100 0101 operation sp+1 sp (sp) ps;sp+1 1 (sp) ipage,page; sp+1 sp (sp) pchigh; sp+1 sp (sp) pclow flags ----- 110. rtl code 0100 1101 operation sp+1 sp (sp) ipage,page; sp+1 sp (sp) pchigh sp+1 sp (sp) pclow flags ----- 111. rts code 0101 0101 operation sp+1 sp (sp) pchigh; sp+1 sp (sp) pclow flags -----
SCG9800 8-bit microcontroller score concept semiconductor ltd. 25 sept 2000 112. setc code 0110 0101 operation 1 c flags c 113. setz code 0101 1000 operation 1 z,0 a, flags n, z 114. skipc code 0011 0001 operation pc+2 pc if c = 1 flags ----- 115. skipmi code 0001 0110 operation pc+2 pc if n = 1 flags ----- 116. skipnc code 0011 1001 operation pc+2 pc if c = 0 flags ----- 117. skipnz code 0010 1001 operation pc+2 pc if z = 0 flags ----- 118. skippl code 0001 1111 operation pc+2 pc if n = 0 flags ----- 119. skipz code 0010 0001 operation pc+2 pc if z = 1 flags ----- 120. sleep code 0000 1100 operation sleep flags ----- 121. stop code 0010 0100 operation stop flags ------ 122. tapage code 0011 1 0101 operation a page flags ----- 123. tz code 0101 0000 operation z=1 if a = 0 z=0 if a 0 flags n, z 124. write code 0101 1101 operation a (bank,x,y) flags ----- 125. xb code 0010 0101 operation b ? a flags ----- 126. xbank code 0011 0101 operation bank ? a flags ----- 127. xsp code 0011 1101 operation sp ? a flags ----- 128. xst code 0010 1101 operation ps ? a flags n, z, c, i
SCG9800 8-bit microcontroller score concept semiconductor ltd. 26 sept 2000 electrical characteristics absolute maximum ratings: 1. vdd 7.0v 2. vih vdd + 0.3v 3. vil vss - 0.3v 4. operating temperature 0 c to + 60 c 5. storage temperature -50 c to + 150 c recommended operating: min typ max unit 1. operating voltage (vdd) 2.4 3.0 5.5 v 2. operating frequency (fosc) - 4.0 - mhz 3. input voltage 3.1 vdd = 2.4v vih 1.6 2.0 2.4 v vil 0 0.4 0.8 v 3.2 vdd = 3.0v vih 2.0 2.4 3.0 v vil 0 0.6 1.0 v 3.3 vdd = 5.5v vih 3.6 4.0 5.5v v vil 0 1.5 1.8v v 4. output voltage 4.1 vdd = 2.4v voh 2.0 - - v @1ma vol - - 0.4 v 4.2 vdd = 3.0v voh 2.4 - - v @2ma vol - - 0.6 v 4.3 vdd = 5.5v voh 4.0 - - v @10ma vol - - 1.5 v 5. input current vih = vdd ih --0.3 a (p0, p1 and p3) - - 150 a (p0 only via internal pull-low resistor) vil = ov il - - 0.3 a (leakage) 6. output current 6.1 vdd = 2.4v, ioh@voh =2.0v 1.0 1.5 - ma iol@vol =0.4v 2.0 3.0 - ma 6.2 vdd = 3.0v, ioh@voh =2.4v 1.5 3.5 - ma iol@vol =0.6v 3.0 7.0 - ma 6.3 vdd = 5.5v, ioh@voh =4.0v 8 10 - ma iol@vol =1.5v 16 20 - ma 7. current dissipation 7.1 operating current @4mhz, 3.0v & output pad load = 50pf 1.0 1.5 4.5 ma 7.2 operating current @4mhz, 5.0v 2.0 3.0 9.0 ma & output pad load = 50pf 7.3 standby current (off mode) - 1.0 9.0 a
SCG9800 8-bit microcontroller score concept semiconductor ltd. 27 sept 2000 pad co-ordinates 61 a16 1a0 60 a17 2a1 59 a18 3a2 58 p43/a19 4a3 57 rd 5a4 56 wr 6a5 55 1 cs 7a6 54 2 cs 8a7 y 53 vdd 9 vdd 52 vss 10 vss x51a8 11 d0 (0,0) 50 a9 12 d1 49 a10 13 d2 48 a11 14 d3 47 a12 15 d4 46 a13 16 d5 45 a14 17 d6 44 a15 18 d7 19 p50 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 p51 p00 p01 p02 vdd vss p03 p04 p05 p06 p07 ext_addr test_rom vss vdd reset- ext_int clk32i clk32o test p_clk_o p_clk the substrate of ic should be connected to vss
SCG9800 8-bit microcontroller score concept semiconductor ltd. 28 sept 2000 pad no pad name x y pad no pad name x y 1 a0 -1773.100 1127.050 41 test 1496.500 -1722.550 2 a1 -1773.100 987.050 42 p_clk_0 1636.500 -1722.550 3 a2 -1773.100 847.050 43 p_clk 1776.500 -1722.550 4 a3 -1773.100 707.050 44 a15 1766.900 -746.700 5 a4 -1773.100 567.050 45 a14 1766.900 -606.700 6 a5 -1773.100 427.050 46 a13 1766.900 -466.700 7 a6 -1773.100 287.050 47 a12 1766.900 -326.700 8 a7 -1773.100 147.050 48 a11 1766.900 -186.700 9 vdd -1773.100 7.050 49 a10 1766.900 -46.700 10 vss -1773.100 -132.950 50 a9 1766.900 93.300 11 d0 -1773.100 -272.950 51 a8 1766.900 233.300 12 d1 -1773.100 -412.950 52 vss 1766.900 373.300 13 d2 -1773.100 -552.950 53 vdd 1766.900 513.300 14 d3 -1773.100 -692.950 54 cs2 1766.900 653.300 15 d4 -1773.100 -832.950 55 cs1 1766.900 793.300 16 d5 -1773.100 -972.950 56 wr 1766.900 933.300 17 d6 -1773.100 -1112.950 57 rd 1766.900 1073.300 18 d7 -1773.100 -1252.950 58 p43/a19 1766.900 1213.300 19 p50 -1773.100 -1512.950 59 a18 1766.900 1353.300 20 p51 -1563.500 -1722.550 60 a17 1766.900 1493.300 21 - - - 61 a16 1766.900 1633.300 22 - - - 23 p00 -1143.500 -1722.550 24 p01 -1003.500 -1722.550 25 p02 -863.500 -1722.550 26 vdd -723.500 -1722.550 27 vss -583.500 -1722.550 28 p03 -443.500 -1722.550 29 p04 -303.500 -1722.550 30 p05 -163.500 -1722.550 31 p06 -23.500 -1722.550 32 p07 116.500 -1722.550 33 ext_addr 256.500 -1722.550 34 test_rom 396.500 -1722.550 35 vss 656.500 -1722.550 36 vdd 796.500 -1722.550 37 reset 936.500 -1722.550 38 ext_int 1076.500 -1722.550 39 clk32i 1216.500 -1722.550 40 clk320 1356.500 -1722.550
SCG9800 8-bit microcontroller score concept semiconductor ltd. 29 sept 2000 application circuit SCG9800 1 SCG9800 application circuit a 11 saturday, september 16, 2000 title size document number rev date: sheet of vcc vcc optional optional score concept semiconductor limited a0 a1 a2 a3 a4 a5 a6 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 rd- d0 d1 d2 d3 d4 d5 d6 d7 a7 d0 d1 d2 d3 d4 d5 d6 d7 p5w0 p5w1 wr- cs1- cs2- a8 a9 a10 a11 a12 a13 a14 a15 rd- reset- a16 a17 a18 a0 a3 a5 a4 a1 a6 a2 a7 p43/a19 r1 1m c1 c2 u4 27c040 a0 12 a1 11 a2 10 a3 9 a4 8 a5 7 a6 6 a7 5 a8 27 a9 26 a10 23 a11 25 a12 4 a13 28 a14 29 a15 3 a16 2 ce 22 oe 24 o0 13 o1 14 o2 15 o3 17 o4 18 o5 19 o6 20 o7 21 a17 30 a18 31 c3 22p r2 100k y1 32768 r3 47k c4 0.1u d3 led d4 led d2 led d1 led u5 SCG9800 a7 8 vdd 9 a0 1 a1 2 a2 3 a3 4 a4 5 a5 6 a6 7 gnd 10 d0 11 d1 12 d2 13 d3 14 d4 15 d5 16 d6 17 d7 18 p50 19 p51 20 p00 23 p01 24 p02 25 vdd 26 gnd 27 p03 28 p04 29 p05 30 p06 31 p07 32 ext_addr 33 test_rom 34 gnd 35 vdd 36 reset 37 ext_int 38 clk32i 39 clk32o 40 test 41 p_clk_o 42 p_clk 43 a15 44 a14 45 a13 46 a12 47 a11 48 a10 49 a9 50 a8 51 gnd 52 vdd 53 cs2 54 cs1 55 wr 56 rd 57 p43/a19 58 a18 59 a17 60 a16 61

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