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thgbm1gxdxebaix 2008-12-08 1 toshiba e-mmc module 1gb / 2gb / 4gb / 8gb / 16gb / 32gb thgbm1gxdxebaix series introduction thgbm1gxdxebaix series are 1-gb , 2-gb , 4-gb , 8-gb , 16-gb and 32-gb densities of e-mmc module products housed in 153/169 ball bga package. this unit is utilized advanc ed toshiba nand flash device(s) and controller chip assembled as multi chip module. thgbm1gxdxebaix has an industry standard mmc protocol for easy use. features thgbm1gxdxebaix series interface thgbm1gxdxebaix has the-mmca 4.3 interface wi th either 1-i/o, 4-i/o and 8-i/o mode support. pin connection 11.5mm x 13.0mm x 1.2mm(max) package pin number name pin number name a3 dat0 h10 vss a4 dat1 j10 vcc a5 dat2 k8 vss b2 dat3 k9 vcc b3 dat4 m4 vccq b4 dat5 m5 cmd b5 dat6 m6 clk b6 dat7 n2 vssq c2 vddi n4 vccq c4 vssq n5 vssq c6 vccq p3 vccq e6 vcc p4 vssq e7 vss p5 vccq f5 vcc p6 vssq g5 vss
thgbm1gxdxebaix 2008-12-08 2 12.0mm x 16.0mm x 1.3mm(max) package 12.0mm x 18.0mm x 1.3mm(max) package 12.0mm x 18.0mm x 1.4mm(max) package 14.0mm x 18.0mm x 1.4mm(max) package pin number name pin number name h3 dat0 r10 vss h4 dat1 t10 vcc h5 dat2 u8 vss j2 dat3 u9 vcc j3 dat4 w4 vccq j4 dat5 w5 cmd j5 dat6 w6 clk j6 dat7 y2 vssq k2 vddi y4 vccq k4 vssq y5 vssq k6 vccq aa3 vccq m6 vcc aa4 vssq m7 vss aa5 vccq n5 vcc aa6 vssq p5 vss
thgbm1gxdxebaix 2008-12-08 3 part numbers available e-mmc module products ? part numbers toshiba part number density package size nand flash type weight thgbm1g3d1ebai8 1-gbytes 11.5mm x 13.0mm x 1.2mm(max) 1 x 8gbit mlc 43nm tbd thgbm1g4d1ebai7 2-gbytes 12.0mm x 16.0mm x 1.3mm(max) 1 x 16gbit mlc 43nm tbd thgbm1g5d2ebai7 4-gbytes 12.0mm x 16.0mm x 1.3mm(max) 2 x 16gbit mlc 43nm 0.41g typ. thgbm1g6d4ebai4 8-gbytes 12.0mm x 18.0mm x 1.3mm(max) 4 x 16gbit mlc 43nm 0.45g typ. thgbm1g7d8ebai0 16-gbytes 12.0mm x 18.0mm x 1.4mm(max) 8 x 16gbit mlc 43nm 0.51g typ. thgbm1g7d4ebai2 16-gbytes 14.0mm x 18.0mm x 1.4mm(max) 4 x 32gbit mlc 43nm tbd THGBM1G8D8EBAI2 32-gbytes 14.0mm x 18.0mm x 1.4mm(max) 8 x 32gbit mlc 43nm 0.60g typ. operating temperature and humidity conditions -25c to +85c, and 0%rh to 95%rh performance 52mhz / x8 mode / sequential access min performance [mb/sec] toshiba part number density nand flash type read write thgbm1g3d1ebai8 1-gbytes 1 x 8gbit mlc 43nm 20 (target) 10 (target) thgbm1g4d1ebai7 2-gbytes 1 x 16gbit mlc 43nm 20 (target) 10 (target) thgbm1g5d2ebai7 4-gbytes 2 x 16gbit mlc 43nm 20 (target) 10 (target) thgbm1g6d4ebai4 8-gbytes 4 x 16gbit mlc 43nm 20 (target) 10 (target) thgbm1g7d8ebai0 16-gbytes 8 x 16gbit mlc 43nm 20 (target) 10 (target) thgbm1g7d4ebai2 16-gbytes 4 x 32gbit mlc 43nm 25 (target) 20 (target) THGBM1G8D8EBAI2 32-gbytes 8 x 32gbit mlc 43nm 25 (target) 20 (target) power supply v cc = 2.7v to 3.6v vccq = 1.7v to 1.95v / 2.7v to 3.6v operating current (rms) operating : 100ma max (without interleave operation) 150ma max (with interleave operation) the measurement for max rms current is done as average rms current consumption over a period of 100ms
thgbm1gxdxebaix 2008-12-08 4 sleep mode current iccqs [ua] iccqs+iccs [ua] toshiba part number density nand flash type typ. *1 max. *2 typ. *1 max. *2 thgbm1g3d1ebai8 1-gbytes 1 x 8gbit mlc 43nm 50 100 80 150 thgbm1g4d1ebai7 2-gbytes 1 x 16gbit mlc 43nm 50 100 80 150 thgbm1g5d2ebai7 4-gbytes 2 x 16gbit mlc 43nm 50 100 100 200 thgbm1g6d4ebai4 8-gbytes 4 x 16gbit mlc 43nm 50 100 150 300 thgbm1g7d8ebai0 16-gbytes 8 x 16gbit mlc 43nm 50 100 200 450 thgbm1g7d4ebai2 16-gbytes 4 x 32gbit mlc 43nm 50 100 150 300 THGBM1G8D8EBAI2 32-gbytes 8 x 32gbit mlc 43nm 50 100 200 450 *1 : the conditions of typical values are 25 c and vccq = 3.3v or 1.8v. *2 : the conditions of maximum values are 85 c and vccq = 3.6v or 1.95v. product architecture the diagram in figure 1 illustra tes the main functional blocks of the thgbm1gxdxebaix series. figure 1 thgbm1gxdxebaix series block diagram regulator vcc(3.3v) p ac k age nand control signal nand m m c i / o b l o c k core logic 1.5v operation voltage 1.5v 0.1uf n a n d i / o b l o c k nand i/o vddi vccq(1.8v/3.3v) mmc i/f(1.8v/3.3v)
thgbm1gxdxebaix 2008-12-08 5 product specifications package dimensions 11.5mm x 13mm x 1.2mm(max) unit: mm tolerance: 0.1 mm 1.2(max)
thgbm1gxdxebaix 2008-12-08 6 12mm x 16mm x 1.3mm(max) unit: mm tolerance: 0.1 mm
thgbm1gxdxebaix 2008-12-08 7 12mm x 18mm x 1.3mm(max) 12mm x 18mm x 1.4mm(max) unit: mm tolerance: 0.1 mm 1 . 4max or
thgbm1gxdxebaix 2008-12-08 8 14mm x 18mm x 1.4mm(max) unit: mm tolerance: 0.1 mm 1 . 4ma x
thgbm1gxdxebaix 2008-12-08 9 density specifications thgbm1gxdxebaix series densities parameter 1gbyte 2gbyte 4gbyte 8gbyte 16gbyte 32gbyte user area density tbd tbd 4,001,366,016 8,006,926,336 16,007,561,216 32,015,122,432 sec_count in extended csd tbd tbd 0x00774000 0x00eea000 0x01dd1000 0x3ba2000 register informations ocr register ocr bit vdd voltage window value [6:0] reserved 000 000b [7] 1.70-1.95 1b [14:8] 2.0-2.6 000 000b [23:15] 2.7-3.6 1 1111 1111b [28:24] reserved 0 0000b [30:29] access mode 10b 2 [31] ( card power up status bit (busy) ) 1 1) this bit is set to low if the card has not finished the power up routine. 2) in thgbm1g3d1ebai8(1gb) and thgbm1g4d1ebai7(2gb) case, the value is 00b. cid register cid bit name field width value [127:120] manufacturer id mid 8 0001 0001b [119:114] * reserved - 6 0b [113:112] * card/bga cbx 2 01b [111:104] * oem/application id oid 8 0b [103:56] product name pnm 48 see product name table [55:48] product revision prv 8 0000 0001b [47:16] product serial psn 32 serial number [15:8] manufacturing date mdt 8 see-mmca specification [7:1] crc7 checksum crc 7 crc7 [0] not used, always ?1? - 1 1b product name table (in cid register) part number product name in cid register density thgbm1g3d1ebai8 0x4d4d43303147 (mmc01g) 1-gbytes thgbm1g4d1ebai7 0x4d4d43303247 (mmc02g) 2-gbytes thgbm1g5d2ebai7 0x4d4d43303447 (mmc04g) 4-gbytes thgbm1g6d4ebai4 0x4d4d43303847 (mmc08g) 8-gbytes thgbm1g7d8ebai0 0x4d4d43313647 (mmc16g) 16-gbytes thgbm1g7d4ebai2 0x4d4d43313647 (mmc16g) 16-gbytes THGBM1G8D8EBAI2 0x4d4d43333247 (mmc32g) 32-gbytes
thgbm1gxdxebaix 2008-12-08 10 csd register value csd bit name field width cell type 1gb 2gb 4gb 8gb 16gb 32gb [127:126] csd structure csd_structure 2 r 10b [125:122] system specification version spec_vers 4 r 0x4 [121:120] reserved - 2 r 00b [119:112] data read access-time 1 taac 8 r 0x0e [111:104] data read access-time 2 in clk cycles (nsac * 100) nsac 8 r 0x00 [103:96] max. bus clock frequency tran_speed 8 r 0x32 [95:84] card command classes ccc 12 r 0x0f5 [83:80] max. read data block length read_bl_len 4 r 0x9 0xa* 0x9 0x9 0x9 0x9 [79:79] partial blocks for read allowed read_bl_partial 1 r 0b [78:78] write block misalignment write_blk_misalign 1 r 0b [77:77] read block misalignment read_blk_misalign 1 r 0b [76:76] dsr implemented dsr_imp 1 r 0b [75:74] reserved - 2 r 00b [73:62] device size c_size 12 r tbd tbd 0xfff 0xfff 0xfff 0xfff [61:59] max. read current @ vdd min. vdd_r_curr_min 3 r 111b [58:56] max. read current @ vdd max. vdd_r_curr_max 3 r 111b [55:53] max. write current @ vdd min. vdd_w_curr_min 3 r 111b [52:50] max. write current @ vdd max. vdd_w_curr_max 3 r 111b [49:47] device size multiplier c_size_mult 3 r 0x7 [46:42] erase group size erase_grp_size 5 r 0x1f [41:37] erase group size multiplier erase_grp_mult 5 r 0x1f [36:32] write protect group size wp_grp_size 5 r 0x03 0x07 [31:31] write protect group enable wp_grp_enable 1 r 1b [30:29] manufacturer default ecc default_ecc 2 r 00b [28:26] write speed factor r2w_factor 3 r 0x5 [25:22] max. write data block length write_bl_len 4 r 0x9 [21:21] partial blocks for write allowed write_bl_partial 1 r 0b [20:17] reserved - 4 r 0x0 [16:16] content protection application content_prot_app 1 r 0b [15:15] file format group file_format_grp 1 r 0b [14:14] copy flag (otp) copy 1 r 0b [13:13] permanent write protection perm_write_protect 1 r 0b [12:12] temporary write protection tmp_write_protect 1 r 0b [11:10] file format file_format 2 r 00b [9:8] ecc code ecc 2 r 00b [7:1] crc crc 7 r crc [0] not used, always ?1? - 1 - 1b * read_bl_len has to be equal to write_bl_len in the s pecification. however, exception to this rule is the 2gb of density device that should indicate 1kb access size in read_bl_len, and this device does not support 1kb access size.
thgbm1gxdxebaix 2008-12-08 11 extended csd register csd-slice name field size (bytes) cell type value [511:505] reserved - 7 - all ?0? [504] supported command sets s_cmd_set 1 r 0x00 [503:229] reserved - 275 - all ?0? [228] boot information boot_info 1 r 0x01 [227] reserved - 1 r all ?0? [226] boot partition size boot_size_multi 1 r 0x04 [225] access size acc_size 1 r 0x07* 0x06 [224] high-capacity erase unit size hc_erase_grp_size 1 r 0x08** 0x04 [223] high-capacity erase timeout erase_timeout_mult 1 r 0x01 [222] reliable write sector count rel_wr_sec_c 1 r 0x10*** [221] high-capacity write protect group size hc_wp_grp_size 1 r 0x01 [220] sleep current (vcc) s_c_vcc 1 r 0x09 [219] sleep current (vccq) s_c_vccq 1 r 0x07 [218] reserved - 1 - all ?0? [217] sleep/awake timeout s_a_timeout 1 r 0x10 [216] reserved - 1 - all ?0? [215:212] sector count sec_count 4 r see capacity specification table [211] reserved - 1 - all ?0? [210] minimum write performance for 8bit @ 52mhz min_perf_w_8_52 1 r 0x00 [209] minimum read performance 8bit @ 52mhz min_perf_r_8_52 1 r 0x3c [208] minimum write performance for 8bit @ 26mhz, for 4bit at 52mhz min_perf_w_8_26_4_52 1 r 0x00 [207] minimum read performance for 8 bit @ 26mhz, for 4bit at 52mhz min_perf_r_8_26_4_52 1 r 0x3c [206] minimum write performance for 4bit @ 26mhz min_perf_w_4_26 1 r 0x00 [205] minimum read performance for 4bit @ 26mhz min_perf_r_4_26 1 r 0x1e [204] reserved - 1 - all ?0? [203] power class for 26mhz @ 3.6v pwr_cl_26_360 1 r 0x02**** 0x00 [202] power class for 52mhz @ 3.6v pwr_cl_52_360 1 r 0x02**** 0x00 [201] power class for 26mhz @ 1.95v pwr_cl_26_195 1 r 0x06**** 0x00 [200] power class for 52mhz @ 1.95v pwr_cl_52_195 1 r 0x06**** 0x00 [199:197] reserved - 3 - all ?0? [196] card type card_type 1 r 0x03 [195] reserved - 1 - all ?0? [194] csd structure version csd_structure 1 r 0x02 [193] reserved - 1 - all ?0? [192] extended csd revision ext_csd_rev 1 r 0x03 [191] command set cmd_set 1 r/w can be set [190] reserved - 1 - all ?0? [189] command set revision cmd_set_rev 1 ro 0x00 [188] reserved - 1 - all ?0? [187] power class power_class 1 r/w can be set
thgbm1gxdxebaix 2008-12-08 12 [186] reserved - 1 - all ?0? [185] high speed interface timing hs_timing 1 r/w can be set [184] reserved 1 - all ?0? [183] bus width mode bus_width 1 wo can be set [182] reserved - 1 - all ?0? [181] erased memory content erased_mem_cont 1 ro 0x01 [180] reserved - 1 - all ?0? [179] boot configuration boot_config 1 r/w can be set [178] reserved - 1 - all ?0? [177] boot bus width boot_bus_width 1 r/w can be set [176] reserved - 1 - all ?0? [175] high-density erase group definition erase_group_def 1 r/w can be set [174:0] reserved - 175 - all ?0? (note) *acc_size thgbm1g7d4ebai2(16-gbytes) and THGBM1G8D8EBAI2(32-gbytes) case, the values are 0x07 **hc_erase_grp_size thgbm1g7d4ebai2(16-gbytes) and THGBM1G8D8EBAI2(32-gbytes) case, the values are 0x08 ***rel_wr_sec_c reliable write address for 8kbyte data size, should be aligned on the boundary of 8kbytes. ****pwr cl thgbm1g7d4ebai2(16-gbytes) and THGBM1G8D8EBAI2(32-gbytes) case, the values are 0x02
thgbm1gxdxebaix 2008-12-08 13 electrical characteristics dc characteristics general parameter symbol test conditions min max unit peak voltage on all lines -0.5 vccq+0.5 v all inputs input leakage current (before initialization sequence 1 and/or the internal pull up resistors connected) ?100 100 a input leakage current (after initialization sequence and the internal pull up resistors disconnected) ?10 10 a all outputs output leakage current (before initialization sequence) -100 100 a output leakage current (after initialization sequence) -10 10 a 1) initialization sequence is defined in section 12.3 of jedec/mmca standard 4.3 power supply voltage parameter symbol test conditions min max unit supply voltage 1 v cc 2.7 3.6 v 1.7 1.95 v supply voltage 2 vccq 2.7 3.6 v supply current parameter symbol test conditions min max unit read i rop ? 100 ma operation (rms) write i wop ? 100 ma internal resistance and device capacitance parameter symbol test conditions min max unit single device capacitance c card ? 12 pf internal pull up resistance dat1 ? dat7 r int 50 150 kohm
thgbm1gxdxebaix 2008-12-08 14 bus signal levels open-drain mode bus signal level parameter symbol test conditions min max unit output high voltage v oh vccq - 0.2 ? v output low voltage v ol ? 0.3 v push-pull mode bus signal level (high-voltage) parameter symbol test conditions min max unit output high voltage v oh i oh = -100 a @ v dd min 0.75 * vccq ? v output low voltage v ol i ol = 100 a @ v dd min ? 0.125 * vccq v input high voltage v ih 0.625* vccq vccq + 0.3 v input low voltage v il v ss - 0.3 0.25 * vccq v push-pull mode bus signal level (low-voltage) parameter symbol test conditions min max unit output high voltage v oh i oh = -100 a @ v dd min vccq - 0.2 ? v output low voltage v ol i ol = 100 a @ v dd min ? 0.2 v input high voltage v ih 0.7 * vccq vccq + 0.3 v input low voltage v il v ss - 0.3 0.3 * vccq v
thgbm1gxdxebaix 2008-12-08 15 bus signal levels card interface timings (high-speed interface timing) parameter symbol test conditions min max unit clock frequency data transfer mode (pp) 2 f pp c l <= 30pf tolerance: +100khz 0 52 mhz clock frequency identification mode (od) f od tolerance: +20khz 0 400 khz clock low time t wl c l <= 30pf 6.5 ? ns clock rise time t tlh c l <= 30pf ? 3 ns clock fall time t thl c l <= 30pf ? 3 ns inputs cmd,dat (referenced to clk) input set-up time t isu c l <= 30pf 3 ? ns input hold time t ih c l <= 30pf 3 ? ns outputs cmd,dat (referenced to clk) output delay time during data transfer t odly c l <= 30pf 0 13.7 ns output hold time t oh c l <= 30pf 2.5 ? ns signal rise time 4 t rise c l <= 30pf ? 3 ns signal fall time t fall c l <= 30pf ? 3 ns 1) clk timing is measured at 50% of vccq 2) thgbm1gxdxebaix shall support the full fr equency range from 0-26mhz, or 0-52mhz 3) e-mmc can operate as high-speed in terface timing at 26mhz clock frequency. 4) clk rise and fall times are measured by min(vih) and max(vil). 5) inputs cmd,dat rise and fall times area measured by min(vih) and max(vil), and outputs cmd, dat rise and fall tim es are measured by min(voh) and max(vol). t odly
thgbm1gxdxebaix 2008-12-08 16 card interface timings (backward-compatible interface timing) parameter symbol test conditions min max unit clock frequency data transfer mode (pp) 2 f pp c l <= 30pf 0 26 mhz clock frequency identification mode (od) f od tolerance: +20khz 0 400 khz clock low time t wl c l <= 30pf 10 ? ns clock rise time t tlh c l <= 30pf ? 10 ns clock fall time t thl c l <= 30pf ? 10 ns inputs cmd,dat (referenced to clk) input set-up time t isu c l <= 30pf 3 ? ns input hold time t ih c l <= 30pf 3 ? ns outputs cmd,dat (referenced to clk) output set-up time t osu c l <= 30pf 11.7 ? ns output hold time t oh c l <= 30pf 8.3 ? ns 1) the e-mmc must always start with the backward-comp atible interface timing. the timing mode can be switched to high-speed interface timing by the host sending the switch command (cmd6) with the argument for high-speed interface select. 2) clk timing is measured at 50% of vccq 3) for compatibility with e-mmcs that support the v4.2 standard or earlier, host should not use >20mhz before switching to high-speed interface timing. 4) clk rise and fall times are measured by min(vih) and max(vil).
thgbm1gxdxebaix 2008-12-08 17 functional restrictions tbd if necessary. reliability guidance this reliability guidance is intended to notify some gu idance related to using raw mlc nand flash. for detailed reliability data, please refer to toshiba?s reliability note. although random bit errors may occur during use, it does not necessarily mean that a block is bad. generally, a block should be marked as bad when a program status failure or erase status failure is detected. the other failure modes may be recovere d by a block erase. ecc treatment for read data is mandatory due to the following data retention and read disturb failures. -write/erase endurance write/erase endurance failures may occur in a cell, page, or block, and are detected by doing a status read after either an auto program or auto block erase operation. the cumulative bad block count will increase along with the number of write/erase cycles. -data retention the data in memory may change after a certain amount of storage time. this is due to charge loss or charge gain. after block erasure and reprogramming, the block may become usable again. here is the combined characteristics image of write/erase endurance and data retention. -read disturb a read operation may disturb the data in memory. the data may change due to charge gain. usually, bit errors occur on other pages in the block, not the page being read. afte r a large number of read cycles (between block erases), a tiny charge may build up and can cause a cell to be soft programmed to another state. after block erasure and reprogramming, the block may become usable again. write/erase endurance [cycles] data retention [years]
thgbm1gxdxebaix 2008-12-08 18 document revision history rev1.0 may 9 th , 2008 released as an initial version rev1.1 oct 24 th , 2008 32gbyte user area density is defined. access size (acc_size), high-capacity area unit size (hc_erase_grp_size) and power class (pwr_cl) values are updated. rev1.2 oct 31 th , 2008 product weight of 4gbyte/8gbyte/16gbyte(8 x 16gbit mlc)/32gbyte are added. rev1.3 nov 6 th , 2008 a comment regarding reliable write is added rev1.4 dec 8 th , 2008 in extended csd register [208 : 207], 4bit at 52mhz expressions were added.
thgbm1gxdxebaix 2008-12-08 19 restrictions on product use 070122eba_r6 ? the information contained herein is subject to change without notice. 021023_d ? toshiba is continually working to improve the quality a nd reliability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their i nherent electrical sensitivity and vulnerability to physical stress. it is the responsibility of t he buyer, when utilizing toshiba products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfun ction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that toshiba products are used within s pecified operating ranges as set forth in the most recent toshiba products specific ations. also, please keep in mind the precautions and conditions set forth in the ?handling guide for semico nductor devices,? or ?toshiba semiconductor reliability handbook? etc. 021023_a ? the toshiba products listed in this document are in tended for usage in general electronics applications (computer, personal equipment, office equipment, measuri ng equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunc tion or failure of which may cause loss of human life or bodily injury (?unintended usage?). unintended usage incl ude atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffi c signal instruments, comb ustion control instruments, medical instruments, all types of safety devices, et c. unintended usage of toshiba products listed in this document shall be made at the customer?s own risk. 021023_b ? the products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_q ? the information contained herein is presented only as a gu ide for the applications of our products. no responsibility is assumed by toshiba for any infringements of patents or other rights of the third parties which may result from its use. no license is granted by imp lication or otherwise under any patents or other rights of toshiba or the third parties. 070122_c ? please use this product in compliance with all applicable la ws and regulations that regulate the inclusion or use of controlled substances. toshiba assumes no liability for damage or losses occurring as a result of noncompliance with applicable laws and regulations. 060819_af ? the products described in this document are subject to foreign exchange and foreign trade control laws. 060925_e

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