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hitachi 4-bit single-chip microcomputers hmcs43xx family hd404344r series, hd404394 series, hd404318 series, hd404358 series, hd404358r series, hd404339 series, hd404369 series hardware manual ade-602-081b rev.3.0 8/4/00 hitachi, ltd.
cautions 1. hitachi neither warrants nor grants licenses of any rights of hitachi? or any third party? patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third party? rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachi? sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachi? sales office for any questions regarding this document or hitachi semiconductor products.
list of items revised or added for this version page item description timer function overview prescaler w column amended 405 18.2.1 timer mode register b1 (tmb1:$009) note amended 418 18.4 interrupts series name amended 560 table 25-21 absolute maximum ratings (hd404358 and hd404358r series) pin voltage hd404358 series rated value amended 566 table 25-25 ac characteristics (hd404358 and hd404358r series) oscillator stabilization period (crystal oscillator) notes added 633 b.2 i/o registers (2) $030?ata control register r0 dcr0 series name amended 636 b.2 i/o registers (2) $038?ata control register r8 dcr8 series name amended

preface introduction the hmcs43xx family of 4-bit microcomputers are built around the hmcs400 cpu core, which has a powerful architecture designed for efficient programming. all of these microcomputers include standard on-chip peripheral functions, including a multiple input channel a/d converter, a serial interface, and multi-function timers. the peripheral functions are developed individually as modules, and connected using a standard interface. this manual describes six product series in the hmcs43xx family: the hd404344r, hd404394, hd404318, hd404358, hd404358r, hd404339, and hd404369 series. the products in these series form a fine-grained product line in which products are differentiated by their memory capacities, medium and high voltage pins, high current pins, low power modes, normal vs. high-speed versions, and other aspects. this allows an appropriate microcomputer to be selected for a wide range of applications. all members of the hmcs43xx family are available in both rom and prom (ztat) versions. prom versions can be programmed freely by the user with a general purpose prom writer. note: ztat is a registered trademark of hitachi, ltd.
manual layout the microcomputers in the hmcs43xx family differ in their memory capacities and peripheral functions. this table provides an overview of the differences between these products as they relate to the structure of this manual. use this table to determine which sections are relevant to the product(s) of interest. organization hd404344r series hd404394 series hd404318 series hd404358/ hd404358r series hd404339 series hd404369 series section 1: overview provides a brief overview of the features of the hmcs43xx family. section 2: memory section 3: cpu section 4: exception handling these sections describe the hmcs400 cpu and its internal states. section 5: low power modes ?? section 6: low power modes ? ??? section 7: i/o ports section 8: i/o ports section 9: i/o ports section 10: i/o ports section 11: i/o ports these sections describe the peripheral functions used in the hmcs43xx family. note that the peripheral functions actually present differ between product series. ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? section 12: i/o ports ? ? ? ? ? section 13: oscillator circuits ?? section 14: oscillator circuits ? ??? section 15: a/d converter section 16: prescaler section 17: timer a ? ? section 18: timer b section 19: timer c section 20: serial interface section 21: alarm output ? ? section 22: rom section 23: ram
organization hd404344r series hd404394 series hd404318 series hd404358/ hd404358r series hd404339 series hd404369 series section 24: application examples describes the use of the a/d converter and timer b. refer to this section when developing software for any of these products. section 25: electrical characteristics appendices note on how to use this manual either or is printed at the top of each page in this manual to indicate that the page refers to one or more specific series or to all products, respectively. since the peripheral functions actually present differ between products, care is required when reading this manual. differences between products are specified in notes and by shading. this manual describes seven product series, the hd404344r, hd404394, hd404318, hd404358, hd404358r, hd404339, and hd404369 series. to use this manual as the manual for a particular product be sure to read both the chapters that pertain to all products as well as the chapters that are related to the product being used.
function overview item hd404344r series hd404394 series hd404318 series hd404358 series hd404358r series hd404339 series hd404369 series rom capacity (words) mask rom 1/2/4 k ztata 4 k mask rom 1/2/4 k ztata 4 k mask rom 4/6/8 k ztata 8 k mask rom 4/6/8 k ztata 16 k mask rom 4/6/8 k ztata 16 k mask rom 4/6/8/12/16 k ztata 16 k mask rom 4/8/12/16 k ztata 16 k ram capacity (digits) 256 256 384 384 (mask rom)/ 512 (ztata) 512 512 512 i/o pins 22 21 34 34 34 54 54 medium voltage pins ?3 ?4 ??8 high voltage pins ??22 (of which one is input-only) ?? 31 (of which one is input-only) ? 10?? ?20?? interrupts priority high int int int int int int int int int int int int * under development
item hd404344r series hd404394 series hd404318 series hd404358 series hd404358r series hd404339 series hd404369 series alarm output ? ? on-chip on-chip on-chip on-chip on-chip system clock oscillator oscillator ceramic, external, cr ceramic, external crystal, ceramic, external crystal, ceramic, external crystal, ceramic, cr, external crystal, ceramic, external crystal, ceramic, external frequency 0.4 to 4.5 mhz 1.0 to 3.5 mhz (cr versions) 0.4 to 4.5 mhz 0.4 to 4.5 mhz 0.4 to 5.0 mhz (5 mhz versions) 0.4 to 8.5 mhz (8.5 mhz versions) 0.4 to 5.0 mhz (5 mhz versions) 0.4 to 8.5 mhz (8.5 mhz versions) 1.0 to 3.5 mhz (cr versions) 0.4 to 4.5 mhz 0.4 to 5.0 mhz (5 mhz versions) 0.4 to 8.5 mhz (8.5 mhz versions) divisor 4 4 4 4 4 4/8/16/32 (software selectable) 4/8/16/32 (software selectable) sub- system clock oscillator frequency divisor ? ? ? ? ? ? ? ? ? ? 32 khz 4/8 (software selectable) 32 khz 4/8 (software selectable) stopping in stop mode ? ? ? ? ? yes yes low power modes watch mode subactive mode ? ? ? ? ? ? ? ? ? ? yes yes yes yes standby mode yes yes yes yes yes yes yes stop mode yes yes yes yes yes yes yes direct return to active mode from subactive mode ? ? ? ? ? yes yes
timer function overview hd404344r/ hd404394 series hd404318/ hd404358/ hd404358r series hd404339/ hd404369 series item bcabcabc timer prescaler s prescaler w external event input (falling edge, rising edge, or double edge) free-running timer time base event counter reload watchdog pwm input capture
i contents section 1 overview .............................................................................................................. 1 1.1 overview ................................................................................................................... ......... 1 1.2 internal block diagrams .................................................................................................... 10 1.3 pin functions.............................................................................................................. ........ 17 1.3.1 hd404344r and hd404394 series pin functions ............................................... 17 1.3.2 hd404318/hd404358/hd404358r series pin functions................................... 23 1.3.3 hd404339/hd404369 series pin functions ........................................................ 31 section 2 memory ................................................................................................................. 39 2.1 overview ................................................................................................................... ......... 39 2.2 rom ........................................................................................................................ ........... 40 2.2.1 vector address area ............................................................................................. 40 2.2.2 zero page subroutine area ................................................................................... 40 2.2.3 pattern area........................................................................................................... 40 2.2.4 program area ........................................................................................................ 41 2.3 ram ........................................................................................................................ ........... 43 2.3.1 ram mapped register area ................................................................................ 48 2.3.2 memory register area.......................................................................................... 57 2.3.3 data area .............................................................................................................. 58 2.3.4 stack area ............................................................................................................. 59 section 3 cpu ........................................................................................................................ 61 3.1 overview .................................................................................................................. .......... 61 3.1.1 features ................................................................................................................. 61 3.1.2 address space ....................................................................................................... 62 3.1.3 register organization............................................................................................ 63 3.2 cpu registers .............................................................................................................. ...... 64 3.2.1 accumulator (a) and b register (b) .................................................................... 64 3.2.2 w register (w), x register (x), and y register (y) ........................................... 64 3.2.3 spx register (spx), spy register (spy)............................................................ 64 3.2.4 carry flag (ca) .................................................................................................... 64 3.2.5 status flag (st) .................................................................................................... 64 3.2.6 program counter (pc) .......................................................................................... 64 3.2.7 stack pointer (sp) ................................................................................................. 65 3.3 addressing modes........................................................................................................... ... 65 3.3.1 ram addressing modes ...................................................................................... 65 3.3.2 rom addressing modes and the p instruction .................................................... 67 3.4 processing states .......................................................................................................... ...... 70 3.4.1 overview ............................................................................................................... 70
ii 3.4.2 program execution state ....................................................................................... 71 3.4.3 exception handling state...................................................................................... 72 3.4.4 program stopped state.......................................................................................... 72 section 4 exception handling ........................................................................................... 73 4.1 overview ................................................................................................................... ......... 73 4.2 reset ...................................................................................................................... ............. 74 4.2.1 overview ............................................................................................................... 74 4.2.2 reset sequence...................................................................................................... 74 4.3 stop mode clear............................................................................................................ ..... 75 4.3.1 overview ............................................................................................................... 75 4.3.2 stop mode clear sequence ( reset pin input) ................................................... 75 4.3.3 stop mode clear sequence ( stopc pin input) ................................................... 75 4.4 initial values of registers and flags on reset and stop mode clear................................ 76 4.5 interrupts ................................................................................................................. ........... 79 4.5.1 overview ............................................................................................................... 79 4.5.2 interrupt registers and flags ................................................................................ 80 4.5.3 external interrupts................................................................................................. 88 4.5.4 internal interrupts.................................................................................................. 88 4.5.5 interrupt handling sequence ................................................................................ 89 section 5 low power modes (hd404344r/hd404394/hd404318 /hd404358 /hd404358r series) .............................................................. 95 5.1 overview ................................................................................................................... ......... 95 5.1.1 features ................................................................................................................. 95 5.1.2 state transition diagram ...................................................................................... 97 5.1.3 pin functions......................................................................................................... 97 5.1.4 registers and flags................................................................................................ 98 5.2 register and flag descriptions .......................................................................................... 99 5.2.1 port mode register b (pmrb: $024) ................................................................... 99 5.2.2 ram enable flag (rame: $021, 3) .................................................................... 101 5.3 standby mode ............................................................................................................... ..... 102 5.3.1 entering standby mode ........................................................................................ 102 5.3.2 clearing standby mode ........................................................................................ 102 5.4 stop mode .................................................................................................................. ........ 104 5.4.1 entering stop mode .............................................................................................. 104 5.4.2 clearing stop mode .............................................................................................. 104 5.4.3 post-stop mode oscillator stabilization period.................................................... 105 5.5 low power mode operating sequence.............................................................................. 105 section 6 low power modes (hd404339 and hd404369 series) ....................... 107 6.1 overview ................................................................................................................... ......... 107 6.1.1 features ................................................................................................................. 107
iii 6.1.2 state transition diagram ...................................................................................... 109 6.1.3 pin functions......................................................................................................... 110 6.1.4 registers and flags................................................................................................ 110 6.2 register and flag descriptions .......................................................................................... 111 6.2.1 miscellaneous register (mis: $00c).................................................................... 111 6.2.2 system clock selection register 1 (ssr1: $027) ................................................ 112 6.2.3 timer mode register a (tma: $008).................................................................. 114 6.2.4 port mode register b (pmrb: $024) ................................................................... 116 6.2.5 low speed on flag (lson: $020, 0) .................................................................. 117 6.2.6 dton flag (dton: $020, 3)............................................................................... 119 6.2.7 ram enable flag (rame: $021, 3) .................................................................... 119 6.3 standby mode ............................................................................................................... ..... 120 6.3.1 entering standby mode ........................................................................................ 120 6.3.2 clearing standby mode ........................................................................................ 120 6.4 stop mode .................................................................................................................. ........ 122 6.4.1 entering stop mode .............................................................................................. 122 6.4.2 clearing stop mode .............................................................................................. 122 6.4.3 post-stop mode oscillator stabilization period.................................................... 123 6.5 watch mode ................................................................................................................. ...... 124 6.5.1 entering watch mode ........................................................................................... 124 6.5.2 clearing watch mode............................................................................................ 124 6.5.3 post-watch mode operating timing .................................................................... 125 6.6 subactive mode............................................................................................................. ..... 126 6.6.1 entering subactive mode...................................................................................... 126 6.6.2 clearing subactive mode...................................................................................... 126 6.6.3 system timing when switching directly from subactive mode to active mode 127 6.7 interrupt frame............................................................................................................ ....... 128 6.8 low power mode operating sequence.............................................................................. 128 6.9 usage notes................................................................................................................ ........ 130 section 7 i/o ports (hd404344r series) ...................................................................... 131 7.1 overview ................................................................................................................... ......... 131 7.1.1 features ................................................................................................................. 131 7.1.2 i/o control ............................................................................................................ 13 3 7.1.3 i/o pin circuit structures...................................................................................... 136 7.1.4 port states in low power modes.......................................................................... 139 7.1.5 handling unused pins ........................................................................................... 139 7.2 d port..................................................................................................................... ............. 140 7.2.1 overview ............................................................................................................... 14 0 7.2.2 register configuration and descriptions .............................................................. 141 7.2.3 pin functions......................................................................................................... 143 7.3 r ports .................................................................................................................... ............ 144 7.3.1 overview ............................................................................................................... 14 4
iv 7.3.2 register configuration and descriptions .............................................................. 145 7.3.3 pin functions......................................................................................................... 151 7.4 usage notes................................................................................................................ ........ 154 section 8 i/o ports (hd404394 series) ......................................................................... 157 8.1 overview ................................................................................................................... ......... 157 8.1.1 features ................................................................................................................. 157 8.1.2 i/o control ............................................................................................................ 15 9 8.1.3 i/o pin circuit structures...................................................................................... 162 8.1.4 port states in low power modes .......................................................................... 166 8.1.5 handling unused pins........................................................................................... 166 8.2 d port..................................................................................................................... ............. 167 8.2.1 overview ............................................................................................................... 16 7 8.2.2 register configuration and descriptions .............................................................. 168 8.2.3 pin functions......................................................................................................... 170 8.3 r ports .................................................................................................................... ............ 171 8.3.1 overview ............................................................................................................... 17 1 8.3.2 register configuration and descriptions .............................................................. 172 8.3.3 pin functions......................................................................................................... 178 8.4 usage notes................................................................................................................ ........ 181 section 9 i/o ports (hd404318 series) ......................................................................... 185 9.1 overview ................................................................................................................... ......... 185 9.1.1 features ................................................................................................................. 185 9.1.2 i/o control ............................................................................................................ 18 8 9.1.3 i/o pin circuit structures...................................................................................... 190 9.1.4 port states in low power modes .......................................................................... 195 9.1.5 handling unused pins ........................................................................................... 195 9.2 d port..................................................................................................................... ............. 196 9.2.1 overview ............................................................................................................... 19 6 9.2.2 register configuration and descriptions .............................................................. 197 9.2.3 pin functions......................................................................................................... 201 9.3 r ports .................................................................................................................... ............ 202 9.3.1 overview ............................................................................................................... 20 2 9.3.2 register configuration and descriptions .............................................................. 204 9.3.3 pin functions......................................................................................................... 211 9.4 usage notes................................................................................................................ ........ 214 section 10 i/o ports (hd404358 and hd404358r series) ..................................... 217 10.1 overview .................................................................................................................. .......... 217 10.1.1 features ................................................................................................................ . 217 10.1.2 i/o control ............................................................................................................ 2 21 10.1.3 i/o pin circuit structures...................................................................................... 223
v 10.1.4 port states in low power modes .......................................................................... 230 10.1.5 handling unused pins ........................................................................................... 230 10.2 d port.................................................................................................................... .............. 231 10.2.1 overview ............................................................................................................... 2 31 10.2.2 register configuration and descriptions .............................................................. 232 10.2.3 pin functions......................................................................................................... 23 7 10.3 r ports ................................................................................................................... ............. 239 10.3.1 overview ............................................................................................................... 2 39 10.3.2 register configuration and descriptions .............................................................. 241 10.3.3 pin functions......................................................................................................... 25 0 10.4 usage notes............................................................................................................... ......... 255 section 11 i/o ports (hd404339 series) ....................................................................... 259 11.1 overview .................................................................................................................. .......... 259 11.1.1 features ................................................................................................................ . 259 11.1.2 i/o control ............................................................................................................ 2 61 11.1.3 i/o pin circuit structures...................................................................................... 264 11.1.4 port states in low power modes .......................................................................... 269 11.1.5 handling unused pins ........................................................................................... 269 11.2 d port.................................................................................................................... .............. 270 11.2.1 overview ............................................................................................................... 2 70 11.2.2 register configuration and descriptions.............................................................. 271 11.2.3 pin functions......................................................................................................... 27 5 11.3 r ports ................................................................................................................... ............. 276 11.3.1 overview ............................................................................................................... 2 76 11.3.2 register configuration and descriptions .............................................................. 278 11.3.3 pin functions......................................................................................................... 28 7 11.4 usage notes............................................................................................................... ......... 291 section 12 i/o ports (hd404369 series) ....................................................................... 295 12.1 overview .................................................................................................................. .......... 295 12.1.1 features ................................................................................................................ . 295 12.1.2 i/o control ............................................................................................................ 2 98 12.1.3 i/o pin circuit structures...................................................................................... 300 12.1.4 port states in low power modes .......................................................................... 304 12.1.5 handling unused pins ........................................................................................... 304 12.2 d port.................................................................................................................... .............. 305 12.2.1 overview ............................................................................................................... 3 05 12.2.2 register configuration and descriptions .............................................................. 306 12.2.3 pin functions......................................................................................................... 31 1 12.3 r ports ................................................................................................................... ............. 313 12.3.1 overview ............................................................................................................... 3 13 12.3.2 register configuration and descriptions .............................................................. 315
vi 12.3.3 pin functions......................................................................................................... 32 3 12.4 usage notes............................................................................................................... ......... 330 section 13 oscillator circuits (hd404344r/hd404394/hd404318 /hd404358/ hd404358r series) .............................................................. 335 13.1 overview .................................................................................................................. .......... 335 13.1.1 features ................................................................................................................ . 335 13.1.2 block diagram ...................................................................................................... 336 13.1.3 oscillator circuit pins ........................................................................................... 337 13.2 oscillator connection and external clock input................................................................ 338 13.3 usage notes............................................................................................................... ......... 340 section 14 oscillator circuits (hd404339 and hd404369 series) ...................... 343 14.1 overview .................................................................................................................. .......... 343 14.1.1 features ................................................................................................................ . 343 14.1.2 block diagram ...................................................................................................... 344 14.1.3 oscillator circuit pins ........................................................................................... 346 14.1.4 register and flag configuration ........................................................................... 346 14.2 register and flag descriptions .......................................................................................... 34 7 14.2.1 system clock selection register 1 (ssr1: $027) ................................................ 347 14.2.2 system clock selection register 2 (ssr2: $028) ................................................ 349 14.2.3 low speed on flag (lson: $020, 0) .................................................................. 350 14.3 oscillator connection and external clock input................................................................ 351 14.4 usage notes............................................................................................................... ......... 353 section 15 a/d converter .................................................................................................. 355 15.1 overview .................................................................................................................. .......... 355 15.1.1 features ................................................................................................................ . 355 15.1.2 block diagram ...................................................................................................... 356 15.1.3 pin configuration .................................................................................................. 359 15.1.4 register and flag configuration ........................................................................... 362 15.2 register and flag descriptions .......................................................................................... 36 3 15.2.1 a/d mode register 1 (amr1: $019) ................................................................... 363 15.2.2 a/d mode register 2 (amr2: $01a) .................................................................. 365 15.2.3 a/d data register l, u (adrl: $017, adru: $018)......................................... 367 15.2.4 a/d channel register (acr: $016) ..................................................................... 368 15.2.5 a/d start flag (adsf: $020, 2) ........................................................................... 371 15.2.6 iad off flag (iaof: $021, 2).............................................................................. 371 15.3 a/d converter operation ................................................................................................... 372 15.3.1 a/d conversion operation.................................................................................... 372 15.3.2 low power mode operation ................................................................................. 373 15.3.3 a/d converter precision ....................................................................................... 374 15.3.4 notes on the analog reference power supply ..................................................... 375
vii 15.4 interrupts ................................................................................................................ ............ 375 15.5 usage notes............................................................................................................... ......... 376 15.6 notes on mounting built-in a/d converter microcomputers (hd404318 and hd404339 series only) .......................................................................... 378 section 16 prescalers ........................................................................................................... 383 16.1 overview .................................................................................................................. .......... 383 16.2 prescaler s (pss)......................................................................................................... ....... 387 16.3 prescaler w (psw) (hd404339 and hd404369 series only).......................................... 387 section 17 timer a (hd404318/hd404358/hd404358r /hd404339 /hd404369 series) .................................................................. 389 17.1 overview .................................................................................................................. .......... 389 17.1.1 features ................................................................................................................ . 389 17.1.2 block diagram ...................................................................................................... 390 17.1.3 register configuration .......................................................................................... 392 17.2 register descriptions..................................................................................................... ..... 393 17.2.1 timer mode register a (tma: $008).................................................................. 393 17.2.2 timer counter a (tca)........................................................................................ 398 17.3 timer a operation ......................................................................................................... .... 399 17.3.1 free-running timer operation ............................................................................. 399 17.3.2 clock time base operation .................................................................................. 400 17.4 interrupts ................................................................................................................ ............ 400 17.5 usage notes............................................................................................................... ......... 400 section 18 timer b ............................................................................................................... 401 18.1 overview .................................................................................................................. .......... 401 18.1.1 features ................................................................................................................ . 401 18.1.2 block diagram ...................................................................................................... 402 18.1.3 timer b pins.......................................................................................................... 40 4 18.1.4 register configuration .......................................................................................... 404 18.2 register descriptions..................................................................................................... ..... 405 18.2.1 timer mode register b1 (tmb1: $009) .............................................................. 405 18.2.2 timer mode register b2 (tmb2: $026) .............................................................. 409 18.2.3 timer counter b (tcb) ........................................................................................ 410 18.2.4 timer write register twbl/u (twbl: $00a, twbu: $00b).......................... 411 18.2.5 timer read register trbl/u (trbl: $00a, trbu: $00b).............................. 412 18.2.6 port mode register b (pmrb: $024) ................................................................... 413 18.2.7 input capture status flag (icsf: $021, 0)............................................................ 415 18.2.8 input capture error flag (icef: $021, 1)............................................................. 415 18.3 timer b operation......................................................................................................... ..... 416 18.3.1 free-running timer.............................................................................................. 416 18.3.2 reload timer operation........................................................................................ 417
viii 18.3.3 external event counter operation ........................................................................ 417 18.3.4 input capture timer operation ............................................................................. 417 18.4 interrupts ................................................................................................................ ............ 418 18.5 usage notes............................................................................................................... ......... 418 section 19 timer c ............................................................................................................... 419 19.1 overview .................................................................................................................. .......... 419 19.1.1 features ................................................................................................................ . 419 19.1.2 block diagram ...................................................................................................... 420 19.1.3 timer c pins.......................................................................................................... 42 1 19.1.4 register configuration .......................................................................................... 421 19.2 register descriptions..................................................................................................... ..... 422 19.2.1 timer mode register c (tmc: $00d) ................................................................. 422 19.2.2 port mode register a (pmra: $004) .................................................................. 426 19.2.3 timer counter c (tcc) ........................................................................................ 427 19.2.4 timer write register twcl/u (twcl: $00e, twcu: $00f)........................... 428 19.2.5 timer read register trcl/u (trcl: $00e, trcu: $00f) ............................... 429 19.2.6 watchdog on flag (wdon: $020, 1) .................................................................. 430 19.3 timer c operation......................................................................................................... ..... 431 19.3.1 free-running timer operation ............................................................................. 431 19.3.2 reload timer operation........................................................................................ 431 19.3.3 pwm output operation ........................................................................................ 432 19.3.4 watchdog timer operation .................................................................................. 432 19.4 interrupts ................................................................................................................ ............ 433 19.5 usage notes............................................................................................................... ......... 433 section 20 serial interface ................................................................................................. 435 20.1 overview .................................................................................................................. .......... 435 20.1.1 features ................................................................................................................ . 435 20.1.2 block diagram ...................................................................................................... 436 20.1.3 serial interface pins .............................................................................................. 437 20.1.4 register configuration .......................................................................................... 437 20.2 register descriptions..................................................................................................... ..... 438 20.2.1 serial mode register (smr: $005) ...................................................................... 438 20.2.2 serial data register srl/u (srl: $006, sru: $007) ......................................... 440 20.2.3 octal counter (oc) ............................................................................................... 441 20.2.4 port mode register a (pmra: $004) .................................................................. 442 20.2.5 port mode register c (pmrc: $025) ................................................................... 443 20.2.6 miscellaneous register (mis: $00c).................................................................... 445 20.3 operation ................................................................................................................. ........... 447 20.3.1 operating modes ................................................................................................... 447 20.3.2 serial data format ................................................................................................ 447 20.3.3 transfer clock....................................................................................................... 448
ix 20.3.4 operating states .................................................................................................... 448 20.3.5 transmission and reception operations............................................................... 451 20.3.6 high- or low-level output selection during idle................................................ 468 20.3.7 transfer clock error detection (external clock mode)....................................... 469 20.4 interrupts ................................................................................................................ ............ 471 20.5 usage notes............................................................................................................... ......... 471 section 21 alarm output (hd404318/hd404358/hd404358r /hd404339 /hd404369 series) .................................................................. 473 21.1 overview .................................................................................................................. .......... 473 21.1.1 features ................................................................................................................ . 473 21.1.2 block diagram ...................................................................................................... 474 21.1.3 pin functions......................................................................................................... 47 5 21.1.4 register configuration .......................................................................................... 475 21.2 register descriptions..................................................................................................... ..... 476 21.2.1 port mode register a (pmra: $004) .................................................................. 476 21.2.2 port mode register c (pmrc: $025) ................................................................... 477 21.3 operation ................................................................................................................. ........... 478 section 22 rom .................................................................................................................... 479 22.1 overview .................................................................................................................. .......... 479 22.2 prom mode ................................................................................................................. ..... 483 22.2.1 prom mode ......................................................................................................... 483 22.2.2 socket adapter pin correspondence and memory map ....................................... 484 22.3 programming ............................................................................................................... ....... 493 22.3.1 write/verify .......................................................................................................... 49 3 22.3.2 prom programming notes .................................................................................. 498 22.3.3 post-programming reliability............................................................................... 499 22.4 notes on ordering rom .................................................................................................... 5 00 section 23 ram .................................................................................................................... 503 23.1 overview ................................................................................................................. ........... 503 23.1.1 features ................................................................................................................ . 503 23.1.2 ram memory map .............................................................................................. 505 23.2 ram enable flag (rame: $021, 3) ................................................................................. 506 23.3 usage notes............................................................................................................... ......... 506 section 24 application examples .................................................................................... 507 24.1 using the a/d converter................................................................................................... . 507 24.2 using timer b ............................................................................................................. ....... 517 section 25 electrical characteristics ............................................................................... 525 25.1 hd404344r series.......................................................................................................... ... 525
x 25.1.1 absolute maximum ratings.................................................................................. 525 25.1.2 electrical characteristics....................................................................................... 526 25.2 hd404394 series........................................................................................................... ..... 536 25.2.1 absolute maximum ratings.................................................................................. 536 25.2.2 electrical characteristics....................................................................................... 537 25.3 hd404318 series........................................................................................................... ..... 548 25.3.1 absolute maximum ratings.................................................................................. 548 25.3.2 electrical characteristics....................................................................................... 549 25.4 hd404358/hd404358r series.......................................................................................... 559 25.4.1 absolute maximum ratings.................................................................................. 559 25.4.2 electrical characteristics....................................................................................... 561 25.5 hd404339 series........................................................................................................... ..... 574 25.5.1 absolute maximum ratings.................................................................................. 574 25.5.2 electrical characteristics....................................................................................... 575 25.6 hd404369 series........................................................................................................... ..... 586 25.6.1 absolute maximum ratings.................................................................................. 586 25.6.2 electrical characteristics....................................................................................... 587 appendix a instruction set ................................................................................................ 601 a.1 instruction set overview................................................................................................... . 601 a.2 operation code map ......................................................................................................... . 609 appendix b registers and flags ...................................................................................... 611 b.1 i/o registers (1) .......................................................................................................... ....... 611 b.2 i/o registers (2) .......................................................................................................... ....... 613 appendix c option lists .................................................................................................... 637 c.1 hd404344r series option list.......................................................................................... 637 c.2 hd404394 series option list ............................................................................................ 638 c.3 hd404318 series option list ............................................................................................ 639 c.4 hd404358 series option list ............................................................................................ 641 c.5 hd404358r series option list.......................................................................................... 642 c.6 hd404339 series option list ............................................................................................ 644 c.7 hd404369 series option list ............................................................................................ 647 appendix d package dimensions .................................................................................... 648
1 section 1 overview 1.1 overview the products in the hmcs43xx family are 4-bit microcomputers that include an on-chip a/d converter with multiple input channels. the hmcs43xx family encompasses an extensive product line of microcomputers that include an on-chip a/d converter in packages with from 28 to 64 pins. figure 1-1 shows the structure of the hmcs43xx family. general-purpose 64 pins 42 pins 28 pins 64 pins 42 pins ztat tm hd407a4369 hd404364/8/12/9 hd407a4359 hd404354/6/8 hd4074394 hd404391/2/4 hd4074339 hd404334/6/8/12/9 hd4074318 hd404314/6/8 ztat tm ztat tm ztat tm ztat tm fluorescent display driver products (high voltage products) hd40a4364/8/12/9 hd40a4354/6/8 hd404369 series twelve a/d converter channels medium voltage pins provided hd404358 series eight a/d converter channels medium voltage pins provided hd407c4359r ztat tm hd407a4359r hd404354r/6r/8r hd4074344 hd404341r/2r/4r ztat tm hd40a4354r/6r/8r hd40c4354r/6r/8r hd40c4341r/2r/4r hd404358r series eight a/d converter channels nmos high current pins provided hd404344r series four a/d converter channels nmos high current pins provided hd404394 series three a/d converter channels medium voltage pins provided hd404339 series twelve a/d converter channels hd404318 series eight a/d converter channels figure 1-1 structure of the hmcs43xx family
2 table 1-1 lists hmcs43xx family product line, and table 1-2 lists the functions of those products. table 1-1 product lineup series rom type product model rom (words) ram (digits) package hd404344r series mask rom standard version hd404341r hd404341rs hd404341rfp 1,024 256 dp-28s fp-28da hd404341rft fp-30d hd404342r hd404342rs 2,048 256 dp-28s hd404342rfp fp-28da hd404342rft fp-30d hd404344r hd404344rs 4,096 256 dp-28s hd404344rfp fp-28da HD404344RFT fp-30d cr version hd40c4341r hd40c4341rs 1,024 256 dp-28s hd40c4341rfp fp-28da hd40c4341rft fp-30d hd40c4342r hd40c4342rs 2,048 256 dp-28s hd40c4342rfp fp-28da hd40c4342rft fp-30d hd40c4344r hd40c4344rs 4,096 256 dp-28s hd40c4344rfp fp-28da hd40c4344rft fp-30d ztat hd4074344 hd4074344s 4,096 256 dp-28s hd4074344fp fp-28da hd4074344ft fp-30d hd404394 series mask rom hd404391 hd404391s hd404391fp 1,024 256 dp-28s fp-28da hd404391ft fp-30d hd404392 hd404392s 2,048 256 dp-28s hd404392fp fp-28da hd404392ft fp-30d note: ztat is a registered trademark of hitachi, ltd.
3 table 1-1 product lineup (cont) series rom type product model rom (words) ram (digits) package hd404394 series mask rom hd404394 hd404394s hd404394fp 4,096 256 dp-28s fp-28da hd404394ft fp-30d ztat hd4074394 hd4074394s 4,096 256 dp-28s hd4074394fp fp-28da hd4074394ft fp-30d hd404318 series mask rom hd404314 hd404314s hd404314h 4,096 384 dp-42s fp-44a hd404316 hd404316s 6,144 384 dp-42s hd404316h fp-44a hd404318 hd404318s 8,192 384 dp-42s hd404318h fp-44a ztat hd4074318 hd4074318s 8,192 384 dp-42s hd4074318h fp-44a hd404358 series mask rom 5 mhz version hd404354 hd404354s hd404354h 4,096 384 dp-42s fp-44a hd404356 hd404356s 6,144 384 dp-42s hd404356h fp-44a hd404358 hd404358s 8,192 384 dp-42s hd404358h fp-44a 8.5 mhz version hd40a4354 hd40a4354s hd40a4354h 4,096 384 dp-42s fp-44a hd40a4356 hd40a4356s 6,144 384 dp-42s hd40a4356h fp-44a hd40a4358 hd40a4358s 8,192 384 dp-42s hd40a4358h fp-44a ztat hd407a4359 hd407a4359s 16,384 512 dp-42s hd407a4359h fp-44a note: ztat is a registered trademark of hitachi, ltd
4 series rom type product model rom (words) ram (digits) package hd404358r series mask rom 5 mhz version hd404354r hd404354rs hd404354rh 4,096 512 dp-42s fp-44a hd404356r hd404356rs 6,144 512 dp-42s hd404356rh fp-44a hd404358r hd404358rs 8,192 512 dp-42s hd404358rh fp-44a 8.5 mhz version hd40a4354r hd40a4354rs hd40a4354rh 4,096 512 dp-42s fp-44a hd40a4356r hd40a4356rs 6,144 512 dp-42s hd40a4356rh fp-44a hd40a4358r hd40a4358rs 8,192 512 dp-42s hd40a4358rh fp-44a cr version hd40c4354r hd40c4354rs 4,096 512 dp-42s hd40c4354rh fp-44a hd40c4356r hd40c4356rs 6,144 512 dp-42s hd40c4356rh fp-44a hd40c4358r hd40c4358rs 8,192 512 dp-42s hd40c4358rh fp-44a ztat 8.5 mhz version hd407a4359r hd407a4359rs hd407a4359rh 16,384 512 dp-42s fp-44a cr version hd407c4359r hd407c4359rs 16,384 512 dp-42s hd407c4359rh fp-44a note: ztat is a registered trademark of hitachi, ltd.
5 table 1-1 product lineup (cont) series rom type product model rom (words) ram (digits) package hd404339 series mask rom hd404334 hd404334s hd404334fs 4,096 512 dp-64s fp-64b hd404336 hd404336s 6,144 512 dp-64s hd404336fs fp-64b hd404338 hd404338s 8,192 512 dp-64s hd404338fs fp-64b hd4043312 hd4043312s 12,288 512 dp-64s hd4043312fs fp-64b hd404339 hd404339s 16,384 512 dp-64s hd404339fs fp-64b ztat hd4074339 hd4074339s 16,384 512 dp-64s hd4074339fs fp-64b hd404369 series mask rom 5 mhz version hd404364 hd404364s hd404364f 4,096 512 dp-64s fp-64b hd404368 hd404368s 8,192 512 dp-64s hd404368f fp-64b hd4043612 hd4043612s 12,288 512 dp-64s hd4043612f fp-64b hd404369 hd404369s 16,384 512 dp-64s hd404369f fp-64b 8.5 mhz version hd40a4364 hd40a4364s hd40a4364f 4,096 512 dp-64s fp-64b hd40a4368 hd40a4368s 8,192 512 dp-64s hd40a4368f fp-64b hd404369 series mask rom 8.5 mhz version hd40a43612 hd40a43612s hd40a43612f 12,288 512 dp-64s fp-64b hd40a4369 hd40a4369s 16,384 512 dp-64s hd40a4369f fp-64b ztat hd407a4369 hd407a4369s 16,384 512 dp-64s hd407a4369f fp-64b note: ztat is a registered trademark of hitachi, ltd.
6 table 1-2 hmcs43xx family functional overview hd404344r hd404394 hd404318 hd404358 hd404358r hd404339 hd404369 item series series series series series series series specifications cpu three ram addressing modes 1. register indirect addressing 2. direct addressing 3. memory register addressing four rom addressing modes and the p instruction 1. direct addressing 2. current addressing 3. zero page addressing 4. table data addressing 5. p instruction (rom data reference instruction) simple and efficient instruction set all instructions are executed in one or two cycles, except for the return instruction, which requires three cycles. rom 16 k hd407a4359 hd407a4359r hd404339 hd404369 (words: hd407c4359r hd4074339 hd40a4369 1 word = hd407a4369 10 bits) 12 k hd4043312 hd4043612 hd40a43612 8 k hd404318 hd404358 hd404358r hd404338 hd404368 hd4074318 hd40a4358 hd40a4358r hd40a4368 hd40c4358r 6 k hd404316 hd404356 hd404356r hd404336 hd40a4356 hd40a4356r hd40c4356r 4 k hd404344r hd404394 hd404314 hd404354 hd404354r hd404334 hd404364 hd40c4344r hd4074394 hd40a4354 hd40a4354r hd40a4364 hd4074344 hd40c4354r 2 k hd404342r hd404392 hd40c4342r 1 k hd404341r hd404391 hd40c4341r
7 table 1-2 hmcs43xx family functional overview (cont) hd404344r hd404394 hd404318 hd404358 hd404358r hd404339 hd404369 item series series series series series series series ram (digits: 256 256 384 384 (mask rom)/ 512 512 512 1 digit = 4 bits) 512 (ztat tm ) i/o ports total: 22 pins total: 21 pins total: 34 pins total: 34 pins total: 34 pins total: 54 pins total: 54 pins standard standard standard standard standard standard standard i/o pins: i/o pins: i/o pins: i/o pins: i/o pins: i/o pins: i/o pins: 22 pins 13 pins 12 pin 29 pins 33 pins 23 pins 45 pins (nmos high medium high voltage medium (nmos high high voltage medium current pins: voltage i/o pins: voltage current pins: i/o pins: voltage 10 pins) nmos 21 pins i/o pins: 20 pins) 30 pins i/o pins: open drain high voltage 4 pins standard high voltage 8 pins i/o pins: input pins: standard input pins: input pins: standard 3 pins 1 pin input pins: 1 pin 1 pin input pins: standard 1 pin 1 pin voltage nmos open drain high current i/o pins: 5 pins a/d converter resistor ladder successive approximations a/d converter resolution: 8 bits generates an interrupt at the end of the a/d conversion period analog analog analog inputs: 8 channels analog inputs: 12 channels inputs: inputs: 4 channels 3 channels plus v ref pin specifications
8 table 1-2 hmcs43xx family functional overview (cont) hd404344r hd404394 hd404318 hd404358 hd404358r hd404339 hd404369 item series series series series series series series timer a can be driven by any one can be driven by any one of eight internal clocks of eight internal clocks generated by dividing the generated by dividing the system clock. system clock. generates an interrupt on can be driven by any one overflow. of five internal clocks generated by dividing the 32.768 khz oscillator. (clock time base) generates an interrupt on overflow. timer b can be driven by any one of seven internal clocks generated by dividing the system clock or by event input. event input detection on rising edges, falling edges, or falling/rising edge pairs generates an interrupt on overflow. also supports input capture operation timer c can be driven by any one of eight internal clocks generated by dividing the system clock. supports pwm output. can also function as a watchdog timer. generates an interrupt on overflow. serial interface single channel 8-bit clock synchronization serial interface one of 13 internal clocks or an external clock can be used as the transfer clock. can control the high/low level output state of the data transmission pin in idle mode. generates interrupts on transfer complete and transfer interrupted. alarm output outputs one of four frequencies generated by dividing the system clock. interrupts external interrupt pins: 1 pin external interrupt pins: 2 pins internal interrupt sources: internal interrupt sources: 5 sources 4 sources interrupt vectors: 7 locations interrupt vectors: 5 locations low power standby mode modes stop mode (external stop mode clear input provided) watch mode subactive mode specifications
9 table 1-2 hmcs43xx family functional overview (cont) hd404344r hd404394 hd404318 hd404358 hd404358r hd404339 hd404369 item series series series series series series series system clock 0.4 to 0.4 to 0.4 to 0.4 to 0.4 to 0.4 to 0.4 to 4.5 mhz 4.5 mhz 4.5 mhz 5.0 mhz, 5.0 mhz, 4.5 mhz 5.0 mhz, 1.0 to 1.0 to 0.4 to 0.4 to 0.4 to 3.5 mhz 3.5 mhz 8.5 mhz, 8.5 mhz, 8.5 mhz 1.0 to 1.0 to 3.5 mhz 3.5 mhz subsystem clock 32.768 khz 32.768 khz specifications
10 1.2 internal block diagrams figures 1-2 to 1-8 show the internal block diagrams for the hd404344r, hd404394, hd404318, hd404358, hd404358r, hd404339, and hd404369 series microcomputers. product hd404341r hd40c4341r hd404342r hd40c4342r hd404344r hd40c4344r hd4074344 rom (words) 1,024 2,048 4,096 4,096 ram (digits) 256 hmcs400 cpu rom ram reset stopc sck figure 1-2 hd404344r series internal block diagram
11 rom ram d 0 d 1 d 2 d 3 d 4 d 5 reset stopc sck figure 1-3 hd404394 series internal block diagram
12 hmcs400 cpu rom ram reset stopc sck figure 1-4 hd404318 series internal block diagram
13 hmcs400 cpu rom ram reset stopc sck figure 1-5 hd404358 series internal block diagram
14 hmcs400 cpu rom ram timer a (8 bits) (free-running timer) timer b (8 bits) (reload timer/event counter) timer c (8 bits) (reload timer/watchdog timer) clock synchronous 8 bits serial interface reset test stopc osc 1 osc 2 v cc gnd alarm output : nmos high current pins d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 ra port ra 1 r0 0 r0 1 r0 2 r0 3 r1 0 r1 1 r1 2 r1 3 r2 0 r2 1 r2 2 r2 3 r3 0 r3 1 r3 2 r3 3 r4 0 r4 1 r4 2 r4 3 r8 0 r8 1 r8 2 r8 3 sck si so toc evnb an 0 an 1 an 2 an 3 an 4 an 5 an 6 an 7 av cc av ss eight-channel a/d converter external interrupt control circuit int 0 int 1 buzz product hd404354r/hd40a4354r/hd40c4354r hd404356r/hd40a4356r/hd40c4356r hd404358r/hd40a4358r/hd40c4358r hd407a4359r/hd407c4359r rom (words) 4,096 6,144 8,192 16,384 ram (digits) 512 r8 port r4 port r3 port r2 port r1 port r0 port d port figure 1-6 hd404358r series internal block diagram
15 rom (words) 4,096 6,144 8,192 12,288 16,384 16,384 ram (digits) 512 reset stopc sck figure 1-7 hd404339 series internal block diagram
16 reset stopc sck figure 1-8 hd404369 series internal block diagram
17 1.3 pin functions 1.3.1 hd404344r and hd404394 series pin functions figures 1-9 and 1-10 show the pin arrangements for the hd404344r and hd404394 series products in the dp-28s, fp-28da, and fp-30d packages. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 r1 0 r1 1 r1 2 r1 3 r2 0 r2 1 r2 2 r2 3 osc 1 osc 2 gnd r3 0 /an 0 r3 1 /an 1 r3 2 /an 2 d 5 d 4 / stopc sck reset stopc sck reset figure 1-9 hd404344r and hd404394 series pin arrangements (dp-28s and fp-28da packages: top view)
18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r1 0 r1 1 r1 2 r1 3 r2 0 r2 1 r2 2 r2 3 osc 1 osc 2 gnd nc r3 0 /an 0 r3 1 /an 1 r3 2 /an 2 d 5 d 4 / stopc sck reset stopc sck reset figure 1-10 hd404344r and hd404394 series pin arrangements (fp-30d package: top view)
19 table 1-3 lists the pin assignments for the hd404344r and hd404394 series microcomputers. table 1-3 hd404344r and hd404394 series pin assignments pin no. pin function dp-28s, fp-28da fp-30d pin hd404344r series hd404394 series 11r1 0 standard voltage high current i/o port medium voltage i/o port 22r1 1 standard voltage high current i/o port medium voltage i/o port 33r1 2 standard voltage high current i/o port medium voltage i/o port 44r1 3 standard voltage high current i/o port standard voltage high current i/o port 55r2 0 standard voltage high current i/o port standard voltage high current i/o port 66r2 1 standard voltage high current i/o port standard voltage high current i/o port 77r2 2 standard voltage high current i/o port standard voltage high current i/o port 88r2 3 standard voltage high current i/o port standard voltage high current i/o port 9 9 osc 1 system clock oscillator connection: input 10 10 osc 2 system clock oscillator connection: output 11 11 gnd ground 12 13 r3 0 /an 0 (v ref ) * standard voltage i/o port/ analog input channel analog reference voltage 13 14 r3 1 /an 1 standard voltage i/o port/analog input channel 14 15 r3 2 /an 2 standard voltage i/o port/analog input channel 15 16 r3 3 /an 3 standard voltage i/o port/analog input channel 16 18 v cc power supply 17 19 test test 18 20 reset sck * items without parentheses apply to the hd404344r series and items in parentheses apply to the hd404394 series.
20 table 1-3 hd404344r and hd404394 series pin assignments (cont) pin no. pin function dp-28s, fp-28da fp-30d pin hd404344r series hd404394 series 21 23 r0 2 /so standard voltage i/o port/serial transmission data output 22 24 r0 3 /toc standard voltage i/o port/timer c output 23 25 d 0 / int stopc 12 nc 17 nc note: no connections should be made to nc pins.
21 table 1-4 lists the pin functions for the hd404344r and hd404394 series microcomputers. table 1-4 hd404344r and hd404394 series pin functions type symbol i/o function power supply v cc power supply: connect to the system power supply. gnd ground: connect to the system ground v ref analog reference voltage (hd404394 series): connection for the a/d converter internal resistor ladder power supply. clock osc 1 input system clock oscillator connection 1: connect a ceramic oscillator or an oscillator circuit to this pin. alternately, for cr oscillation a resistor should be connected. use an oscillator with a clock frequency between 400 khz and 4.5 mhz. see section 13, oscillator circuits, for examples of the circuits used when connecting a ceramic oscillator or resistor, or when using an external clock input. osc 2 output system clock oscillator connection 2: connect a ceramic oscillator to this pin. use an oscillator with a frequency of between 400 khz and 4.5 mhz. alternately, for cr oscillation a resistor should be connected. leave this pin open if an external clock is input to the osc 1 pin. port d 0 to d 5 i/o d port: i/o pins (cmos three state) that can be accessed in 1-bit units. pins d 1 and d 2 are high current pins that can accept influx currents of up to 15 ma. r0 0 to r0 3 i/o r0 port: standard i/o pins (cmos three state) that can be accessed as a 4-bit unit. r1 0 to r1 3 i/o r1 port (hd404344r series): i/o pins (cmos three state) that can be accessed as a 4-bit unit. pins r1 0 to r1 3 are high current pins that can accept influx currents of up to 15 ma. r1 port (hd404394 series): i/o pins that can be accessed as a 4-bit unit. pins r1 0 to r1 2 are medium voltage i/o pins (nmos open drain). also, pin r1 3 is a standard voltage high current pin that can accept influx currents of up to 15 ma.
22 table 1-4 hd404344r and hd404394 series pin functions (cont) type symbol i/o function port r2 0 to r2 3 i/o r2 port (hd404344r series): i/o pins (cmos three state) that can be accessed as a 4-bit unit. pins r2 0 to r2 3 are high current pins that can accept influx currents of up to 15 ma. r2 port (hd404394 series): i/o pins (nmos open drain) that can be accessed as a 4-bit unit. pins r2 0 to r2 3 are high current pins that can accept influx currents of up to 15 ma. r3 0 to r3 3 , (r3 1 to r3 3 ) * i/o r3 port: standard i/o pins (cmos three state) that can be accessed as a 4-bit (3-bit) * unit. system control test input test: connect to ground. reset stopc int sck * input analog input channels 0 to 3 (hd404344r series): analog input channels for the a/d converter. analog input channels 1 to 3 (hd404394 series): analog input channels for the a/d converter. note: * items without parentheses apply to the hd404344r series and items in parentheses apply to the hd404394 series.
23 1.3.2 hd404318/hd404358/hd404358r series pin functions figures 1-11 and 1-12 show the pin arrangements for the hd404318, hd404358 and hd404358r series products in the dp-42s and fp-44a packages. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 ra 1 /v disp r0 0 / sck reset stopc sck reset stopc figure 1-11 hd404318, hd404358 and hd404358r series pin arrangements (dp-42s package: top view)
24 test reset sck stopc reset sck stopc figure 1-12 hd404318, hd404358 and hd404358r series pin arrangements (fp-44a package: top view)
25 table 1-5 lists the pin assignments for the hd404318, hd404358 and hd404358r series microcomputers. table 1-5 hd404318, hd404358 and hd404358r series pin assignments pin no. pin function dp-42s fp-44a pin hd404318 series hd404358 series hd404358r series 139ra 1 / (v disp ) * high voltage input port/high voltage pin output power supply standard voltage input port 240r0 0 / sck reset * items in parentheses apply only to the hd404318 series.
26 table 1-5 hd404318, hd404358 and hd404358r series pin assignments (cont) pin no. pin function dp-42s fp-44a pin hd404318 series hd404358 series hd404358r series 21 16 v cc power supply 22 17 d 0 / int int stopc
27 table 1-5 hd404318, hd404358 and hd404358r series pin assignments (cont) pin no. pin function dp-42s fp-44a pin hd404318 series hd404358 series hd404358r series 39 35 r2 0 high voltage i/o port medium voltage i/o port standard voltage high current i/o port 40 36 r2 1 high voltage i/o port medium voltage i/o port standard voltage high current i/o port 41 37 r2 2 high voltage i/o port medium voltage i/o port standard voltage high current i/o port 42 38 r2 3 high voltage i/o port medium voltage i/o port standard voltage high current i/o port 22 nc 44 nc note: no connections should be made to nc pins.
28 table 1-6 lists the pin functions for the hd404318, hd404358 and hd404358r series microcomputers. table 1-6 hd404318, hd404358 and hd404358r series pin functions type symbol i/o function power supply v cc power supply: connect to the system power supply. gnd ground: connect to the system ground av cc analog power supply: the a/d converter power supply connection. connect to a potential identical to that of v cc at a point as close as possible to the v cc pin. note that a bypass capacitor (about 0.1 ?) should be connected between the av cc pin and the av ss pin if a power supply separate from the v cc power supply is used for the a/d converter power supply. this capacitor is not required if the av cc pin is connected directly to the v cc pin. av ss analog ground: the a/d converter ground connection. connect to a potential identical to that of gnd at a point as close as possible to the gnd pin. v disp high voltage pin output power supply (hd404318 series): used as the output power supply by the high voltage pins. clock osc 1 input system clock oscillator connection 1: connect a ceramic or crystal oscillator, or an external oscillator circuit. use an oscillator or clock with a frequency of between 400 khz and 4.5 mhz for the hd404318 and a frequency between 400 khz and 8.5 mhz for the hd404358/hd404358r. alternately, for cr oscillation * a resistor should be connected. see section 13, oscillator circuits for examples of the circuits used when a ceramic or crystal oscillator, a resistor, or an external clock is used. osc 2 output system clock oscillator connection 2: connect a ceramic or crystal oscillator to this pin. use an oscillator with a frequency of between 400 khz and 4.5 mhz for the hd404318 and a frequency between 400 khz and 8.5 mhz for the hd404358/hd404358r. alternately, for cr oscillation * a resistor should be connected. leave this pin open if an external clock is input to the osc 1 pin.
29 table 1-6 hd404318, hd404358 and hd404358r series pin functions (cont) type symbol i/o function port d 0 to d 8 i/o high voltage d port (hd404318 series): high voltage i/o pins (pmos open drain) that can be accessed in 1-bit units. d port (hd404358 series): standard voltage i/o pins (cmos three state) that can be accessed in 1-bit units. d port (hd404358r series): standard voltage i/o pins (cmos three state) that can be accessed in 1-bit units. pins d 5 to d 8 are high-current pins (cmos three state) capable of handling current levels of up to 15 ma. r0 0 to r0 3 i/o r0 port: standard voltage i/o pins (cmos three state) that can be accessed as a 4-bit unit. r0 port (hd404358r series): standard voltage high current i/o pins (cmos three state) that can be accessed as a 4-bit unit. pins r0 0 to r0 3 are high - current pins capable of handling current levels of up to 15 ma. r1 0 to r1 3 i/o high voltage r1 port (hd404318 series): high voltage i/o pins (pmos open drain) that can be accessed as a 4-bit unit. r1 port (hd404358 series): standard voltage i/o pins (cmos three state) that can be accessed as a 4-bit unit. r1 port (hd404358r series): standard voltage high current i/o pins that can be accessed as a 4-bit unit. pins r1 0 to r1 3 are high-current pins (cmos three state) capable of handling current levels of up to 15 ma. r2 0 to r2 3 i/o high voltage r2 port (hd404318 series): high voltage i/o pins (pmos open drain) that can be accessed as a 4-bit unit. medium voltage r2 port (hd404358 series): medium voltage i/o pins (nmos open drain) that can be accessed as a 4-bit unit. r2 port (hd404358r series): standard voltage high current i/o pins that can be accessed as a 4-bit unit. pins r2 0 to r2 3 are high-current pins (cmos three state) capable of handling current levels of up to 15 ma. r3 0 to r3 3 i/o r3 port: standard voltage i/o pins (cmos three state) that can be accessed as a 4-bit unit. r4 0 to r4 3 i/o r4 port: standard voltage i/o pins (cmos three state) that can be accessed as a 4-bit unit.
30 table 1-6 hd404318, hd404358 and hd404358r series pin functions (cont) type symbol i/o function port r8 0 to r8 3 i/o high voltage r8 port (hd404318 series): high voltage i/o pins (pmos open drain) that can be accessed as a 4-bit unit. r8 port (hd404358 series): standard voltage i/o pins (cmos three state) that can be accessed as a 4-bit unit. r8 port (hd404358r series): standard voltage large current i/o pins that can be accessed as a 4-bit unit. pins r8 0 to r8 3 are high-current pins (cmos three state) capable of handling current levels of up to 15 ma. ra 1 input high voltage ra port (hd404318 series): single bit high voltage input pin. ra port (hd404358/hd404358r series): single bit standard input pin. system control test input test: connect to ground. reset stopc int int sck * apply to the hd404358r series.
31 1.3.3 hd404339/hd404369 series pin functions figures 1-13 and 1-14 show the pin arrangements for the hd404339 and hd404369 series products in the dp-64s, and fp-64b packages. ra 1 /v disp r2 3 r2 2 r2 1 r2 0 r1 3 r1 2 r1 1 r1 0 r9 3 r9 2 r9 1 r9 0 r8 3 r8 2 r8 1 r8 0 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 / stopc sck reset stopc sck reset figure 1-13 hd404339 and hd404369 series pin arrangements (dp-64s package: top view)
32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 fp-64b 20 21 22 23 24 25 26 27 28 29 30 31 32 r7 1 r7 0 r6 3 r6 2 r6 1 r6 0 ra 1 /v disp r2 3 r2 2 r2 1 r2 0 r1 3 r1 2 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 r1 1 r1 0 r9 3 r9 2 r9 1 r9 0 r8 3 r8 2 r8 1 r8 0 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 r7 2 r0 0 / sck reset stopc sck reset stopc figure 1-14 hd404339 and hd404369 series pin arrangements (fp-64b package: top view)
33 table 1-7 lists the pin assignments for the hd404339 and hd404369 series microcomputers. table 1-7 hd404339 and hd404369 series pin assignments pin no. pin function dp-64s fp-64b pin hd404339 series hd404369 series 159 r6 0 standard voltage i/o port 260 r6 1 standard voltage i/o port 361 r6 2 standard voltage i/o port 462 r6 3 standard voltage i/o port 563 r7 0 standard voltage i/o port 664 r7 1 standard voltage i/o port 71 r7 2 standard voltage i/o port 82 r0 0 / sck reset
34 table 1-7 hd404339 and hd404369 series pin assignments (cont) pin no. pin function dp-64s fp-64b pin hd404339 series hd404369 series 29 23 r5 1 /an 9 standard voltage i/o port/analog input channel 30 24 r5 2 /an 10 standard voltage i/o port/analog input channel 31 25 r5 3 /an 11 standard voltage i/o port/analog input channel 32 26 av cc analog power supply 33 27 v cc power supply 34 28 d 0 / int int stopc
35 table 1-7 hd404339 and hd404369 series pin assignments (cont) pin no. pin function dp-64s fp-64b pin hd404339 series hd404369 series 55 49 r9 3 high voltage i/o port standard voltage i/o port 56 50 r1 0 high voltage i/o port medium voltage i/o port 57 51 r1 1 high voltage i/o port medium voltage i/o port 58 52 r1 2 high voltage i/o port medium voltage i/o port 59 53 r1 3 high voltage i/o port medium voltage i/o port 60 54 r2 0 high voltage i/o port medium voltage i/o port 61 55 r2 1 high voltage i/o port medium voltage i/o port 62 56 r2 2 high voltage i/o port medium voltage i/o port 63 57 r2 3 high voltage i/o port medium voltage i/o port 64 58 ra 1 / (vdisp) * high voltage input port/ high voltage pin output power supply standard voltage input port note: * items in parentheses apply only to the hd404339 series.
36 table 1-8 lists the pin functions for the hd404339 and hd404369 series microcomputers. table 1-8 hd404339 and hd404369 series pin functions type symbol i/o function power supply v cc power supply: connect to the system power supply. gnd ground: connect to the system ground av cc analog power supply: the a/d converter power supply connection. connect to a potential identical to that of v cc at a point as close as possible to the v cc pin. note that a bypass capacitor (about 0.1 ?) should be connected between the av cc pin and the av ss pin if a power supply separate from the v cc power supply is used for the a/d converter power supply. this capacitor is not required if the av cc pin is connected directly to the v cc pin. av ss analog ground: the a/d converter ground connection. connect to a potential identical to that of gnd at a point as close as possible to the gnd pin. v disp high voltage pin output power supply (hd404339 series): used as the output power supply by the high voltage pins. clock osc 1 input system clock oscillator connection 1: connect a ceramic or crystal oscillator to this pin. alternatively, an external clock signal may be input to this pin. use an oscillator or clock with a frequency of between 400 khz and 4.5 mhz for the hd404339 and a frequency between 400 khz and 8.5 mhz for the hd404369. see section 14, oscillator circuits for examples of the circuits used when a ceramic or crystal oscillator or an external clock is used. osc 2 output system clock oscillator connection 2: connect a ceramic or crystal oscillator to this pin. use an oscillator with a frequency of between 400 khz and 4.5 mhz for the hd404339 and a frequency between 400 khz and 8.5 mhz for the hd404369. leave this pin open if an external clock is input to the osc 1 pin. x1 input subsystem clock oscillator connection 1: connect a 32.768 khz crystal oscillator to this pin. tie this pin to ground if the subsystem clock is not used. x2 output subsystem clock oscillator connection 2: connect a 32.768 khz crystal oscillator to this pin. leave this pin open if the subsystem clock is not used.
37 table 1-8 hd404339 and hd404369 series pin functions (cont) type symbol i/o function port d 0 to d 13 i/o high voltage d port (hd404339 series): high voltage i/o pins (pmos open drain) that can be accessed in 1- bit units. d port (hd404369 series): standard i/o pins (cmos three state) that can be accessed in 1-bit units. r0 0 to r0 3 i/o r0 port: standard i/o pins (cmos three state) that can be accessed as a 4-bit unit. r1 0 to r1 3 i/o high voltage r1 port (hd404339 series): high voltage i/o pins (pmos open drain) that can be accessed as a 4-bit unit. medium voltage r1 port (hd404369 series): medium voltage i/o pins (nmos open drain) that can be accessed as a 4-bit unit. r2 0 to r2 3 i/o high voltage r2 port (hd404339 series): high voltage i/o pins (pmos open drain) that can be accessed as a 4-bit unit. medium voltage r2 port (hd404369 series): medium voltage i/o pins (nmos open drain) that can be accessed as a 4-bit unit. r3 0 to r3 3 i/o r3 port: standard i/o pins (cmos three state) that can be accessed as a 4-bit unit. r4 0 to r4 3 i/o r4 port: standard i/o pins (cmos three state) that can be accessed as a 4-bit unit. r5 0 to r5 3 i/o r5 port: standard i/o pins (cmos three state) that can be accessed as a 4-bit unit. r6 0 to r6 3 i/o r6 port: standard i/o pins (cmos three state) that can be accessed as a 4-bit unit. r7 0 to r7 2 i/o r7 port: three-bit standard i/o pins (cmos three state). r8 0 to r8 3 i/o high voltage r8 port (hd404339 series): high voltage i/o pins (pmos open drain) that can be accessed as a 4-bit unit. r8 port (hd404369 series): standard i/o pins (cmos three state) that can be accessed as a 4-bit unit. r9 0 to r9 3 i/o high voltage r9 port (hd404339 series): high voltage i/o pins (pmos open drain) that can be accessed as a 4-bit unit. r9 port (hd404369 series): standard i/o pins (cmos three state) that can be accessed as a 4-bit unit.
38 table 1-8 hd404339 and hd404369 series pin functions (cont) type symbol i/o function port ra 1 input high voltage ra port (hd404339 series): single bit high voltage input pin. ra port (hd404369 series): single bit standard input pin. system control test input test: connect to ground. reset stopc int int sck
39 section 2 memory 2.1 overview table 2-1 lists rom and ram capacities of the products in the hmcs43xx family. table 2-1 rom and ram capacities series product rom ram hd404344r hd404341r/hd40c4341r 1,024 words 256 digits hd404342r/hd40c4342r 2,048 words hd404344r/hd40c4344r 4,096 words hd4074344 4,096 words hd404394 hd404391 1,024 words 256 digits hd404392 2,048 words hd404394 4,096 words hd4074394 4,096 words hd404318 hd404314 4,096 words 384 digits hd404316 6,144 words hd404318 8,192 words hd4074318 8,192 words hd404358 hd404354/hd40a4354 4,096 words 384 digits hd404356/hd40a4356 6,144 words hd404358/hd40a4358 8,192 words hd407a4359 16,384 words 512 digits hd404358r hd404354r/hd40a4354r/hd40c4354r 4,096 words 512 digits hd404356r/hd40a4356r/hd40c4356r 6,144 words hd404358r/hd40a4358r/hd40c4358r 8,192 words hd407a4359r 16,384 words hd407c4359r 16,384 words note: 1 word: 10 bits 1 digit: 4 bits
40 table 2-1 rom and ram capacities (cont) series product rom ram hd404339 hd404334 4,096 words 512 digits hd404336 6,144 words hd404338 8,192 words hd4043312 12,288 words hd404339 16,384 words hd4074339 16,384 words hd404369 hd404364/hd40a4364 4,096 words 512 digits hd404368/hd40a4368 8,192 words hd4043612/hd40a43612 12,288 words hd404369/hd40a4369 16,384 words hd407a4369 16,384 words note: 1 word: 10 bits 1 digit: 4 bits 2.2 rom 2.2.1 vector address area the vector address area is allocated to rom addresses $0000 to $000f. on a reset, when stop mode is cleared, or when an interrupt is handled, the processor executes the instruction at one of eight fixed vector addresses depending on the particular exception handling factor involved. therefore, user software should specify a jmpl instruction (the unconditional long jump instruction: two words) that branches to the start of the appropriate reset, stop mode clear, or interrupt handling routine at each of these vector addresses. (see figures 2-1 and 2-2.) 2.2.2 zero page subroutine area the zero page subroutine area is allocated to rom addresses $0000 to $003f. user programs can make conditional subroutine calls to arbitrary addresses in this area with the cal instruction. 2.2.3 pattern area the pattern area is allocated to rom addresses $0000 to $0fff. user programs can move rom bit patterns (8 bits) in this area either to the r1 and r2 port data register pair or to the accumulator and b register pair with the p instruction.
41 2.2.4 program area all of the rom address space can be used as program area. figure 2-1 shows the rom memory map for the microcomputers in the hd404344r and hd404394 series. $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000a $000b $000c $000d $000e $000f $0000 $000f $0010 $003f $0040 $03ff $0400 $07ff $0800 $0fff $1000 $3fff rom address rom address vector address area (16 words) zero page subroutine area (64 words) 1-kword rom product program/pattern area (1,024 words) 2-kword rom product program/pattern area (2,048 words) 4-kword rom product program/pattern area (4,096 words) unused jmpl instruction (jumps to the reset and stop mode clear handling routine) jmpl instruction (jumps to the int 0 interrupt handling routine) unused jmpl instruction (jumps to the timer b interrupt handling routine) jmpl instruction (jumps to the timer c interrupt handling routine) jmpl instruction (jumps to the a/d converter interrupt handling routine) jmpl instruction (jumps to the serial interface interrupt handling routine) note: the program/pattern area differs between different products in these series. rom capacity product pattern area addresses capacity addresses capacity program area hd404341r hd40c4341r hd404391 $0000 to $03ff $0000 to $03ff 1-kword 1,024 words 1,024 words hd404342r hd40c4342r hd404392 $0000 to $07ff $0000 to $07ff 2-kword 2,048 words 2,048 words hd404344r hd40c4344r hd4074344 hd404394 hd4074394 $0000 to $0fff $0000 to $0fff 4-kword 4,096 words 4,096 words figure 2-1 hd404344r and hd404394 series rom memory map
42 figure 2-2 shows the memory map for the microcomputers in the hd404318, hd404358, hd404358r, hd404339, and hd404369 series. $0000 to $0fff $0000 to $17ff $0000 to $1fff $0000 to $2fff $0000 to $3fff hd404314 hd404316 hd404318 hd4074318 hd404354 hd40a4354 hd404356 hd40a4356 hd404358 hd40a4358 hd407a4359 hd404334 hd404336 hd404338 hd4043312 hd404339 hd4074339 hd404364 hd40a4364 hd404368 hd40a4368 hd4043612 hd40a43612 hd404369 hd40a4369 hd407a4369 $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000a $000b $000c $000d $000e $000f $0000 $000f $0010 $003f $0040 $0fff $1000 $17ff $1800 $1fff $2000 $2fff $3000 $3fff rom address rom address vector address area (16 words) zero page subroutine area (64 words) 4-kword rom product program/pattern area (4,096 words) 6-kword rom product program area (6,144 words) 8-kword rom product program area (8,192 words) 12-kword rom product program area (12,288 words) 16-kword rom product program area (16,384 words) jmpl instruction (jumps to the reset and stop mode clear handling routine) jmpl instruction (jumps to the int 0 interrupt handling routine) jmpl instruction (jumps to the int 1 interrupt handling routine) jmpl instruction (jumps to the timer a interrupt handling routine) jmpl instruction (jumps to the timer b interrupt handling routine) jmpl instruction (jumps to the timer c interrupt handling routine) jmpl instruction (jumps to the a/d converter interrupt handling routine) jmpl instruction (jumps to the serial interface interrupt handling routine) note: the program area differs between different products in these series. rom capacity product program area addresses capacity 4-kword 6-kword 8-kword 12-kword 16-kword 4,096 words 6,144 words 8,192 words 12,288 words 16,384 words hd404354r hd40a4354r hd40c4354r hd404356r hd40a4356r hd40c4356r hd404358r hd40a4358r hd40c4358r hd407a4359r hd407c4359r figure 2-2 hd404318, hd404358, hd404358r, hd404339, and hd404369 series rom memory map
43 2.3 ram figure 2-3 shows the ram memory map for the microcomputers in the hd404344r and hd404394 series. w w r/w r/w w r/w r/w w w r/w r/w w r r w w w w w $000 $003 $004 $005 $006 $007 $009 $00a $00b $00c $00d $00e $00f $016 $017 $018 $019 $01a $020 $023 $024 $025 $026 (pmra) (smr) (srl) (sru) (tmb1) (trbl/twbl) (trbu/twbu) (mis) (tmc) (trcl/twcl) (trcu/twcu) $000 $03f (acr) (adrl) (adru) (amr1) (amr2) (pmrb) (pmrc) (tmb2) * * symbols r: w: r/w: read only write only read/write $040 $050 $100 $3c0 $3ff w w w w (dcr0) (dcr1) (dcr2) (dcr3) w w $02c $02d $030 $031 $032 $033 (dcd0) (dcd1) $00a $00b $00e $00f (twbl) (twbu) w w r r w w r r (trbl) (trbu) (trcl) (trcu) (twcl) (twcu) ram address ram address interrupt control bit area port mode register a serial mode register serial data register l serial data register u unused unused register flag area unused unused unused note: * timer b miscellaneous register timer mode register c timer c a/d channel register a/d data register l a/d data register u a/d mode register 1 a/d mode register 2 port mode register b port mode register c port mode register b2 data control registers d 0 to d 3 data control registers d 4 and d 5 data control register r0 data control register r1 data control register r2 data control register r3 timer write register bl timer write register bu timer write register cl timer write register cu timer read register bl timer read register bu timer read register cl timer read register cu ram mapped register area memory register (mr) data (176 digits) unused stack (64 digits) two registers are mapped to the same address at locations $00a, $00b, $00e, and $00f. unused timer mode register b1 figure 2-3 hd404344r and hd404394 series ram memory map
44 figure 2-4 shows the ram memory map for the microcomputers in the hd404318 series. w w r/w r/w w w r/w r/w w w r/w r/w w r r w w w w w w w $000 $003 $004 $005 $006 $007 $008 $009 $00a $00b $00c $00d $00e $00f $016 $017 $018 $019 $01a $020 $023 $024 $025 $026 $033 $034 (pmra) (smr) (srl) (sru) (tma) (tmb1) (trbl/twbl) (trbu/twbu) (mis) (tmc) (trcl/twcl) (trcu/twcu) $000 $03f (acr) (adrl) (adru) (amr1) (amr2) (pmrb) (pmrc) (tmb2) (dcr3) (dcr4) w $030 (dcr0) $040 $050 $180 $3c0 $3ff * * $00a $00b $00e $00f (twbl) (twbu) w w r r w w r r (trbl) (trbu) (trcl) (trcu) (twcl) (twcu) ram address ram address interrupt control bit area port mode register a serial mode register serial data register l serial data register u timer mode register a timer mode register b1 timer b miscellaneous register timer mode register c timer c a/d channel register a/d data register l a/d data register u a/d mode register 1 a/d mode register 2 unused register flag area port mode register b port mode register c port mode register b2 unused data control register r0 unused data control register r3 data control register r4 unused symbols r: w: r/w: read only write only read/write note: * two registers are mapped to the same address at locations $00a, $00b, $00e, and $00f. timer write register bl timer write register bu timer write register cl timer write register cu ram mapped register area memory register (mr) data (304 digits) unused stack (64 digits) timer read register bl timer read register bu timer read register cl timer read register cu unused figure 2-4 hd404318 series ram memory map
45 figure 2-5 shows the ram memory map for the microcomputers in the hd404358/hd404358r series. w w r/w r/w w w r/w r/w w w r/w r/w w r r w w w w w w $000 $003 $004 $005 $006 $007 $008 $009 $00a $00b $00c $00d $00e $00f $016 $017 $018 $019 $01a $020 $023 $024 $025 $026 $038 (pmra) (smr) (srl) (sru) (tma) (tmb1) (trbl/twbl) (trbu/twbu) (mis) (tmc) (trcl/twcl) (trcu/twcu) $000 $03f (acr) (adrl) (adru) (amr1) (amr2) (pmrb) (pmrc) (tmb2) (dcr8) * 1 * 1 $050 $180 $3c0 $3ff $200 w w w w w (dcr0) (dcr1) (dcr2) (dcr3) (dcr4) w w w $02c $02d $02e $02f $030 $031 $032 $033 $034 (dcd0) (dcd1) (dcd2) $040 $00a $00b $00e $00f (twbl) (twbu) w w r r w w r r (trbl) (trbu) (trcl) (trcu) (twcl) (twcu) ram address ram address symbols r: w: r/w: read only write only read/write notes: two registers are mapped to the same address at locations $00a, $00b, $00e, and $00f. interrupt control bit area unused unused unused unused unused port mode register a serial mode register serial data register l serial data register u timer mode register a timer mode register b1 timer b timer c a/d channel register a/d data register l a/d data register u a/d mode register 1 a/d mode register 2 register flag area port mode register b port mode register c port mode register b2 data control registers d 0 to d 3 data control registers d 4 to d 7 data control register d8 data control register r0 data control register r1 data control register r2 data control register r3 data control register r4 data control register r8 timer write register bl timer write register bu timer write register cl timer write register cu timer read register bl timer read register bu timer read register cl timer read register cu ram mapped register area memory register (mr) data (304 digits) * 2 data (432 digits) * 3 unused stack (64 digits) 1. applies to the hd404354, hd404356, hd404358, hd40a4354, hd40a4356, and hd40a4358. applies to the hd404354r, hd404356r, hd404358r, hd40a4354r, hd40a4356r, hd40a4358r, hd40c4354r, hd40c4356r, hd40c4358r, hd407a4359r, hd407c4359r, hd407a4359. 2. 3. miscellaneous register timer mode register c unused figure 2-5 hd404358/hd404358r series ram memory map
46 figure 2-6 shows the ram memory map for the microcomputers in the hd404339 series. w w r/w r/w w w r/w r/w w w r/w r/w w r r w w w w w w w w w w w w $000 $003 $004 $005 $006 $007 $008 $009 $00a $00b $00c $00d $00e $00f $016 $017 $018 $019 $01a $020 $024 $025 $026 $027 $028 $033 $034 $035 $036 $037 (pmra) (smr) (srl) (sru) (tma) (tmb1) (trbl/twbl) (trbu/twbu) (mis) (tmc) (trcl/twcl) (trcu/twcu) $000 $03f (acr) (adrl) (adru) (amr1) (amr2) (pmrb) (pmrc) (tmb2) (ssr1) (ssr2) (dcr3) (dcr4) (dcr5) (dcr6) (dcr7) w $030 (dcr0) $040 $050 $200 $3c0 $3ff * * $00a $00b $00e $00f (twbl) (twbu) w w r r w w r r (trbl) (trbu) (trcl) (trcu) (twcl) (twcu) $023 ram address ram address interrupt control bit area port mode register a serial mode register serial data register l serial data register u timer mode register a timer mode register b1 timer b timer c unused register flag area unused a/d channel register a/d data register l a/d data register u a/d mode register 1 a/d mode register 2 port mode register b port mode register c port mode register b2 system clock selection register 1 system clock selection register 2 data control register r0 unused data control register r3 data control register r4 data control register r5 data control register r6 data control register r7 unused timer write register bl timer write register bu timer write register cl timer write register cu timer read register bl timer read register bu timer read register cl timer read register cu symbols r: w: r/w: read only write only read/write note: * two registers are mapped to the same address at locations $00a, $00b, $00e, and $00f. unused ram mapped register area memory register (mr) data (432 digits) stack (64 digits) miscellaneous register timer mode register c unused figure 2-6 hd404339 series ram memory map
47 figure 2-7 shows the ram memory map for the microcomputers in the hd404369 series. w w r/w r/w w w r/w r/w w w r/w r/w w r r w w w w w w w w w w w w w w w w w w w w w interrupt control bit area $003 $004 $005 $006 $007 $008 $009 $00a $00b $00c $00d $00e $00f $016 $017 $018 $019 $01a $020 $023 $024 $025 $026 $027 $028 $02c $02d $02e $02f $030 $031 $032 $033 $034 $035 $036 $037 $038 $039 (pmra) (smr) (srl) (sru) (tma) (tmb1) (trbl/twbl) (trbu/twbu) (mis) (tmc) (trcl/twcl) (trcu/twcu) $000 $03f (acr) (adrl) (adru) (amr1) (amr2) (pmrb) (pmrc) (tmb2) (ssr1) (ssr2) (dcd0) (dcd1) (dcd2) (dcd3) (dcr0) (dcr1) (dcr2) (dcr3) (dcr4) (dcr5) (dcr6) (dcr7) (dcr8) (dcr9) * * $040 $050 $3c0 $3ff $200 $00a $00b $00e $00f (twbl) (twbu) w w r r w w r r (trbl) (trbu) (trcl) (trcu) (twcl) (twcu) symbols r: w: r/w: read only write only read/write note: * two registers are mapped to the same address at locations $00a, $00b, $00e, and $00f. ram address ram address unused unused register flag area unused unused port mode register a serial mode register serial data register l serial data register u timer mode register a timer mode register b1 miscellaneous register timer mode register c timer b timer c a/d channel register a/d data register l a/d data register u a/d mode register 1 a/d mode register 2 port mode register b port mode register c port mode register b2 system clock selection register 1 system clock selection register 2 data control registers d 0 to d 3 data control registers d 4 to d 7 data control registers d 8 to d 11 data control registers d 12 and d 13 data control register r0 data control register r1 data control register r2 data control register r3 data control register r4 data control register r5 data control register r6 data control register r7 data control register r8 data control register r9 timer write register bl timer write register bu timer write register cl timer write register cu timer read register bl timer read register bu timer read register cl timer read register cu ram mapped register area memory register (mr) data (432 digits) unused stack (64 digits) figure 2-7 hd404369 series ram memory map
48 2.3.1 ram mapped register area the ram mapped register area is allocated to ram addresses $000 to $03f. it consists of three sub-areas: the interrupt control bit area ($000 to $003), the special register area ($004 to $01f, and $024 to $03f), and the register flag area ($020 to $023). (1) interrupt control bit area ($000 to $003): the interrupt control bit area consists of the bits used for interrupt control. these bits can only be accessed by using the ram bit manipulation instructions sem, semd, rem, remd, tm, and tmd. figures 2-8 and 2-9 show the configurations of the interrupt control bit areas in each series in the hmcs43xx family. the bits in the interrupt control bit area can be set to 1 with a sem or semd instruction and can be cleared to 0 with a rem or remd instruction. the tm and tmd instructions can be used to test these bits. however, there are restrictions on the instructions that can be used with certain bits. table 2-2 lists the instruction restrictions on the interrupt control bit area. bit 3 bit 2 bit 1 bit 0 ram address im0 (int 0 interrupt mask) if0 (int 0 interrupt request flag) rsp (stack pointer reset) ie (interrupt enable flag) imtc (timer c interrupt mask) iftc (timer c interrupt request flag) imtb (timer b interrupt mask) iftb (timer b interrupt request flag) ims (serial interrupt mask) ifs (serial interrupt request flag) imad (a/d converter interrupt mask) ifad (a/d converter interrupt request flag) $000 $002 $003 : shaded bits are unused figure 2-8 hd404344r and hd404394 series interrupt control bit area configuration
49 bit 3 bit 2 bit 1 bit 0 ram address im0 (int 0 interrupt mask) if0 (int 0 interrupt request flag) rsp (stack pointer reset) ie (interrupt enable flag) imtc (timer c interrupt mask) iftc (timer c interrupt request flag) imtb (timer b interrupt mask) iftb (timer b interrupt request flag) ims (serial interrupt mask) ifs (serial interrupt request flag) imad (a/d converter interrupt mask) ifad (a/d converter interrupt request flag) $000 $002 $003 imta (timer a interrupt mask) ifta (timer a interrupt request flag) im1 (int 1 interrupt mask) if1 (int 1 interrupt request flag) $001 figure 2-9 hd404318, hd404358, hd404358r, hd404339, and hd404369 series interrupt control bit area configuration table 2-2 interrupt control bit area instruction limitations instruction bit sem/semd instruction rem/remd instruction tm/tmd instruction * ie im if rsp x symbols : allowed : the instruction will not be executed. x : unused if : interrupt request flag im : interrupt mask ie : interrupt enable flag rsp: reset stack pointer note: * the microcomputer status is undefined if a tm or tmd instruction is executed for a nonexistent bit or for an unused bit.
50 (2) special register area ($004 to $01f, and $024 to $03f): the special register area consists of mode registers for external interrupts and peripheral functions, i/o port data control registers, and other registers. there are three types of registers allocated to the special register area: read- only registers, write-only registers, and read/write registers. these registers can be referenced by immediate instructions, ram register instructions, arithmetic instructions, and comparison instructions. figures 2-10 to 2-12 show the structures of the special register areas.
51 $000 $003 pmra $004 smr $005 srl $006 sru $007 tmb1 $009 trbl/twbl $00a trbu/twbu $00b mis $00c tmc $00d trcl/twcl $00e trcu/twcu $00f acr $016 adrl $017 adru $018 amr1 $019 amr2 $01a $020 $023 pmrb $024 pmrc $025 tmb2 $026 dcd0 $02c dcd1 $02d dcr0 $030 dcr1 $031 dcr2 $032 dcr3 $033 $03f r0 3 /toc r0 1 /si transfer clock selection r0 2 /so r0 0 / sck r3 3 /an 3 r3 2 /an 2 r3 1 /an 1 r3 0 /an 0 * a/d conversion time d 4 / stopc d 0 /int 0 /evnb transfer clock selection bit 3 bit 2 bit 1 bit 0 ram address : unused serial data register (lower) serial data register (upper) interrupt control bit area auto-reload on/off clock source setting (timer b) timer b register (lower) timer b register (upper) pull-up mos control reload on/off so pmos control clock source setting (timer c) timer c register (lower) timer c register (upper) a/d execution channel selection (an 0 to an 3 (hd404344r)/an 1 to an 3 (hd404394)) a/d data register (lower) a/d data register (upper) register flag area so idle h/l setting evnb edge selection port d 3 dcr port d 2 dcr port d 1 dcr port d 5 dcr port d 0 dcr port d 4 dcr port r0 3 dcr port r1 3 dcr port r2 3 dcr port r3 3 dcr port r0 2 dcr port r1 2 dcr port r2 2 dcr port r3 2 dcr port r0 1 dcr port r1 1 dcr port r2 1 dcr port r3 1 dcr port r0 0 dcr port r1 0 dcr port r2 0 dcr port r3 0 dcr note: * applies to the hd404344r series. unused in the hd404394 series. figure 2-10 hd404344r and hd404394 series special register area structure
52 $000 $003 pmra $004 smr $005 srl $006 sru $007 tma $008 tmb1 $009 trbl/twbl $00a trbu/twbu $00b mis $00c tmc $00d trcl/twcl $00e trcu/twcu $00f acr $016 adrl $017 adru $018 amr1 $019 amr2 $01a $020 $023 pmrb $024 pmrc $025 tmb2 $026 dcd0 $02c dcd1 $02d dcd2 $02e dcr0 $030 dcr1 $031 dcr2 $032 dcr3 $033 dcr4 $034 dcr8 $038 $03f d 3 /buzz r0 0 / sck r3 3 /an 3 d 4 / stopc r0 3 /toc r3 2 /an 2 r0 1 /si r0 2 /so r3 1 /an 1 r4/an 4 to an 7 r3 0 /an 0 d 2 /evnb d 1 /int 1 d 0 /int 0 : unused note: * applies to the hd404358/hd404358r series. unused in the hd404318 series. ram address bit 3 bit 2 bit 1 bit 0 interrupt control bit area transfer clock selection serial data register (lower) serial data register (upper) clock source setting (timer a) clock source setting (timer b) auto-reload on/off timer b register (lower) timer b register (upper) pull-up mos control reload on/off so pmos control clock source setting (timer c) timer c register (lower) timer c register (upper) a/d execution channel selection (an 0 to an 7 ) a/d data register (lower) a/d data register (upper) register flag area alarm frequency input capture setting so idle h/l setting transfer clock selection evnb edge selection port d 3 dcr * port d 7 dcr * port d 2 dcr * port d 6 dcr * port d 1 dcr * port d 5 dcr * port d 0 dcr * port d 4 dcr * port d 8 dcr * port r0 3 dcr port r1 3 dcr * port r2 3 dcr * port r3 3 dcr port r4 3 dcr port r0 2 dcr port r1 2 dcr * port r2 2 dcr * port r3 2 dcr port r4 2 dcr port r0 1 dcr port r1 1 dcr * port r2 1 dcr * port r3 1 dcr port r4 1 dcr port r0 0 dcr port r1 0 dcr * port r2 0 dcr * port r3 0 dcr port r4 0 dcr port r8 3 dcr * port r8 2 dcr * port r8 1 dcr * port r8 0 dcr * a/d conversion time figure 2-11 hd404318, hd404358 and hd404358r series special register area structure
53 $000 $003 pmra $004 smr $005 srl $006 sru $007 tma $008 tmb1 $009 trbl/twbl $00a trbu/twbu $00b mis $00c tmc $00d trcl/twcl $00e trcu/twcu $00f acr $016 adrl $017 adru $018 amr1 $019 amr2 $01a $020 $023 pmrb $024 pmrc $025 tmb2 $026 ssr1 $027 ssr2 $028 dcd0 $02c dcd1 $02d dcd2 $02e dcd3 $02f dcr0 $030 dcr1 $031 dcr2 $032 dcr3 $033 dcr4 $034 dcr5 $035 dcr6 $036 dcr7 $037 dcr8 $038 dcr9 $039 $03f d 3 /buzz r0 0 / sck r3 3 /an 3 d 4 / stopc r0 3 /toc r3 2 /an 2 r5/an 8 to an 11 r3 1 /an 1 r4/an 4 to an 7 r3 0 /an 0 d 2 /evnb d 1 /int 1 d 0 /int 0 r0 1 /si r0 2 /so ram address bit 3 bit 2 bit 1 bit 0 : unused note: * applies to the hd404369 series. unused in the hd404339 series. interrupt control bit area transfer clock selection serial data register (lower) serial data register (upper) clock source setting (timer a) clock source setting (timer b) timer a/time base reload on/off timer b register (lower) timer b register (upper) pull-up mos control reload on/off so pmos control interrupt frame period control timer c register (lower) timer c register (upper) clock source setting (timer c) a/d execution channel selection (an0 to an11) a/d data register (lower) a/d data register (upper) a/d conversion time register flag area alarm frequency so idle h/l setting transfer clock selection input capture setting 32 khz/divisor selection evnb edge selection 32 khz oscillator stop system clock selection oscillator divisor selection port d 3 dcr * port d 7 dcr * port d 11 dcr * port d 2 dcr * port d 6 dcr * port d 10 dcr * port d 1 dcr * port d 5 dcr * port d 9 dcr * port d 13 dcr * port r0 1 dcr port r1 1 dcr * port r2 1 dcr * port r3 1 dcr port r4 1 dcr port r5 1 dcr port r6 1 dcr port r7 1 dcr port r8 1 dcr * port r9 1 dcr * port d 0 dcr * port d 4 dcr * port d 8 dcr * port d 12 dcr * port r0 0 dcr port r1 0 dcr * port r2 0 dcr * port r3 0 dcr port r4 0 dcr port r5 0 dcr port r6 0 dcr port r7 0 dcr port r8 0 dcr * port r9 0 dcr * port r0 3 dcr port r1 3 dcr * port r2 3 dcr * port r3 3 dcr port r4 3 dcr port r5 3 dcr port r6 3 dcr port r0 2 dcr port r1 2 dcr * port r2 2 dcr * port r3 2 dcr port r4 2 dcr port r5 2 dcr port r6 2 dcr port r7 2 dcr port r8 2 dcr * port r9 2 dcr * port r8 3 dcr * port r9 3 dcr * figure 2-12 hd404339 and hd404369 series special register area structure
54 (3) register flag area ($020 to $023): the register flag area consists of the adsf and wdon flags, interrupt control bits, and other bits. these bits can only be accessed by using the ram bit manipulation instructions sem, semd, rem, remd, tm, and tmd. figures 2-13 to 2-15 show the configurations of the register flag areas in each series in the hmcs43xx family. the bits in the register flag area can be set to 1 with a sem or semd instruction and can be cleared to 0 with a rem or remd instruction. the tm and tmd instructions can be used to test these bits. however, there are restrictions on the instructions that can be used with certain bits. table 2-3 lists the instruction restrictions on the register flag area. bit 3 bit 2 bit 1 bit 0 ram address $020 $022 $023 : unused rame (ram enable flag) $021 iaof (i ad off flag) wdon (watchdog on flag) adsf (a/d start flag) figure 2-13 hd404344r and hd404394 series register flag area configuration
55 bit 3 bit 2 bit 1 bit 0 ram address adsf (a/d start flag) wdon (watchdog on flag) $020 $022 $023 : unused rame (ram enable flag) iaof (i ad off flag) icef (input capture error flag) icsf (input capture status flag) $021 figure 2-14 hd404318, hd404358 and hd404358r series register flag area configuration bit 3 bit 2 bit 1 bit 0 ram address dton (dton flag) adsf (a/d start flag) wdon (watchdog on flag) lson (lson flag) rame (ram enable flag) iaof (i ad off flag) icef (input capture error flag) icsf (input capture status flag) $020 $022 $023 : unused $021 figure 2-15 hd404339 and hd404369 series register flag area configuration
56 table 2-3 register flag area instruction limitations instruction bit sem/semd instruction rem/remd instruction tm/tmd instruction * im lson iaof if icsf icef rame rsp x wdon x adsf x dton (active mode) (subactive mode) unused x symbols : allowed : the instruction will not be executed. x : unused dton: direct transfer on flag if : interrupt request flag im : interrupt mask note: * the microcomputer status is undefined if a tm or tmd instruction is executed for a nonexistent bit or for an unused bit.
57 2.3.2 memory register area the memory register (mr) area is allocated to ram addresses $040 to $04f. figure 2-16 shows the structure of the mr area. this area consists of 16 memory registers, and is a data area that can be accessed by the lamr and xmra register to register instructions in addition to the usual ram access instructions. mr (0) mr (1) mr (2) mr (3) mr (4) mr (5) mr (6) mr (7) mr (8) mr (9) mr (10) mr (11) mr (12) mr (13) mr (14) mr (15) $040 $041 $042 $043 $044 $045 $046 $047 $048 $049 $04a $04b $04c $04d $04e $04f ram address figure 2-16 memory register area structure
58 2.3.3 data area the data area is allocated to the whole of ram. note that the size differs between products. table 2-4 shows the structure of the data areas in the different products in the hmcs43xx family. table 2-4 data area structure series product ram addresses capacity (digits) hd404344r all products $050 to $0ff 176 hd404394 hd404318 all products $050 to $17f 304 hd404358 hd404354/hd40a4354 hd404356/hd40a4356 hd404358/hd40a4358 $050 to $17f 304 hd407a4359 $050 to $1ff 432 hd404358r all products $050 to $1ff 432 hd404339 all products $050 to $1ff 432 hd404369 all products $050 to $1ff 432
59 2.3.4 stack area the stack area is allocated to ram addresses $3c0 to $3ff. figure 2-17 shows the structure of the stack area. this area is used to save the program counter (pc), the status (st), and the carry (ca) on a subroutine call (with the cal or call instruction) or an interrupt. since four digits are used for each level, up to 16 levels of subroutine calls can be used. the saved value of the pc is restored by the rtn and rtni instructions. the st and ca are only restored by the rtni instruction. that part of the stack area not used for subroutine calls or interrupts can be used as a data area. level 16 level 15 level 14 level 13 level 12 level 11 level 10 level 9 level 8 level 7 level 6 level 5 level 4 level 3 level 2 level 1 $3fc $3fd $3fe $3ff st pc 10 ca pc 3 pc 13 pc 9 pc 6 pc 2 pc 12 pc 8 pc 5 pc 1 pc 11 pc 7 pc 4 pc 0 $3c0 $3ff ram address bit 3 bit 2 bit 1 bit 0 pc 13:0 is the program counter note: the value of the pc is saved with all bits inverted. figure 2-17 stack area structure
60
61 section 3 cpu 3.1 overview the hmcs400 cpu supports a concise and efficient instruction set in which all instructions are either one-word or two-word instructions, and all instructions are executed in one or two cycles, except for the return instruction, which requires 3 cycles. 3.1.1 features the hmcs400 cpu provides the following features. ? 101 instructions in ten classes ? immediate instructions: 4 ? register to register instructions: 8 ? ram addressing instructions: 13 ? ram/register instructions: 10 ? arithmetic instructions: 25 ? comparison instructions: 12 ? ram bit manipulation instructions: 6 ? rom addressing instructions: 8 ? i/o instructions: 11 (including the p instruction*) ? control instructions: 4 ? three ram addressing modes and four rom addressing modes ? ram addressing modes register indirect addressing direct addressing memory register addressing ? rom addressing modes direct addressing current page addressing zero page addressing table data addressing* note: * the p instruction is a special instruction that transfers the contents of rom (8 bits) determined by the table data addressing mode to either the accumulator/b register pair or to the r1/r2 port data register pair.
62 ? a 16,384 word rom address space and a 1,024 digit ram address space ? instruction execution time: 1 ? (when f osc = 4 mhz) ? low power modes the sby and stop instructions switch the hmcs400 cpu to a low power mode. 3.1.2 address space the hmcs400 cpu address space consists of two independent address spaces: a rom address space and a ram address space. the rom address space consists of word (10-bit) units with addresses in the range $0000 to $3fff. the ram address space consists of digit (4-bit) units with addresses in the range $000 to $3ff. see section 2, ?emory?for detailed information.
63 3.1.3 register organization figure 3-1 shows the organization of the hmcs400 cpu internal registers. 30 30 30 30 30 30 0 1 0 0 0 0 a b w x y spx spy ca st pc sp 13 9 1 5 11 1 accumulator b register w register x register y register spx register spy register carry status program counter initial value: 0, r/w not allowed stack pointer initial value: $3ff, r/w not allowed initial value: undefined, r/w allowed initial value: undefined, r/w allowed initial value: undefined, r/w allowed initial value: undefined, r/w allowed initial value: undefined, r/w allowed initial value: undefined, r/w allowed initial value: undefined, r/w allowed initial value: undefined, r/w allowed initial value: 1, r/w not allowed figure 3-1 hmcs400 cpu internal register organization
64 3.2 cpu registers 3.2.1 accumulator (a) and b register (b) the a and b registers are 4-bit registers that hold the results of alu (arithmetic and logic unit) operations and transfer data with memory, i/o ports, and other registers. 3.2.2 w register (w), x register (x), and y register (y) the w register is a 2-bit register and the x and y registers are 4-bit registers that are used in the ram register indirect addressing mode. the y register is also used for d port addressing. 3.2.3 spx register (spx), spy register (spy) the spx and spy registers are 4-bit registers that are used as auxiliary registers for the x and y registers. 3.2.4 carry flag (ca) the ca flag is a 1-bit flag that holds the alu overflow state when an arithmetic instruction is executed. when an overflow occurs ca is set to 1, and when no overflow occurs, it is cleared to 0. the ca flag is influenced by the sec and rec carry set and reset instructions and by the rotl and rotr rotate with carry instructions. during interrupt handling, the carry state is saved on the stack and restored by the rtni instruction. 3.2.5 status flag (st) the st flag is a 1-bit flag that holds the result of arithmetic instructions, comparison instructions, and bit test instructions. it is used as the condition for the br, brl, cal, and call conditional branch instructions. the st flag retains its value until another arithmetic, comparison, or bit test instruction is executed. the st flag is set to 1 after a conditional branch instruction is executed, regardless of whether the branch condition holds or not. during interrupt handling, the st flag state is saved on the stack and restored by the rtni instruction. 3.2.6 program counter (pc) the pc is a 14-bit counter that holds the address in rom of the next instruction that the cpu will execute.
65 3.2.7 stack pointer (sp) the sp is a 10-bit register that points to the ram address of the next empty slot in the stack area. the sp is initialized to $3ff by a reset. it is decremented by four each time data is saved when a subroutine is called or an interrupt is handled. it is incremented by four each time a return instruction is executed. the top four bits of the sp are always 1111. therefore, 16 levels is the maximum amount of stack that can be used. in addition to the reset method described above, the stack pointer can also be reset to $3ff by clearing to 0 the reset stack pointer (rsp) bit in the interrupt control bit area with a ram bit manipulation instruction (rem or remd). 3.3 addressing modes the hmcs400 cpu supports a total of seven addressing modes; three ram addressing modes and four rom addressing modes. 3.3.1 ram addressing modes the hmcs400 cpu supports the three ram addressing modes shown in figure 3-2. (1) register indirect addressing mode: register indirect addressing mode instructions consist of one word, and use the w, x, and y registers to form a 10-bit ram address. (see figure 3-2 (1).) (2) direct addressing mode: direct addressing mode instructions consist of two words. the first word is the opcode and the second word specifies a 10-bit ram address. (see figure 3-2 (2).) (3) memory register addressing mode: memory register addressing mode instructions consist of one word, in which the upper 6 bits specify the opcode and the lower 4 bits specify one of the memory registers 0 to 15. (see figure 3-2 (3).)
66 w 1 w 0 x 3 x 2 x 1 x 0 y 3 y 2 y 1 y 0 ap 9 ap 8 ap 7 ap 6 ap 5 ap 4 ap 3 ap 2 ap 1 ap 0 ram address d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 ap 9 ap 8 ap 7 ap 6 ap 5 ap 4 ap 3 ap 2 ap 1 ap 0 (2) direct addressing mode (1) register indirect addressing (3) memory register addressing mode ap 9 ap 8 ap 7 ap 6 ap 5 ap 4 ap 3 ap 2 ap 1 ap 0 m 3 m 2 m 1 m 0 000100 ram address ram address w register x register y register instruction (first word) instruction (second word) instruction opcode opcode figure 3-2 ram addressing modes
67 3.3.2 rom addressing modes and the p instruction the hmcs400 cpu supports the four rom addressing modes shown in figure 3-3. the hmcs400 cpu also supports, as a special case, access to rom data at addresses determined by table data addressing using the p instruction. (see figure 3-4.) (1) direct addressing mode: direct addressing mode instructions consist of two words. the lower 4 bits of the first word and the 10 bits of the second word form a 14-bit rom address. (see figure 3-3 (1).) (2) current page addressing mode: the hmcs400 cpu rom address space ($0000 to $3fff) is divided into 256 word units, called pages. thus the rom address space is divided into 64 pages numbered page 0 to page 63. current page addressing mode instructions consist of one word. the lower 8 bits, which follow the 2-bit opcode, specify a rom address in the same page as the instruction itself. (see figure 3-3 (2).) (3) zero page addressing mode: zero page addressing mode instructions consist of one word. the lower 6 bits, which follow the 4-bit opcode, specify an address from $0000 to $003f in page zero. (see figure 3-3 (3).) (4) table data addressing mode: table data addressing mode instructions consist of one word. the lower 4 bits, which follow the 6-bit opcode, in conjunction with the contents of the accumulator (a) and the b register (b), form a 12-bit rom address. (5) p instruction: the p instruction is used to access rom data at an address determined by table data addressing. the upper two bits of the referenced rom data are used to determine where the lower 8 bits will be transferred. if bit 8 is 1, the data is transferred to the a/b pair, if bit 9 is 1 the data is transferred to the r1/r2 port data register (pdr) pair. (see figure 3-4.) if both bits 8 and 9 are 1, the data is transferred to both the a/b pair and the r1/r2 port pdr pair. the pc is not influenced by the execution of a p instruction.
68 [jmpl] [brl] [call] p 3 p 2 p 1 p 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 pc 0 pc 1 pc 2 pc 3 pc 4 pc 5 pc 6 pc 7 pc 8 pc 9 pc 10 pc 11 pc 12 pc 13 (1) direct addressing mode [br] pc 0 pc 1 pc 2 pc 3 pc 4 pc 5 pc 6 pc 7 pc 8 pc 9 pc 10 pc 11 pc 12 pc 13 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 [cal] pc 0 pc 1 pc 2 pc 3 pc 4 pc 5 pc 6 pc 7 pc 8 pc 9 pc 10 pc 11 pc 12 pc 13 a 5 a 4 a 3 a 2 a 1 a 0 000000 0 0 [tbr] pc 0 pc 1 pc 2 pc 3 pc 4 pc 5 pc 6 pc 7 pc 8 pc 9 pc 10 pc 11 pc 12 pc 13 p 3 p 2 p 1 p 0 b 3 b 2 b 1 b 0 a 3 a 2 a 1 a 0 00 (2) current page addressing mode (3) zero page addressing mode (4) table data addressing mode instruction (first word) instruction (second word) instruction instruction instruction b register accumulator program counter program counter program counter program counter opcode opcode opcode opcode figure 3-3 rom addressing modes
69 [p] ra 0 ra 1 ra 2 ra 3 ra 4 ra 5 ra 6 ra 7 ra 8 ra 9 ra 10 ra 11 ra 12 ra 13 p 3 p 2 p 1 p 0 b 3 b 2 b 1 b 0 a 3 a 2 a 1 a 0 00 (1) address specification ro 9 ro 8 ro 7 ro 6 ro 5 ro 4 ro 3 ro 2 ro 1 ro 0 r1 0 r1 1 r1 2 r1 3 r2 0 r2 1 r2 2 r2 3 ro 9 ro 8 ro 7 ro 6 ro 5 ro 4 ro 3 ro 2 ro 1 ro 0 a 0 a 1 a 2 a 3 b 0 b 1 b 2 b 3 (2) pattern output instruction b register accumulator (when ro 8 = 1) (when ro 9 = 1) referenced rom address rom data accumulator, b register rom data port data registers for r1/r2 port opcode figure 3-4 rom data reference using the p instruction
70 3.4 processing states 3.4.1 overview the hmcs400 cpu has three processing states: the program execution state, the exception handling state, and the program stopped state. figure 3-5 shows a classification of the processing states and figure 3-6 shows the state transition diagram for these states. * * processing state program execution state active mode the cpu operates at high speed according to the system clock. state in which programs are executed sequentially. transitional state in which the cpu processing state has been changed due to a reset, the clearing of stop mode, or an interrupt exception handling event exception handling state subactive mode stop mode watch mode standby mode low power modes note: * only applies to the hd404339/hd404369 series. program stop state low power state in which clock supply to the cpu is stopped the cpu operates at low speed according to the subsystem clock. figure 3-5 processing state classification
71 program execution state exception handling state program stopped state stop or sby instruction completion of exception handling interrupt or reset interrupt, reset, or stop mode clear figure 3-6 state transition diagram 3.4.2 program execution state in the program execution state, the hmcs400 cpu executes programs sequentially. the program execution state has two modes: active mode and subactive mode. (1) active mode: in active mode, the hmcs400 cpu operates at high speed on the system clock. (2) subactive mode (hd404339/hd404369 series products only): in subactive mode, the hmcs400 cpu operates at low speed from the subsystem clock. this provides low power operation. the hmcs400 cpu switches to subactive mode when an int low power modes , for details on the low power states.
72 3.4.3 exception handling state the exception handling state is the transitional state in which the hmcs400 cpu normal processing flow has changed due to a reset, the clearing of stop mode, or an interrupt. in interrupt exception handling, the program counter (pc), carry (ca), and status (st) are saved on the stack. refer to section 4, exception handling , for details on exception handling. 3.4.4 program stopped state the program stopped state has three modes: stop mode, watch mode, and standby modes. these modes realize low power states. (1) stop mode: stop mode is entered when a stop instruction is executed in active mode when the tma3 bit in timer mode register a (tma) is set to 0. the system clock oscillator stops and the cpu, peripheral functions, and i/o ports go to the reset state. the contents of ram will be maintained as long as the stipulated voltage is applied. the transition to stop mode must be made from active mode. (2) watch mode (hd404339/hd404369 series products only): watch mode is entered in the following two cases: ? ? (3) standby mode: standby mode is entered when an sby instruction is executed. (active mode
73 section 4 exception handling 4.1 overview the hmcs400 cpu recognizes three types of exception factors: reset, stop mode clear, and interrupts. table 4-1 lists the types of exception handling and their priorities. table 4-1 exceptions their priorities priority exception factor exception handling initiation timing high reset there are two reset exception factors: ? reset pin input when the reset pin goes low the system enters the reset state and exception handling starts immediately. ? watchdog timer overflow when the watchdog timer overflows the system enters the reset state and exception handling starts immediately. stop mode clear there are two stop mode clear exception factors: ? reset pin input stop mode is cleared when the reset pin goes low. the system enters the reset state and exception handling starts immediately. ? stopc pin input stop mode is cleared when the stopc pin goes low. the system enters the reset state and exception handling starts immediately. low interrupts when an interrupt request occurs exception handling starts at the completion of the current instruction or at the completion of the current exception handling.
74 4.2 reset 4.2.1 overview reset is the highest priority exception. there are two factors that initiate reset exception handling as follows. (1) reset pin input: when the reset pin goes low all processing is discontinued and the system goes to the reset state. a reset causes the cpu internal registers and the built-in peripheral module registers to be initialized, and then reset exception handling starts immediately. (2) watchdog timer overflow: when timer c is used as a watchdog timer, the system enters the reset state when timer c overflows. after performing the same operations as performed in response to a reset pin input, reset exception handling starts immediately. 4.2.2 reset sequence when a reset exception factor occurs the system enters the reset state. to reliably reset the system when the system clock oscillator is stopped (including the state immediately following power on), the reset pin must be held low for at least the duration of the oscillator stabilization period, i.e., trc. similarly, when stop mode is cleared by a stopc pin input, the stopc pin must be held low for at least trc. also, when resetting during normal operation, the reset pin must be held low for at least two instruction cycles. when a reset exception factor occurs, the system operates as follows. note: refer to section 25, ?lectrical characteristics? for detailed information on trc. 1. when reset exception handling starts due to either a reset pin input or a watchdog timer overflow, the ram enable flag (rame) in the register flag area is cleared to 0. 2. the cpu internal states and the built-in peripheral module registers are initialized. the interrupt enable flag (ie) is cleared to 0 disabling all interrupts. refer to section 4.4, ?nitial values of registers and flags at reset and stop mode clear? for the initial values of the registers. 3. the vector address $0000 is loaded into the pc. therefore, the cpu will branch to the reset handling routine if a jmpl instruction to that routine is stored in locations $0000 and $0001. the reset pin input is an asynchronous input; that is, whatever state the system is in, it will always goes to the reset state when the reset pin goes low.
75 4.3 stop mode clear 4.3.1 overview the exception factors that clear stop mode are input to the stopc pin and input to the reset pin when the system is in stop mode. this exception factor causes stop mode to be cleared and the system to be reset. 4.3.2 stop mode clear sequence ( reset pin input) when the reset pin goes low with the system in stop mode, stop mode is cleared and the system enters the reset state. to reliably clear stop mode, the reset pin must be held low for at least trc. 4.3.3 stop mode clear sequence ( stopc pin input) when the stopc pin goes low with the system in stop mode, stop mode is cleared and the system enters the reset state. to reliably clear stop mode, the stopc pin must be held low for at least trc. except for setting the ram enable flag to 1 and retaining the values of the pmrb3 bit in port mode register b (pmrb) and the ssr13 bit in system clock selection register 1 (ssr1)*, operation is identical to reset exception handling. note: * applies only to the hd404339 and hd404369 series.
76 4.4 initial values of registers and flags on reset and stop mode clear table 4-2 lists the values of registers and flags on reset and when stop mode is cleared. table 4-2 (1) initial values of registers and flags on reset and stop mode clear initial value item hd404344r and hd404394 series hd404318, hd404358 and hd404358r series hd404339 and hd404369 series program counter (pc) $0000 $0000 $0000 status (st) 1 1 1 stack pointer (sp) $3ff $3ff $3ff interrupt flags and masks interrupt enable flag interrupt request flag interrupt mask (ie) (if) (im) 0 0 1 0 0 1 0 0 1 i/o high voltage pin port data register (pdr) all bits 0 all bits 0 all bits 0 medium/standard voltage port data register (pdr) all bits 1 all bits 1 all bits 1 data control register (dcr) all bits 0 all bits 0 all bits 0 port mode register a (pmra) -000 0000 0000 port mode register b (pmrb) 0--0 0000 0000 port mode register c (rmrc) --00 0000 0000 timer and timer mode register a (tma) -000 0000 serial interface timer mode register b1 timer mode register b2 (tmb1) (tmb2) 0000 --00 0000 -000 0000 -000 timer mode register c (tmc) 0000 0000 0000 serial mode register (smr) 0000 0000 0000 prescaler s (pss) $000 $000 $000 prescaler w (psw) $00 timer counter a (tca) $00 $00 timer counter b (tcb) $00 $00 $00 timer counter c (tcc) $00 $00 $00 note: ??indicates undefined bits, and ??indicates nonexistent bits. shaded areas indicate that the corresponding register does not exist.
77 table 4-2 (1) initial values of registers and flags on reset and stop mode clear (cont) initial value item hd404344r and hd404394 series hd404318, hd404358 and hd404358r series hd404339 and hd404369 series timer and serial interface timer write register b timer write register c octal counter (twbu, l) (twcu, l) (oc) $x0 $x0 000 $x0 $x0 000 $x0 $x0 000 a/d converter a/d mode register 1 a/d mode register 2 (amr1) (amr2) 0000/000- ---0 0000 --00 0000 -000 a/d channel register (acr) 0000 0000 0000 a/d data register (adru, l) $80 $80 $80 bit registers low speed on flag (lson) 0 direct transfer on flag (dton) 0 watchdog timer on flag (wdon) 0 0 0 a/d start flag (adsf) 0 0 0 input capture status flag (icsf) 0 0 input capture error flag (icef) 0 0 iad off flag (iaof) 0 0 0 others miscellaneous register (mis) 00-- 00-- 0000 system clock selection register 1, bits 2 to 0 (ssr1) 000 system clock selection register 2 (ssr2) --00 note: ??indicates undefined bits, and ??indicates nonexistent bits. shaded areas indicate that the corresponding register does not exist.
78 table 4-2 (2) lists the states of the registers and flags not listed in table 4-2 (1). table 4-2 (2) initial values of registers and flags on reset and stop mode clear stop mode cleared by stopc pin input after other system resets carry accumulator b register w register (ca) (a) (b) (w) the values directly preceding the system reset are not retained. these must be initialized by the user program. the values directly preceding the system reset are not retained. these must be initialized by the user program. x/spx registers (x/spx) y/spy registers (y/spy) serial data register (sru, l) ram the values immediately prior to the point stop mode was entered are retained. port mode register b, bit 3 system clock selection register 1, bit 3 (pmrb3) (ssr13) the values immediately prior to the point stop mode was entered are retained. ram enable flag (rame) 1 0
79 4.5 interrupts 4.5.1 overview there are two classes of sources that can initiate interrupt handling: external interrupts ( int 0 and int 1 ) and requests from built-in peripheral modules. independent vector addresses are allocated to each of these interrupts. table 4-3 lists the interrupts, their priorities, and their vector addresses. when multiple interrupts occur at the same time, the interrupt with the highest priority is processed. table 4-3 interrupts interrupt hd404344r and hd404394 series hd404318, hd404358, hd404358r, hd404339, and hd404369 series vector address priority int 0 int 0 $0002 high * int 1 $0004 * timer a $0006 timer b timer b $0008 timer c timer c $000a a/d converter a/d converter $000c serial interface serial interface $000e low note: * vector addresses $0004 to $0007 are not used in the hd404344r and hd404394 series. these interrupts have the following features. ? all external and internal interrupts are controlled by the interrupt enable flag (ie). that is, no interrupts are accepted when the ie bit is cleared to 0. ? the int 0 and int 1 pin input interrupts are falling edge detection external interrupts.
80 4.5.2 interrupt registers and flags table 4-4 lists the registers and flags that control interrupts. note that the control bits in the interrupt control bit area can only be manipulated with the ram bit manipulation instructions. table 4-4 interrupt control registers address register abbreviation r/w initial value $024 port mode register b pmrb w $0 $000, 0 interrupt enable flag ie r/w 0 $000, 1 $000, 2 $000, 3 reset sp bit external interrupt 0 request flag external interrupt mask interrupt control bit area rsp if0 im0 (w) r/(w) r/w undefined 0 1 $001, 0 external interrupt 1 request flag * if1 r/(w) 0 $001, 1 external interrupt 1 mask * im1 r/w 1 $001, 2 timer a interrupt request flag * ifta r/(w) 0 $001, 3 timer a interrupt mask * imta r/w 1 $002, 0 timer b interrupt request flag iftb r/(w) 0 $002, 1 timer b interrupt mask imtb r/w 1 $002, 2 timer c interrupt request flag iftc r/(w) 0 $002, 3 timer c interrupt mask imtc r/w 1 $003, 0 a/d interrupt request flag ifad r/(w) 0 $003, 1 a/d interrupt mask imad r/w 1 $003, 2 serial interrupt request flag ifs r/(w) 0 $003, 3 serial interrupt mask ims r/w 1 ?w)?indicates that only a write of 0 to clear the flag is possible. note: * applies to the hd404318, hd404358, hd404358r, hd404339, and hd404369 series. these flags cannot be used in the hd404344r and hd404394 series.
81 (1) port mode register b (pmrb: $024): pmrb is a 4-bit write-only register that switches the d port i/o pin shared functions. hd404344r and hd404394 series 0 1 d 4 / stopc 1 0 pmrb0 0 w d 4 i/o pin stopc bit 3? 4 / stopc pin function switch (pmrb3): selects whether the d 4 / stopc pin is used as the d 4 i/o pin or as the stopc input pin. the pmrb3 bit is cleared to 0 on reset. in stop mode, the value of the pmrb3 bit immediately prior to entering stop mode is retained. pmrb3 description 0 the d 4 / stopc stopc stopc bit 0? 0 / int 0 /evnb pin function switch (pmrb0): selects whether the d 0 / int 0 /evnb pin is used as the d 0 i/o pin or as the int 0 /evnb input pin. refer to section 18.2.2, ?imer mode register b2 (tmb2)? for details on switching between the int 0 and evnb functions. the pmrb0 bit is cleared to 0 on reset and in stop mode. pmrb0 description 0 the d 0 / int int int
82 hd404318, hd404358, hd404358r, hd404339, and hd404369 series bit initial value read/write 3 pmrb3 0 w 2 pmrb2 0 w 1 pmrb1 0 w 0 pmrb0 0 w 0 1 d 0 /int 0 pin function switch d 0 i/o pin int 0 input pin 0 1 d 4 / stopc stopc bit 3? 4 / stopc pin function switch (pmrb3): selects whether the d 4 / stopc pin is used as the d 4 i/o pin or as the stopc input pin. the pmrb3 bit is cleared to 0 on reset. in stop mode, the value of the pmrb3 bit immediately prior to entering stop mode is retained. pmrb3 description 0 the d 4 / stopc stopc stopc
83 bit 2? 2 /evnb pin function switch (pmrb2): selects whether the d 2 /evnb pin is used as the d 2 i/o pin or as the evnb input pin. the pmrb2 bit is cleared to 0 on reset. pmrb2 description 0 the d 2 /evnb pin functions as the d 2 i/o pin. (initial value) 1 the d 2 /evnb pin functions as the evnb input pin. bit 1? 1 / int 1 pin function switch (pmrb1): selects whether the d 1 / int 1 pin is used as the d 1 i/o pin or as the int 1 input pin. the pmrb1 bit is cleared to 0 on reset and in stop mode. pmrb1 description 0 the d 1 / int int int bit 0? 0 / int 0 pin function switch (pmrb0): selects whether the d 0 / int 0 pin is used as the d 0 i/o pin or as the int 0 input pin. the pmrb0 bit is cleared to 0 on reset and in stop mode. pmrb0 description 0 the d 0 / int int int (2) interrupt enable flag (ie: $000, 0): the ie flag controls whether the cpu will accept interrupts for all interrupt request types. the ie flag is cleared to 0 by the hardware when an interrupt is accepted and is set to 1 when an rtni instruction is executed. this flag can be read and written by the bit manipulation instructions. this flag is cleared to 0 on reset and in stop mode. ie description 0 the cpu disables all interrupts. (initial value) 1 the cpu accepts interrupts.
84 (3) external interrupt 0 and 1 request flags (if0: $000, 2 , if1: $001, 0*): if0 and if1 are flags that reflect whether an interrupt request is outstanding on the corresponding int 0 and int 1 external interrupt pin. when the specified input edge is detected on an external interrupt pin, the corresponding external interrupt request flag is set to 1. only falling edges are detected on the int 0 and int 1 pins. the if0 and if1 flags can be read and written only by the bit manipulation instructions. however, note that only a 0 may be written. if0 and if1 are never cleared automatically, even when an interrupt is received. they must be cleared to 0 by the software. these flags are cleared to 0 on reset and in stop mode. if0, if1 * description 0 indicates that no interrupt has been requested on the corresponding int int int int * the external interrupt 1 request flag (if1) applies to the hd404318, hd404358, hd404358r, hd404339, and hd404369 series. since there is no int (4) external interrupt 0 and 1 masks (im0: $000, 3, im1: $001, 1*): im0 and im1 are bits that mask the corresponding if0 and if1 flags. the cpu will accept an external interrupt when if0 or if1 is set to 1 only if the corresponding im0 or im1 is cleared to 0 and ie is 1. the cpu will not receive an interrupt request from if0 or if1 if the corresponding im0 or im1 is set to 1. that is, the interrupt will be deferred. im0 and im1 can be read and written only by the bit manipulation instructions. these masks are set to 1 on reset and in stop mode. im0, im1 * description 0 if0 or if1 is enabled. 1 if0 or if1 is masked. the interrupt will be deferred even if either if0 or if1 is set to 1. (initial value) note: * the external interrupt 1 mask (im1) applies to the hd404318, hd404358, hd404358r, hd404339, and hd404369 series. since there is no int
85 (5) timer a to c interrupt request flags (ifta: $001, 2*, iftb: $002, 0, iftc: $002, 2): ifta to iftc are flags that reflect whether an interrupt request is outstanding from the corresponding timer a to c. when one of timers a to c overflows, the corresponding interrupt request flag (ifta to iftc) is set to 1. ifta to iftc can be read and written only by the bit manipulation instructions. however, note that only a 0 may be written. ifta to iftc are never cleared automatically, even when an interrupt is received. they must be cleared to 0 by the software. these flags are cleared to 0 on reset and in stop mode. ifta * to iftc description 0 indicates that no interrupt has been requested by the corresponding timer a to c. (initial value) 1 indicates that an interrupt has been requested by the corresponding timer a to c. note: * the timer a interrupt request flag (ifta) applies to the hd404318, hd404358, hd404358r, hd404339, and hd404369 series. since there is no timer a in hd404344r and hd404394 series products, the ifta flag cannot be used in those products. (6) timer a to c interrupt masks (imta: $001, 3*, imtb: $002, 1, imtc: 002, 3): imta to imtc are bits that mask the corresponding ifta to iftc flags. the cpu will accept a timer interrupt when one of ifta to iftc is set to 1 only if the corresponding imta to imtc is cleared to 0 and ie is 1. if imta to imtc is set to 1, even if the corresponding ifta or iftc is set to 1. that is, the interrupt will be deferred. imta to imtc can be read and written only by the bit manipulation instructions. these masks are set to 1 on reset and in stop mode. imta * to imtc description 0 ifta to iftc are enabled. 1 ifta to iftc are masked. the interrupt will be deferred even if any of ifta to iftc are set to 1. (initial value) note: * the timer a interrupt mask (imta) applies to the hd404318, hd404358, hd404358r, hd404339, and hd404369 series. since there is no timer a in hd404344r and hd404394 series products, the imta mask cannot be used in those products.
86 (7) serial interrupt request flag (ifs: $003, 2): ifs is a bit that reflects whether an interrupt is outstanding from the serial interface. ifs is set to 1 when the serial interface completes a transfer, including forced termination. the ifs flag can be read and written only by the bit manipulation instructions. however, note that only a 0 may be written. ifs is never cleared automatically, even when an interrupt is received. it must be cleared to 0 by the software. this flag is cleared to 0 on reset and in stop mode. ifs description 0 indicates that no interrupt has been requested by the serial interface. (initial value) 1 indicates that an interrupt has been requested by the serial interface. (8) serial interrupt mask (ims: $003, 3): ims is a bit that masks the ifs flag. the cpu will accept a serial interrupt when ifs is set to 1 only if ims is cleared to 0 and ie is 1. the cpu will not receive an interrupt request from ifs if ims is set to 1. that is, the interrupt will be deferred. ims can be read and written only by the bit manipulation instructions. this mask is set to 1 on reset and in stop mode. ims description 0 ifs is enabled. 1 ifs is masked. the interrupt will be deferred even if ifs is set to 1. (initial value)
87 (9) a/d interrupt request flag (ifad: $003, 0): ifad is a bit that reflects whether an a/d interrupt request is outstanding. this bit is set to 1 when the a/d converter completes a conversion. the ifad flag can be read and written only by the bit manipulation instructions. however, note that only a 0 may be written. ifad is never cleared automatically, even when an interrupt is received. it must be cleared to 0 by the software. this flag is cleared to 0 on reset and in stop mode. ifad description 0 indicates that no interrupt has been requested by the a/d converter. (initial value) 1 indicates that an interrupt has been requested by the a/d converter. (10) a/d interrupt mask (imad: $003, 1): imad is a bit that masks the ifad flag. the cpu will accept an a/d interrupt when ifad is set to 1 only if imad is cleared to 0 and ie is 1. the cpu will not receive an interrupt request from ifad if imad is set to 1. that is, the interrupt will be deferred. imad can be read and written only by the bit manipulation instructions. this mask is set to 1 on reset and in stop mode. imad description 0 ifad is enabled. 1 ifad is masked. the interrupt will be deferred even if ifad is set to 1. (initial value)
88 4.5.3 external interrupts there is one external interrupt source, the int 0 pin, in hd404344r and hd404394 series products, and there are two external interrupt sources, the int 0 and int 1 pins, in hd404318, hd404358, hd404358r, hd404339, and hd404369 series products. these external interrupts are generated by falling edges on the corresponding int 0 and int 1 pins. when an external interrupt occurs, the corresponding external interrupt request flag (if0 or if1) is set to 1. these interrupts can be masked or enabled independently by the external interrupt masks im0 and im1. note that all interrupts are masked or enabled by the interrupt enable flag ie. when an external interrupt is accepted, the ie flag is cleared to 0 by the hardware during interrupt handling to disable the acceptance of other interrupts. the int 0 interrupt has higher priority than the int 1 interrupt. refer to table 4-3 for details. 4.5.4 internal interrupts there are four internal interrupt sources from the built-in peripheral modules in the hd404344r and hd404394 series products: timer b, timer c, the a/d converter, and the serial interface. there are five internal interrupt sources from the built-in peripheral modules in the hd404318, hd404358, hd404358r, hd404339, and hd404369 series products: timer a, timer b, timer c, the a/d converter, and the serial interface. when an internal interrupt occurs, the corresponding interrupt request flag (if) is set to 1. these interrupts can be masked or enabled independently by the interrupt masks (im). note that all interrupts are masked or enabled by the interrupt enable flag ie. when an internal interrupt is accepted, the ie flag is cleared to 0 by the hardware during interrupt handling to disable the acceptance of other interrupts. refer to table 4-3 for details on the priority of internal interrupts.
89 4.5.5 interrupt handling sequence interrupts are controlled by the interrupt controller. figure 4-1 shows the block diagram of the interrupt controller, and tables 4-5 (a) and 4-5 (b) list the activation conditions for interrupt handling. figures 4-2 and 4-3 show the flowcharts for the sequences up to the point where an interrupt is accepted. the interrupt handling sequence is described below. 1. when an interrupt occurs and the interrupt request flag (if) is set to 1 in the state where the corresponding interrupt mask (im) is cleared to 0, an interrupt signal is sent to the priority controller. 2. the priority controller selects the interrupt with the highest priority and defers the other interrupts. 3. next the interrupt controller checks the interrupt enable flag (ie). if ie is 1, the highest priority interrupt is accepted, but if ie is 0, all interrupts are deferred. 4. when an interrupt is accepted, the interrupt controller waits for the execution of the current instruction to complete. at that point, the values of the program counter (pc), the carry (ca), and the status (st) are saved on the stack and the stack pointer is decremented by 4. 5. ie is cleared to 0. this disables all interrupts. 6. the interrupt controller generates the vector address corresponding to the accepted interrupt and loads that value into the pc. execution of the interrupt handler starts at the branch destination of the jmpl instruction stored at the vector address. (the user must code a jmpl instruction to the start of the corresponding interrupt handler at each vector address.)
90 $000,0 ie $000,2 if0 $000,3 im0 $001,0 if1 $001,1 im1 $001,2 ifta $001,3 imta $002,0 iftb $002,1 imtb $002,2 iftc $002,3 imtc $003,0 ifad $003,1 imad $003,2 ifs $003,3 ims int 0 interrupt int 1 interrupt timer a interrupt timer b interrupt timer c interrupt a/d interrupt serial interrupt note: items enclosed in the dashed box apply to the hd404318, hd404358, hd404358r, hd404339, and hd404369 series products. the hd404344r and hd404394 series products do not have the int 1 and timer a interrupts. priority controller interrupt request vector address figure 4-1 interrupt controller block diagram
91 table 4-5 (a) interrupt handling activation conditions (hd404344r and hd404394 series) interrupt control bit interrupt source int 0 timer b timer c a/d converter serial interface ie 1111 1 if0 im0 imtb * 100 0 iftc imtc ** 10 0 ifad imad ** * 10 ifs ims **** 1 note: * operation is not influenced by this value, be it 0 or 1. table 4-5 (b) interrupt handling activation conditions (hd404318, hd404358, hd404358r, hd404339, and hd404369 series) interrupt control bit interrupt source int 0 int 1 timer a timer b timer b a/d converter serial interface ie 111111 1 if0 im0 im1 * 10000 0 ifta imta ** 1000 0 iftb imtb *** 100 0 iftc imtc *** * 10 0 ifad imad ***** 10 ifs ims ****** 1 note: * operation is not influenced by this value, be it 0 or 1.
92 no yes ie = 1? pc figure 4-2 interrupt acceptance flowchart
93 1 2 34 56 instruction cycles instruction execution * interrupt acceptance registers pushed on stack, ie reset registers pushed on stack, vector address generation execution of the jmpl instruction at the vector address execution of the instruction at the start of the interrupt routine note: * registers are pushed on the stack and ie is reset after the completion of instruction execution for two cycle instructions also. figure 4-3 interrupt handling sequence
94
95 section 5 low power modes (hd404344r/hd404394/hd404318/hd404358 /hd404358r series) 5.1 overview 5.1.1 features the hd404344r, hd404394, hd404318, hd404358, and hd404358r series support the following two low power modes. ? standby mode ? stop mode table 5-1 lists the methods for switching to and clearing these modes and the clock states. table 5-2 lists the internal states of the cpu and the built-in peripheral modules. table 5-1 operating modes and clock states mode entering procedure system clock oscillator clearing procedure standby mode sby instruction operating ? reset pin input ? interrupt request stop mode stop instruction stopped ? reset pin input ? stopc pin input in stop mode
96 table 5-2 operation in low power modes mode function stop mode standby mode cpu reset maintained ram maintained maintained timer a * reset timer b reset timer c reset serial interface reset a/d converter reset i/o ports reset (high impedance) maintained notes: shaded items operate normally. * applies to the hd404318, hd404358 and hd404358r series. there is no timer a in the hd404344r and hd404394 series.
97 5.1.2 state transition diagram figure 5-1 shows the state transition diagram for the low power modes. rame = 0 rame = 1 f osc : cpu : per : stopc f osc f cyc cpu per reset due to a reset pin input or a watchdog timer overflow reset 1 reset 2 operates stopped f cyc f osc : cpu : per : operates f cyc f cyc f osc : cpu : per : stopped stopped stopped sby instruction standby mode interrupt active mode stop instruction stop mode symbol system clock oscillator f osc /4 cpu operating clock built-in peripheral module operating clock description figure 5-1 state transition diagram 5.1.3 pin functions table 5-3 lists the functions of the pins used to control the low power operating modes. table 5-3 pin functions pin symbol i/o function stop mode clear stopc input stop mode clear
98 5.1.4 registers and flags table 5-4 lists the registers and flags that control the low power operating modes. table 5-4 registers and flags address item abbreviation r/w initial value $024 port mode register b pmrb w $0 $021, 3 ram enable flag rame r/(w) 0 (w): indicates that only a write of 0 to clear the flag is possible. note: the rame flag is allocated in the register flag area and can only be manipulated with the bit manipulation instructions. refer to section 2, ?emory? for details.
99 5.2 register and flag descriptions 5.2.1 port mode register b (pmrb: $024) hd404344r and hd404394 series pmrb is a 2-bit write-only register that switches the functions of the d port pins. the pmrb0 bit is cleared to 0 on reset and in stop mode. the pmrb3 bit is cleared to 0 only on reset. this section describes the pmrb3 bit. refer to the sections titled ?ort mode register b?in sections 7 and 8, ?/o ports? for details on the pmrb0 bit. 0 1 d 4 / stopc pin function switch bit initial value read/write 3 pmrb3 0 w 2 1 0 pmrb0 0 w d 4 i/o pin stopc input pin 0 1 d 0 /int 0 /evnb pin function switch d 0 i/o pin int 0 /evnb input pin unused bit 3? 4 / stopc pin function switch (pmrb3): selects whether the d 4 / stopc pin is used as the d 4 i/o pin or as the stopc input pin. pmrb3 description 0 the d 4 / stopc pin functions as the d 4 i/o pin. (initial value) 1 the d 4 / stopc pin functions as the stopc input pin.
100 hd404318, hd404358 and hd404358r series pmrb is a 4-bit write-only register that switches the functions of the d port pins. the pmrb2 to pmrb0 bits are cleared to 0 on reset and in stop mode. the pmrb3 bit is cleared to 0 only on reset. this section describes the pmrb3 bit. refer to the sections titled ?ort mode register b?in sections 9 and 10, ?/o ports? for details on the pmrb0 to pmrb2 bits. bit initial value read/write 3 pmrb3 0 w 2 pmrb2 0 w 1 pmrb1 0 w 0 pmrb0 0 w 0 1 d 0 /int 0 pin function switch d 0 i/o pin int 0 input pin 0 1 d 4 / stopc pin function switch d 4 i/o pin stopc input pin 0 1 d 2 /evnb pin function switch d 2 i/o pin evnb input pin 0 1 d 1 /int 1 pin function switch d 1 i/o pin int 1 input pin bit 3? 4 / stopc pin function switch (pmrb3): selects whether the d 4 / stopc pin is used as the d 4 i/o pin or as the stopc input pin. the pmrb3 bit is cleared to 0 only on reset. pmrb3 description 0 the d 4 / stopc pin functions as the d 4 i/o pin. (initial value) 1 the d 4 / stopc pin functions as the stopc input pin.
101 5.2.2 ram enable flag (rame: $021, 3) rame reflects whether stop mode was cleared by a reset pin input or by a stopc pin input. in stop mode, the contents of ram directly prior to entering stop mode are maintained, and the contents of ram are maintained both when stop mode is cleared by a stopc pin input and when it is cleared by a reset pin input. however, the contents of ram are maintained only by resets meant to clear stop mode. therefore, to use the previous contents of ram after stop mode is cleared, applications must clear stop mode with a stopc pin input and test the value of the rame flag after switching to active mode. if rame is 1, the contents of ram are guaranteed to have been maintained. although 0 can be written to clear this flag, it cannot be set to 1. this flag is cleared to 0 on reset. rame description 0 indicates the stop mode was not cleared by a stopc pin input. (initial value) 1 indicates the stop mode was cleared by a stopc pin input.
102 5.3 standby mode 5.3.1 entering standby mode standby mode is entered by executing an sby instruction from active mode. in standby mode, the oscillators continue to operate but the clocks related to instruction execution stop. cpu operation stops and the states of registers, ram, and d ports and r ports set to output maintain the values they had prior to standby mode. timers, the serial interface, and other built-in peripheral modules continue to operate. power consumption is lower than in active mode due to the cpu being stopped. 5.3.2 clearing standby mode standby mode can be cleared either by a reset pin input or by an interrupt. (1) clearing with a reset pin input: when the reset pin goes low the system enters the reset state and standby mode is cleared. (2) clearing with an interrupt: standby mode is cleared and the system enters active mode when an interrupt occurs with its corresponding interrupt flag (if) set to 1 and its interrupt mask (im) cleared to 0. after the transition the instruction following the sby instruction is executed. if the interrupt enable flag (ie) is 1, the corresponding interrupt handler will be executed. if ie is 0, the interrupt is deferred and the execution of the immediately preceding instruction sequence continues. figure 5-2 shows the flowchart for the sequence that occurs when low power modes are cleared.
103 reset = 0 stopc = 0 no no yes yes rame = 1 rame = 0 yes yes yes yes yes yes yes yes no no no no no no no reset = 0 if0 im0 = 1 if1 im1 = 1 ifta imta = 1 iftb imtb = 1 iftc imtc = 1 ifad imad = 1 ifs ims = 1 no yes no if = 1 im = 0 ie = 1 * * note: * applies to the hd404318, hd404358 and hd404358r series. since the hd404344r and hd404394 series do not have int 1 or timer a, these interrupts do not occur. stop mode standby mode system clock oscillator started system reset next instruction executed next instruction executed interrupts enabled system clock oscillator started figure 5-2 flowchart for exiting low power modes
104 5.4 stop mode 5.4.1 entering stop mode the system switches to stop mode when a stop instruction is executed in active mode. in stop mode, the contents of ram are maintained and the cpu and all functions of the peripheral modules stop. accordingly, stop mode is the mode with the lowest power consumption of all operating modes. note that the system clock oscillator stops in stop mode. 5.4.2 clearing stop mode stop mode is cleared by an input to either the reset stopc (1) clearing with a reset pin input: when the reset (2) clearing with a stopc pin input: when the stopc reset stopc reset stopc
105 5.4.3 post-stop mode oscillator stabilization period figure 5-3 shows the timing chart for clearing stop mode. be sure to hold the reset stopc ac characteristics in section 25, electrical characteristics , for details. oscillator internal clock stopc or reset stop mode stop instruction executed t res (oscillator stabilization period (t rc ) or longer) figure 5-3 stop mode clear timing 5.5 low power mode operating sequence figure 5-4 shows the low power mode operating sequence. if a stop or sby instruction is executed in the state where the ie flag is cleared, an interrupt flag is set, and the corresponding interrupt mask is cleared, then the stop or sby instruction will be cancelled (treated as a nop) and execution will continue from the next instruction. therefore, before executing a stop or sby instruction, either clear all interrupt flags or mask interrupts.
106 if = 1 im = 0 ie = 0 if = 1 im = 0 stopc = 0 rame = 1 no yes no yes yes no no yes pc ( pc) + 1 pc ( pc) + 1 stop/sby instruction interrupt handling routine hardware nop executed system operation cycle standby mode stop mode hardware nop executed instruction execution system reset note: see figure 5-2, flowchart for exiting low power modes , for details on if and im operation. figure 5-4 low power mode operating sequence
107 section 6 low power modes (hd404339 and hd404369 series) 6.1 overview 6.1.1 features the hd404339 and hd404369 series support the following four low power modes. ? standby mode ? stop mode ? watch mode ? subactive mode table 6-1 lists the methods for switching to and clearing these modes and the clock states in these modes. table 6-2 lists the internal states of the cpu and the built-in peripheral modules. table 6-1 operating modes and clock states state mode entering procedure system clock oscillator subsystem clock oscillator clearing procedure standby mode sby instruction from active mode ? reset pin input ? interrupt request stop mode stop instruction when tma3 = 0 stopped * ? reset pin input ? stopc pin input in stop mode watch mode stop instruction when tma3 = 1 or sby instruction from subactive mode (when either lson is 1 or lson is 0 and dton is 0) stopped ? reset pin input ? timer a or int 0 interrupt request subactive mode a timer a or int 0 interrupt request from watch mode when lson is 1. stopped ? reset pin input ? stop or sby instruction notes: shaded items indicate normal operation. * this oscillator either operates or stops in this mode depending on the setting of ssr13 in the system clock selection register 1 (ssr1).
108 table 6-2 operation in low power modes mode function stop mode watch mode standby mode subactive mode cpu reset maintained maintained ram maintained maintained maintained timer a reset timer b reset stopped timer c reset stopped serial interface reset stopped * a/d converter reset stopped stopped i/o ports reset (high impedance) maintained maintained notes: shaded items operate normally. * in external clock mode data transmission and reception are performed if a clock signal is supplied. however, interrupts are stopped.
109 6.1.2 state transition diagram figure 6-1 shows the state transition diagram for the low power modes. stop instruction stop instruction rame = 0 rame = 1 stopc stopc (tma3 = 0) (tma3 = 1) f osc f x f cyc f w f sub cpu clk per lson dton * 1 * 2 * 3 f osc : f x : cpu : clk : per : standby mode operates operates stopped f cyc f cyc f osc : f x : cpu : clk : per : operates operates stopped f w f cyc f osc : f x : cpu : clk : per : operates operates f cyc f cyc f cyc f osc : f x : cpu : clk : per : operates operates f cyc f w f cyc f osc : f x : cpu : clk : per : stopped operates f sub f w f sub f osc : f x : cpu : clk : per : stopped operates stopped stopped stopped f osc : f x : cpu : clk : per : stopped stopped stopped stopped stopped f osc : f x : cpu : clk : per : stopped operates stopped f w stopped f osc : f x : cpu : clk : per : stopped operates stopped f w stopped (tma3 = 0, ssr13 = 0) (tma3 = 0, ssr13 = 1) (tma3 = 1, lson = 0) (tma3 = 1, lson = 1) reset due to either a reset pin input or the watchdog timer reset 1 reset 2 active mode sby instruction interrupt sby instruction interrupt subactive mode stop instruction stop instruction timer a or int 0 interrupt timer a or int 0 interrupt stop mode watch mode notes: 1. 2. 3. stop/sby instruction (dton=1, lson=0) stop/sby instruction (dton=0, lson=0) stop/sby instruction (dton=, lson=1) symbol description system clock oscillator subsystem clock oscillator f osc /4, f osc /8, f osc /16, or f osc /32 f x /8 f x /8 or f x /4 cpu operating clock timer a operating clock built-in peripheral module operating clock (except timer a) low speed on flag dton flag figure 6-1 state transition diagram
110 6.1.3 pin functions table 6-3 lists the functions of the pins used to control the low power operating modes. table 6-3 pin functions pin symbol i/o function stop mode clear stopc input stop mode clear 6.1.4 registers and flags table 6-4 lists the registers and flags that control the low power operating modes. table 6-4 registers and flags address item abbreviation r/w initial value $00c miscellaneous register mis w $0 $027 system clock selection register 1 ssr1 w $0 $008 timer mode register a tma w $0 $024 port mode register b pmrb w $0 $020, 0 low speed on flag lson r/w 0 $020, 3 dton flag dton r/w 0 $021, 3 ram enable flag rame r/(w) 0 (w): indicates that only a write of 0 to clear the flag is possible. note: control bits in the register flag area can only be manipulated with the bit manipulation instructions. refer to section 2, ?emory? for details.
111 6.2 register and flag descriptions 6.2.1 miscellaneous register (mis: $00c) mis is a 4-bit write-only register that turns the port pull-up mos transistors on or off, turns the r port so pin output buffer pmos transistor on or off, and sets both the oscillator stabilization period time when clearing a low power mode as well as the interrupt frame period for watch and subactive modes. mis is initialized to $0 on reset and in stop mode. this section describes the mis0 and mis1 bits. the mis2 and mis3 bits are described in the ?iscellaneous register?items in section 11 and 12, ?/o ports? mis1 0 1 0 1 0 1 0.24414 ms 15.625 ms 125 ms 0.12207 (0.24414) ms * 7.8125 ms 62.5 ms 0 1 bit initial value read/write 3 mis3 0 w 0 mis0 0 w 2 mis2 0 w 1 mis1 0 w note: * values in parentheses are direct transition time values. r0 2 /so pin output buffer control 0 1 pull-up mos transistor control interrupt frame period and oscillator stabilization period interrupt frame period oscillator stabilization period oscillator circuit conditions external clock ceramic oscillator crystal oscillator unused pmos transistor active (cmos output) pmos transistor off (nmos open drain output) all pull-up mos transistors off pull-up mos transistors active mis0
112 bits 1, 0?nterrupt frame period and oscillator stabilization period (mis1, mis0): these bits set the interrupt frame period (in watch mode and subactive mode) and the oscillator stabilization period when clearing low power modes. the oscillator stabilization period set by the mis1 and mis0 bits must be longer than the oscillator stabilization period (t rc ) for the system clock stipulated in the ac characteristics. mis1 mis0 interrupt frame period (t) * 1 oscillator stabilization period (trc) * 1 oscillator circuit conditions 0 0 0.24414 ms 0.12207 ms (0.24414 ms) * 2 external clock input 1 15.625 ms 7.8125 ms ceramic oscillator 1 0 125 ms 62.5 ms crystal oscillator 1 unused unused notes: 1. these values for t and trc assume a 32.768 khz crystal oscillator connected to pins x1 and x2. 2. values in parentheses are for direct transition from subactive mode to active mode. 6.2.2 system clock selection register 1 (ssr1: $027) ssr1 is a 3-bit write-only register that specifies the system clock oscillator frequency (f osc ) used, sets the divisor for the subsystem clock frequency (f sub ), and sets subsystem clock operation in stop mode. the ssr12 and ssr11 bits are initialized to 0 on reset and in stop mode. the ssr13 bit is initialized to 0 only on reset. this section describes ssr13 and ssr12. the ssr11 bit is described in section 14.2.1, system clock selection register 1 (ssr1) .
113 bit initial value read/write 3 ssr13 0 w 0 2 ssr12 0 w 1 ssr11 0 w 0 1 subsystem clock divisor switch 0 1 system clock selection * 1 unused 0 1 subsystem clock stop setting notes: 1. 2. 3. when the subsystem clock (32.768 khz crystal oscillator) is used, use the ranges 0.4 mhz bit 3?ubsystem clock stop setting (ssr13): this bit selects whether the subsystem clock (32.768 khz oscillator) operates or stops in stop mode. ssr13 description 0 the subsystem clock operates in stop mode (initial value) 1 the subsystem clock stops in stop mode
114 bit 2?ubsystem clock divisor switch (ssr12): this bit sets the divisor for the subsystem clock supplied to the cpu and the built-in peripheral modules in subactive mode. however, note that the divisor for the subsystem clock supplied to prescaler w (psw) is fixed at 8, i.e., f w = f x /8. ssr12 description 0f sub is 1/8 of the subsystem clock oscillator f x , i.e., f sub = f x /8 (initial value) a single cpu instruction cycle takes 244.14 s (when f x = 32.768 khz) 1f sub is 1/4 of the subsystem clock oscillator f x , i.e., f sub = f x /4 a single cpu instruction cycle takes 122.07 s (when f x = 32.768 khz) 6.2.3 timer mode register a (tma: $008) tma is a 4-bit write-only register that sets the timer counter a operating clock and specifies tca clearing and prescaler w (psw) when timer a is used in time base mode. tma is initialized to $0 on reset and in stop mode. this section describes the tma3 bit. the tma2 to tma0 bits are described in section 17.2.1, timer mode register a .
115 tma3 tma2 tma1 tma0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 * 1 pss pss pss pss pss pss pss pss psw psw psw psw psw 2048 t cyc 1024 t cyc 512 t cyc 128 t cyc 32 t cyc 8 t cyc 4 t cyc 2 t cyc 32 t wcyc 16 t wcyc 8 t wcyc 2 t wcyc 1/2 t wcyc unused psw, tca clear bit initial value read/write 3 tma3 0 w 0 tma0 0 w 2 tma2 0 w 1 tma1 0 w timer a clock selection prescaler input clock period mode free-running timer clock time base mode 0 1 0 1 0 1 0 1 0 1 0 0 1 note: * don t care bit 3?rescaler selection (tma3): this bit sets the tca clock source. when psw is used as the clock source, timer a operates in time base mode and generates the interrupt frame timing in watch mode and subactive mode. tma3 description 0 pss is used as the tca clock source. timer a operates as a free-running timer. (initial value) 1 psw is used as the tca clock source. timer a operates as a clock time base. (see section 17.3.2, clock time base operation .)
116 6.2.4 port mode register b (pmrb: $024) pmrb is a 4-bit write-only register that switches the functions of the d port pins. the pmrb2 to pmrb0 bits are cleared to 0 on reset and in stop mode. the pmrb3 bit is cleared to 0 only on reset. this section describes the pmrb3 bit. refer to the sections titled port mode register b in sections 11 and 12, i/o ports , for details on the pmrb2 to pmrb0 bits. bit initial value read/write 3 pmrb3 0 w 2 pmrb2 0 w 1 pmrb1 0 w 0 pmrb0 0 w 0 1 d 0 /int 0 pin function switch d 0 i/o pin int 0 input pin 0 1 d 4 / stopc stopc bit 3? 4 / stopc pin function switch (pmrb3): selects whether the d 4 / stopc stopc pmrb3 description 0 the d 4 / stopc stopc stopc
117 6.2.5 low speed on flag (lson: $020, 0) lson selects whether the system clock ( cpu = per = f cyc ) or the subsystem clock ( cpu = per = f sub ) is taken as the operating clock for the cpu and the built-in peripheral modules other than timer a at operating mode transitions. this bit is used for entering and exiting watch mode and subactive mode, and functions in combination with the dton flag (dton), the tma3 bit, the stop instruction, the sby instruction, the int lson description 0 the system clock is used as the operating clock for the cpu and peripheral modules other than timer a. (initial value) 1 the subsystem clock is used as the operating clock for the cpu and peripheral modules other than timer a. figure 6-2 shows the operating mode transitions that are influenced by lson and dton. tma3 = 1 lson = 0 tma3 = 1 lson = 1 * 1 * 2 active mode stop or sby instruction (dton = 1, lson = 0) subactive mode stop instruction (tma3 = 1, lson = 0) int 0 or timer a interrupt stop or sby instruction (dton = , lson = 1) watch mode int 0 or timer a interrupt notes: 1. 2. stop or sby instruction (dton = 0, lson = 0) stop instruction (tma3 = 1, lson = 1) figure 6-2 mode transitions and the lson and dton flags
118 although the lson flag takes effect as soon as it is written, its read value only becomes valid after a state transition. the figure below gives an example. lson = 1 0 written to lson reading lson returns 1 reading lson returns 0 watch mode subactive mode active mode
119 6.2.6 dton flag (dton: $020, 3) dton controls the direct transition from subactive mode to active mode. this flag can be set to 1 only in subactive mode. this flag is cleared to 0 on reset, in stop mode, and in active mode. dton description 0 when a stop or sby instruction is executed in subactive mode the system switches to watch mode. (initial value) 1 when a stop or sby instruction is executed in subactive mode with lson set to 0, the system switches to active mode. (if lson is 1, the system switches to watch mode.) 6.2.7 ram enable flag (rame: $021, 3) rame reflects whether stop mode was cleared by a reset stopc stopc reset stopc rame description 0 indicates the stop mode was not cleared by a stopc stopc
120 6.3 standby mode 6.3.1 entering standby mode standby mode is entered by executing an sby instruction from active mode. in standby mode, the oscillators continue to operate but the clocks related to instruction execution stop. cpu operation stops and the states of registers, ram, and d ports and r ports set to output maintain the values they had prior to standby mode. timers, the serial interface, and other built-in peripheral modules continue to operate. power consumption is lower than in active mode due to the cpu being stopped. 6.3.2 clearing standby mode standby mode can be cleared either by a reset (1) clearing with a reset pin input: when the reset (2) clearing with an interrupt: standby mode is cleared and the system enters active mode when an interrupt occurs with its corresponding interrupt flag (if) set to 1 and its interrupt mask (im) cleared to 0. after the transition the instruction following the sby instruction is executed. if the interrupt enable flag (ie) is 1, the corresponding interrupt handler will be executed. if ie is 0, the interrupt is deferred and the execution of the immediately preceding instruction sequence continues. figure 6-3 shows the flowchart for the sequence that occurs when low power modes are cleared.
121 reset stopc reset im0 im1 imta imtb imtc imad ims figure 6-3 flowchart for exiting low power modes
122 6.4 stop mode 6.4.1 entering stop mode the system switches to stop mode when a stop instruction is executed when the tma3 bit in tma is cleared to 0. in stop mode, the contents of ram are maintained and the cpu and all functions of the peripheral modules stop. accordingly, stop mode is the mode with the lowest power consumption of all operating modes. note that the system clock oscillator stops in stop mode. also, the ssr13 bit in ssr1 selects whether the subsystem clock operates or stops. 6.4.2 clearing stop mode stop mode is cleared by an input to either the reset stopc (1) clearing with a reset pin input: when the reset (2) clearing with a stopc pin input: when the stopc reset stopc reset stopc
123 6.4.3 post-stop mode oscillator stabilization period figure 6-4 shows the timing chart for clearing stop mode. be sure to hold the reset stopc ac characteristics in section 25, electrical characteristics , for details. oscillator internal clock stopc reset figure 6-4 stop mode clear timing
124 6.5 watch mode 6.5.1 entering watch mode the system switches to watch mode from active when a stop instruction is executed when the tma3 bit in tma is cleared to 1. the system also switches to watch mode from subactive mode when either a stop or sby instruction is executed either with lson set to 1 or with dton cleared to 0. in watch mode the system clock stops but the subsystem clock continues to operate, and timer a operates (in clock time base mode) from the subsystem clock. all other built-in peripheral modules stop. ram and the d and r ports set to output retain their values prior to entering watch mode. power consumption in watch mode is the second lowest, exceeding only that in stop mode. watch mode is convenient when only clock operation is required. 6.5.2 clearing watch mode watch mode can be cleared either by a reset int (1) clearing with a reset pin input: when the reset (2) clearing with an int 0 or timer a interrupt: watch mode is cleared when an int
125 6.5.3 post-watch mode operating timing figure 6-5 shows the operation timing when the system switches to active mode after watch mode is cleared by an int int int figure 6-5 watch mode to active mode transition timing
126 6.6 subactive mode 6.6.1 entering subactive mode the system switches to subactive mode when a timer a or int 6.6.2 clearing subactive mode subactive mode is cleared by executing either a stop or sby instruction. the system will switch to either active mode or watch mode depending on the settings of the lson and dton flags as shown in figure 6-2.
127 6.6.3 system timing when switching directly from subactive mode to active mode the system can switch directly from subactive mode to active mode under control of the dton and lson flags. the procedure is as follows. 1. in subactive mode, set lson to 0 and dton to 1*. 2. execute either a stop or an sby instruction. this procedure will cause the system to switch directly from subactive mode to active mode after an internal processing time plus the time trc specified by the mis register mis1 and mis0 bits, as shown in figure 6-6. note: * dton can be set to 1 only in subactive mode. this flag is always cleared to 0 on reset, in stop mode, and in active mode. (lson set to 0 and dton to 1) stop or sby instruction t: t rc : t d : t d tt rc subactive mode system internal processing time oscillator stabilization period active mode interrupt strobe direct transition complete timing interrupt frame period oscillator stabilization period direct transition time figure 6-6 direct transition timing the time td to switch from subactive mode to active mode is t rc < td < t + t rc , as shown in figure 6-6.
128 6.7 interrupt frame a clock generated by dividing the subsystem clock by 8 is supplied to the timer a and int int int 6.8 low power mode operating sequence figure 6-7 shows the low power mode operating sequence. if a stop or sby instruction is executed in the state where the ie flag is cleared, an interrupt flag is set, and the corresponding interrupt mask is cleared. the stop or sby instruction will then be cancelled (treated as a nop) and execution will continue from the next instruction. therefore, before executing a stop or sby instruction, either clear all interrupt flags or mask interrupts.
129 if = 1 im = 0 ie = 0 if = 1 im = 0 stopc = 0 rame = 1 no yes no yes yes no no yes pc ( ( flowchart for exiting low power modes , for details on if and im operation. figure 6-7 low power mode operating sequence
130 6.9 usage notes interrupts will not be detected correctly if the high level or low level periods in the int int int int int figure 6-8 edge sensing techniques int 0 int 0 (a) high level case (b) low level case interrupt frame point a low point b low interrupt frame point a high point b high figure 6-9 sampling examples
131 section 7 i/o ports (hd404344r series) 7.1 overview 7.1.1 features the hd404344r series i/o ports have the following features. ? the 22 pins in the d and r ports (d 0 to d 5 and the pins in the ports r0 to r3) are all three state cmos i/o pins. of these pins, the ten pins d 1 , d 2 , r1 0 to r1 3 , and r2 0 to r2 3 are high current i/o pins that can each accept a current influx of up to 15 ma. ? certain i/o pins (d 0 , d 4 , and the pins in the ports r 0 and r 3 ) are shared with the built-in peripheral modules, such as timers and the serial interface. setting these pins for use with the built-in peripheral modules takes priority over their setting for use as d or r port pins. ? register settings are used to select input or output for i/o pins and to select the i/o port or peripheral module usage for shared function pins. ? all peripheral module output pins are cmos outputs. however, the r0 2 /so pin can be selected to be an nmos open drain output by setting a register. ? since the system is reset in stop mode, the built-in peripheral module selections are cleared and the i/o pins go to the high impedance state. ? the cmos output pins have built-in programmable pull-up mos transistors. the on/off state of these transistors can be controlled by register settings on an individual basis. note that the pull-up mos transistor on/off settings are independent of the pin settings for use as built-in peripheral module pins. table 7-1 provides an overview of the hd404344r series port functions.
132 table 7-1 port functions port overview pin shared function function switching register d 0 to d 5 d 0 / int 0 /evnb external interrupt input 0/ timer b event input pmrb d 1 d 2 d 3 d 4 / stopc stop mode clear pmrb d 5 r0 r0 0 / sck transfer clock i/o smr r0 1 /si serial reception data input pmra r0 2 /so serial transmission data output r0 3 /toc timer c output r1 r1 0 r1 1 r1 2 r1 3 r2 r2 0 r2 1 r2 2 r2 3 r3 r3 0 /an 0 analog input channel 0 amr1 r3 1 /an 1 analog input channel 1 r3 2 /an 2 analog input channel 2 r3 3 /an 3 analog input channel 3 ? i/o port ? accessed in bit units ? accessed with the sed, sedd, red, redd, td, and tdd instructions. ? programmable pull-up mos transistors ? d 1 and d 2 are high current pins (up to 15 ma) ? i/o ports ? accessed in 4-bit units. ? accessed with the lar, lbr, lra, and lrb instructions. ? programmable pull-up mos transistors ? r1 0 to r1 3 and r2 0 to r2 3 are high current pins (up to 15 ma).
133 7.1.2 i/o control all the d port and r port pins are cmos three state i/o ports. (1) i/o pin circuits: input and output through the d port and r port pins is controlled by the port data registers (pdr) and the data control registers (dcd, dcr). when a bit in a dcd or dcr register is 1, the corresponding pin will function as an output pin and output the value in its pdr. similarly, if a dcd or dcr bit is 0, the corresponding pin will function as an input pin. figure 7-1 shows the i/o pin circuit structure. pull-up mos transistor v cc v cc pmos nmos hlt mis3 dcd, dcr pdr output data input data input control signal notes: 1. 2. since the system is reset in stop mode, the built-in peripheral module selections are cleared. since the internal hlt signal goes to the low (active) level, the i/o pins go to the high impedance state. also, all the pull-up mos transistors are turned off. in all low power modes other than stop mode, the internal hlt signal goes to the high level. figure 7-1 i/o pin circuit structure
134 (2) pull-up mos control: each i/o pin in the d and r ports has a built-in programmable pull- up mos transistor. when the miscellaneous register (mis) mis3 bit is set to 1 the pull-up mos transistor for pins for which the corresponding pdr is set to 1 will be turned on. thus the on/off state of each pin can be controlled independently by the pdrs. note that the pull-up mos transistor on/off settings are independent of the pin settings for use as built-in peripheral module pins. table 7-2 shows how register settings control the port i/o pins. table 7-2 register settings for i/o pin control mis3 0 1 dcd, dcr 0101 pdr 01010101 cmos pmos on on buffer nmos on on pull-up mos transistor on on notes: 1. : off 2. the pdr registers are not allocated addresses in ram. the pdr registers are accessed by special-purpose i/o instructions.
135 (3) miscellaneous register (mis: $00c): mis is a 2-bit write-only register that controls the on/off states of the d and r port pin pull-up mos transistors and the on/off state of the r0 2 /so pin output buffer pmos transistor. mis is initialized to $0 on reset and in stop mode. bit initial value read/write 3 mis3 0 w 0 2 mis2 0 w 1 0 1 r0 2 /so pin output buffer control unused 0 1 pull-up mos transistor control pmos transistor active (cmos output) pmos transistor off (nmos open drain output) all pull-up mos transistors off pull-up mos transistors active bit 3?ull-up mos transistor control (mis3): controls the on/off states of the pull-up mos transistors built into the i/o port pins. mis3 description 0 all pull-up mos transistors will be turned off. (initial value) 1 pull-up mos transistors for which the corresponding pdr bit is 1 will be turned on. bit 2?0 2 /so pin output buffer control (mis2): controls the on/off state of the r0 2 /so pin output buffer pmos transistor. mis2 description 0 the r0 2 /so pin output will be a cmos output. (initial value) 1 the r0 2 /so pin output will be an nmos open drain output.
136 7.1.3 i/o pin circuit structures table 7-3 shows the port and peripheral module pin circuits. table 7-3 input and output pin circuits class circuit applicable pins standard voltage pins i/o pins pull-up control signal buffer control signal output data input control signal input data v cc v cc hlt mis3 dcd, dcr pdr d 0 to d 5 , r0 0 , r0 1 , r0 3 , r1 0 to r1 3 , r2 0 to r2 3 , r3 0 to r3 3 v cc v cc hlt mis3 dcr pdr mis2 pull-up control signal buffer control signal output data input control signal input data r0 2
137 table 7-3 input and output pin circuits (cont) class circuit applicable pins standard voltage pins built-in peripheral module pins i/o pins v cc v cc hlt mis3 sck sck pull-up control signal output data input data sck output pins v cc v cc hlt mis3 so mis2 pull-up control signal pmos control signal output data so v cc v cc hlt mis3 toc pull-up control signal output data toc
138 table 7-3 input and output pin circuits (cont) class circuit applicable pins standard voltage pins built-in peripheral module pins input pins si, int 0 /evnb, stopc v cc hlt mis3 pdr input data si, int 0 /evnb, stopc v cc hlt mis3 pdr input control a/d input an 0 to an 3
139 7.1.4 port states in low power modes the d 0 and d 4 pins and the r0 and r3 port pins have shared functions as input or output pins for built-in peripheral modules. in standby mode, since the cpu stops, the pins selected as output ports maintain their immediately prior output values. also, pins selected for use by built-in peripheral modules that operate in standby mode continue to operate. (output pins used by modules that stop in standby mode maintain their immediately prior output values.) see section 5, ?ow power modes? for details on which built-in peripheral modules can operate in each mode. table 7-4 lists the port states in the low power modes. table 7-4 port states in low power modes low power mode port states standby mode pins maintain their values immediately prior to entering standby mode. stop mode built-in peripheral function selections are cleared, and the port and peripheral function i/o pins go to the high impedance state. 7.1.5 handling unused pins i/o pins that are unused in user systems must be tied to a fixed potential, since floating i/o pins can cause noise that can interfere with lsi operation. the built-in pull-up mos transistors can be used to pull up unused pins to vcc. alternatively, unused pins can be pulled up to v cc with external resistors of about 100 k ? . application programs should maintain the pdr and dcr contents for unused pins at their reset state values. also note that unused pins must not be selected for use as peripheral function i/o pins.
140 7.2 d port 7.2.1 overview the d port is a 6-pin i/o port (d 0 to d 5 , where d 1 and d 2 are high current pins that can each accept a current influx of up to 15 ma) that can be accessed in 1-bit units. the output levels on the pins d 0 to d 5 can be set to low or high by accessing the port in one-bit units with the sed, sedd, red, and redd output instructions. the output data is stored in the pdr for each pin. the level on each of the pins d0 to d5 can be tested in one-bit units with the td and tdd input instructions. the dcd registers are used to turn the d port output buffers on or off. when the dcd bit corresponding to a given pin is 1, the data in the corresponding pdr will be output from that pin. the on/off states of the output buffers can be controlled individually for each d port pin. the dcd registers are allocated in the ram address space. the pins d 0 and d 4 have shared functions as built-in peripheral module pins. pmrb is used to switch these functions. figure 7-2 shows the structure of the d port. d port d 0 /int 0 /evnb (i/o, input, or input) d 1 (i/o) d 2 (i/o) d 3 (i/o) d 4 / stopc (i/o or input) d 5 (i/o) : high current pins figure 7-2 d port structure
141 7.2.2 register configuration and descriptions table 7-5 shows the configuration of the d port registers. table 7-5 d port register configuration address register symbol r/w initial value port data registers pdr w * 1 $02c data control registers dcd0 w $0 $02d dcd1 w --00 $024 port mode register b pmrb w 0--0 note: * the sed, sedd, red, and redd instructions can be used to write to the pdrs. (1) port data registers (pdr): each of the i/o pins d 0 to d 5 includes a built-in pdr. when a sed or sedd instruction is executed for one of the pins d 0 to d 5 the corresponding pdr is set to 1, and when a red or redd instruction is executed, the corresponding pdr is cleared to 0. when a bit corresponding to a d port pin in dcd0 or dcd1 is 1, the corresponding output buffer is turned on and the value of the corresponding pdr will be output from that pin. the pdr registers are set to 1 on reset and in stop mode. (2) data control registers (dcd0, dcd1: $02c, $02d) dcd0: $02c dcd1: $02d bit initial value read/write 3 dcd03 0 w 0 dcd00 0 w 2 dcd02 0 w 1 dcd01 0 w bit initial value read/write 3 0 dcd10 0 w 2 1 dcd11 0 w bits in dcd0 and dcd1 description 0 the cmos output buffer is turned off and the output goes to the high impedance state. (initial value) 1 the output buffer is turned on and the value in the corresponding pdr is output.
142 the bits in dcd0 and dcd1 correspond to the d port pins as shown in the table. bit register bit 3 bit 2 bit 1 bit 0 dcd0 d 3 d 2 d 1 d 0 dcd1 d 5 d 4 (3) port mode register b (pmrb: $024): pmrb is a 2-bit write-only register that switches the d port i/o pin shared functions. bit initial value read/write 3 pmrb3 0 w 0 pmrb0 0 w 2 1 0 1 d 0 /int 0 /evnb pin function switch 0 1 d 4 / stopc pin function switch d 0 i/o pin int 0 /evnb input pin d 4 i/o pin stopc input pin unused bit 3? 4 / stopc pin function switch (pmrb3): selects whether the d 4 / stopc pin is used as the d 4 i/o pin or as the stop mode clear pin ( stopc ). pmrb3 description 0 the d 4 / stopc pin functions as the d 4 i/o pin. (initial value) 1 the d 4 / stopc pin functions as the stopc input pin. bit 0? 0 / int 0 /evnb pin function switch (pmrb0): selects whether the d 0 / int 0 /evnb pin is used as the d 0 i/o pin or as the int 0 /evnb input pin. pmrb0 description 0 the d 0 / int 0 /evnb pin functions as the d 0 i/o pin. (initial value) 1 the d 0 / int 0 /evnb pin functions as the int 0 /evnb input pin. refer to section 18.2.2, ?imer mode register b2 (tmb2)? for details on switching between the int 0 and evnb functions.
143 7.2.3 pin functions the functions of the pins d 0 to d 5 are switched by register settings as shown in table 7-6. table 7-6 d port pin functions pin pin functions and selection methods d 0 / int 0 /evnb the pin function is switched as shown below by the pmrb pmrb0 bit and the dcd0 dcd00 bit. pmrb0 0 1 dcd00 0 1 pin function d 0 input pin d 0 output pin int 0 /evnb input pin * note: * to use this pin as the evnb pin, mask the int 0 interrupt by setting the int 0 interrupt mask (im0: $000,3) to 1. d 1 the pin function is switched as shown below by the dcd0 dcd01 bit. dcd01 0 1 pin function d 1 input pin d 1 output pin d 2 the pin function is switched as shown below by the dcd0 dcd02 bit. dcd02 0 1 pin function d 2 input pin d 2 output pin d 3 the pin function is switched as shown below by the dcd0 dcd03 bit. dcd03 0 1 pin function d 3 input pin d 3 output pin d 4 / stopc the pin function is switched as shown below by the pmrb pmrb3 bit and the dcd1 dcd10 bit. pmrb3 0 1 dcd10 0 1 pin function d 4 input pin d 4 output pin stopc input pin d 5 the pin function is switched as shown below by the dcd1 dcd11 bit. dcd11 0 1 pin function d 5 input pin d 5 output pin
144 7.3 r ports 7.3.1 overview the r port consists of the four 4-bit i/o ports r0 to r3. these ports are accessed in 4-bit units. the individual ports r0 to r3 are accessed in 4-bit units with the lra and lrb output instructions to control the output levels (high or low) on each pin. output data is stored in the pdr built into each pin. similarly, the lar and lbr input instructions can be used to access the r ports in 4-bit units to read the input levels on the port pins. dcr registers are used to control the port r0 to r3 output buffer on/off states. when the dcr bit corresponding to a pin in one of the ports r0 to r3 is set to 1, the data in the corresponding pdr is output from that pin. thus the output buffer on/off states can be controlled on an individual pin basis for the r port pins. the dcr registers are allocated in the ram address space. the pins in ports r1 and r2 are high current pins that can accept current influxes of up to 15 ma. the r0 and r3 port pins have shared functions as built-in peripheral module pins. register settings are used to switch these functions. (see table 7-7.) figure 7-3 shows the r port pin structure. r0 port r2 port r0 0 / sck (i/o or i/o) r0 1 /si (i/o or input) r0 2 /so (i/o or output) r0 3 /toc (i/o or output) r1 port r3 port r2 0 (i/o) r2 1 (i/o) r2 2 (i/o) r2 3 (i/o) r1 0 (i/o) r1 1 (i/o) r1 2 (i/o) r1 3 (i/o) r3 0 /an 0 (i/o or input) r3 1 /an 1 (i/o or input) r3 2 /an 2 (i/o or input) r3 3 /an 3 (i/o or input) : high current pins figure 7-3 r port circuit
145 7.3.2 register configuration and descriptions table 7-7 shows the configuration of the r port related registers. table 7-7 r port register configuration address register symbol r/w initial value port data registers pdr w * 1 $030 data control registers dcr0 w $0 $031 dcr1 w $0 $032 dcr2 w $0 $033 dcr3 w $0 $004 port mode register a pmra w $0 $005 serial mode register smr w $0 $019 a/d mode register 1 amr1 w $0 note: * the lra and lrb instructions are used to write to the pdr registers. (1) port data registers (pdr): all the i/o pins in ports r0 to r3 include a pdr that holds the output data. when an lra or an lrb instruction is executed for one of ports r0 to r3, the contents of the accumulator (a) or the b register (b) are transferred to the specified r port pdrs. when the corresponding bit in dcr0 to dcr3 for the specified port is 1, the output buffers for the corresponding pins will be turned on and the values in the pdrs will be output from the pins. the pdr registers are set to 1 on reset and in stop mode.
146 (2) data control registers (dcr0 to dcr3: $030, $031, $032, $033) dcr0: $030 dcr1: $031 dcr2: $032 dcr3: $033 bit initial value read/write 3 dcr03 0 w 0 dcr00 0 w 2 dcr02 0 w 1 dcr01 0 w bit initial value read/write 3 dcr13 0 w 0 dcr10 0 w 2 dcr12 0 w 1 dcr11 0 w bit initial value read/write 3 dcr23 0 w 0 dcr20 0 w 2 dcr22 0 w 1 dcr21 0 w bit initial value read/write 3 dcr33 0 w 0 dcr30 0 w 2 dcr32 0 w 1 dcr31 0 w bits in dcr0 to dcr3 description 0 the output buffer (cmos buffer) is turned off and the output goes to the high impedance state. (initial value) 1 the output buffer is turned on and the corresponding pdr value is output. the table below lists the correspondence between the bits in dcr0 to dcr3 and the port r0 to r3 pins. bit register bit 3 bit 2 bit 1 bit 0 dcr0 r0 3 r0 2 r0 1 r0 0 dcr1 r1 3 r1 2 r1 1 r1 0 dcr2 r2 3 r2 2 r2 1 r2 0 dcr3 r3 3 r3 2 r3 1 r3 0
147 (3) port mode register a (pmra: $004): pmra is a 3-bit write-only register whose bits pmra2 to pmra0 switch the functions of the port r0 shared function pins. bit initial value read/write 3 0 pmra0 0 w 2 pmra2 0 w 1 pmra1 0 w 0 1 r0 3 /toc pin function switch 0 1 r0 1 /si pin function switch 0 1 r0 2 /so pin function switch r0 3 i/o pin toc output pin r0 1 i/o pin si input pin r0 2 i/o pin so output pin unused bit 2?0 3 /toc pin function switch (pmra2): selects whether the r0 3 /toc pin functions as the r0 3 i/o pin or as the timer c output pin (toc). pmra2 description 0 the r0 3 /toc pin functions as the r0 3 i/o pin. (initial value) 1 the r0 3 /toc pin functions as the toc output pin. bit 1?0 1 /si pin function switch (pmra1): selects whether the r0 1 /si pin functions as the r0 1 i/o pin or as the serial reception data input pin (si). pmra1 description 0 the r0 1 /si pin functions as the r0 1 i/o pin. (initial value) 1 the r0 1 /si pin functions as the si input pin.
148 bit 0?0 2 /so pin function switch (pmra0): selects whether the r0 2 /so pin functions as the r0 2 i/o pin or as the serial transmission data output pin (so). pmra0 description 0 the r0 2 /so pin functions as the r0 2 i/o pin. (initial value) 1 the r0 2 /so pin functions as the so output pin. (4) serial mode register (smr: $005): smr is a 4-bit write-only register whose smr3 bit switches the r0 0 / sck pin function. this section only describes the smr3 bit. see section 20.2.1, ?erial mode register (smr)?for details on bits smr2 to smr0. bit initial value read/write 3 smr3 0 w 0 smr0 0 w 2 smr2 0 w 1 smr1 0 w transfer clock selection 0 1 r0 0 / sck pin function switch r0 0 i/o pin sck i/o pin bit 3?0 0 / sck pin function switch (smr3): selects whether the r0 0 / sck pin functions as the r0 0 i/o pin or as the serial interface transfer clock i/o pin. smr3 description 0 the r0 0 / sck pin functions as the r0 0 i/o pin. (initial value) 1 the r0 0 / sck pin functions as the sck i/o pin.
149 (5) a/d mode register 1 (amr1: $019): amr1 is a 4-bit write-only register that switches the functions of the r3 port shared function pins. bit initial value read/write 3 amr13 0 w 0 amr10 0 w 2 amr12 0 w 1 amr11 0 w 0 1 r3 2 /an 2 pin function switch 0 1 r3 1 /an 1 pin function switch 0 1 r3 0 /an 0 pin function switch 0 1 r3 3 /an 3 pin function switch r3 2 i/o pin an 2 input pin r3 1 i/o pin an 1 input pin r3 0 i/o pin an 0 input pin r3 3 i/o pin an 3 input pin bit 3?3 3 /an 3 pin function switch (amr13): selects whether the r3 3 /an 3 pin functions as the r3 3 i/o pin or as the a/d converter channel 3 input pin an 3 . amr13 description 0 the r3 3 /an 3 pin functions as the r3 3 i/o pin. (initial value) 1 the r3 3 /an 3 pin functions as the an 3 input pin. bit 2?3 2 /an 2 pin function switch (amr12): selects whether the r3 2 /an 2 pin functions as the r3 2 i/o pin or as the a/d converter channel 2 input pin an 2 . amr12 description 0 the r3 2 /an 2 pin functions as the r3 2 i/o pin. (initial value) 1 the r3 2 /an 2 pin functions as the an 2 input pin.
150 bit 1?3 1 /an 1 pin function switch (amr11): selects whether the r3 1 /an 1 pin functions as the r3 1 i/o pin or as the a/d converter channel 1 input pin an 1 . amr11 description 0 the r3 1 /an 1 pin functions as the r3 1 i/o pin. (initial value) 1 the r3 1 /an 1 pin functions as the an 1 input pin. bit 0?3 0 /an 0 pin function switch (amr10): selects whether the r3 0 /an 0 pin functions as the r3 0 i/o pin or as the a/d converter channel 0 input pin an 0 . amr10 description 0 the r3 0 /an 0 pin functions as the r3 0 i/o pin. (initial value) 1 the r3 0 /an 0 pin functions as the an 0 input pin.
151 7.3.3 pin functions the pin functions of the r port pins are switched by register settings as shown in table 7-8. table 7-8 r port pin functions pin pin functions and selection methods r0 0 / sck the pin function is switched by the smr smr3 bit and the dcr0 dcr00 bit as shown below. smr3 0 1 dcr00 0 1 pin function r0 0 input pin r0 0 output pin sck i/o pin r0 1 /si the pin function is switched by the pmra pmra1 bit and the dcr0 dcr01 bit as shown below. pmra1 0 1 dcr01 0 1 pin function r0 1 input pin r0 1 output pin si input pin r0 2 /so the pin function is switched by the pmra pmra0 bit and the dcr0 dcr02 bit as shown below. pmra0 0 1 dcr02 0 1 pin function r0 2 input pin r0 2 output pin so output pin r0 3 /toc the pin function is switched by the pmra pmra2 bit and the dcr0 dcr03 bit as shown below. pmra2 0 1 dcr03 0 1 pin function r0 3 input pin r0 3 output pin toc output pin
152 table 7-8 r port pin functions (cont) pin pin functions and selection methods r1 0 the pin function is switched by the dcr1 dcr10 bit as shown below. dcr10 0 1 pin function r1 0 input pin r1 0 output pin r1 1 the pin function is switched by the dcr1 dcr11 bit as shown below. dcr11 0 1 pin function r1 1 input pin r1 1 output pin r1 2 the pin function is switched by the dcr1 dcr12 bit as shown below. dcr12 0 1 pin function r1 2 input pin r1 2 output pin r1 3 the pin function is switched by the dcr1 dcr13 bit as shown below. dcr13 0 1 pin function r1 3 input pin r1 3 output pin r2 0 the pin function is switched by the dcr2 dcr20 bit as shown below. dcr20 0 1 pin function r2 0 input pin r2 0 output pin r2 1 the pin function is switched by the dcr2 dcr21 bit as shown below. dcr21 0 1 pin function r2 1 input pin r2 1 output pin r2 2 the pin function is switched by the dcr2 dcr22 bit as shown below. dcr22 0 1 pin function r2 2 input pin r2 2 output pin r2 3 the pin function is switched by the dcr2 dcr23 bit as shown below. dcr23 0 1 pin function r2 3 input pin r2 3 output pin
153 table 7-8 r port pin functions (cont) pin pin functions and selection methods r3 0 /an 0 the pin function is switched by the amr1 amr10 bit and the dcr3 dcr30 bit as shown below. amr10 0 1 dcr30 0 1 pin function r3 0 input pin r3 0 output pin an 0 input pin r3 1 /an 1 the pin function is switched by the amr1 amr11 bit and the dcr3 dcr31 bit as shown below. amr11 0 1 dcr31 0 1 pin function r3 1 input pin r3 1 output pin an 1 input pin r3 2 /an 2 the pin function is switched by the amr1 amr12 bit and the dcr3 dcr32 bit as shown below. amr12 0 1 dcr32 0 1 pin function r3 2 input pin r3 2 output pin an 2 input pin r3 3 /an 3 the pin function is switched by the amr1 amr13 bit and the dcr3 dcr33 bit as shown below. amr13 0 1 dcr33 0 1 pin function r3 3 input pin r3 3 output pin an 3 input pin
154 7.4 usage notes keep the following points in mind when using the i/o ports. ? when the mis mis2 bit is set to 1, the r0 2 /so pin will be an nmos open drain output regardless of whether it is selected for use as the r0 2 pin or as the so pin by the pmra pmra0 bit. ? i/o pins that are unused in user systems must be tied to a fixed potential, since floating i/o pins can cause noise that can interfere with lsi operation. the built-in pull-up mos transistors can be used to pull up unused pins to v cc . alternatively, unused pins can be pulled up to v cc with external resistors of about 100 k ? . application programs should maintain the pdr and dcr contents for unused pins at their reset state values. also note that unused pins must not be selected for use as peripheral function i/o pins. ? when the mis mis3 bit is set to 1 (pull-up mos transistors active) and the pdr for an r port/analog input shared function pin has the value 1, the mos transistor for the corresponding pin will not be turned off by selecting the analog input function with the amr1 register. to use an r port/analog input shared function pin as an analog input when the pull-up mos transistors are active, always clear the pdr for the corresponding pin to 0 first and then turn off the pull-up mos transistor. (note that the pdr registers are set to 1 immediately following a reset.) figure 7-4 shows the circuit for the r port/analog input shared function pins. amr1 is used to set the port outputs to high impedance. acr is used to switch the analog input channel. the states of the r port/analog input shared function pins are set, as shown in table 7-9, by the combination of the amr1 register, the mis3 bit, the dcr, and the pdr settings.
155 v cc v cc hlt mis3 dcr pdr amr (a/d mode register setting value) acr (a/d channel register setting value) pull-up control signal buffer control signal output data input control signal input data a/d input figure 7-4 r port/analog input shared function pin circuit structure table 7-9 program control of the r port/analog input shared function pins corresponding bit in amr1 0 (r port selected) mis3 bit 0 1 dcr 0101 pdr 01010101 cmos buffer pmos on on nmos on on pull-up mos transistor on on note: : off corresponding bit in amr1 1 (analog input selected) mis3 bit 0 1 dcr 0101 pdr 01010101 cmos buffer pmos nmos pull-up mos transistor on on note: : off
156
157 section 8 i/o ports (hd404394 series) 8.1 overview 8.1.1 features the hd404394 series i/o ports have the following features. ? the hd404394 series microcomputers have a total of 21 i/o pins, of which the three pins r1 0 to r1 2 are medium voltage nmos open drain i/o pins. the five pins r1 3 and r2 0 to r2 3 are standard voltage nmos open drain i/o pins. the remaining 13 pins, d 0 to d 5 , r0 0 to r0 3 , and r3 1 to r3 3 , are three state cmos i/o pins. of these pins, the pins d 1 , d 2 , and the r 1 and r 2 port pins are high current i/o pins that can each accept a current influx of up to 15 ma. ? certain i/o pins (d 0 , d 4 , and the pins in the ports r0 and r3) are shared with the built-in peripheral modules, such as timers and the serial interface. setting these pins for use with the built-in peripheral modules takes priority over their setting for use as d or r port pins. ? register settings are used to select input or output for i/o pins and to select the i/o port or peripheral module usage for shared function pins. ? all peripheral module output pins are cmos outputs. however, the r0 2 /so pin can be selected to be an nmos open drain output by setting a register. ? since the system is reset in stop mode, the built-in peripheral module selections are cleared and the i/o pins go to the high impedance state. ? the cmos output pins have built-in programmable pull-up mos transistors. the on/off state of these transistors can be controlled by register settings on an individual basis. note that the pull-up mos transistor on/off settings are independent of the pin settings for use as built-in peripheral module pins. table 8-1 provides an overview of the hd404394 series port functions.
158 table 8-1 port functions port overview pin shared function function switching register d 0 to d 5 d 0 / int 0 /evnb external interrupt input 0/ timer b event input pmrb d 1 d 2 d 3 d 4 / stopc stop mode clear pmrb d 5 r0 r0 0 / sck transfer clock i/o smr r0 1 /si serial reception data input pmra r0 2 /so serial transmission data output r0 3 /toc timer c output r1 r1 0 r1 1 r1 2 r1 3 r2 r2 0 r2 1 r2 2 r2 3 r3 r3 1 /an 1 analog input channel 1 amr1 r3 2 /an 2 analog input channel 2 r3 3 /an 3 analog input channel 3 ? i/o port ? accessed in bit units ? accessed with the sed, sedd, red, redd, td, and tdd instructions. ? programmable pull-up mos transistors ? d 1 and d 2 are high current pins (up to 15 ma) ? i/o ports ? accessed in 4-bit units ? accessed with the lar, lbr, lra, and lrb instructions. ? the standard i/o pins (r0 0 to r0 3 and r3 1 to r3 3 ) have programmable pull-up mos transistors. ? r1 0 to r1 2 are medium voltage nmos open drain i/o pins. ? r1 3 and r2 0 to r2 3 are standard voltage nmos open drain i/o pins. ? r1 0 to r1 3 and r2 0 to r2 3 are high current pins (up to 15 ma).
159 8.1.2 i/o control r1 0 to r1 2 are medium voltage nmos open drain i/o ports, r1 3 and the r 2 port are standard voltage nmos open drain i/o ports, and the d port and the r0 and r3 port pins are cmos three state i/o ports. the different port types have different circuit structures as follows. (1) medium voltage nmos open drain i/o pin circuit: r1 0 to r1 2 are medium voltage nmos open drain i/o ports. i/o through these ports is controlled by the port data registers (pdr) and the data control registers (dcr). when the dcr bit corresponding to a given pin is 1, that pin functions as an output pin and when the value in the pdr is 0, the nmos transistor will turn on and the pin will output a low level voltage. when the pdr is 1, the pin will go to the high impedance state. when a given dcr bit is 0, the corresponding pin will function as an input pin. (2) standard voltage nmos open drain i/o pin circuit: r1 3 and r2 0 to r2 3 are standard voltage nmos open drain i/o ports. i/o through these ports is controlled by the pdr and dcr registers. when the dcr bit corresponding to a given pin is 1, that pin functions as an output pin and when the value in the pdr is 0, the nmos transistor will turn on and the pin will output a low level voltage. when the pdr is 1, the pin will go to the high impedance state. when a given dcr bit is 0, the corresponding pin will function as an input pin. (3) standard voltage cmos three state i/o pin circuit: the d, r0 and r3 ports are standard voltage cmos three state i/o ports. i/o is controlled by the pdr registers and the data control registers (dcd, dcr). when a bit in a dcd or dcr register is 1, the corresponding pin will function as an output pin and output the value in its pdr. similarly, if a dcd or dcr bit is 0, the corresponding pin will function as an input pin.
160 (4) pull-up mos control: each i/o pin in the d, r0, and r3 ports has a built-in programmable pull-up mos transistor. when the miscellaneous register (mis) mis3 bit is set to 1 the pull-up mos transistor for pins for which the corresponding pdr is set to 1 will be turned on. thus the on/off state of each pin can be controlled independently by the pdrs. note that the pull-up mos transistor on/off settings are independent of the pin settings for use as built-in peripheral module pins. table 8-2 shows how register settings control the port i/o pins. table 8-2 register settings for i/o pin control mis3 0 1 dcd, dcr 0101 pdr 01010101 cmos buffer pmos on on nmos on on pull-up mos transistor on on notes: 1. ? off 2. the pdr registers are not allocated addresses in ram. the pdr registers are accessed by special-purpose i/o instructions.
161 (5) miscellaneous register (mis: $00c): mis is a 2-bit write-only register that controls the on/off states of the d, r0, and r3 port pin pull-up mos transistors and the on/off state of the r0 2 /so pin output buffer pmos transistor. mis is initialized to $0 on reset and in stop mode. bit initial value read/write 3 mis3 0 w 0 2 mis2 0 w 1 0 1 r0 2 /so pin output buffer control unused 0 1 pull-up mos transistor control pmos transistor active (cmos output) pmos transistor off (nmos open drain output) all pull-up mos transistors off pull-up mos transistors active bit 3?ull-up mos transistor control (mis3): controls the on/off states of the pull-up mos transistors built into the i/o port pins. mis3 description 0 all pull-up mos transistors will be turned off. (initial value) 1 pull-up mos transistors for which the corresponding pdr bit is 1 will be turned on. bit 2?0 2 /so pin output buffer control (mis2): controls the on/off state of the r0 2 /so pin output buffer pmos transistor. mis2 description 0 the r0 2 /so pin output will be a cmos output. (initial value) 1 the r0 2 /so pin output will be an nmos open drain output.
162 8.1.3 i/o pin circuit structures table 8-3 shows the port and peripheral module pin circuits. notes: 1. since the system is reset in stop mode, the built-in peripheral module selections are cleared. since the internal hlt signal goes to the low (active) level, the i/o pins go to the high impedance state. also, all the pull-up mos transistors are turned off. 2. in all low power modes other than stop mode, the internal hlt signal goes to the high level. table 8-3 input and output pin circuits class circuit applicable pins standard voltage pins i/o pins v cc v cc hlt mis3 dcd, dcr pdr pull-up control signal buffer control signal output data input control signal input data d 0 to d 5 , r0 0 , r0 1 , r0 3 , r3 1 to r3 3 pdr hlt dcr buffer control signal input control signal output data input data r1 3 , r2 0 to r2 3
163 table 8-3 input and output pin circuits (cont) class circuit applicable pins standard voltage pins i/o pins v cc v cc hlt mis3 dcr pdr mis2 pull-up control signal buffer control signal output data input control signal input data r0 2 medium voltage pins pdr dcr hlt buffer control signal output data input control signal input data r1 0 to r1 2
164 table 8-3 input and output pin circuits (cont) class circuit applicable pins standard voltage pins standard peripheral module pins i/o pins v cc v cc hlt mis3 sck sck pull-up control signal output data input data sck output pins v cc v cc hlt mis3 so mis2 pull-up control signal pmos control signal output data so v cc v cc hlt mis3 toc pull-up control signal output data toc
165 table 8-3 input and output pin circuits (cont) class circuit applicable pins standard voltage pins built-in peripheral module pins input pins si, int 0 /evnb, stopc v cc hlt mis3 pdr input data si, int 0 /evnb, stopc v cc hlt mis3 pdr input control a/d input an 1 to an 3
166 8.1.4 port states in low power modes the d 0 and d 4 pins and the r0 and r3 port pins have shared functions as input or output pins for built-in peripheral modules. in standby mode, since the cpu stops, the pins selected as output ports maintain their immediately prior output values. also, pins selected for use by built-in peripheral modules that operate in standby mode continue to operate. (output pins used by modules that stop in standby mode maintain their immediately prior output values.) see section 5, ?ow power modes? for details on which built-in peripheral modules can operate in each mode. table 8-4 lists the port states in the low power modes. table 8-4 port states in low power modes low power mode port states standby mode pins maintain their values immediately prior to entering standby mode. stop mode built-in peripheral function selections are cleared, and the port and peripheral function i/o pins go to the high impedance state. 8.1.5 handling unused pins i/o pins that are unused in user systems must be tied to a fixed potential, since floating i/o pins can cause noise that can interfere with lsi operation. the built-in pull-up mos transistors can be used to pull up unused pins to v cc . alternatively, unused pins can be pulled up to v cc with external resistors of about 100 k ? . application programs should maintain the pdr, dcd and dcr contents for unused pins at their reset state values. alternatively, unused pins can be selected for use as peripheral function i/o pins.
167 8.2 d port 8.2.1 overview the d port is a 6-pin i/o port (d 0 to d 5 , where d 1 and d 2 are high current pins that can each accept a current influx of up to 15 ma) that can be accessed in 1-bit units. the output levels on the pins d 0 to d 5 can be set to low or high by accessing the port in one-bit units with the sed, sedd, red, and redd output instructions. the output data is stored in the pdr for each pin. the level on each of the pins d0 to d5 can be tested in one-bit units with the td and tdd input instructions. the dcd registers are used to turn the d port output buffers on or off. when the dcd corresponding to a given pin is 1, the data in the corresponding pdr will be output from that pin. the on/off states of the output buffers can be controlled individually for each d port pin. the dcd registers are allocated in the ram address space. the pins d 0 and d 4 have shared functions as built-in peripheral module pins. pmrb is used to switch these functions. figure 8-1 shows the structure of the d port. d port d 0 /int 0 /evnb (i/o, input, or input) d 1 (i/o) d 2 (i/o) d 3 (i/o) d 4 / stopc (i/o or input) d 5 (i/o) : high current pins figure 8-1 d port structure
168 8.2.2 register configuration and descriptions table 8-5 shows the configuration of the d port registers. table 8-5 d port register configuration address register symbol r/w initial value port data registers pdr w * 1 $02c data control registers dcd0 w $0 $02d dcd1 w --00 $024 port mode register b pmrb w 0--0 note: * the sed, sedd, red, and redd instructions can be used to write to the pdrs. (1) port data registers (pdr): each of the i/o pins d 0 to d 5 includes a built-in pdr. when a sed or sedd instruction is executed for one of the pins d 0 to d 5 the corresponding pdr is set to 1, and when a red or redd instruction is executed, the corresponding pdr is cleared to 0. when a bit corresponding to a d port pin in dcd0 or dcd1 is 1, the corresponding output buffer is turned on and the value of the corresponding pdr will be output from that pin. the pdr registers are set to 1 on reset and in stop mode. (2) data control registers (dcd0, dcd1: $02c, $02d) dcd0: $02c dcd1: $02d bit initial value read/write 3 dcd03 0 w 0 dcd00 0 w 2 dcd02 0 w 1 dcd01 0 w bit initial value read/write 3 0 dcd10 0 w 2 1 dcd11 0 w bits in dcd0 and dcd1 description 0 the cmos output buffer is turned off and the output goes to the high impedance state. (initial value) 1 the output buffer is turned on and the value in the corresponding pdr is output.
169 the bits in dcd0 and dcd1 correspond to the d port pins as shown in the table. bit register bit 3 bit 2 bit 1 bit 0 dcd0 d 3 d 2 d 1 d 0 dcd1 d 5 d 4 (3) port mode register b (pmrb: $024): pmrb is a 2-bit write-only register that switches the d port i/o pin shared functions. bit initial value read/write 3 pmrb3 0 w 0 pmrb0 0 w 2 1 0 1 d 0 /int 0 /evnb pin function switch 0 1 d 4 / stopc pin function switch d 0 i/o pin int 0 /evnb input pin d 4 i/o pin stopc input pin unused bit 3? 4 / stopc pin function switch (pmrb3): selects whether the d 4 / stopc pin is used as the d 4 i/o pin or as the stop mode clear pin ( stopc ). pmrb3 description 0 the d 4 / stopc pin functions as the d 4 i/o pin. (initial value) 1 the d 4 / stopc pin functions as the stopc input pin. bit 0? 0 / int 0 /evnb pin function switch (pmrb0): selects whether the d 0 / int 0 /evnb pin is used as the d 0 i/o pin or as the int 0 /evnb input pin. pmrb0 description 0 the d 0 / int 0 /evnb pin functions as the d 0 i/o pin. (initial value) 1 the d 0 / int 0 /evnb pin functions as the int 0 /evnb input pin. refer to section 18.2.2, ?imer mode register b2 (tmb2)? for details on switching between the int 0 and evnb functions.
170 8.2.3 pin functions the functions of the pins d0 to d5 are switched by the bits in registers pmra and pmrb as shown in table 8-6. table 8-6 d port pin functions pin pin functions and selection methods d 0 / int 0 /evnb the pin function is switched as shown below by the pmrb pmrb0 bit and the dcd0 dcd00 bit. pmrb0 0 1 dcd00 0 1 pin function d 0 input pin d 0 output pin int 0 /evnb input pin * note: * to use this pin as the evnb pin, mask the int 0 interrupt by setting the int 0 interrupt mask (im0: $000,3) to 1. d 1 the pin function is switched as shown below by the dcd0 dcd01 bit. dcd01 0 1 pin function d 1 input pin d 1 output pin d 2 the pin function is switched as shown below by the dcd0 dcd02 bit. dcd02 0 1 pin function d 2 input pin d 2 output pin d 3 the pin function is switched as shown below by the dcd0 dcd03 bit. dcd03 0 1 pin function d 3 input pin d 3 output pin d 4 / stopc the pin function is switched as shown below by the pmrb pmrb3 bit and the dcd1 dcd10 bit. pmrb3 0 1 dcd10 0 1 pin function d 4 input pin d 4 output pin stopc input pin d5 the pin function is switched as shown below by the dcd1 dcd11 bit. dcd11 0 1 pin function d 5 input pin d 5 output pin
171 8.3 r ports 8.3.1 overview the r port consists of the three 4-bit i/o ports and one 3-bit port, ports r0 to r3. these ports are accessed in 4-bit units. ports r0 and r3 are standard voltage i/o ports, r1 0 to r1 2 are medium voltage nmos open drain i/o ports, and r1 3 and r2 are standard voltage nmos open drain i/o ports. the individual ports r0 to r3 are accessed in 4-bit units with the lra and lrb output instructions to control the output levels (high or low) on each pin. output data is stored in the pdr built into each pin. similarly, the lar and lbr input instructions can be used to access the r ports in 4-bit units to read the input levels on the port pins. dcr registers are used to control the port r0 to r3 output buffer on/off states. when the dcr bit corresponding to a pin in one of the ports r0 to r3 is set to 1, the data in the corresponding pdr is output from that pin. thus the output buffer on/off states can be controlled on an individual pin basis for the r port pins. the dcr registers are allocated in the ram address space. the pins in ports r1 and r2 are high current pins that can accept current influxes of up to 15 ma. the r0 and r3 port pins have shared functions as built-in peripheral module pins. register settings are used to switch these functions. (see table 8-7.) figure 8-2 shows the r port pin structure. r0 0 /sck (i/o or i/o) r0 1 /si (i/o or input) r0 2 /so (i/o or output) r0 3 /toc (i/o or output) r3 1 /an 1 (i/o or input) r3 2 /an 2 (i/o or input) r3 3 /an 3 (i/o or input) r2 0 (i/o) r2 1 (i/o) r2 2 (i/o) r2 3 (i/o) r1 0 (i/o) r1 1 (i/o) r1 2 (i/o) r1 3 (i/o) r0 port r2 port r1 port r3 port standard voltage nmos open drain medium voltage nmos open drain standard voltage nmos open drain : high current pins figure 8-2 r port structure
172 8.3.2 register configuration and descriptions table 8-7 shows the configuration of the r port related registers, table 8-7 r port register configuration address register symbol r/w initial value port data registers pdr w * 1 $030 data control registers dcr0 w $0 $031 dcr1 w $0 $032 dcr2 w $0 $033 dcr3 w $0 $004 port mode register a pmra w $0 $005 serial mode register smr w $0 $019 a/d mode register 1 amr1 w $0 note: * the lra and lrb instructions are used to write to the pdr registers. (1) port data registers (pdr): all the i/o pins in ports r0 to r3 include a pdr that holds the output data. when an lra or an lrb instruction is executed for one of ports r0 to r3, the contents of the accumulator (a) or the b register (b) are transferred to the specified r port pdrs. when the corresponding bit in dcr0 to dcr3 for the specified port is 1, the output buffers for the corresponding pins will be turned on and the values in the pdrs will be output from the pins. the pdr registers are set to 1 on reset and in stop mode.
173 (2) data control registers (dcr0 to dcr3: $030, $031, $032, $033) dcr0: $030 dcr1: $031 dcr2: $032 dcr3: $033 bit initial value read/write 3 dcr03 0 w 0 dcr00 0 w 2 dcr02 0 w 1 dcr01 0 w bit initial value read/write 3 dcr13 0 w 0 dcr10 0 w 2 dcr12 0 w 1 dcr11 0 w bit initial value read/write 3 dcr23 0 w 0 dcr20 0 w 2 dcr22 0 w 1 dcr21 0 w bit initial value read/write 3 dcr33 0 w 0 2 dcr32 0 w 1 dcr31 0 w bits in dcr0 to dcr3 description 0 the output buffer (cmos buffer) is turned off and the output goes to the high impedance state. (initial value) 1 ? cmos three state outputs: the buffer is turned on and the corresponding pdr value is output. ? nmos open drain pins: a low level is output when the pdr is set to 0, and the pin goes to the high impedance state when the pdr is set to 1. the table below lists the correspondence between the bits in dcr0 to dcr3 and the port r0 to r3 pins. bit register bit 3 bit 2 bit 1 bit 0 dcr0 r0 3 r0 2 r0 1 r0 0 dcr1 r1 3 r1 2 r1 1 r1 0 dcr2 r2 3 r2 2 r2 1 r2 0 dcr3 r3 3 r3 2 r3 1
174 (3) port mode register a (pmra: $004): pmra is a 3-bit write-only register whose bits pmra2 to pmra0 switch the functions of the port r0 shared function pins. bit initial value read/write 3 0 pmra0 0 w 2 pmra2 0 w 1 pmra1 0 w 0 1 r0 3 /toc pin function switch 0 1 r0 1 /si pin function switch 0 1 r0 2 /so pin function switch r0 3 i/o pin toc output pin r0 1 i/o pin si input pin r0 2 i/o pin so output pin unused bit 2?0 3 /toc pin function switch (pmra2): selects whether the r0 3 /toc pin functions as the r0 3 input pin or as the timer c output pin (toc). pmra2 description 0 the r0 3 /toc pin functions as the r0 3 i/o pin. (initial value) 1 the r0 3 /toc pin functions as the toc output pin. bit 1?r0 1 /si pin function switch (pmra1): selects whether the r0 1 /si pin functions as the r0 1 i/o pin or as the serial reception data input pin (si). pmra1 description 0 the r0 1 /si pin functions as the r0 1 i/o pin. (initial value) 1 the r0 1 /si pin functions as the si input pin.
175 bit 0?0 2 /so pin function switch (pmra0): selects whether the r0 2 /so pin functions as the r0 2 i/o pin or as the serial transmission data output pin (so). pmra0 description 0 the r0 2 /so pin functions as the r0 2 i/o pin. (initial value) 1 the r0 2 /so pin functions as the so output pin. (4) serial mode register (smr: $005): smr is a 4-bit write-only register whose smr3 bit switches the r0 0 / sck pin function. this section only describes the smr3 bit. see section 20.2.1, ?erial mode register (smr)?for details on bits smr2 to smr0. bit initial value read/write 3 smr3 0 w 0 smr0 0 w 2 smr2 0 w 1 smr1 0 w transfer clock selection 0 1 r0 0 / sck pin function switch r0 0 i/o pin sck i/o pin bit 3?0 0 / sck pin function switch (smr3): selects whether the r0 0 / sck pin functions as the r0 0 i/o pin or as the serial interface transfer clock i/o pin. smr3 description 0 the r0 0 / sck pin functions as the r0 0 i/o pin. (initial value) 1 the r0 0 / sck pin functions as the sck i/o pin.
176 (5) a/d mode register 1 (amr1: $019): amr1 is a 3-bit write-only register that switches the functions of the r3 port shared function pins. bit initial value read/write 3 amr13 0 w 0 2 amr12 0 w 1 amr11 0 w 0 1 r3 2 /an 2 pin function switch 0 1 r3 1 /an 1 pin function switch 0 1 r3 3 /an 3 pin function switch r3 2 i/o pin an 2 input pin r3 1 i/o pin an 1 input pin r3 3 i/o pin an 3 input pin unused bit 3?3 3 /an 3 pin function switch (amr13): selects whether the r3 3 /an 3 pin functions as the r3 3 i/o pin or as the a/d converter channel 3 input pin an 3 . amr13 description 0 the r3 3 /an 3 pin functions as the r3 3 i/o pin. (initial value) 1 the r3 3 /an 3 pin functions as the an 3 input pin.
177 bit 2?3 2 /an 2 pin function switch (amr12): selects whether the r3 2 /an 2 pin functions as the r3 2 i/o pin or as the a/d converter channel 2 input pin an 2 . amr12 description 0 the r3 2 /an 2 pin functions as the r3 2 i/o pin. (initial value) 1 the r3 2 /an 2 pin functions as the an 2 input pin. bit 1?r3 1 /an 1 pin function switch (amr11): selects whether the r3 1 /an 1 pin functions as the r3 1 i/o pin or as the a/d converter channel 1 input pin an 1 . amr11 description 0 the r3 1 /an 1 pin functions as the r3 1 i/o pin. (initial value) 1 the r3 1 /an 1 pin functions as the an 1 input pin.
178 8.3.3 pin functions the pin functions of the r port pins are switched by register settings as shown in table 8-8. table 8-8 r port pin functions pin pin functions and selection methods r0 0 / sck the pin function is switched by the smr smr3 bit and the dcr0 dcr00 bit as shown below. smr3 0 1 dcr00 0 1 pin function r0 0 input pin r0 0 output pin sck i/o pin r0 1 /si the pin function is switched by the pmra pmra1 bit and the dcr0 dcr01 bit as shown below. pmra1 0 1 dcr01 0 1 pin function r0 1 input pin r0 1 output pin si input pin r0 2 /so the pin function is switched by the pmra pmra0 bit and the dcr0 dcr02 bit as shown below. pmra0 0 1 dcr02 0 1 pin function r0 2 input pin r0 2 output pin so output pin r0 3 /toc the pin function is switched by the pmra pmra2 bit and the dcr0 dcr03 bit as shown below. pmra2 0 1 dcr03 0 1 pin function r0 3 input pin r0 3 output pin toc output pin
179 table 8-8 r port pin functions (cont) pin pin functions and selection methods r1 0 the pin function is switched by the dcr1 dcr10 bit as shown below. dcr10 0 1 pin function r1 0 input pin r1 0 output pin * 1 r1 1 the pin function is switched by the dcr1 dcr11 bit as shown below. dcr11 0 1 pin function r1 1 input pin r1 1 output pin * 1 r1 2 the pin function is switched by the dcr1 dcr12 bit as shown below. dcr12 0 1 pin function r1 2 input pin r1 2 output pin * 1 r1 3 the pin function is switched by the dcr1 dcr13 bit as shown below. dcr13 0 1 pin function r1 3 input pin r1 3 output pin * 2 r2 0 the pin function is switched by the dcr2 dcr20 bit as shown below. dcr20 0 1 pin function r2 0 input pin r2 0 output pin * 2 r2 1 the pin function is switched by the dcr2 dcr21 bit as shown below. dcr21 0 1 pin function r2 1 input pin r2 1 output pin * 2 r2 2 the pin function is switched by the dcr2 dcr22 bit as shown below. dcr22 0 1 pin function r2 2 input pin r2 2 output pin * 2 r2 3 the pin function is switched by the dcr2 dcr23 bit as shown below. dcr23 0 1 pin function r2 3 input pin r2 3 output pin * 2 notes on next page.
180 notes: 1. r1 0 to r1 2 are medium voltage nmos open drain i/o pins. these pins go to the high impedance state when their pdr is set to 1. 2. r1 3 and r2 0 to r2 3 are standard voltage nmos open drain i/o pins. these pins go to the high impedance state when their pdr is set to 1. table 8-8 r port pin functions (cont) pin pin functions and selection methods r3 1 /an 1 the pin function is switched by the amr1 amr11 bit and the dcr3 dcr31 bit as shown below. amr11 0 1 dcr31 0 1 pin function r3 1 input pin r3 1 output pin an 1 input pin r3 2 /an 2 the pin function is switched by the amr1 amr12 bit and the dcr3 dcr32 bit as shown below. amr12 0 1 dcr32 0 1 pin function r3 2 input pin r3 2 output pin an 2 input pin r3 3 /an 3 the pin function is switched by the amr1 amr13 bit and the dcr3 dcr33 bit as shown below. amr13 0 1 dcr33 0 1 pin function r3 3 input pin r3 3 output pin an 3 input pin
181 8.4 usage notes keep the following points in mind when using the i/o ports. ? when the mis mis2 bit is set to 1, the r0 2 /so pin will be an nmos open drain output regardless of whether it is selected for use as the r0 2 pin or as the so pin by the pmra pmra0 bit. ? i/o pins that are unused in user systems must be tied to a fixed potential, since floating i/o pins can cause noise that can cause the lsi to operate incorrectly. the built-in pull-up mos transistors can be used to pull up unused pins to v cc . alternatively, unused pins can be pulled up to v cc with external resistors of about 100 k ? . application programs should maintain the pdr and dcr contents for unused pins at their reset state values. also note that unused pins must not be selected for use as peripheral function i/o pins. ? when the mis mis3 bit is set to 1 (pull-up mos transistors active) and the pdr for an r port/analog input shared function pin has the value 1, the mos transistor for the corresponding pin will not be turned off by selecting the analog input function with the amr1 register. to use an r port/analog input shared function pin as an analog input when the pull-up mos transistors are active, always clear the pdr for the corresponding pin to 0 first and then turn off the pull-up mos transistor. (note that the pdr registers are set to 1 immediately following a reset.) figure 8-3 shows the circuit for the r port/analog input shared function pins. amr1 is used to set the port outputs to high impedance. acr is used to switch the analog input channel. the states of the r port/analog input shared function pins are set, as shown in table 8-9, by the combination of the amr1 register, the mis3 bit, the dcr, and the pdr settings.
182 v cc v cc hlt mis3 dcr pdr amr (a/d mode register setting value) acr (a/d channel register setting value) input control signal input data a/d input figure 8-3 r port/analog input shared function pin circuit table 8-9 program control of the r port/analog input shared function pins corresponding bit in amr1 0 (r port selected) mis3 bit 0 1 dcr 0101 pdr 01010101 cmos buffer pmos on on nmos on on pull-up mos transistor on on note: : off corresponding bit in amr1 1 (analog input selected) mis3 bit 0 1 dcr 0101 pdr 01010101 cmos buffer pmos nmos pull-up mos transistor on on note: : off
183 ? in the hd404394 series evaluation chip set, the circuits for the medium voltage nmos open drain pins (r1 0 to r1 2 ) and the standard voltage nmos open drain pins (r1 3 and r2 0 to r2 3 ) differ from the ztat and the mask rom microcomputer versions as shown in figure 8-4. although the outputs in both the ztat and mask rom versions can be set to high impedance by the combinations listed in table 8.10, the r1 0 to r1 2 outputs cannot be set to high impedance in the evaluation chip set. also note that the r1 3 and r2 0 to r2 3 outputs go to the high level when both the corresponding dcr and pdr are 1. please keep this in mind when using the evaluation chip set. pdr dcr hlt v cc v cc hlt mis3 dcr pdr * input data input control signal input data input control signal note: * only included in the r1 0 to r1 2 pin circuits. does not appear in the r1 3 and r2 0 to r2 3 pin circuits. (a) evaluation chip pin circuit structure (b) ztat and mask rom pin circuit structure figure 8-4 medium voltage nmos open drain pin circuits
184 table 8-10 ztat and mask rom microcomputer nmos open drain pin high impedance control dcr pdr description 0 * high impedance output (initial value) 1 0 nmos buffer on. low level output 1 high impedance output note: * don t care
185 section 9 i/o ports (hd404318 series) 9.1 overview 9.1.1 features the hd404318 series i/o ports have the following features. ? the nine pins d 0 to d 8 as well as the r1, r2, and r8 ports are high voltage i/o pins. also, ra 1 is a high voltage input pin. r0, r3, and r4 are standard voltage i/o pins that, in output mode, are cmos three state outputs. ? certain i/o pins (d 0 to d 4 , and the pins in the r0, r3, and r4 ports) are shared with the built- in peripheral modules, such as timers and the serial interface. setting these pins for use with the built-in peripheral modules takes priority over their setting for use as d or r port pins. ? register settings are used to select input or output for i/o pins and to select the i/o port or peripheral module usage for shared function pins. ? of the built-in peripheral module pins, the d 3 /buzz pin is a pmos open drain output. all other output pins are cmos outputs. however, the r0 2 /so pin can be selected to be an nmos open drain output by setting a register. ? since the system is reset in stop mode, the built-in peripheral module selections are cleared and the i/o pins go to the high impedance state. ? the cmos output pins have built-in programmable pull-up mos transistors. the on/off state of these transistors can be controlled by register settings on an individual basis. note that the pull-up mos transistor on/off settings are independent of the pin settings for use as built-in peripheral module pins. table 9-1 provides an overview of the hd404318 series port functions.
186 table 9-1 port functions port overview pin shared function function switching register d 0 to d 8 d 0 / int 0 external interrupt input 0 pmrb d 1 / int 1 external interrupt input 1 d 2 /evnb timer b event input d 3 /buzz alarm output pmra d 4 / stopc stop mode clear pmrb d 5 to d 8 r0 r0 0 / sck transfer clock i/o smr r0 1 /si serial reception data input pmra r0 2 /so serial transmission data output r0 3 /toc timer c output r3 r3 0 /an 0 analog input channel 0 amr1 r3 1 /an 1 analog input channel 1 r3 2 /an 2 analog input channel 2 r3 3 /an 3 analog input channel 3 r4 r4 0 /an 4 analog input channel 4 amr2 r4 1 /an 5 analog input channel 5 r4 2 /an 6 analog input channel 6 r4 3 /an 7 analog input channel 7 ? high voltage i/o port ? accessed in bit units ? accessed with the sed, sedd, red, redd, td, and tdd instructions. ? pull-down resistors available as a mask option. ? standard voltage i/o ports ? accessed in 4-bit units. ? accessed with the lar, lbr, lra, and lrb instructions. ? programmable pull-up mos transistors
187 table 9-1 port functions (cont) port overview pin shared function function switching register r1 r1 0 r1 1 r1 2 r1 3 r2 r2 0 r2 1 r2 2 r2 3 r8 r8 0 r8 1 r8 2 r8 3 ra ? high voltage input port (1 bit) ? accessed with the lar and lbr instructions. ra 1 /v disp high voltage pin output power supply mask option ? high voltage i/o ports ? accessed in 4-bit units. ? accessed with the lar, lbr, lra, and lrb instructions. ? pull-down resistors available as a mask option.
188 9.1.2 i/o control the d, r1, r2, and r8 ports are high voltage i/o ports, ra 1 is a 1-bit high voltage input port, and r0, r3, and r4 are standard voltage i/o ports. the different port types have different circuit structures as follows. (1) high voltage i/o pin circuit: the d, r1, r2, and r8 port pins are high voltage i/o pins that have no i/o switching function. when a port data register is set to 1, the pmos transistor turns on and a high level voltage is output from the pin. when the pdr is set to 0, the pin goes to the open state. if the built-in pull-down resistor mask option was selected, the v disp voltage is output. when external signals are applied, applications must set the pdr value to 0 so that the external (input) and internal (output) signals do not collide at the pin. note that there are no pull-down resistors on the high voltage i/o pins in the ztat versions of these microcomputers. (2) standard voltage cmos three state i/o pin circuit: the pins in the r0, r3, and r4 ports are standard voltage cmos three state i/o ports. i/o through these ports is controlled by the pdrs and the data control registers (dcr). when the dcr bit corresponding to a given pin is 1, that pin functions as an output pin and outputs the value in the pdr. when a given dcr bit is 0, the corresponding pin functions as an input pin. (3) pull-up mos control: each i/o pin in the r0, r3, and r4 ports has a built-in programmable pull-up mos transistor. when the miscellaneous register (mis) mis3 bit is set to 1 the pull-up mos transistor for pins for which the corresponding pdr is set to 1 will be turned on. thus the on/off state of each pin can be controlled independently by the pdrs. note that the pull-up mos transistor on/off settings are independent of the pin settings for use as built-in peripheral module pins. table 9-2 shows how register settings control the port i/o pins. table 9-2 register settings for i/o pin control mis3 0 1 dcr 0101 pdr 01010101 cmos buffer pmos on on nmos on on pull-up mos transistor on on notes: 1. ? off 2. the pdr registers are not allocated addresses in ram. the pdr registers are accessed by special-purpose i/o instructions.
189 (4) miscellaneous register (mis: $00c): mis is a 2-bit write-only register that controls the on/off states of the r0, r3, and r4 port pin pull-up mos transistors and the on/off state of the r0 2 /so pin output buffer pmos transistor. mis is initialized to $0 on reset and in stop mode. 0 1 bit initial value read/write 3 mis3 0 w 0 2 mis2 0 w 1 r0 2 /so pin output buffer control 0 1 pull-up mos transistor control pmos transistor active (cmos output) pmos transistor off (nmos open drain output) all pull-up mos transistors off pull-up mos transistors active unused bit 3?ull-up mos transistor control (mis3): controls the on/off states of the pull-up mos transistors built into the i/o port pins. mis3 description 0 all pull-up mos transistors will be turned off. (initial value) 1 pull-up mos transistors for which the corresponding pdr bit is 1 will be turned on. bit 2?0 2 /so pin output buffer control (mis2): controls the on/off state of the r0 2 /so pin output buffer pmos transistor. mis2 description 0 the r0 2 /so pin output will be a cmos output. (initial value) 1 the r0 2 /so pin output will be an nmos open drain output.
190 9.1.3 i/o pin circuit structures table 9-3 shows the port and peripheral module pin circuits. notes: 1. since the system is reset in stop mode, the built-in peripheral module selections are cleared. since the internal hlt signal goes to the low (active) level, the i/o pins go to the high impedance state. also, all the pull-up mos transistors are turned off. 2. in all low power modes other than stop mode, the internal hlt signal goes to the high level. table 9-3 input and output pin circuits class circuit applicable pins standard voltage pins i/o pins v cc v cc hlt mis3 dcr pdr pull-up control signal buffer control signal output data input control signal input data r0 0 , r0 1 , r0 3 , r3 0 to r3 3 , r4 0 to r4 3 v cc v cc hlt mis3 dcr pdr mis2 pull-up control signal buffer control signal output data input control signal input data r0 2
191 table 9-3 input and output pin circuits (cont) class circuit applicable pins standard voltage pins standard peripheral module pins i/o pins v cc v cc hlt mis3 sck sck pull-up control signal output data input data sck output pins v cc v cc hlt mis3 so mis2 pull-up control signal pmos control signal output data so v cc v cc hlt mis3 toc pull-up control signal output data toc
192 table 9-3 input and output pin circuits (cont) class circuit applicable pins standard voltage pins built-in peripheral module pins input pins si v cc hlt mis3 pdr input data si v cc hlt mis3 pdr a/d input input control an 0 to an 7
193 table 9-3 input and output pin circuits (cont) class circuit applicable pins high voltage pins i/o pins pins with pull-down resistors v cc hlt v disp pull-down resistor input control signal output data input data d 0 to d 8 , r1 0 to r1 3 , r2 0 to r2 3 , r8 0 to r8 3 pins without pull-down resistors * v cc hlt output data input control signal input data input pin input control signal input data ra 1 note: * the ztat versions of these microcomputers only support pins without pull-down resistors.
194 table 9-3 input and output pin circuits (cont) class circuit applicable pins high voltage pins built-in peripheral module pins output pins pins with pull-down resistors v cc hlt v disp output data pull-down resistor buzz pins without pull-down resistors * v cc hlt output data input pins pins with pull-down resistors int 0 , int 1 , evnb, stop c v cc hlt mis3 pdr v disp input data pull-down resistor int 0 , int 1 , evnb, stopc pins without pull-down resistors * v cc hlt mis3 pdr int 0 , int 1 , evnb, stop c note: * the ztat versions of these microcomputers only support pins without pull-down resistors.
195 9.1.4 port states in low power modes the d 0 to d 4 pins and the r0, r3, and r4 port pins have shared functions as input or output pins for built-in peripheral modules. in standby mode, since the cpu stops, the pins selected as output ports maintain their immediately prior output values. also, pins selected for use by built-in peripheral modules that operate in standby mode continue to operate. (output pins used by modules that stop in standby mode maintain their immediately prior output values.) see section 5, ?ow power modes? for details on which built-in peripheral modules can operate in each mode. table 9-4 lists the port states in the low power modes. table 9-4 port states in low power modes low power mode port states standby mode pins maintain their values immediately prior to entering standby mode. stop mode built-in peripheral function selections are cleared, and the port and peripheral function i/o pins go to the high impedance state. 9.1.5 handling unused pins i/o pins that are unused in user systems must be tied to a fixed potential, since floating i/o pins can cause noise that can interfere with lsi operation. the following are examples of techniques that can prevent noise problems. high voltage pin: select ?o pull-down mos transistor (pmos open drain)?as the mask option and connect the pin to v cc on the user system printed circuit board. standard voltage pin: either use the built-in pull-up mos transistor to pull the pin up to v cc , or pull up the pin to v cc externally with a pull-up resistor of about 100 k ? . application programs should maintain the pdr and dcr contents for unused pins at their reset state values. also note that unused pins must not be selected for use as peripheral function i/o pins.
196 9.2 d port 9.2.1 overview the d port is a 9-pin high voltage i/o port (d 0 to d 8 ) that can be accessed in 1-bit units. the output levels on the pins d 0 to d 8 can be set to low or high by accessing the port in one-bit units with the sed, sedd, red, and redd output instructions. the output data is stored in the pdr for each pin. the level on each of the pins d 0 to d 8 can be tested in one-bit units with the td and tdd input instructions. the pins d 0 to d 4 have shared functions as built-in peripheral module pins. pmra and pmrb are used to switch these functions. figure 9-1 shows the structure of the d port. d 0 /int 0 (i/o or input) d 1 /int 1 (i/o or input) d 2 /evnb (i/o or input) d 3 /buzz (i/o or output) d 4 / stopc (i/o or input) d 5 (i/o) d 6 (i/o) d 7 (i/o) d 8 (i/o) d port high voltage pins figure 9-1 d port structure
197 9.2.2 register configuration and descriptions table 9-5 shows the configuration of the d port registers. table 9-5 d port register configuration address register symbol r/w initial value port data registers pdr w * 0 $004 port mode register a pmra w $0 $024 port mode register b pmrb w $0 note: * the sed, sedd, red, and redd instructions can be used to write to the pdrs. (1) port data registers (pdr): each of the i/o pins d 0 to d 8 includes a built-in pdr that stores the output data. when a sed or sedd instruction is executed for one of the pins d 0 to d 8 the corresponding pdr is set to 1, and when a red or redd instruction is executed, the corresponding pdr is cleared to 0. the pdrs are cleared to 0 on reset and in stop mode.
198 (2) port mode register a (pmra: $004): pmra is a 4-bit write-only register whose pmra3 bit switches the function of the d 3 /buzz pin. this section describes the function of the pmra3 bit. see section 9.3.2 (3), ?ort mode register a (pmra)? for details on the pmra2 to pmra0 bits. bit initial value read/write 3 pmra3 0 w 0 pmra0 0 w 2 pmra2 0 w 1 pmra1 0 w 0 1 r0 3 /toc pin function switch 0 1 r0 1 /si pin function switch 0 1 r0 2 /so pin function switch 0 1 d 3 /buzz pin function switch r0 3 i/o pin toc output pin r0 1 i/o pin si input pin r0 2 i/o pin so output pin d 3 i/o pin buzz output pin bit 3? 3 /buzz pin function switch (pmra3): selects whether the d 3 /buzz pin functions as the d 3 input pin or as the alarm output pin (buzz). pmra3 description 0d 3 /buzz pin functions as the d 3 i/o pin. (initial value) 1d 3 /buzz pin functions as the buzz output pin.
199 (3) port mode register b (pmrb: $024): pmrb is a 4-bit write-only register that switches the d port i/o pin shared functions. bit initial value read/write 3 pmrb3 0 w 0 pmrb0 0 w 2 pmrb2 0 w 1 pmrb1 0 w 0 1 d 2 /evnb pin function switch 0 1 d 1 /int 1 pin function switch 0 1 d 0 /int 0 pin function switch 0 1 d 4 / stopc pin function switch d 2 i/o pin evnb input pin d 1 i/o pin int 1 input pin d 0 i/o pin int 0 input pin d 4 i/o pin stopc input pin bit 3? 4 / stopc pin function switch (pmrb3): selects whether the d 4 / stopc pin is used as the d 4 i/o pin or as the stop mode clear pin ( stopc ). pmrb3 description 0 the d 4 / stopc pin functions as the d 4 i/o pin. (initial value) 1 the d 4 / stopc pin functions as the stopc input pin. bit 2? 2 /evnb pin function switch (pmrb2): selects whether the d 2 /evnb pin is used as the d 2 i/o pin or as the timer b event count input pin (evnb). pmrb2 description 0 the d 2 /evnb pin functions as the d 2 i/o pin. (initial value) 1 the d 2 /evnb pin functions as the evnb input pin.
200 bit 1? 1 / int 1 pin function switch (pmrb1): selects whether the d 1 / int 1 pin is used as the d 1 i/o pin or as external interrupt 1 input pin ( int 1 ). pmrb1 description 0 the d 1 / int 1 pin functions as the d 1 i/o pin. (initial value) 1 the d 1 / int 1 pin functions as the int 1 input pin. bit 0? 0 / int 0 pin function switch (pmrb0): selects whether the d 0 / int 0 pin is used as the d 0 i/o pin or as external interrupt 0 input pin ( int 0 ). pmrb0 description 0 the d 0 / int 0 pin functions as the d 0 i/o pin. (initial value) 1 the d 0 / int 0 pin functions as the int 0 input pin.
201 9.2.3 pin functions the functions of the pins d 0 to d 4 are switched by register pmra and pmrb settings as shown in table 9-6. table 9-6 d 0 to d 4 port pin functions pin pin functions and selection methods d 0 / int 0 the pin function is switched as shown below by the pmrb pmrb0 bit. pmrb0 0 1 pin function d 0 i/o pin int 0 input pin d 1 / int 1 the pin function is switched as shown below by the pmrb pmrb1 bit. pmrb1 0 1 pin function d 1 i/o pin int 1 input pin d 2 /evnb the pin function is switched as shown below by the pmrb pmrb2 bit. pmrb2 0 1 pin function d 2 i/o pin evnb input pin d 3 /buzz the pin function is switched as shown below by the pmra pmra3 bit. pmra3 0 1 pin function d 3 i/o pin buzz output pin d 4 / stopc the pin function is switched as shown below by the pmrb pmrb3 bit. pmrb3 0 1 pin function d 4 i/o pin stopc input pin
202 9.3 r ports 9.3.1 overview the r port consists of the six 4-bit i/o ports r0 to r4 and r8 and the 1-bit input port ra 1 . these ports are accessed in 4-bit units. r0, r3, and r4 are standard voltage i/o ports. ra is a high voltage input port and r1, r2 and r8 are high voltage i/o ports that can directly drive fluorescent display tubes. the individual ports r0 to r4 and r8 are accessed in 4-bit units with the lra and lrb output instructions to control the output levels (high or low) on each pin. output data is stored in the pdr built into each pin. similarly, the lar and lbr input instructions can be used to access the r ports in 4-bit units to read the input levels on the port pins. the ra 1 input-only port consists of a single bit. the values of bits 3, 2, and 0 are undefined when this port is accessed by the input instructions. dcr registers are used to control on/off states of the r0, r3, and r4 output buffers. when the dcr bit corresponding to a pin in an r0, r3, or r4 port is set to 1, the contents of the pdr corresponding to that pin is output from the pin. thus the output buffer on/off states can be controlled on an individual pin basis for the r port pins. the dcr registers are allocated in the ram address space. the r0, r3, and r4 port pins have shared functions as built-in peripheral module pins. register settings are used to switch these functions. (see table 9-7.) figure 9-2 shows the r port pin structure.
203 r0 0 /sck (i/o or i/o) r0 1 /si (i/o or input) r0 2 /so (i/o or output) r0 3 /toc (i/o or output) r2 0 (i/o) r2 1 (i/o) r2 2 (i/o) r2 3 (i/o) r4 0 /an 4 (i/o or input) r4 1 /an 5 (i/o or input) r4 2 /an 6 (i/o or input) r4 3 /an 7 (i/o or input) ra 1 /v disp * (input or ) r3 0 /an 0 (i/o or input) r3 1 /an 1 (i/o or input) r3 2 /an 2 (i/o or input) r3 3 /an 3 (i/o or input) r1 0 (i/o) r1 1 (i/o) r1 2 (i/o) r1 3 (i/o) r8 0 (i/o) r8 1 (i/o) r8 2 (i/o) r8 3 (i/o) r0 port r3 port r4 port r1 port r2 port r8 port ra port high voltage pins high voltage pins high voltage pins high voltage pins note: * in products with on-chip mask resistors, the use of this pin as the v disp pin (display power supply pin) can be selected as a mask option. high voltage pins for which a pull-down mos transistor is selected are pulled down to the v disp potential. figure 9-2 r port structure
204 9.3.2 register configuration and descriptions table 9-7 shows the configuration of the r port related registers. table 9-7 r port register configuration address register symbol r/w initial value port data registers standard voltage pins high voltage pins pdr w * 1 0 $030 data control registers dcr0 w $0 $033 dcr3 w $0 $034 dcr4 w $0 $004 port mode register a pmra w $0 $005 serial mode register smr w $0 $019 a/d mode register 1 amr1 w $0 $01a a/d mode register 2 amr2 w --00 note: * the lra and lrb instructions are used to write to the pdr registers. (1) port data registers (pdr): all the i/o pins in ports r0 to r4 and r8 include a pdr that holds the output data. when an lra or an lrb instruction is executed for one of ports r0 to r4 or r8, the contents of the accumulator (a) or the b register (b) are transferred to the specified r port pdrs. when bits in dcr0, dcr3, or dcr4 are set to 1, the output buffers for the corresponding pins in port r0, r3 or r4 will be turned on and the values in the pdrs will be output from those pins. the pdr registers for standard voltage pins are set to 1 on reset and in stop mode, and the pdrs for high voltage pins are cleared to 0.
205 (2) data control registers (dcr0, dcr3, dcr4: $030, $033, $034) dcr4: $034 dcr3: $033 bit initial value read/write 3 dcr43 0 w 0 dcr40 0 w 2 dcr42 0 w 1 dcr41 0 w bit initial value read/write 3 dcr33 0 w 0 dcr30 0 w 2 dcr32 0 w 1 dcr31 0 w bit initial value read/write 3 dcr03 0 w 0 dcr00 0 w 2 dcr02 0 w 1 dcr01 0 w dcr0: $030 bits in dcr0, dcr3, and dcr4 description 0 the output buffer (cmos buffer) is turned off and the output goes to the high impedance state. (initial value) 1 the output buffer is turned on and the corresponding pdr value is output. the table below lists the correspondence between the bits in dcr0, dcr3, and dcr4 and the port r0, r3, and r4 pins. bit register bit 3 bit 2 bit 1 bit 0 dcr0 r0 3 r0 2 r0 1 r0 0 dcr3 r3 3 r3 2 r3 1 r3 0 dcr4 r4 3 r4 2 r4 1 r4 0
206 (3) port mode register a (pmra: $004): pmra is a 4-bit write-only register whose bits pmra2 to pmra0 switch the functions of the port r0 shared function pins. this section describes the bits pmra2 to pmra0. see section 9.2.2 (2), port mode register a (pmra) , for details on the pmra3 bit. bit initial value read/write 3 pmra3 0 w 0 pmra0 0 w 2 pmra2 0 w 1 pmra1 0 w 0 1 r0 3 /toc pin function switch 0 1 r0 1 /si pin function switch 0 1 r0 2 /so pin function switch 0 1 d 3 /buzz pin function switch r0 3 i/o pin toc output pin r0 1 i/o pin si input pin r0 2 i/o pin so output pin d 3 i/o pin buzz output pin bit 2?0 3 /toc pin function switch (pmra2): selects whether the r0 3 /toc pin functions as the r0 3 i/o pin or as the timer c output pin (toc). pmra2 description 0 the r0 3 /toc pin functions as the r0 3 i/o pin. (initial value) 1 the r0 3 /toc pin functions as the toc output pin.
207 bit 1?0 1 /si pin function switch (pmra1): selects whether the r0 1 /si pin functions as the r0 1 i/o pin or as the serial reception data input pin (si). pmra1 description 0 the r0 1 /si pin functions as the r0 1 i/o pin. (initial value) 1 the r0 1 /si pin functions as the si input pin. bit 0?0 2 /so pin function switch (pmra0): selects whether the r0 2 /so pin functions as the r0 2 i/o pin or as the serial transmission data output pin (so). pmra0 description 0 the r0 2 /so pin functions as the r0 2 i/o pin. (initial value) 1 the r0 2 /so pin functions as the so output pin. (4) serial mode register (smr: $005): smr is a 4-bit write-only register whose smr3 bit switches the r0 0 / sck serial mode register (smr) for details on bits smr2 to smr0. bit initial value read/write 3 smr3 0 w 0 smr0 0 w 2 smr2 0 w 1 smr1 0 w 0 1 r0 0 / sck pin function switch r0 0 i/o pin sck i/o pin transfer clock selection bit 3?0 0 / sck pin function switch (smr3): selects whether the r0 0 / sck sck smr3 description 0 the r0 0 / sck pin functions as the r0 0 i/o pin. (initial value) 1 the r0 0 / sck pin functions as the sck i/o pin.
208 (5) a/d mode register 1 (amr1: $019): amr1 is a 4-bit write-only register that switches the functions of the r3 port shared function pins. bit initial value read/write 3 amr13 0 w 0 amr10 0 w 2 amr12 0 w 1 amr11 0 w 0 1 r3 2 /an 2 pin function switch 0 1 r3 1 /an 1 pin function switch 0 1 r3 0 /an 0 pin function switch 0 1 r3 3 /an 3 pin function switch r3 2 i/o pin an 2 input pin r3 1 i/o pin an 1 input pin r3 0 i/o pin an 0 input pin r3 3 i/o pin an 3 input pin bit 3?3 3 /an 3 pin function switch (amr13): selects whether the r3 3 /an 3 pin functions as the r3 3 i/o pin or as the a/d converter channel 3 input pin an 3 . amr13 description 0 the r3 3 /an 3 pin functions as the r3 3 i/o pin. (initial value) 1 the r3 3 /an 3 pin functions as the an 3 input pin. bit 2?3 2 /an 2 pin function switch (amr12): selects whether the r3 2 /an 2 pin functions as the r3 2 i/o pin or as the a/d converter channel 2 input pin an 2 . amr12 description 0 the r3 2 /an 2 pin functions as the r3 2 i/o pin. (initial value) 1 the r3 2 /an 2 pin functions as the an 2 input pin.
209 bit 1?3 1 /an 1 pin function switch (amr11): selects whether the r3 1 /an 1 pin functions as the r3 1 i/o pin or as the a/d converter channel 1 input pin an 1 . amr11 description 0 the r3 1 /an 1 pin functions as the r3 1 i/o pin. (initial value) 1 the r3 1 /an 1 pin functions as the an 1 input pin. bit 0?3 0 /an 0 pin function switch (amr10): selects whether the r3 0 /an 0 pin functions as the r3 0 i/o pin or as the a/d converter channel 0 input pin an 0 . amr10 description 0 the r3 0 /an 0 pin functions as the r3 0 i/o pin. (initial value) 1 the r3 0 /an 0 pin functions as the an 0 input pin.
210 (6) a/d mode register 2 (amr2: $01a): amr2 is a 2-bit write-only register whose amr21 bit switches the functions of all four bits of the r4 port (r4 0 to r4 3 ) to be a/d converter input channels (an 4 to an 7 ). this section describes the amr21 bit. see section 15.2.2, a/d mode register 2 (amr2) , for details on the amr20 bit. bit initial value read/write 3 0 amr20 0 w 2 1 amr21 0 w 0 1 r4 0 /an 4 to r4 3 /an 7 pin function switch 0 1 a/d conversion time r4 0 to r4 3 i/o pins an 4 to an 7 input pins 34 t cyc 67 t cyc unused bit 1?4 0 /an 4 to r4 3 /an 7 pin function switch (amr21): selects whether the r4 0 /an 4 to r4 3 /an 7 pins function as the r4 0 to r4 3 i/o pins or as the a/d converter channel 4 to 7 input pins (an 4 to an 7 ). amr21 description 0 the r4 0 /an 4 to r4 3 /an 7 pins function as the r4 0 to r4 3 i/o pins. (initial value) 1 the r4 0 /an 4 to r4 3 /an 7 pins function as the an 4 to an 7 input pins.
211 9.3.3 pin functions the pin functions of the r port pins are switched by register settings as shown in table 9-8. table 9-8 r port pin functions pin pin functions and selection methods r 0 / sck the pin function is switched by the smr smr3 bit and the dcr0 dcr00 bit as shown below. smr3 0 1 dcr00 0 1 pin function r0 0 input pin r0 0 output pin sck i/o pin r0 1 /si the pin function is switched by the pmra pmra1 bit and the dcr0 dcr01 bit as shown below. pmra1 0 1 dcr01 0 1 pin function r0 1 input pin r0 1 output pin si input pin r0 2 /so the pin function is switched by the pmra pmra0 bit and the dcr0 dcr02 bit as shown below. pmra0 0 1 dcr02 0 1 pin function r0 2 input pin r0 2 output pin so output pin r0 3 /toc the pin function is switched by the pmra pmra2 bit and the dcr0 dcr03 bit as shown below. pmra2 0 1 dcr03 0 1 pin function r0 3 input pin r0 3 output pin toc output pin
212 table 9-8 r port pin functions (cont) pin pin functions and selection methods r3 0 /an 0 the pin function is switched by the amr1 amr10 bit and the dcr3 dcr30 bit as shown below. amr10 0 1 dcr30 0 1 pin function r3 0 input pin r3 0 output pin an 0 input pin r3 1 /an 1 the pin function is switched by the amr1 amr11 bit and the dcr3 dcr31 bit as shown below. amr11 0 1 dcr31 0 1 pin function r3 1 input pin r3 1 output pin an 1 input pin r3 2 /an 2 the pin function is switched by the amr1 amr12 bit and the dcr3 dcr32 bit as shown below. amr12 0 1 dcr32 0 1 pin function r3 2 input pin r3 2 output pin an 2 input pin r3 3 /an 3 the pin function is switched by the amr1 amr13 bit and the dcr3 dcr33 bit as shown below. amr13 0 1 dcr33 0 1 pin function r3 3 input pin r3 3 output pin an 3 input pin r4 0 /an 4 the pin function is switched by the amr2 amr21 bit and the dcr4 dcr40 bit as shown below. amr21 0 1 dcr40 0 1 pin function r4 0 input pin r4 0 output pin an 4 input pin
213 table 9-8 r port pin functions (cont) pin pin functions and selection methods r4 1 /an 5 the pin function is switched by the amr2 amr21 bit and the dcr4 dcr41 bit as shown below. amr21 0 1 dcr41 0 1 pin function r4 1 input pin r4 1 output pin an 5 input pin r4 2 /an 6 the pin function is switched by the amr2 amr21 bit and the dcr4 dcr42 bit as shown below. amr21 0 1 dcr42 0 1 pin function r4 2 input pin r4 2 output pin an 6 input pin r4 3 /an 7 the pin function is switched by the amr2 amr21 bit and the dcr4 dcr43 bit as shown below. amr21 0 1 dcr43 0 1 pin function r4 3 input pin r4 3 output pin an 7 input pin
214 9.4 usage notes keep the following points in mind when using the i/o ports. ? ? no pull-down mos transistor (pmos open drain) as the mask option and connect the pin to v cc on the user system printed circuit board. standard voltage pin: either use the built-in pull-up mos transistor to pull the pin up to v cc , or pull up the pin to v cc externally with a pull-up resistor of about 100 k ? ?
215 v cc v cc hlt mis3 dcr pdr amr (a/d mode register setting value) acr (a/d channel register setting value) pull-up control signal buffer control signal output data input control signal input data a/d input figure 9-3 r port/analog input shared function pin circuit structure
216 table 9-9 program control of the r port/analog input shared use pins corresponding bit in amr1 or amr2 0 (r port selected) mis3 bit 0 1 dcr 0101 pdr 01010101 cmos buffer pmos on on nmos on on pull-up mos transistor on on note: : off corresponding bit in amr1 or amr2 1 (analog input selected) mis3 bit 0 1 dcr 0101 pdr 01010101 cmos buffer pmos nmos pull-up mos transistor on on note: : off
217 section 10 i/o ports (hd404358 and hd404358r series) 10.1 overview 10.1.1 features the hd404358 and hd404358r series i/o ports have the following features. ? hd404358 series: the four pins r2 0 to r2 3 are medium voltage nmos open drain i/o pins. ra 1 is an input-only pin. the d, r0, r1, r3, r4, and r8 port pins are standard voltage i/o pins that, in output mode, are cmos three state outputs. hd404358r series: pins d 0 to d 8 , r0, r1, r2, r3, r4, and r8 are cmos three state standard voltage i/o pins. of these, 20 pins (d 5 to d 8 , r0, r1, r2, and r8) can handle current levels of up to 15 ma. also, ra 1 is an input-only pin. ? certain i/o pins (d 0 to d 4 , and the pins in the r0, r3, and r4 ports) are shared with the built- in peripheral modules, such as timers and the serial interface. setting these pins for use with the built-in peripheral modules takes priority over their setting for use as d or r port pins. ? register settings are used to select input or output for i/o pins and to select the i/o port or peripheral module usage for shared function pins. ? all peripheral module output pins are cmos outputs. however, the r0 2 /so pin can be selected to be an nmos open drain output by setting a register. ? since the system is reset in stop mode, the built-in peripheral module selections are cleared and the i/o pins go to the high impedance state. ? the cmos output pins have built-in programmable pull-up mos transistors. the on/off state of these transistors can be controlled by register settings on an individual basis. note that the pull-up mos transistor on/off settings are independent of the pin settings for use as built-in peripheral module pins. table 10-1 provides an overview of the hd404358 series port functions.
218 table 10-1 port functions port overview pin shared function function switching register d 0 to d 8 d 0 / int 0 external interrupt input 0 pmrb d 1 / int 1 external interrupt input 1 d 2 /evnb timer b event input d 3 /buzz alarm output pmra d 4 / stopc stop mode clear pmrb d 5 to d 8 hd404358 series: ? standard voltage i/o port ? accessed in bit units ? accessed with the sed, sedd, red, redd, td, and tdd instructions. ? programmable pull-up mos transistors hd404358r series: ? standard voltage i/o port. ? d 5 to d 8 is high current pins (max. 15 ma) ? accessed in bit units ? accessed with the sed, sedd, red, redd, td, and tdd instructions. ? programmable pull-up mos transistors
219 table 10-1 port functions (cont) port overview pin shared function function switching register r0 r0 0 / sck transfer clock i/o smr r0 1 /si serial reception data input pmra r0 2 /so serial transmission data output r0 3 /toc timer c output r3 r3 0 /an 0 analog input channel 0 amr1 r3 1 /an 1 analog input channel 1 r3 2 /an 2 analog input channel 2 r3 3 /an 3 analog input channel 3 r4 r4 0 /an 4 analog input channel 4 amr2 r4 1 /an 5 analog input channel 5 r4 2 /an 6 analog input channel 6 r4 3 /an 7 analog input channel 7 r1 r1 0 r1 1 r1 2 r1 3 r8 r8 0 r8 1 r8 2 r8 3 hd404358 series: ? standard voltage i/o port ? accessed in 4-bit units. ? accessed with the lar, lbr, lra, and lrb instructions. ? programmable pull-up mos transistors hd404358r series: ? standard voltage i/o port. ? r0, r1, r8 is high current pins (max. 15 ma) ? accessed in 4-bit units. ? accessed with the lar, lbr, lra, and lrb instructions. ? programmable pull-up mos transistors
220 table 10-1 port functions (cont) port overview pin shared function function switching register r2 r2 0 r2 1 r2 2 r2 3 ra ? standard voltage input port (1 bit) ? accessed with the lar and lbr instructions. ra 1 hd404358 series: ? medium voltage nmos open drain i/o port ? accessed in 4-bit units. ? accessed with the lar, lbr, lra, and lrb instructions. hd404358r series: ? standard voltage i/o port. ? high current pins (max. 15 ma) ? accessed in 4-bit units. ? accessed with the lar, lbr, lra, and lrb instructions. ? programmable pull-up mos transistors
221 10.1.2 i/o control hd404358 series: r2 is a medium voltage nmos open drain i/o port and the d 0 to d 8 , r0, r1, r3, r4 and r8 ports are standard voltage i/o ports. the different port types have different circuit structures as follows. hd404358r series: the d 0 to d 8 , r0, r1, r2, r3, r4 and r8 are standard voltage i/o ports. (1) medium voltage nmos open drain i/o pin circuit (hd404358 series): r2 is a medium voltage nmos open drain i/o port and i/o through this port is controlled by the port data registers (pdr) and the data control registers (dcr). when the dcr bit corresponding to a given pin is 1, that pin functions as an output pin and when the value in the pdr is 0, the pin? nmos transistor turns on and the pin outputs a low level voltage. when the value in the pdr is 1 the pin goes to the high impedance state. when a given dcr bit is 0, the corresponding pin functions as an input pin. (2) standard voltage cmos three state i/o pin circuit: the pins in the d 0 to d 8 , r0, r1, r3, r4, and r8 ports (hd404358 series) or d 0 to d 8 , r0, r1, r2, r3, r4 and r8 ports (hd404358r) are standard voltage cmos three state i/o ports. i/o through these ports is controlled by the pdrs and the data control registers (dcd or dcr). when the dcd or dcr bit corresponding to a given pin is 1, that pin functions as an output pin and outputs the value in the pdr. when a given dcd or dcr bit is 0, the corresponding pin functions as an input pin. (3) pull-up mos control: the i/o pins in ports d 0 to d 8 and ports r0, r1, r3, r4, and r8 (hd404358 series) have built-in programmable pull-up mos transistors. this also applies to i/o pins in ports d 0 to d 8 and ports r0, r1, r2, r3, r4, and r8 (hd404358r series). when the miscellaneous register (mis) mis3 bit is set to 1 the pull-up mos transistor for pins for which the corresponding pdr is set to 1 will be turned on. thus the on/off state of each pin can be controlled independently by the pdrs. note that the pull-up mos transistor on/off settings are independent of the pin settings for use as built-in peripheral module pins. table 10-2 shows how register settings control the port i/o pins. table 10-2 register settings for i/o pin control mis3 0 1 dcd, dcr 0101 pdr 01010101 cmos buffer pmos on on nmos on on pull-up mos transistor on on
222 notes: 1. ? off 2. the pdr registers are not allocated addresses in ram. the pdr registers are accessed by special-purpose i/o instructions. (4) miscellaneous register (mis: $00c): mis is a 2-bit write-only register that controls the on/off states of the d, r0, and r3 port pin pull-up mos transistors and the on/off state of the r0 2 /so pin output buffer pmos transistor. mis is initialized to $0 on reset and in stop mode. 0 1 bit initial value read/write 3 mis3 0 w 0 2 mis2 0 w 1 r0 2 /so pin output buffer control 0 1 pull-up mos transistor control pmos transistor active (cmos output) pmos transistor off (nmos open drain output) all pull-up mos transistors off pull-up mos transistors active unused bit 3?ull-up mos transistor control (mis3): controls the on/off states of the pull-up mos transistors built into the i/o port pins. mis3 description 0 all pull-up mos transistors will be turned off. (initial value) 1 pull-up mos transistors for which the corresponding pdr bit is 1 will be turned on. bit 2?0 2 /so pin output buffer control (mis2): controls the on/off state of the r0 2 /so pin output buffer pmos transistor. mis2 description 0 the r0 2 /so pin output will be a cmos output. (initial value) 1 the r0 2 /so pin output will be an nmos open drain output.
223 10.1.3 i/o pin circuit structures table 10-3 shows the port and peripheral module pin circuits for the hd404358 series, and table 10-4 shows the port and peripheral module pin circuits for the hd404358r series. notes: 1. since the system is reset in stop mode, the built-in peripheral module selections are cleared. since the internal hlt signal goes to the low (active) level, the i/o pins go to the high impedance state. also, all the pull-up mos transistors are turned off. 2. in all low power modes other than stop mode, the internal hlt signal goes to the high level. table 10-3 input and output pin circuits class circuit applicable pins standard voltage pins i/o pins v cc v cc hlt mis3 dcd, dcr pdr pull-up control signal buffer control signal output data input control signal input data d 0 to d 8 , r0 0 , r0 1 , r0 3 , r1 0 to r1 3 , r3 0 to r3 3 , r4 0 to r4 3 , r8 0 to r8 3 v cc v cc hlt mis3 dcr pdr mis2 pull-up control signal buffer control signal output data input control signal input data r0 2
224 table 10-3 input and output pin circuits (cont) class circuit applicable pins standard voltage pins input pins input control signal input data ra 1 medium voltage pins i/o pins pdr dcr hlt input data output data input control signal r2 0 to r2 3
225 table 10-3 input and output pin circuits (cont) class circuit applicable pins standard voltage pins standard peripheral module pins i/o pins v cc v cc hlt mis3 sck sck pull-up control signal output data input data sck output pins v cc v cc hlt mis3 so mis2 pull-up control signal pmos control signal output data so v cc v cc hlt mis3 toc, buzz pull-up control signal output data toc, buzz
226 table 10-3 input and output pin circuits (cont) class circuit applicable pins standard voltage pins built-in peripheral module pins input pins si, int 0 , int 1 , evnb, stopc v cc hlt mis3 pdr input data si, int 0 , int 1 , evnb, stopc v cc hlt mis3 pdr a/d input input control an 0 to an 7
227 table 10-4 input and output pin circuits class circuit applicable pins standard voltage pins i/o pins v cc v cc input control signal hlt mis3 dcd, dcr pdr input data output data buffer control signal pull-up control signal d 0 to d 8 , r0 0 , r0 1 , r0 3 , r1 0 to r1 3 , r2 0 to r2 3 , r3 0 to r3 3 , r4 0 to r4 3 , r8 0 to r8 3 v cc v cc hlt mis3 dcd, dcr pdr mis2 input control signal input data output data buffer control signal pull-up control signal r0 2 input pins input control signal input data ra 1
228 table 10-4 input and output pin circuits (cont) class circuit applicable pins standard voltage pins standard peripheral module pins i/o pins v cc v cc hlt mis3 sck sck input control signal output data buffer control signal pull-up control signal sck output pins v cc v cc hlt mis3 so pmos control signal mis2 output data buffer control signal pull-up control signal so v cc v cc hlt mis3 toc, buzz output data buffer control signal pull-up control signal toc, buzz
229 table 10-4 input and output pin circuits (cont) class circuit applicable pins standard voltage pins standard peripheral module pins input pins si, int 0 , int 1 ,evnb, stopc v cc hlt mis3 pdr si, int 0 , int 1 , evnb, stopc a/d input input control v cc hlt mis3 pdr an 0 to an 7
230 10.1.4 port states in low power modes the d 0 to d 4 pins and the r0, r3, and r4 port pins have shared functions as input or output pins for built-in peripheral modules. in standby mode, since the cpu stops, the pins selected as output ports maintain their immediately prior output values. also, pins selected for use by built-in peripheral modules that operate in standby mode continue to operate. (output pins used by modules that stop in standby mode maintain their immediately prior output values.) see section 5, ?ow power modes? for details on which built-in peripheral modules can operate in each mode. table 10-5 lists the port states in the low power modes. table 10-5 port states in low power modes low power mode port states standby mode pins maintain their values immediately prior to entering standby mode. stop mode built-in peripheral function selections are cleared, and the port and peripheral function i/o pins go to the high impedance state. 10.1.5 handling unused pins i/o pins that are unused in user systems must be tied to a fixed potential, since floating i/o pins can cause noise that can interfere with lsi operation. the built-in pull-up mos transistors can be used to pull up unused pins to v cc . alternatively, unused pins can be pulled up to v cc with external resistors of about 100 k ? . application programs should maintain the pdr, dcd and dcr contents for unused pins at their reset state values. also note that unused pins must not be selected for use as peripheral function i/o pins.
231 10.2 d port 10.2.1 overview the d port of the hd404358 series consists of nine i/o ports (d 0 to d 8 ) that can be accessed in 1-bit units. the d port of the hd404358r series consists of nine i/o ports (d 0 to d 8 ; of which d 5 to d 8 are capable of handling high current levels of up to 15 ma) that can be accessed in 1-bit units. the output levels on the pins d 0 to d 8 can be set to low or high by accessing the port in one-bit units with the sed, sedd, red, and redd output instructions. the output data is stored in the pdr for each pin. the level on each of the pins d 0 to d 8 can be tested in one-bit units with the td and tdd input instructions. the dcd registers are used to turn the d port output buffers on or off. when the dcd bit corresponding to a given pin is 1, the data in the corresponding pdr will be output from that pin. the on/off states of the output buffers can be controlled individually for each d port pin. the dcd registers are allocated in the ram address space. the pins d 0 to d 4 have shared functions as built-in peripheral module pins. pmrb is used to switch these functions. figure 10-1 shows the structure of the d port. d 0 /int 0 (i/o or input) d 1 /int 1 (i/o or input) d 2 /evnb (i/o or input) d 3 /buzz (i/o or output) d 4 / stopc (i/o or input) d 5 (i/o) d 6 (i/o) d 7 (i/o) d 8 (i/o) high current pins (hd404358r series) d port figure 10-1 d port structure
232 10.2.2 register configuration and descriptions table 10-6 shows the configuration of the d port registers. table 10-6 d port register configuration address register symbol r/w initial value port data registers pdr w * 1 $02c data control registers dcd0 w $0 $02d dcd1 w $0 $02e dcd2 w ---0 $004 port mode register a pmra w $0 $024 port mode register b pmrb w $0 note: * the sed, sedd, red, and redd instructions can be used to write to the pdrs. (1) port data registers (pdr): each of the i/o pins d 0 to d 8 includes a built-in pdr. when a sed or sedd instruction is executed for one of the pins d 0 to d 8 the corresponding pdr is set to 1, and when a red or redd instruction is executed, the corresponding pdr is cleared to 0. when bits in dcd0 to dcd2 are set to 1, the output buffers for the corresponding pins will be turned on and the values in the pdrs will be output from those pins. the pdrs are cleared to 1 on reset and in stop mode.
233 (2) data control registers (dcd0 to dcd2: $02c, $02d, $02e) dcd2: $02e dcd1: $02d bit initial value read/write 3 0 dcd20 0 w 2 1 bit initial value read/write 3 dcd13 0 w 0 dcd10 0 w 2 dcd12 0 w 1 dcd11 0 w dcd0: $02c bit initial value read/write 3 dcd03 0 w 0 dcd00 0 w 2 dcd02 0 w 1 dcd01 0 w bits in dcd0 to dcd2 description 0 the output buffer (cmos buffer) is turned off and the output goes to the high impedance state. (initial value) 1 the output buffer is turned on and the corresponding pdr value is output. the table below lists the correspondence between the bits in dcd0 to dcd2 and the d port pins. bit register bit 3 bit 2 bit 1 bit 0 dcd0 d 3 d 2 d 1 d 0 dcd1 d 7 d 6 d 5 d 4 dcd2 d 8
234 (3) port mode register a (pmra: $004): pmra is a 4-bit write-only register whose pmra3 bit switches the function of the d 3 /buzz pin. this section describes the function of the pmra3 bit. see section 10.3.2 (3), ?ort mode register a (pmra)? for details on the pmra2 to pmra0 bits. bit initial value read/write 3 pmra3 0 w 0 pmra0 0 w 2 pmra2 0 w 1 pmra1 0 w 0 1 r0 3 /toc pin function switch 0 1 r0 1 /si pin function switch 0 1 r0 2 /so pin function switch 0 1 d 3 /buzz pin function switch r0 3 i/o pin toc output pin r0 1 i/o pin si input pin r0 2 i/o pin so output pin d 3 i/o pin buzz output pin bit 3? 3 /buzz pin function switch (pmra3): selects whether the d 3 /buzz pin functions as the d 3 i/o pin or as the alarm output pin (buzz). pmra3 description 0 the d 3 /buzz pin functions as the d 3 i/o pin. (initial value) 1 the d 3 /buzz pin functions as the buzz output pin.
235 (4) port mode register b (pmrb: $024): pmrb is a 4-bit write-only register that switches the d port i/o pin shared functions. bit initial value read/write 3 pmrb3 0 w 0 pmrb0 0 w 2 pmrb2 0 w 1 pmrb1 0 w 0 1 d 2 /evnb pin function switch 0 1 d 1 /int 1 pin function switch 0 1 d 0 /int 0 pin function switch 0 1 d 4 / stopc pin function switch d 2 i/o pin evnb input pin d 1 i/o pin int 1 input pin d 0 i/o pin int 0 input pin d 4 i/o pin stopc input pin bit 3? 4 / stopc pin function switch (pmrb3): selects whether the d 4 / stopc pin is used as the d 4 i/o pin or as the stop mode clear pin ( stopc ). pmrb3 description 0 the d 4 / stopc pin functions as the d 4 i/o pin. (initial value) 1 the d 4 / stopc pin functions as the stopc input pin. bit 2? 2 /evnb pin function switch (pmrb2): selects whether the d 2 /evnb pin is used as the d 2 i/o pin or as the timer b event count input pin (evnb). pmrb2 description 0 the d 2 /evnb pin functions as the d 2 i/o pin. (initial value) 1 the d 2 /evnb pin functions as the evnb input pin.
236 bit 1? 1 / int 1 pin function switch (pmrb1): selects whether the d 1 / int 1 pin is used as the d 1 i/o pin or as external interrupt 1 input pin ( int 1 ). pmrb1 description 0 the d 1 / int 1 pin functions as the d 1 i/o pin. (initial value) 1 the d 1 / int 1 pin functions as the int 1 input pin. bit 0? 0 / int 0 pin function switch (pmrb0): selects whether the d 0 / int 0 pin is used as the d 0 i/o pin or as external interrupt 0 input pin ( int 0 ). pmrb0 description 0 the d 0 / int 0 pin functions as the d 0 i/o pin. (initial value) 1 the d 0 / int 0 pin functions as the int 0 input pin.
237 10.2.3 pin functions the functions of the pins d 0 to d 8 are switched by register settings as shown in table 10-7. table 10-7 d 0 to d 8 port pin functions pin pin functions and selection methods d 0 / int 0 the pin function is switched as shown below by the pmrb pmrb0 bit and the dcd0 dcd00 bit. pmrb 0 1 dcd00 0 1 pin function d 0 input pin d 0 output pin int 0 input pin d 1 / int 1 the pin function is switched as shown below by the pmrb pmrb1 bit and the dcd0 dcd01 bit. pmrb1 0 1 dcd01 0 1 pin function d 1 input pin d 1 output pin int 1 input pin d 2 /evnb the pin function is switched as shown below by the pmrb pmrb2 bit and the dcd0 dcd02 bit. pmrb2 0 1 dcd02 0 1 pin function d 2 input pin d 2 output pin evnb input pin d 3 /buzz the pin function is switched as shown below by the pmra pmra3 bit and the dcd0 dcd03 bit. pmra3 0 1 dcd03 0 1 pin function d 3 input pin d 3 output pin buzz output pin d 4 / stopc the pin function is switched as shown below by the pmrb pmrb3 bit and the dcd1 dcd10 bit. pmrb3 0 1 dcd10 0 1 pin function d 4 input pin d 4 output pin stopc input pin
238 table 10-7 d 0 to d 8 port pin functions (cont) pin pin functions and selection methods d 5 the pin function is switched as shown below by the dcd1 dcd11 bit. dcd11 0 1 pin function d 5 input pin d 5 output pin d 6 the pin function is switched as shown below by the dcd1 dcd12 bit. dcd12 0 1 pin function d 6 input pin d 6 output pin d 7 the pin function is switched as shown below by the dcd1 dcd13 bit. dcd13 0 1 pin function d 7 input pin d 7 output pin d 8 the pin function is switched as shown below by the dcd2 dcd20 bit. dcd20 0 1 pin function d 8 input pin d 8 output pin
239 10.3 r ports 10.3.1 overview the r port consists of the six 4-bit i/o ports r0 to r4 and r8 and the 1-bit input port ra 1 . these ports are accessed in 4-bit units. r0, r1, r3, r4, and r8 are standard voltage cmos three state i/o ports and r2 is a medium voltage nmos open drain i/o port of hd404358 series. on the hd404358r series pins r0, r1, r2, r3, r4, and r8 are cmos three state standard voltage i/o pins. of these, r0, r1, r2, and r8 can handle high current levels of up to 15 ma. the individual ports r0 to r4 and r8 are accessed in 4-bit units with the lra and lrb output instructions to control the output levels (high or low) on each pin. output data is stored in the pdr built into each pin. similarly, the lar and lbr input instructions can be used to access the r ports in 4-bit units to read the input levels on the port pins. the ra1 input-only port consists of a single bit. the values of bits 3, 2, and 0 are undefined when this port is accessed by the input instructions. dcr registers are used to control on/off states of the r port output buffers. when the dcr bit corresponding to a pin in an r port is set to 1, the contents of the pdr corresponding to that pin is output from the pin. thus the output buffer on/off states can be controlled on an individual pin basis for the r port pins. the dcr registers are allocated in the ram address space. the r0, r3, and r4 port pins have shared functions as built-in peripheral module pins. register settings are used to switch these functions. (see table 10-8.) figure 10-2 shows the r port pin structure.
240 r0 0 / sck (i/o or i/o) r0 1 /si (i/o or input) r0 2 /so (i/o or output) r0 3 /toc (i/o or output) r3 0 /an 0 (i/o or input) r3 1 /an 1 (i/o or input) r3 2 /an 2 (i/o or input) r3 3 /an 3 (i/o or input) r4 0 /an 4 (i/o or input) r4 1 /an 5 (i/o or input) r4 2 /an 6 (i/o or input) r4 3 /an 7 (i/o or input) ra 1 (input) r1 0 (i/o) r1 1 (i/o) r1 2 (i/o) r1 3 (i/o) r8 0 (i/o) r8 1 (i/o) r8 2 (i/o) r8 3 (i/o) r0 port r4 port r1 port r3 port r8 port ra port r2 0 (i/o) r2 1 (i/o) r2 2 (i/o) r2 3 (i/o) r2 port medium voltage pins hd404358r series r0 port r0 0 / sck r0 1 /si r0 2 /so r0 3 /toc (i/o or i/o) (i/o or input) (i/o or output) (i/o or output) r2 port r2 0 r2 1 r2 2 r2 3 (i/o) (i/o) (i/o) (i/o) r4 port r4 0 /an 4 r4 1 /an 5 r4 2 /an 6 r4 3 /an 7 (i/o or input) (i/o or input) (i/o or input) (i/o or input) ra port ra 1 (input) r1 port r3 port r3 0 /an 0 r3 1 /an 1 r3 2 /an 2 r3 3 /an 3 (i/o or input) (i/o or input) (i/o or input) (i/o or input) nmos high current pins nmos high current pins r1 0 r1 1 r1 2 r1 3 (i/o) (i/o) (i/o) (i/o) r8 0 r8 1 r8 2 r8 3 (i/o) (i/o) (i/o) (i/o) r8 port nmos high current pins hd404358 series figure 10-2 r port structure
241 10.3.2 register configuration and descriptions table 10-8 shows the configuration of the r port related registers. table 10-8 r port register configuration address register symbol r/w initial value port data registers pdr w * 1 $030 data control registers dcr0 w $0 $031 dcr1 w $0 $032 dcr2 w $0 $033 dcr3 w $0 $034 dcr4 w $0 $038 dcr8 w $0 $004 port mode register a pmra w $0 $005 serial mode register smr w $0 $019 a/d mode register 1 amr1 w $0 $01a a/d mode register 2 amr2 w --00 note: * the lra and lrb instructions are used to write to the pdr registers. (1) port data registers (pdr): all the i/o pins in ports r0 to r4 and r8 include a pdr that holds the output data. when an lra or an lrb instruction is executed for one of ports r0 to r4 or r8, the contents of the accumulator (a) or the b register (b) are transferred to the specified r port pdrs. when bits in dcr0 to dcr4, or dcr8 are set to 1, the output buffers for the corresponding pins in port r0 to r4 or r8 will be turned on and the values in the pdrs will be output from those pins. the pdr registers are set to 1 on reset and in stop mode.
242 (2) data control registers (dcr0 to dcr4, dcr8: $030, $031, $032, $033, $034, $038) dcr2: $032 dcr1: $031 bit initial value read/write 3 dcr23 0 w 0 dcr20 0 w 2 dcr22 0 w 1 dcr21 0 w bit initial value read/write 3 dcr13 0 w 0 dcr10 0 w 2 dcr12 0 w 1 dcr11 0 w dcr0: $030 bit initial value read/write 3 dcr03 0 w 0 dcr00 0 w 2 dcr02 0 w 1 dcr01 0 w dcr8: $038 dcr4: $034 bit initial value read/write 3 dcr83 0 w 0 dcr80 0 w 2 dcr82 0 w 1 dcr81 0 w bit initial value read/write 3 dcr43 0 w 0 dcr40 0 w 2 dcr42 0 w 1 dcr41 0 w dcr3: $033 bit initial value read/write 3 dcr33 0 w 0 dcr30 0 w 2 dcr32 0 w 1 dcr31 0 w
243 bits in dcr0 to dcr4, and dcr8 description 0 the output buffer (cmos buffer) is turned off and the output goes to the high impedance state. (initial value) 1 ? the cmos three state output buffer is turned on and the corresponding pdr value is output. ? for medium voltage nmos open drain pins (r2) of hd404358 series, when the pdr is 0 a low level is output. when the pdr is 1, the pin goes to the high impedance state. the table below lists the correspondence between the bits in dcr0 to dcr4 and dcr8 and the port r0 to r4 and r8 pins. bit register bit 3 bit 2 bit 1 bit 0 dcr0 r0 3 r0 2 r0 1 r0 0 dcr1 r1 3 r1 2 r1 1 r1 0 dcr2 r2 3 r2 2 r2 1 r2 0 dcr3 r3 3 r3 2 r3 1 r3 0 dcr4 r4 3 r4 2 r4 1 r4 0 dcr8 r8 3 r8 2 r8 1 r8 0
244 (3) port mode register a(pmra: $004): pmra is a 4-bit write-only register whose bits pmra2 to pmra0 switch the functions of the port r0 shared function pins. this section describes the bits pmra2 to pmra0. see section 10.2.2 (3), ?ort mode register a (pmra)? for details on the pmra3 bit. bit initial value read/write 3 pmra3 0 w 0 pmra0 0 w 2 pmra2 0 w 1 pmra1 0 w 0 1 r0 3 /toc pin function switch 0 1 r0 1 /si pin function switch 0 1 r0 2 /so pin function switch 0 1 d 3 /buzz pin function switch r0 3 i/o pin toc output pin r0 1 i/o pin si input pin r0 2 i/o pin so output pin d 3 i/o pin buzz output pin bit 2?0 3 /toc pin function switch (pmra2): selects whether the r0 3 /toc pin functions as the r0 3 i/o pin or as the timer c output pin (toc). pmra2 description 0 the r0 3 /toc pin functions as the r0 3 i/o pin. (initial value) 1 the r0 3 /toc pin functions as the toc output pin.
245 bit 1?0 1 /si pin function switch (pmra1): selects whether the r0 1 /si pin functions as the r0 1 i/o pin or as the serial reception data input pin (si). pmra1 description 0 the r0 1 /si pin functions as the r01 i/o pin. (initial value) 1 the r0 1 /si pin functions as the si input pin. bit 0?0 2 /so pin function switch (pmra0): selects whether the r0 2 /so pin functions as the r0 2 i/o pin or as the serial transmission data output pin (so). pmra0 description 0 the r0 2 /so pin functions as the r0 2 i/o pin. (initial value) 1 the r0 2 /so pin functions as the so output pin.
246 (4) serial mode register (smr: $005): smr is a 4-bit write-only register whose smr3 bit switches the r0 0 / sck pin function. this section only describes the smr3 bit. see section 20.2.1, ?erial mode register (smr)?for details on bits smr2 to smr0. bit initial value read/write 3 smr3 0 w 0 smr0 0 w 2 smr2 0 w 1 smr1 0 w 0 1 r0 0 / sck pin function switch r0 0 i/o pin sck i/o pin transfer clock selection bit 3?0 0 / sck pin function switch (smr3): selects whether the r0 0 / sck pin functions as the r0 0 i/o pin or as the serial interface transfer clock i/o pin. smr3 description 0 the r0 0 / sck pin functions as the r0 0 i/o pin. (initial value) 1 the r0 0 / sck pin functions as the sck i/o pin.
247 (5) a/d mode register 1 (amr1: $019): amr1 is a 4-bit write-only register that switches the functions of the r3 port shared function pins. bit initial value read/write 3 amr13 0 w 0 amr10 0 w 2 amr12 0 w 1 amr11 0 w 0 1 r3 2 /an 2 pin function switch 0 1 r3 1 /an 1 pin function switch 0 1 r3 0 /an 0 pin function switch 0 1 r3 3 /an 3 pin function switch r3 2 i/o pin an 2 input pin r3 1 i/o pin an 1 input pin r3 0 i/o pin an 0 input pin r3 3 i/o pin an 3 input pin bit 3?3 3 /an 3 pin function switch (amr13): selects whether the r3 3 /an 3 pin functions as the r3 3 i/o pin or as the a/d converter channel 3 input pin an 3 . amr13 description 0 the r3 3 /an 3 pin functions as the r3 3 i/o pin. (initial value) 1 the r3 3 /an 3 pin functions as the an 3 input pin. bit 2?3 2 /an 2 pin function switch (amr12): selects whether the r3 2 /an 2 pin functions as the r3 2 i/o pin or as the a/d converter channel 2 input pin an 2 . amr12 description 0 the r3 2 /an 2 pin functions as the r3 2 i/o pin. (initial value) 1 the r3 2 /an 2 pin functions as the an 2 input pin.
248 bit 1?3 1 /an 1 pin function switch (amr11): selects whether the r3 1 /an 1 pin functions as the r3 1 i/o pin or as the a/d converter channel 1 input pin an 1 . amr11 description 0 the r3 1 /an 1 pin functions as the r3 1 i/o pin. (initial value) 1 the r3 1 /an 1 pin functions as the an 1 input pin. bit 0?3 0 /an 0 pin function switch (amr10): selects whether the r3 0 /an 0 pin functions as the r3 0 i/o pin or as the a/d converter channel 0 input pin an 0 . amr10 description 0 the r3 0 /an 0 pin functions as the r3 0 i/o pin. (initial value) 1 the r3 0 /an 0 pin functions as the an 0 input pin.
249 (6) a/d mode register 2 (amr2: $1a): amr2 is a 2-bit write-only register whose amr21 bit switches the functions of all four bits of the r4 port (r4 0 to r4 3 ) to be a/d converter input channels (an 4 to an 7 ). this section describes the amr21 bit. see section 15.2.2, ?/d mode register 2 (amr2)? for details on the amd20 bit. bit initial value read/write 3 0 amr20 0 w 2 1 amr21 0 w 0 1 r4 0 /an 4 to r4 3 /an 7 pin function switch 0 1 a/d conversion time r4 0 to r4 3 i/o pins an 4 to an 7 input pins 34 t cyc 67 t cyc unused bit 1?4 0 /an 4 to r4 3 /an 7 pin function switch (amr21): selects whether the r4 0 /an 4 to r4 3 /an 7 pins function as the r4 0 to r4 3 i/o pins or as the a/d converter channel 4 to 7 input pins (an 4 to an 7 ). amr21 description 0 the r4 0 /an 4 to r4 3 /an 7 pins function as the r4 0 to r4 3 i/o pins. (initial value) 1 the r4 0 /an 4 to r4 3 /an 7 pins function as the an 4 to an 7 input pins.
250 10.3.3 pin functions the pin functions of the r port pins are switched by register settings as shown in table 10-9. table 10-9 r port pin functions pin pin functions and selection methods r0 0 / sck the pin function is switched by the smr smr3 bit and the dcr0 dcr00 bit as shown below. smr3 0 1 dcr00 0 1 pin function r0 0 input pin r0 0 output pin sck i/o pin r0 1 /si the pin function is switched by the pmra pmra1 bit and the dcr0 dcr01 bit as shown below. pmra1 0 1 dcr01 0 1 pin function r0 1 input pin r0 1 output pin si input pin r0 2 /so the pin function is switched by the pmra pmra0 bit and the dcr0 dcr02 bit as shown below. pmra0 0 1 dcr02 0 1 pin function r0 2 input pin r0 2 output pin so output pin r0 3 /toc the pin function is switched by the pmra pmra2 bit and the dcr0 dcr03 bit as shown below. pmra2 0 1 dcr03 0 1 pin function r0 3 input pin r0 3 output pin toc output pin
251 table 10-9 r port pin functions (cont) pin pin functions and selection methods r1 0 the pin function is switched by the dcr1 dcr10 bit as shown below. dcr10 0 1 pin function r1 0 input pin r1 0 output pin r1 1 the pin function is switched by the dcr1 dcr11 bit as shown below. dcr11 0 1 pin function r1 1 input pin r1 1 output pin r1 2 the pin function is switched by the dcr1 dcr12 bit as shown below. dcr12 0 1 pin function r1 2 input pin r1 2 output pin r1 3 the pin function is switched by the dcr1 dcr13 bit as shown below. dcr13 0 1 pin function r1 3 input pin r1 3 output pin r2 0 the pin function is switched by the dcr2 dcr20 bit as shown below. dcr20 0 1 pin function r2 0 input pin r2 0 output pin * r2 1 the pin function is switched by the dcr2 dcr21 bit as shown below. dcr21 0 1 pin function r2 1 input pin r2 1 output pin * r2 2 the pin function is switched by the dcr2 dcr22 bit as shown below. dcr22 0 1 pin function r2 2 input pin r2 2 output pin * note: * r2 0 to r2 3 are medium voltage nmos open drain i/o pins of hd404358 series. these pins go to the high impedance state when their pdr is set to 1.
252 table 10-9 r port pin functions (cont) pin pin functions and selection methods r2 3 the pin function is switched by the dcr2 dcr23 bit as shown below. dcr23 0 1 pin function r2 3 input pin r2 3 output pin * r3 0 /an 0 the pin function is switched by the amr1 amr10 bit and the dcr3 dcr30 bit as shown below. amr10 0 1 dcr30 0 1 pin function r3 0 input pin r3 0 output pin an 0 input pin r3 1 /an 1 the pin function is switched by the amr1 amr11 bit and the dcr3 dcr31 bit as shown below. amr11 0 1 dcr31 0 1 pin function r3 1 input pin r3 1 output pin an 1 input pin r3 2 /an 2 the pin function is switched by the amr1 amr12 bit and the dcr3 dcr32 bit as shown below. amr12 0 1 dcr32 0 1 pin function r3 2 input pin r3 2 output pin an 2 input pin r3 3 /an 3 the pin function is switched by the amr1 amr13 bit and the dcr3 dcr33 bit as shown below. amr13 0 1 dcr33 0 1 pin function r3 3 input pin r3 3 output pin an 3 input pin note: * r2 0 to r2 3 are medium voltage nmos open drain i/o pins of hd404358 series. these pins go to the high impedance state when their pdr is set to 1.
253 table 10-9 r port pin functions (cont) pin pin functions and selection methods r4 0 /an 4 the pin function is switched by the amr2 amr21 bit and the dcr4 dcr40 bit as shown below. amr21 0 1 dcr40 0 1 pin function r4 0 input pin r4 0 output pin an 4 input pin r4 1 /an 5 the pin function is switched by the amr2 amr21 bit and the dcr4 dcr41 bit as shown below. amr21 0 1 dcr41 0 1 pin function r4 1 input pin r4 1 output pin an 5 input pin r4 2 /an 6 the pin function is switched by the amr2 amr21 bit and the dcr4 dcr42 bit as shown below. amr21 0 1 dcr42 0 1 pin function r4 2 input pin r4 2 output pin an 6 input pin r4 3 /an 7 the pin function is switched by the amr2 amr21 bit and the dcr4 dcr43 bit as shown below. amr21 0 1 dcr43 0 1 pin function r4 3 input pin r4 3 output pin an 7 input pin
254 table 10-9 r port pin functions (cont) pin pin functions and selection methods r8 0 the pin function is switched by the dcr8 dcr80 bit as shown below. dcr80 0 1 pin function r8 0 input pin r8 0 output pin r8 1 the pin function is switched by the dcr8 dcr81 bit as shown below. dcr81 0 1 pin function r8 1 input pin r8 1 output pin r8 2 the pin function is switched by the dcr8 dcr82 bit as shown below. dcr82 0 1 pin function r8 2 input pin r8 2 output pin r8 3 the pin function is switched by the dcr8 dcr83 bit as shown below. dcr83 0 1 pin function r8 3 input pin r8 3 output pin
255 10.4 usage notes keep the following points in mind when using the i/o ports. ? when the mis mis2 bit is set to 1, the r0 2 /so pin will be an nmos open drain output regardless of whether it is selected for use as the r0 2 pin or as the so pin by the pmra pmra0 bit. ? i/o pins that are unused in user systems must be tied to a fixed potential, since floating i/o pins can cause noise that can interfere with lsi operation. the built-in pull-up mos transistors can be used to pull up unused pins to v cc . alternatively, unused pins can be pulled up to v cc with external resistors of about 100 k ? . application programs should maintain the pdr, dcd and dcr contents for unused pins at their reset state values. also note that unused pins must not be selected for use as peripheral function i/o pins. ? when the mis mis3 bit is set to 1 (pull-up mos transistors active) and the pdr for an r port/analog input shared function pin has the value 1, the mos transistor for the corresponding pin will not be turned off by selecting the analog input function with the amr1 or amr2 register. to use an r port/analog input shared function pin as an analog input when the pull-up mos transistors are active, always clear the pdr for the corresponding pin to 0 first and then turn off the pull-up mos transistor. (note that the pdr registers are set to 1 immediately following a reset.) figure 10-3 shows the circuit for the r port/analog input shared function pins. amr1 and amr2 are used to set the port outputs to high impedance. acr is used to switch the analog input channel. the states of the r port/analog input shared function pins are set, as shown in table 10-10, by the combination of the amr1 or amr2 register, the mis3 bit, the dcr, and the pdr settings.
256 v cc v cc hlt mis3 dcr pdr amr (a/d mode register setting value) acr (a/d channel register setting value) input control signal input data a/d input figure 10-3 r port/analog input shared function pin circuit
257 table 10-10 program control of the r port/analog input shared function pins corresponding bit in amr1 or amr2 0 (r port selected) mis3 bit 0 1 dcr 0101 pdr 01010101 cmos buffer pmos on on nmos on on pull-up mos transistor on on note: : off corresponding bit in amr1 or amr2 1 (analog input selected) mis3 bit 0 1 dcr 0101 pdr 01010101 cmos buffer pmos nmos pull-up mos transistor on on note: : off ? in the hd404358 series evaluation chip set, the circuits for the medium voltage nmos open drain pins (the r2 port pins) differ from the ztat and the mask rom microcomputer versions as shown in figure 10-4. although the outputs in both the ztat and mask rom versions can be set to high impedance by the combinations listed in table 10-11, these outputs cannot be set to high impedance in the evaluation chip set. please keep this in mind when using the evaluation chip set. figure 10-4 shows the circuit for the medium voltage nmos open drain pins.
258 pdr dcr hlt v cc v cc hlt mis3 dcr pdr input data input control signal input data input control signal (a) evaluation chip pin circuit structure (b) ztat and mask rom pin circuit structure figure 10-4 medium voltage nmos open drain pin circuits table 10-11 ztat and mask rom microcomputer medium voltage pin high impedance control dcr pdr description 0 * high impedance output (initial value) 1 0 nmos buffer on. low level output 1 high impedance output note: * don t care
259 section 11 i/o ports (hd404339 series) 11.1 overview 11.1.1 features the hd404339 series i/o ports have the following features. ? the 14 pins d 0 to d 13 as well as the r1, r2, r8, and r9 ports are high voltage i/o pins. also, ra 1 is a high voltage input pin. ? r0, r3, and r4 are standard voltage i/o pins that, in output mode, are cmos three state outputs. ? certain i/o pins (d 0 to d 4 , and the pins in the r0 and r3 to r5 ports) are shared with the built- in peripheral modules, such as timers and the serial interface. setting these pins for use with the built-in peripheral modules takes priority over their setting for use as d or r port pins. ? register settings are used to select input or output for i/o pins and to select the i/o port or peripheral module usage for shared function pins. ? of the built-in peripheral module pins, the d 3 /buzz pin is a pmos open drain output. all other output pins are cmos three state outputs. however, the r0 2 /so pin can be selected to be an nmos open drain output by setting a register. ? since the system is reset in stop mode, the built-in peripheral module selections are cleared and the i/o pins go to the high impedance state. ? the cmos output pins have built-in programmable pull-up mos transistors. the on/off state of these transistors can be controlled by register settings on an individual basis. note that the pull-up mos transistor on/off settings are independent of the pin settings for use as built-in peripheral module pins. table 11-1 provides an overview of the hd404339 series port functions.
260 table 11-1 port functions port overview pin shared function function switching register d 0 to d 13 d 0 / int 0 external interrupt input 0 pmrb d 1 / int 1 external interrupt input 1 d 2 /evnb timer b event input d 3 /buzz alarm output pmra d 4 / stopc stop mode clear pmrb d 5 to d 13 r0 r0 0 / sck transfer clock i/o smr r0 1 /si serial reception data input pmra r0 2 /so serial transmission data output r0 3 /toc timer c output r3 r3 0 /an 0 analog input channel 0 amr1 r3 1 /an 1 analog input channel 1 r3 2 /an 2 analog input channel 2 r3 3 /an 3 analog input channel 3 r4 r4 0 /an 4 analog input channel 4 amr2 r4 1 /an 5 analog input channel 5 r4 2 /an 6 analog input channel 6 r4 3 /an 7 analog input channel 7 r5 r5 0 /an 8 analog input channel 8 amr2 r5 1 /an 9 analog input channel 9 r5 2 /an 10 analog input channel 10 r5 3 /an 11 analog input channel 11 r6, r7 r6 0 to r6 3 r7 0 to r7 2 ? high voltage i/o port ? accessed in bit units ? accessed with the sed, sedd, red, redd, td, and tdd instructions. ? pull-down resistors available as a mask option. ? standard voltage i/o ports ? accessed in 4-bit units. ? accessed with the lar, lbr, lra, and lrb instructions. ? programmable pull-up mos transistors
261 table 11-1 port functions (cont) port overview pin shared function function switching register r1, r2, r8, r9 ? high voltage i/o ports ? accessed in 4-bit units. ? accessed with the lar, lbr, lra, and lrb instructions. ? pull-down resistors available as a mask option. r1 0 to r1 3 r2 0 to r2 3 r8 0 to r8 3 r9 0 to r9 3 ra ? high voltage input port (1 bit) ? accessed with the lar and lbr instructions. ra 1 /v disp high voltage pin output power supply mask option 11.1.2 i/o control the d, r1, r2, r8, and r9 ports are high voltage i/o ports, ra 1 is a 1-bit high voltage input port, and r0 and r3 to r7 are standard voltage i/o ports. the different port types have different circuit structures as follows. (1) high voltage i/o pin circuit: the d, r1, r2, r8, and r9 port pins are high voltage i/o pins that have no i/o switching function. when a port data register is set to 1, the pmos transistor turns on and a high level voltage is output from the pin. when the pdr is set to 0, the pin goes to the open state. if the built-in pull-down resistor mask option was selected, the v disp voltage is output. when external signals are applied, applications must set the pdr value to 0 so that the external (input) and internal (output) signals do not collide at the pin. note that there are no pull-down resistors on the high voltage i/o pins in the ztat versions of these microcomputers. (2) standard voltage cmos three state i/o pin circuit: the pins in the r0 and r3 to r7 ports are standard voltage cmos three state i/o ports. i/o through these ports is controlled by the pdrs and the data control registers (dcr). when the dcr bit corresponding to a given pin is 1, that pin functions as an output pin and outputs the value in the pdr. when a given dcr bit is 0, the corresponding pin functions as an input pin.
262 (3) pull-up mos control: each i/o pin in the r0 and r3 to r7 ports has a built-in programmable pull-up mos transistor. when the miscellaneous register (mis) mis3 bit is set to 1 the pull-up mos transistor for pins for which the corresponding pdr is set to 1 will be turned on. thus the on/off state of each pin can be controlled independently by the pdrs. note that the pull- up mos transistor on/off settings are independent of the pin settings for use as built-in peripheral module pins. table 11-2 shows how register settings control the port i/o pins. table 11-2 register settings for i/o pin control mis3 0 1 dcr 0101 pdr 01010101 cmos buffer pmos on on nmos on on pull-up mos transistor on on notes: 1. ? off 2. the pdr registers are not allocated addresses in ram. the pdr registers are accessed by special-purpose i/o instructions.
263 (4) miscellaneous register (mis: $00c): mis is a 4-bit write-only register that controls the on/off states of the r0 and r3 to r7 port pin pull-up mos transistors, the on/off state of the r0 2 /so pin output buffer pmos transistor, the interrupt frame period in watch and subactive modes, and the oscillator stabilization period when a low power mode is cleared. mis is initialized to $0 on reset and in stop mode. this section describes the mis2 and mis3 bits. refer to section 6.2.1, ?iscellaneous register (mis)? for details on the mis0 and mis1 bits. bit initial value read/write 3 mis3 0 w 0 mis0 0 w 2 mis2 0 w 1 mis1 0 w 0 1 r0 2 /so pin output buffer control 0 1 pull-up mos transistor control pmos transistor active (cmos output) pmos transistor off (nmos open drain output) all pull-up mos transistors off pull-up mos transistors active interrupt frame period and oscillator stabilization time settings bit 3?ull-up mos transistor control (mis3): controls the on/off states of the pull-up mos transistors built into the i/o port pins. mis3 description 0 all pull-up mos transistors will be turned off. (initial value) 1 pull-up mos transistors for which the corresponding pdr bit is 1 will be turned on. bit 2?0 2 /so pin output buffer control (mis2): controls the on/off state of the r0 2 /so pin output buffer pmos transistor. mis2 description 0 the r0 2 /so pin output will be a cmos output. (initial value) 1 the r0 2 /so pin output will be an nmos open drain output.
264 11.1.3 i/o pin circuit structures table 11-3 shows the port and peripheral module pin circuits. notes: 1. since the system is reset in stop mode, the built-in peripheral module selections are cleared. since the internal hlt signal goes to the low (active) level, the i/o pins go to the high impedance state. also, all the pull-up mos transistors are turned off. 2. in all low power modes other than stop mode, the internal hlt signal goes to the high level. table 11-3 input and output pin circuits class circuit applicable pins standard voltage pins i/o pins v cc v cc hlt mis3 dcr pdr pull-up control signal buffer control signal output data input control signal input data r0 0 , r0 1 , r0 3 , r3 0 to r3 3 , r4 0 to r4 3 , r5 0 to r5 3 , r6 0 to r6 3 , r7 0 to r7 2 v cc v cc hlt mis3 dcr pdr mis2 pull-up control signal buffer control signal output data input control signal input data r0 2
265 table 11-3 input and output pin circuits (cont) class circuit applicable pins standard voltage pins standard peripheral module pins i/o pins v cc v cc hlt mis3 sck sck pull-up control signal output data input data sck output pins v cc v cc hlt mis3 so mis2 pull-up control signal pmos control signal output data so v cc v cc hlt mis3 toc pull-up control signal output data toc
266 table 11-3 input and output pin circuits (cont) class circuit applicable pins standard voltage pins built-in peripheral module pins input pins si v cc hlt mis3 pdr input data si v cc hlt mis3 pdr a/d input input control an 0 to an 11
267 table 11-3 input and output pin circuits (cont) class circuit applicable pins high voltage pins i/o pins pins with pull-down resistors v cc hlt v disp pull-down resistor input control signal output data input data d 0 to d 13 , r1 0 to r1 3 , r2 0 to r2 3 , r8 0 to r8 3 , r9 0 to r9 3 pins without pull-down resistors * v cc hlt output data input control signal input data input pins input control signal input data ra 1 note: * the ztat versions of these microcomputers only support pins without pull-down resistors.
268 table 11-3 input and output pin circuits (cont) class circuit applicable pins high voltage pins built-in peripheral module pins output pins pins with pull-down resistors v cc hlt v disp output data pull-down resistor buzz pins without pull-down resistors * v cc hlt output data input pins pins with pull-down resistors int 0 , int 1 , evnb, stopc v cc hlt mis3 pdr v disp input data pull-down resistor int 0 , int 1 , evnb, stopc pins without pull-down resistors * v cc hlt mis3 pdr int 0 , int 1 , evnb, stop c note: * the ztat versions of these microcomputers only support pins without pull-down resistors.
269 11.1.4 port states in low power modes the d 0 to d 4 pins and the r0 and r3 to r5 port pins have shared functions as input or output pins for built-in peripheral modules. since the cpu stops in standby and watch modes, the pins selected as output ports maintain their immediately prior output values. also, pins selected for use by built-in peripheral modules that operate in standby or watch mode continue to operate. (output pins used by modules that stop in these modes maintain their immediately prior output values.) see section 6, ?ow power modes? for details on which built-in peripheral modules can operate in each mode. table 11-4 lists the port states in the low power modes. table 11-4 port states in low power modes low power mode port states standby mode, watch mode pins maintain their values immediately prior to entering standby or watch mode. stop mode built-in peripheral function selections are cleared, and the port and peripheral function i/o pins go to the high impedance state. 11.1.5 handling unused pins i/o pins that are unused in user systems must be tied to a fixed potential, since floating i/o pins can cause noise that can interfere with lsi operation. the following are examples of techniques that can prevent noise problems. high voltage pin: select ?o pull-down mos transistor (pmos open drain)?as the mask option and connect the pin to v cc on the user system printed circuit board. standard voltage pin: either use the built-in pull-up mos transistor to pull the pin up to v cc , or pull up the pin to v cc externally with a pull-up resistor of about 100 k ? . application programs should maintain the pdr and dcr contents for unused pins at their reset state values. also note that unused pins must not be selected for use as peripheral function i/o pins.
270 11.2 d port 11.2.1 overview the d port is a 14-pin high voltage i/o port (d 0 to d 13 ) that can be accessed in 1-bit units. the output levels on the pins d 0 to d 13 can be set to low or high by accessing the port in one-bit units with the sed, sedd, red, and redd output instructions. the output data is stored in the pdr for each pin. the level on each of the pins d 0 to d 13 can be tested in one-bit units with the td and tdd input instructions. the pins d 0 to d 4 have shared functions as built-in peripheral module pins. pmra and pmrb are used to switch these functions. figure 11-1 shows the structure of the d port. d 0 /int 0 (i/o or input) d 1 /int 1 (i/o or input) d 2 /evnb (i/o or input) d 3 /buzz (i/o or output) d 4 / stopc (i/o or input) d 5 (i/o) d 6 (i/o) d 7 (i/o) d 8 (i/o) d 9 (i/o) d 10 (i/o) d 11 (i/o) d 12 (i/o) d 13 (i/o) d port high voltage pins figure 11-1 d port structure
271 11.2.2 register configuration and descriptions table 11-5 shows the configuration of the d port registers. table 11-5 d port register configuration address register symbol r/w initial value port data registers pdr w * 0 $004 port mode register a pmra w $0 $024 port mode register b pmrb w $0 note: * the sed, sedd, red, and redd instructions can be used to write to the pdrs. (1) port data registers (pdr): each of the i/o pins d 0 to d 13 includes a built-in pdr. when a sed or sedd instruction is executed for one of the pins d 0 to d 13 the corresponding pdr is set to 1, and when a red or redd instruction is executed, the corresponding pdr is cleared to 0. the pdrs are cleared to 0 on reset and in stop mode.
272 (2) port mode register a (pmra: $004): pmra is a 4-bit write-only register whose pmra3 bit switches the function of the d 3 /buzz pin. this section describes the function of the pmra3 bit. see section 11.3.2 (3), ?ort mode register a (pmra)? for details on the pmra2 to pmra0 bits. bit initial value read/write 3 pmra3 0 w 0 pmra0 0 w 2 pmra2 0 w 1 pmra1 0 w 0 1 r0 3 /toc pin function switch 0 1 r0 1 /si pin function switch 0 1 r0 2 /so pin function switch 0 1 d 3 /buzz pin function switch r0 3 i/o pin toc output pin r0 1 i/o pin si input pin r0 2 i/o pin so output pin d 3 i/o pin buzz output pin bit 3? 3 /buzz pin function switch (pmra3): selects whether the d 3 /buzz pin functions as the d 3 i/o pin or as the alarm output pin (buzz). pmra3 description 0d 3 /buzz pin functions as the d 3 i/o pin. (initial value) 1d 3 /buzz pin functions as the buzz output pin.
273 (3) port mode register b (pmrb: $024): pmrb is a 4-bit write-only register that switches the d port i/o pin shared functions. bit initial value read/write 3 pmrb3 0 w 0 pmrb0 0 w 2 pmrb2 0 w 1 pmrb1 0 w 0 1 d 2 /evnb pin function switch 0 1 d 1 /int 1 pin function switch 0 1 d 0 /int 0 pin function switch 0 1 d 4 / stopc pin function switch d 2 i/o pin evnb input pin d 1 i/o pin int 1 input pin d 0 i/o pin int 0 input pin d 4 i/o pin stopc input pin bit 3? 4 / stopc pin function switch (pmrb3): selects whether the d 4 / stopc pin is used as the d 4 i/o pin or as the stop mode clear pin ( stopc ). pmrb3 description 0 the d 4 / stopc pin functions as the d 4 i/o pin. (initial value) 1 the d 4 / stopc pin functions as the stopc input pin. bit 2? 2 /evnb pin function switch (pmrb2): selects whether the d 2 /evnb pin is used as the d 2 i/o pin or as the timer b event count input pin (evnb). pmrb2 description 0 the d 2 /evnb pin functions as the d 2 i/o pin. (initial value) 1 the d 2 /evnb pin functions as the evnb input pin.
274 bit 1? 1 / int 1 pin function switch (pmrb1): selects whether the d 1 / int 1 pin is used as the d 1 i/o pin or as the external interrupt 1 input pin ( int 1 ). pmrb1 description 0 the d 1 / int 1 pin functions as the d 1 i/o pin. (initial value) 1 the d 1 / int 1 pin functions as the int 1 input pin. bit 0? 0 / int 0 pin function switch (pmrb0): selects whether the d 0 / int 0 pin is used as the d 0 i/o pin or as the external interrupt 0 input pin ( int 0 ). pmrb0 description 0 the d 0 / int 0 pin functions as the d 0 i/o pin. (initial value) 1 the d 0 / int 0 pin functions as the int 0 input pin.
275 11.2.3 pin functions the pin functions of the pins d 0 to d 4 are switched by register settings as shown in table 11-6. table 11-6 d 0 to d 4 port pin functions pin pin functions and selection methods d 0 / int 0 the pin function is switched as shown below by the pmrb pmrb0 bit. pmrb0 0 1 pin function d0 i/o pin int0 input pin d 1 / int 1 the pin function is switched as shown below by the pmrb pmrb1 bit. pmrb1 0 1 pin function d 1 i/o pin int 1 input pin d 2 /evnb the pin function is switched as shown below by the pmrb pmrb2 bit. pmrb2 0 1 pin function d 2 i/o pin evnb input pin d 3 /buzz the pin function is switched as shown below by the pmra pmra3 bit. pmra3 0 1 pin function d 3 i/o pin buzz output pin d 4 / stopc the pin function is switched as shown below by the pmrb pmrb3 bit. pmrb3 0 1 pin function d 4 i/o pin stopc input pin
276 11.3 r ports 11.3.1 overview the r port consists of the nine 4-bit i/o ports r0 to r6, r8, and r9, the 3-bit i/o port r7, and the 1-bit input port ra 1 . these ports are accessed in 4-bit units. r0 and r3 to r7 are standard voltage i/o ports. ra is a high voltage input port and r1, r2, r8 and r9 are high voltage i/o ports that can directly drive fluorescent display tubes. the individual r ports are accessed in 4-bit units with the lra and lrb output instructions to control the output levels (high or low) on each pin. output data is stored in the pdr built into each pin. similarly, the lar and lbr input instructions can be used to access the r ports in 4-bit units to read the input levels on the port pins. the ra 1 input-only port consists of a single bit. the values of bits 3, 2, and 0 are undefined when this port is accessed by the input instructions. dcr registers are used to control on/off states of the r0 and r3 to r7 output buffers. when the dcr bit corresponding to a pin in an r0 or r3 to r7 port is set to 1, the contents of the pdr corresponding to that pin is output from the pin. thus the output buffer on/off states can be controlled on an individual pin basis for the r port pins. the dcr registers are allocated in the ram address space. the r0 and r3 to r5 port pins have shared functions as built-in peripheral module pins. register settings are used to switch these functions. (see table 11-7.) figure 11-2 shows the r port pin structure.
277 r0 0 / sck (i/o or i/o) r0 1 /si (i/o or input) r0 2 /so (i/o or output) r0 3 /toc (i/o or output) r4 0 /an 4 (i/o or input) r4 1 /an 5 (i/o or input) r4 2 /an 6 (i/o or input) r4 3 /an 7 (i/o or input) r3 0 /an 0 (i/o or input) r3 1 /an 1 (i/o or input) r3 2 /an 2 (i/o or input) r3 3 /an 3 (i/o or input) r1 0 (i/o) r1 1 (i/o) r1 2 (i/o) r1 3 (i/o) r8 0 (i/o) r8 1 (i/o) r8 2 (i/o) r8 3 (i/o) r5 0 /an 8 (i/o or input) r5 1 /an 9 (i/o or input) r5 2 /an 10 (i/o or input) r5 3 /an 11 (i/o or input) r6 0 (i/o) r6 1 (i/o) r6 2 (i/o) r6 3 (i/o) ra 1 /v disp * (input/ ) r9 0 (i/o) r9 1 (i/o) r9 2 (i/o) r9 3 (i/o) r0 port r1 port r3 port r4 port r5 port r6 port r7 port r2 0 (i/o) r2 1 (i/o) r2 2 (i/o) r2 3 (i/o) r2 port r8 port r9 port ra port r7 0 (i/o) r7 1 (i/o) r7 2 (i/o) high voltage pins high voltage pins high voltage pins high voltage pins high voltage pin note: * in products with on-chip mask resistors, the use of this pin as the v disp pin (display power supply pin) can be selected as a mask option. high voltage pins for which a pull-down mos transistor is selected are pulled down to the v disp potential. figure 11-2 r port structure
278 11.3.2 register configuration and descriptions table 11-7 shows the configuration of the r port related registers, table 11-7 r port register configuration address register symbol r/w initial value port data registers standard voltage pins pdr w * 1 high voltage pins 0 $030 data control registers dcr0 w $0 $033 dcr3 w $0 $034 dcr4 w $0 $035 dcr5 w $0 $036 dcr6 w $0 $037 dcr7 w -000 $004 port mode register a pmra w $0 $005 serial mode register smr w $0 $019 a/d mode register 1 amr1 w $0 $01a a/d mode register 2 amr2 w -000 note: * the lra and lrb instructions are used to write to the pdr registers. (1) port data registers: all the i/o pins in ports r0 to r9 include a pdr that holds the output data. when an lra or an lrb instruction is executed for one of ports r0 to r9, the contents of the accumulator (a) or the b register (b) are transferred to the specified r port pdrs. when bits in dcr0 and dcr3 to dcr7 are set to 1, the output buffers for the corresponding pins in ports r0 and r3 to r7 will be turned on and the values in the pdrs will be output from those pins. the pdr registers for standard voltage pins are set to 1 on reset and in stop mode, and the pdrs for high voltage pins are cleared to 0.
279 (2) data control registers (dcr0, dcr3 to dcr7: $030, $033 to $037) dcr4: $034 dcr3: $033 bit initial value read/write 3 dcr43 0 w 0 dcr40 0 w 2 dcr42 0 w 1 dcr41 0 w bit initial value read/write 3 dcr33 0 w 0 dcr30 0 w 2 dcr32 0 w 1 dcr31 0 w dcr0: $030 bit initial value read/write 3 dcr03 0 w 0 dcr00 0 w 2 dcr02 0 w 1 dcr01 0 w dcr7: $037 dcr6: $036 bit initial value read/write 3 0 dcr70 0 w 2 dcr72 0 w 1 dcr71 0 w bit initial value read/write 3 dcr63 0 w 0 dcr60 0 w 2 dcr62 0 w 1 dcr61 0 w dcr5: $035 bit initial value read/write 3 dcr53 0 w 0 dcr50 0 w 2 dcr52 0 w 1 dcr51 0 w
280 bits in dcr0 and dcr3 to dcr7 description 0 the output buffer (cmos buffer) is turned off and the output goes to the high impedance state. (initial value) 1 the output buffer is turned on and the corresponding pdr value is output. the table below lists the correspondence between the bits in dcr0 and dcr3 to dcr7 and the port r0 and r3 to r7 pins. bit register bit 3 bit 2 bit 1 bit 0 dcr0 r0 3 r0 2 r0 1 r0 0 dcr3 r3 3 r3 2 r3 1 r3 0 dcr4 r4 3 r4 2 r4 1 r4 0 dcr5 r5 3 r5 2 r5 1 r5 0 dcr6 r6 3 r6 2 r6 1 r6 0 dcr7 r7 2 r7 1 r7 0
281 (3) port mode register a (pmra: $004): pmra is a 4-bit write-only register whose bits pmra2 to pmra0 switch the functions of the port r0 shared function pins. this section describes the bits pmra2 to pmra0. see section 11.2.2 (2), port mode register a (pmra) , for details on the pmra3 bit. bit initial value read/write 3 pmra3 0 w 0 pmra0 0 w 2 pmra2 0 w 1 pmra1 0 w 0 1 r0 3 /toc pin function switch 0 1 r0 1 /si pin function switch 0 1 r0 2 /so pin function switch 0 1 d 3 /buzz pin function switch r0 3 i/o pin toc output pin r0 1 i/o pin si input pin r0 2 i/o pin so output pin d 3 i/o pin buzz output pin bit 2?0 3 /toc pin function switch (pmra2): selects whether the r0 3 /toc pin functions as the r0 3 i/o pin or as the timer c output pin (toc). pmra2 description 0 the r0 3 /toc pin functions as the r0 3 i/o pin. (initial value) 1 the r0 3 /toc pin functions as the toc output pin.
282 bit 1?0 1 /si pin function switch (pmra1): selects whether the r0 1 /si pin functions as the r0 1 i/o pin or as the serial reception data input pin (si). pmra1 description 0 the r0 1 /si pin functions as the r0 1 i/o pin. (initial value) 1 the r0 1 /si pin functions as the si input pin. bit 0?0 2 /so pin function switch (pmra0): selects whether the r0 2 /so pin functions as the r0 2 i/o pin or as the serial transmission data output pin (so). pmra0 description 0 the r0 2 /so pin functions as the r0 2 i/o pin. (initial value) 1 the r0 2 /so pin functions as the so output pin.
283 (4) serial mode register (smr: $005): smr is a 4-bit write-only register whose smr3 bit switches the r0 0 / sck serial mode register (smr) for details on bits smr2 to smr0. bit initial value read/write 3 smr3 0 w 0 smr0 0 w 2 smr2 0 w 1 smr1 0 w 0 1 r0 0 / sck pin function switch r0 0 i/o pin sck i/o pin transfer clock selection bit 3?0 0 / sck pin function switch (smr3): selects whether the r0 0 / sck sck smr3 description 0 the r0 0 / sck pin functions as the r0 0 i/o pin. (initial value) 1 the r0 0 / sck pin functions as the sck i/o pin.
284 (5) a/d mode register 1 (amr1: $019): amr1 is a 4-bit write-only register that switches the functions of the r3 port shared function pins. bit initial value read/write 3 amr13 0 w 0 amr10 0 w 2 amr12 0 w 1 amr11 0 w 0 1 r3 2 /an 2 pin function switch 0 1 r3 1 /an 1 pin function switch 0 1 r3 0 /an 0 pin function switch 0 1 r3 3 /an 3 pin function switch r3 2 i/o pin an 2 input pin r3 1 i/o pin an 1 input pin r3 0 i/o pin an 0 input pin r3 3 i/o pin an 3 input pin bit 3?3 3 /an 3 pin function switch (amr13): selects whether the r3 3 /an 3 pin functions as the r3 3 i/o pin or as the a/d converter channel 3 input pin an 3 . amr13 description 0 the r3 3 /an 3 pin functions as the r3 3 i/o pin. (initial value) 1 the r3 3 /an 3 pin functions as the an 3 input pin. bit 2?3 2 /an 2 pin function switch (amr12): selects whether the r3 2 /an 2 pin functions as the r3 2 i/o pin or as the a/d converter channel 2 input pin an 2 . amr12 description 0 the r3 2 /an 2 pin functions as the r3 2 i/o pin. (initial value) 1 the r3 2 /an 2 pin functions as the an 2 input pin.
285 bit 1?3 1 /an 1 pin function switch (amr11): selects whether the r3 1 /an 1 pin functions as the r3 1 i/o pin or as the a/d converter channel 1 input pin an 1 . amr11 description 0 the r3 1 /an 1 pin functions as the r3 1 i/o pin. (initial value) 1 the r3 1 /an 1 pin functions as the an 1 input pin. bit 0?3 0 /an 0 pin function switch (amr10): selects whether the r3 0 /an 0 pin functions as the r3 0 i/o pin or as the a/d converter channel 0 input pin an 0 . amr10 description 0 the r3 0 /an 0 pin functions as the r3 0 i/o pin. (initial value) 1 the r3 0 /an 0 pin functions as the an 0 input pin.
286 (6) a/d mode register 2 (amr2: $01a): amr2 is a 3-bit write-only register whose amr21 bit switches the functions of all four bits of the r4 port (r4 0 to r4 3 ) to be a/d converter input channels (an 4 to an 7 ), and whose amr22 bit switches the r5 port to be the an 8 to an 11 input channels. this section describes the amr21 and amr22 bits. see section 15.2.2, a/d mode register 2 (amr2) , for details on the amr20 bit. bit initial value read/write 3 0 amr20 0 w 2 amr22 0 w 1 amr21 0 w 0 1 r5 0 /an 8 to r5 3 /an 11 pin function switch 0 1 r4 0 /an 4 to r4 3 /an 7 pin function switch 0 1 a/d conversion time r5 0 to r5 3 i/o pins an 8 to an 11 input pins r4 0 to r4 3 i/o pins an 4 to an 7 input pins 34 t cyc 67 t cyc unused bit 2?5 0 /an 8 to r5 3 /an 11 pin function switch (amr22): selects whether the r5 0 /an 8 to r5 3 /an 11 pins function as the r5 0 to r5 3 i/o pins or as the a/d converter channel 8 to 11 input pins (an 8 to an 11 ). amr22 description 0 the r5 0 /an 8 to r5 3 /an 11 pins function as the r5 0 to r5 3 i/o pins. (initial value) 1 the r5 0 /an 8 to r5 3 /an 11 pins function as the an 8 to an 11 input pins. bit 1?4 0 /an 4 to r4 3 /an 7 pin function switch (amr21): selects whether the r4 0 /an 4 to r4 3 /an 7 pins function as the r4 0 to r4 3 i/o pins or as the a/d converter channel 4 to 7 input pins (an 4 to an 7 ). amr21 description 0 the r4 0 /an 4 to r4 3 /an 7 pins function as the r4 0 to r4 3 i/o pins. (initial value) 1 the r4 0 /an 4 to r4 3 /an 7 pins function as the an 4 to an 7 input pins.
287 11.3.3 pin functions the pin functions of the r port pins are switched by register settings as shown in table 11-8. table 11-8 r port pin functions pin pin functions and selection methods r0 0 / sck the pin function is switched by the smr smr3 bit and the dcr0 dcr00 bit as shown below. smr3 0 1 dcr00 0 1 pin function r0 0 input pin r0 0 output pin sck i/o pin r0 1 /si the pin function is switched by the pmra pmra1 bit and the dcr0 dcr01 bit as shown below. pmra1 0 1 dcr01 0 1 pin function r0 1 input pin r0 1 output pin si input pin r0 2 /so the pin function is switched by the pmra pmra0 bit and the dcr0 dcr02 bit as shown below. pmra0 0 1 dcr02 0 1 pin function r0 2 input pin r0 2 output pin so output pin r0 3 /toc the pin function is switched by the pmra pmra2 bit and the dcr0 dcr03 bit as shown below. pmra2 0 1 dcr03 0 1 pin function r0 3 input pin r0 3 output pin toc output pin
288 table 11-8 r port pin functions (cont) pin pin functions and selection methods r3 0 /an 0 the pin function is switched by the amr1 amr10 bit and the dcr3 dcr30 bit as shown below. amr10 0 1 dcr30 0 1 pin function r3 0 input pin r3 0 output pin an 0 input pin r3 1 /an 1 the pin function is switched by the amr1 amr11 bit and the dcr3 dcr31 bit as shown below. amr11 0 1 dcr31 0 1 pin function r3 1 input pin r3 1 output pin an 1 input pin r3 2 /an 2 the pin function is switched by the amr1 amr12 bit and the dcr3 dcr32 bit as shown below. amr12 0 1 dcr32 0 1 pin function r3 2 input pin r3 2 output pin an 2 input pin r3 3 /an 3 the pin function is switched by the amr1 amr13 bit and the dcr3 dcr33 bit as shown below. amr13 0 1 dcr33 0 1 pin function r3 3 input pin r3 3 output pin an 3 input pin r4 0 /an 4 the pin function is switched by the amr2 amr21 bit and the dcr4 dcr40 bit as shown below. amr21 0 1 dcr40 0 1 pin function r4 0 input pin r4 0 output pin an 4 input pin
289 table 11-8 r port pin functions (cont) pin pin functions and selection methods r4 1 /an 5 the pin function is switched by the amr2 amr21 bit and the dcr4 dcr41 bit as shown below. amr21 0 1 dcr41 0 1 pin function r4 1 input pin r4 1 output pin an 5 input pin r4 2 /an 6 the pin function is switched by the amr2 amr21 bit and the dcr4 dcr42 bit as shown below. amr21 0 1 dcr42 0 1 pin function r4 2 input pin r4 2 output pin an 6 input pin r4 3 /an 7 the pin function is switched by the amr2 amr21 bit and the dcr4 dcr43 bit as shown below. amr21 0 1 dcr43 0 1 pin function r4 3 input pin r4 3 output pin an 7 input pin r5 0 /an 8 the pin function is switched by the amr2 amr22 bit and the dcr5 dcr50 bit as shown below. amr22 0 1 dcr50 0 1 pin function r5 0 input pin r5 0 output pin an 8 input pin r5 1 /an 9 the pin function is switched by the amr2 amr22 bit and the dcr5 dcr51 bit as shown below. amr22 0 1 dcr51 0 1 pin function r5 1 input pin r5 1 output pin an 9 input pin
290 table 11-8 r port pin functions (cont) pin pin functions and selection methods r5 2 /an 10 the pin function is switched by the amr2 amr22 bit and the dcr5 dcr52 bit as shown below. amr22 0 1 dcr52 0 1 pin function r5 2 input pin r5 2 output pin an 10 input pin r5 3 /an 11 the pin function is switched by the amr2 amr22 bit and the dcr5 dcr53 bit as shown below. amr22 0 1 dcr53 0 1 pin function r5 3 input pin r5 3 output pin an 11 input pin
291 11.4 usage notes keep the following points in mind when using the i/o ports. ? ? no pull-down mos transistor (pmos open drain) as the mask option and connect the pin to v cc on the user system printed circuit board. standard voltage pin: either use the built-in pull-up mos transistor to pull the pin up to v cc , or pull up the pin to v cc externally with a pull-up resistor of about 100 k ? ?
292 v cc v cc hlt mis3 dcr pdr amr (a/d mode register setting value) acr (a/d channel register setting value) input control signal input data a/d input figure 11-3 r port/analog input shared function pin circuit structure
293 table 11-9 program control of the r port/analog input shared function pins corresponding bit in amr1 or amr2 0 (r port selected) mis3 bit 0 1 dcr 0101 pdr 01010101 cmos buffer pmos on on nmos on on pull-up mos transistor on on note: : off corresponding bit in amr1 or amr2 1 (analog input selected) mis3 bit 0 1 dcr 0101 pdr 01010101 cmos buffer pmos nmos pull-up mos transistor on on note: : off
294
295 section 12 i/o ports (hd404369 series) 12.1 overview 12.1.1 features the hd404369 series i/o ports have the following features. ? the eight pins r1 0 to r1 3 and r2 0 to r2 3 are medium voltage nmos open drain i/o pins. ra 1 is an input-only pin. the d, r0, r1, and r3 to r9 port pins are standard voltage i/o pins that, in output mode, are cmos three state outputs. ? certain i/o pins (d 0 to d 4 , and the pins in the r0 and r3 to r5 ports) are shared with the built- in peripheral modules, such as timers and the serial interface. setting these pins for use with the built-in peripheral modules takes priority over their setting for use as d or r port pins. ? register settings are used to select input or output for i/o pins and to select the i/o port or peripheral module usage for shared function pins. ? all peripheral module output pins are cmos outputs. however, the r0 2 /so pin can be selected to be an nmos open drain output by setting a register. ? since the system is reset in stop mode, the built-in peripheral module selections are cleared and the i/o pins go to the high impedance state. ? the cmos output pins have built-in programmable pull-up mos transistors. the on/off state of these transistors can be controlled by register settings on an individual basis. note that the pull-up mos transistor on/off settings are independent of the pin settings for use as built-in peripheral module pins. table 12-1 provides an overview of the hd404369 series port functions.
296 table 12-1 port functions port overview pin shared function function switching register d 0 to d 13 d 0 / int 0 external interrupt input 0 pmrb d 1 / int 1 external interrupt input 1 d 2 /evnb timer b event input d 3 /buzz alarm output pmra d 4 / stopc stop mode clear pmrb d 5 to d 13 r0 r0 0 / sck transfer clock i/o smr r0 1 /si serial reception data input pmra r0 2 /so serial transmission data output r0 3 /toc timer c output r3 r3 0 /an 0 analog input channel 0 amr1 r3 1 /an 1 analog input channel 1 r3 2 /an 2 analog input channel 2 r3 3 /an 3 analog input channel 3 r4 r4 0 /an 4 analog input channel 4 amr2 r4 1 /an 5 analog input channel 5 r4 2 /an 6 analog input channel 6 r4 3 /an 7 analog input channel 7 r5 r5 0 /an 8 analog input channel 8 amr2 r5 1 /an 9 analog input channel 9 r5 2 /an 10 analog input channel 10 r5 3 /an 11 analog input channel 11 r6 to r9 r6 0 to r6 3 r7 0 to r7 2 r8 0 to r8 3 r9 0 to r9 3 ? standard voltage i/o port ? accessed in bit units ? accessed with the sed, sedd, red, redd, td, and tdd instructions. ? programmable pull-up mos transistors ? standard voltage i/o port ? accessed in 4-bit units. ? accessed with the lar, lbr, lra, and lrb instructions. ? programmable pull-up mos transistors
297 table 12-1 port functions (cont) port overview pin shared function function switching register r1, r2 ? medium voltage nmos open drain i/o port ? accessed in 4-bit units. ? accessed with the lar, lbr, lra, and lrb instructions. r1 0 to r1 3 r2 0 to r2 3 ra ? standard voltage input port (1 bit) ? accessed with the lar and lbr instructions. ra 1
298 12.1.2 i/o control r1 and r2 are medium voltage nmos open drain i/o ports and the d, r0, and r3 to r9 ports are standard voltage i/o ports. the different port types have different circuit structures as follows. (1) medium voltage nmos open drain i/o pin circuit: r1 and r2 are medium voltage nmos open drain i/o ports and i/o through these ports is controlled by the port data registers (pdr) and the data control registers (dcr). when the dcr bit corresponding to a given pin is 1, that pin functions as an output pin and when the value in the pdr is 0, the pin? nmos transistor turns on and the pin outputs a low level voltage. when the value in the pdr is 1 the pin goes to the high impedance state. when a given dcr bit is 0, the corresponding pin functions as an input pin. (2) standard voltage cmos three state i/o pin circuit: the pins in the d, r0, and r3 to r9 ports are standard voltage cmos three state i/o ports. i/o through these ports is controlled by the pdrs and the data control registers (dcd or dcr). when the dcd or dcr bit corresponding to a given pin is 1, that pin functions as an output pin and outputs the value in the pdr. when a given dcd or dcr bit is 0, the corresponding pin functions as an input pin. (3) pull-up mos control: each i/o pin in the d, r0 and r3 to r9 ports has a built-in programmable pull-up mos transistor. when the miscellaneous register (mis) mis3 bit is set to 1 the pull-up mos transistor for pins for which the corresponding pdr is set to 1 will be turned on. thus the on/off state of each pin can be controlled independently by the pdrs. note that the pull- up mos transistor on/off settings are independent of the pin settings for use as built-in peripheral module pins. table 12-2 shows how register settings control the port i/o pins. table 12-2 register settings for i/o pin control mis3 0 1 dcd, dcr 0101 pdr 01010101 cmos buffer pmos on on nmos on on pull-up mos transistor on on notes: 1. ? off 2. the pdr registers are not allocated addresses in ram. the pdr registers are accessed by special-purpose i/o instructions.
299 (4) miscellaneous register (mis: $00c): mis is a 4-bit write-only register that controls the on/off states of the d, r0, and r3 to r9 port pin pull-up mos transistors and the on/off state of the r0 2 /so pin output buffer pmos transistor. mis is initialized to $0 on reset and in stop mode. this section describes the mis2 and mis3 bits. refer to section 6.2.1, ?iscellaneous register (mis)? for details on the mis0 and mis1 bits. bit initial value read/write 3 mis3 0 w 0 mis0 0 w 2 mis2 0 w 1 mis1 0 w 0 1 r0 2 /so pin output buffer control 0 1 pull-up mos transistor control pmos transistor active (cmos output) pmos transistor off (nmos open drain output) all pull-up mos transistors off pull-up mos transistors active interrupt frame period and oscillator stabilization time settings bit 3?ull-up mos transistor control (mis3): controls the on/off states of the pull-up mos transistors built into the i/o port pins. mis3 description 0 all pull-up mos transistors will be turned off. (initial value) 1 pull-up mos transistors for which the corresponding pdr bit is 1 will be turned on. bit 2?0 2 /so pin output buffer control (mis2): controls the on/off state of the r0 2 /so pin output buffer pmos transistor. mis2 description 0 the r0 2 /so pin output will be a cmos output. (initial value) 1 the r0 2 /so pin output will be an nmos open drain output.
300 12.1.3 i/o pin circuit structures table 12-3 shows the port and peripheral module pin circuits. notes: 1. since the system is reset in stop mode, the built-in peripheral module selections are cleared. since the internal hlt signal goes to the low (active) level, the i/o pins go to the high impedance state. also, all the pull-up mos transistors are turned off. 2. in all low power modes other than stop mode, the internal hlt signal goes to the high level. table 12-3 input and output pin circuits class circuit applicable pins standard voltage pins i/o pins v cc v cc hlt mis3 dcd, dcr pdr pull-up control signal buffer control signal output data input control signal input data d 0 to d 13 , r0 0 , r0 1 , r0 3 , r3 0 to r3 3 , r4 0 to r4 3 , r5 0 to r5 3 , r6 0 to r6 3 , r7 0 to r7 2 , r8 0 to r8 3 , r9 0 to r9 3 v cc v cc hlt mis3 dcr pdr mis2 pull-up control signa buffer control signal output data input control signal input data r0 2
301 table 12-3 input and output pin circuits (cont) class circuit applicable pins standard voltage pins input pins input control signal input data ra 1 medium voltage pins i/o pins pdr dcr hlt input data output data input control signal r1 0 to r1 3 , r2 0 to r2 3
302 table 12-3 input and output pin circuits (cont) class circuit applicable pins standard voltage pins standard peripheral module pins i/o pins v cc v cc hlt mis3 sck sck pull-up control signal output data input data sck output pins v cc v cc hlt mis3 so mis2 pull-up control signal pmos control signal output data so v cc v cc hlt mis3 toc, buzz pull-up control signal output data toc, buzz
303 table 12-3 input and output pin circuits (cont) class circuit applicable pins standard voltage pins built-in peripheral module pins input pins si, int 0 , int 1 , evnb, stopc v cc hlt mis3 pdr input data si, int 0 , int 1 , evnb, stopc v cc hlt mis3 pdr a/d input input control an 0 to an 11
304 12.1.4 port states in low power modes the d 0 to d 4 pins and the r0 and r3 to r5 port pins have shared functions as input or output pins for built-in peripheral modules. since the cpu stops in standby and watch mode, the pins selected as output ports maintain their immediately prior output values. also, pins selected for use by built- in peripheral modules that operate in standby or watch mode continue to operate. (output pins used by modules that stop in standby or watch mode maintain their immediately prior output values.) see section 6, ?ow power modes? for details on which built-in peripheral modules can operate in each mode. table 12-4 lists the port states in the low power modes. table 12-4 port states in low power modes low power mode port states standby mode, watch mode pins maintain their values immediately prior to entering standby mode. stop mode built-in peripheral function selections are cleared, and the port and peripheral function i/o pins go to the high impedance state. 12.1.5 handling unused pins i/o pins that are unused in user systems must be tied to a fixed potential, since floating i/o pins can cause noise that can interfere with lsi operation. the built-in pull-up mos transistors can be used to pull up unused pins to v cc . alternatively, unused pins can be pulled up to v cc with external resistors of about 100 k ? . application programs should maintain the pdr and dcr contents for unused pins at their reset state values. also note that unused pins must not be selected for use as peripheral function i/o pins.
305 12.2 d port 12.2.1 overview the d port is a 14-pin i/o port (d 0 to d 13 ) that can be accessed in 1-bit units. the output levels on the pins d 0 to d 13 can be set to low or high by accessing the port in one-bit units with the sed, sedd, red, and redd output instructions. the output data is stored in the pdr for each pin. the level on each of the pins d 0 to d 13 can be tested in one-bit units with the td and tdd input instructions. the dcd registers are used to turn the d port output buffers on or off. when the dcd bit corresponding to a given pin is 1, the data in the corresponding pdr will be output from that pin. the on/off states of the output buffers can be controlled individually for each d port pin. the dcd registers are allocated in the ram address space. the pins d 0 to d 4 have shared functions as built-in peripheral module pins. pmrb is used to switch these functions. figure 12-1 shows the structure of the d port. d 0 /int 0 (i/o or input) d 1 /int 1 (i/o or input) d 2 /evnb (i/o or input) d 3 /buzz (i/o or output) d 4 / stopc (i/o or input) d 5 (i/o) d 6 (i/o) d 7 (i/o) d 8 (i/o) d 9 (i/o) d 10 (i/o) d 11 (i/o) d 12 (i/o) d 13 (i/o) d port figure 12-1 d port structure
306 12.2.2 register configuration and descriptions table 12-5 shows the configuration of the d port registers. table 12-5 d port register configuration address register symbol r/w initial value port data registers pdr w * 1 $02c data control registers dcd0 w $0 $02d dcd1 w $0 $02e dcd2 w $0 $02f dcd3 w --00 $024 port mode register b pmrb w $0 note: * the sed, sedd, red, and redd instructions can be used to write to the pdrs. (1) port data registers (pdr): each of the i/o pins d 0 to d 13 includes a built-in pdr. when a sed or sedd instruction is executed for one of the pins d 0 to d 13 the corresponding pdr is set to 1, and when a red or redd instruction is executed, the corresponding pdr is cleared to 0. when bits in dcd0 to dcd3 are set to 1, the output buffers for the corresponding pins will be turned on and the values in the pdrs will be output from those pins. the pdrs are cleared to 1 on reset and in stop mode.
307 (2) data control registers (dcd0 to dcd3: $02c, $02d, $02e, $02f) dcd2: $02e dcd1: $02d bit initial value read/write 3 dcd23 0 w 0 dcd20 0 w 2 dcd22 0 w 1 dcd21 0 w bit initial value read/write 3 dcd13 0 w 0 dcd10 0 w 2 dcd12 0 w 1 dcd11 0 w dcd0: $02c bit initial value read/write 3 dcd03 0 w 0 dcd00 0 w 2 dcd02 0 w 1 dcd01 0 w dcd3: $02f bit initial value read/write 3 0 dcd30 0 w 2 1 dcd31 0 w bits in dcd0 to dcd3 description 0 the output buffer (cmos buffer) is turned off and the output goes to the high impedance state. (initial value) 1 the output buffer is turned on and the corresponding pdr value is output. the table below lists the correspondence between the bits in dcd0 to dcd2 and the d port pins. bit register bit 3 bit 2 bit 1 bit 0 dcd0 d 3 d 2 d 1 d 0 dcd1 d 7 d 6 d 5 d 4 dcd2 d 11 d 10 d 9 d 8 dcd3 d 13 d 12
308 (3) port mode register a (pmra: $004): pmra is a 4-bit write-only register whose pmra3 bit switches the function of the d 3 /buzz pin. this section describes the function of the pmra3 bit. see section 12.3.2 (3), ?ort mode register a (pmra)? for details on the pmra2 to pmra0 bits. bit initial value read/write 3 pmra3 0 w 0 pmra0 0 w 2 pmra2 0 w 1 pmra1 0 w 0 1 r0 3 /toc pin function switch 0 1 r0 1 /si pin function switch 0 1 r0 2 /so pin function switch 0 1 d 3 /buzz pin function switch r0 3 i/o pin toc output pin r0 1 i/o pin si input pin r0 2 i/o pin so output pin d 3 i/o pin buzz output pin bit 3? 3 /buzz pin function switch (pmra3): selects whether the d 3 /buzz pin functions as the d 3 i/o pin or as the alarm output pin (buzz). pmra3 description 0d 3 /buzz pin functions as the d 3 i/o pin. (initial value) 1d 3 /buzz pin functions as the buzz output pin.
309 (4) port mode register b (pmrb: $024): pmrb is a 4-bit write-only register that switches the d port i/o pin shared functions. bit initial value read/write 3 pmrb3 0 w 0 pmrb0 0 w 2 pmrb2 0 w 1 pmrb1 0 w 0 1 d 2 /evnb pin function switch 0 1 d 1 /int 1 pin function switch 0 1 d 0 /int 0 pin function switch 0 1 d 4 / stopc pin function switch d 2 i/o pin evnb input pin d 1 i/o pin int 1 input pin d 0 i/o pin int 0 input pin d 4 i/o pin stopc input pin bit 3? 4 / stopc pin function switch (pmrb3): selects whether the d 4 / stopc pin is used as the d 4 i/o pin or as the stop mode clear pin ( stopc ). pmrb3 description 0 the d 4 / stopc pin functions as the d 4 i/o pin. (initial value) 1 the d 4 / stopc pin functions as the stopc input pin. bit 2? 2 /evnb pin function switch (pmrb2): selects whether the d 2 /evnb pin is used as the d 2 i/o pin or as the timer b event count input pin (evnb). pmrb2 description 0 the d 2 /evnb pin functions as the d 2 i/o pin. (initial value) 1 the d 2 /evnb pin functions as the evnb input pin.
310 bit 1? 1 / int 1 pin function switch (pmrb1): selects whether the d 1 / int 1 pin is used as the d 1 i/o pin or as the external interrupt 1 input pin ( int 1 ). pmrb1 description 0 the d 1 / int 1 pin functions as the d 1 i/o pin. (initial value) 1 the d1/ int 1 pin functions as the int 1 input pin. bit 0? 0 / int 0 pin function switch (pmrb0): selects whether the d 0 / int 0 pin is used as the d 0 i/o pin or as the external interrupt 0 input pin ( int 0 ). pmrb0 description 0 the d 0 / int 0 pin functions as the d 0 i/o pin. (initial value) 1 the d 0 / int 0 pin functions as the int 0 input pin.
311 12.2.3 pin functions the functions of the pins d 0 to d 13 are switched by register settings as shown in table 12-6. table 12-6 d 0 to d 13 port pin functions pin pin functions and selection methods d 0 / int 0 the pin function is switched as shown below by the pmrb pmrb0 bit and the dcd0 dcd00 bit. pmrb 0 1 dcd00 0 1 pin function d 0 input pin d 0 output pin int 0 input pin d 1 / int 1 the pin function is switched as shown below by the pmrb pmrb1 bit and the dcd0 dcd01 bit. pmrb1 0 1 dcd01 0 1 pin function d 1 input pin d 1 output pin int 1 input pin d 2 /evnb the pin function is switched as shown below by the pmrb pmrb2 bit and the dcd0 dcd02 bit. pmrb2 0 1 dcd02 0 1 pin function d 2 input pin d 2 output pin evnb input pin d 3 /buzz the pin function is switched as shown below by the pmra pmra3 bit and the dcd0 dcd03 bit. pmra3 0 1 dcd03 0 1 pin function d 3 input pin d 3 output pin buzz output pin d 4 / stopc the pin function is switched as shown below by the pmrb pmrb3 bit and the dcd1 dcd10 bit. pmrb3 0 1 dcd10 0 1 pin function d 4 input pin d 4 output pin stopc input pin
312 table 12-6 d 0 to d 13 port pin functions (cont) pin pin functions and selection methods d 5 the pin function is switched as shown below by the dcd1 dcd11 bit. dcd11 0 1 pin function d 5 input pin d 5 output pin d 6 the pin function is switched as shown below by the dcd1 dcd12 bit. dcd12 0 1 pin function d 6 input pin d 6 output pin d 7 the pin function is switched as shown below by the dcd1 dcd13 bit. dcd13 0 1 pin function d 7 input pin d 7 output pin d 8 the pin function is switched as shown below by the dcd2 dcd20 bit. dcd20 0 1 pin function d 8 input pin d 8 output pin d 9 the pin function is switched as shown below by the dcd2 dcd21 bit. dcd21 0 1 pin function d 9 input pin d 9 output pin d 10 the pin function is switched as shown below by the dcd2 dcd22 bit. dcd22 0 1 pin function d 10 input pin d 10 output pin d 11 the pin function is switched as shown below by the dcd2 dcd23 bit. dcd23 0 1 pin function d 11 input pin d 11 output pin d 12 the pin function is switched as shown below by the dcd3 dcd30 bit. dcd30 0 1 pin function d 12 input pin d 12 output pin
313 table 12-6 d 0 to d 13 port pin functions (cont) pin pin functions and selection methods d 13 the pin function is switched as shown below by the dcd3 dcd31 bit. dcd31 0 1 pin function d 13 input pin d 13 output pin 12.3 r ports 12.3.1 overview the r port consists of the nine 4-bit i/o ports r0 to r6, r8, and r9, the 3-bit i/o port r7, and the 1-bit input port ra 1 . r0 and r3 to r9 are standard voltage cmos three state i/o ports and r1 and r2 are medium voltage nmos open drain i/o ports. the individual ports r0 to r9 are accessed in 4-bit units with the lra and lrb output instructions to control the output levels (high or low) on each pin. output data is stored in the pdr built into each pin. similarly, the lar and lbr input instructions can be used to access the r ports in 4-bit units to read the input levels on the port pins. the ra 1 input-only port consists of a single bit. the values of bits 3, 2, and 0 are undefined when this port is accessed by the input instructions. dcr registers are used to control on/off states of the r port output buffers. when the dcr bit corresponding to a pin in an r port is set to 1, the contents of the pdr corresponding to that pin is output from the pin. thus the output buffer on/off states can be controlled on an individual pin basis for the r port pins. the dcr registers are allocated in the ram address space. the r0 and r3 to r5 port pins have shared functions as built-in peripheral module pins. register settings are used to switch these functions. (see table 12-7.) figure 12-2 shows the r port pin structure.
314 r0 0 / sck (i/o or i/o) r0 1 /si (i/o or input) r0 2 /so (i/o or output) r0 3 /toc (i/o or output) r4 0 /an 4 (i/o or input) r4 1 /an 5 (i/o or input) r4 2 /an 6 (i/o or input) r4 3 /an 7 (i/o or input) r2 0 (i/o) r2 1 (i/o) r2 2 (i/o) r2 3 (i/o) r1 0 (i/o) r1 1 (i/o) r1 2 (i/o) r1 3 (i/o) r5 0 /an 8 (i/o or input) r5 1 /an 9 (i/o or input) r5 2 /an 10 (i/o or input) r5 3 /an 11 (i/o or input) r6 0 (i/o) r6 1 (i/o) r6 2 (i/o) r6 3 (i/o) r8 0 (i/o) r8 1 (i/o) r8 2 (i/o) r8 3 (i/o) r9 0 (i/o) r9 1 (i/o) r9 2 (i/o) r9 3 (i/o) r0 port r1 port r2 port r4 port r6 port r8 port ra port r3 0 /an 0 (i/o or input) r3 1 /an 1 (i/o or input) r3 2 /an 2 (i/o or input) r3 3 /an 3 (i/o or input) r3 port r5 port r7 port r9 port ra 1 (input) medium voltage pins r7 0 (i/o) r7 1 (i/o) r7 2 (i/o) medium voltage pins figure 12-2 r port structure
315 12.3.2 register configuration and descriptions table 12-7 shows the configuration of the r port related registers. table 12-7 r port register configuration address register symbol r/w initial value port data registers pdr w * 1 $030 data control registers dcr0 w $0 $031 dcr1 w $0 $032 dcr2 w $0 $033 dcr3 w $0 $034 dcr4 w $0 $035 dcr5 w $0 $036 dcr6 w $0 $037 dcr7 w -000 $038 dcr8 w $0 $039 dcr9 w $0 $004 port mode register a pmra w $0 $005 serial mode register smr w $0 $019 a/d mode register 1 amr1 w $0 $01a a/d mode register 2 amr2 w -000 note: * the lra and lrb instructions are used to write to the pdr registers. (1) port data registers (pdr): all the i/o pins in ports r0 to r9 include a pdr that holds the output data. when an lra or an lrb instruction is executed for one of ports r0 to r9, the contents of the accumulator (a) or the b register (b) are transferred to the specified r port pdrs. when bits in dcr0 to dcr9 are set to 1, the output buffers for the corresponding pins in ports r0 to r9 will be turned on and the values in the pdrs will be output from those pins. the pdr registers are set to 1 on reset and in stop mode.
316 (2) data control registers (dcr0 to dcr9: $030 to $039) dcr2: $032 dcr1: $031 bit initial value read/write 3 dcr23 0 w 0 dcr20 0 w 2 dcr22 0 w 1 dcr21 0 w bit initial value read/write 3 dcr13 0 w 0 dcr10 0 w 2 dcr12 0 w 1 dcr11 0 w dcr0: $030 bit initial value read/write 3 dcr03 0 w 0 dcr00 0 w 2 dcr02 0 w 1 dcr01 0 w dcr5: $035 dcr4: $034 bit initial value read/write 3 dcr53 0 w 0 dcr50 0 w 2 dcr52 0 w 1 dcr51 0 w bit initial value read/write 3 dcr43 0 w 0 dcr40 0 w 2 dcr42 0 w 1 dcr41 0 w dcr3: $033 bit initial value read/write 3 dcr33 0 w 0 dcr30 0 w 2 dcr32 0 w 1 dcr31 0 w dcr6: $036 bit initial value read/write 3 dcr63 0 w 0 dcr60 0 w 2 dcr62 0 w 1 dcr61 0 w
317 dcr9: $039 dcr8: $038 bit initial value read/write 3 dcr93 0 w 0 dcr90 0 w 2 dcr92 0 w 1 dcr91 0 w bit initial value read/write 3 dcr83 0 w 0 dcr80 0 w 2 dcr82 0 w 1 dcr81 0 w dcr7: $037 bit initial value read/write 3 0 w 0 dcr70 0 w 2 dcr72 0 w 1 dcr71 0 w bits in dcr0 to dcr9 description 0 the output buffer (cmos buffer) is turned off and the output goes to the high impedance state. (initial value) 1 ? the cmos three state output buffer is turned on and the corresponding pdr value is output. ? for medium voltage nmos open drain pins (r1 and r2), when the pdr is 0 a low level is output. when the pdr is 1, the pin goes to the high impedance state. the table below lists the correspondence between the bits in dcr0 to dcr9 and the port r0 to r9 pins. bit register bit 3 bit 2 bit 1 bit 0 dcr0 r0 3 r0 2 r0 1 r0 0 dcr1 r1 3 r1 2 r1 1 r1 0 dcr2 r2 3 r2 2 r2 1 r2 0 dcr3 r3 3 r3 2 r3 1 r3 0 dcr4 r4 3 r4 2 r4 1 r4 0 dcr5 r5 3 r5 2 r5 1 r5 0 dcr6 r6 3 r6 2 r6 1 r6 0 dcr7 r7 2 r7 1 r7 0 dcr8 r8 3 r8 2 r8 1 r8 0 dcr9 r9 3 r9 2 r9 1 r9 0
318 (3) port mode register a (pmra: $004): pmra is a 4-bit write-only register whose bits pmra2 to pmra0 switch the functions of the port r0 shared function pins. this section describes the bits pmra2 to pmra0. see section 12.2.2 (3), port mode register a (pmra) , for details on the pmra3 bit. bit initial value read/write 3 pmra3 0 w 0 pmra0 0 w 2 pmra2 0 w 1 pmra1 0 w 0 1 r0 3 /toc pin function switch 0 1 r0 1 /si pin function switch 0 1 r0 2 /so pin function switch 0 1 d 3 /buzz pin function switch r0 3 i/o pin toc output pin r0 1 i/o pin si input pin r0 2 i/o pin so output pin d 3 i/o pin buzz output pin bit 2?0 3 /toc pin function switch (pmra2): selects whether the r0 3 /toc pin functions as the r0 3 i/o pin or as the timer c output pin (toc). pmra2 description 0 the r0 3 /toc pin functions as the r0 3 i/o pin. (initial value) 1 the r0 3 /toc pin functions as the toc output pin.
319 bit 1?0 1 /si pin function switch (pmra1): selects whether the r0 1 /si pin functions as the r0 1 i/o pin or as the serial reception data input pin (si). pmra1 description 0 the r0 1 /si pin functions as the r0 1 i/o pin. (initial value) 1 the r0 1 /si pin functions as the si input pin. bit 0?0 2 /so pin function switch (pmra0): selects whether the r0 2 /so pin functions as the r0 2 i/o pin or as the serial transmission data output pin (so). pmra0 description 0 the r0 2 /so pin functions as the r0 2 i/o pin. (initial value) 1 the r0 2 /so pin functions as the so output pin. (4) serial mode register (smr: $005): smr is a 4-bit write-only register whose smr3 bit switches the r0 0 / sck serial mode register (smr) for details on bits smr2 to smr0. bit initial value read/write 3 smr3 0 w 0 smr0 0 w 2 smr2 0 w 1 smr1 0 w 0 1 r0 0 / sck pin function switch r0 0 i/o pin sck i/o pin transfer clock selection bit 3?0 0 / sck pin function switch (smr3): selects whether the r0 0 / sck sck smr3 description 0 the r0 0 / sck pin functions as the r0 0 i/o pin. (initial value) 1 the r0 0 / sck pin functions as the sck i/o pin.
320 (5) a/d mode register 1 (amr1: $019): amr1 is a 4-bit write-only register that switches the functions of the r3 port shared function pins. bit initial value read/write 3 amr13 0 w 0 amr10 0 w 2 amr12 0 w 1 amr11 0 w 0 1 r3 2 /an 2 pin function switch 0 1 r3 1 /an 1 pin function switch 0 1 r3 0 /an 0 pin function switch 0 1 r3 3 /an 3 pin function switch r3 2 i/o pin an 2 input pin r3 1 i/o pin an 1 input pin r3 0 i/o pin an 0 input pin r3 3 i/o pin an 3 input pin bit 3?3 3 /an 3 pin function switch (amr13): selects whether the r3 3 /an 3 pin functions as the r3 3 i/o pin or as the a/d converter channel 3 input pin an 3 . amr13 description 0 the r3 3 /an 3 pin functions as the r3 3 i/o pin. (initial value) 1 the r3 3 /an 3 pin functions as the an 3 input pin. bit 2?3 2 /an 2 pin function switch (amr12): selects whether the r3 2 /an 2 pin functions as the r3 2 i/o pin or as the a/d converter channel 2 input pin an 2 . amr12 description 0 the r3 2 /an 2 pin functions as the r3 2 i/o pin. (initial value) 1 the r3 2 /an 2 pin functions as the an 2 input pin.
321 bit 1?3 1 /an 1 pin function switch (amr11): selects whether the r3 1 /an 1 pin functions as the r3 1 i/o pin or as the a/d converter channel 1 input pin an 1 . amr11 description 0 the r3 1 /an 1 pin functions as the r3 1 i/o pin. (initial value) 1 the r3 1 /an 1 pin functions as the an 1 input pin. bit 0?3 0 /an 0 pin function switch (amr10): selects whether the r3 0 /an 0 pin functions as the r3 0 i/o pin or as the a/d converter channel 0 input pin an 0 . amr10 description 0 the r3 0 /an 0 pin functions as the r3 0 i/o pin. (initial value) 1 the r3 0 /an 0 pin functions as the an 0 input pin.
322 (6) a/d mode register 2 (amr2: $01a): amr2 is a 3-bit write-only register whose amr21 bit switches the functions of all four bits of the r4 port to be a/d converter input channels (an 4 to an 7 ), and whose amr22 bit switches the functions of all four bits of the r5 port to be a/d converter input channels (an 8 to an 11 ). this section describes the amr22 and amr21 bits. see section 15.2.2, a/d mode register 2 (amr2) , for details on the amr20 bit. bit initial value read/write 3 0 amr20 0 w 2 amr22 0 w 1 amr21 0 w 0 1 r5 0 /an 8 to r5 3 /an 11 pin function switch 0 1 r4 0 /an 4 to r4 3 /an 7 pin function switch 0 1 a/d conversion time r5 0 to r5 3 i/o pins an 8 to an 11 input pins r4 0 to r4 3 i/o pins an 4 to an 7 input pins 34 t cyc 67 t cyc unused bit 2?5 0 /an 8 to r5 3 /an 11 pin function switch (amr22): selects whether the r5 0 /an 8 to r5 3 /an 11 pins function as the r5 0 to r5 3 i/o pins or as the a/d converter channel 8 to 11 input pins (an 8 to an 11 ). amr22 description 0 the r5 0 /an 8 to r5 3 /an 11 pins function as the r5 0 to r5 3 i/o pins. (initial value) 1 the r5 0 /an 8 to r5 3 /an 11 pins function as the an 8 to an 11 input pins. bit 1?4 0 /an 4 to r4 3 /an 7 pin function switch (amr21): selects whether the r4 0 /an 4 to r4 3 /an 7 pins function as the r4 0 to r4 3 i/o pins or as the a/d converter channel 4 to 7 input pins (an 4 to an 7 ). amr21 description 0 the r4 0 /an 4 to r4 3 /an 7 pins function as the r4 0 to r4 3 i/o pins. (initial value) 1 the r4 0 /an 4 to r4 3 /an 7 pins function as the an 4 to an 7 input pins.
323 12.3.3 pin functions the pin functions of the r port pins are switched by register settings as shown in table 12-8. table 12-8 r port pin functions pin pin functions and selection methods r0 0 / sck the pin function is switched by the smr smr3 bit and the dcr0 dcr00 bit as shown below. smr3 0 1 dcr00 0 1 pin function r0 0 input pin r0 0 output pin sck i/o pin r0 1 /si the pin function is switched by the pmra pmra1 bit and the dcr0 dcr01 bit as shown below. pmra1 0 1 dcr01 0 1 pin function r01 input pin r01 output pin si input pin r0 2 /so the pin function is switched by the pmra pmra0 bit and the dcr0 dcr02 bit as shown below. pmra0 0 1 dcr02 0 1 pin function r0 2 input pin r0 2 output pin so output pin r0 3 /toc the pin function is switched by the pmra pmra2 bit and the dcr0 dcr03 bit as shown below. pmra2 0 1 dcr03 0 1 pin function r0 3 input pin r0 3 output pin toc output pin
324 table 12-8 r port pin functions (cont) pin pin functions and selection methods r1 0 the pin function is switched by the dcr1 dcr10 bit as shown below. dcr10 0 1 pin function r1 0 input pin r1 0 output pin * r1 1 the pin function is switched by the dcr1 dcr11 bit as shown below. dcr11 0 1 pin function r1 1 input pin r1 1 output pin * r1 2 the pin function is switched by the dcr1 dcr12 bit as shown below. dcr12 0 1 pin function r1 2 input pin r1 2 output pin * r1 3 the pin function is switched by the dcr1 dcr13 bit as shown below. dcr13 0 1 pin function r1 3 input pin r1 3 output pin * r2 0 the pin function is switched by the dcr2 dcr20 bit as shown below. dcr20 0 1 pin function r2 0 input pin r2 0 output pin * r2 1 the pin function is switched by the dcr2 dcr21 bit as shown below. dcr21 0 1 pin function r2 1 input pin r2 1 output pin * r2 2 the pin function is switched by the dcr2 dcr22 bit as shown below. dcr22 0 1 pin function r2 2 input pin r2 2 output pin * note: * r1 0 to r1 3 and r2 0 to r2 3 are medium voltage nmos open drain i/o pins. these pins go to the high impedance state when their pdr is set to 1.
325 table 12-8 r port pin functions (cont) pin pin functions and selection methods r2 3 the pin function is switched by the dcr2 dcr23 bit as shown below. dcr23 0 1 pin function r2 3 input pin r2 3 output pin * r3 0 /an 0 the pin function is switched by the amr1 amr10 bit and the dcr3 dcr30 bit as shown below. amr10 0 1 dcr30 0 1 pin function r3 0 input pin r3 0 output pin an 0 input pin r3 1 /an 1 the pin function is switched by the amr1 amr11 bit and the dcr3 dcr31 bit as shown below. amr11 0 1 dcr31 0 1 pin function r3 1 input pin r3 1 output pin an 1 input pin r3 2 /an 2 the pin function is switched by the amr1 amr12 bit and the dcr3 dcr32 bit as shown below. amr12 0 1 dcr32 0 1 pin function r3 2 input pin r3 2 output pin an 2 input pin r3 3 /an 3 the pin function is switched by the amr1 amr13 bit and the dcr3 dcr33 bit as shown below. amr13 0 1 dcr33 0 1 pin function r3 3 input pin r3 3 output pin an 3 input pin note: * r1 0 to r1 3 and r2 0 to r2 3 are medium voltage nmos open drain i/o pins. these pins go to the high impedance state when their pdr is set to 1.
326 table 12-8 r port pin functions (cont) pin pin functions and selection methods r4 0 /an 4 the pin function is switched by the amr2 amr21 bit and the dcr4 dcr40 bit as shown below. amr21 0 1 dcr40 0 1 pin function r4 0 input pin r4 0 output pin an 4 input pin r4 1 /an 5 the pin function is switched by the amr2 amr21 bit and the dcr4 dcr41 bit as shown below. amr21 0 1 dcr41 0 1 pin function r4 1 input pin r4 1 output pin an 5 input pin r4 2 /an 6 the pin function is switched by the amr2 amr21 bit and the dcr4 dcr42 bit as shown below. amr21 0 1 dcr42 0 1 pin function r4 2 input pin r4 2 output pin an 6 input pin r4 3 /an 7 the pin function is switched by the amr2 amr21 bit and the dcr4 dcr43 bit as shown below. amr21 0 1 dcr43 0 1 pin function r4 3 input pin r4 3 output pin an 7 input pin
327 table 12-8 r port pin functions (cont) pin pin functions and selection methods r5 0 /an 8 the pin function is switched by the amr2 amr22 bit and the dcr5 dcr50 bit as shown below. amr22 0 1 dcr50 0 1 pin function r5 0 input pin r5 0 output pin an 8 input pin r5 1 /an 9 the pin function is switched by the amr2 amr22 bit and the dcr5 dcr51 bit as shown below. amr22 0 1 dcr51 0 1 pin function r5 1 input pin r5 1 output pin an 9 input pin r5 2 /an 0 the pin function is switched by the amr2 amr22 bit and the dcr5 dcr52 bit as shown below. amr22 0 1 dcr52 0 1 pin function r5 2 input pin r5 2 output pin an 10 input pin r5 3 /an 11 the pin function is switched by the amr2 amr22 bit and the dcr5 dcr53 bit as shown below. amr22 0 1 dcr53 0 1 pin function r5 3 input pin r5 3 output pin an 11 input pin
328 table 12-8 r port pin functions (cont) pin pin functions and selection methods r6 0 the pin function is switched by the dcr6 dcr60 bit as shown below. dcr60 0 1 pin function r6 0 input pin r6 0 output pin r6 1 the pin function is switched by the dcr6 dcr61 bit as shown below. dcr61 0 1 pin function r6 1 input pin r6 1 output pin r6 2 the pin function is switched by the dcr6 dcr62 bit as shown below. dcr62 0 1 pin function r6 2 input pin r6 2 output pin r6 3 the pin function is switched by the dcr6 dcr63 bit as shown below. dcr63 0 1 pin function r6 3 input pin r6 3 output pin r7 0 the pin function is switched by the dcr7 dcr70 bit as shown below. dcr70 0 1 pin function r7 0 input pin r7 0 output pin r7 1 the pin function is switched by the dcr7 dcr71 bit as shown below. dcr71 0 1 pin function r7 1 input pin r7 1 output pin r7 2 the pin function is switched by the dcr7 dcr72 bit as shown below. dcr72 0 1 pin function r7 2 input pin r7 2 output pin
329 table 12-8 r port pin functions (cont) pin pin functions and selection methods r8 0 the pin function is switched by the dcr8 dcr80 bit as shown below. dcr80 0 1 pin function r8 0 input pin r8 0 output pin r8 1 the pin function is switched by the dcr8 dcr81 bit as shown below. dcr81 0 1 pin function r8 1 input pin r8 1 output pin r8 2 the pin function is switched by the dcr8 dcr82 bit as shown below. dcr82 0 1 pin function r8 2 input pin r8 2 output pin r8 3 the pin function is switched by the dcr8 dcr83 bit as shown below. dcr83 0 1 pin function r8 3 input pin r8 3 output pin r9 0 the pin function is switched by the dcr9 dcr90 bit as shown below. dcr90 0 1 pin function r9 0 input pin r9 0 output pin r9 1 the pin function is switched by the dcr9 dcr91 bit as shown below. dcr91 0 1 pin function r9 1 input pin r9 1 output pin r9 2 the pin function is switched by the dcr9 dcr92 bit as shown below. dcr92 0 1 pin function r9 2 input pin r9 2 output pin r9 3 the pin function is switched by the dcr9 dcr93 bit as shown below. dcr93 0 1 pin function r9 3 input pin r9 3 output pin
330 12.4 usage notes keep the following points in mind when using the i/o ports. ? ? ? ?
331 v cc v cc hlt mis3 dcr pdr amr (a/d mode register setting value) acr (a/d channel register setting value) input control signal input data a/d input figure 12-3 r port/analog input shared function pin circuit
332 table 12-9 program control of the r port/analog input shared function pins corresponding bit in amr1 or amr2 0 (r port selected) mis3 bit 0 1 dcr 0101 pdr 01010101 cmos buffer pmos on on nmos on on pull-up mos transistor on on note: : off corresponding bit in amr1 or amr2 1 (analog input selected) mis3 bit 0 1 dcr 0101 pdr 01010101 cmos buffer pmos nmos pull-up mos transistor on on note: : off ? and the mask rom microcomputer versions as shown in figure 12-4. although the outputs in both the ztat and mask rom versions can be set to high impedance by the combinations listed in table 12- 10, these outputs cannot be set to high impedance in the evaluation chip set. please keep this in mind when using the evaluation chip set. figure 12-4 shows the circuit for the medium voltage nmos open drain pins.
333 pdr dcr hlt v cc v cc hlt mis3 dcr pdr input data input control signal input data input control signal (a) evaluation chip pin circuit structure (b) ztat and mask rom pin circuit structure figure 12-4 medium voltage nmos open drain pin circuits table 12-10 ztat and mask rom microcomputer nmos open drain pin high impedance control dcr pdr description 0 * high impedance output (initial value) 1 0 nmos buffer on. low level output 1 high impedance output note: * don t care
334
335 section 13 oscillator circuits (hd404344r/hd404394/hd404318/hd404358/ hd404358r series) 13.1 overview 13.1.1 features the hd404344r, hd404394, hd404318, hd404358, and hd404358r series microcomputers include a system clock oscillator circuit with the following features. ? the system clock oscillator circuit supports the use of a ceramic oscillator, a crystal oscillator, a resistor, or an external clock input. the system clock is generated by dividing the oscillator frequency by four internally (i.e., f cyc = f osc /4). note that cpu = per = f cyc . the following oscillator elements and external clock frequencies can be used. hd404344r series use an oscillator or an external clock with a frequency in the range 0.4 to 5.4 mhz* 1 . alternately, for cr oscillation* 2 connect a resistor. hd404394 and hd404318 series use an oscillator or an external clock with a frequency in the range 0.4 to 4.5 mhz. hd404358 series use an oscillator or an external clock with a frequency in either the range 0.4 to 5.0 mhz* 3 , or the range 0.4 to 8.5 mhz* 4 . hd404358r series use an oscillator or an external clock with a frequency in the range 0.4 to 5.0 mhz* 5 or 0.4 to 8.5 mhz* 6 . alternately, for cr oscillation* 7 connect a resistor. notes: 1. hd404341r, hd404342r, hd404344r, hd4074344 2. hd40c4341r, hd40c4342r, hd40c4344r 3. hd404354, hd404356, hd404358 4. hd40a4354, hd40a4356, hd40a4358, hd407a4359 5. hd404354r, hd404356r, hd404358r 6. hd40a4354r, hd40a4356r, hd40a4358r, hd407a4359r 7. hd40c4354r, hd40c4356r, hd40c4358r, hd407c4359r
336 ? the built-in peripheral module operating clock ( per ) is input to an 11-bit prescaler (pss) and divided to generate the clocks that are used as the counter operating clocks for the built-in peripheral modules. the divisors can be set individually using the mode registers for each built-in peripheral module. 13.1.2 block diagram figure 13-1 shows the block diagram of the oscillator circuit used in the hd404344r, hd404394, hd404318, hd404358, and hd404358r series microcomputers. osc 1 osc 2 f cyc t cyc cpu per f osc system clock oscillator divider circuit 1/4 timing generator cpu ? rom ? ram ? registers, flags ? i/o built-in peripheral modules symbol f osc description the frequency of the ceramic or crystal oscillator or cr oscillator connected between the osc 1 and osc 2 oscillator pins f cyc f osc /4 t cyc the clock period for the f cyc frequency (this period is equal to one instruction cycle in active mode and also to one count period of prescaler s (pss).) cpu the system clock (the operating clock in active mode) per the system clock (the built-in peripheral module and interrupt clock) figure 13-1 oscillator circuit block diagram (hd404344r/hd404394/hd404318/hd404358/hd404358r series)
337 13.1.3 oscillator circuit pins table 13-1 lists the pins used by the oscillator circuit. table 13-1 oscillator circuit pins pin symbol i/o function system clock oscillator pin 1 osc 1 input connections for the system clock oscillator element * (an external clock can be input to osc 1 .) system clock oscillator pin 2 osc 2 output note: * hd404344r series connect a ceramic oscillator with a frequency in the range 0.4 to 4.5 mhz or a resistor. hd404394 and hd404318 series use a ceramic or crystal oscillator element with a frequency in the range 0.4 to 4.5 mhz. hd404358 series use a ceramic or crystal oscillator element with a frequency in either the range 0.4 to 5.0 mhz, or the range 0.4 to 8.5 mhz. hd404358r series connect a ceramic or crystal oscillator with a frequency in the range 0.4 to 5.0 mhz or 0.4 to 8.5 mhz, or a resistor.
338 13.2 oscillator connection and external clock input the system clock oscillator circuit supports the use of a ceramic oscillator, a crystal oscillator, a resistor, or an external clock input. table 13-2 shows sample oscillator circuits. table 13-2 oscillator circuit examples circuit circuit constants external clock osc 1 osc 2 external oscillator left open ceramic oscillator (osc 1 , osc 2 ) osc 1 osc 2 c 1 c 2 r f gnd ceramic oscillator ceramic oscillator: csa 4.00mg (murata manufacturing) r f = 1 m ? 20% c 1 = c 2 = 30 pf 20%
339 table 13-2 oscillator circuit examples (cont) circuit circuit constants crystal oscillator * 1 (osc 1 , osc 2 ) osc 1 osc 2 osc 1 osc 2 c 1 c 2 r f lc s r s c 0 gnd cut parallel resonator type crystal oscillator crystal oscillator r f = 1 m ? 20% c 1 = c 2 = 10 to 22 pf 20% crystal oscillator: equivalent circuit shown at left c 0 = 7 pf max r s = 100 ? max f = 1.0 to 4.5 mhz cr oscillator * 2 (osc 1 , osc 2 ) osc 1 osc 2 r f r f = 20 k ? 1% notes: 1. applies to the hd404318, hd404358, and hd404358r series. 2. applies to the hd404344r and hd404358r series.
340 13.3 usage notes keep the following points in mind when designing and implementing the oscillator circuit. ? when using a crystal or ceramic oscillator the circuit constants will differ depending on the device actually used, the stray capacitances in the mounted circuit and other factors. therefore, these circuit parameters should be determined in consultation with the manufacturer of the crystal or ceramic oscillator element used. ? the distance between the osc 1 and osc 2 pins and the devices connected to those pins should be kept as short as possible. do not allow any other lines to cross those lines. (see figure 13-2.) correct oscillation may become impossible due to induced signals if any lines cross. ? in like manner, the distance between the osc 1 and osc 2 terminals, on the one hand, and the oscillator resistor, on the other, should be as short as possible. do not allow any other lines to cross them.
341 osc 1 r2 3 osc 2 gnd osc 1 reset osc 2 gnd test av ss gnd hd404344r/hd404394 series hd404318/hd404358/hd404358r series figure 13-2 wiring examples for crystal and ceramic oscillators
342
343 section 14 oscillator circuits (hd404339 and hd404369 series) 14.1 overview 14.1.1 features the microcomputers in the hd404339 and hd404369 series include a system clock oscillator circuit and a subsystem clock oscillator circuit with the following features. ? the system clock oscillator circuit supports the use of a ceramic or crystal oscillator or an external clock input. the system clock is generated by dividing the oscillator frequency by either 4, 8, 16, or 32 internally (i.e., f cyc = f osc /4, f osc /8, f osc /16, or f osc /32: the divisor is software selectable). note that cpu = per = f cyc . the following oscillator elements and external clock frequencies can be used. hd404339 series use an oscillator element or an external clock with a frequency in the range 0.4 to 4.5 mhz. hd404369 series use an oscillator element or an external clock with a frequency in either the range 0.4 to 5.0 mhz* 1 , or the range 0.4 to 8.5 mhz* 2 . notes: 1. hd404364, hd404368, hd4043612, hd404369 2. hd40a4364, hd40a4368, hd40a43612, hd40a4369, hd407a4369 ? the built-in peripheral module operating clock ( per ) is input to an 11-bit prescaler (pss) and divided to generate the clocks that are used as the counter operating clocks for the built-in peripheral modules. the divisors can be set individually using the mode registers for each built-in peripheral module. ? a 32.768 khz crystal oscillator is used as the subsystem clock oscillator. a clock generated by dividing this frequency by four or eight (f sub = f x /4 or f x /8) with an internal divider circuit is used as the system clock in subactive mode. the divisor can be selected by setting a register. ? in all operating modes, a clock generated by dividing the subsystem clock frequency by eight is input to prescaler w (psw). a clock generated by psw division is used in timer a clock time base operation.
344 14.1.2 block diagram figure 14-1 shows the block diagram of the oscillator circuits used in the hd404339 and hd404369 series microcomputers. osc 1 osc 2 x1 x2 cpu ? rom ? ram ? registers, flags ? i/o f osc f cyc f sub t cyc cpu f x t subcyc f w t wcyc per clk lson tma3 * 1 * 2 system clock oscillator subsystem clock oscillator divider circuit: 1/4, 1/8, 1/16, 1/32 divider circuit: 1/4 or 1/8 divider circuit: 1/8 timing generator timing generator timing generator system clock selection circuit clock time base clock selection circuit built-in peripheral module interrupts (except timer a) timer a interrupt notes: symbols are described on the following page. 1. 2. the divisor is selected by the system clock selection register 2 (ssr2: $028) ssr21 and ssr20 bits. the divisor is selected by the system clock selection register 1 (ssr1: $027) ssr12 bit. figure 14-1 oscillator circuit block diagram (hd404339/hd404369 series)
345 symbol description f osc the frequency of the ceramic or crystal oscillator connected between the osc 1 and osc 2 oscillator pins f x the frequency of the crystal oscillator connected between the x1 and x2 oscillator pins (32.768 khz) f cyc f osc /4, f osc /8, f osc /16, or f osc /32 t cyc the clock period for the f cyc frequency (this period is equal to one instruction cycle in active mode and also to one count period for prescaler s (pss).) f w f x /8 t wcyc the clock period for the f w frequency (one count period for prescaler w (psw)) f sub f x /4 or f x /8 t subcyc the clock period for the f w frequency (one instruction cycle in subactive mode) cpu the system clock (the cpu operating clock) clk the clock used for timer a and interrupt frame generation (supplied from pss when the tma3 bit is 0, and from psw when the tma3 bit is 1.) per the system clock (the built-in peripheral module and interrupt clock)
346 14.1.3 oscillator circuit pins table 14-1 lists the pins used by the oscillator circuit. table 14-1 oscillator circuit pins pin symbol i/o function system clock oscillator pin 1 osc 1 input connections for the system clock oscillator element * (an external clock can be input to osc 1 .) system clock oscillator pin 2 osc 2 output subsystem clock oscillator pin 1 x1 input connections for the 32.768 khz crystal oscillator. subsystem clock oscillator pin 2 x2 output note: * hd404339 series use a ceramic or crystal oscillator element with a frequency in the range 0.4 to 4.5 mhz. hd404369 series use a ceramic or crystal oscillator element with a frequency in either the range 0.4 to 5.0 mhz, or the range 0.4 to 8.5 mhz. 14.1.4 register and flag configuration table 14-2 lists the registers and flag used in oscillator circuit control. table 14-2 register and flag configuration address item symbol r/w initial value $027 system clock selection register 1 ssr1 w $0 $028 system clock selection register 2 ssr2 w $0 $020, 0 low speed on flag lson r/w 0 note: * lson is a control bit allocated in the register flag area. it can only be manipulated by the ram bit manipulation instructions.
347 14.2 register and flag descriptions 14.2.1 system clock selection register 1 (ssr1: $027) ssr1 is a 4-bit write-only register that is used to specify the system clock oscillator frequency (f osc ) actually used, to select the subsystem clock frequency (f sub ) divisor, and to set the subsystem clock oscillator operating state in stop mode. the ssr1 ssr12 and ssr11 bits are initialized to zero on reset and in stop mode. bit initial value read/write 3 ssr13 0 w 0 2 ssr12 0 w 1 ssr11 0 w 0 1 subsystem clock divisor switch 0 1 system clock selection unused 0 1 subsystem clock stop setting f sub = f x /8 f sub = f x /4 0.4 to 1.0 mhz 1.6 to 4.5 mhz (hd404339 series) 1.6 to 5.0 mhz (hd404369 series) * 1 1.6 to 8.5 mhz (hd404369 series) * 2 the subsystem clock operates in stop mode the subsystem clock stops in stop mode notes: 1. 2. hd404364, hd404368, hd4043612, hd404369 hd40a4364, hd40a4368, hd40a43612, hd40a4369, hd407a4369
348 bit 3?ubsystem clock stop setting (ssr13): selects whether the subsystem clock (32.768 khz) operates or stops in stop mode. this bit is initialized to 0 only on reset. ssr13 description 0 the subsystem clock operates in stop mode (initial value) 1 the subsystem clock stops in stop mode bit 2?ubsystem clock divisor switch (ssr12): specifies the divisor for the subsystem clock that is supplied to the cpu and the built-in peripheral modules in subactive mode. however, note that the divisor for the subsystem clock supplied to psw is fixed at eight, i.e., f w = f x /8. thus the clock used for timer a in clock time base mode is not affected by the setting of this bit. this bit must be set in active mode. the microcomputer may operate incorrectly if this bit is changed in subactive mode. also, note that this bit is initialized to 0 on reset and in stop mode. ssr12 description 0f sub will be 1/8 of the subsystem clock oscillator frequency f x (f sub = f x /8) and the cpu single instruction cycle time will be 244.14 s (when f x = 32.768 khz). (initial value) 1f sub will be 1/4 of the subsystem clock oscillator frequency f x (f sub = f x /4) and the cpu single instruction cycle time will be 122.07 s (when f x = 32.768 khz). bit 1?ystem clock selection (ssr11): the ssr11 bit must be set to match the frequency of the system clock. this bit is initialized to 0 on reset and in stop mode. ssr11 description 0 the system clock frequency is between 0.4 and 1.0 mhz (initial value) 1 the system clock frequency is between 1.6 and 4.5 mhz (hd404339 series) the system clock frequency is between 1.6 and 5.0 mhz (hd404369 series) * 1 the system clock frequency is between 1.6 and 8.5 mhz (hd404369 series) * 2 notes: if these register settings do not match the frequency of the system oscillator, the subsystem using the 32 khz oscillator will not operate correctly. if the subsystem clock is used, then the system clock frequency must either be between 0.4 and 1.0 mhz or between 1.6 and 4.5 mhz (or 1.6 and 5.0 mhz, or 1.6 and 8.5 mhz). 1. hd404364, hd404368, hd4043612, hd404369 2. hd40a4364, hd40a4368, hd40a43612, hd40a4369, hd407a4369
349 14.2.2 system clock selection register 2 (ssr2: $028) ssr2 is a 2-bit write-only register that selects the system clock divisor. ssr2 is initialized to $0 on reset and in stop mode. bit initial value read/write 3 0 ssr20 0 w 2 1 ssr21 0 w 0 1 system clock divisor selection 0 1 0 1 unused division by 4 (f cyc = f osc /4) division by 8 (f cyc = f osc /8) division by 16 (f cyc = f osc /16) division by 32 (f cyc = f osc /32) bits 1 and 0?ystem clock selection (ssr21, ssr20): these bits set the system clock divisor to be 4, 8, 16, or 32, i.e., the system oscillator frequency is divided by 4, 8, 16, or 32. (f cyc = f osc /4, f osc /8, f osc /16, or f osc /32) this setting only takes effect when watch mode is entered. that is, the system clock must be stopped to change the divisor. ssr21 ssr20 description 0 0 the system clock divisor is 4 (f cyc = f osc /4) (initial value) 1 the system clock divisor is 8 (f cyc = f osc /8) 1 0 the system clock divisor is 16 (f cyc = f osc /16) 1 the system clock divisor is 32 (f cyc = f osc /32) there are two methods for changing the system clock divisor as follows. 1. in active mode, set the divisor by writing the ssr21 and ssr20 bits. at this point the immediately prior divisor setting remains in effect. now, switch to watch mode and then return to active mode. when the system returns to active mode the new clock divisor will be in effect. 2. in subactive mode, set the divisor by writing the ssr21 and ssr20 bits. then, return to active mode by passing through watch mode. when the system returns to active mode the new clock divisor will be in effect. (the change will also take effect for direct transition to active mode.)
350 14.2.3 low speed on flag (lson: $020, 0) lson selects whether the system operating clock is taken from the system clock or from the subsystem clock when switching modes between active mode, watch mode, and subactive mode. see section 6.2.5, low speed on flag (lson) , for details.
351 14.3 oscillator connection and external clock input the system clock oscillator circuit supports the use of a ceramic or crystal oscillator with a frequency between 0.4 and 4.5 mhz (or between 0.4 and 8.5 mhz) or an external clock input. a 32.768 mhz crystal oscillator must be used as the subsystem clock oscillator. table 14-3 shows sample oscillator circuits. table 14-3 oscillator circuit examples circuit circuit constants external clock osc 1 osc 2 external oscillator left open ceramic oscillator (osc 1 , osc 2 ) osc 1 osc 2 c 1 c 2 r f gnd ceramic oscillator ceramic oscillator: csa 4.00mg (murata manufacturing) r f = 1 m ? 20% c 1 = c 2 = 30 pf 20% crystal oscillator (osc 1 , osc 2 ) osc 1 osc 2 osc 1 osc 2 c 1 c 2 r f lc s r s c 0 gnd cut parallel resonator type crystal oscillator crystal oscillator r f = 1 m ? 20% c 1 = c 2 = 10 to 22 pf 20% crystal oscillator: equivalent circuit shown at left c 0 = 7 pf max r s = 100 ? max f = 1.0 to 4.5 mhz
352 table 14-3 oscillator circuit examples (cont) circuit circuit constants crystal oscillator (x1, x2) x1 x2 x1 x2 c 1 c 2 lc s r s c 0 gnd crystal oscillator cut parallel resonator type crystal oscillator crystal oscillator: 32.768 khz; mx38t (nippon denpa kogyo, ltd.) c1 = c2 = 20 pf 20% rs = 14 k ? c0 = 1.5 pf
353 14.4 usage notes keep the following points in mind when designing and implementing clock oscillator circuits. ? when using a crystal or ceramic oscillator the circuit constants will differ depending on the device actually used, the stray capacitances in the mounted circuit and other factors. therefore, these circuit parameters should be determined in consultation with the manufacturer of the crystal or ceramic oscillator element used. ? the distance between the osc 1 and osc 2 pins (and x1 and x2 pins) and the devices connected to those pins should be kept as short as possible. do not allow any other lines to cross those lines. (see figure 14-2.) correct oscillation may become impossible due to induced signals if any lines cross. ? if the subsystem clock (the 32.768 khz oscillator) is not used, connect the x1 pin to ground and leave the x2 pin open. reset osc 1 osc 2 gnd x1 x2 av ss gnd figure 14-2 wiring example for crystal and ceramic oscillators
354
355 section 15 a/d converter 15.1 overview the hmcs43xx family microcomputers include a built-in resistor ladder successive approximations a/d converter. 15.1.1 features the a/d converter has the following features. ? eight bit resolution (1/256 of the reference voltage) ? input channels series number of channels hd404344r 4 hd404394 3 hd404318 8 hd404358 hd404358r hd404339 12 hd404369 ? analog power supply series analog reference power supply hd404344r v cc (internal connection) hd404394 v ref hd404318 av cc hd404358 hd404358r hd404339 hd404369 ? conversion time: 34t cyc or 67t cyc (t cyc : system clock period) ? an interrupt is generated at the completion of an a/d conversion.
356 15.1.2 block diagram figures 15-1 (a), (b), and (c) show the block diagrams of the a/d converter circuits used in the hd404344r/hd404394 series, hd404318/hd404358/hd404358r series, and hd404339/hd404369 series microcomputers, respectively. 4 2 (an 0 ) an 1 an 2 an 3 v cc (v ref ) gnd comp * 1 * 2 + selector encoder a/d interrupt request flag (ifad) a/d control register a/d start flag (adsf) a/d mode register 1 (amr1) a/d mode register 2 (amr2) a/d data register (adr) conversion time control a/d channel register (acr) internal data bus off in stop mode or when iaof is set to 1. resistor ladder i ad off flag (iaof) notes: 1. 2. applies to the hd404344r series. unused in the hd404394 series. connected to v cc in the hd404344r series, v ref in the hd404394 series. figure 15-1 (a) a/d converter block diagram (hd404344r/hd404394 series)
357 4 3 an 0 an 1 an 2 an 3 an 4 an 5 an 6 an 7 av cc av ss comp + selector a/d interrupt request flag (ifad) encoder a/d control register a/d start flag (adsf) off in stop mode or when iaof is set to 1. resistor ladder conversion time control a/d mode register 2 (amr2) a/d mode register 1 (amr1) a/d data register (adr) a/d channel register (acr) i ad off flag (iaof) internal data bus figure 15-1 (b) a/d converter block diagram (hd404318/hd404358/hd404358r series)
358 4 2 4 an 0 an 1 an 2 an 3 an 4 an 5 an 6 an 7 an 8 an 9 an 10 an 11 av cc av ss comp + selector off in stop mode, watch mode, subactive mode, or when iaof is set to 1. resistor ladder encoder a/d control register a/d start flag (adsf) i ad off flag (iaof) a/d interrupt request flag (ifad) a/d mode register 1 (amr1) a/d mode register 2 (amr2) a/d data register (adr) conversion time control a/d channel register (acr) internal data bus figure 15-1 (c) a/d converter block diagram (hd404339/hd404369 series)
359 15.1.3 pin configuration table 15-1 shows the configuration of the a/d converter pins. table 15-1 pin configuration hd404344r series pin symbol i/o function analog input channel 0 r3 0 /an 0 i/o or input shared function: analog input channel 0 or r3 0 analog input channel 1 r3 1 /an 1 i/o or input shared function: analog input channel 1 or r3 1 analog input channel 2 r3 2 /an 2 i/o or input shared function: analog input channel 2 or r3 2 analog input channel 3 r3 3 /an 3 i/o or input shared function: analog input channel 3 or r3 3 hd404394 series pin symbol i/o function analog reference power supply v ref analog reference power supply analog input channel 1 r3 1 /an 1 i/o or input shared function: analog input channel 1 or r3 1 analog input channel 2 r3 2 /an 2 i/o or input shared function: analog input channel 2 or r3 2 analog input channel 3 r3 3 /an 3 i/o or input shared function: analog input channel 3 or r3 3
360 table 15-1 pin configuration (cont) hd404318/hd404358/hd404358r series pin symbol i/o function analog power supply av cc power supply for the analog block analog ground av ss ground for the analog block analog input channel 0 r3 0 /an 0 i/o or input shared function: analog input channel 0 or r3 0 analog input channel 1 r3 1 /an 1 i/o or input shared function: analog input channel 1 or r3 1 analog input channel 2 r3 2 /an 2 i/o or input shared function: analog input channel 2 or r3 2 analog input channel 3 r3 3 /an 3 i/o or input shared function: analog input channel 3 or r3 3 analog input channel 4 r4 0 /an 4 i/o or input shared function: analog input channel 4 or r4 0 analog input channel 5 r4 1 /an 5 i/o or input shared function: analog input channel 5 or r4 1 analog input channel 6 r4 2 /an 6 i/o or input shared function: analog input channel 6 or r4 2 analog input channel 7 r4 3 /an 7 i/o or input shared function: analog input channel 7 or r4 3
361 table 15-1 pin configuration (cont) hd404339/hd404369 series pin symbol i/o function analog power supply av cc power supply for the analog block analog ground av ss ground for the analog block analog input channel 0 r3 0 /an 0 i/o or input shared function: analog input channel 0 or r3 0 analog input channel 1 r3 1 /an 1 i/o or input shared function: analog input channel 1 or r3 1 analog input channel 2 r3 2 /an 2 i/o or input shared function: analog input channel 2 or r3 2 analog input channel 3 r3 3 /an 3 i/o or input shared function: analog input channel 3 or r3 3 analog input channel 4 r4 0 /an 4 i/o or input shared function: analog input channel 4 or r4 0 analog input channel 5 r4 1 /an 5 i/o or input shared function: analog input channel 5 or r4 1 analog input channel 6 r4 2 /an 6 i/o or input shared function: analog input channel 6 or r4 2 analog input channel 7 r4 3 /an 7 i/o or input shared function: analog input channel 7 or r4 3 analog input channel 8 r5 0 /an 8 i/o or input shared function: analog input channel 8 or r5 0 analog input channel 9 r5 1 /an 9 i/o or input shared function: analog input channel 9 or r5 1 analog input channel 10 r5 2 /an 10 i/o or input shared function: analog input channel 10 or r5 2 analog input channel 11 r5 3 /an 11 i/o or input shared function: analog input channel 11 or r5 3
362 15.1.4 register and flag configuration table 15-2 shows the configuration of the registers and flags used by the a/d converter. table 15-2 register and flag configuration address item symbol r/w initial value $019 a/d mode register 1 amr1 w $0 $01a a/d mode register 2 amr2 w $0 $017 a/d data register l adrl r $0 $018 a/d data register u adru r $8 $016 a/d channel register acr w $0 $020, 2 a/d start flag adsf r/w * 0 $021, 2 iad off flag iaof r/w * 0 note: * adsf and iaof are allocated in the register flag area and can only be manipulated with the ram bit manipulation instructions. only a 1 can be written to the adsf flag, i.e., it can only be set to 1, it cannot be cleared to 0.
363 15.2 register and flag descriptions 15.2.1 a/d mode register 1 (amr1: $019) amr1 is a 4-bit write-only register that switches the functions of the r3 port shared function pins. bit initial value read/write 3 amr13 0 w 0 amr10 * 0 w 2 amr12 0 w 1 amr11 0 w 0 1 r3 2 /an 2 pin function switch 0 1 r3 1 /an 1 pin function switch 0 1 r3 0 /an 0 pin function switch * 0 1 r3 3 /an 3 pin function switch r3 2 i/o pin an 2 input pin r3 1 i/o pin an 1 input pin r3 0 i/o pin an 0 input pin r3 3 i/o pin an 3 input pin note: * applies to the hd404344r, hd404318, hd404358, hd404358r, hd404339, and hd404369 series. the amr10 bit is unused in the hd404394 series. bit 3?3 3 /an 3 pin function switch (amr13): selects whether the r3 3 /an 3 pin functions as the r3 3 i/o pin or as the a/d converter channel 3 input pin an 3 . amr13 description 0 the r3 3 /an 3 pin functions as the r3 3 i/o pin. (initial value) 1 the r3 3 /an 3 pin functions as the an 3 input pin.
364 bit 2?3 2 /an 2 pin function switch (amr12): selects whether the r3 2 /an 2 pin functions as the r3 2 i/o pin or as the a/d converter channel 2 input pin an 2 . amr12 description 0 the r3 2 /an 2 pin functions as the r3 2 i/o pin. (initial value) 1 the r3 2 /an 2 pin functions as the an 2 input pin. bit 1?3 1 /an 1 pin function switch (amr11): selects whether the r3 1 /an 1 pin functions as the r3 1 i/o pin or as the a/d converter channel 1 input pin an 1 . amr11 description 0 the r3 1 /an 1 pin functions as the r3 1 i/o pin. (initial value) 1 the r3 1 /an 1 pin functions as the an 1 input pin. hd404344r/hd404318/hd404358/hd404358r/hd404339/hd404369 series bit 0?3 0 /an 0 pin function switch (amr10): selects whether the r3 0 /an 0 pin functions as the r3 0 i/o pin or as the a/d converter channel 0 input pin an 0 . amr10 description 0 the r3 0 /an 0 pin functions as the r3 0 i/o pin. (initial value) 1 the r3 0 /an 0 pin functions as the an 0 input pin. hd404394 series bit 0?eserved bit: this bit is unused.
365 15.2.2 a/d mode register 2 (amr2: $01a) amr2 is a 4-bit write-only register that sets the a/d conversion time and switches the functions of certain r port shared function pins. bit initial value read/write 3 0 amr20 0 w 2 amr22 * 2 0 w 1 amr21 * 1 0 w 0 1 r5 0 /an 8 to r5 3 /an 11 pin function switch * 2 0 1 r4 0 /an 4 to r4 3 /an 7 pin function switch * 1 0 1 a/d conversion time r5 0 to r5 3 i/o pins an 8 to an 11 input pins r4 0 to r4 3 i/o pins an 4 to an 7 input pins 34 t cyc 67 t cyc unused notes: 1. 2. applies to the hd404318, hd404358, hd404358r, hd404339, and hd404369 series. the amr21 bit is unused in the hd404344r and hd404394 series. applies to the hd404339 and hd404369 series. the amr22 bit is unused in the hd404344r, hd404394, hd404318, hd404358, and hd404358r series. hd404339/hd404369 series bit 2?5 0 /an 8 to r5 3 /an 11 pin function switch (amr22): selects whether the r5 0 /an 8 to r5 3 /an 11 pins function as the r5 0 to r5 3 i/o pins or as the a/d converter channel 8 to 11 input pins (an 8 to an 11 ). amr22 description 0 the r5 0 /an 8 to r5 3 /an 11 pins function as the r5 0 to r5 3 i/o pins. (initial value) 1 the r5 0 /an 8 to r5 3 /an 11 pins function as the an 8 to an 11 input pins. hd404344r/hd404394/hd404318/hd404358/hd404358r series bit 2?eserved bit: this bit is unused.
366 hd404318/hd404358/hd404358r/hd404339/hd404369 series bit 1?4 0 /an 4 to r4 3 /an 7 pin function switch (amr21): selects whether the r4 0 /an 4 to r4 3 /an 7 pins function as the r4 0 to r4 3 i/o pins or as the a/d converter channel 4 to 7 input pins (an 4 to an 7 ). amr21 description 0 the r4 0 /an 4 to r4 3 /an 7 pins function as the r4 0 to r4 3 i/o pins. (initial value) 1 the r4 0 /an 4 to r4 3 /an 7 pins function as the an 4 to an 7 input pins. hd404344r/hd404394 series bit 1?eserved bit: this bit is unused. bit 0?/d conversion time selection (amr20): selects the a/d conversion time. amr20 description 0 conversion time = 34t cyc (initial value) 1 conversion time = 67t cyc note: t cyc is the system clock period.
367 15.2.3 a/d data register l, u (adrl: $017, adru: $018) the adrl/u pair (adrl and adru) forms an 8-bit read-only register in which adrl is the lower digit and adru is the upper digit. the 8-bit a/d converted data is transferred to the adrl/u pair and held until the start of the next conversion. the contents of this register is not guaranteed during a/d converter operation. the adrl/u pair is not cleared on reset. bit initial value read/write adrl 0 adrl0 0 r 2 adrl2 0 r 1 adrl1 0 r 3 adrl3 0 r a/d converted data (lower 4 bits) bit initial value read/write adru 0 adru0 0 r 2 adru2 0 r 1 adru1 0 r 3 adru3 1 r a/d converted data (upper 4 bits)
368 15.2.4 a/d channel register (acr: $016) acr is a 4-bit write-only register that selects the input channel for which a/d conversion will be performed. acr3 acr2 acr1 acr0 hd404344r hd404394 hd404318/ hd404358/ hd404358r hd404339/ hd404369 0 1 0 1 0 1 0 1 0 1 0 1 * 0 1 0 1 0 1 0 1 0 1 0 1 * an 0 an 1 an 2 an 3 an 1 an 2 an 3 an 0 an 1 an 2 an 3 an 4 an 5 an 6 an 7 an 0 an 1 an 2 an 3 an 4 an 5 an 6 an 7 an 8 an 9 an 10 an 11 * don't care bit initial value read/write 0 acr0 0 w 2 acr2 0 w 1 acr1 0 w 3 acr3 0 w analog input channel selection input channel : unused note:
369 bits 3 to 0?nalog input channel selection (acr3 to acr0): these bits select the analog input channel. hd404344r series acr3 acr2 acr1 acr0 description 0000 analog input channel 0 (an0) selected. (initial value) 1 analog input channel 1 (an1) selected. 1 0 analog input channel 2 (an2) selected. 1 analog input channel 3 (an3) selected. 1 ** unused 1 *** note: * don t care hd404394 series acr3 acr2 acr1 acr0 description 0000 unused (initial value) 1 analog input channel 1 (an1) selected. 1 0 analog input channel 2 (an2) selected. 1 analog input channel 3 (an3) selected. 1 ** unused 1 *** note: * don t care hd404318/hd404358/hd404358r series acr3 acr2 acr1 acr0 description 0000 analog input channel 0 (an0) selected. (initial value) 1 analog input channel 1 (an1) selected. 1 0 analog input channel 2 (an2) selected. 1 analog input channel 3 (an3) selected. 1 0 0 analog input channel 4 (an4) selected. 1 analog input channel 5 (an5) selected. 1 0 analog input channel 6 (an6) selected. 1 analog input channel 7 (an7) selected. 1 *** unused note: * don t care
370 hd404339/hd404369 series acr3 acr2 acr1 acr0 description 0000 analog input channel 0 (an0) selected. (initial value) 1 analog input channel 1 (an1) selected. 1 0 analog input channel 2 (an2) selected. 1 analog input channel 3 (an3) selected. 1 0 0 analog input channel 4 (an4) selected. 1 analog input channel 5 (an5) selected. 1 0 analog input channel 6 (an6) selected. 1 analog input channel 7 (an7) selected. 1000 analog input channel 8 (an8) selected. 1 analog input channel 9 (an9) selected. 1 0 analog input channel 10 (an10) selected. 1 analog input channel 11 (an11) selected. 1 ** unused note: * don t care
371 15.2.5 a/d start flag (adsf: $020, 2) adsf starts the a/d conversion process. when adsf is set to 1, the a/d converter starts. when the conversion completes, the converted data is transferred to the adrl/u pair and adsf is cleared to 0. adsf can be read and written using the ram bit manipulation instructions. adsf is cleared to 0 on reset and in stop mode. adsf description 0 (read) indicates that the a/d conversion had completed. (initial value) (write) the value 0 cannot be written. 1 (read) an a/d conversion is in progress. (write) starts the a/d converter. 15.2.6 iad off flag (iaof: $021, 2) the current flow through the resistor ladder can be cut off by setting iaof to 1 in either standby mode or active mode. however, the a/d converter will not operate correctly in this state. do not use the a/d converter when iaof is set to 1. iaof description 0 current flows in the resistor ladder. (initial value) 1 no current flows in the resistor ladder.
372 15.3 a/d converter operation 15.3.1 a/d conversion operation figure 15-2 shows the a/d conversion operation sequence. a/d conversion completes. 1. select the analog input channel and set the a/d conversion time. (amr1, amr2, acr) 2. start an a/d conversion. (adsf = 1) 3. the converted data is transferred to the adrl/u pair. (adsf = 0, ifad = 1) 4. read out the adrl/u pair. figure 15-2 a/d conversion operation sequence an a/d converter operation proceeds as follows. 1. select the analog input channel and set the a/d conversion time using the amr register (amr1, amr2, and acr). 2. start an a/d conversion by setting adsf to 1. 3. when the a/d conversion completes, the converted data is transferred to the adrl/u pair, and adsf is cleared to 0. at the same time, ifad is set to 1. 4. read out the data from the adrl/u pair. figure 15-3 shows the timing chart for a/d converter operation.
373 adsf ifad adrl, adru t cyc : system clock period a/d conversion time (34t cyc or 67t cyc ) a/d conversion time (34t cyc or 67t cyc ) set set clear clear read read undefined conversion result undefined conversion result figure 15-3 a/d converter operation timing chart 15.3.2 low power mode operation the current supplied to the resistor ladder is cut off in stop mode, watch mode*, and subactive mode. as a result, the a/d converter does not operate in these modes. note: * applies to the hd404339 and hd404369 series.
374 15.3.3 a/d converter precision since an a/d converter converts an analog signal to a digital code, there is, in principle, a quantization error (defined to be 1/2 the lsb) associated with the conversion. figure 15-4 shows the correspondence between an eight-bit resolution a/d converter? analog input voltage and the result of the conversion. $ff $fe $fd $03 $02 $01 $00 2 1 3 254 253 255 256 256 256 256 256 256 1 note: the analog input voltage in this figure is scaled to av cc av ss = 1. a/d conversion result (8 bits) quantization error ideal a/d conversion characteristics analog input voltage figure 15-4 correspondence between a/d converter analog input and digital output the difference between the result of an a/d conversion and the analog input is called the absolute precision. see the ?/d converter characteristics?item for each series in section 25, ?lectrical characteristics? for the absolute precision provided by these a/d converters.
375 15.3.4 notes on the analog reference power supply in products in which the a/d converter reference voltage is fixed at av cc or v cc (the hd404344r, hd404318, hd404358, hd404358r, hd404339, and hd404369 series), the resolution is fixed at av cc /256 or v cc /256. (note that a reference voltage in the range v cc ?0.3 av cc v cc + 0.3 must be used even in products that provide an av cc pin.) the hd404394 series microcomputers, which include a v ref pin, support a/d conversions with an even higher resolution (v ref /256) by varying the v ref pin voltage. however, the voltage applied to the v ref pin must be in the range v cc /2 v ref v cc . 15.4 interrupts the a/d converter interrupt source is the completion of a/d conversion. when a/d conversion completes, the ifad bit in the interrupt control bit area is set to 1. ifad is never cleared automatically, even if the interrupt is accepted. the interrupt handling routine should clear ifad to 0. the a/d interrupt can be independently enabled or masked with the a/d interrupt mask (imad) in the interrupt control bit area.
376 15.5 usage notes keep the following points in mind when using the a/d converter. ? adsf is allocated in the register flag area. use the sem and semd instructions to set adsf. do not attempt to write a 0 to adsf. ? do not write adsf during an a/d conversion. ? the contents of the adrl/u pair are undefined during an a/d conversion. ? do not write a 1 to iaof during an a/d conversion. ? the pull-up mos transistors on r port/analog input shared function pins are not turned off by selecting the pin for use as an analog input pin with amr1 if the mis mis3 bit is set to 1 (pull-up mos transistors active) and the pdr for the corresponding pin is set to 1. if the pull- up mos transistors are activated, always be sure to turn off the pull-up mos transistor for the pin being used as an analog input pin by clearing to 0 the pdr for that pin. note that the pdrs are set to 1 immediately following a reset. figure 15-5 shows the circuit structure of the r port/analog input shared function pins. amr1 is a register that is used to set the port output to the high impedance state. acr is used to switch the pin function to the analog input function. table 15-3 lists the states of the r port/analog input shared function pins that can be set by combinations of the amr1 (amr2), mis3 bit, dcr, and pdr settings.
377 v cc v cc hlt mis3 dcr pdr amr (a/d mode register setting value) acr (a/d channel register setting value) input control signal input data a/d input pull-up control signal buffer control signal output data figure 15-5 r port/analog input shared function pin circuit
378 table 15-3 program control of r port/analog input shared function pin states corresponding bit in amr1 or amr2 0 (r port selected) mis3 bit 0 1 dcr 0101 pdr 01010101 cmos buffer pmos on on nmos on on pull-up mos transistor on on note: : off corresponding bit in amr1 or amr2 1 (analog input selected) mis3 bit 0 1 dcr 0101 pdr 01010101 cmos buffer pmos nmos pull-up mos transistor on on note: : off 15.6 notes on mounting built-in a/d converter microcomputers (hd404318 and hd404339 series only) observe the following points when designing and implementing built-in a/d converter microcomputers circuits. ? insert bypass capacitors (laminated ceramic type) of about 0.1 ? between av cc and av ss and between pins used as analog pins and av ss . also, connect unused analog pins to av ss . figure 15-6 (a) shows connection examples for the hd404318 series, and figure 15-6 (b) shows connection examples for the hd404339 series.
379 av cc an 0 an 1 an 7 an 2 av ss av cc an 0 an 1 an 7 an 2 av ss av cc an 0 an 1 an 7 an 2 av ss v cc gnd v cc v cc gnd gnd 0.1 f to to to when an 0 to an 7 are unused and the r3 and r4 ports are also unused when an 0 and an 1 are used, and an 2 to an 7 are unused when an 0 to an 7 (all the analog pins) are used three 0.1 f capacitors nine 0.1 f capacitors figure 15-6 (a) connection examples for av cc /av ss and av ss and the used analog pins (hd404318 series)
380 av cc an 0 an 1 an 11 an 2 av ss av cc an 0 an 1 an 11 an 2 av ss av cc an 0 an 1 an 11 an 2 av ss v cc gnd v cc v cc gnd gnd 0.1 f when an 0 to an 11 are unused and the r3 to r5 ports are also unused when an 0 and an 1 are used, and an 2 to an 11 are unused when an 0 to an 11 (all the analog pins) are used three 0.1 f capacitors thirteen 0.1 f capacitors to to to figure 15-6 (b) connection examples for av cc /av ss and av ss and the used analog pins (hd404339 series)
381 ? connect the capacitor used in normal power supply circuit design between v cc and ground. since there will be no resistors inserted in series in the power supply circuit, the capacitors are connected in parallel. thus a total of two capacitors, a large capacitor (c1) and a small capacitor (c2) are used. figure 15-7 shows this circuit. gnd gnd v cc v cc c 1 c 2 power supply line connection circuit example figure 15-7 v cc to ground circuit example
382
383 section 16 prescalers 16.1 overview the microcomputers in the hmcs43xx family include one or two built-in prescalers. the prescaler(s) provided differ between product series. series prescaler hd404344r/hd404394/hd404318/hd404358/ hd404358r hd404339/hd404369 prescaler s (pss) prescaler w (psw) the internal clocks for timers a to c and the operating clocks for each built-in peripheral module are selected from the prescaler outputs by the mode registers for the built-in peripheral modules. table 16-1 lists the input clocks and operating conditions for the prescalers. table 16-1 prescaler input clocks and operating conditions hd404344r/hd404394/hd404318/hd404358/hd404358r series item input clock reset condition stop condition prescaler s ? system clock ? system reset ? system reset ? stop mode hd404339/hd404369 series item input clock reset condition stop condition prescaler s ? in active mode and standby mode: system clock ? in subactive mode: subsystem clock ? system reset ? system reset ? stop mode ? watch mode prescaler w ? a clock generated by dividing the 32.768 khz subsystem clock by eight. ? system reset ? software * ? system reset ? stop mode note: * psw is cleared to 0 when all the bits tma3 to tma1 in timer mode register a (tma) are set to 1.
384 figure 16-1 (a) shows the prescaler output destinations for the hd404344r and hd404394 series, figure 16-1 (b) shows the destinations for the hd404318, hd404358, and hd404358r series, and figure 16-1 (c) shows the destinations for the hd404339 and hd404369 series. system clock prescaler s timer b timer c serial interface figure 16-1 (a) prescaler output destinations (hd404344r and hd404394 series)
385 system clock prescaler s timer b timer c serial interface timer a alarm output circuit figure 16-1 (b) prescaler output destinations (hd404318, hd404358, and hd404358r series)
386 subsystem clock prescaler w timer b timer c serial interface timer a alarm output circuit system clock clock selector prescaler s figure 16-1 (c) prescaler output destinations (hd404339 and hd404369 series)
387 16.2 prescaler s (pss) pss is an 11-bit counter that takes the system clock as its input in active mode and standby mode, and the subsystem clock in subactive mode*. pss is initialized to $000 on reset, and divides the system clock after the reset is cleared. although pss operation stops during reset, in stop mode, and in watch mode*, it continues to operate in all other operating modes. although the pss output is supplied to all the built-in peripheral modules, the divisor it implements can be selected independently for each built-in peripheral module. note: * applies to the hd404339 and hd404369 series. 16.3 prescaler w (psw) (hd404339 and hd404369 series only) psw is a 5-bit counter that takes as its input a clock generated by dividing the 32.768 khz subsystem clock by eight. psw is initialized to $00 on reset, and divides the subsystem clock after the reset is cleared. although psw stops during reset and in stop mode, it continues to operate in all other operating modes. psw can be reset in software. only timer a uses the psw output.
388
389 section 17 timer a (hd404318/hd404358/hd404358r/hd404339 /hd404369 series) 17.1 overview the microcomputers in the hd404318, hd404358, hd404358r, hd404339, and hd404369 series include the timer a peripheral module. (the microcomputers in the hd404344r and hd404394 series do not include timer a.) 17.1.1 features timer a is an eight-bit free-running timer. timer a can also be used as a clock time base in microcomputers in the hd404339 and hd404369 series, which include the 32.768 khz subsystem clock oscillator. hd404318/hd404358/hd404358rseries ? the timer clock can be selected from one of eight internal clock signals (2048t cyc , 1024t cyc , 512t cyc , 128t cyc , 32t cyc , 8t cyc , 4t cyc , and 2t cyc ) generated by prescaler s (pss). ? interrupts can be generated on timer counter a (tca) overflow. hd404339/hd404369 series ? the timer clock can be selected from one of eight internal clock signals (with periods of 2048t cyc , 1024t cyc , 512t cyc , 128t cyc , 32t cyc , 8t cyc , 4t cyc , and 2t cyc ) when prescaler s (pss) is used. ? the timer clock can be selected from one of five internal clock signals (with periods of 32t wcyc , 16t wcyc , 8t wcyc , 2t wcyc , and 1/2t wcyc ) when prescaler w (psw) is used (when timer a is used as a clock time base). ? interrupts can be generated by the overflow of the timer counter a (tca) register. note: t cyc (which is 1/ per ) is the period of one pss count cycle, and t wcyc (which is 244.24 ?) is the period of one psw count cycle.
390 17.1.2 block diagram figures 17-1 (a) and (b) show the block diagrams of timer a in the hd404318, hd404358, and hd404358r series and in the hd404339 and hd404369 series, respectively. 2 4 8 32 128 512 1024 per 3 2048 : data bus : clock line : signal line system clock prescaler s (pss) selector timer mode register a (tma) timer a interrupt request flag (ifta) timer counter a (tca) overflow internal data bus figure 17-1 (a) timer a block diagram (hd404318, hd404358, and hd404358r series)
391 2 4 8 32 128 512 2048 3 2 16 8 32 per 32.768 khz f w t wcyc 1/2t wcyc 2f w 1024 1/4 1/2 : data bus : clock line : signal line oscillator prescaler w (psw) selector timer a interrupt request flag (ifta) selector clock timer counter a (tca) overflow internal data bus selector system clock prescaler s (pss) timer mode register a (tma) figure 17-1 (b) timer a block diagram (hd404339 and hd404369 series)
392 17.1.3 register configuration table 17-1 lists the registers associated with timer a. table 17-1 timer a register structure address register symbol r/w initial value $008 timer mode register a tma w $0 timer counter a tca $00
393 17.2 register descriptions 17.2.1 timer mode register a (tma: $008) hd404318/hd404358/hd404358r series tma is a 4-bit write-only register that selects the divisor for prescaler s, which is used as the timer a clock source. tma is initialized to $0 on reset and in stop mode. bit initial value read/write 3 0 tma0 0 w 2 tma2 0 w 1 tma1 0 w 0 1 0 1 2048 t cyc 1024 t cyc 512 t cyc 128 t cyc 32 t cyc 8 t cyc 4 t cyc 2 t cyc 0 1 0 1 0 1 0 1 0 1 tma2 tma1 tma0 note: t cyc = f osc /4 unused timer a clock selection input clock period
394 bits 2 to 0?imer a clock selection (tma2 to tma0): these bits select the timer a clock source divisor. description input clock period tma2 tma1 tma0 source prescaler symbol f osc = 400 khz f osc = 800 khz f osc = 2 mhz f osc = 4 mhz 0 0 0 pss 2048t cyc 20.48 ms 10.24 ms 4.096 ms 2.048 ms 1 pss 1024t cyc 10.24 ms 5.12 ms 2.048 ms 1.024 ms 1 0 pss 512t cyc 5.12 ms 2.56 ms 1.024 ms 512 s 1 pss 128t cyc 1.28 ms 640 s 256 s 128 s 1 0 0 pss 32t cyc 320 s 160 s 64 s 32 s 1 pss 8t cyc 80 s 40 s 16 s 8 s 1 0 pss 4t cyc 40 s 20 s 8 s 4 s 1 pss 2t cyc 20 s 10 s 4 s 2 s
395 hd404339/hd404369 series tma is a 4-bit write-only register that selects the prescaler to be used as the timer a clock source (pss or psw) and the divisor used. tma is initialized to $0 on reset and in stop mode. bit initial value read/write 3 tma3 0 w 0 tma0 0 w 2 tma2 0 w 1 tma1 0 w 0 1 0 1 0 1 0 1 2048 t cyc * 1 1024 t cyc 512 t cyc 128 t cyc 32 t cyc 8 t cyc 4 t cyc 2 t cyc 32 t wcyc * 2 16 t wcyc 8 t wcyc 2 t wcyc 1/2 t wcyc unused clears psw and tca 0 1 0 1 0 1 0 1 0 1 0 1 0 1 * 0 1 0 1 tma3 tma1 tma0 0 1 tma2 pss pss pss pss pss pss pss pss psw psw psw psw timer a clock selection prescaler input clock period mode free- running timer mode clock time base mode notes: 1. 2. t cyc = f osc /4, f osc /8, f osc /16, or f osc /32 t wcyc = f x /8 * don t care bit 3?imer a source prescaler selection (tma3): selects pss or psw as the timer a clock source. tma3 description 0 pss is used as the timer a clock source. (initial value) 1 psw is used as the timer a clock source.
396 bits 2 to 0?imer a clock selection (tma2 to tma0): these bits select the timer a clock source period. the period selected depends on the combination with tma3 as follows. ? free-running mode a. system clock divisor: 4 (ssr21, ssr20* = 00) description input clock period tma3 tma2 tma1 tma0 source prescaler symbol f osc = 400 khz f osc = 800 khz f osc = 2 mhz f osc = 4 mhz 0000pss 2048t cyc 20.48 ms 10.24 ms 4.096 ms 2.048 ms 1 pss 1024t cyc 10.24 ms 5.12 ms 2.048 ms 1.024 ms 1 0 pss 512t cyc 5.12 ms 2.56 ms 1.024 ms 512 s 1 pss 128t cyc 1.28 ms 640 s 256 s 128 s 1 0 0 pss 32t cyc 320 s 160 s 64 s 32 s 1 pss 8t cyc 80 s 40 s 16 s 8 s 1 0 pss 4t cyc 40 s 20 s 8 s 4 s 1 pss 2t cyc 20 s 10 s 4 s 2 s note: * system clock selection register 2 (ssr2) bits 1 and 0 b. system clock divisor: 8 (ssr21, ssr20* = 01) description input clock period tma3 tma2 tma1 tma0 source prescaler symbol f osc = 400 khz f osc = 800 khz f osc = 2 mhz f osc = 4 mhz 0000pss 2048t cyc 40.96 ms 20.48 ms 8.192 ms 4.096 ms 1 pss 1024t cyc 20.48 ms 10.24 ms 4.096 ms 2.048 ms 1 0 pss 512t cyc 10.24 ms 5.12 ms 2.048 ms 1.024 ms 1 pss 128t cyc 2.56 ms 1.28 ms 512 s 256 s 1 0 0 pss 32t cyc 640 s 320 s 128 s 64 s 1 pss 8t cyc 160 s 80 s 32 s 16 s 1 0 pss 4t cyc 80 s 40 s 16 s 8 s 1 pss 2t cyc 40 s 20 s 8 s 4 s note: * system clock selection register 2 (ssr2) bits 1 and 0
397 c. system clock divisor: 16 (ssr21, ssr20* = 10) description input clock period tma3 tma2 tma1 tma0 source prescaler symbol f osc = 400 khz f osc = 800 khz f osc = 2 mhz f osc = 4 mhz 0000pss 2048t cyc 81.92 ms 40.96 ms 16.384 ms 8.192 ms 1 pss 1024t cyc 40.96 ms 20.48 ms 8.192 ms 4.096 ms 1 0 pss 512t cyc 20.48 ms 10.24 ms 4.096 ms 2.048 ms 1 pss 128t cyc 5.12 ms 2.56 ms 1.024 ms 512 s 1 0 0 pss 32t cyc 1.28 ms 640 s 256 s 128 s 1 pss 8t cyc 320 s 160 s 64 s 32 s 1 0 pss 4t cyc 160 s 80 s 32 s 16 s 1 pss 2t cyc 80 s 40 s 16 s 8 s note: * system clock selection register 2 (ssr2) bits 1 and 0 d. system clock divisor: 32 (ssr21, ssr20* = 11) description input clock period tma3 tma2 tma1 tma0 source prescaler symbol f osc = 400 khz f osc = 800 khz f osc = 2 mhz f osc = 4 mhz 0000pss 2048t cyc 163.84 ms 81.92 ms 32.768 ms 16.384 ms 1 pss 1024t cyc 81.92 ms 40.96 ms 16.384 ms 8.192 ms 1 0 pss 512t cyc 40.96 ms 20.48 ms 8.192 ms 4.096 ms 1 pss 128t cyc 10.24 ms 5.12 ms 2.048 ms 1.024 ms 1 0 0 pss 32t cyc 2.56 ms 1.28 ms 512 s 256 s 1 pss 8t cyc 640 s 320 s 128 s 64 s 1 0 pss 4t cyc 320 s 160 s 64 s 32 s 1 pss 2t cyc 160 s 80 s 32 s 16 s note: * system clock selection register 2 (ssr2) bits 1 and 0
398 ? clock time base mode description input clock period tma3 tma2 tma1 tma0 source prescaler symbol f x = 32.768 khz 1000psw 32t wcyc 7.8125 ms 1 psw 16t wcyc 3.9063 ms 1 0 psw 8t wcyc 1.9531 ms 1 psw 2t wcyc 488.28 s 100 1/2t wcyc 122.07 s 1 unused 1 * clears psw and tca. note: * don t care 17.2.2 timer counter a (tca) tca is an 8-bit increment-only counter that is incremented by the input internal clock. the input clock period is selected by the tma register*. it is not possible to read or write tca. when tca overflows the timer a interrupt request flag (ifta) is set to 1. tca is initialized to $00 on reset and in stop mode. bit initial value read/write 7 tca7 0 6 tca6 0 5 tca5 0 4 tca4 0 3 tca3 0 0 tca0 0 2 tca2 0 1 tca1 0 counter value note: * hd404318/hd404358/hd404358r series the pss output is selected by the tma tma2 to tma0 bits. the tma tma3 bit is unused. the frequency of the system clock ( per ) divided by pss is fixed at 1/4 the oscillator frequency ( per = f osc /4). hd404339/hd404369 series the pss or psw output is selected by the tma tma3 to tma0 bits. the frequency of the system clock ( per ) divided by pss can be selected to be 1/4, 1/8, 1/16, or 1/32 of the oscillator frequency, i.e., per = f osc /4, f osc /8, f osc /16, or f osc /32 by system clock selection register 2 (ssr2). the frequency of the subsystem clock (f w ) divided by psw is fixed at 1/8 the oscillator frequency (f w = f x /8). writing 111 to bits tma3 to tma1 of tma clears psw and tca.
399 17.3 timer a operation 17.3.1 free-running timer operation timer a can be used as an 8-bit free-running timer. hd404318/hd404358/hd404358r series timer a is incremented continuously immediately following a reset. hd404339/hd404369 series timer a operates as a free-running timer when the tma tma3 bit is set to 0. since tca is cleared to $00 and tma3 is cleared to 0 on reset, timer a is incremented continuously immediately following a reset and thus functions as a free-running timer. tca cannot be cleared when timer a is operating as a free-running timer, i.e., when the tma3 bit is 0. the following describes the free-running timer operation common to the microcomputers in the hd404318, hd404358, hd404358r, hd404339, and hd404369 series. timer a operates on one of eight internal clocks output from pss and selected by the tma tma2 to tma0 bits. timer a overflows on the next clock input after the tca counter reaches $ff and ifta is set to 1. a cpu interrupt is generated if the timer a interrupt mask is 0 at that time. see section 4, exception handling , for details on interrupts. on an overflow, the tca value returns to $00, and tca begins to count up once again. thus timer a functions as an interval timer that outputs an overflow periodically every 256 input clock periods.
400 17.3.2 clock time base operation hd404339/hd404369 series when the tma tma3 bit is set to 1 timer a functions as a clock time base. the tma tma2 to tma0 bits select the timer a operating clock to be one of five internal clocks: four clocks output from psw and a clock that is not modified by psw. clock time base operation generates interrupts with a precise timing by using the 32.768 khz crystal oscillator as the base clock. in clock time base operation (when the tma3 bit is 1) tca and psw can be cleared to $00 by setting both tma2 and tma1 to 1. clock time base mode is used when switching to and clearing watch and subactive modes. see section 6, low power modes , for details. 17.4 interrupts the timer a interrupt source is generated by tca overflow. when tca overflows, ifta in the interrupt control bit area is set to 1. ifta is never cleared automatically, even if the interrupt is accepted. the interrupt handling routine should clear ifta to 0. the timer a interrupt can be independently enabled or disabled by imta in the interrupt control bit area. see section 4, exception handling , for details. 17.5 usage notes errors in the overflow period can occur if the divisor is changed during operation in time base mode. do not change the divisor during timer operation.
401 section 18 timer b 18.1 overview 18.1.1 features timer b is an 8-bit multifunction (free-running/event counter/reload timer/input capture*) timer with the following features. note: * applies to the hd404318, hd404358, hd404358r, hd404339, and hd404369 series. timer b in the hd404344r and hd404394 series does not support the input capture function. hd404344r/hd404394 series ? the timer clock can be selected from one of seven internal clocks (2048t cyc , 512t cyc , 128t cyc , 32t cyc , 8t cyc , 4t cyc , and 2t cyc ), from prescaler s (pss), or taken from an external event input. ? an interrupt can be generated on timer counter b (tcb) overflow. hd404318/hd404358/hd404358r/hd404339/hd404369 series ? the timer clock can be selected from one of seven internal clocks (2048t cyc , 512t cyc , 128t cyc , 32t cyc , 8t cyc , 4t cyc , and 2t cyc ) from prescaler s (pss), or taken from an external event input. ? an interrupt can be generated on timer counter b (tcb) overflow. ? timer b also supports input capture operation triggered by an external event input. ? interrupts can be generated on input capture events.
402 18.1.2 block diagram figure 18-1 shows the block diagram for timer b during free-running and reload timer operation. (twbl) (twbu) 2 4 8 32 128 512 2048 2 3 4 4 4 evnb (tcbl) (tcbu) edge detection logic system clock per prescaler s (pss) selector timer mode register b1 (tmb1) edge detection control timer mode register b2 (tmb2) free- running control timer b interrupt request flag (iftb) timer read register bl (trbl) timer counter b timer write register b internal data bus : data bus : clock line : signal line figure 18-1 timer b block diagram (free-running and reload timer)
403 figure 18-2 shows the block diagram for timer b during input capture operation. (hd404318, hd404358, hd404358r, hd404339, and hd404369 series) (tcbl) (tcbu) per 2 3 4 4 evnb (trbl) (trbu) edge detection logic system clock prescaler s (pss) selector timer mode register b1 (tmb1) edge detection control timer mode register b2 (tmb2) input capture status flag (icsf) input capture error flag (icef) error control logic timer b interrupt request flag (iftb) timer read register b timer counter b input capture timer control internal data bus overflow : data bus : clock line : signal line figure 18-2 timer b block diagram (hd404318, hd404358, hd404358r, hd404339, and hd404369 series) (input capture timer)
404 18.1.3 timer b pins table 18-1 lists the timer b pins. table 18-1 timer b pins pin symbol i/o function timer b event input evnb input timer b event input and input capture timer trigger input pin * note: * applies to the hd404318, hd404358, hd404358r, hd404339, and hd404369 series. timer b in the hd404344r and hd404394 series does not support the input capture function. 18.1.4 register configuration table 18-2 lists the registers used by timer b. table 18-2 register configuration address register symbol r/w initial value $009 timer mode register b1 tmb1 w $0 $026 timer mode register b2 tmb2 w $0 timer counter b tcb $00 $00a timer write register bl twbl w $0 $00b timer write register bu twbu w undefined $00a timer read register bl trbl r undefined $00b timer read register bu trbu r undefined $024 port mode register b pmrb w $0 $021, 0 input capture status flag * icsf * r/w * 0 $021, 1 input capture error flag * icef * r/w * 0 note: * applies to the hd404318, hd404358, hd404358r, hd404339, and hd404369 series. timer b in the hd404344r and hd404394 series does not support the input capture function. icsf and icef are allocated in the register flag area and can be manipulated with the ram bit manipulation instructions. a value of 1 can be written to these flags to set them, but they cannot be cleared to 0 by program instructions. see section 2, memory , for details.
405 18.2 register descriptions 18.2.1 timer mode register b1 (tmb1: $009) tmb1 is a 4-bit write-only register that selects the timer b function (free-running or reload timer) and the operating clock. tmb1 is cleared to $0 on reset and in stop mode. bit initial value read/write 3 tmb13 0 w 0 tmb10 0 w 2 tmb12 0 w 1 tmb11 0 w 0 1 0 1 2048 t cyc 512 t cyc 128 t cyc 32 t cyc 8 t cyc 4 t cyc 2 t cyc evnb (external event input pin) 0 1 0 1 0 1 0 1 0 1 tmb12 tmb11 tmb10 timer b clock selection 0 1 timer b function selection free-running timer reload timer input clock source note: set port mode register b to the values shown below when the timer b clock is taken from external event input. hd404344r and hd404394 series: set the pmrb0 bit to 1. hd404318, hd404358, hd404358r, hd404339, and hd404369 series: set the pmrb2 bit to 1. bit 3?imer b function selection (tmb13): selects the timer b function. tmb13 description 0 selects the free-running timer function. (initial value) 1 selects the reload timer function.
406 bits 2 to 0?imer b clock selection (tmb12 to tmb10): these bits select the timer b input clock. ? active mode hd404344r/hd404394/hd404318/hd404358/hd404358r series description input clock period tmb12 tmb11 tmb10 source prescaler symbol f osc = 400 khz f osc = 800 khz f osc = 2 mhz f osc = 4 mhz 0 0 0 pss 2048t cyc 20.48 ms 10.24 ms 4.096 ms 2.048 ms 1 pss 512t cyc 5.12 ms 2.56 ms 1.024 ms 512 s 1 0 pss 128t cyc 1.28 ms 640 s 256 s 128 s 1 pss 32t cyc 320 s 160 s 64 s 32 s 1 0 0 pss 8t cyc 80 s 40 s 16 s 8 s 1 pss 4t cyc 40 s 20 s 8 s 4 s 1 0 pss 2t cyc 20 s 10 s 4 s 2 s 1 external event input (evnb pin) hd404339/hd404369 series 1. system clock divisor: 4 (ssr21, ssr20 * = 00) description input clock period tmb12 tmb11 tmb10 source prescaler symbol f osc = 400 khz f osc = 800 khz f osc = 2 mhz f osc = 4 mhz 0 0 0 pss 2048t cyc 20.48 ms 10.24 ms 4.096 ms 2.048 ms 1 pss 512t cyc 5.12 ms 2.56 ms 1.024 ms 512 s 1 0 pss 128t cyc 1.28 ms 640 s 256 s 128 s 1 pss 32t cyc 320 s 160 s 64 s 32 s 1 0 0 pss 8t cyc 80 s 40 s 16 s 8 s 1 pss 4t cyc 40 s 20 s 8 s 4 s 1 0 pss 2t cyc 20 s 10 s 4 s 2 s 1 external event input (evnb pin) note: * system clock selection register 2 (ssr2) bits 1 and 0
407 hd404339/hd404369 series 2. system clock divisor: 8 (ssr21, ssr20 * = 01) description input clock period tmb12 tmb11 tmb10 source prescaler symbol f osc = 400 khz f osc = 800 khz f osc = 2 mhz f osc = 4 mhz 0 0 0 pss 2048t cyc 40.96 ms 20.48 ms 8.192 ms 4.096 ms 1 pss 512t cyc 10.24 ms 5.12 ms 2.048 ms 1.024 ms 1 0 pss 128t cyc 2.56 ms 1.28 ms 512 s 256 s 1 pss 32t cyc 640 s 320 s 128 s 64 s 1 0 0 pss 8t cyc 160 s 80 s 32 s 16 s 1 pss 4t cyc 80 s 40 s 16 s 8 s 1 0 pss 2t cyc 40 s 20 s 8 s 4 s 1 external event input (evnb pin) note: * system clock selection register 2 (ssr2) bits 1 and 0 3. system clock divisor: 16 (ssr21, ssr20 * = 10) description input clock period tmb12 tmb11 tmb10 source prescaler symbol f osc = 400 khz f osc = 800 khz f osc = 2 mhz f osc = 4 mhz 0 0 0 pss 2048t cyc 81.92 ms 40.96 ms 16.384 ms 8.192 ms 1 pss 512t cyc 20.48 ms 10.24 ms 4.096 ms 2.048 ms 1 0 pss 128t cyc 5.12 ms 2.56 ms 1.024 ms 512 s 1 pss 32t cyc 1.28 ms 640 s 256 s 128 s 1 0 0 pss 8t cyc 320 s 160 s 64 s 32 s 1 pss 4t cyc 160 s 80 s 32 s 16 s 1 0 pss 2t cyc 80 s 40 s 16 s 8 s 1 external event input (evnb pin) note: * system clock selection register 2 (ssr2) bits 1 and 0
408 hd404339/hd404369 series 4. system clock divisor: 32 (ssr21, ssr20 * = 11) description input clock period tmb12 tmb11 tmb10 source prescaler symbol f osc = 400 khz f osc = 800 khz f osc = 2 mhz f osc = 4 mhz 0 0 0 pss 2048t cyc 163.84 ms 81.92 ms 32.768 ms 16.384 ms 1 pss 512t cyc 40.96 ms 20.48 ms 8.192 ms 4.096 ms 1 0 pss 128t cyc 10.24 ms 5.12 ms 2.048 ms 1.024 ms 1 pss 32t cyc 2.56 ms 1.28 ms 512 s 256 s 1 0 0 pss 8t cyc 640 s 320 s 128 s 64 s 1 pss 4t cyc 320 s 160 s 64 s 32 s 1 0 pss 2t cyc 160 s 80 s 32 s 16 s 1 external event input (evnb pin) note: * system clock selection register 2 (ssr2) bits 1 and 0 ? subactive mode hd404339/hd404369 series description input clock period source f x = 32.768 khz (in subactive mode) tmb12 tmb11 tmb10 prescaler symbol ssr12 * = 0 ssr12 * = 1 0 0 0 pss 2048t cyc 500 ms 250 ms 1 pss 512t cyc 125 ms 62.5 ms 1 0 pss 128t cyc 31.25 ms 15.625 ms 1 pss 32t cyc 7.8125 ms 3.9063 ms 1 0 0 pss 8t cyc 1.9531 ms 976.56 s 1 pss 4t cyc 976.56 s 488.28 s 1 0 pss 2t cyc 488.28 s 244.14 s 1 pss external event input (evnb pin) note: * system clock selection register 1 (ssr1) bit 2
409 18.2.2 timer mode register b2 (tmb2: $026) tmb2 is a 3-bit write-only register that selects the input capture function and the evnb pin input edge detection type. tmb2 is initialized to $0 on reset and in stop mode. bit initial value read/write 3 0 tmb20 0 w 2 tmb22 * 0 w 1 tmb21 0 w 0 1 0 1 0 1 tmb21 tmb20 0 1 input capture setting * free-running/reload timer input capture timer evnb pin edge detection selection evnb pin edge detection no detection falling edge detection rising edge detection falling/rising edge pair detection note: * applies to the hd404318, hd404358, hd404358r, hd404339, and hd404369 series. tmb22 is unused in the hd404344r and hd404394 series. bit 2?nput capture setting (tmb22) hd404318/hd404358/hd404358r/hd404339/hd404369 series selects the timer b function. when this bit is 0, the tmb1 tmb13 bit selects either the free- running timer or the reload timer function. tmb22 description 0 selects the free-running/reload timer function. (initial value) 1 selects the input capture timer function.
410 bits 1 and 0?vnb pin edge detection selection (tmb21, tmb20) tmb21 tmb20 description 0 0 no edges are detected on the evnb pin input. (initial value) 1 falling edges are detected on the evnb pin input. 1 0 rising edges are detected on the evnb pin input. 1 falling/rising edge pairs are detected on the evnb pin input. 18.2.3 timer counter b (tcb) tcb is an 8-bit up counter that is incremented by the input internal clock. bit initial value read/write 7 tcb7 0 6 tcb6 0 5 tcb5 0 4 tcb4 0 3 tcb3 0 0 tcb0 0 2 tcb2 0 1 tcb1 0 counter value the tcb input clock is selected by the tmb1 tmb12 to tmb10 bits. the value in tcb can be read by reading out the trbl/u pair, and tcb can be written by writing to the twbl/u pair. the timer b interrupt request flag (iftb) is set to 1 when tcb overflows. if the free-running timer function is selected for timer b (tmb13 = 0) at this time, tcb will be cleared to $00 and start to count again. if the reload timer function is selected for timer b (tmb13 = 1), the value in the twbl/u pair will be written to tcb and tcb will start counting from that value. tcb is initialized to $00 on reset and in stop mode.
411 18.2.4 timer write register twbl/u (twbl: $00a, twbu: $00b) the twbl/u pair form an 8-bit write-only register in which twbl is the upper digit and twbu is the lower digit. the twbl/u pair is used to set the initial value of tcb, i.e., to set the reload value in reload operation. bit initial value read/write 3 twbu3 undefined w 0 twbu0 undefined w 2 twbu2 undefined w 1 twbu1 undefined w twbu bit initial value read/write 3 twbl3 0 w 0 twbl0 0 w 2 twbl2 0 w 1 twbl1 0 w twbl data must be written in the order twbl first and then twbu. when twbl is written, the value in tcb does not change. next, when twbu is written, the value in twbu is transferred to the upper digit of tcb and the value in twbl is transferred to the lower digit of tcb. when the twbl/u pair is being written for the second or later time and there is no need to change the twbl reload value, timer b can be initialized by writing only twbu. twbl is initialized to $0 and twbu is undefined on reset and in stop mode.
412 18.2.5 timer read register trbl/u (trbl: $00a, trbu: $00b) the trbl/u pair form an 8-bit read-only register in which trbl and trbu directly read out the upper and lower digits respectively of tcb in timer b operating modes other than input capture operation*. that is, the trbl/u pair is used to read out the value in tcb. note: * applies to the hd404318, hd404358, hd404358r, hd404339, and hd404369 series. timer b in the hd404344r and hd404394 series does not support the input capture function. bit initial value read/write 3 trbu3 undefined r 0 trbu0 undefined r 2 trbu2 undefined r 1 trbu1 undefined r trbu bit initial value read/write 3 trbl3 undefined r 0 trbl0 undefined r 2 trbl2 undefined r 1 trbl1 undefined r trbl data must be read in the order trbu first and then trbl. when trbu is read out, the current value of the upper digit in tcb is returned and at the same time the value of the lower digit is latched into trbl. then, reading out the value in trbl returns that latched value. this means that the exact value of tcb at the point trbu was read is acquired. in input capture operation in hd404318, hd404358, hd404358r, hd404339, and hd404369 series microcomputers, trbl and trbu form an 8-bit register that latches the value in tcb, and can be read in any order. trbl and trbu are undefined on reset and in stop mode.
413 18.2.6 port mode register b (pmrb: $024) hd404344r/hd404394 series pmrb is a 2-bit write-only register whose pmrb0 bit switches an i/o pin for use as an event counter. this section describes the pmrb0 bit. see the ?ort mode register b?item in sections 7 and 8, ?/o ports? for details on the switching performed by the pmrb3 bit. bit initial value read/write 3 pmrb3 0 w 0 pmrb0 0 w 2 1 0 1 d 0 /int 0 /evnb pin function switch 0 1 d 4 / stopc stopc bit 0? 0 / int 0 /evnb pin function switch (pmrb0): selects whether the d 0 / int 0 /evnb pin functions as the d0 i/o pin or as the external interrupt 0/timer b event ( int 0 /evnb) input pin. pmrb0 description 0 the d 0 / int int int set the pmrb0 bit to 1 when this pin is to be used as the evnb pin. also, set the tmb1 tmb12 to tmb10 bits to 111, and select the edge detection type with the tmb2 tmb21 and tmb20 bits. note that the int 0 interrupt should normally be masked at this time. see section 18.2.1, ?imer mode register b1 (tmb1)? for more details.
414 hd404318/hd404358/hd404358r/hd404339/hd404369 series pmrb is a 4-bit write-only register whose pmrb2 bit switches an i/o pin to be used for event counting or input capture. this section describes the pmrb2 bit. see the ?ort mode register?items in sections 9 to 12, ?/o ports? for details on the switching performed by the pmrb3, pmrb1, and pmrb0 bits. bit initial value read/write 3 pmrb3 0 w 0 pmrb0 0 w 2 pmrb2 0 w 1 pmrb1 0 w 0 1 d 2 /evnb pin function switch 0 1 d 1 /int 1 pin function switch 0 1 d 0 /int 0 pin function switch 0 1 d 4 / stopc stopc bit 2? 2 /evnb pin function switch (pmrb2): selects whether the d 2 /evnb pin functions as the d 2 i/o pin or as the timer b event input pin (evnb). pmrb2 description 0 the d 2 /evnb pin functions as the d 2 i/o pin. (initial value) 1 the d 2 /evnb pin functions as the evnb input pin. set the pmrb0 bit to 1 when this pin is to be used as the evnb pin. also, set the tmb1 tmb12 to tmb10 bits to 111, and select the edge detection type with the tmb2 tmb21 and tmb20 bits. see section 18.2.1, ?imer mode register b1 (tmb1)? for more details.
415 18.2.7 input capture status flag (icsf: $021, 0) hd404318/hd404358/hd404358r/hd404339/hd404369 series icsf is set to 1 when the edge specified by bits tmb21 to tmb20 is detected on the evnb pin in input capture operation, i.e., when tmb22 is set to 1. icsf can be read and written (only 0 can be written) only by the ram bit manipulation instructions. icsf is cleared to 0 on reset and in stop mode. icsf description 0 indicates that no edge was detected in the input capture trigger input (evnb). (initial value) 1 indicates that an edge was detected in the input capture trigger input (evnb). 18.2.8 input capture error flag (icef: $021, 1) hd404318/hd404358/hd404358r/hd404339/hd404369 series icef is set to 1 if the next input capture event is detected when icsf is set to 1, or if tcb overflows when icsf is set to 1. icef can be read and written (only 0 can be written) only by the ram bit manipulation instructions. icef is cleared to 0 on reset and in stop mode. icef description 0 indicates that no input capture operating error has occurred. (initial value) 1 indicates that either the next input capture trigger was detected with icsf = 1, or that tcb overflowed with icsf = 1.
416 18.3 timer b operation timer b is an 8-bit multifunction timer. table 18-3 lists the functions supported for each series in the hmcs43xx family. the functions are selected by timer mode register b. table 18-3 timer b functions series function hd404344r/hd404394 hd404318/hd404358/hd404358r/ hd404339/hd404369 free-running timer reload timer external event counter input capture timer 18.3.1 free-running timer timer b can be used as an 8-bit free-running timer. when the tmb tmb22* bit is 0 and furthermore the tmb1 tmb13 bit is 0, timer b operates as an 8-bit free-running timer. since tcb is cleared to $00 and the tmb22* and tmb13 bits are cleared to 0 on reset, timer b is incremented continuously as a free-running timer immediately following a reset. the timer b operating clock is selected by tmb tmb12 to tmb10 to be one of seven internal clocks output from pss. note: * applies to the hd404318, hd404358, hd404358r, hd404339, and hd404369 series. this bit is unused in the hd404344r and hd404394 series. on the clock input after the count value in tcb reaches $ff, timer b overflows and iftb is set to 1. if the timer b interrupt mask (imtb) is 0 at this time, a cpu interrupt is generated. see section 4, ?xception handling? for details on interrupts. on an overflow, the tcb count returns to $00 and timer b begins to count again.
417 18.3.2 reload timer operation when the tmb tmb22* bit is 0 and furthermore the tmb1 tmb13 bit is 1, timer b operates as an 8-bit reload timer. when a reload value is loaded into the twbl/u pair, that value is loaded into tcb and timer b begins to count up from that value. on the clock input after the count value in tcb reaches $ff, timer b overflows, the value in the twbl/u pair is loaded into tcb, and timer b continues counting from that value. this means that the timer b overflow period can be set to be any value in the range 1 to 256 times the input clock period. the operating clock and interrupt operation during reload timer operation are identical to those for free-running timer operation. when a new reload value is loaded into the twbl/u pair that value is immediately written to tcb. note: * applies to the hd404318, hd404358, hd404358r, hd404339, and hd404369 series. the tmb22 bit is unused in the hd404344r and hd404394 series. 18.3.3 external event counter operation when the tmb1 tmb12 to tmb10 bits are set to 111, tcb is incremented by the evnb pin input signal edges specified by the tmb21 and tmb20 bits. other aspects of timer b operation in this mode are identical to either free-running or reload timer operation depending on the setting of the tmb1 tmb13 bit. 18.3.4 input capture timer operation hd404318/hd404358/hd404358r/hd404339/hd404369 series the input capture timer function measures the period between evnb input pin edge detection events. an internal clock must be selected as the tcb operating clock when timer b is used as an input capture timer. timer b operates as an input capture timer when the tmb2 tmb22 bit is set to 1. tcb will be cleared to $00 at that point. the tmb2 tmb21 and tmb20 bits select the edge detection event type, which can be either a falling edge, a rising edge, or a falling/rising edge pair on the evnb input pin. when an edge is detected on the evnb pin, the value of tcb at that time is written to the trbl/u pair and iftb and icsf are both set to 1. at the same time tcb is cleared to $00 and continues to count up from $00. icef is set to 1 if the next edge is detected when icsf is set to 1 or if tcb overflows.
418 when timer b is used as an input capture timer (when the tmb22 bit is 1) trbl and trbu can be read in any order. (see figure 18-2.) 18.4 interrupts timer b interrupts are generated on tcb overflow and on evnb pin edge detections during input capture timer operation*. when an interrupt is generated, iftb in the interrupt control bit area is set to 1. timer b in the hd404344r and hd404394 series does not support the input capture function. iftb is never cleared automatically, even if the interrupt is accepted. the interrupt handling routine should clear iftb to 0. the timer b interrupt can be independently enabled or disabled by imtb in the interrupt control bit area. note: * applies to the hd404318, hd404358, hd404358r, hd404339, and hd404369 series. timer b in the hd404344r and hd404394 series does not support the input capture function. 18.5 usage notes keep the following points in mind when using timer b. ? be sure to write twbl first and then twbu when using the twbl/u pair to set the tcb reload value or to initialize tcb. the value in the twbl/u pair is written to tcb at the point that twbu is written. thus if twbl has been set and only the value in the upper digit is to be changed, it is only necessary to write twbu. ? be sure to read trbu first and then trbl when reading the tcb value using the trbl/u pair. the value in the lower digit of tcb is latched into trbl when trbu is read. thus reading trbl returns the value of the tcb lower digit at the point trbu was last read. however, the trbl/u pair can be read in any order during input capture timer operation. ? when changing the value of tmb1, the new value becomes valid two instructions after the execution of the instruction that wrote tmb1. therefore it is necessary for programs that initialize timer b (set the reload value or initialize tcb) by writing to the twbl/u pair to perform this initialization only after the mode changed by tmb1 has become valid. ? when detection of falling/rising edge pairs on the evnb pin is selected by the tmb2 setting, the falling edge and the rising edge must be separated by at least 2t cyc .
419 section 19 timer c 19.1 overview 19.1.1 features timer c is an 8-bit multifunction timer (free-running/reload timer) with the following features. ? the timer clock can be selected from one of eight internal clocks (2048t cyc , 1024t cyc , 512t cyc , 128t cyc , 32t cyc , 8t cyc , 4t cyc , and 2t cyc ), from prescaler s (pss). ? timer c can be used as a watchdog timer. ? timer c can be used to generate waveform (pwm) output. ? an interrupt can be generated on timer counter c (tcc) overflow.
420 19.1.2 block diagram figure 19-1 shows the block diagram for timer c. 2 4 8 32 128 512 1024 3 4 4 4 toc 2048 system reset signal watchdog on flag (wdon) watchdog timer control logic timer c interrupt request flag (iftc) timer output control logic system clock per prescaler (pss) selector timer read register cl (trcl) internal data bus timer counter c (tccl) (tccu) timer write register c (twcl) (twcu) free- running/ reload control timer mode register c (tmc) timer output control port mode register a (pmra) : data bus : clock line : signal line figure 19-1 timer c block diagram
421 19.1.3 timer c pins table 19-1 lists the timer c pins. table 19-1 timer c pins pin symbol i/o function timer c output toc output timer c output pin 19.1.4 register configuration table 19-2 lists the registers used by timer c. table 19-2 register configuration address register symbol r/w initial value $00d timer mode register c tmc w $0 $004 port mode register a pmra w $0 timer counter c tcc $00 $00e timer write register cl twcl w $0 $00f timer write register cu twcu w undefined $00e timer read register cl trcl r undefined $00f timer read register cu trcu r undefined $020, 1 watchdog on flag wdon * r/w * 0 note: * wdon is allocated in the register flag area and can be manipulated only with the ram bit manipulation instructions. a value of 1 can be written to set this flag, but it cannot be cleared to 0 by program instructions. see section 2, ?emory? for details.
422 19.2 register descriptions 19.2.1 timer mode register c (tmc: $00d) tmc is a 4-bit write-only register that selects the timer c function (free-running or reload timer) and the operating clock. tmc is cleared to $0 on reset and in stop mode. bit initial value read/write 3 tmc3 0 w 0 tmc0 0 w 2 tmc2 0 w 1 tmc1 0 w 0 1 0 1 2048 t cyc 1024 t cyc 512 t cyc 128 t cyc 32 t cyc 8 t cyc 4 t cyc 2 t cyc 0 1 0 1 0 1 0 1 0 1 tmc2 tmc1 tmc0 timer c clock selection 0 1 timer c function selection free-running timer reload timer input clock cource bit 3?imer c function selection (tmc3): selects the timer c function. tmc3 description 0 selects the free-running timer function. (initial value) 1 selects the reload timer function.
423 bits 2 to 0?imer c clock selection (tmc2 to tmc0): these bits select the timer c input clock. ? active mode hd404344r/hd404394/hd404318/hd404358/hd404358r series description input clock period tmc2 tmc1 tmc0 source prescaler symbol f osc = 400 khz f osc = 800 khz f osc = 2 mhz f osc = 4 mhz 0 0 0 pss 2048t cyc 20.48 ms 10.24 ms 4.096 ms 2.048 ms 1 pss 1024t cyc 10.24 ms 5.12 ms 2.048 ms 1.024 ms 1 0 pss 512t cyc 5.12 ms 2.56 ms 1.024 ms 512 s 1 pss 128t cyc 1.28 ms 640 s 256 s 128 s 1 0 0 pss 32t cyc 320 s 160 s 64 s 32 s 1 pss 8t cyc 80 s 40 s 16 s 8 s 1 0 pss 4t cyc 40 s 20 s 8 s 4 s 1 pss 2t cyc 20 s 10 s 4 s 2 s hd404339/hd404369 series 1. system clock divisor: 4 (ssr21, ssr20 * = 00) description input clock period tmc2 tmc1 tmc0 source prescaler symbol f osc = 400 khz f osc = 800 khz f osc = 2 mhz f osc = 4 mhz 0 0 0 pss 2048t cyc 20.48 ms 10.24 ms 4.096 ms 2.048 ms 1 pss 1024t cyc 10.24 ms 5.12 ms 2.048 ms 1.024 ms 1 0 pss 512t cyc 5.12 ms 2.56 ms 1.024 ms 512 s 1 pss 128t cyc 1.28 ms 640 s 256 s 128 s 1 0 0 pss 32t cyc 320 s 160 s 64 s 32 s 1 pss 8t cyc 80 s 40 s 16 s 8 s 1 0 pss 4t cyc 40 s 20 s 8 s 4 s 1 pss 2t cyc 20 s 10 s 4 s 2 s note: * system clock selection register 2 (ssr2) bits 1 and 0
424 hd404339/hd404369 series 2. system clock divisor: 8 (ssr21, ssr20 * = 01) description input clock period tmc2 tmc1 tmc0 source prescaler symbol f osc = 400 khz f osc = 800 khz f osc = 2 mhz f osc = 4 mhz 0 0 0 pss 2048t cyc 40.96 ms 20.48 ms 8.192 ms 4.096 ms 1 pss 1024t cyc 20.48 ms 10.24 ms 4.096 ms 2.048 ms 1 0 pss 512t cyc 10.24 ms 5.12 ms 2.048 ms 1.024 ms 1 pss 128t cyc 2.56 ms 1.28 ms 512 s 256 s 1 0 0 pss 32t cyc 640 s 320 s 128 s 64 s 1 pss 8t cyc 160 s 80 s 32 s 16 s 1 0 pss 4t cyc 80 s 40 s 16 s 8 s 1 pss 2t cyc 40 s 20 s 8 s 4 s note: * system clock selection register 2 (ssr2) bits 1 and 0 3. system clock divisor: 16 (ssr21, ssr20 * = 10) description input clock period tmc2 tmc1 tmc0 source prescaler symbol f osc = 400 khz f osc = 800 khz f osc = 2 mhz f osc = 4 mhz 0 0 0 pss 2048t cyc 81.92 ms 40.96 ms 16.384 ms 8.192 ms 1 pss 1024t cyc 40.96 ms 20.48 ms 8.192 ms 4.096 ms 1 0 pss 512t cyc 20.48 ms 10.24 ms 4.096 ms 2.048 ms 1 pss 128t cyc 5.12 ms 2.56 ms 1.024 ms 512 s 1 0 0 pss 32t cyc 1.28 ms 640 s 256 s 128 s 1 pss 8t cyc 320 s 160 s 64 s 32 s 1 0 pss 4t cyc 160 s 80 s 32 s 16 s 1 pss 2t cyc 80 s 40 s 16 s 8 s note: * system clock selection register 2 (ssr2) bits 1 and 0
425 hd404339/hd404369 series 4. system clock divisor: 32 (ssr21, ssr20 * = 11) description input clock period tmc2 tmc1 tmc0 source prescaler symbol f osc = 400 khz f osc = 800 khz f osc = 2 mhz f osc = 4 mhz 0 0 0 pss 2048t cyc 163.84 ms 81.92 ms 32.768 ms 16.384 ms 1 pss 1024t cyc 81.92 ms 40.96 ms 16.384 ms 8.192 ms 1 0 pss 512t cyc 40.96 ms 20.48 ms 8.192 ms 4.096 ms 1 pss 128t cyc 10.24 ms 5.12 ms 2.048 ms 1.024 ms 1 0 0 pss 32t cyc 2.56 ms 1.28 ms 512 s 256 s 1 pss 8t cyc 640 s 320 s 128 s 64 s 1 0 pss 4t cyc 320 s 160 s 64 s 32 s 1 pss 2t cyc 160 s 80 s 32 s 16 s note: * system clock selection register 2 (ssr2) bits 1 and 0 ? subactive mode hd404339/hd404369 series description input clock period source f x = 32.768 khz tmc2 tmc1 tmc0 prescaler symbol ssr12 * = 0 ssr12 * = 1 0 0 0 pss 2048t cyc 500 ms 250 ms 1 pss 1024t cyc 250 ms 125 ms 1 0 pss 512t cyc 125 ms 62.5 ms 1 pss 128t cyc 31.25 ms 15.625 ms 1 0 0 pss 32t cyc 7.8125 ms 3.9063 ms 1 pss 8t cyc 1.9531 ms 976.56 s 1 0 pss 4t cyc 976.56 s 488.28 s 1 pss 2t cyc 488.28 s 244.14 s note: * system clock selection register 1 (ssr1) bit 2
426 19.2.2 port mode register a (pmra: $004) pmra is a 4-bit write-only register whose pmra2 bit switches the r0 3 /toc pin function. this section describes the pmra2 bit. see sections 20.2.4 and 21.2.1, ?ort mode register a (pmra)? for details on the pmra3, pmra1, and pmra0 bits. 0 1 bit initial value read/write 3 pmra3 * 0 w 0 pmra0 0 w 2 pmra2 0 w 1 pmra1 0 w r0 3 /toc pin function switch 0 1 r0 1 /si pin function switch 0 1 r0 2 /so pin function switch 0 1 d 3 /buzz pin function switch * r0 3 i/o pin toc output pin r0 1 i/o pin si input pin r0 2 i/o pin so output pin d 3 i/o pin buzz output pin note: * applies to the hd404318, hd404358, hd404358r, hd404339, and hd404369 series. the pmra3 bit is unused in the hd404344r and hd404394 series. bit 2?0 3 /toc pin function switch (pmra2): selects whether the r0 3 /toc pin functions as the r0 3 i/o pin or as the timer c output pin (toc). pmra2 description 0 the r0 3 /toc pin functions as the r0 3 i/o pin. (initial value) 1 the r0 3 /toc pin functions as the toc output pin.
427 19.2.3 timer counter c (tcc) tcc is an 8-bit up counter that is incremented by the input internal clock. bit initial value read/write 7 tcc7 0 6 tcc6 0 5 tcc5 0 4 tcc4 0 3 tcc3 0 0 tcc0 0 2 tcc2 0 1 tcc1 0 counter value the tcc input clock is selected by the tmc tmc2 to tmc0 bits. the value in tcc can be read by reading out the trcl/u pair, and tcc can be written by writing to the twcl/u pair. the timer c interrupt request flag (iftc) is set to 1 when tcc overflows. if the free-running timer function is selected for timer c (tmc3 = 0) at this time, tcc will be cleared to $00 and start to count again. if the reload timer function is selected for timer c (tmc3 = 1), the value in the twcl/u pair will be written to tcc and tcc will start counting from that value. tcc is initialized to $00 on reset and in stop mode.
428 19.2.4 timer write register twcl/u (twcl: $00e, twcu: $00f) the twcl/u pair form an 8-bit write-only register in which twcl is the lower digit and twcu is the upper digit. the twcl/u pair is used to set the initial value of tcc, i.e., to set the reload value in reload operation. bit initial value read/write 3 twcu3 undefined w 0 twcu0 undefined w 2 twcu2 undefined w 1 twcu1 undefined w twcu bit initial value read/write 3 twcl3 0 w 0 twcl0 0 w 2 twcl2 0 w 1 twcl1 0 w twcl data must be written in the order twcl first and then twcu. when twcl is written, the value in tcc does not change. next, when twcu is written, the value in twcu is transferred to the upper digit of tcc and the value in twcl is transferred to the lower digit of tcc. when the twcl/u pair is being written for the second or later time and there is no need to change the twcl reload value, timer c can be initialized by writing only twcu. twcl is initialized to $0 and twcu is undefined on reset and in stop mode.
429 19.2.5 timer read register trcl/u (trcl: $00e, trcu: $00f) the trcl/u pair form an 8-bit read-only register in which trcl and trcu directly read out the lower and upper digits respectively of tcc. that is, the trcl/u pair is used to read out the value in tcc. bit initial value read/write 3 trcu3 undefined r 0 trcu0 undefined r 2 trcu2 undefined r 1 trcu1 undefined r trcu bit initial value read/write 3 trcl3 undefined r 0 trcl0 undefined r 2 trcl2 undefined r 1 trcl1 undefined r trcl data must be read in the order trcu first and then trcl. when trcu is read out, the current value of the upper digit in tcc is returned and at the same time the value of the lower digit is latched into trcl. then, reading out the value in trcl returns that latched value. this means that the exact value of tcc at the point trcu was read is acquired. trcl and trcu are undefined on reset and in stop mode.
430 19.2.6 watchdog on flag (wdon: $020, 1) wdon selects whether timer c functions as a watchdog timer. wdon is allocated in the register flag area and can only by manipulated by the ram bit manipulation instructions. only a value of 1 can be written to this flag. it cannot be cleared to 0 by program instructions. wdon is cleared to 0 on reset and in stop mode. wdon description 0 timer c functions normally. (initial value) 1 timer c functions as a watchdog timer. when timer c overflows the system goes to the reset state and reset exception handling begins.
431 19.3 timer c operation timer c is an 8-bit multifunction timer with the following functions. ? free-running timer ? reload timer ? pwm output ? watchdog timer 19.3.1 free-running timer operation when the tmc tmc3 bit is 0, timer c operates as an 8-bit free-running timer. since tcc is cleared to $00 and the tmc3 bit is cleared to 0 on reset, timer c is incremented continuously as a free-running timer immediately following a reset. the timer c operating clock is selected by tmc tmc2 to tmc0 to be one of eight internal clocks output from pss. on the clock input after the count value in tcc reaches $ff, timer c overflows and iftc is set to 1. if the timer c interrupt mask (imtc) is 0 at this time, a cpu interrupt is generated. see section 4, exception handling , for details on interrupts. on an overflow, the tcc count returns to $00 and timer c begins to count again. 19.3.2 reload timer operation when the tmc tmc3 bit is 1, timer c operates as an 8-bit reload timer. when a reload value is loaded into the twcl/u pair, that value is loaded into tcc and timer c begins to count up from that value. on the clock input after the count value in tcc reaches $ff, timer c overflows, the value in the twcl/u pair is loaded into tcc, and timer c continues counting from that value. this means that the timer c overflow period can be set to be any value in the range 1 to 256 times the input clock period. the operating clock and interrupt operation during reload timer operation are identical to those for free-running timer operation. when a new reload value is loaded into the twcl/u pair that value is immediately written to tcc.
432 19.3.3 pwm output operation when the pmra pmra2 bit is set to 1, the r0 3 /toc pin functions as the toc output pin and timer c generates a pwm output signal. pwm output operation is a function that generates a variable duty pulse output. the output waveform is controlled by the contents of tmc and the twcl/u pair as shown in figure 19-2. t 256 t (256 n) t t (n + 1) tmc3 = 0 (free-running timer) tmc3 = 1 (reload timer) note: t: n: the period of the timer counter c (tcc) input clock. controlled by timer mode register c. the value in the twcl/u pair. when n is 255 the pwm output will be a constant low level signal. figure 19-2 pwm output waveform 19.3.4 watchdog timer operation when wdon is set to 1 timer c functions as a watchdog timer. a watchdog timer is used to detect program runaway. in watchdog timer operation, when timer c overflows the system goes to the reset state and reset exception handling begins. therefore, the application program must reset tcc before its value becomes $ff so that overflows do not occur in normal operation.
433 19.4 interrupts the timer c interrupt is generated on tcc overflow. when tcc overflows, iftc in the interrupt control bit area is set to 1. iftc is never cleared automatically, even if the interrupt is accepted. the interrupt handling routine should clear iftc to 0. the timer c interrupt can be independently enabled or disabled by imtc in the interrupt control bit area. 19.5 usage notes keep the following points in mind when using timer c. ? be sure to write twcl first and then twcu when using the twcl/u pair to initialize tcc. the value in the twcl/u pair is written to tcc at the point that twcu is written. thus if twcl has been set and only the value in the upper digit is to be changed, it is only necessary to write twcu. however, when using pwm output with the reload timer setting (i.e., with the pmra2 bit set to 1 and the tmc3 bit set to 0) in hd404358, hd404358r, and hd404369 series microcomputers, after the twcl/u pair has been written, the contents of the twcl/u pair are written to tcc when tcc overflows. also, if only the upper digit needs to be changed, first write twcl and then write twcu. ? be sure to read trcu first and then trcl when reading the tcc value using the trcl/u pair. the value in the lower digit of tcc is latched into trcl when trcu is read. thus reading trcl returns the value of the tcc lower digit at the point trcu was last read. ? when changing the value of tmc, the new value becomes valid two instructions after the execution of the instruction that wrote tmc. therefore it is necessary for programs that initialize timer c (set the reload value or initialize tcc) by writing to the twcl/u pair to perform this initialization only after the mode changed by tmc has become valid. ? keep the following points in mind when using the timer output as pwm output. in pwm output mode, the duty and the period between the point when the timer write register is updated and the point when the next overflow interrupt is generated differ from the set values as shown in table 19-3. therefore, when using pwm output, only use the output following the overflow interrupt generated after the timer write register was updated. the pwm output following the first overflow will have the duty and period specified by the settings.
434 table 19-3 pwm output immediately following timer write register update t (255 n) t (n + 1) timer write register update (set value: n) interrupt request generated t (255 n) t (n + 1) t (n' + 1) t (255 n) t t (255 n) t t t pwm output m ode f ree-running ( hd404344r, h d404394, h d404318, h d404339 s eries) r eload ( all series) timer write register updated during high level output timer write register updated during low level output timer write register update (set value: n) interrupt request generated timer write register update (set value: n) interrupt request generated timer write register update (set value: n) interrupt request generated
435 section 20 serial interface 20.1 overview the hmcs43xx microcomputers include a built-in single-channel serial interface. this serial interface is a built-in peripheral module that implements serial data communication with other lsis. in particular, this serial interface implements 8-bit clock synchronous communication. 20.1.1 features the serial interface has the following features. ? the clock source can be selected from one of 13 internal clocks: either the system clock or one of the prescaler s (pss*) outputs divided by 2 or 4. alternatively, an external clock can be used as the clock source. ? during idle periods, the transfer output pin can be set to either high or low. ? interrupts can be generated on transfer complete and transfer errors. note: * see section 16, ?rescalers? for details.
436 20.1.2 block diagram figure 20-1 shows the block diagram of the serial interface. system clock 2 8 32 128 512 2048 per 3 so sck si : data bus : clock line : signal line idle control logic i/o control logic prescaler s (pss) selector selector octal counter (oc) clock serial interrupt request flag (ifs) serial data register (srl, sru) transfer control internal data bus serial mode register (smr) port mode register (pmrc) 1/2 1/2 figure 20-1 serial interface block diagram
437 20.1.3 serial interface pins table 20-1 lists the pins used by the serial interface. table 20-1 serial interface pins pin symbol i/o function serial clock i/o sck i/o transfer clock input and output serial reception data input si input serial reception data input serial transmission data output so output serial transmission data output 20.1.4 register configuration table 20-2 lists the registers used by the serial interface. table 20-2 register configuration address register symbol r/w initial value $005 serial mode register smr w $0 $006 serial data register l srl r/w undefined $007 serial data register u sru r/w undefined octal counter oc 000 $004 port mode register a pmra w $0 $025 port mode register c pmrc w 00-0 $00c miscellaneous register mis w $0
438 20.2 register descriptions 20.2.1 serial mode register (smr: $005) smr is a 4-bit write-only register that switches the r port and serial clock pin function, selects the transfer clock, and controls serial interface initialization. the serial interface is initialized by write operations to the smr. clock supply to the serial data register and the octal counter stops and the octal counter is cleared to 0. if a program writes to smr during a data transfer, the data transmission or reception is aborted and the serial interrupt request flag is set to 1. smr is initialized to $0 on reset and in stop mode. smr2 smr1 smr0 sck per /2048 per /512 per /128 per /32 per /8 per /2 per output output output output output output output input bit initial value read/write 3 smr3 0 w 0 smr0 0 w 2 smr2 0 w 1 smr1 0 w 0 1 r0 0 / sck sck
439 bit 3?0 0 / sck pin function switch (smr3): selects whether the r0 0 / sck smr3 description 0 the r0 0 / sck sck sck bits 2 to 0?ransfer clock selection (smr2 to smr0, pmrc0): these bits select the serial interface transfer clock source to be either an external clock, the system clock, or a prescaler s (pss) output. if pss output is selected, the pmrc pmrc0 bit selects whether the pss output will be divided by 2 or 4. pmrc smr transfer clock transfer clock divisor (a pss divisor of transfer clock pmrc0 smr2 smr1 smr0 sck pin source 2 or 4) period 0 0 0 0 output pss ( per /2048) 2 4096 t cyc (initial value) 1 output pss ( per /512) 2 1024 t cyc 1 0 output pss ( per /128) 2 256 t cyc 1 output pss ( per /32) 2 64 t cyc 1 0 0 output pss ( per /8) 2 16 t cyc 1 output pss ( per /2) 2 4 t cyc 1 0 output system clock per t cyc 1 input external clock 1 0 0 0 output pss ( per /2048) 4 8192 t cyc (initial value) 1 output pss ( per /512) 4 2048 t cyc 1 0 output pss ( per /128) 4 512 t cyc 1 output pss ( per /32) 4 128 t cyc 1 0 0 output pss ( per /8) 4 32 t cyc 1 output pss ( per /2) 4 8 t cyc 1 0 output system clock per t cyc 1 input external clock notes: per : the built-in peripheral module operating clock t cyc :system clock period
440 20.2.2 serial data register srl/u (srl: $006, sru: $007) the srl/u pair form an 8-bit read/write register in which sru is the upper digit and srl is the lower digit. data to be transmitted is written to this register and received data is read from this register. data written to the srl/u pair is shifted right (from upper bit positions to lower bit positions) one bit at a time on the falling edge of the transfer clock and the lsb data is output from the so pin. similarly, external data that was transferred lsb first is input from the si pin. this data is acquired by shifting the srl/u pair right one bit at a time. (see figure 20-2.) the srl/u pair can only be read or written after the last data transmission or reception operation has completed. data integrity is not guaranteed if data is read or written during a data transmission or reception operation. the srl/u pair is undefined on reset and in stop mode. sru sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 sru srl shift direction transmission operation msb lsb so pin sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 sru srl shift direction reception operation msb lsb si pin bit initial value read/write 7 sr7 undefined r/w 6 sr6 undefined r/w 5 sr5 undefined r/w 4 sr4 undefined r/w 3 sr3 undefined r/w 0 sr0 undefined r/w 2 sr2 undefined r/w 1 sr1 undefined r/w srl figure 20-2 shift operations during data transmission and reception
441 20.2.3 octal counter (oc) bit initial value read/write 2 oc2 0 1 oc1 0 0 oc0 0 oc is a 3-bit counter that controls the serial interface operating state transitions. when an sts instruction is executed in the sts instruction wait state, oc is initialized to 000, and after the serial interface switches to the transfer state the oc is incremented by 1 on each rising edge of the transfer clock. when either eight transfer clock cycles complete or the transmission or reception is aborted, oc is cleared to 000 and the serial interface switches from the transfer state to the sts instruction wait state or the transfer clock wait state. at the same time ifs is set to 1. oc is initialized to 000 on reset and in stop mode. see section 20.3.4, operating states , for details on the oc and operating state transitions.
442 20.2.4 port mode register a (pmra: $004) pmra is a 4-bit write-only register whose pmra2 to pmra0 bits switch the r0 port pin function. pmra3 switches the function of the d port d 3 /buzz pin. this section describes the pmra1 and pmra0 bits. see sections 19.2.2 and 21.2.1, port mode register a (pmra) , for details on the pmra3 and pmra2 bits. bit initial value read/write 3 pmra3 * 0 w 0 pmra0 0 w 2 pmra2 0 w 1 pmra1 0 w 0 1 r0 3 /toc pin function switch 0 1 r0 1 /si pin function switch 0 1 r0 2 /so pin function switch 0 1 d 3 /buzz pin function switch * r0 3 i/o pin toc output pin r0 1 i/o pin si input pin r0 2 i/o pin so output pin d 3 i/o pin buzz output pin note: * applies to the hd404318, hd404358, hd404358r, hd404339, and hd404369 series. the pmra3 bit is unused in the hd404344r and hd404394 series. bit 1?r0 1 /si pin function switch (pmra1): selects whether the r0 1 /si pin functions as the r0 1 i/o pin or as the serial reception data input pin (si). pmra1 description 0 the r0 1 /si pin functions as the r0 1 i/o pin. (initial value) 1 the r0 1 /si pin functions as the si input pin.
443 bit 0?0 2 /so pin function switch (pmra0): selects whether the r0 2 /so pin functions as the r0 2 i/o pin or as the serial transmission data output pin (so). pmra0 description 0 the r0 2 /so pin functions as the r0 2 i/o pin. (initial value) 1 the r0 2 /so pin functions as the so output pin. 20.2.5 port mode register c (pmrc: $025) pmrc is a 4-bit write-only register that selects the high/low level output state during serial interface idle and sets the divisor for the pss output used as the transfer clock. this register also sets the alarm frequency, do not update or write to this register during serial interface transfers. writing to this register during a transfer can cause the serial interface to operate incorrectly. this section describes the pmrc1 and pmrc0 bits. see section 21.2.2, port mode register c , for details on the pmrc3 and pmrc2 bits. bit initial value read/write 3 pmrc3 * 0 w 0 pmrc0 0 w 2 pmrc2 * 0 w 1 pmrc1 undefined w 0 1 idle time high/low output control 0 1 transfer clock divisor selection alarm output frequency selection * the so pin outputs a low level the so pin outputs a high level pss output divided by 2 pss output divided by 4 note: * applies to the hd404318, hd404358, hd404358r, hd404339, and hd404369 series. the pmrc3 and pmrc2 bits are unused in the hd404344r and hd404394 series.
444 bit 1?dle time high/low output control (pmrc1): controls the state of the so pin during serial interface idle. the so pin changes state when this bit is written. pmrc1 is undefined on reset and in stop mode. pmrc1 description 0 the so pin outputs a low level during idle. (initial value) 1 the so pin outputs a high level during idle. bit 0?ransfer clock divisor selection (pmrc0): selects whether the pss output divided by 2 or 4 is used as the transfer clock. this bit, along with the smr smr2 to smr0 bits, controls the corresponding serial interface transfer clock. pmrc0 is initialized to 0 on reset and in stop mode. pmrc0 description 0 the pss output divided by 2 is used as the transfer clock. (initial value) 1 the pss output divided by 4 is used as the transfer clock.
445 20.2.6 miscellaneous register (mis: $00c) mis is a 4-bit write-only register that controls the port pull-up mos transistor on/off states, controls the r0 2 /so pin output buffer pmos transistor on/off state, sets the interrupt frame period (t) in watch mode and subactive mode, and sets the oscillator stabilization time (t rc ) when low power modes are cleared. mis is initialized to $0 on reset and in stop mode. mis1 mis0 interrupt frame period oscillator stabilization period oscillator circuit conditions 0 1 bit initial value read/write 3 mis3 0 w 0 mis0 * 1 0 w 2 mis2 0 w 1 mis1 * 1 0 w r0 2 /so pin output buffer control 0 1 pull-up mos transistor control pmos transistor active (cmos output) pmos off (nmos open drain output) pull-up mos transistors all off pull-up mos transistors active interrupt frame period and oscillator stabilization time setting * 1 0.12207 (0.24414) ms * 2 7.8125 ms 62.5 ms external clock ceramic oscillator crystal oscillator 0.24414 ms 15.625 ms 125 ms unused 0 1 0 1 0 1 notes: 1. 2. applies to the hd404339 and hd404369 series. the mis1 and mis0 bits are unused in the hd404344r, hd404394, hd404318, hd404358, and hd404358r series. values in parentheses are direct transition times.
446 this section describes the mis2 bit. see sections 11.1.2(4), 12.1.2(4) and 6.2.1, miscellaneous register (mis) , for details on the mis3, mis1, and mis0 bits. bit 2?0 2 /so pin output buffer control (mis2): controls the r0 2 /so pin output buffer pmos transistor on/off state. mis2 description 0 the r0 2 /so pin functions as a cmos output. (initial value) 1 the r0 2 /so pin functions as an nmos open drain output.
447 20.3 operation 20.3.1 operating modes the serial interface performs 8-bit clock synchronization communication. the serial interface has the four operating modes listed in table 20-3. these modes are selected by the smr smr3 bit and the pmra pmra1 and pmra0 bits. table 20-3 serial interface operating modes smr pmra smr3 pmra1 pmra0 operating mode 1 0 0 transfer clock continuous output mode 1 transmission mode 1 0 reception mode 1 transmission/reception mode 20.3.2 serial data format figure 20-3 shows the transfer format for clock synchronous serial data. eight bits of data can be transmitted or received in a single operation. data is transmitted (or received) in an lsb first format. transmitted data is output from one falling edge of the transfer clock to the next falling edge, and received data is input on the rising edge of the transfer clock. transfer clock serial output data serial input data latch timing lsb msb 12345678 figure 20-3 clock synchronous serial data transfer format
448 20.3.3 transfer clock either an internal clock or an external clock can be used as the transfer clock. the internal clock can be set to be either the system clock or one of 12 clocks generated by dividing pss output by 2 or 4, for a total of 13 internal clock options. when an internal clock is used, the sck 20.3.4 operating states serial interface transfer operations are initiated by the sts instruction. when an sts instruction is executed, oc is cleared to 000 and is incremented on each transfer clock rising edge. oc is cleared to 000 and ifs is set to 1 when eight transfer clock cycles have completed or when a transmission or reception is aborted. the serial interface has four operating states as follows. ? ? ? ?
449 figure 20-4 shows the state transition diagram for the serial interface. sts instruction wait state (oc = 000, transfer clock disabled) transfer clock wait state (oc = 000) transfer state (oc (1) external clock mode sts instruction wait state (oc = 000, transfer clock disabled) transfer clock wait state (oc = 000) transfer state (oc (2) internal clock mode transfer clock continuous output state (pmra0, pmra1 = 00) smr write transfer clock numbers enclosed in ovals are referenced in the descriptions in this section. 00 04 01 06 02 03 05 10 18 11 12 15 14 17 13 16 smr write (ifs figure 20-4 serial interface state transition diagram
450 (1) sts instruction wait state: the serial interface enters the sts instruction wait state on a system reset (items 00 and 10 in figure 20-4). the sts instruction wait state is the state in which the serial interface internal state is initialized. in this state, the serial interface will not operate even if a transfer clock is applied. when an sts instruction is executed ( 01 or 11 ) the serial interface switches to the transfer clock wait state. (2) transfer clock wait state: the transfer clock wait state is the period between the execution of an sts instruction and the first transfer clock falling edge. when the transfer clock is applied ( 02 or 12 ) with the serial interface in the transfer clock wait state, the oc counter is incremented, the srl/u pair shift operation starts, and the serial interface switches to the transfer state. however, when transfer clock continuous output mode is selected in internal clock mode, the serial interface does not switch to the transfer state, but rather it switches to the transfer clock continuous output state ( 17 ). if smr is written when the serial interface is in the transfer clock wait state, the serial interface switches to the sts instruction wait state ( 04 or 14 ). (3) transfer state: transfer state is the period between the first transfer clock falling edge and the eighth transfer clock rising edge. if either an sts instruction is executed or eight transfer clock cycles are applied, oc is cleared to 000 and the serial interface state switches. if an sts instruction was executed ( 05 or 15 ), the serial interface switches to the transfer clock wait state. if eight transfer clock cycles were applied, the serial interface transfers to either the transfer clock wait state ( 03 ) if it was in external clock mode, or the sts instruction wait state ( 13 ) if it was in internal clock mode. in internal clock mode, the transfer clock stops after eight clock cycles. if smr is written in the transfer state ( 06 or 16 ), the serial interface is initialized and it switches to the sts instruction wait state. when a transition from transfer state to any other state occurs, oc is cleared to 000 and ifs is set to 1. (4) transfer clock continuous output state (internal clock mode only): transfer clock continuous output state is a state in which no data transfer is performed but the transfer clock is output continuously from the sck
451 20.3.5 transmission and reception operations (1) serial interface initialization: the first step in data transmission or reception operation is initialization of the serial interface by software. this is performed by either resetting the system or writing to the smr register. (2) data transmission a. data transmission procedure in external clock mode figure 20-5 shows the data transmission procedure in external clock mode. 1. setup transmission mode. (pmra1,0 = 01) 2. setup external clock mode. (smr3 to smr0 = 1111) 3. select the idle time so output level. (pmrc1) 4. write the data to be transmitted. (srl/u) 5. execute an sts instruction. 5. ifs = 1 transfer clock input (8 cycles) figure 20-5 data transmission procedure (external clock mode)
452 use the following procedure for data transmission in external clock mode. 1. setup transmission mode by setting the pmra1 and pmra0 bits to 01. 2. setup external clock mode by setting the smr3 to smr0 bits to 1111. the serial interface internal states are initialized when smr is written. 3 select either a low or high level so pin idle output by setting the pmrc1 bit. the so pin will immediately go to either the high or low level when pmrc1 is written. 4 write the data to be transmitted to the srl/u pair. 5 execute an sts instruction. the serial interface will switch from the sts instruction wait state to the transfer clock wait state. when the external clock is applied, the serial interface will switch from the transfer clock wait state to the transfer state on the first transfer clock falling edge, and the serial interface will begin the transmission operation. 6. when eight transfer clock cycles have been input, oc is cleared to 000 and ifs is set to 1. at the same time the serial interface switches from the transfer state to the transfer clock wait state thus completing the transmission operation. after the transfer completes, the so pin holds the value of the msb of the transmitted data. the output value on the so pin can be changed by setting the pmrc1 bit. in the transfer clock wait state, if the transfer clock continues to be input, data transmission operations are repeated. also, the serial interface can be returned to the sts instruction wait state to prepare for the next transmission by performing a dummy write to the smr register. if the smr register is written during a transmission operation, oc is cleared to 0 and ifs is set to 1. at the same time the serial interface switches to the sts instruction wait state and the transmission is aborted. figure 20-6 shows the operation sequence for data transmission in external clock mode.
453 state system reset pmra write smr write pmrc write srl/u pair write sck figure 20-6 serial transmission operation sequence (external clock mode)
454 b. data transmission procedure in internal clock mode figure 20-7 shows the data transmission procedure in internal clock mode. 1. setup transmission mode. (pmra1,0 = 01) 2. setup internal clock mode. (smr3 = 1) (smr2 to smr0 = 000 to 110) (pmrc0 = 0 or 1) 3. select the idle time so output level. (pmrc1) 4. write the data to be transmitted. (srl/u) 5. execute an sts instruction. 6. ifs = 1 transfer clock input (8 cycles) figure 20-7 data transmission procedure (internal clock mode)
455 use the following procedure for data transmission in internal clock mode. 1. setup transmission mode by setting the pmra1 and pmra0 bits to 01. 2. setup internal clock mode by setting the smr2 to smr0 bits. the serial interface internal states are initialized when smr is written. select a divisor of 2 or 4 transfer clock for the prescaler output by setting the pmrc0 bit. 3. select either a low or high level so pin idle output by setting the pmrc1 bit. the so pin will immediately go to either the high or low level when pmrc1 is written. 4. write the data to be transmitted to the srl/u pair. 5. execute an sts instruction. the serial interface will switch from the sts instruction wait state to the transfer clock wait state. when the internal clock is applied, the serial interface will switch from the transfer clock wait state to the transfer state on the first transfer clock falling edge, and the serial interface will begin the transfer operation. 6. when eight transfer clock cycles have been input, oc is cleared to 000 and ifs is set to 1. at the same time the serial interface switches from the sts instruction wait state to the transfer clock wait state thus completing the transfer. after the transfer completes, the so pin holds the value of the msb of the transmitted data. the output value on the so pin can be changed by setting the pmrc1 bit. in internal clock mode, the sck
456 figure 20-8 shows the operation sequence for data transmission in internal clock mode. state system reset pmra write smr write pmrc write srl/u pair write sck figure 20-8 serial transmission operation sequence (internal clock mode)
457 (3) data reception a. data reception procedure in external clock mode figure 20-9 shows the data reception procedure in external clock mode. 2. setup external clock mode. (smr3 to smr0 = 1111) 3. execute an sts instruction. 4. ifs = 1 5. read out the received data. (srl/u) transfer clock input (8 cycles) 1. setup reception mode. (pmra1, 0 = 10) figure 20-9 data reception procedure (external clock mode)
458 use the following procedure for data reception in external clock mode. 1. setup reception mode by setting the pmra1 and pmra0 bits to 10. 2. setup external clock mode by setting the smr3 to smr0 bits to 1111. the serial interface internal states are initialized when smr is written. 3. execute an sts instruction. the serial interface will switch from the sts instruction wait state to the transfer clock wait state. when the external clock is applied, the serial interface will switch from the transfer clock wait state to the transfer state on the first transfer clock falling edge, and the serial interface will begin the reception operation. 4. when eight transfer clock cycles have been input, oc is cleared to 000 and ifs is set to 1. at the same time the serial interface switches from the transfer state to the transfer clock wait state thus completing the reception operation. 5. read out the received data from the srl/u pair. after the completion of data reception with the serial interface in the transfer clock wait state, the reception operation will be repeated if the transfer clock continues to be input. also, the serial interface can be returned to the sts instruction wait state to prepare for the next transmission by performing a dummy write to the smr register. if the smr register is written during a reception operation, oc is cleared to 000 and ifs is set to 1. at the same time the serial interface switches to the sts instruction wait state and the reception is aborted.
459 figure 20-10 shows the operation sequence for data reception in external clock mode. state system reset pmra write smr write sts instruction sck figure 20-10 serial reception operation sequence (external clock mode)
460 b. data reception procedure in internal clock mode figure 20-11 shows the data reception procedure in internal clock mode. 1. setup reception mode. (pmra1,0 = 10) 2. setup internal clock mode. (smr3 = 1) (smr2 to smr0 = 000 to 110) (pmrc0 = 0 or 1) 3. execute an sts instruction. 4. ifs = 1 5. read out the received data. (srl/u) transfer clock input (8 cycles) figure 20-11 data reception procedure (internal clock mode)
461 use the following procedure for data reception in internal clock mode. 1. setup reception mode by setting the pmra1 and pmra0 bits to 10. 2. setup internal clock mode by setting the smr2 to smr0 bits, and select the transfer clock. the serial interface internal states are initialized when smr is written. select a divisor of 2 or 4 for the prescaler output by setting the pmrc0 bit. 3. execute an sts instruction. the serial interface will switch from the sts instruction wait state to the transfer clock wait state. when the internal clock is applied, the serial interface will switch from the transfer clock wait state to the transfer state on the first transfer clock falling edge, and the serial interface will begin the reception operation. 4. when eight transfer clock cycles have been input, oc is cleared to 000 and ifs is set to 1. at the same time the serial interface switches from the transfer state to the sts instruction wait state thus completing the reception operation. 5. read out the received data from the srl/u pair. if the smr register is written during a reception operation, oc is cleared to 000 and ifs is set to 1. at the same time the serial interface switches to the sts instruction wait state and the reception is aborted.
462 figure 20-12 shows the operation sequence for data reception in internal clock mode. ifs cleared by transfer completion handling routine state system reset pmra write smr write sts instruction sck figure 20-12 serial reception operation sequence (internal clock mode)
463 (4) simultaneous transmission and reception a. simultaneous transmission and reception in external clock mode figure 20-13 shows the simultaneous transmission and reception procedure in external clock mode. 1. setup transmission/reception mode. (pmra1, pmra0 = 11) 2. setup external clock mode. (smr3 to smr0 = 1111) 3. select the idle time so output level. (pmrc1) 4 write the data to be transmitted. (srl/u) 5. execute an sts instruction. 6. ifs = 1 7. read out the received data. (srl/u) transfer clock input (8 clock cycles) figure 20-13 simultaneous transmission and reception procedure (external clock mode)
464 use the following procedure for simultaneous transmission and reception in external clock mode. 1. setup transmission/reception mode by setting the pmra1 and pmra0 bits to 11. 2. setup external clock mode by setting the smr3 to smr0 bits to 1111. the serial interface internal states are initialized when smr is written. 3. select either a low or high level so pin idle output by setting the pmrc1 bit. the so pin will immediately go to either the high or low level when pmrc1 is written. 4. write the data to be transmitted to the srl/u pair. 5. execute an sts instruction. the serial interface will switch from the sts instruction wait state to the transfer clock wait state. when the external clock is applied, the serial interface will switch from the transfer clock wait state to the transfer state on the first transfer clock falling edge, and the serial interface will begin the transmission/reception operation. the srl/u pair will be shifted right (in the msb to lsb direction) in synchronization with the transfer clock, received data will be acquired in the msb, and transmitted data will be output from the lsb. 6. when eight transfer clock cycles have been input, oc is cleared to 000 and ifs is set to 1. at the same time the serial interface switches from the transfer state to the transfer clock wait state thus completing the transmission/reception operation. 7. read out the received data from the srl/u pair. after the transfer completes, the so pin holds the value of the msb of the transmitted data. the output value on the so pin can be changed by setting the pmrc1 bit. in the transfer clock wait state, if the transfer clock continues to be input, data transmission/ reception operations are repeated. also, the serial interface can be returned to the sts instruction wait state to prepare for the next transmission/reception by performing a dummy write to the smr register. if the smr register is written during a transmission/reception operation, oc is cleared to 000 and ifs is set to 1. at the same time the serial interface switches to the sts instruction wait state and the transmission/reception operation is aborted. see figures 20-6 and 20-10 for the transmission/reception operation in external clock mode.
465 b. simultaneous transmission and reception in internal clock mode figure 20-14 shows the simultaneous transmission and reception procedure in internal clock mode. 1. setup transmission/reception mode. (pmra1, pmra0 = 11) 2. setup internal clock mode. (smr3 = 1) (smr2 to smr0 = 000 to 110) (pmrc0 = 0 or 1) 3. select the idle time so output level. (pmrc1) 4. write the data to be transmitted. (srl/u) 5. execute an sts instruction. 6. ifs = 1 7. read out the received data. (srl/u) transfer clock input (8 clock cycles) figure 20-14 simultaneous transmission and reception procedure (internal clock mode)
466 use the following procedure for simultaneous transmission and reception in internal clock mode. 1. setup transmission/reception mode by setting the pmra1 and pmra0 bits to 11. 2. setup internal clock mode by setting the smr2 to smr0 bits, and select the transfer clock. the serial interface internal states are initialized when smr is written. select a divisor of 2 or 4 transfer clock for the prescaler output by setting the pmrc0 bit. 3. select either a low or high level so pin idle output by setting the pmrc1 bit. the so pin will immediately go to either the high or low level when pmrc1 is written. 4. write the data to be transmitted to the srl/u pair. 5. execute an sts instruction. the serial interface will switch from the sts instruction wait state to the transfer clock wait state. when the internal clock is applied, the serial interface will switch from the transfer clock wait state to the transfer state on the first transfer clock falling edge, and the serial interface will begin the transmission/reception operation. 6. when eight transfer clock cycles have been input, oc is cleared to 000 and ifs is set to 1. at the same time the serial interface switches from the transfer state to the sts instruction wait state thus completing the transmission/reception operation. 7. read out the received data from the srl/u pair. after the transfer completes, the so pin holds the value of the msb of the transmitted data. the output value on the so pin can be changed by setting the pmrc1 bit. in internal clock mode, the sck
467 (5) transfer clock continuous output operation: figure 20-15 shows the transfer clock continuous output operation procedure. 1. setup transfer clock continuous output operation. (pmra1, pmra0 = 00) 2. setup internal clock mode. (smr3 = 1) (smr2 to smr0 = 000 to 110) (pmrc0 = 0 or 1) 3. execute an sts instruction. 4. a transfer clock identical to the internal clock is output from the sck sck figure 20-15 transfer clock continuous output operation procedure
468 use the following procedure for transfer clock continuous output. 1. setup transfer clock continuous output mode by setting the pmra1 and pmra0 bits to 00. 2. setup internal clock mode by setting the smr2 to smr0 bits, and select the transfer clock. the serial interface internal states are initialized when smr is written. select a divisor of 2 or 4 for the prescaler output by setting the pmrc0 bit. 3. execute an sts instruction. the serial interface will switch from the sts instruction wait state to the transfer clock wait state. 4. when the internal clock is applied, the serial interface will switch from the transfer clock wait state to the transfer state on the first transfer clock falling edge, and a transfer clock identical to the internal clock will be output from the sck 20.3.6 high- or low-level output selection during idle the serial interface allows user software to set the state of the so pin arbitrarily during serial interface idle states, i.e., the sts instruction wait state and the transfer clock wait state. the output level during serial interface idle state is controlled by writing the pmrc pmrc1 bit. in the transfer state, the so pin output level cannot be controlled.
469 20.3.7 transfer clock error detection (external clock mode) the serial interface will operate incorrectly if external noise results in extraneous pulses being added to the transfer clock. the procedure shown in figures 20-16 and 20-17 allows such errors to be detected. transfer completion (ifs figure 20-16 transfer clock error detection flowchart
470 if more than 8 clock cycles are incorrectly applied in the transfer state, oc will be cleared to 000 and ifs set to 1 on the eighth (including noise) clock cycle. at the same time, the serial interface will switch from the transfer state to the transfer clock wait state. however, the serial interface will switch to the transfer state once again on the falling edge of the next clock pulse, which is a correct clock pulse. at the same time, the interrupt processing routine will terminate the transfer, clear ifs to 0, and perform a dummy write to smr. since this dummy write causes the serial interface to switch from the transfer state to the sts instruction wait state, ifs will be set to 1 once again. (see figure 20-4.) therefore, transfer clock errors can be detected by testing the ifs state after performing the smr dummy write. figure 20-17 shows the transfer clock error detection sequence. 12 34567 8 transfer clock wait state transfer clock wait state state sck figure 20-17 transfer clock error detection sequence
471 20.4 interrupts the serial interface interrupt source is generated when the serial interface switches from the transfer state to any other state, i.e., when oc is cleared to 000. ifs is set to 1 when the serial interface interrupt source occurs. ifs is never cleared automatically, even if the interrupt is accepted. the interrupt handling routine should clear ifs to 0. the serial interrupt can be independently enabled or masked with the serial interrupt mask (ims) in the interrupt control bit area. 20.5 usage notes keep the following points in mind when using the serial interface. ? ? sck sck ? ?
472
473 section 21 alarm output (hd404318/hd404358/hd404358r/hd404339 /hd404369 series) 21.1 overview the microcomputers in the hd404318, hd404358, hd404358r, hd404339, and hd404369 series include a built-in alarm output circuit. 21.1.1 features this circuit can output a signal generated by dividing the system clock to the buzz pin for use as an alarm drive signal. the alarm output circuit has the following features. ? the alarm output circuit can output one of four frequencies (these will be 488 hz, 977 hz, 1.95 khz, and 3.91 khz when f osc is 4 mhz) generated by dividing the system clock. the output waveform is a 50% duty square wave.
474 21.1.2 block diagram figure 21-1 shows the block diagram of the alarm output circuit. alarm output control logic port mode register a (pmra) buzz system clock per 256 512 1024 2048 2 port mode register c (pmrc) : data bus : clock line : signal line prescaler s (pss) selector internal data bus figure 21-1 alarm output circuit block diagram
475 21.1.3 pin functions table 21-1 lists the pins used by the alarm output circuit. table 21-1 pin configuration pin symbol i/o function alarm output buzz output alarm signal output 21.1.4 register configuration table 21-2 lists the registers used by the alarm output circuit. table 21-2 register configuration address register symbol r/w initial value $004 port mode register a pmra w $0 $025 port mode register c pmrc w $0
476 21.2 register descriptions 21.2.1 port mode register a (pmra: $004) pmra is a 4-bit write-only register whose pmra3 bit switches the function of the d 3 /buzz pin and whose other bits switch the functions of the r0 port pins. this section describes the pmra3 bit. see the ?ort mode register a (pmra)?items in sections 9 to 12, ?/o ports? for details on the pmra2 to pmra0 bit in the hd404318, hd404358, hd404358r, hd404339, and hd404369 series microcomputers. bit initial value read/write 3 pmra3 0 w 0 pmra0 0 w 2 pmra2 0 w 1 pmra1 0 w 0 1 r0 3 /toc pin function switch 0 1 r0 1 /si pin function switch 0 1 r0 2 /so pin function switch 0 1 d 3 /buzz pin function switch r0 3 i/o pin toc output pin r0 1 i/o pin si input pin r0 2 i/o pin so output pin d 3 i/o pin buzz output pin bit 3? 3 /buzz pin function switch (pmra3): selects whether the d 3 /buzz pin functions as the d 3 i/o pin or as the alarm output pin (buzz). pmra3 description 0 the d 3 /buzz pin functions as the d 3 i/o pin. (initial value) 1 the d 3 /buzz pin functions as the buzz output pin.
477 21.2.2 port mode register c (pmrc: $025) pmrc is a 4-bit write-only register whose pmrc3 and pmrc2 bits select the alarm output frequency. this section describes the pmrc3 and pmrc2 bits. see section 20.2.5, ?ort mode register c (pmrc)?for details on the pmrc1 and pmrc0 bits. pmrc3 pmrc2 alarm frequency 0 1 0 1 0 1 per /2048 per /1024 per /512 per /256 per : built-in peripheral module operating clock bit initial value read/write 3 pmrc3 0 w 0 pmrc0 0 w 2 pmrc2 0 w 1 pmrc1 0 w alarm frequency selection 0 1 idle time high/low output control 0 1 transfer clock divisor selection the so pin outputs a low level the so pin outputs a high level pss output divided by 2 pss output divided by 4
478 bits 3 and 2?larm frequency selection (pmrc3, pmrc2): the pmrc3 and pmrc2 bits are initialized to 0 on reset and in stop mode. pmrc3 pmrc2 description alarm frequency when per = 1 mhz * 0 0 a signal with a frequency of per /2048 is output. 488 hz 1 a signal with a frequency of per /1024 is output. 977 hz 1 0 a signal with a frequency of per /512 is output. 1.95 khz 1 a signal with a frequency of per /256 is output. 3.91 khz note: * hd404318/hd404358/hd404358r series: per = f osc /4 hd404339/hd404369 series: per = f osc /4, f osc /8, f osc /16, or f osc /32 21.3 operation the alarm output circuit selects one of four frequencies generated by using prescaler s (pss) to divide the system clock. figure 21-2 shows the output waveform. the output is a 50% duty square wave. 0 v v cc when f osc = 4 mhz, per = f osc /4 and the per /512 setting is selected. (frequency: 1.95 khz) (256 s) (256 s) figure 21-2 alarm output waveform example
479 section 22 rom 22.1 overview table 22-1 lists the built-in rom provided by the hmcs43xx family microcomputers. table 22-1 built-in rom hd404344r/hd404394 series product number hd404344r series hd404394 series capacity rom type hd404341rs hd404391s 1,024 words mask rom hd404341rfp hd404391fp hd404341rft hd404391ft hd40c4341rs hd40c4341rfp hd40c4341rft hd404342rs hd404392s 2,048 words hd404342rfp hd404392fp hd404342rft hd404392ft hd40c4342rs hd40c4342rfp hd40c4342rft hd404344rs hd404394s 4,096 words hd404344rfp hd404394fp HD404344RFT hd404394ft hd40c4344rs hd40c4344rfp hd40c4344rft hd4074344s hd4074394s 4,096 words ztat * hd4074344fp hd4074394fp hd4074344ft hd4074394ft note: * ztat is a registered trademark of hitachi, ltd.
480 table 22-1 built-in rom (cont) hd404318 series product number capacity rom type hd404314s 4,096 words mask rom hd404314h hd404316s 6,144 words hd404316h hd404318s 8,192 words hd404318h hd4074318s 8,192 words ztat * hd4074318h note: * ztat is a registered trademark of hitachi, ltd. hd404358 series product number capacity rom type hd404354s/hd40a4354s 4,096 words mask rom hd404354h/hd40a4354h hd404356s/hd40a4356s 6,144 words hd404356h/hd40a4356h hd404358s/hd40a4358s 8,192 words hd404358h/hd40a4358h hd407a4359s 16,384 words ztat * hd407a4359h note: * ztat is a registered trademark of hitachi, ltd.
481 table 22-1 built-in rom (cont) hd404358r series product number capacity rom type hd404354rs/hd40a4354rs/hd40c4354rs 4,096 words mask rom hd404354rh/hd40a4354rh/hd40c4354rh hd404356rs/hd40a4356rs/hd40c4356rs 6,144 words hd404356rh/hd40a4356rh/hd40c4356rh hd404358rs/hd40a4358rs/hd40c4358rs 8,192 words hd404358rh/hd40a4358rh/hd40c4358rh hd407a4359rs/hd407c4359rs 16,384 words ztat * hd407a4359rh/hd407c4359rh note: * ztat is a registered trademark of hitachi, ltd. hd404339 series product number capacity rom type hd404334s 4,096 words mask rom hd404334fs hd404336s 6,144 words hd404336fs hd404338s 8,192 words hd404338fs hd4043312s 12,288 words hd4043312fs hd404339s 16,384 words hd404339fs hd4074339s 16,384 words ztat * hd4074339fs note: * ztat is a registered trademark of hitachi, ltd.
482 table 22-1 built-in rom (cont) hd404369 series product number capacity rom type hd404364s/hd40a4364s 4,096 words mask rom hd404364f/hd40a4364f hd404368s/hd40a4368s 8,192 words hd404368f/hd40a4368f hd4043612s/hd40a43612s 12,288 words hd4043612f/hd40a43612f hd404369s/hd40a4369s 16,384 words hd404369f/hd40a4369f hd407a4369s 16,384 words ztat * hd407a4369f note: * ztat is a registered trademark of hitachi, ltd.
483 22.2 prom mode 22.2.1 prom mode the hd4074344, hd4074394, hd4074318, hd407a4359, hd407a4359r, hd407c4359r, hd4074339, and hd407a4369 microcomputers support prom mode. when these microcomputers are set to prom mode, their microcomputer functions are stopped and they operate identically to the hn27c256 and hn27256 prom products, thus allowing the internal prom to be programmed. table 22-2 shows the method for switching these products to prom mode. table 22-2 prom mode setup methods hd4074344/hd4074394 pin setting level mode pin m 0 (r3 1 /an 1 ) low level reset pin reset hd4074318/hd4074339 pin setting level mode pin m 0 (d 0 / int 0 ) high level mode pin m 1 (d 1 / int 1 ) reset pin reset low level hd407a4359/hd407a4359r/hd407c4359r/hd407a4369 pin setting level mode pin m 0 (r4 1 /an 5 ) low level mode pin m 1 (r4 2 /an 6 ) reset pin reset
484 22.2.2 socket adapter pin correspondence and memory map the on-chip prom is programmed by using a socket adapter corresponding to the package type as shown in table 22-3. this converts the microcomputer to a 28-pin package thus allowing the use of a general-purpose prom writer. figures 22-1 to 22-5 show the socket adapter pin correspondences. since the hmcs400 series instructions are 10-bit instructions, these products include an on-chip conversion circuit that allows a general-purpose prom writer to be used. this circuit divides each instruction into upper and lower 5-bit segments and allows each segment to be programmed as a different address. since the hd4074344 and hd4074394 have 4,096 words of prom on chip, the prom writer should be set for an 8-kbyte address space ($0000 to $1fff). since the hd4074318 has 8,192 words of prom on chip, the prom writer should be set for a 16-kbyte address space ($0000 to $3fff). and since the hd407a4359, hd407a4359r, hd407c4359r, hd4074339, and hd407a4369 have 16,384 words of prom on chip, the prom writer should be set for a 32- kbyte address space ($0000 to $7fff). figures 22-6 to 22-8 show the memory maps when these microcomputers are in prom mode. table 22-3 socket adapters product number package socket adapter product number hd4074344/hd4074394 dp-28s hs4344ess01h fp-28da hs4344esp01h fp-30d hs4344esf01h hd4074318 dp-42s hs4318ess01h fp-44a hs4318esh01h hd407a4359/hd407a4359r/ dp-42s hs4359ess01h hd407c4359r fp-44a hs4359esh01h hd4074339 dp-64s hs4339ess01h fp-64b hs4339esf01h hd407a4369 dp-64s hs4369ess01h fp-64b hs4369esf01h
485 figure 22-1 shows the hd4074344 and hd4074394 socket adapter pin correspondence. 17 15 19 20 21 22 23 24 25 26 28 1 2 3 4 5 6 7 8 27 9 14 16 13 18 11 fp-30d 19 16 21 22 23 24 25 26 27 28 30 1 2 3 4 5 6 7 8 29 9 15 18 14 20 11 pin v pp o 0 o 1 o 2 o 3 o 4 a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 10 a 11 a 12 ce oe v cc gnd hn27c256, hn27256 1 11 12 13 15 16 10 9 8 7 6 5 4 3 25 24 21 23 2 20 22 28 14 hd4074344/hd4074349 hn27c256, hn27256 (pin 28) symbols v pp : o 0 to o 4 : a 0 to a 12 : oe : ce : notes: unused pin test r3 3 /an 3 r0 0 / sck r0 1 /si r0 2 /so r0 3 /toc d 0 /int 0 /evnb d 1 d 2 d 3 d 5 r1 0 r1 1 r1 2 r1 3 r2 0 r2 1 r2 2 r2 3 d 4 / stopc osc 1 r3 2 /an 2 (x on ) v cc r3 1 /an 1 (m 0 ) reset gnd dp-28s, fp-28da pin programming power supply data i/o address input output enable chip enable 1. the prom adapter unused address pins (a 13 and a 14 ) and unused data pins (o 5 to o 7 ) are connected inside the socket adapter with the circuit shown below. 2. pins not specifically mentioned in the figure should be left open. figure 22-1 hd4074344 and hd4074394 socket adapter pin correspondence
486 figure 22-2 shows the hd4074318 socket adapter pin correspondence. dp-42s 6 12 13 14 15 16 17 18 19 39 24 25 27 28 35 36 37 38 29 40 41 42 33 34 31 32 22 23 2 3 8 30 21 20 7 10 11 fp-44a 1 7 8 9 10 11 12 13 14 35 19 20 23 24 31 32 33 34 25 36 37 38 29 30 27 28 17 18 40 41 3 26 16 15 2 5 6 test r3 0 /an 0 r3 1 /an 1 r3 2 /an 2 r3 3 /an 3 r4 0 /an 4 r4 1 /an 5 r4 2 /an 6 r4 3 /an 7 r2 0 d 2 /evnb d 3 /buzz d 5 d 6 r1 0 r1 1 r1 2 r1 3 d 7 r2 1 r2 2 r2 3 r8 2 r8 3 r8 0 r8 1 d 0 /int 0 (m 0 ) d 1 /int 1 (m 1 ) r0 0 / sck r0 1 /si osc 1 d 8 v cc av cc reset gnd av ss pin v pp o 0 o 1 o 2 o 3 o 4 o 5 o 6 o 7 a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 10 a 11 a 12 a 13 a 14 ce oe v cc gnd hn27c256, hn27256 1 11 12 13 15 16 17 18 19 10 9 8 7 6 5 4 3 25 24 21 23 2 26 27 20 22 28 14 hd4074318 hn27c256, hn27256 (pin 28) note: pins not specifically mentioned in the figure should be left open. pin symbols v pp : o 0 to o 7 : a 0 to a 14 : oe : ce : programming power supply data i/o address input output enable chip enable figure 22-2 hd4074318 socket adapter pin correspondence
487 figure 22-3 shows the hd407a4359, hd407a4359r, and hd407c4359r socket adapter pin correspondence. dp-42s 6 1 12 4 13 5 14 22 15 23 16 39 24 25 27 28 35 36 37 38 29 40 41 42 33 34 31 32 2 3 8 30 21 20 17 18 7 10 11 fp-44a 1 39 7 42 8 43 9 17 10 18 11 35 19 20 23 24 31 32 33 34 25 36 37 38 29 30 27 28 40 41 3 26 16 15 12 13 2 5 6 test ra 1 r3 0 /an 0 r0 2 /so r3 1 /an 1 r0 3 /toc r3 2 /an 2 d 0 /int 0 r3 3 /an 3 d 1 /int 1 r4 0 /an 4 r2 0 d 2 /evnb d 3 /buzz d 5 d 6 r1 0 r1 1 r1 2 r1 3 d 7 r2 1 r2 2 r2 3 r8 2 r8 3 r8 0 r8 1 r0 0 /sck r0 1 /si osc 1 d 8 v cc av cc r4 1 /an 5 (m 0 ) r4 2 /an 6 (m 1 ) reset gnd av ss pin v pp o 0 o 1 o 2 o 3 o 4 a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 10 a 11 a 12 a 13 a 14 ce oe v cc gnd hn27c256, hn27256 1 11 12 13 15 16 10 9 8 7 6 5 4 3 25 24 21 23 2 26 27 20 22 28 14 hd407a4359/hd407a4359r, and hd407c4359r hn27c256, hn27256 (pin 28) unused pin pin symbols v pp : o 0 to o 4 : a 0 to a 14 : oe: ce: programming power supply data i/o address input output enable chip enable notes: 1. the prom adapter unused data pins (o 5 to o 7 ) are connected inside the socket adapter with the circuit shown below. 2. pins not specifically mentioned in the figure should be left open. figure 22-3 hd407a4359, hd407a4359r, and hd407c4359r socket adapter pin correspondence
488 figure 22-4 shows the hd4074339 socket adapter pin correspondence. dp-64s 12 5 20 4 21 3 22 2 23 1 24 25 26 27 60 36 37 39 40 56 57 58 59 41 61 62 63 50 51 48 49 34 35 8 9 14 42 33 32 13 16 17 19 fp-64b 6 63 14 62 15 61 16 60 17 59 18 19 20 21 54 30 31 33 34 50 51 52 53 35 55 56 57 44 45 42 43 28 29 2 3 8 36 27 26 7 10 11 13 test r7 0 r3 0 /an 0 r6 3 r3 1 /an 1 r6 2 r3 2 /an 2 r6 1 r3 3 /an 3 r6 0 r4 0 /an 4 r4 1 /an 5 r4 2 /an 6 r4 3 /an 7 r2 0 d 2 /evnb d 3 /buzz d 5 d 6 r1 0 r1 1 r1 2 r1 3 d 7 r2 1 r2 2 r2 3 r8 2 r8 3 r8 0 r8 1 d 0 /int 0 (m 0 ) d 1 /int 1 (m 1 ) r0 0 /sck r0 1 /si osc 1 d 8 v cc av cc reset gnd x1 av ss pin v pp o 0 o 1 o 2 o 3 o 4 o 5 o 6 o 7 a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 10 a 11 a 12 a 13 a 14 ce oe v cc gnd hn27c256, hn27256 1 11 12 13 15 16 17 18 19 10 9 8 7 6 5 4 3 25 24 21 23 2 26 27 20 22 28 14 hd4074339 hn27c256, hn27256 (pin 28) symbols v pp : o 0 to o 7 : a 0 to a 14 : oe : ce : programming power supply data i/o address input output enable chip enable pin note: pins not specifically mentioned in the figure should be left open. figure 22-4 hd4074339 socket adapter pin correspondence
489 figure 22-5 shows the hd407a4369 socket adapter pin correspondence. dp-64s 12 64 20 10 21 11 22 34 23 35 24 60 36 37 39 40 56 57 58 59 41 61 62 63 50 51 48 49 8 9 14 42 33 32 25 26 13 17 16 19 fp-64b 6 58 14 4 15 5 16 28 17 29 18 54 30 31 33 34 50 51 52 53 35 55 56 57 44 45 42 43 2 3 8 36 27 26 19 20 7 11 10 13 test ra 1 r3 0 /an 0 r0 2 /so r3 1 /an 1 r0 3 /toc r3 2 /an 2 d 0 /int 0 r3 3 /an 3 d 1 /int 1 r4 0 /an 4 r2 0 d 2 /evnb d 3 /buzz d 5 d 6 r1 0 r1 1 r1 2 r1 3 d 7 r2 1 r2 2 r2 3 r8 2 r8 3 r8 0 r8 1 r0 0 / sck r0 1 /si osc 1 d 8 v cc av cc r4 1 /an 5 (m 0 ) r4 2 /an 6 (m 1 ) reset x1 gnd av ss pin v pp o 0 o 1 o 2 o 3 o 4 a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 10 a 11 a 12 a 13 a 14 ce oe v cc gnd hn27c256, hn27256 1 11 12 13 15 16 10 9 8 7 6 5 4 3 25 24 21 23 2 26 27 20 22 28 14 hd407a4369 hn27c256, hn27256 (pin 28) unused pin pin symbols v pp : o 0 to o 4 : a 0 to a 14 : oe : ce : programming power supply data i/o address input output enable chip enable notes: 1. the prom adapter unused data pins (o 5 to o 7 ) are connected inside the socket adapter with the circuit shown below. 2. pins not specifically mentioned in the figure should be left open. figure 22-5 hd407a4369 socket adapter pin correspondence
490 figure 22-6 shows the prom mode memory map for the hd4074344 and the hd4074394. bit address bit address $0000 $0001 $001f $0020 $007f $0080 $1fff $0000 $000f $0010 $003f $0040 $0fff 79 hd4074344 and hd4074394 address map vector address area (32 bytes) zero page subroutine area (128 bytes) pattern area/program area (8,192 bytes) vector address area (16 words) zero page subroutine area (64 words) pattern area/program area (4,096 words) upper three bits not used (set to 111). byte: word: ro 9 6 1 1 5 1 1 4 ro 4 ro 9 3 ro 3 ro 8 2 ro 2 ro 7 1 ro 1 ro 6 0 ro 0 ro 5 1 1 6543210 87 ro 6 ro 5 ro 4 ro 3 ro 2 ro 1 ro 0 ro 8 ro 7 hn27c256 or hn27256 address map 8 bits 10 bits figure 22-6 hd4074344 and hd4074394 prom mode memory map
491 figure 22-7 shows the prom mode memory map for the hd4074318. bit address bit address $0000 $0001 $001f $0020 $007f $0080 $1fff $2000 $3fff $0000 $000f $0010 $003f $0040 $0fff $1000 $1fff 79 hd4074318 address map vector address area (32 bytes) zero page subroutine area (128 bytes) pattern area (8,192 bytes) program area (32,768 bytes) vector address area (16 words) zero page subroutine area (64 words) pattern area (4,096 words) program area (8,192 words) upper three bits not used (set to 111). byte: word: ro 9 6 1 1 5 1 1 4 ro 4 ro 9 3 ro 3 ro 8 2 ro 2 ro 7 1 ro 1 ro 6 0 ro 0 ro 5 1 1 6543210 87 ro 6 ro 5 ro 4 ro 3 ro 2 ro 1 ro 0 ro 8 ro 7 hn27c256 or hn27256 address map 8 bits 10 bits figure 22-7 hd4074318 prom mode memory map
492 figure 22-8 shows the prom mode memory map for the hd407a4359, hd407a4359r, hd407c4359r, hd4074339, and hd407a4369. bit address bit address $0000 $0001 $001f $0020 $007f $0080 $1fff $2000 $7fff $0000 $000f $0010 $003f $0040 $0fff $1000 $3fff 79 hd407a4359, hd407a4359r, hd407c4359r, hd4074339, and hd407a4369 address map vector address area (32 bytes) zero page subroutine area (128 bytes) pattern area (8,192 bytes) program area (32,768 bytes) vector address area (16 words) zero page subroutine area (64 words) pattern area (4,096 words) program area (16,192 words) upper three bits not used (set to 111). byte: word: ro 9 6 1 1 5 1 1 4 ro 4 ro 9 3 ro 3 ro 8 2 ro 2 ro 7 1 ro 1 ro 6 0 ro 0 ro 5 1 1 6543210 87 ro 6 ro 5 ro 4 ro 3 ro 2 ro 1 ro 0 ro 8 ro 7 hn27c256 or hn27256 address map 8 bits 10 bits figure 22-8 hd407a4359, hd407a4359r, hd407c4359r, hd4074339, and hd407a4369 prom mode memory map
493 22.3 programming table 22-4 lists the settings used to select write, verify, and other modes when prom programming. table 22-4 write mode selection in prom mode pin mode ce oe o 0 to o 7 (o 0 to o 4 ) * 1 a 0 to a 14 (a 0 to a 12 ) * 2 write l h data input address input verify h l data output address input programming disable h h high impedance address input symbols l: low level h: high level notes: 1. o 0 to o 7 : applies to the hd4074318 and hd4074339. o 0 to o 4 : applies to the hd4074344, hd4074394, hd407a4359, hd407a4359r, hd407c4359r, and hd407a4369. 2. a 0 to a 14 : applies to the hd4074318, hd407a4359, hd407a4359r, hd407c4359r, hd4074339, and hd407a4369. a 0 to a 12 : applies to the hd4074344 and hd4074394. note that write and read operations in prom mode have the same specifications as the hn27c256 and hn27256 standard eprom products. 22.3.1 write/verify write/verify mode provides efficient high-speed programming. with this method, high-speed writing can be performed without electrically stressing the device and without reducing data reliability. data in unused regions is set to $ff. figure 22-9 shows the basic flowchart for this high-speed programming technique. tables 22-5 and 22-6 list the electrical characteristics during programming and figure 22-10 shows the timing.
494 figure 22-9 shows the flowchart for high-speed programming. start setup write/verify mode v cc = 6.0 0.25 v, v pp = 12.5 0.3 v address = 0 n = 0 n + 1 n write t pw = 1 ms 5% verify last address? end n < 25 reject write t opw = 3n ms setup read mode v cc = 5.0 0.5 v, v pp = v cc 0.6 v no go no yes yes yes go no no address + 1 address all addresses read? figure 22-9 flowchart for high-speed programming
495 table 22-5 lists the dc characteristics and table 22-6 lists the ac characteristics. table 22-5 dc characteristics v cc = 6.0 v ?.25 v, v pp = 12.5 v ?.3 v, v ss = 0 v, t a = 25? ??, unless specified otherwise. item symbol min typ max unit test conditions input high level voltage o 0 to o 7 (o 0 to o 4 ) * 1 , a 0 to a 14 (a 0 to a 12 ) * 2 , oe , ce v ih 2.2 v cc + 0.3 v input low level voltage o 0 to o 7 (o 0 to o 4 ) * 1 , a 0 to a 14 (a 0 to a 12 ) * 2 , oe , ce v il 0.3 0.8 v output high level voltage o 0 to o 7 (o 0 to o 4 ) * 1 v oh 2.4 vi oh = 200 a output low level voltage o 0 to o 7 (o 0 to o 4 ) * 1 v ol 0.4 v i ol = 1.6 ma input leakage current o 0 to o 7 (o 0 to o 4 ) * 1 , a 0 to a 14 (a 0 to a 12 ) * 2 , oe , ce | i il | 2av in = 5.25 v/0.5 v v cc current i cc 30 ma v pp current i pp 40 ma notes: 1. o 0 to o 7 : applies to the hd4074318 and hd4074339. o 0 to o 4 : applies to the hd4074344, hd4074394, hd407a4359, hd407a4359r, hd407c4359r, and hd407a4369. 2. a 0 to a 14 : applies to the hd4074318, hd407a4359, hd407a4359r, hd407c4359r, hd4074339, and hd407a4369. a 0 to a 12 : applies to the hd4074344 and hd4074394.
496 table 22-6 ac characteristics v cc = 6.0 v ?.25 v, v pp = 12.5 v ?.3 v, t a = 25? ??, unless specified otherwise. item symbol min typ max unit test conditions address setup time t as 2 s figure 22-10 * oe setup time t oes 2 s data setup time t ds 2 s address hold time t ah 0 s data hold time t dh 2 s data output disable time t df 130 ns v pp setup time t vps 2 s program pulse width t pw 0.95 1.0 1.05 ms ce pulse width during overprogramming t opw 2.85 78.75 ms v cc setup time t vcs 2 s data output delay time t oe 0 500 ns note: * input pulse level: 0.8 to 2.2 v input rise/fall times 20 ns timing reference levels: input: 1.0 v, 2.0 v output: 0.8 v, 2.0 v
497 figure 22-10 shows the prom write/verify timing. write verify input data output data t as t ah t ds t vps t vcs t dh t df t pw t opw t oes t oe address data v pp ce oe v pp v cc v cc v cc gnd figure 22-10 prom write/verify timing
498 22.3.2 prom programming notes ? use the stipulated voltages and times for prom programming. the programming voltage (v pp ) in prom mode is 12.5 v. the product may be permanently damaged if a voltage in excess of the rated voltage is applied. in particular, be especially careful of prom writer overshoot. when the prom writer is setup for either the hitachi hn27256 or hn27c256, or the intel specifications, v pp will be 12.5 v. ? make sure that the prom writer, the socket adapter, and microcomputer chip are all aligned correctly, i.e., that their respective index marks match. incorrect alignment can result in product damage due to overcurrents. before writing, reconfirm that the product is correctly connected to the prom writer. ? do not touch the socket adapter or microcomputer during programming. this could cause contact faults that could result in programming failures.
499 22.3.3 post-programming reliability after programming, screening products by baking them at 150? can be effective at improving data retention characteristics. baking is one type of screening and allows early data retention failures in prom memory cells to be caught in a short period. figure 22-11 shows the flowchart for the recommended screening procedure. write the program and verify the values written high temperature bake without power program read check v cc = 4.5 v or 5.5 v 150 c 10 c, 48 h +8 h * 0 h note: * the bake time is measured from the time the furnace internal temperature reaches 150 c. mounting figure 22-11 recommended screening procedure
500 22.4 notes on ordering rom there are products in which data areas drawn on the mask and the rom data actually used differ. write 1s to the addresses in unused areas in the rom data. this applies both when ordering using eproms and when ordering by sending data. figure 22-12 shows the rom data configurations for the corresponding products. vector address zero page subroutine (64 words) program & pattern (4,096 words) $0000 $000f $0010 $003f $0040 $0fff $1000 $1fff versions with 4 kwords of rom: hd404314, hd404354, hd404354r, hd40a4354r, hd40c4354r, hd404334, hd40a4354 vector address zero page subroutine (64 words) program & pattern (6,144 words) $0000 $000f $0010 $003f $0040 $1fff versions with 6 kwords of rom: hd404316, hd404356, hd404356r, hd40a4356r, hd40c4356r, hd404336, hd40a4356 $17ff $1800 vector address zero page subroutine (64 words) $0000 $000f $0010 $003f $0040 $03ff $0400 versions with 1 kword of rom: hd404341r, hd404391 $0fff vector address zero page subroutine (64 words) $0000 $000f $0010 $003f $0040 versions with 2 kwords of rom: hd404342r, hd404392 $0fff $07ff $0800 program & pattern (1,024 words) program & pattern (2,048 words) products that require 4 kwords of data when ordering products that require 8 kwords of data when ordering unused unused unused unused figure 22-12 rom data configurations (1)
501 products that require 16 kwords of data when ordering vector address zero page subroutine (64 words) $0000 $000f $0010 $003f $0040 versions with 4 kwords of rom: hd404364, hd40a4364 $3fff program & pattern (8,192 words) vector address zero page subroutine (64 words) $0000 $000f $0010 $003f $0040 $1fff $2000 versions with 8 kwords of rom: hd404368, hd40a4368 $3fff vector address program & pattern (12,228 words) zero page subroutine (64 words) $0000 $000f $0010 $003f $0040 $2fff $3000 versions with 12 kwords of rom: hd4043312, hd4043612, hd40a43612 unused $3fff program & pattern (4,096 words) $0fff $1000 unused unused figure 22-12 rom data configurations (2)
502
503 section 23 ram 23.1 overview 23.1.1 features the hmcs43xx family ram consists of three areas: the memory register area, the data area, and the stack area. the sizes of the memory register and stack areas are identical in all products in the hmcs43xx family, but the size of the data areas differs between products. registers that control the system, interrupts, and the built-in peripheral modules are allocated in the ram address space. this section describes the ram areas other than the area used for these control registers. the ram areas have the following features. ? memory register area (locations $040 to $04f) this is a 16 digit area that consists of the 16 memory registers (mr(0) to mr(15)). in addition to the usual ram access instructions, the register to register instructions (lamr and xmra) can be used to access this area. ? data area hd404344r/hd404394 series the data area consists of 176 digits of memory at ram addresses $050 to $0ff. hd404318 series the data area consists of 304 digits of memory at ram addresses $050 to $17f. hd404358 series the data area consists of 304 digits of memory at ram addresses $050 to $17f in products with 8,192 or fewer words of rom, i.e., the hd404354, hd404356, hd404358, hd40a4354, hd40a4356, and hd40a4358. the data area consists of 432 digits of memory at ram addresses $050 to $1ff in products with 12,288 or more words of rom, i.e., the hd404359, hd40a4359, and hd407a4359. hd404358r series the data area consists of 432 digits of memory at ram addresses $050 to $1ff.
504 hd404339 series the data area consists of 432 digits of memory at ram addresses $050 to $1ff. hd404369 series the data area consists of 432 digits of memory at ram addresses $050 to $1ff. ? stack area (locations $3c0 to $3ff) this area is used to save the program counter (pc), status (st), and carry (ca) during subroutine calls and interrupt handling. locations not used as stack area can be used as data area.
505 23.1.2 ram memory map figure 23-1 shows the ram memory map. ram mapped register area unused 64 digits 176 digits * 1 304 digits * 2 432 digits * 3 ram address $000 $040 $050 $100 $180 $200 $3c0 $3ff : 16 digits memory register area data area stack area areas in which ram is physically present notes: 1. 2. 3. applies to the hd404344r and hd404394 series. applies to all products in the hd404318 series and to the hd404354, hd404356, hd404358, hd40a4354, hd40a4356, and hd40a4358 in the hd404358 series. applies to all products in the hd404339 series, to the hd407a4359 in the hd404358 series, and to all products in the hd404358r series, and to all products in the hd404369 series. figure 23-1 ram memory map
506 23.2 ram enable flag (rame: $021, 3) the rame flag shown in table 23-1 is a flag that indicates that the contents of ram prior to the mode transition that cleared stop mode were maintained. table 23-1 ram enable flag address flag symbol r/w initial value $021, 3 ram enable flag rame r/w * 0 note: * rame is allocated in the register flag area and can only be manipulated with the ram bit manipulation instructions. only a value of 0 can be written to this flag, thus clearing it. rame is set to 1 when stop mode is cleared by a stopc input. after clearing stop mode, a user program can be sure that the contents of ram just before stop mode was entered were maintained by reading this flag and confirming that it was set to 1. see the ?am enable flag?items, sections 5.2.2 and 6.2.7, for more details on the rame flag. 23.3 usage notes keep the following points in mind when using ram. ? the contents of ram are not guaranteed when power is first applied. ? the contents of ram are not guaranteed after a reset. ? after power is turned on the values stored in the memory register area, data area, and stack area are undefined, regardless of whether a reset is input or not. it is essential to initialize these areas before use.
507 section 24 application examples 24.1 using the a/d converter this section describes the use of the a/d converter. feel free to take advantage of the techniques presented here in user application systems. this section has the following structure: functions and application functions application example system specifications register settings flowcharts program example figure 24-1 application example organization this application example uses an hd404339 series microcomputer. while the techniques shown here apply equally to the hd404344r, hd404318, hd404358, hd404358r, and hd404369 series microcomputers, the details of the register settings, clock settings, and pin arrangements would differ somewhat. see section 15, ?/d converter? for details. note: although the operation of the program examples included in this section has been verified, their operation should be re-verified if they are used in an actual user system.
508 (1) functions and application functions ? this application measures four analog input channels with an 8-bit resolution. ? this system can be used for various types of sensor detection applications (e.g., temperature or humidity) and key scan inputs. (2) application example (use of the 8-bit 4-channel a/d converter) system specifications ? the system stores the results of the 4-channel a/d conversions in ram. figure 24-2 shows the mapping of the ram where the results are stored. $1 ch1 $2 ch2 $0 ch0 $3 (lower digit) ch3 (upper digit) y x $a $b figure 24-2 ram mapping ? the completion of an a/d converter operation is detected by reading the a/d converter interrupt request flag. this application does not use interrupts.
509 register settings ? a/d mode register 1 (amr1: $019) ? a/d mode register 2 (amr2: $01a) ? a/d channel register (acr: $016) the analog input pins and the a/d conversion time are specified by these three registers. ? a/d start flag (adsf: $020, 2) setting this flag starts an a/d conversion. 1: a/d conversion start 0: a/d conversion complete ? a/d interrupt request flag (ifad: $003, 0) indicates that an a/d conversion has completed. 1: a/d conversion complete 0: a/d conversion in progress ? iad off flag (iaof: $021, 2) controls the current in the a/d converter resistor ladder. ? a/d data register (adrl: $017, adru: $018) holds the result of an 8-bit a/d conversion. adrl: holds the lower 4 bits of an 8-bit a/d conversion. adru: holds the upper 4 bits of an 8-bit a/d conversion.
510 flowcharts a. main routine admn have all four channels been converted? yes a/d converter initial settings no a/d converter start a/d conversion process the conversion results
511 b. a/d converter initial settings adinit set the a/d mode registers 1 and 2 and the a/d channel register. ? set the conversion time to 67t cyc . ? set the r3 0 /an 0 to r3 3 /an 3 pins to be analog input pins. ? select the an 3 pin. clear the a/d converter interrupt request flag clear the ram area to be used. 1. 2. 3. rtn
512 c. a/d conversion rtn adscn a/d conversion enabled? first a/d conversion? initialize ram clear the a/d converter interrupt request flag a/d conversion complete? select the next channel update the pointer to the ram that holds the result store the result of the conversion in ram have all four channels completed? set the flag that indicates that all four channels were converted. yes no no yes yes no no yes select the an 3 pin start the a/d converter start the a/d converter
513 sample program * symbol definitions rsp equ 1,$000 * stack pointer reset ifad equ 0,$003 * a/d interrupt request flag adsf equ 2,$020 * a/d start flag iaof equ 2,$021 * iad off flag amr1 equ $019 * a/d mode register 1 amr2 equ $01a * a/d mode register 2 acr equ $016 * a/d channel register adrl equ $017 * a/d data register (lower digit) adru equ $018 * a/d data register (upper digit) * ram mapping adchno equ $0a4 * a/d conversion result storage address pointer adflag equ $0b4 * flag ram adstf equ 0,adflag * a/d start flag ad1stf equ 1,adflag * a/d first flag adendf equ 2,adflag * a/d end flag * interrupt vector settings org $0000 jmpl admn * reset vector address jmpl admn * int 0 interrupt vector address jmpl admn * int 1 interrupt vector address jmpl admn * timer a interrupt vector address jmpl admn * timer b interrupt vector address jmpl admn * timer c interrupt vector address jmpl admn * a/d interrupt vector address jmpl admn * serial interrupt vector address
514 * main program org $0100 admn equ * remd rsp * stack pointer reset br *+1 * status set call adinit * call the adinit routine (initializes the a/d converter and ram.) semd adstf * start the a/d converter admn01 call adscn * call the adscn routine (executes the a/d conversions.) tmd adendf * a/d conversion completed? brs admn99 * if yes, branch to admn99. brs admn01 * if no, branch to admn01. admn99 brs admn99 * adinit routine (initializes the a/d converter and ram.) adinit equ * lmid $f,amr1 * a/d mode register 1 (sets the r3 0 /an 0 to r3 3 /an 3 pins to function as the an 0 to an 3 pins.) lmid 1, amr2 * a/d mode register 2 (sets the a/d conversion time to be 67t cyc .) lmid 3, acr * a/d channel register (sets the analog input channel to be an 3 .) remd ifad * clear the a/d interrupt request flag. remd iaof * clear the iad off flag. lmid 0,adflag * clear the usage flag. lmid 3,adchno * initialize the pointer. rtn * adscn routine (executes the a/d conversions.) adscn equ * lwi 0 * clear the w register. tmd adstf * is adstf 1? brs adscn00 * if yes, branch to adscn00. adscn99 rtn * if no, return to the main program. adscn00 tmd ad1stf * is ad1stf 1? brs adscn10 * if yes, branch to adscn10.
515 *** first (channel 3) a/d conversion *** lmid 3,acr * a/d channel register remd ifad * a/d interrupt request flag semd ad1stf * set ad1stf. (indicates that the first a/d conversion is being performed.) lmid 3,adchno * initialize the pointer. semd adsf * set the a/d start flag (starts an a/d conversion.) brs adscn99 * branch to adscn99. *** channel 0 to 2 a/d conversions *** adscn10 tmd ifad * a/d interrupt request flag (has the previous a/d conversion completed?) brs adscn11 * if yes, branch to adscn11. brs adscn99 * if no, branch to adscn99. adscn11 remd ifad * clear the a/d interrupt request flag. lxi $a * specify the adrl transfer destination ram address (x). lamd adchno * load the pointer. lya * specify the transfer destination ram address (y). lamd adrl * move the adrl value to the accumulator. lma * store the contents of the accumulator in ram. lxi $b * specify the adru transfer destination ram address (x). lamd adru * move the adru value to the accumulator. lmady * store the contents of the accumulator in ram. y y ?1 brs adscn12 * branch to adscn12 if the a/d conversion has not completed. lmid 4,adflag * if the a/d conversion has completed, set adendf to 1, ad1stf to 0, and adstf to 0. brs adscn99 * branch to adscn99.
516 adscn12 lay * move the next transfer destination ram address (y) to the accumulator. lmad adchn0 * update the pointer. lmad acr * select the next a/d conversion channel. semd adsf * set the a/d start flag (starts an a/d conversion.) br *+1 * set the status. brs adscn99 * branch to adscn99. end
517 24.2 using timer b this section describes the use of timer b. feel free to take advantage of the techniques presented here in user application systems. this section has the following structure: functions and application functions application example system specifications register settings circuit diagram flowcharts program example figure 24-3 application example organization this application example uses an hd404339 series microcomputer. while the techniques shown here apply equally to the hd404318, hd404358, hd404358r, and hd404369 series microcomputers, the details of the register settings, clock settings, and pin arrangements would differ somewhat in the hd404318, hd404358, and hd404358r series. see section 18, ?imer b? for details. note: although the operation of the program examples included in this section has been verified, their operation should be re-verified if they are used in an actual user system.
518 (1) functions and application functions ? free-running/reload timer ............ key scan control, fixed time interrupts, and other functions ? external event counter ................. pulse counter ? input capture timer operation ....... measuring the time between trigger input edges. (2) application example (frequency measurement using timer b) this section presents an application that uses the hd4074339 timer b (in input capture timer mode) to determine the frequency of an input signal (square wave) and display the result in a pair of leds. system specifications ? the system clock used has a 1 mhz internal frequency based on a 4 mhz applied frequency. ? the signal to be measured is input to the evnb pin, and the result of the frequency determination is output from the d port (pins d 5 and d 6 ) to be displayed on two leds connected to those pins. ? the input frequency is judged to be one of three levels as listed below, and the result is displayed in the leds. overflow....................... both leds off under 1000 hz ............. one led lit. 1000 hz or over............ two leds lit. ? input capture mode is used for the timer b operating mode.
519 register settings ? a 4 mhz system clock oscillator frequency and a system clock divisor of 4 are used. the system clock selection register 1 (ssr1: $027) bit 1 is set. the system clock selection register 2 (ssr2: $028) is set to $0. ? the input clock period used is 8t cyc . timer mode register b1 (tmb1: $009) is set to $4. this allows timer b to measure periods up to a maximum of 8 ? 256 counts, which is 2040 ? (490 hz), in 8 ? units. ? the timer is used in input capture mode and rising edge detection is used. timer mode register b2 (tmb2: $026) is set to $6. ? the pull-up mos transistors are set to be active by setting bit 3 in the miscellaneous register (mis: $00c). since the d 2 /evnb pin is used as the evnb pin, the port mode register (pmrb: $024) bit 2 is set. tmb1 register setting ($009) bit tmb13 tmb12 tmb11 tmb10 setting 0100 tmb2 register setting ($026) bit tmb23 tmb22 tmb21 tmb20 setting x 1 1 0
520 figure 24-4 shows the timer b counter output. input signal 2048 s $ff 1000 s $7d 0 s $00 two leds lit one led lit both leds off : the counter is reset on an edge input 490 hz 1000 hz time overflow 490 hz or lower between 491 and 1000 hz 1001 hz or higher counter output figure 24-4 timer b counter output
521 frequency determination block circuit diagram: this circuit determines the frequency of a signal output from a pulse generator using an hd4074339. hd4074339 d 5 (39) d 6 (40) d 2 /evnb (36) led led 200 ? 200 ? v cc pulse generator figure 24-5 frequency determination block circuit diagram
522 flowcharts timer b interrupt processing did the counter overflow? is the counter value $7d or greater? turn on two leds timer b interrupt main initial settings wait for interrupt rtni turn off the leds turn on one led yes yes no no
523 sample program * symbol definitions ie equ $0,$000 * interrupt enable flag iftb equ $0,$002 * timer b interrupt flag imtb equ $1,$002 * timer b interrupt mask mis equ $3,$00c * miscellaneous register tmb1 equ $009 * timer mode register b1 trbl equ $00a * timer read register bl trbu equ $00b * timer read register bu tmb2 equ $026 * timer mode register b2 icef equ $1,$021 * ict error flag icsf equ $0,$021 * ict status flag pmrb equ $024 * port mode register b ssr1 equ $027 * system clock selection register 1 ssr2 equ $028 * system clock selection register 2 * interrupt vector settings org $000 strv jmpl fdprog * start vector address org $008 ictv jmpl tbint * timer b interrupt vector address * main program org $1000 lmid $2,ssr1 * system clock: 4 mhz lmid $0,ssr2 * system clock divisor: 4 lmid $4,tmb1 * input clock period: 8tcyc lmid $6,tmb2 * set timer b to ict mode with rising edge detection. lmid $4,pmrb * pin mode: evnb semd mis * pull-up mos transistors active remd icef * reset the ict error flag. remd icsf * reset the ict status flag. remd imtb * reset the timer b interrupt mask. semd ie * ie = 1 (interrupts enabled) bint nop * interrupt wait loop jmpl bint
524 * timer b interrupt handling routine tbint remd iftb * reset the timer b interrupt flag. tmd icef * if icef = 1 brl set0 compu lai $7 alemd trbu * if $7 trbu brl ifeq jmpl set2 ifeq anemd trbu * if $7 trbu brl set1 compl lai $d alemd trbl * if $d trbl brl set1 jmpl set2 set0 sedd $5 * turn both leds off. sedd $6 jmpl tmerend set1 redd $5 * light one led. sedd $6 jmpl tmerend set2 redd $5 * light both leds. redd $6 tmerend remd icef * reset the ict error flag. remd icsf * reset the ict status flag. rtni end ict: input capture timer $: indicates a hexadecimal value.
525 section 25 electrical characteristics 25.1 hd404344r series 25.1.1 absolute maximum ratings table 25-1 lists the absolute maximum ratings of the hd404344r series microcomputers. table 25-1 absolute maximum ratings (hd404344r series) item symbol rated value unit notes power supply voltage v cc ?.3 to +7.0 v programming voltage v pp ?.3 to +14.0 v 1 pin voltage v t ?.3 to v cc + 0.3 v 2 allowable total input current (current flowing in to the lsi) i 0 100 ma 3 allowable total output current (current flowing out from the lsi) i 0 30 ma 4 allowable input current i 0 30 ma 5, 6 (current flowing in to the lsi) 4 ma 5, 7 allowable output current (current flowing out from the lsi) ? 0 4ma8 operating temperature t opr ?0 to +75 ? storage temperature t stg ?5 to +125 ? notes: 1. applies to the hd4074344 test (v pp ) pin. 2. applies to d 0 to d 5 , r0, r1, r2, and r3. 3. the allowable total input current is the sum of the currents flowing from all the i/o pins to ground at the same time. 4. the allowable total output current is the sum of the currents flowing from v cc to all the i/o pins at the same time. 5. the allowable input current is the maximum value of the currents flowing from each i/o pin to ground. 6. applies to d 1 , d 2 , r1, and r2. 7. applies to d 0 , d 3 to d 5 , r0, and r3. 8. the allowable output current is the maximum value of the currents flowing from v cc to each i/o pin. use of this lsi at levels that exceed the absolute maximum ratings can permanently damage the lsi. also note that it is desirable to use this lsi within the conditions specified in the ?lectrical characteristics?section during normal operation. exceeding those conditions can cause the lsi to operate incorrectly and may adversely affect lsi reliability. all voltage values are referenced to ground.
526 25.1.2 electrical characteristics (1) dc characteristics tables 25-2 and 25-3 list the dc characteristics of the hd404344r series microcomputers. table 25-2 dc characteristics (hd404344r series) hd404344r, hd404342r, hd404341r, hd40c4344r, hd40c4342r, hd40c4341r : v cc = 2.5 to 5.5 v, gnd = 0 v, t a = ?0 to 75? hd4074344 : v cc = 2.7 to 5.5 v, gnd = 0 v, t a = ?0 to 75? unless specified otherwise. applicable rated value test item symbol pins min typ max unit conditions notes input high level voltage v ih reset , stopc , int 0 , sck , evnb 0.8 v cc ? cc + 0.3 v si 0.7 v cc ? cc + 0.3 osc 1 v cc ?0.5 v cc + 0.3 input low level voltage v il reset , stopc , int 0 , sck , evnb ?.3 0.2 v cc v si ?.3 0.3 v cc osc 1 ?.3 0.5 output high level voltage v oh sck , so, toc v cc ?1.0 v i oh = 0.5 ma output low level voltage v ol sck , so, toc 0.4 v i ol = 0.5 ma i/o leakage current | i il | reset , stopc , int 0 , sck , si, so, evnb, toc, osc 1 1 av in = 0 v to v cc 1 active mode current drain i cc1 v cc 3.5 ma v cc = 5 v, f osc = 4 mhz 2 i cc2 0.4 v cc = 3 v, 2, 4 0.5 f osc = 400 khz 2, 5
527 table 25-2 dc characteristics (hd404344r series) (cont) hd404344r, hd404342r, hd404341r, hd40c4344r, hd40c4342r, hd40c4341r : v cc = 2.5 to 5.5 v, gnd = 0 v, t a = ?0 to 75? hd4074344 : v cc = 2.7 to 5.5 v, gnd = 0 v, t a = ?0 to 75? unless specified otherwise. applicable rated value test item symbol pins min typ max unit conditions notes standby mode current drain i sby1 v cc 1.5 ma v cc = 5 v, f osc = 4 mhz 3 i sby2 0.2 v cc = 3 v, 3, 4 0.4 f osc = 400 khz 3, 5 stop mode current drain i stop v cc 10 ? v in ( reset ) = v cc ?0.3 v to v cc , v in (test) = 0 v to 0.3 v stop mode data retention voltage v stop v cc 2v notes: 1. except for the current flowing in the pull-up mos transistors and output buffers. 2. the power supply current with the system in the reset state and no i/o currents flowing. test conditions system state reset state pin states ? reset ..................... at the ground potential ? test ........................ at the ground potential ? d0 to d5, r0 to r3... at the v cc potential 3. the power supply current with the system timers operating and no i/o currents flowing. test conditions system state ? i/o: the same as in the reset state ? standby mode pin states ? reset ..................... at the v cc potential ? test ........................ at the ground potential ? d 0 to d 5 , r0 to r3 .... at the v cc potential 4. applies to the hd4074344. 5. applies to the hd404344r, hd404342r, hd404341r, hd40c4344r, hd40c4342r, and hd40c4341r.
528 table 25-3 standard pin i/o characteristics (hd404344r series) hd404344r, hd404342r, hd404341r, hd40c4344r, hd40c4342r, hd40c4341r : v cc = 2.5 to 5.5 v, gnd = 0 v, t a = ?0 to 75? hd4074344 : v cc = 2.7 to 5.5 v, gnd = 0 v, t a = ?0 to 75? unless specified otherwise. applicable rated value test item symbol pins min typ max unit conditions notes input high level voltage v ih d 0 to d 5 , r0 to r3 0.7 v cc ? cc + 0.3 v input low level voltage v il d 0 to d 5 , r0 to r3 ?.3 0.3 v cc v output high level voltage v oh d 0 to d 5 , r0 to r3 v cc ?1.0 v i oh = 0.5 ma output low level voltage v ol d 0 to d 5 , r0 to r3 0.4 v i ol = 0.5 ma d 1 , d 2 , r1, r2 2.0 i ol = 15 ma, v cc = 4.5 v to 5.5 v i/o leakage current |i il |d 0 to d 5 , r0 to r3 1 av in = 0 v to v cc 1 pull-up mos transistor current ? pu d 0 to d 5 , r0 to r3 30 150 300 ? v cc = 5 v, v in = 0 v notes: 1. except for the current flowing in the pull-up mos transistors and output buffers.
529 (2) ac characteristics tables 25-4 and 25-5 list the ac characteristics of the hd404344r series microcomputers. table 25-4 ac characteristics (hd404344r series) hd404344r, hd404342r, hd404341r, hd40c4344r, hd40c4342r, hd40c4341r : v cc = 2.5 to 5.5 v, gnd = 0 v, t a = ?0 to 75? hd4074344 : v cc = 2.7 to 5.5 v, gnd = 0 v, t a = ?0 to 75? unless specified otherwise. applicable rated value test item symbol pins min typ max unit conditions notes clock oscillator frequency (ceramic oscillator) f osc osc 1 , osc 2 0.4 4.5 mhz clock divisor = 4 clock oscillator frequency (resistor oscillator) f osc osc 1 , osc 2 1.0 2.0 3.5 mhz clock divisor = 4 r f = 20 k ? instruction cycle time (ceramic oscillator, external clock) t cyc 0.89 10 s clock divisor = 4 instruction cycle time (resistor oscillator) t cyc 1.14 4.0 ? clock divisor = 4 r f = 20 k ? oscillator stabilization period (external clock) t rc osc 1 , osc 2 2.0 ms 1 oscillator stabilization period (ceramic oscillator) t rc osc 1 , osc 2 2.0 ms 1 oscillator stabilization period (resistor oscillator) t rc osc 1 , osc 2 0.5 ms r f = 20 k ? 1, 8 external clock high level width t cph osc 1 92ns 2
530 table 25-4 ac characteristics (hd404344r series) (cont) hd404344r, hd404342r, hd404341r, hd40c4344r, hd40c4342r, hd40c4341r : v cc = 2.5 to 5.5 v, gnd = 0 v, t a = ?0 to 75? hd4074344 : v cc = 2.7 to 5.5 v, gnd = 0 v, t a = ?0 to 75? unless specified otherwise. applicable rated value test item symbol pins min typ max unit conditions notes external clock low level width t cpl osc 1 92ns 2 external clock rise time t cpr osc 1 20ns 2 external clock fall time t cpf osc 1 20ns 2 int 0 , evnb high level width t ih int 0 , evnb 2 t cyc 3 int 0 , evnb low level width t il int 0 , evnb 2 t cyc 3 reset low level width t rstl reset 2 t cyc 4 stopc low level width t stpl stopc 1 t rc 5 reset rise time t rstr reset 20ms 4 stopc rise time t stpr stopc 20ms 5 input capacitance c in all input pins other than test, and r1 0 to r1 2 15 pf f = 1 mhz, v in = 0 v test 15 f = 1 mhz, 6 40 v in = 0 v 7 r1 0 to r1 2 15 f = 1 mhz, 6 30 v in = 0 v 7 notes: 1. there are three cases where the oscillator stabilization period applies: when power is first applied, the time between the point when v cc reaches v cc min and the point the oscillator is stable. when stop mode is cleared, the time between the point when the reset input reaches the low level and the point the oscillator is stable. when stop mode is cleared, the time between the point when the stopc input reaches the low level and the point the oscillator is stable. to assure the time necessary to achieve stable oscillation at power on and when clearing stop mode, apply a low level to the reset or stopc input for at least t rc .
531 since the oscillator stabilization period varies with the details of the mounted circuit, stray capacitances, and other factors, this value should be determined based on thorough consultations with the manufacturer of the ceramic oscillator used. 2. see figure 25-1. 3. see figure 25-2. 4. see figure 25-3. 5. see figure 25-4. 6. applies to the hd404344r, hd404342r, hd404341r, hd40c4344r, hd40c4342r, and hd40c4341r. 7. applies to the hd4074344. 8. applies to the hd40c4344r, hd40c4342r, and hd40c4341r. v cc 0.5v 0.5 v t cpr t cpf t cpl t cph 1/f cp osc 1 figure 25-1 external clock timing (hd404344r series) 0.8 v cc 0.2 v cc t ih t il int 0 , evnb figure 25-2 interrupt timing (hd404344r series) 0.8 v cc 0.2 v cc t rstl t rstr reset figure 25-3 reset timing (hd404344r series) 0.8 v cc 0.2 v cc t stpl t stpr stopc figure 25-4 stopc timing (hd404344r series)
532 table 25-5 serial interface timing characteristics (hd404344r series) hd404344r, hd404342r, hd404341r, hd40c4344r, hd40c4342r, hd40c4341r : v cc = 2.5 to 5.5 v, gnd = 0 v, t a = ?0 to 75? hd4074344 : v cc = 2.7 to 5.5 v, gnd = 0 v, t a = ?0 to 75? unless specified otherwise. when the transfer clock is output: applicable rated value test item symbol pins min typ max unit conditions notes transfer clock cycle time t scyc sck 1 t cyc with the load shown in figure 25-6 1 transfer clock high level width t sckh sck 0.4 t scyc with the load shown in figure 25-6 1 transfer clock low level width t sckl sck 0.4 t scyc with the load shown in figure 25-6 1 transfer clock rise time t sckr sck 80 ns with the load shown in figure 25-6 1 transfer clock fall time t sckf sck 80 ns with the load shown in figure 25-6 1 serial output data delay time t dso so 300 ns with the load shown in figure 25-6 1 serial input data setup time t ssi si 100 ns 1 serial input data hold time t hsi si 200 ns 1 note: 1. see figure 25-5.
533 table 25-5 serial interface timing characteristics (hd404344r series) (cont) hd404344r, hd404342r, hd404341r, hd40c4344r, hd40c4342r, hd40c4341r : v cc = 2.5 to 5.5 v, gnd = 0 v, t a = ?0 to 75? hd4074344 : v cc = 2.7 to 5.5 v, gnd = 0 v, t a = ?0 to 75? unless specified otherwise. when the transfer clock is input: applicable rated value test item symbol pins min typ max unit conditions notes transfer clock cycle time t scyc sck 1 t cyc 1 transfer clock high level width t sckh sck 0.4 t scyc 1 transfer clock low level width t sckl sck 0.4 t scyc 1 transfer clock rise time t sckr sck 80 ns 1 transfer clock fall time t sckf sck 80 ns 1 serial output data delay time t dso so 300 ns with the load shown in figure 25-6 1 serial input data setup time t ssi si 100 ns 1 serial input data hold time t hsi si 200 ns 1 note: 1. see figure 25-5.
534 t scyc t sckf t sckl t sckh t dso t ssi t hsi 0.7 v cc 0.3 v cc v cc 0.5 v 0.4 v v cc 0.5 v (0.8 v cc ) * 0.4 v (0.2 v cc ) * si so sck note: * the values v cc 0.5 v and 0.4 v are the voltages for transfer clock output. the values 0.8 v cc and 0.2 v cc are the voltages for transfer clock input. t sckr figure 25-5 serial interface timing v cc r l = 2.6 k ? 1s2074 h or equivalent product r 12 k ? c 30 pf test point figure 25-6 timing load circuit
535 (3) a/d converter characteristics table 25-6 lists the characteristics of the hd404344r series a/d converter. table 25-6 a/d converter characteristics (hd404344r series) hd404344r, hd404342r, hd404341r, hd40c4344r, hd40c4342r, hd40c4341r : v cc = 2.5 to 5.5 v, gnd = 0 v, t a = 20 to 75 c hd4074344 : v cc = 2.7 to 5.5 v, gnd = 0 v, t a = 20 to 75 c unless specified otherwise. applicable rated value test item symbol pins min typ max unit conditions notes analog input voltage av in an 0 to an 3 gnd v cc v analog input capacitance ca in an 0 to an 3 15 pf resolution 8 bits number of inputs 0 4 channels absolute an 0 to an 3 2.0 2.0 lsb 1 precision 2.5 2.5 t a = 25 c, v cc = 5.0 v 2 conversion time 34 67 t cyc input impedance an 0 to an 3 1 m ? f osc = 1 mhz, v in = 0 v notes: 1. supplies to the hd404344r, hd404342r, hd404341r, hd40c4344r, hd40c4342r, hd40c4341r. 2. supplies to the hd4074344.
536 25.2 hd404394 series 25.2.1 absolute maximum ratings table 25-7 lists the absolute maximum ratings of the hd404394 series microcomputers. table 25-7 absolute maximum ratings (hd404394 series) item symbol rated value unit notes power supply voltage v cc 0.3 to +7.0 v programming voltage v pp 0.3 to +14.0 v 1 pin voltage v t 0.3 to v cc + 0.3 v 2 0.3 to +15.0 v 3 allowable total input current (current flowing in to the lsi) i 0 100 ma 4 allowable total output current (current flowing in to the lsi) i 0 30 ma 5 allowable input current i 0 30 ma 6, 7 (current flowing in to the lsi) 4 ma 6, 8 allowable output current (current flowing out from the lsi) i 0 4ma9 operating temperature t opr 20 to +75 c storage temperature t stg 55 to +125 c notes: 1. applies to the hd4074394 test (v pp ) pin. 2. applies to d 0 to d 5 , r0, r13, r2, and r3 1 to r3 3 . 3. applies to r1 0 to r1 2 . 4. the allowable total input current is the sum of the currents flowing from all the i/o pins to ground at the same time. 5. the allowable total output current is the sum of the currents flowing from v cc to all the i/o pins at the same time. 6. the allowable input current is the maximum value of the currents flowing from each i/o pin to ground. 7. applies to d 1 , d 2 , r1, and r2. 8. applies to d 0 , d 3 to d 5 , r0, and r3 1 to r3 3 . 9. the allowable output current is the maximum value of the currents flowing from v cc to each i/o pin. use of this lsi at levels that exceed the absolute maximum ratings can permanently damage the lsi. also note that it is desirable to use this lsi within the conditions specified in the electrical characteristics section during normal operation. exceeding those conditions can cause the lsi to operate incorrectly and may adversely affect lsi reliability. all voltage values are referenced to ground.
537 25.2.2 electrical characteristics (1) dc characteristics tables 25-8 to 25-10 list the dc characteristics of the hd404394 series microcomputers. table 25-8 dc characteristics (hd404394 series) v cc = 2.7 to 5.5 v, gnd = 0 v, t a = 20 to 75 c unless specified otherwise. applicable rated value test item symbol pins min typ max unit conditions notes input high level voltage v ih reset , stopc , int 0 , sck , evnb 0.8 v cc v cc + 0.3 v si 0.7 v cc v cc + 0.3 osc 1 v cc 0.5 v cc + 0.3 input low level voltage v il reset , stopc , int 0 , sck , evnb 0.3 0.2 v cc v si 0.3 0.3 v cc osc 1 0.3 0.5 output high level voltage v oh sck , so, toc v cc 1.0 v i oh = 0.5 ma output low level voltage v ol sck , so, toc 0.4 v i ol = 0.5 ma i/o leakage current | i il | reset , stopc , sck , int 0 , si, so, evnb, toc, osc 1 1av in = 0 v to v cc 1 active mode current drain i cc1 v cc 3.5 ma v cc = 5 v, f osc = 4 mhz 2 i cc2 0.4 v cc = 3 v, f osc = 400 khz
538 table 25-8 dc characteristics (hd404394 series) (cont) v cc = 2.7 to 5.5 v, gnd = 0 v, t a = 20 to 75 c unless specified otherwise. applicable rated value test item symbol pins min typ max unit conditions notes standby mode current drain i sby1 v cc 1.5 ma v cc = 5 v, f osc = 4 mhz 3 i sby2 0.2 v cc = 3 v, f osc = 400 khz stop mode current drain i stop v cc 10 a v in ( reset ) = v cc 0.3 v to v cc , v in (test) = 0 v to 0.3 v stop mode data retention voltage v stop v cc 2 v notes: 1. except for the current flowing in the pull-up mos transistors and output buffers. 2. the power supply current with the system in the reset state and no i/o currents flowing. test conditions system state reset state pin states reset ..................... at the ground potential test ........................ at the ground potential d 0 to d 5 , r 0 to r 3 ...... at the v cc potential 3. the power supply current with the system timers operating and no i/o currents flowing. test conditions system state i/o: the same as in the reset state standby mode pin states reset ..................... at the v cc potential test ........................ at the ground potential d 0 to d 5 , r0 to r3 .... at the v cc potential
539 table 25-9 standard pin i/o characteristics (hd404394 series) v cc = 2.7 to 5.5 v, gnd = 0 v, t a = 20 to 75 c unless specified otherwise. applicable rated value test item symbol pins min typ max unit conditions notes input high level voltage v ih d 0 to d 5 , r0, r1 3 , r2, r3 1 to r3 3 0.7 v cc v cc + 0.3 v input low level voltage v il d 0 to d 5 , r0, r1 3 , r2, r3 1 to r3 3 0.3 0.3 v cc v output high level voltage v oh d 0 to d 5 , r0, r3 1 to r3 3 v cc 1.0 v i oh = 0.5 ma r1 3 , r2 v cc 0.5 500 k ? at v cc output low level voltage v ol d 0 to d 5 , r0, r1 3 , r2, r3 1 to r3 3 0.4 v i ol = 0.5 ma d 1 , d 2 , r1 3 , r2 2.0 i ol = 15 ma, v cc = 4.5 v to 5.5 v i/o leakage current |i il |d 0 to d 5 , r0, r1 3 , r2, r3 1 to r3 3 1av in = 0 v to v cc 1 pull-up mos transistor current i pu d 0 to d 5 , r0, r3 1 to r3 3 30 150 300 a v cc = 5 v, v in = 0 v note: except for the current flowing in the pull-up mos transistors and output buffers.
540 table 25-10 medium voltage nmos open drain pin i/o characteristics (hd404394 series) v cc = 2.7 to 5.5 v, gnd = 0 v, t a = 20 to 75 c unless specified otherwise. applicable rated value test item symbol pins min typ max unit conditions notes input high level voltage v ih r1 0 to r1 2 0.7 v cc 12.0 v input low level voltage v il r1 0 to r1 2 0.3 0.3 v cc v output high level voltage v oh r1 0 to r1 2 11.5 v 500 k ? at 12 v output low v ol r1 0 to r1 2 0.4 v i oh = 0.5 ma level voltage 2.0 i ol = 15 ma, v cc = 4.5 v to 5.5 v i/o leakage current | i il |r1 0 to r1 2 20 a v in = 0 v to 12 v 1 note: except for the current flow in the output buffers.
541 (2) ac characteristics tables 25-11 and 25-12 list the ac characteristics of the hd404394 series microcomputers. table 25-11 ac characteristics (hd404394 series) v cc = 2.7 to 5.5 v, gnd = 0 v, t a = 20 to 75 c unless specified otherwise. applicable rated value test item symbol pins min typ max unit conditions notes clock oscillator frequency f osc osc 1 , osc 2 0.4 4 4.5 mhz instruction cycle time (ceramic oscillator) t cyc 0.89 1 10 s clock divisor = 4 oscillator stabilization period t rc osc 1 , osc 2 2ms 1 external clock high level width t cph osc 1 92 ns 2 external clock low level width t cpl osc 1 92 ns 2 external clock rise time t cpr osc 1 20 ns 2 external clock fall time t cpf osc 1 20 ns 2 int 0 , evnb high level width t ih int 0 , evnb 2 t cyc 3 int 0 , evnb low level width t il int 0 , evnb 2 t cyc 3 reset low level width t rstl reset 2 t cyc 4 stopc low level width t stpl stopc 1 t rc 5 reset rise time t rstr reset 20 ms 4 stopc rise time t stpr stopc 20 ms 5
542 table 25-11 ac characteristics (hd404394 series) (cont) v cc = 2.7 to 5.5 v, gnd = 0 v, t a = 20 to 75 c unless specified otherwise. applicable rated value test item symbol pins min typ max unit conditions notes input capacitance c in all input pins other than test, v ref , and r1 0 to r1 2 15 pf f = 1 mhz, v in = 0 v test 15 f = 1 mhz, 6 40 v in = 0 v 7 v ref 30 f = 1 mhz, v in = 0 v r1 0 to r1 2 30 f = 1 mhz, v in = 0 v notes: 1. there are three cases where the oscillator stabilization period applies: when power is first applied, the time between the point when v cc reaches 2.7 v and the point the oscillator is stable. when stop mode is cleared, the time between the point when the reset input reaches the low level and the point the oscillator is stable. when stop mode is cleared, the time between the point when the stopc input reaches the low level and the point the oscillator is stable. to assure the time necessary to achieve stable oscillation at power on and when clearing stop mode, apply a low level to the reset or stopc input for at least t rc . since the oscillator stabilization period varies with the details of the mounted circuit, stray capacitances, and other factors, this value should be determined based on thorough consultations with the manufacturer of the ceramic oscillator used. 2. see figure 25-7. 3. see figure 25-8. 4. see figure 25-9. 5. see figure 25-10. 6. applies to the hd404391, hd404392, and hd404394. 7. applies to the hd4074394.
543 v cc 0.5v 0.5 v t cpr t cpf t cpl t cph 1/f cp osc 1 figure 25-7 external clock timing (hd404394 series) 0.8 v cc 0.2 v cc t ih t il int 0 , evnb figure 25-8 interrupt timing (hd404394 series) 0.8 v cc 0.2 v cc t rstl t rstr reset figure 25-9 reset timing (hd404394 series) 0.8 v cc 0.2 v cc t stpl t stpr stopc figure 25-10 stopc timing (hd404394 series)
544 table 25-12 serial interface timing characteristics (hd404394 series) v cc = 2.7 to 5.5 v, gnd = 0 v, t a = 20 to 75 c unless specified otherwise. when the transfer clock is output: applicable rated value test item symbol pins min typ max unit conditions notes transfer clock cycle time t scyc sck 1 t cyc with the load shown in figure 25-12 1 transfer clock high level width t sckh sck 0.4 t scyc with the load shown in figure 25-12 1 transfer clock low level width t sckl sck 0.4 t scyc with the load shown in figure 25-12 1 transfer clock rise time t sckr sck 80 ns with the load shown in figure 25-12 1 transfer clock fall time t sckf sck 80 ns with the load shown in figure 25-12 1 serial output data delay time t dso so 300 ns with the load shown in figure 25-12 1 serial input data setup time t ssi si 100 ns 1 serial input data hold time t hsi si 200 ns 1 note: see figure 25-11.
545 table 25-12 serial interface timing characteristics (hd404394 series) (cont) v cc = 2.7 to 5.5 v, gnd = 0 v, t a = 20 to 75 c unless specified otherwise. when the transfer clock is input: applicable rated value test item symbol pins min typ max unit conditions notes transfer clock cycle time t scyc sck 1 t cyc 1 transfer clock high level width t sckh sck 0.4 t scyc 1 transfer clock low level width t sckl sck 0.4 t scyc 1 transfer clock rise time t sckr sck 80 ns 1 transfer clock fall time t sckf sck 80 ns 1 serial output data delay time t dso so 300 ns with the load shown in figure 25-12 1 serial input data setup time t ssi si 100 ns 1 serial input data hold time t hsi si 200 ns 1 note: see figure 25-11.
546 t scyc t sckf t sckl t sckh t dso t ssi t hsi 0.7 v cc 0.3 v cc v cc 0.5 v 0.4 v v cc 0.5 v (0.8 v cc ) * 0.4 v (0.2 v cc ) * si so sck note: * the values v cc 0.5 v and 0.4 v are the voltages for transfer clock output. the values 0.8 v cc and 0.2 v cc are the voltages for transfer clock input. t sckr figure 25-11 serial interface timing v cc r l = 2.6 k ? 1s2074 h or equivalent product r 12 k ? c 30 pf test point figure 25-12 timing load circuit
547 (3) a/d converter characteristics table 25-13 lists the characteristics of the hd404394 series a/d converter. table 25-13 a/d converter characteristics (hd404394 series) v cc = 2.7 to 5.5 v, gnd = 0 v, t a = 20 to 75 c unless specified otherwise. applicable rated value test item symbol pins min typ max unit conditions notes analog input reference voltage range v ref v ref 0.5 v cc v cc v analog input voltage av in an 1 to an 3 gnd v ref v current from v ref to gnd i ad 200 a v ref = v cc = 5.0 v analog input capacitance ca in an 1 to an 3 15 pf resolution 8 bits number of inputs 0 3 channels absolute precision an 1 to an 3 3.0 3.0 lsb t a = 25 c, v ref = v cc = 5.0 v conversion time 34 67 t cyc input impedance an 1 to an 3 1 m ? f osc = 1 mhz, v in = 0 v
548 25.3 hd404318 series 25.3.1 absolute maximum ratings table 25-14 lists the absolute maximum ratings of the hd404318 series microcomputers. table 25-14 absolute maximum ratings (hd404318 series) item symbol rated value unit notes power supply voltage v cc 0.3 to +7.0 v programming voltage v pp 0.3 to +14.0 v 1 pin voltage v t 0.3 to v cc + 0.3 v 2 v cc 45 to v cc + 0.3 v 3 allowable total input current (current flowing in to the lsi) i 0 70 ma 4 allowable total output current (current flowing out from the lsi) i 0 150 ma 5 allowable input current i 0 4 ma 6, 7 (current flowing in to the lsi) 20 ma 6, 8 allowable output current i 0 4 ma 9, 10 (current flowing out from the lsi) 30 ma 10, 11 operating temperature t opr 20 to +75 c storage temperature t stg 55 to +125 c notes: 1. applies to the hd4074318 test (v pp ) pin. 2. applies to all standard pins. 3. applies to high voltage pins. 4. the allowable total input current is the sum of the currents flowing from all the i/o pins to ground at the same time. 5. the allowable total output current is the sum of the currents flowing from v cc to all the i/o pins at the same time. 6. the allowable input current is the maximum value of the currents flowing from each i/o pin to ground. 7. applies to r3 and r4. 8. applies to r0. 9. applies to r0, r3, and r4. 10. the allowable output current is the maximum value of the currents flowing from v cc to each i/o pin. 11. applies to d 0 to d 8 , r1, r2, and r8. use of this lsi at levels that exceed the absolute maximum ratings can permanently damage the lsi. also note that it is desirable to use this lsi within the conditions specified in the electrical characteristics section during normal operation. exceeding those conditions can cause the lsi to operate incorrectly and may adversely affect lsi reliability.
549 25.3.2 electrical characteristics (1) dc characteristics tables 25-15 to 25-17 list the dc characteristics of the hd404318 series microcomputers. table 25-15 dc characteristics (hd404318 series) v cc = 4.0 to 5.5 v, gnd = 0 v, v disp = v cc 40 v to v cc , t a = 20 to 75 c unless specified otherwise. applicable rated value test item symbol pins min typ max unit conditions notes input high level voltage v ih reset , sck , si int 0 , int 1 , stopc , evnb 0.8 v cc v cc + 0.3 v osc 1 v cc 0.5 v cc + 0.3 input low level voltage v il reset , sck , si 0.3 0.2 v cc v int 0 , int 1 , stopc , evnb v cc 40 0.2 v cc osc 1 0.3 0.5 output high level voltage v oh sck , so, toc v cc 0.5 v i oh = 0.5 ma output low level voltage v ol sck , so, toc 0.4 v i ol = 0.4 ma i/o leakage current | i il | reset , sck , si, so, toc, osc 1 1av in = 0 v to v cc 1 int 0 , int 1 , stopc, evnb 20 v in = v cc 40 v to v cc active mode i cc v cc 5.0 ma v cc = 5 v, 2, 5 current drain 8.0 f osc = 4 mhz 2, 6
550 table 25-15 dc characteristics (hd404318 series) (cont) v cc = 4.0 to 5.5 v, gnd = 0 v, v disp = v cc 40 v to v cc , t a = 20 to 75 c unless specified otherwise. applicable rated value test item symbol pins min typ max unit conditions notes standby mode current drain i sby v cc 2.0 ma v cc = 5 v, f osc = 4 mhz 3 stop mode i stop v cc 10 a v cc = 5 v 4, 5 current drain 20 4, 6 stop mode data retention voltage v stop v cc 2 v notes: 1. except for the current flowing in the pull-up mos transistors and output buffers. 2. the power supply current with the system in the reset state and no i/o currents flowing. test conditions system state reset state pin states reset , test .......... at the ground potential r0, r3, and r4......... at the v cc potential d 0 to d 8 , r1, r2, r8, and ra 1 ............. at the v disp potential 3. the power supply current with the system timers operating and no i/o currents flowing. test conditions system state i/o: the same as in the reset state standby mode pin states reset ..................... at the v cc potential test ........................ at the ground potential r0, r3, and r4......... at the v cc potential d 0 to d 8 , r1, r2, r8, and ra 1 ............. at the v disp potential 4. the power supply current with no i/o currents flowing. test conditions pin states r0, r3, and r4......... at the v cc potential d 0 to d 8 , r1, r2, r8, and ra 1 ............. at the ground potential 5. applies to the hd404314, hd404316, and hd404318. 6. applies to the hd4074318.
551 table 25-16 standard pin i/o characteristics (hd404318 series) v cc = 4.0 to 5.5 v, gnd = 0 v, v disp = v cc 40 v to v cc , t a = 20 to 75 c unless specified otherwise. applicable rated value test item symbol pins min typ max unit conditions notes input high level voltage v ih r0, r3, r4 0.7 v cc v cc + 0.3 v v input low level voltage v il r0, r3, r4 0.3 0.3 v cc v output high level voltage v oh r0, r3, r4 v cc 0.5 v i oh = 0.5 ma output low v ol r3, r4 0.4 v i ol = 1.6 ma level voltage r0 2.0 i ol = 10 ma i/o leakage current | i il | r0, r3, r4 1av in = 0 v to v cc 1 pull-up mos i pu r0, r3, r4 30 150 300 a v cc = 5 v, 2 transistor current 30 80 180 v in = 0 v 3 notes: 1. except for the current flowing in the output buffers. 2. applies to the hd404314, hd404316, and hd404318. 3. applies to the hd4074318.
552 table 25-17 high voltage pin i/o characteristics (hd404318 series) v cc = 4.0 to 5.5 v, gnd = 0 v, v disp = v cc 40 v to v cc , t a = 20 to 75 c unless specified otherwise. applicable rated value test item symbol pins min typ max unit conditions notes input high level voltage v ih d 0 to d 8 , r1, r2, r8, ra 1 0.7 v cc v cc + 0.3 v input low level voltage v il d 0 to d 8 , r1, r2, r8, ra 1 v cc 40 0.3 v cc v output high level voltage v oh d 0 to d 8 , r1, r2 r8, buzz v cc 3.0 v cc 2.0 v cc 1.0 v i oh = 15 ma i oh = 10 ma i oh = 4 ma output low level voltage v ol d 0 to d 8 , r1, r2 r8, buzz v cc 37 v cc 37 vv disp = v cc 40 v 150 k ? at v cc 40 v 1 2 i/o leakage current |i il |d 0 to d 8 , r1, r2, r8 ra 1 , buzz 20 a v in = v cc 40 v to v cc 3 pull-down resistor current i pd d 0 to d 8 , r1, r2, r8, buzz 200 600 1000 a v disp = v cc 35 v, v in = v cc 1 notes: 1. applies to pins for which the pull-down resistor mask option was selected. 2. applies to pins for which the no pull-down resistor mask option was selected. 3. except for the current flow in the output buffers.
553 (2) ac characteristics tables 25-18 and 25-19 list the ac characteristics of the hd404318 series microcomputers. table 25-18 ac characteristics (hd404318 series) v cc = 4.0 to 5.5 v, gnd = 0 v, v disp = v cc 40 v to v cc , t a = 20 to 75 c unless specified otherwise. applicable rated value test item symbol pins min typ max unit conditions notes clock oscillator frequency f osc osc 1 , osc 2 0.4 4 4.5 mhz clock divisor = 4 instruction cycle time t cyc 0.89 1 10 s oscillator stabilization period (ceramic oscillator) t rc osc 1 , osc 2 7.5 ms 1 oscillator stabilization period (crystal oscillator) t rc osc 1 , osc 2 40 ms 1 external clock high level width t cph osc 1 92 ns 2 external clock low level width t cpl osc 1 92 ns 2 external clock rise time t cpr osc 1 20 ns 2 external clock fall time t cpf osc 1 20 ns 2 int 0 , int 1 , and evnb high level width t ih int 0 , int 1 , evnb 2 t cyc 3 int 0 , int 1 , and evnb low level width t il int 0 , int 1 , evnb 2 t cyc 3 reset low level width t rstl reset 2 t cyc 4 stopc low level width t stpl stopc 1 t rc 5
554 table 25-18 ac characteristics (hd404318 series) (cont) v cc = 4.0 to 5.5 v, gnd = 0 v, v disp = v cc 40 v to v cc , t a = 20 to 75 c unless specified otherwise. applicable rated value test item symbol pins min typ max unit conditions notes reset rise time t rstr reset 20 ms 4 stopc rise time t stpr stopc 20 ms 5 input capacitance c in all input pins other than test 30 pf f = 1 mhz, v in = 0 v test 30 f = 1 mhz, 6 180 v in = 0 v 7 notes: 1. there are three cases where the oscillator stabilization period applies: when power is first applied, the time between the point when v cc reaches 4.0 v and the point the oscillator is stable. when stop mode is cleared, the time between the point when the reset input reaches the low level and the point the oscillator is stable. when stop mode is cleared, the time between the point when the stopc input reaches the low level and the point the oscillator is stable. to assure the time necessary to achieve stable oscillation at power on and when clearing stop mode, apply a low level to the reset or stopc input for at least t rc . since the oscillator stabilization period varies with the details of the mounted circuit, stray capacitances, and other factors, this value should be determined based on thorough consultations with the manufacturer of the ceramic oscillator used. 2. see figure 25-13. 3. see figure 25-14. 4. see figure 25-15. 5. see figure 25-16. 6. applies to the hd404314, hd404316, and hd404318. 7. applies to the hd4074318.
555 v cc 0.5v 0.5 v t cpr t cpf t cpl t cph 1/f cp osc 1 figure 25-13 external clock timing (hd404318 series) 0.8 v cc 0.2 v cc t ih t il int 0 , int 1 , evnb figure 25-14 interrupt timing (hd404318 series) 0.8 v cc 0.2 v cc t rstl t rstr reset figure 25-15 reset timing (hd404318 series) 0.8 v cc 0.2 v cc t stpl t stpr stopc figure 25-16 stopc timing (hd404318 series)
556 table 25-19 serial interface timing characteristics (hd404318 series) v cc = 4.0 to 5.5 v, gnd = 0 v, v disp = v cc 40 v to v cc , t a = 20 to 75 c unless specified otherwise. when the transfer clock is output: applicable rated value test item symbol pins min typ max unit conditions notes transfer clock cycle time t scyc sck 1 t cyc with the load shown in figure 25-18 1 transfer clock high level width t sckh sck 0.4 t scyc with the load shown in figure 25-18 1 transfer clock low level width t sckl sck 0.4 t scyc with the load shown in figure 25-18 1 transfer clock rise time t sckr sck 80 ns with the load shown in figure 25-18 1 transfer clock fall time t sckf sck 80 ns with the load shown in figure 25-18 1 serial output data delay time t dso so 300 ns with the load shown in figure 25-18 1 serial input data setup time t ssi si 100 ns 1 serial input data hold time t hsi si 200 ns 1 note: see figure 25-17.
557 table 25-19 serial interface timing characteristics (hd404318 series) (cont) v cc = 4.0 to 5.5 v, gnd = 0 v, v disp = v cc 40 v to v cc , t a = 20 to 75 c unless specified otherwise. when the transfer clock is input: applicable rated value test item symbol pins min typ max unit conditions notes transfer clock cycle time t scyc sck 1 t cyc 1 transfer clock high level width t sckh sck 0.4 t scyc 1 transfer clock low level width t sckl sck 0.4 t scyc 1 transfer clock rise time t sckr sck 80 ns 1 transfer clock fall time t sckf sck 80 ns 1 serial output data delay time t dso so 300 ns with the load shown in figure 25-18 1 serial input data setup time t ssi si 100 ns 1 serial input data hold time t hsi si 200 ns 1 note: see figure 25-17.
558 t scyc t sckf t sckl t sckh t dso t ssi t hsi 0.8 v cc 0.2 v cc v cc 2.0 v 0.8 v v cc 2.0 v (0.8 v cc ) * 0.8 v (0.2 v cc ) * si so sck note: * the values v cc 2.0 v and 0.8 v are the voltages for transfer clock output. the values 0.8 v cc and 0.2 v cc are the voltages for transfer clock input. t sckr figure 25-17 serial interface timing (hd404318 series) v cc r l = 2.6 k ? 1s2074 h or equivalent product r 12 k ? c 30 pf test point figure 25-18 timing load circuit
559 (3) a/d converter characteristics table 25-20 lists the characteristics of the hd404318 series a/d converter. table 25-20 a/d converter characteristics (hd404318 series) v cc = 4.0 to 5.5 v, gnd = 0 v, v disp = v cc 40 v to v cc , t a = 20 to 75 c unless specified otherwise. applicable rated value test item symbol pins min typ max unit conditions notes analog supply voltage av cc av cc v cc 0.3 v cc v cc + 0.3 v 1 analog input voltage av in an 0 to an 7 av ss av cc v current from av cc to av ss i ad 200 a v cc = av cc = 5.0 v analog input capacitance ca in an 0 to an 7 30 pf resolution 8 8 8 bits number of inputs 0 8 channels absolute precision 2.0 lsb conversion time 34 67 t cyc input impedance an 0 to an 7 1 m ? note: connect to the v cc pin if the a/d converter is not used in the application. 25.4 hd404358/hd404358r series 25.4.1 absolute maximum ratings table 25-21 lists the absolute maximum ratings of the hd404358 and hd404358r series microcomputers.
560 table 25-21 absolute maximum ratings (hd404358 and hd404358r series) hd404358 series hd404358r series item symbol rated value rated value unit notes power supply voltage v cc 0.3 to +7.0 0.3 to +7.0 v programming voltage v pp 0.3 to +14.0 0.3 to +14.0 v 1 pin voltage v t 0.3 to v cc + 0.3 0.3 to v cc + 0.3 v 2 0.3 to +15.0 v3 allowable total input current (current flowing in to the lsi) i 0 105 160 ma 4 allowable total output current (current flowing out from the lsi) i 0 50 50 ma 5 allowable input current i 0 4 4 ma 6, 7 (current flowing in to the lsi) 30 30 ma 6, 8 allowable output current (current flowing out from the lsi) i 0 4 4 ma 9, 10 operating temperature t opr 20 to +75 20 to +75 c storage temperature t stg 55 to +125 55 to +125 c notes: 1. applies to the hd407a4359, hd407a4359r, and hd407c4359r test (v pp ) pin. 2. applies to all standard pins. 3. applies to the medium voltage pins. 4. the allowable total input current is the sum of the currents flowing from all the i/o pins to ground at the same time. 5. the allowable total output current is the sum of the currents flowing from v cc to all the i/o pins at the same time. 6. the allowable input current is the maximum value of the currents flowing from each i/o pin to ground. 7. hd404358 series: applies to d 0 to d 8 , r0, r1, r3, r4, and r8. hd404358r series: applies to d 0 to d 4 , r3, and r4. 8. hd404358 series: applies to r2. hd404358r series: applies to d 5 to d 8 , r0, r1, r2, and r8. 9. hd404358 series: applies to d 0 to d 8 , r0, r1, r3, r4, and r8. hd404358r series: applies to d 0 to d 8 , r0, r1, r2, r3, r4, and r8. 10. the allowable output current is the maximum value of the currents flowing from v cc to each i/o pin. use of this lsi at levels that exceed the absolute maximum ratings can permanently damage the lsi. also note that it is desirable to use this lsi within the conditions specified in the electrical characteristics section during normal operation. exceeding those conditions can cause the lsi to operate incorrectly and may adversely affect lsi reliability. all voltage values are referenced to ground.
561 25.4.2 electrical characteristics (1) dc characteristics tables 25-22 to 25-24 list the dc characteristics of the hd404358 and hd404358r series microcomputers. table 25-22 dc characteristics (hd404358 and hd404358r series) hd404354, hd404356, hd404358, hd40a4354, hd40a4356, hd40a4358: v cc = 2.7 to 6.0 v, gnd = 0 v, t a = 20 to 75 c hd407a4359: v cc = 2.7 to 5.5 v, gnd = 0 v, t a = 20 to 75 c hd404358r series: v cc = 2.5 to 5.5 v, gnd = 0 v, t a = 20 to 75 c unless specified otherwise. applicable rated value test item symbol pins min typ max unit conditions notes input high level voltage v ih reset , stopc , int 0 , int 1 , sck , evnb 0.8 v cc v cc + 0.3 v si 0.7 v cc v cc + 0.3 osc 1 v cc 0.5 v cc + 0.3 input low level voltage v il reset , stopc , int 0 , int 1 , sck , evnb 0.3 0.2 v cc v si 0.3 0.3 v cc osc 1 0.3 0.5 output high level voltage v oh sck , so, toc v cc 0.5 v i oh = 0.5 ma output low level voltage v ol sck , so, toc 0.4 v i ol = 0.4 ma i/o leakage current | i il | reset , stopc , int 0 , int 1 , sck , si, so, evnb, toc, osc 1 1av in = 0 v to v cc 1
562 table 25-22 dc characteristics (hd404358 and hd404358r series) (cont) hd404354, hd404356, hd404358, hd40a4354, hd40a4356, hd40a4358: v cc = 2.7 to 6.0 v, gnd = 0 v, t a = 20 to 75 c hd407a4359: v cc = 2.7 to 5.5 v, gnd = 0 v, t a = 20 to 75 c hd404358r series: v cc = 2.5 to 5.5 v, gnd = 0 v, t a = 20 to 75 c unless specified otherwise. applicable rated value test item symbol pins min typ max unit conditions notes active mode current drain i cc v cc 5.0 ma v cc = 5 v, f osc = 4 mhz 2.5 i cc1 3.5 ma v cc = 5 v, f osc = 4 mhz 2.6 i cc2 0.6 ma v cc = 3 v, f osc = 400 khz i cc3 6.5 ma v cc = 5 v, f osc = 8 mhz standby mode current drain i sby v cc 2.0 ma v cc = 5 v, f osc = 4 mhz 3.5 i sby1 1.5 ma v cc = 5 v, f osc = 4 mhz 3.6 i sby2 0.4 ma v cc = 3 v, f osc = 400 khz i sby3 2.5 ma v cc = 5 v, f osc = 8 mhz stop mode current drain i stop v cc 10 a v cc = 5 v 4 stop mode data retention voltage v stop v cc 2 v notes: 1. except for the current flowing in the pull-up mos transistors and output buffers. 2. the power supply current with the system in the reset state and no i/o currents flowing. test conditions system state reset state pin states reset , test .......... at the ground potential
563 3. the power supply current with the system timers operating and no i/o currents flowing. test conditions system state i/o: the same as in the reset state standby mode pin states reset ..................... at the v cc potential test ........................ at the ground potential d 0 to d 8 , r0 to r4, r8, and ra 1 ............. at the v cc potential 4. the power supply current with no i/o currents flowing. test conditions pin states reset ..................... at the v cc potential test ........................ at the ground potential d 0 to d 8 , r0 to r4, r8, and ra 1 ............. at the v cc potential 5. applies to the hd404358 series. 6. applies to the hd404358r series. table 25-23 standard pin i/o characteristics (hd404358 and hd404358r series) hd404354, hd404356, hd404358, hd40a4354, hd40a4356, hd40a4358: v cc = 2.7 to 6.0 v, gnd = 0 v, t a = 20 to 75 c hd407a4359: v cc = 2.7 to 5.5 v, gnd = 0 v, t a = 20 to 75 c hd404358r series: v cc = 2.5 to 5.5 v, gnd = 0 v, t a = 20 to 75 c unless specified otherwise. applicable rated value test item symbol pins min typ max unit conditions notes input high level voltage v ih hd404358 series d 0 to d 8 , r0, r1, r3, r4, r8, ra 1 hd404358r series d 0 to d 8 , r0 to r4, r8, ra 1 0.7 v cc v cc + 0.3 v input low level voltage v il hd404358 series d 0 to d 8 , r0, r1, r3, r4, r8, ra 1 hd404358r series d 0 to d 8 , r0 to r4, r8, ra 1 0.3 0.3 v cc v
564 table 25-23 standard pin i/o characteristics (hd404358 and hd404358r series) (cont) hd404354, hd404356, hd404358, hd40a4354, hd40a4356, hd40a4358: v cc = 2.7 to 6.0 v, gnd = 0 v, t a = 20 to 75 c hd407a4359: v cc = 2.7 to 5.5 v, gnd = 0 v, t a = 20 to 75 c hd404358r series: v cc = 2.5 to 5.5 v, gnd = 0 v, t a = 20 to 75 c unless specified otherwise. applicable rated value test item symbol pins min typ max unit conditions notes output high level voltage v oh hd404358 series d 0 to d 8 , r0, r1, r3, r4, r8 v cc 0.5 v i oh = 0.5 ma hd404358r series d 0 to d 8 , r0 to r4, r8 v cc 1.0 output low level voltage v ol hd404358 series d 0 to d 8 , r0, r1, r3, r4, r8 hd404358r series d 0 to d 4 , r3, r4 0.4 v i ol = 1.6 ma hd404358r series d 5 to d 8 , r0 to r2, r8 2.0 v i ol = 15 ma, v cc = 4.5 to 5.5 v i/o leakage current |i il | hd404358 series d 0 to d 8 , r0, r1, r3, r4, r8, ra 1 hd404358r series d 0 to d 8 , r0 to r4, r8, ra 1 1av in = 0 v to v cc 1 pull-up mos transistor current i pu hd404358 series d 0 to d 8 , r0, r1, r3, r4, r8 hd404358r series d 0 to d 8 , r0 to r4, r8 30 150 300 a v cc = 5 v, v in = 0 v note: 1. except for the current flowing in the output buffers.
565 table 25-24 medium voltage nmos open drain pin i/o characteristics (hd404358 series) hd404354, hd404356, hd404358, hd40a4354, hd40a4356, hd40a4358: v cc = 2.7 to 6.0 v, gnd = 0 v, t a = 20 to 75 c hd407a4359: v cc = 2.7 to 5.5 v, gnd = 0 v, t a = 20 to 75 c unless specified otherwise. applicable rated value test item symbol pins min typ max unit conditions notes input high level voltage v ih r2 0.7 v cc 12.0 v input low level voltage v il r2 0.3 0.3 v cc v output high level voltage v oh r2 11.5 v 500 k ? at 12 v output low v ol r2 0.4 v i ol = 0.4 ma level voltage 2.0 i ol = 15 ma, v cc = 4.5 v to 5.5 v i/o leakage current | i il |r2 20 a v in = 0 v to v cc 1 note: 1. except for the current flow in the output buffers.
566 (2) ac characteristics tables 25-25 and 25-26 list the ac characteristics of the hd404358 and hd404358r series microcomputers. table 25-25 ac characteristics (hd404358 and hd404358r series) hd404354, hd404356, hd404358, hd40a4354, hd40a4356, hd40a4358: v cc = 2.7 to 6.0 v, gnd = 0 v, t a = 20 to +75 c hd407a4369: v cc = 2.7 to 5.5 v, gnd = 0 v, t a = 20 to +75 c hd404354r, hd404356r, hd404358r, hd40a4354r, hd40a4356r, hd40a4358r, hd40c4354r, hd40c4356r, hd40c4358r, hd407a4359r, hd407c4359r: v cc = 2.5 to 5.5 v, gnd = 0 v, t a = 20 to +75 c unless specified otherwise. applicable rated value test item symbol pins min typ max unit conditions notes clock oscillator frequency (ceramic oscillator, crystal oscillator) f osc osc 1 , osc 2 0.4 0.4 0.4 4 4 4 5.0 8.5 8.5 mhz clock divisor = 4 clock divisor = 4 v cc = 4.0 to 5.5 v clock divisor = 4 v cc = 4.5 to 5.5 v 6 7 clock oscillator frequency (resistor oscillator) f osc osc 1 , osc 2 1.0 2.2 3.5 mhz clock divisor = 4 8 instruction cycle time (ceramic oscillator, crystal oscillator, external clock input) t cyc 0.8 0.47 1 1 10 10 s clock divisor = 4 clock divisor = 4 6, 7 instruction cycle time (resistor oscillator) t cyc 1.14 1.81 4.0 s clock divisor = 4 r f = 20 k ? 8 oscillator stabilization period (ceramic oscillator) t rc osc 1 , osc 2 7.5 ms 1 oscillator stabilization period (crystal oscillator) t rc osc 1 , osc 2 30 40 ms 1,11 1,12 oscillator stabilization period (resistor oscillator) t rc osc 1 , osc 2 0.5 ms 1, 8
567 table 25-25 ac characteristics (hd404358 and hd404358r series) (cont) hd404354, hd404356, hd404358, hd40a4354, hd40a4356, hd40a4358: v cc = 2.7 to 6.0 v, gnd = 0 v, t a = 20 to +75 c hd407a4369: v cc = 2.7 to 5.5 v, gnd = 0 v, t a = 20 to +75 c hd404354r, hd404356r, hd404358r, hd40a4354r, hd40a4356r, hd40a4358r, hd40c4354r, hd40c4356r, hd40c4358r, hd407a4359r, hd407c4359r: v cc = 2.5 to 5.5 v, gnd = 0 v, t a = 20 to +75 c unless specified otherwise. applicable rated value test item symbol pins min typ max unit conditions notes external clock high t cph osc 1 80 ns 2 level width 47 v cc = 4.0 to 5.5 v 2, 6 47 v cc = 4.5 to 5.5 v 2, 7 external clock low t cpl osc 1 80 ns 2 level width 47 v cc = 4.0 to 5.5 v 2, 6 47 v cc = 4.5 to 5.5 v 2, 7 external clock rise time t cpr osc 1 20 ns 2 15 v cc = 4.0 to 5.5 v 2, 6 15 v cc = 4.5 to 5.5 v 2, 7 external clock fall time t cpf osc 1 20 ns 2 15 v cc = 4.0 to 5.5 v 2, 6 15 v cc = 4.5 to 5.5 v 2, 7 int 0 , int 1 , and evnb high level width t ih int 0 , int 1 , evnb 2 t cyc 3 int 0 , int 1 , and evnb low level width t il int 0 , int 1 , evnb 2 t cyc 3 reset low level width t rstl reset 2 t cyc 4 stopc low level width t stpl stopc 1 t rc 5 reset rise time t rstr reset 20 ms 4 stopc rise time t stpr stopc 20 ms 5
568 table 25-25 ac characteristics (hd404358 and hd404358r series) (cont) hd404354, hd404356, hd404358, hd40a4354, hd40a4356, hd40a4358: v cc = 2.7 to 6.0 v, gnd = 0 v, t a = 20 to +75 c hd407a4369: v cc = 2.7 to 5.5 v, gnd = 0 v, t a = 20 to +75 c hd404354r, hd404356r, hd404358r, hd40a4354r, hd40a4356r, hd40a4358r, hd40c4354r, hd40c4356r, hd40c4358r, hd407a4359r, hd407c4359r: v cc = 2.5 to 5.5 v, gnd = 0 v, t a = 20 to +75 c unless specified otherwise. applicable rated value test item symbol pins min typ max unit conditions notes input capacitance c in all i/o pins other than test 15 pf f = 1 mhz, v in = 0v 11 all i/o pins other than test, r2 15 12 test 15 13 40 9 180 10 r2 30 12 notes: 1. there are three cases where the oscillator stabilization period applies: when power is first applied, the time between the point when v cc reaches min and the point the oscillator is stable. when stop mode is cleared, the time between the point when the reset input reaches the low level and the point the oscillator is stable. when stop mode is cleared, the time between the point when the stopc input reaches the low level and the point the oscillator is stable. to assure the time necessary to achieve stable oscillation at power on and when clearing stop mode, apply a low level to the reset or stopc input for at least t rc . since the oscillator stabilization period varies with the details of the mounted circuit, stray capacitances, and other factors, this value should be determined based on thorough consultations with the manufacturer of the ceramic oscillator used. 2. see figure 25-19. 3. see figure 25-20. 4. see figure 25-21. 5. see figure 25-22. 6. applies to the hd40a4354r, hd40a4356r, hd40a4358r, and hd407a4359r. 7. applies to the hd40a4354, hd40a4356, hd40a4358, and hd407a4359. 8. applies to the hd40c4354r, hd40c4356r, hd40c4358r, and hd407c4359r. 9. applies to the hd407a4359r and hd407c4359r. 10. applies to the hd407a4359.
569 11. applies to the hd404358r. 12. applies to the hd404358. 13. applies to the hd404354r, hd404356r, hd404358r, hd40a4354r, hd40a4356r, hd40a4358r, hd40c4354r, hd40c4356r, and hd40c4358r v cc 0.5v 0.5 v t cpr t cpf t cpl t cph 1/f cp osc 1 figure 25-19 external clock timing (hd404358 and hd404358r series) 0.8 v cc 0.2 v cc t ih t il int 0 , int 1 , evnb figure 25-20 interrupt timing (hd404358 and hd404358r series) 0.8 v cc 0.2 v cc t rstl t rstr reset figure 25-21 reset timing (hd404358 and hd404358r series) 0.8 v cc 0.2 v cc t stpl t stpr stopc figure 25-22 stopc timing (hd404358 and hd404358r series)
570 table 25-26 serial interface timing characteristics (hd404358 and hd404358r series) hd404354, hd404356, hd404358, hd40a4354, hd40a4356, hd40a4358: v cc = 2.7 to 6.0 v, gnd = 0 v, t a = 20 to 75 c hd407a4359: v cc = 2.7 to 5.5 v, gnd = 0 v, t a = 20 to 75 c hd404358r series: v cc = 2.5 to 5.5 v, gnd = 0 v, t a = 20 to +75 c, unless specified otherwise. when the transfer clock is output: applicable rated value test item symbol pins min typ max unit conditions notes transfer clock cycle time t scyc sck 1 t cyc with the load shown in figure 25-24 1 transfer clock high level width t sckh sck 0.4 t scyc with the load shown in figure 25-24 1 transfer clock low level width t sckl sck 0.4 t scyc with the load shown in figure 25-24 1 transfer clock rise time t sckr sck 80 ns with the load shown in figure 25-24 1 transfer clock fall time t sckf sck 80 ns with the load shown in figure 25-24 1 serial output data delay time t dso so 300 ns with the load shown in figure 25-24 1 serial input data setup time t ssi si 100 ns 1 serial input data hold time t hsi si 200 ns 1 note: 1. see figure 25-23.
571 table 25-26 serial interface timing characteristics (hd404358 series) (cont) hd404354, hd404356, hd404358, hd40a4354, hd40a4356, hd40a4358: v cc = 2.7 to 6.0 v, gnd = 0 v, t a = 20 to 75 c hd407a4359: v cc = 2.7 to 5.5 v, gnd = 0 v, t a = 20 to 75 c hd404358r series: v cc = 2.5 to 5.5 v, gnd = 0 v, t a = 20 to +75 c, unless specified otherwise. when the transfer clock is input: applicable rated value test item symbol pins min typ max unit conditions notes transfer clock cycle time t scyc sck 1 t cyc 1 transfer clock high level width t sckh sck 0.4 t scyc 1 transfer clock low level width t sckl sck 0.4 t scyc 1 transfer clock rise time t sckr sck 80 ns 1 transfer clock fall time t sckf sck 80 ns 1 serial output data delay time t dso so 300 ns with the load shown in figure 25-24 1 serial input data setup time t ssi si 100 ns 1 serial input data hold time t hsi si 200 ns 1 note: 1. see figure 25-23.
572 t scyc t sckf t sckl t sckh t dso t ssi t hsi 0.7 v cc 0.3 v cc v cc 0.5 v 0.4 v v cc 0.5 v (0.8 v cc ) * 0.4 v (0.2 v cc ) * si so sck note: * the values v cc 0.5 v and 0.4 v are the voltages for transfer clock output. the values 0.8 v cc and 0.2 v cc are the voltages for transfer clock input. t sckr figure 25-23 serial interface timing (hd404358 and hd404358r series) v cc r l = 2.6 k ? 1s2074 h or equivalent product r 12 k ? c 30 pf test point figure 25-24 timing load circuit
573 (3) a/d converter characteristics table 25-27 lists the characteristics of the hd404358 and hd404358r series a/d converter. table 25-27 a/d converter characteristics (hd404358 and hd404358r series) hd404354, hd404356, hd404358, hd40a4354, hd40a4356, hd40a4358: v cc = 2.7 to 6.0 v, gnd = 0 v, t a = 20 to 75 c hd407a4359: v cc = 2.7 to 5.5 v, gnd = 0 v, t a = 20 to 75 c hd404358r: v cc = 2.5 to 5.5 v, gnd = 0 v, t a = 20 to +75 c, unless specified otherwise. applicable rated value test item symbol pins min typ max unit conditions notes analog supply voltage av cc av cc v cc 0.3 v cc v cc + 0.3 v 1 analog input voltage av in an 0 to an 7 av ss av cc v current from av cc to av ss i ad 200 500 a v cc = av cc = 5.0 v 2 3 analog input capacitance ca in an 0 to an 7 30 pf resolution 8 bits number of inputs 0 8 channels absolute precision 2.0 2.0 lsb conversion time 34 67 tcyc input impedance an 0 to an 7 1 m ? notes: 1. connect to the v cc pin if the a/d converter is not used in the application. 2. applies to the hd404358. 3. applies to the hd404358r.
574 25.5 hd404339 series 25.5.1 absolute maximum ratings table 25-28 lists the absolute maximum ratings of the hd404339 series microcomputers. table 25-28 absolute maximum ratings (hd404339 series) item symbol rated value unit notes power supply voltage v cc 0.3 to +7.0 v programming voltage v pp 0.3 to +14.0 v 1 pin voltage v t 0.3 to v cc + 0.3 v 2 v cc 45 to v cc + 0.3 v 3 allowable total input current (current flowing in to the lsi) i 0 70 ma 4 allowable total output current (current flowing out from the lsi) i 0 150 ma 5 allowable input current i 0 4 ma 6, 7 (current flowing in to the lsi) 20 ma 6, 8 allowable output current i 0 4 ma 9, 10 (current flowing out from the lsi) 30 ma 10, 11 operating temperature t opr 20 to +75 c storage temperature t stg 55 to +125 c notes: 1. applies to the hd4074339 test (v pp ) pin. 2. applies to all standard pins. 3. applies to high voltage pins. 4. the allowable total input current is the sum of the currents flowing from all the i/o pins to ground at the same time. 5. the allowable total output current is the sum of the currents flowing from v cc to all the i/o pins at the same time. 6. the allowable input current is the maximum value of the currents flowing from each i/o pin to ground. 7. applies to r3 to r5. 8. applies to r0, r6, and r7. 9. applies to r0, and r3 0 to r7 2 . 10. the allowable output current is the maximum value of the currents flowing from v cc to each i/o pin. 11. applies to d 0 to d 13 , r1, r2, r8 and r9. use of this lsi at levels that exceed the absolute maximum ratings can permanently damage the lsi. also note that it is desirable to use this lsi within the conditions specified in the electrical characteristics section during normal operation. exceeding those conditions can cause the lsi to operate incorrectly and may adversely affect lsi reliability. all voltage values are referenced to ground.
575 25.5.2 electrical characteristics (1) dc characteristics tables 25-29 to 25-31 list the dc characteristics of the hd404339 series microcomputers. table 25-29 dc characteristics (hd404339 series) v cc = 4.0 to 5.5 v, gnd = 0 v, v disp = v cc 40 v to v cc , t a = 20 to 75 c unless specified otherwise. applicable rated value test item symbol pins min typ max unit conditions notes input high level voltage v ih reset , sck , si int 0 , int 1 , stopc , evnb 0.8 v cc v cc + 0.3 v osc 1 v cc 0.5 v cc + 0.3 input low level voltage v il reset , sck , si 0.3 0.2 v cc v int 0 , int 1 , stopc , evnb v cc 40 0.2 v cc osc 1 0.3 0.5 output high level voltage v oh sck , so, toc v cc 0.5 v i oh = 0.5 ma output low level voltage v ol sck , so, toc 0.4 v i ol = 0.4 ma i/o leakage current | i il | reset , sck , si, so, toc, osc 1 1av in = 0 v to v cc 1 int 0 , int 1 , stopc , evnb 20 v in = v cc 40 v to v cc active mode current drain i cc v cc 5.0 ma v cc = 5 v, f osc = 4 mhz 2, 5, 6 8.0 2, 5, 7
576 table 25-29 dc characteristics (hd404339 series) (cont) v cc = 4.0 to 5.5 v, gnd = 0 v, v disp = v cc 40 v to v cc , t a = 20 to 75 c unless specified otherwise. applicable rated value test item symbol pins min typ max unit conditions notes standby mode current drain i sby v cc 2.0 ma v cc = 5 v, f osc = 4 mhz 3, 5 subactive mode current drain i sub v cc 100 320 a v cc = 5 v, using a 32 khz oscillator 4, 6 4, 7 watch mode current drain i wtc v cc 20 a v cc = 5 v, using a 32 khz oscillator 4 stop mode i stop v cc 10 a x1 = gnd, 4, 6 current drain 20 x2 = open 4, 7 stop mode data retention voltage v stop v cc 2 v notes: 1. except for the current flowing in the pull-up mos transistors and output buffers. 2. the power supply current with the system in the reset state and no i/o currents flowing. test conditions system state reset state pin states reset , test .......... at the ground potential r0, r3 0 to r7 2 .......... at the v cc potential d 0 to d 13 , r1, r2, r8, r9, and ra 1 ....... at the v disp potential 3. the power supply current with the system timers operating and no i/o currents flowing. test conditions system state i/o: the same as in the reset state standby mode pin states reset ..................... at the v cc potentiall test ........................ at the ground potential r0, r3 0 to r7 2 .......... at the v cc potential d 0 to d 13 , r1, r2, r8, r9, and ra 1 ....... at the v disp potential
577 4. the power supply current with no i/o currents flowing. test conditions pin states r0, r3 0 to r7 2 .......... at the v cc potential d 0 to d 13 , r1, r2, r8, r9, and ra 1 ....... at the ground potential 5. the current drain during operation and in standby mode is proportional to f osc . therefore, the current ratings when f osc is x mhz can be calculated roughly as follows. maximum value (f osc = x mhz) = x/4 maximum value (f osc = 4 mhz) 6. applies to the hd404334, hd404336, hd404338, hd4043312, and hd404339. 7. applies to the hd4074339. table 25-30 standard pin i/o characteristics (hd404339 series) v cc = 4.0 to 5.5 v, gnd = 0 v, v disp = v cc 40 v to v cc , t a = 20 to 75 c unless specified otherwise. applicable rated value test item symbol pins min typ max unit conditions notes input high level voltage v ih r0, r3 0 to r7 2 0.7 v cc v cc + 0.3 v v input low level voltage v il r0, r3 0 to r7 2 0.3 0.3 v cc v output high level voltage v oh r0, r3 0 to r7 2 v cc 0.5 v i oh = 0.5 ma output low v ol r3 to r5 0.4 v i ol = 1.6 ma level voltage r0, r6 0 to r7 2 2.0 i ol = 10 ma i/o leakage current | i il | r0, r3 0 to r7 2 1av in = 0 v to v cc 1 pull-up mos transistor current i pu r0, r3 0 to r7 2 30 30 150 80 300 180 a v cc = 5 v, v in = 0 v 2 3 notes: 1. except for the current flowing in the output buffers. 2. applies to the hd404334, hd404336, hd404338, hd4043312, and hd404339. 3. applies to the hd4074339.
578 table 25-31 high voltage pin i/o characteristics (hd404339 series) v cc = 4.0 to 5.5 v, gnd = 0 v, v disp = v cc 40 v to v cc , t a = 20 to 75 c unless specified otherwise. applicable rated value test item symbol pins min typ max unit conditions notes input high level voltage v ih d 0 to d 13 , r1, r2, r8, r9, ra 1 0.7 v cc v cc + 0.3 v input low level voltage v il d 0 to d 13 , r1, r2, r8, r9, ra 1 v cc 40 0.3 v cc v output high level voltage v oh d 0 to d 13 , r1, r2, r8, r9, buzz v cc 3.0 v cc 2.0 v cc 1.0 v i oh = 15 ma i oh = 10 ma i oh = 4 ma output low level voltage v ol d 0 to d 13 , r1, r2, r8, v cc 37 v v disp = v cc 40 v 1 r9, buzz v cc 37 150 k ? at v cc 40 v 2 i/o leakage current |i il |d 0 to d 13 , r1, r2, r8, r9, ra 1 , buzz 20 a v in = v cc 40 v to v cc 3 pull-down resistor current i pd d 0 to d 13 , r1, r2, r8, r9, buzz 200 600 1000 a v disp = v cc 35 v, v in = v cc 1 notes: 1. applies to pins for which the pull-down resistor mask option was selected. 2. applies to pins for which the no pull-down resistor mask option was selected. 3. except for the current flow in the output buffers.
579 (2) ac characteristics tables 25-32 and 25-33 list the ac characteristics of the hd404339 series microcomputers. table 25-32 ac characteristics (hd404339 series) v cc = 4.0 to 5.5 v, gnd = 0 v, v disp = v cc 40 v to v cc , t a = 20 to 75 c unless specified otherwise. applicable rated value test item symbol pins min typ max unit conditions notes clock oscillator frequency f osc osc 1 , osc 2 0.4 4 4.5 mhz clock divisor = 4 1 x1, x2 32.768 khz instruction cycle t cyc 0.89 1 10 s time t subcyc 244.14 using a 32 khz oscillator, clock divisor = 8 122.07 using a 32 khz oscillator, clock divisor = 4 oscillator stabilization period (ceramic oscillator) t rc osc 1 , osc 2 7.5 ms 2 oscillator stabilization period (crystal oscillator) t rc osc 1 , osc 2 x1, x2 40 2 ms s 2 2 external clock high level width t cph osc 1 92 ns 3 external clock low level width t cpl osc 1 92 ns 3 external clock rise time t cpr osc 1 20 ns 3 external clock fall time t cpf osc 1 20 ns 3
580 table 25-32 ac characteristics (hd404339 series) (cont) v cc = 4.0 to 5.5 v, gnd = 0 v, v disp = v cc 40 v to v cc , t a = 20 to 75 c unless specified otherwise. applicable rated value test item symbol pins min typ max unit conditions notes int 0 , int 1 , and evnb high level width t ih int 0 , int 1 , evnb 2 t cyc / t subcyc 4 int 0 , int 1 , and evnb low level width t il int 0 , int 1 , evnb 2 t cyc / t subcyc 4 reset low level width t rstl reset 2 t cyc 5 stopc low level width t stpl stopc 1 t rc 6 reset rise time t rstr reset 20 ms 5 stopc rise time t stpr stopc 20 ms 6 input capacitance c in all input pins other than test 30 pf f = 1 mhz, v in = 0 v test 30 f = 1 mhz, 7 180 v in = 0 v 8 notes: 1. when a sub-system oscillator (a 32.768 khz crystal oscillator) is used, f osc must either be in the range 0.4 mhz f osc 1.0 mhz or be in the range 1.6 mhz f osc 4.5 mhz. furthermore, the ssr11 bit in the system clock selection register 1 (ssr1: $027) must be set to indicate which of those ranges f osc falls in. 2. there are three cases where the oscillator stabilization period applies: when power is first applied, the time between the point when v cc reaches 4.0 v and the point the oscillator is stable. when stop mode is cleared, the time between the point when the reset input reaches the low level and the point the oscillator is stable. when stop mode is cleared, the time between the point when the stopc input reaches the low level and the point the oscillator is stable. to assure the time necessary to achieve stable oscillation at power on and when clearing stop mode, apply a low level to the reset or stopc input for at least t rc . since the oscillator stabilization period varies with the details of the mounted circuit, stray capacitances, and other factors, this value should be determined based on thorough consultations with the manufacturer of the ceramic oscillator used. 3. see figure 25-25. 4. see figure 25-26. 5. see figure 25-27. 6. see figure 25-28.
581 7. applies to the hd404334, hd404336, hd404338, hd4043312, and hd404339. 8. applies to the hd4074339. v cc 0.5v 0.5 v t cpr t cpf t cpl t cph 1/f cp osc 1 figure 25-25 external clock timing (hd404339 series) 0.8 v cc 0.2 v cc t ih t il int 0 , int 1 , evnb figure 25-26 interrupt timing (hd404339 series) 0.8 v cc 0.2 v cc t rstl t rstr reset figure 25-27 reset timing (hd404339 series) 0.8 v cc 0.2 v cc t stpl t stpr stopc figure 25-28 stopc timing (hd404339 series)
582 table 25-33 serial interface timing characteristics (hd404339 series) v cc = 4.0 to 5.5 v, gnd = 0 v, v disp = v cc 40 v to v cc , t a = 20 to 75 c unless specified otherwise. applicable rated value test item symbol pins min typ max unit conditions notes transfer clock cycle time t scyc sck 1 t cyc with the load shown in figure 25-30 1 transfer clock high level width t sckh sck 0.4 t scyc with the load shown in figure 25-30 1 transfer clock low level width t sckl sck 0.4 t scyc with the load shown in figure 25-30 1 transfer clock rise time t sckr sck 80 ns with the load shown in figure 25-30 1 transfer clock fall time t sckf sck 80 ns with the load shown in figure 25-30 1 serial output data delay time t dso so 300 ns with the load shown in figure 25-30 1 serial input data setup time t ssi si 100 ns 1 serial input data hold time t hsi si 200 ns 1 note: see figure 25-29.
583 table 25-33 serial interface timing characteristics (hd404339 series) (cont) v cc = 4.0 to 5.5 v, gnd = 0 v, v disp = v cc 40 v to v cc , t a = 20 to 75 c unless specified otherwise. when the transfer clock is input: applicable rated value test item symbol pins min typ max unit conditions notes transfer clock cycle time t scyc sck 1 t cyc 1 transfer clock high level width t sckh sck 0.4 t scyc 1 transfer clock low level width t sckl sck 0.4 t scyc 1 transfer clock rise time t sckr sck 80 ns 1 transfer clock fall time t sckf sck 80 ns 1 serial output data delay time t dso so 300 ns with the load shown in figure 25-30 1 serial input data setup time t ssi si 100 ns 1 serial input data hold time t hsi si 200 ns 1 note: see figure 25-29.
584 t scyc t sckf t sckl t sckh t dso t ssi t hsi 0.8 v cc 0.2 v cc v cc 2.0 v 0.8 v v cc 2.0 v (0.8 v cc ) * 0.8 v (0.2 v cc ) * si so sck note: * the values v cc 2.0 v and 0.8 v are the voltages for transfer clock output. the values 0.8 v cc and 0.2 v cc are the voltages for transfer clock input. t sckr figure 25-29 serial interface timing (hd404339 series) v cc r l = 2.6 k ? 1s2074 h or equivalent product r 12 k ? c 30 pf test point figure 25-30 timing load circuit
585 (3) a/d converter characteristics table 25-34 lists the characteristics of the hd404339 series a/d converter. table 25-34 a/d converter characteristics (hd404339 series) v cc = 4.0 to 5.5 v, gnd = 0 v, v disp = v cc 40 v to v cc , t a = 20 to 75 c unless specified otherwise. applicable rated value test item symbol pins min typ max unit conditions notes analog supply voltage av cc av cc v cc 0.3 v cc v cc + 0.3 v 1 analog input voltage av in an 0 to an 11 av ss av cc v current from av cc to av ss i ad 200 a v cc = av cc = 5.0 v analog input capacitance ca in an 0 to an 11 30 pf resolution 8 8 8 bits number of inputs 0 12 channels absolute precision 2.0 lsb conversion time 34 67 t cyc input impedance an 0 to an 11 1 m ? note: connect to the v cc pin if the a/d converter is not used in the application.
586 25.6 hd404369 series 25.6.1 absolute maximum ratings table 25-35 lists the absolute maximum ratings of the hd404369 series microcomputers. table 25-35 absolute maximum ratings (hd404369 series) item symbol rated value unit notes power supply voltage v cc 0.3 to +7.0 v programming voltage v pp 0.3 to +14.0 v 1 pin voltage v t 0.3 to v cc + 0.3 v 2 0.3 to +15.0 v 3 allowable total input current (current flowing in to the lsi) i 0 105 ma 4 allowable total output current (current flowing out from the lsi) i 0 50 ma 5 allowable input current i 0 4 ma 6, 7 (current flowing in to the lsi) 30 ma 6, 8 allowable output current (current flowing out from the lsi) i 0 4 ma 7, 9 operating temperature t opr 20 to +75 c storage temperature t stg 55 to +125 c notes: 1. applies to the hd407a4369 test (v pp ) pin. 2. applies to all standard pins. 3. applies to the medium voltage pins. 4. the allowable total input current is the sum of the currents flowing from all the i/o pins to ground at the same time. 5. the allowable total output current is the sum of the currents flowing from v cc to all the i/o pins at the same time. 6. the allowable input current is the maximum value of the currents flowing from each i/o pin to ground. 7. applies to d 0 to d 13 , r0, and r3 to r9. 8. applies to r1 and r2. 9. the allowable output current is the maximum value of the currents flowing from v cc to each i/o pin. use of this lsi at levels that exceed the absolute maximum ratings can permanently damage the lsi. also note that it is desirable to use this lsi within the conditions specified in the electrical characteristics section during normal operation. exceeding those conditions can cause the lsi to operate incorrectly and may adversely affect lsi reliability. all voltage values are referenced to ground.
587 25.6.2 electrical characteristics (1) dc characteristics tables 25-36 to 25-38 list the dc characteristics of the hd404369 series microcomputers. table 25-36 dc characteristics (hd404369 series) hd404364, hd404368, hd4043612, hd404369, hd40a4364, hd40a4368, hd40a43612, hd40a4369: v cc = 2.7 to 6.0 v, gnd = 0 v, t a = 20 to 75 c hd407a4369: v cc = 2.7 to 5.5 v, gnd = 0 v, t a = 20 to 75 c, unless specified otherwise. applicable rated value test item symbol pins min typ max unit conditions notes input high level voltage v ih reset , stopc , int 0 , int 1 , sck , evnb 0.8 v cc v cc + 0.3 v si 0.7 v cc v cc + 0.3 osc1 v cc 0.5 v cc + 0.3 input low level voltage v il reset , stopc , int 0 , int 1 , sck , evnb 0.3 0.2 v cc v si 0.3 0.3 v cc osc 1 0.3 0.5 output high level voltage v oh sck , so, toc v cc 0.5 v i oh = 0.5 ma output low level voltage v ol sck, so, toc 0.4 v i ol = 0.4 ma i/o leakage current | i il | reset , stopc , int 0 , int 1 , sck , si, so, evnb, toc, osc 1 1av in = 0 v to v cc 1
588 table 25-36 dc characteristics (hd404369 series) (cont) hd404364, hd404368, hd4043612, hd404369, hd40a4364, hd40a4368, hd40a43612, hd40a4369: v cc = 2.7 to 6.0 v, gnd = 0 v, t a = 20 to 75 c hd407a4369: v cc = 2.7 to 5.5 v, gnd = 0 v, t a = 20 to 75 c, unless specified otherwise. applicable rated value test item symbol pins min typ max unit conditions notes active mode current drain i cc v cc 5.0 ma v cc = 5 v, f osc = 4 mhz 2, 5 standby mode current drain i sby v cc 2.0 ma v cc = 5 v, f osc = 4 mhz 3, 5 subactive mode current drain i sub v cc 100 a v cc = 5 v, using a 32 khz oscillator 4 watch mode current drain i wtc v cc 20 a v cc = 5 v, using a 32 khz oscillator 4 stop mode current drain i stop v cc 10 a v cc = 5 v, x1 = gnd, x2 = open 4 stop mode data retention voltage v stop v cc 2 v notes: 1. except for the current flowing in the pull-up mos transistors and output buffers. 2. the power supply current with the system in the reset state and no i/o currents flowing. test conditions system state reset state pin states reset , test .......... at the ground potential 3. the power supply current with the system timers operating and no i/o currents flowing. test conditions system state i/o: the same as in the reset state standby mode pin states reset ..................... at the v cc potential test ........................ at the ground potential d 0 to d 13 , r0 to r9, and ra 1 .................... at the v cc potential
589 4. the power supply current with no i/o currents flowing. test conditions pin states reset ..................... at the v cc potential test ........................ at the ground potential d 0 to d 13 , r0 to r9, and ra 1 .................... at the v cc potential 5. the current drain during operation and in standby mode is proportional to f osc . therefore, the current ratings when f osc is x mhz can be calculated roughly as follows. maximum value (f osc = x mhz) = x/4 maximum value (f osc = 4 mhz) table 25-37 standard pin i/o characteristics (hd404369 series) hd404364, hd404368, hd4043612, hd404369, hd40a4364, hd40a4368, hd40a43612, hd40a4369: v cc = 2.7 to 6.0 v, gnd = 0 v, t a = 20 to 75 c hd407a4369: v cc = 2.7 to 5.5 v, gnd = 0 v, t a = 20 to 75 c, unless specified otherwise. applicable rated value test item symbol pins min typ max unit conditions notes input high level voltage v ih d 0 to d 13 , r0, r3 to r9, ra 1 0.7 v cc v cc + 0.3 v input low level voltage v il d 0 to d 13 , r0, r3 to r9, ra 1 0.3 0.3 v cc v output high level voltage v oh d 0 to d 13 , r0, r3 to r9 v cc 0.5 v i oh = 0.5 ma output low level voltage v ol d 0 to d 13 , r0, r3 to r9 0.4 v i ol = 1.6 ma i/o leakage current |i il |d 0 to d 13 , r0, r3 to r9, ra 1 1av in = 0 v to v cc 1 pull-up mos transistor current i pu d 0 to d 13 , r0, r3 to r9 30 150 300 a v cc = 5 v, v in = 0 v note: except for the current flowing in the output buffers.
590 table 25-38 medium voltage nmos open drain pin i/o characteristics (hd404369 series) hd404364, hd404368, hd4043612, hd404369, hd40a4364, hd40a4368, hd40a43612, hd40a4369: v cc = 2.7 to 6.0 v, gnd = 0 v, t a = 20 to 75 c hd407a4369: v cc = 2.7 to 5.5 v, gnd = 0 v, t a = 20 to 75 c, unless specified otherwise. applicable rated value test item symbol pins min typ max unit conditions notes input high level voltage v ih r1, r2 0.7 v cc 12.0 v input low level voltage v il r1, r2 0.3 0.3 v cc v output high level voltage v oh r1, r2 11.5 v 500 k ? at 12 v output low v ol r1, r2 0.4 v i ol = 0.4 ma level voltage 2.0 i ol = 15 ma, v cc = 4.5 v to 5.5 v i/o leakage current | i il | r1, r2 20 a v in = 0 v to v cc 1 note: except for the current flow in the output buffers.
591 (2) ac characteristics tables 25-39 (1), 25-39 (2), and 25-40 list the ac characteristics of the hd404369 series microcomputers. table 25-39 (1) ac characteristics (hd404364, hd404368, hd4043612, and hd404369) v cc = 2.7 to 6.0 v, gnd = 0 v, t a = 20 to 75 c unless specified otherwise. applicable rated value test item symbol pins min typ max unit conditions notes clock oscillator frequency f osc osc 1 , osc 2 0.4 4 5.0 mhz clock divisor = 4 1 x1, x2 32.768 khz instruction cycle t cyc 0.8 1 10 s 1 time t subcyc 244.14 using a 32 khz oscillator, clock divisor = 8 122.07 using a 32 khz oscillator, clock divisor = 4 oscillator stabilization period (ceramic oscillator) t rc osc 1 , osc 2 7.5 ms 2 oscillator stabilization period t rc osc 1 , osc 2 40 ms 2 (crystal oscillator) x1, x2 2s 2 external clock high level width t cph osc 1 80 ns 3 external clock low level width t cpl osc 1 80 ns 3 external clock rise time t cpr osc 1 20 ns 3 external clock fall time t cpf osc 1 20 ns 3 int 0 , int 1 , and evnb high level width t ih int 0 , int 1 , evnb 2 t cyc / t subcyc 4
592 table 25-39 (1) ac characteristics (hd404364, hd404368, hd4043612, and hd404369) (cont) v cc = 2.7 to 6.0 v, gnd = 0 v, t a = 20 to 75 c unless specified otherwise. applicable rated value test item symbol pins min typ max unit conditions notes int 0 , int 1 , and evnb low level width t il int 0 , int 1 , evnb 2 t cyc / t subcyc 4 reset low level width t rstl reset 2 t cyc 5 stopc low level width t stpl stopc 1 t rc 6 reset rise time t rstr reset 20 ms 5 stopc rise time t stpr stopc 20 ms 6 input capacitance c in all i/o pins other than r1 and r2 15 pf f = 1 mhz, v in = 0 v r1, r2 30 f = 1 mhz, v in = 0 v notes: 1. when a sub-system oscillator (a 32.768 khz crystal oscillator) is used, f osc must either be in the range 0.4 mhz f osc 1.0 mhz or be in the range 1.6 mhz f osc 5.0 mhz. furthermore, the ssr11 bit in the system clock selection register 1 (ssr1: $027) must be set to indicate which of those ranges f osc falls in. 2. there are three cases where the oscillator stabilization period applies: when power is first applied, the time between the point when v cc reaches 2.7 v and the point the oscillator is stable. when stop mode is cleared, the time between the point when the reset input reaches the low level and the point the oscillator is stable. when stop mode is cleared, the time between the point when the stopc input reaches the low level and the point the oscillator is stable. to assure the time necessary to achieve stable oscillation at power on and when clearing stop mode, apply a low level to the reset or stopc input for at least t rc . since the oscillator stabilization period varies with the details of the mounted circuit, stray capacitances, and other factors, this value should be determined based on thorough consultations with the manufacturer of the ceramic oscillator used. 3. see figure 25-31. 4. see figure 25-32. 5. see figure 25-33. 6. see figure 25-34.
593 table 25-39 (2) ac characteristics (hd40a4364, hd40a4368, hd40a43612, hd40a4369, and hd407a4369) hd40a4364, hd40a4368, hd40a43612, hd40a4369: v cc = 2.7 to 6.0 v, gnd = 0 v, t a = 20 to 75 c hd407a4369: v cc = 2.7 to 5.5 v, gnd = 0 v, t a = 20 to 75 c, unless specified otherwise. applicable rated value test item symbol pins min typ max unit conditions notes clock oscillator f osc osc 1 , 0.4 4 5.0 mhz clock divisor = 4 1 frequency osc 2 0.4 4 8.5 clock divisor = 4, v cc = 4.5 to 5.5 v 2 x1, x2 32.768 khz instruction cycle t cyc 0.8 1 10 s 1 time 0.47 1 10 v cc = 4.5 to 5.5 v 2 t subcyc 244.14 using a 32 khz oscillator, clock divisor = 8 122.07 using a 32 khz oscillator, clock divisor = 4 oscillator stabilization period (ceramic oscillator) t rc osc 1 , osc 2 7.5 ms 3 oscillator stabilization period t rc osc 1 , osc 2 40 ms 3 (crystal oscillator) x1, x2 2s 3 external clock t cph osc 1 80 ns 4 high level width 47 v cc = 4.5 to 5.5 v 4 external clock t cpl osc 1 80 ns 4 low level width 47 v cc = 4.5 to 5.5 v 4
594 table 25-39 (2) ac characteristics (hd40a4364, hd40a4368, hd40a43612, hd40a4369, and hd407a4369) (cont) hd40a4364, hd40a4368, hd40a43612, hd40a4369: v cc = 2.7 to 6.0 v, gnd = 0 v, t a = 20 to 75 c hd407a4369: v cc = 2.7 to 5.5 v, gnd = 0 v, t a = 20 to 75 c, unless specified otherwise. applicable rated value test item symbol pins min typ max unit conditions notes external clock t cpr osc 1 20 ns 4 rise time 15 v cc = 4.5 to 5.5 v 4 external clock t cpf osc 1 20 ns 4 fall time 15 v cc = 4.5 to 5.5 v 4 int 0 , int 1 , and evnb high level width t ih int 0 , int 1 , evnb 2 t cyc / t subcyc 5 int 0 , int 1 , and evnb low level width t il int 0 , int 1 , evnb 2 t cyc / t subcyc 5 reset low level width t rstl reset 2 t cyc 6 stopc low level width t stpl stopc 1 t rc 7 reset rise time t rstr reset 20 ms 6 stopc rise time t stpr stopc 20 ms 7 input capacitance c in all i/o pins other than test, r1 and r2 15 pf f = 1 mhz, v in = 0 v test 15 f = 1 mhz, 8 180 v in = 0 v 9 r1, r2 30 f = 1 mhz, v in = 0 v notes: 1. when a sub-system oscillator (a 32.768 khz crystal oscillator) is used, f osc must either be in the range 0.4 mhz f osc 1.0 mhz or be in the range 1.6 mhz f osc 5.0 mhz. furthermore, the ssr11 bit in the system clock selection register 1 (ssr1: $027) must be set to indicate which of those ranges f osc falls in.
595 2. when a sub-system oscillator (a 32.768 khz crystal oscillator) is used, f osc must either be in the range 0.4 mhz f osc 1.0 mhz or be in the range 1.6 mhz f osc 8.5 mhz. furthermore, the ssr11 bit in the system clock selection register 1 (ssr1: $027) must be set to indicate which of those ranges f osc falls in. 3. there are three cases where the oscillator stabilization period applies: when power is first applied, the time between the point when v cc reaches 2.7 v and the point the oscillator is stable. when stop mode is cleared, the time between the point when the reset input reaches the low level and the point the oscillator is stable. when stop mode is cleared, the time between the point when the stopc input reaches the low level and the point the oscillator is stable. to assure the time necessary to achieve stable oscillation at power on and when clearing stop mode, apply a low level to the reset or stopc input for at least trc. since the oscillator stabilization period varies with the details of the mounted circuit, stray capacitances, and other factors, this value should be determined based on thorough consultations with the manufacturer of the ceramic oscillator used. 4. see figure 25-31. 5. see figure 25-32. 6. see figure 25-33. 7. see figure 25-34. 8. applies to the hd40a4364, hd40a4368, hd40a43612, and hd40a4369. 9. applies to the hd407a4369.
596 v cc 0.5v 0.5 v t cpr t cpf t cpl t cph 1/f cp osc 1 figure 25-31 external clock timing (hd404369 series) 0.8 v cc 0.2 v cc t ih t il int 0 , int 1 , evnb figure 25-32 interrupt timing (hd404369 series) 0.8 v cc 0.2 v cc t rstl t rstr reset figure 25-33 reset timing (hd404369 series) 0.8 v cc 0.2 v cc t stpl t stpr stopc figure 25-34 stopc timing (hd404369 series)
597 table 25-40 serial interface timing characteristics (hd404369 series) hd404364, hd404368, hd4043612, hd404369, hd40a4364, hd40a4368, hd40a43612, hd40a4369: v cc = 2.7 to 6.0 v, gnd = 0 v, t a = 20 to 75 c hd407a4369: v cc = 2.7 to 5.5 v, gnd = 0 v, t a = 20 to 75 c, unless specified otherwise. when the transfer clock is output: applicable rated value test item symbol pins min typ max unit conditions notes transfer clock cycle time t scyc sck 1 t cyc with the load shown in figure 25-36 1 transfer clock high level width t sckh sck 0.4 t scyc with the load shown in figure 25-36 1 transfer clock low level width t sckl sck 0.4 t scyc with the load shown in figure 25-36 1 transfer clock rise time t sckr sck 80 ns with the load shown in figure 25-36 1 transfer clock fall time t sckf sck 80 ns with the load shown in figure 25-36 1 serial output data delay time t dso so 300 ns with the load shown in figure 25-36 1 serial input data setup time t ssi si 100 ns 1 serial input data hold time t hsi si 200 ns 1 note: see figure 25-35.
598 table 25-40 serial interface timing characteristics (hd404369 series) (cont) hd404364, hd404368, hd4043612, hd404369, hd40a4364, hd40a4368, hd40a43612, hd40a4369: v cc = 2.7 to 6.0 v, gnd = 0 v, t a = 20 to 75 c hd407a4369: v cc = 2.7 to 5.5 v, gnd = 0 v, t a = 20 to 75 c, unless specified otherwise. when the transfer clock is input: applicable rated value test item symbol pins min typ max unit conditions notes transfer clock cycle time t scyc sck 1 t cyc 1 transfer clock high level width t sckh sck 0.4 t scyc 1 transfer clock low level width t sckl sck 0.4 t scyc 1 transfer clock rise time t sckr sck 80 ns 1 transfer clock fall time t sckf sck 80 ns 1 serial output data delay time t dso so 300 ns with the load shown in figure 25-36 1 serial input data setup time t ssi si 100 ns 1 serial input data hold time t hsi si 200 ns 1 note: see figure 25-35.
599 t scyc t sckf t sckl t sckh t dso t ssi t hsi 0.7 v cc 0.3 v cc v cc 0.5 v 0.4 v v cc 0.5 v (0.8 v cc ) * 0.4 v (0.2 v cc ) * si so sck n ote: * the values v cc 0.5 v and 0.4 v are the voltages for transfer clock output. the values 0.8 v cc and 0.2 v cc are the voltages for transfer clock input. t sckr figure 25-35 serial interface timing (hd404369 series) v cc r l = 2.6 k ? 1s2074 h or equivalent product r 12 k ? c 30 pf test point figure 25-36 timing load circuit
600 (3) a/d converter characteristics table 25-41 lists the characteristics of the hd404369 series a/d converter. table 25-41 a/d converter characteristics (hd404369 series) hd404364, hd404368, hd4043612, hd404369, hd40a4364, hd40a4368, hd40a43612, hd40a4369: v cc = 2.7 to 6.0 v, gnd = 0 v, t a = 20 to 75 c hd407a4369: v cc = 2.7 to 5.5 v, gnd = 0 v, t a = 20 to 75 c, unless specified otherwise. applicable rated value test item symbol pins min typ max unit conditions notes analog supply voltage av cc av cc v cc 0.3 v cc v cc + 0.3 v 1 analog input voltage av in an 0 to an 11 av ss av cc v current from av cc to av ss i ad 200 a v cc = av cc = 5.0 v analog input capacitance ca in an 0 to an 11 30 pf resolution 8 8 8 bits number of inputs 0 12 channels absolute precision 2.0 lsb conversion time 34 67 t cyc input impedance an 0 to an 11 1 m ? note: connect to the v cc pin if the a/d converter is not used in the application.
601 appendix a instruction set a.1 instruction set overview the hmcs400 cpu supports 101 instructions, which can be classified into the following ten classes. ? immediate instructions ? register to register instructions ? ram addressing instructions ? ram to register instructions ? arithmetic and logic instructions ? comparison instructions ? ram bit manipulation instructions ? rom addressing instructions ? i/o instructions ? control instructions tables a-1 (1) to a-1 (10) describe the functions of these instructions. the table below describes the operation symbols used in the instruction descriptions.
602 operation symbols a b move a to b a ? b exchange a and b x logical negation (not) symbol 1 high level 0 low level lsb low order bit msb high order bit nz a value other than 0 (not zero) nb no borrow occurred due to the operation ovf overflow due to an addition logical and symbol logical or symbol logical exclusive or inequality (not equal) comparison symbol (less than or equal) i, m, p expresses a single digit hexadecimal value ($0 to $f). d expresses a three digit hexadecimal value ($000 to $3ff). n expresses a two bit binary number. a expresses a six bit binary number. b expresses an eight bit binary number. u means p and d. y, x expresses either 0 or 1.
603 table a-1 (1) immediate instructions operation mnemonic operation code function status words/ cycles load a from immediate lai i 100011i 3 i 2 i 1 i 0 i a 1/1 load b from immediate lbi i 100000i 3 i 2 i 1 i 0 i b 1/1 load memory from immediate lmid i, d 0 d 9 1 d 8 1 d 7 0 d 6 1 d 5 0 d 4 i 3 d 3 i 2 d 2 i 1 d 1 i 0 d 0 i m 2/2 load memory from immediate, increment y lmiiy i 101001i3i2i1i0i m, y + 1 y nz 1/1 table a-1 (2) register to register instructions operation mnemonic operation code function status words/ cycles load a from b lab 0001001000b a 1/1 load b from a lba 0011001000a b 1/1 load a from w law 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w a 2/2 * load a from y lay 0010101111y a 1/1 load a from spx laspx 0001101000 spx a 1/1 load a from spy laspy 0001011000 spy a 1/1 load a from mr lamr m 100111m 3 m 2 m 1 m 0 mr (m) a 1/1 exchange mr and a xmra m 101111m 3 m 2 m 1 m 0 mr (m) ? a 1/1 note: * the law and lwa instructions require an operand ($000) in the second word. however, there is no need to explicitly code this word since the assembler will provide it automatically.
604 table a-1 (3) ram addressing instructions operation mnemonic operation code function status words/ cycles load w from immediate lwi i 00111100i1i0i w 1/1 load x from immediate lxi i 100010i3i2i1i0i x 1/1 load y from immediate lyi i 100001i3i2i1i0i y 1/1 load w from a lwa 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 a w 2/2 * load x from a lxa 0011101000a x 1/1 load y from a lya 0011011000a y 1/1 increment y iy 0001011100y + 1 y nz 1/1 decrement y dy 0011011111y 1 y nb 1/1 add a to y ayy 0001010100y + a y ovf 1/1 subtract a from y syy 0011010100y a y nb 1/1 exchange x and spx xspx 0000000001x ? spx 1/1 exchange y and spy xspy 0000000010y ? spy 1/1 exchange x and spx, y and spy xspxy 0000000011x ? spx, y ? spy 1/1 note: * the law and lwa instructions require an operand ($000) in the second word. however, there is no need to explicitly code this word since the assembler will provide it automatically.
605 table a-1 (4) ram to register instructions operation mnemonic operation code function status words/ cycles load a from memory lam(xy) 00100100yxm a (x spx, y spy) 1/1 load a from memory lamd d 0 d 9 1 d 8 1 d 7 0 d 6 0 d 5 1 d 4 0 d 3 0 d 2 0 d 1 0 d 0 m a 2/2 load b from memory lbm(xy) 00010000yxm b (x spx, y spy) 1/1 load memory from a lma(xy) 00100101yxa m (x spx, y spy) 1/1 load memory from a lmad d 0 d 9 1 d 8 1 d 7 0 d 6 0 d 5 1 d 4 0 d 3 1 d 2 0 d 1 0 d 0 a m 2/2 load memory from a, increment y lmaiy(x) 000101000xa m y + 1 y (x spx) nz 1/1 load memory from a, decrement y lmady(x) 001101000xa m y ?1 y (x spx) nb 1/1 exchange memory and a xma(xy) 00100000yxm a (x spx, y spy) 1/1 exchange memory and a xmad d 0 d9 1 d8 1 d7 0 d6 0 d5 0 d4 0 d3 0 d2 0 d1 0 d0 m a 2/2 exchange memory and b xmb(xy) 00110000yxm b (x spx, y spy) 1/1 note: the terms (xy) and (x) in the mnemonics are interpreted as follows. mnemonics with (xy) represent four mnemonics. the table below uses lam(xy) as an example. the assembler generates the bits y and x shown in the table below for these instructions. mnemonic y x function lam 0 0 lamx 0 1 x ? spx lamy 1 0 y ? spy lamxy 1 1 x ? spx, y ? spy mnemonics with (x) represent two mnemonics. the table below uses lmaiy(x) as an example. the assembler generates the bit x shown in the table below for these instructions. mnemonic x function lmaiy 0 lmaiyx 1 x ? spx
606 table a-1 (5) arithmetic and logic instructions operation mnemonic operation code function status words/ cycles add immediate to a ai i 101000i 3 i 2 i 1 i 0 a + i a ovf 1/1 increment b ib 0001001100b + 1 b nz 1/1 decrement b db 0011001111b 1 b nb 1/1 decimal adjust for addition daa 0010100110 1/1 decimal adjust for subtraction das 0010101010 1/1 negate a nega 0001100000 a + 1 a 1/1 complement b comb 0101000000 b b 1/1 rotate right a with carry rotr 0010100000 1/1 rotate left a with carry rotl 0010100001 1/1 set carry sec 00111011111 ca 1/1 reset carry rec 00111011000 ca 1/1 test carry tc 0001101111 ca 1/1 add a to memory am 0000001000m + a a ovf 1/1 add a to memory amd d 0 d 9 1 d 8 0 d 7 0 d 6 0 d 5 0 d 4 1 d 3 0 d 2 0 d 1 0 d 0 m + a a ovf 2/2 add a to memory with carry amc 0000011000m + a + ca a ovf ca ovf 1/1 add a to memory with carry amcd d 0 d 9 1 d 8 0 d 7 0 d 6 0 d 5 1 d 4 1 d 3 0 d 2 0 d 1 0 d 0 m + a + ca a ovf ca ovf 2/2 subtract a from memory with carry smc 0010011000m a ca a nb ca nb 1/1 subtract a from memory with carry smcd d 0 d 9 1 d 8 1 d 7 0 d 6 0 d 5 1 d 4 1 d 3 0 d 2 0 d 1 0 d 0 m ?a ca a nb ca nb 2/2 or a and b or 0101000100a b a 1/1 and memory with a anm 0010011100a m anz 1/1 and memory with a anmd d 0 d 9 1 d 8 1 d 7 0 d 6 0 d 5 1 d 4 1 d 3 1 d 2 0 d 1 0 d 0 a m anz 2/2 or memory with a orm 0000001100a m anz 1/1 or memory with a ormd d 0 d 9 1 d 8 0 d 7 0 d 6 0 d 5 0 d 4 1 d 3 1 d 2 0 d 1 0 d 0 a m anz 2/2 eor memory with a eorm 0000011100a m anz 1/1 eor memory with a eormd d 0 d 9 1 d 8 0 d 7 0 d 6 0 d 5 1 d 4 1 d 3 1 d 2 0 d 1 0 d 0 a m anz 2/2
607 table a-1 (6) comparison instructions operation mnemonic operation code function status words/ cycles immediate not equal to memory inem i 000010i3i2i1i0i m nz 1/1 immediate not equal to memory inemd i, d 0 d 9 1 d 8 0 d 7 0 d 6 1 d 5 0 d 4 i 3 d 3 i 2 d 2 i 1 d 1 i 0 d 0 i m nz 2/2 a not equal to memory anem 0000000100a m nz 1/1 a not equal to memory anemd d 0 d 9 1 d 8 0 d 7 0 d 6 0 d 5 0 d 4 0 d 3 1 d 2 0 d 1 0 d 0 a m nz 2/2 b not equal to memory bnem 0001000100b m nz 1/1 y not equal to immediate ynei i 000111i 3 i 2 i 1 i 0 y i nz 1/1 immediate less than or equal to memory ilem i 000011i 3 i 2 i 1 i 0 i m nb 1/1 immediate less than or equal to memory ilemd i, d 0 d 9 1 d 8 0 d 7 0 d 6 1 d 5 1 d 4 i 3 d 3 i 2 d 2 i 1 d 1 i 0 d 0 i m nb 2/2 a less than or equal to memory alem 0000010100a m nb 1/1 a less than or equal to memory alemd d 0 d 9 1 d 8 0 d 7 0 d 6 0 d 5 1 d 4 0 d 3 1 d 2 0 d 1 0 d 0 a m nb 2/2 b less than or equal to memory blem 0011000100b m nb 1/1 a less than or equal to immediate alei i 101011i 3 i 2 i 1 i 0 a i nb 1/1 table a-1 (7) ram bit manipulation instructions operation mnemonic operation code function status words/ cycles set memory bit sem n 00100001n 1 n 0 1 m (n) 1/1 set memory bit semd n, d 0 d 9 1 d 8 1 d 7 0 d 6 0 d 5 0 d 4 0 d 3 1 d 2 n 1 d 1 n 0 d 0 1 m (n) 2/2 reset memory bit rem n 00100010n 1 n 0 0 m (n) 1/1 reset memory bit remd n, d 0 d 9 1 d 8 1 d 7 0 d 6 0 d 5 0 d 4 1 d 3 0 d 2 n 1 d 1 n 0 d 0 0 m (n) 2/2 test memory bit tm n 00100011n 1 n 0 m (n) 1/1 test memory bit tmd n, d 0 d 9 1 d 8 1 d 7 0 d 6 0 d 5 0 d 4 1 d 3 1 d 2 n 1 d 1 n 0 d 0 m (n) 2/2
608 table a-1 (8) rom addressing instructions operation mnemonic operation code function status words/ cycles branch on status 1 br b 1 1 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 1 1/1 long branch on status 1 brl u 0 d 9 1 d 8 0 d 7 1 d 6 1 d 5 1 d 4 p 3 d 3 p 2 d 2 p 1 d 1 p 0 d 0 1 2/2 long jump unconditionally jmpl u 0 d 9 1 d 8 0 d 7 1 d 6 0 d 5 1 d 4 p 3 d 3 p 2 d 2 p 1 d 1 p 0 d 0 2/2 subroutine jump on status 1 cal a 0111a 5 a 4 a 3 a 2 a 1 a 0 1 1/2 long subroutine jump on status 1 call u 0 d 9 1 d 8 0 d 7 1 d 6 1 d 5 0 d 4 p 3 d 3 p 2 d 2 p 1 d 1 p 0 d 0 1 2/2 table branch tbr p 001011p 3 p 2 p 1 p 0 1/1 return from subroutine rtn 0000010000 1/3 return from interrupt rtni 00000100011 ie, ca restored st 1/3 table a-1 (9) i/o instructions operation mnemonic operation code function status words/ cycles set discrete i/o latch sed 00111001001 d (y) 1/1 set discrete i/o latch direct sedd m 101110m 3 m 2 m 1 m 0 1 d (m) 1/1 reset discrete i/o latch red 00011001000 d (y) 1/1 reset discrete i/o latch direct redd m 100110m 3 m 2 m 1 m 0 0 d (m) 1/1 test discrete i/o latch td 0011100000 d (y) 1/1 test discrete i/o latch direct tdd m 101010m 3 m 2 m 1 m 0 d (m) 1/1 load a from r-port register lar m 100101m 3 m 2 m 1 m 0 r (m) a 1/1 load b from r-port register lbr m 100100m 3 m 2 m 1 m 0 r (m) b 1/1 load r-port register from a lra m 101101m 3 m 2 m 1 m 0 a r (m) 1/1 load r-port register from b lrb m 101100m 3 m 2 m 1 m 0 b r (m) 1/1 pattern generation p p 011011p 3 p 2 p 1 p 0 1/2 table a-1 (10) control instructions operation mnemonic operation code function status words/ cycles no operation nop 0000000000 1/1 start serial sts 0101001000 1/1 standby mode/watch mode * sby 0101001100 1/1 stop mode/watch mode stop 0101001101 1/1 note: * only on the transition from subactive mode.
609 a.2 operation code map table a-2 opcode map r8 l h r9 0 1 2 3 4 5 6 7 8 9 a b c d e f 0 1 2 3 4 5 6 7 8 9 a b c d e f 0 0 1 one word/two cycle instructions one word/three cycle instructions ram direct addressing instructions (two word/ two cycles) two word/two cycle instructions 0123456789abcdef nop xspx xspy xspxy anem am orm lbm(xy) bnem lab ib lmaiy(x) ayy laspy iy rtn rtni alem amc eorm nega red laspx tc inem i(4) inem i(4) ynei i(4) lma(xy) lam(xy) sem n(2) lma(xy) rem n(2) smc tm n(2) anm rotr daa das lay rotl db dy sec lba lya rec lxa blem syy sed xmb(xy) lmady(x) td lwi i(2) tbr p(4) lbi i(4) lyi i(4) lxi i(4) lai i(4) lbr m(4) lar m(4) redd m(4) lamr m(4) ai i(4) lmiy i(4) tdd m(4) alei i(4) lrb m(4) lra m(4) sedd m(4) xmra m(4)
610 table a-2 opcode map (cont) r8 l h r9 0 1 2 3 4 5 6 7 8 9 a b c d e f 0 1 2 3 4 5 6 7 8 9 a b c d e f 1 0 1 0123456789abcdef law anemd amd ormd lwa alemd amcd eormd comb or sts sby stop inemd i(4) inemd i(4) jmpl p(4) call p(4) brl p(4) xmad lamd semd n(2) lmad remd n(2) smcd tmd n(2) anmd lmid i(4) cal a(6) br b(8) p p(4) one word/two cycle instructions one word/three cycle instructions ram direct addressing instructions (two word/ two cycles) two word/two cycle instructions
611 appendix b registers and flags b.1 i/o registers (1) no indication: registers and bits common to all products in the hmcs43xx family. : registers and bits supported by the hd404318, hd404358, and hd404358r series. : registers and bits supported by the hd404339 and hd404369 series. : registers and bits that are unused in all products in the hmcs43xx family. ram bit address register symbol bit 3 bit 2 bit 1 bit 0 module/function $000 interrupt control bit area im0 if0 rsp ie interrupt control $001 imta ifta im1 if1 $002 imtc iftc imtb iftb $003 ims ifs imad ifad $004 port mode register a pmra pmra3 pmra2 pmra1 pmra0 d 3 and r 0 port pin function switching $005 serial mode register smr smr3 smr2 smr1 smr0 serial interface $006 serial data register l srl sr3 sr2 sr1 sr0 $007 serial data register u sru sr7 sr6 sr5 sr4 $008 timer mode register a tma tma3 tma2 tma1 tma0 timer a $009 timer mode register b1 tmb1 tmb13 tmb12 tmb11 tmb10 timer b $00a timer read register bl/ trbl trbl3 trbl2 trbl1 trbl0 timer write register bl twbl twbl3 twbl2 twbl1 twbl0 $00b timer read register bu/ trbu trbu3 trbu2 trbu1 trbu0 timer write register bu twbu twbu3 twbu2 twbu1 twbu0 $00c miscellaneous register mis mis3 mis2 mis1 mis0 system control and other functions $00d timer mode register c tmc tmc3 tmc2 tmc1 tmc0 timer c $00e timer read register cl/ trcl trcl3 trcl2 trcl1 trcl0 timer write register cl twcl twcl3 twcl2 twcl1 twcl0 $00f timer read register cu/ trcu trcu3 trcu2 trcu1 trcu0 timer write register cu twcu twcu3 twcu2 twcu1 twcu0 $010 to $015 $016 a/d channel register acr acr3 * 1 acr2 * 1 acr1 * 1 acr0 * 1 a/d converter $017 a/d data register l adrl adrl3 adrl2 adrl1 adrl0 $018 a/d data register u adru adru3 adru2 adru1 adru0 $019 a/d mode register 1 amr1 amr13 amr12 amr11 amr10 * 2 $01a a/d mode register 2 amr2 amr22 amr21 amr20 notes: 1. specification of a channel number not supported by the particular product is illegal. 2. amr10 is unused only in the hd404394 series.
612 b.1 i/o registers (1) (cont) no indication: registers and bits common to all products in the hmcs43xx family. : registers and bits supported by the hd404318, hd404358, and hd404358r series. : registers and bits supported by the hd404339 and hd404369 series. : registers and bits that are unused in all products in the hmcs43xx family. ram bit address register symbol bit 3 bit 2 bit 1 bit 0 module/function $01b to $01f $020 $021 register flag area dton rame adsf iaof wdon icef lson icsf flags used by peripheral modules $022 and other functions $023 $024 port mode register b pmrb pmrb3 pmrb2 pmrb1 pmrb0 d port pin function switching $025 port mode register c pmrc pmrc3 pmrc2 pmrc1 pmrc0 serial interface $026 timer mode register b2 tmb2 tmb22 tmb21 tmb20 timer b $027 system clock selection register 1 ssr1 ssr13 ssr12 ssr11 clock oscillator $028 system clock selection register 2 ssr2 ssr21 ssr20 $029 to $02b $02c to $039 data control register dcd0 to dcd3, dcr0 to dcr9 the set of valid bits differs between products. see sections 7 to 12, ?/o ports? for details. port i/o control $03a to $03f
613 b.2 i/o registers (2) $004?ort mode register a pmra d0 and r0 ports bit initial value read/write 3 pmra3 * 0 w 0 pmra0 0 w 2 pmra2 0 w 1 pmra1 0 w 0 1 r0 3 /toc pin function switch 0 1 r0 1 /si pin function switch 0 1 r0 2 /so pin function switch 0 1 d 3 /buzz pin function switch * r0 3 i/o pin toc output pin r0 1 i/o pin si input pin r0 2 i/o pin so output pin d 3 i/o pin buzz output pin note: * applies to the hd404318, hd404358, hd404358r, hd404339, and hd404369 series. the pmra3 bit is unused in the hd404344r and hd404394 series.
614 $005?erial mode register smr serial interface smr2 smr1 smr0 sck pin clock source prescaler divisor * 0 1 0 1 0 1 0 1 0 1 0 1 0 1 pss pss pss pss pss pss system clock external clock per /2048 per /512 per /128 per /32 per /8 per /2 per output output output output output output output input bit initial value read/write 3 smr3 0 w 0 smr0 0 w 2 smr2 0 w 1 smr1 0 w 0 1 r0 0 /sck pin function switch r0 0 i/o pin sck i/o pin transfer clock selection note: * the transfer clock divisor is determined by the combination of the prescaler divisor specified by the smr2 to smr0 bits and the prescaler output divisor (2 or 4) specified by the pmrc pmrc0 bit.
615 $006?erial data register l $007?erial data register u srl sru serial interface sru bit initial value read/write 7 sr7 undefined r/w 6 sr6 undefined r/w 5 sr5 undefined r/w 4 sr4 undefined r/w 3 sr3 undefined r/w 0 sr0 undefined r/w 2 sr2 undefined r/w 1 sr1 undefined r/w srl
616 $008?imer mode register a tma timer a hd404318/hd404358/hd404358r series bit initial value read/write 3 0 tma0 0 w 2 tma2 0 w 1 tma1 0 w 0 1 0 1 2048 t cyc 1024 t cyc 512 t cyc 128 t cyc 32 t cyc 8 t cyc 4 t cyc 2 t cyc 0 1 0 1 0 1 0 1 0 1 tma2 tma1 tma0 note: t cyc = f osc /4 unused timer a clock selection input clock period
617 $008?imer mode register a tma timer a hd404339/hd404369 series tma3 tma2 tma1 tma0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 * 1 pss pss pss pss pss pss pss pss psw psw psw psw 2048 t cyc * 1 1024 t cyc 512 t cyc 128 t cyc 32 t cyc 8 t cyc 4 t cyc 2 t cyc 32 t wcyc * 2 16 t wcyc 8 t wcyc 2 t wcyc 1/2 t wcyc unused psw and tca clear bit initial value read/write 3 tma3 0 w 0 tma0 0 w 2 tma2 0 w 1 tma1 0 w timer a clock selection prescaler input clock period mode free-running timer mode clock time base mode 0 1 0 1 0 1 0 1 0 1 0 0 1 notes: 1. 2. t cyc = f osc /4, f osc /8, f osc /16 or f osc /32 t wcyc = f x /8 * don t care
618 $009?imer mode register b1 tmb1 timer b bit initial value read/write 3 tmb13 0 w 0 tmb10 0 w 2 tmb12 0 w 1 tmb11 0 w 0 1 0 1 2048 t cyc 512 t cyc 128 t cyc 32 t cyc 8 t cyc 4 t cyc 2 t cyc evnb (external event input pin) 0 1 0 1 0 1 0 1 0 1 tmb12 tmb11 tmb10 timer b clock selection 0 1 timer b function selection free-running timer reload timer input clock source note: set port mode register b as shown below when either t cyc = f osc /4 or external event input is used as the timer b clock. hd404344r/hd404394 series: set the pmrb0 bit to 1. hd404318/hd404358/hd404358r/hd404339/hd404369 series: set the pmrb2 bit to 1.
619 $00a?imer read register bl $00b?imer read register bu trbl trbu timer b bit initial value read/write 3 trbu3 undefined r 0 trbu0 undefined r 2 trbu2 undefined r 1 trbu1 undefined r trbu bit initial value read/write 3 trbl3 undefined r 0 trbl0 undefined r 2 trbl2 undefined r 1 trbl1 undefined r trbl $00a?imer write register bl $00b?imer write register bu twbl twbu timer b bit initial value read/write 3 twbu3 undefined w 0 twbu0 undefined w 2 twbu2 undefined w 1 twbu1 undefined w twbu bit initial value read/write 3 twbl3 0 w 0 twbl0 0 w 2 twbl2 0 w 1 twbl1 0 w twbl
620 $00c?iscellaneous register mis system control mis1 0 1 0 1 0 1 0.24414 ms 15.625 ms 125 ms 0.12207 (0.24414) ms * 2 7.8125 ms 62.5 ms 0 1 bit initial value read/write 3 mis3 0 w 0 mis0 * 1 0 w 2 mis2 0 w 1 mis1 * 1 0 w notes: 1. 2. applies to the hd404339 and hd404369 series. unused in the hd404318, hd404358, hd404358r, hd404344r, and hd404394 series. values in parentheses are direct transition times. r0 2 /so pin output buffer control 0 1 pull-up mos transistor control interrupt frame period and oscillator stabilization period * 1 interrupt frame period oscillator stabilization period oscillator circuit conditions external clock ceramic oscillator crystal oscillator unused pmos transistor active (cmos output) pmos transistor off (nmos open drain output) all pull-up mos transistors off pull-up mos transistors active mis0
621 $00d?imer mode register c tmc timer c bit initial value read/write 3 tmc3 0 w 0 tmc0 0 w 2 tmc2 0 w 1 tmc1 0 w 0 1 0 1 2048 t cyc 1024 t cyc 512 t cyc 128 t cyc 32 t cyc 8 t cyc 4 t cyc 2 t cyc 0 1 0 1 0 1 0 1 0 1 tmc2 tmc1 tmc0 timer c clock selection 0 1 timer c function selection free-running timer reload timer input clock cource
622 $00e?imer read register cl $00f?imer read register cu trcl trcu timer c bit initial value read/write 3 trcu3 undefined r 0 trcu0 undefined r 2 trcu2 undefined r 1 trcu1 undefined r trcu bit initial value read/write 3 trcl3 undefined r 0 trcl0 undefined r 2 trcl2 undefined r 1 trcl1 undefined r trcl $00e?imer write register cl $00f?imer write register cu twcl twcu timer c bit initial value read/write 3 twcu3 undefined w 0 twcu0 undefined w 2 twcu2 undefined w 1 twcu1 undefined w twcu bit initial value read/write 3 twcl3 0 w 0 twcl0 0 w 2 twcl2 0 w 1 twcl1 0 w twcl
623 $016?/d channel register acr a/d converter acr3 acr2 acr1 acr0 hd404344r hd404394 hd404318/ hd404358/ hd404358r hd404339/ hd404369 0 1 0 1 0 1 0 1 0 1 0 1 * 0 1 0 1 0 1 0 1 0 1 0 1 * an 0 an 1 an 2 an 3 an 1 an 2 an 3 an 0 an 1 an 2 an 3 an 4 an 5 an 6 an 7 an 0 an 1 an 2 an 3 an 4 an 5 an 6 an 7 an 8 an 9 an 10 an 11 * don't care bit initial value read/write 0 acr0 0 w 2 acr2 0 w 1 acr1 0 w 3 acr3 0 w analog input channel selection input channel : unused note:
624 $017?/d data register l $018?/d data register u adrl adru a/d converter bit initial value read/write adrl 0 adrl0 0 r 2 adrl2 0 r 1 adrl1 0 r 3 adrl3 0 r a/d converted data (lower 4 bits) bit initial value read/write adru 0 adru0 0 r 2 adru2 0 r 1 adru1 0 r 3 adru3 1 r a/d converted data (upper 4 bits)
625 $019?/d mode register amr1 a/d converter bit initial value read/write 3 amr13 0 w 0 amr10 * 0 w 2 amr12 0 w 1 amr11 0 w 0 1 r3 2 /an 2 pin function switch 0 1 r3 1 /an 1 pin function switch 0 1 r3 0 /an 0 pin function switch * 0 1 r3 3 /an 3 pin function switch r3 2 i/o pin an 2 input pin r3 1 i/o pin an 1 input pin r3 0 i/o pin an 0 input pin r3 3 i/o pin an 3 input pin note: * applies to the hd404344r, hd404318, hd404358, hd404358r, hd404339, and hd404369 series. the amr10 bit is unused in the hd404394 series.
626 $01a?/d mode register 2 amr2 a/d converter bit initial value read/write 3 0 amr20 0 w 2 amr22 * 2 0 w 1 amr21 * 1 0 w 0 1 r5 0 /an 8 to r5 3 /an 11 pin function switch * 2 0 1 r4 0 /an 4 to r4 3 /an 7 pin function switch * 1 0 1 a/d conversion time r5 0 to r5 3 i/o pins an 8 to an 11 input pins r4 0 to r4 3 i/o pins an 4 to an 7 input pins 34 t cyc 67 t cyc unused notes: 1. 2. applies to the hd404318, hd404358, hd404358r, hd404339, and hd404369 series. the amr21 bit is unused in the hd404344r and hd404394 series. applies to the hd404339 and hd404369 series. the amr22 bit is unused in the hd404344r, hd404394, hd404318, hd404358, and hd404358r series.
627 $024?ort mode register b pmrb d port function switching hd404344r/hd404394 series bit initial value read/write 3 pmrb3 0 w 0 pmrb0 0 w 2 1 0 1 d 0 /int 0 /evnb pin function switch 0 1 d 4 /stopc pin function switch d 0 i/o pin int 0 /evnb input pin d 4 i/o pin stopc input pin unused
628 $024?ort mode register b pmrb d port function switching hd404318/hd404358/hd404358r/hd404339/hd404369 series bit initial value read/write 3 pmrb3 0 w 0 pmrb0 0 w 2 pmrb2 0 w 1 pmrb1 0 w 0 1 d 2 /evnb pin function switch 0 1 d 1 /int 1 pin function switch 0 1 d 0 /int 0 pin function switch 0 1 d 4 /stopc pin function switch d 2 i/o pin evnb input pin d 1 i/o pin int 1 input pin d 0 i/o pin int 0 input pin d 4 i/o pin stopc input pin
629 $025?ort mode register c pmrc serial interface pmrc3 pmrc2 alarm frequency 0 1 0 1 0 1 per /2048 per /1024 per /512 per /256 per : the built-in peripheral module operating clock bit initial value read/write 3 pmrc3 * 0 w 0 pmrc0 0 w 2 pmrc2 * 0 w 1 pmrc1 0 w alarm frequency selection 0 1 idle time high/low output control 0 1 transfer clock divisor selection the so pin outputs a low level during idle the so pin outputs a high level during idle pss output divided by 2 pss output divided by 4 note: * applies to the hd404318, hd404358, hd404358r, hd404339, and hd404369 series. the pmrc3 and pmrc2 bits are unused in the hd404344r and hd404394 series.
630 $026?imer mode register b2 tmb2 timer b bit initial value read/write 3 0 tmb20 0 r/w 2 tmb22 * 0 r/w 1 tmb21 0 r/w 0 1 0 1 0 1 tmb21 tmb20 0 1 input capture setting * free-running/reload timer input capture timer evnb pin edge detection selection evnb pin edge detection no detection falling edge detection rising edge detection falling/rising edge pair detection note: * applies to the hd404318, hd404358, hd404358r, hd404339, and hd404369 series. the tmb22 bit is unused in the hd404344r and hd404394 series.
631 $027?ystem clock selection register 1 ssr1 clock oscillator hd404339/hd404369 series bit initial value read/write 3 ssr13 0 w 0 2 ssr12 0 w 1 ssr11 0 w 0 1 subsystem clock divisor switch 0 1 system clock selection * 1 unused 0 1 subsystem clock stop setting notes: 1. 2. 3. when the subsystem clock (32.768 khz crystal oscillator) is used, use the ranges 0.4 mhz f osc 1.0 mhz and 1.6 mhz f osc 4.5 mhz (8.5 mhz: hd404369 series). applies to the hd404364, hd404368, hd4043612, and hd404369. applies to the hd40a4364, hd40a4368, hd40a43612, hd40a4369, and hd407a4369. f sub = f x /8 f sub = f x /4 0.4 to 1.0mhz 1.6 to 4.5 mhz (hd404339 series) 1.6 to 5.0 mhz (hd404369 series) * 2 1.6 to 8.5 mhz (hd404369 series) * 3 the subsystem clock operates in stop mode the subsystem clock stops in stop mode
632 $028?ystem clock selection register 2 ssr2 clock oscillator hd404339/hd404369 series bit initial value read/write 3 0 ssr20 0 w 2 1 ssr21 0 w 0 1 system clock divisor selection 0 1 0 1 unused division by 4 (f cyc = f osc /4) division by 8 (f cyc = f osc /8) division by 16 (f cyc = f osc /16) division by 32 (f cyc = f osc /32) $02c?ata control register d0 dcd0 d port hd404344r/hd404394/hd404358/hd404358r/hd404369 series bit initial value read/write 3 dcd03 0 w 0 dcd00 0 w 2 dcd02 0 w 1 dcd01 0 w $02d?ata control register d1 dcd1 d port hd404344r/hd404394/hd404358/hd404358r/hd404369 series bit initial value read/write 3 dcd13 * 0 w 0 dcd10 0 w 2 dcd12 * 0 w 1 dcd11 0 w note: * applies to the hd404358, hd404358r, and hd404369 series. the dcd13 and dcd12 bits are unused in the hd404344r and hd404394 series.
633 $02e?ata control register d2 dcd2 d port hd404358/hd404358r/hd404369 series bit initial value read/write 3 dcd23 * 0 w 0 dcd20 0 w 2 dcd22 * 0 w 1 dcd21 * 0 w note: * applies to the hd404369 series. the dcd23 to dcd21 bits are unused in the hd404358 and hd404358r series. $02f?ata control register d3 dcd3 d port hd404369 series bit initial value read/write 3 0 dcd30 0 w 2 1 dcd31 0 w $030?ata control register r0 dcr0 r0 port hd404344r/hd404394/hd404318/hd404358/hd404358r/hd404339/hd404369 series bit initial value read/write 3 dcr03 0 w 0 dcr00 0 w 2 dcr02 0 w 1 dcr01 0 w
634 $031?ata control register r1 dcr1 r1 port hd404344r/hd404394/hd404358/hd404358r/hd404369 series bit initial value read/write 3 dcr13 0 w 0 dcr10 0 w 2 dcr12 0 w 1 dcr11 0 w $032?ata control register r2 dcr2 r2 port hd404344r/hd404394/hd404358/hd404358r/hd404369 series bit initial value read/write 3 dcr23 0 w 0 dcr20 0 w 2 dcr22 0 w 1 dcr21 0 w $033?ata control register r3 dcr3 r3 port hd404344r/hd404394/hd404318/hd404358/hd404358r/hd404339/hd404369 series bit initial value read/write 3 dcr33 0 w 0 dcr30 * 0 w 2 dcr32 0 w 1 dcr31 0 w note: * applies to the hd404344r, hd404318, hd404358, hd404358r, hd404339, and hd404369 series. the dcr30 bit is unused in the hd404394 series.
635 $034?ata control register r4 dcr4 r4 port hd404318/hd404358/hd404358r/hd404339/hd404369 series bit initial value read/write 3 dcr43 0 w 0 dcr40 0 w 2 dcr42 0 w 1 dcr41 0 w $035?ata control register r5 dcr5 r5 port hd404339/hd404369 series bit initial value read/write 3 dcr53 0 w 0 dcr50 0 w 2 dcr52 0 w 1 dcr51 0 w $036?ata control register r6 dcr6 r6 port hd404339/hd404369 series bit initial value read/write 3 dcr63 0 w 0 dcr60 0 w 2 dcr62 0 w 1 dcr61 0 w
636 $037?ata control register r7 dcr7 r7 port hd404339/hd404369 series bit initial value read/write 3 0 dcr70 0 w 2 dcr72 0 w 1 dcr71 0 w $038?ata control register r8 dcr8 r8 port hd404358/hd404358r/hd404369 series bit initial value read/write 3 dcr83 0 w 0 dcr80 0 w 2 dcr82 0 w 1 dcr81 0 w $039?ata control register r9 dcr9 r9 port hd404369 series bit initial value read/write 3 dcr93 0 w 0 dcr90 0 w 2 dcr92 0 w 1 dcr91 0 w
637 appendix c option lists c.1 hd404344r series option list please check off the appropriate applications and enter the necessary information. 1 rom size hd404341r: 1-kword ceramic oscillator hd404342r: 2-kword external clock hd404344r: 4-kword hd40c4341r: 1-kword resister oscillator hd40c4342r: 2-kword hd40c4344r: 4-kword 2 rom code data type please specify the first type below (the upper bits and lower bits are mixed together), when using the eprom on-package microcomputer type (including ztat version). the upper bits and lower bits are mixed together. the upper five bits and lower five bits are programmed to the same eprom in alternating order (i.e., lululu?. the upper bits and lower bits are separated. the upper five bits and lower five bits are programmed to different eproms. 3 system oscillator (osc 1 and osc 2 ) hd404341r/hd404342r/ hd404344r hd40c4341r/hd40c4342r/ hd40c4344r ceramic oscillator f = mhz external clock f = mhz resistor oscillator the shaded portion indicates unavailable selections. 4 stop mode 5 package used dp-28s not used fp-28da fp-30d date of order customer department name rom code name lsi number (hitachi entry)
638 c.2 hd404394 series option list please check off the appropriate applications and enter the necessary information . 1 rom size hd404391: 1-kword hd404392: 2-kword hd404394: 4-kword 2 rom code data type please specify the first type below (the upper bits and lower bits are mixed together), when using the eprom on-package microcomputer type (including ztat version). the upper bits and lower bits are mixed together. the upper five bits and lower five bits are programmed to the same eprom in alternating order (i.e., lululu?. the upper bits and lower bits are separated. the upper five bits and lower five bits are programmed to different eproms. 3 system oscillator (osc 1 and osc 2 ) ceramic oscillator f = mhz external clock f = mhz 4 stop mode used not used 5 package dp-28s fp-28da fp-30d date of order customer department name rom code name lsi number (hitachi entry)
639 c.3 hd404318 series option list please check off the appropriate applications and enter the necessary information . 1 rom size hd404314: 4-kword hd404316: 6-kword hd404318: 8-kword 2 i/o option i/o option i/o option pin i/o d e pin i/o d e d 0 / int 0 i/o r1 r1 0 i/o d 1 / int 1 i/o r1 1 i/o d 2 /evnb i/o r1 2 i/o d 3 /buzz i/o r1 3 i/o d 4 / stopc i/o r2 r2 0 i/o d 5 i/o r2 1 i/o d 6 i/o r2 2 i/o d 7 i/o r2 3 i/o d 8 i/o r8 r8 0 i/o d: without pull-down resistance r8 1 i/o e: with pull-down resistance r8 2 i/o r8 3 i/o 3 ra 1 /v disp ra ra 1 i selected in option 3 ra 1 : without pull-down resistance (d) v disp note: if even one pin is selected with i/o option e, pin ra 1 /v disp must be selected to function as v disp . continued on the following page. date of order customer department name rom code name lsi number (hitachi entry)
640 continued from the preceding page. 4 rom code data type please specify the first type below (the upper bits and lower bits are mixed together), when using the eprom on-package microcomputer type (including ztat versions). the upper bits and lower bits are mixed together. the upper five bits and lower five bits are programmed to the same eprom in alternating order (i.e., lululu?. the upper bits and lower bits are separated. the upper five bits and lower five bits are programmed to different eproms. 5 system oscillator (osc 1 and osc 2 ) ceramic oscillator f = mhz crystal oscillator f = mhz external clock f = mhz 6 stop mode used not used 7 package dp-42s fp-44a rom code name lsi number (hitachi entry)
641 c.4 hd404358 series option list please check off the appropriate applications and enter the necessary information. 1 rom size 5 mhz operation: hd404354 4-kword 8.5 mhz operation: hd40a4354 5 mhz operation: hd404356 6-kword 8.5 mhz operation: hd40a4356 5 mhz operation: hd404358 8-kword 8.5 mhz operation: hd40a4358 2 rom code data type please specify the first type below (the upper bits and lower bits are mixed together), when using the eprom on-package microcomputer type (including ztat version). the upper bits and lower bits are mixed together. the upper five bits and lower five bits are programmed to the same eprom in alternating order (i.e., lululu...). the upper bits and lower bits are separated. the upper five bits and lower five bits are programmed to different eproms. 3 system oscillator (osc 1 and osc 2 ) ceramic oscillator f = mhz crystal oscillator f = mhz external clock f = mhz 4 stop mode used not used 5 package dp-42s fp-44a date of order customer department name rom code name lsi number (hitachi entry)
642 c.5 hd404358r series option list please check off the appropriate applications and enter the necessary information. 1 rom size 5 mhz operation: hd404354r 4-kword 8.5 mhz operation: hd40a4354r cr oscillator version: hd40c4354r 5 mhz operation: hd404356r 6-kword 8.5 mhz operation: hd40a4356r cr oscillator version: hd40c4356r 5 mhz operation: hd404358r 8-kword 8.5 mhz operation: hd40a4358r cr oscillator version: hd40c4358r 2 rom code data type please specify the first type below (the upper bits and lower bits are mixed together), when using the eprom on-package microcomputer type (including ztat version). the upper bits and lower bits are mixed together. the upper five bits and lower five bits are programmed to the same eprom in alternating order (i.e., lululu?. the upper bits and lower bits are separated. the upper five bits and lower five bits are programmed to different eproms. 3 system oscillator (osc 1 and osc 2 ) hd404354r/6r/8r, hd40a4354r/6r/8r hd40c4354r/6r/8r ceramic oscillator f = mhz crystal oscillator f = mhz external clock f = mhz resistor oscillator the shaded portion indicates unavailable selections. continued on the following page. date of order customer department name rom code name lsi number (hitachi entry)
643 continued from the preceding page. 4 stop mode used not used 5 package dp-42s fp-44a rom code name lsi number (hitachi entry)
644 c.6 hd404339 series option list please check off the appropriate applications and enter the necessary information. 1 rom size hd404334: 4-kword hd404336: 6-kword hd404338: 8-kword hd4043312: 12-kword hd404339: 16-kword 2 optional function * with 32-khz cpu operation, with time-base for clock * without 32-khz cpu operation, with time-base for clock without 32-khz cpu operation, without time-base for clock note: * options marked with an asterisk require a subsystem crystal oscillator (x1, x2). continued on the following page. date of order customer department name rom code name lsi number (hitachi entry)
645 continued from the preceding page. 3 i/o option i/o option i/o option pin i/o d e pin i/o d e d 0 / int 0 i/o r1 r1 0 i/o d 1 / int 1 i/o r1 1 i/o d 2 /evnb i/o r1 2 i/o d 3 /buzz i/o r1 3 i/o d 4 / stopc i/o r2 r2 0 i/o d 5 i/o r2 1 i/o d 6 i/o r2 2 i/o d 7 i/o r2 3 i/o d 8 i/o r8 r8 0 i/o d 9 i/o r8 1 i/o d 10 i/o r8 2 i/o d 11 i/o r8 3 i/o d 12 i/o r9 r9 0 i/o d 13 i/o r9 1 i/o d: without pull-down resistance r9 2 i/o e: with pull-down resistance r9 3 i/o ra ra 1 i selected in item 4 4 ra 1 /v disp ra 1 : without pull-down resistance (d) v disp note: if even one pin is selected with i/o option e, pin ra 1 /v disp must be selected to function as vdisp. continued on the following page. rom code name lsi number (hitachi entry)
646 continued from the preceding page. 5 rom code data type please specify the first type below (the upper bits and lower bits are mixed together), when using the eprom on-package microcomputer type (including ztat version) the upper bits and ower bits are mixed together. the upper five bits and lower five bits are programmed to the same eprom in alternating order (i.e., lululu...). the upper bits and lower bits are separated. the upper five bits and lower five bits are programmed to different eproms. 6 system oscillator (osc 1 and osc 2 ) ceramic oscillator f = mhz crystal oscillator f = mhz external clock f = mhz 7 stop mode used not used 8 package fp-64b dp-64s rom code name lsi number (hitachi entry)
647 c.7 hd404369 series option list please check off the appropriate applications and enter the necessary information . 1 rom size 5 mhz operation: hd404364 4-kword 8.5 mhz operation: hd40a4364 5 mhz operation: hd404368 8-kword 8.5 mhz operation: hd40a4368 5 mhz operation: hd4043612 12-kword 8.5 mhz operation: hd40a43612 5 mhz operation: hd404369 16-kword 8.5 mhz operation: hd40a439 2 function options * with 32-khz cpu operation, with time-base for clock * without 32-khz cpu operation: with time-base for clock without 32-khz cpu operation: without time-base for clock note: * options marked with an asterisk require a subsystem crystal oscillator (x1, x2). 3 rom code data type please specify the first type below (the upper bits and lower bits are mixed together), when using the eprom on-package microcomputer type (including ztat version). the upper bits and lower bits are mixed together. the upper five bits and lower five bits are programmed to the same eprom in alternating order (i.e., lululu...). the upper bits and lower bits are separated. the upper five bits and lower five bits are programmed to different eproms. 4 system oscillator (osc 1 and osc 2 ) 5 stop mode ceramic oscillator f = mhz used crystal oscillator f = mhz not used external clock f = mhz dp-64s fp-64b date of order customer department name rom code name lsi number (hitachi entry)
648 appendix d package dimensions hitachi code jedec eiaj weight (reference value) dp-28s conforms 1.9 g unit: mm 10.16 0.51 min 2.54 min 5.10 max 0.25 0 ?15 + 0.11 ?0.05 0.48 0.10 1.78 0.25 27.1 27.9 max 1.0 8.8 10.8 max 28 15 114 2.41 max
649 hitachi code jedec eiaj weight (reference value) fp-28da conforms conforms 0.82 g unit: mm *dimension including the plating thickness base material dimension *0.17 0.05 3.00 max 8.40 18.00 18.75 max 1.12 max 28 15 1 14 11.80 0.30 0 8 1.00 0.20 1.70 0.20 0.15 m *0.40 0.08 1.27 0.38 0.06 + 0.15 0.10 0.20 0.15 0.04
650 hitachi code jedec eiaj weight (reference value) fp-30d unit: mm *dimension including the plating thickness base material dimension 0.10 m 0.10 0.10 2.00 max *0.32 0.08 0.65 15 30 11.0 11.2 max 8.0 *0.17 0.05 0.5 0.1 10.0 0.2 0 8 16 1.05 max 1 0.10 1.0 0.30 0.06 0.15 0.04
651 hitachi code jedec eiaj weight (reference value) dp-42s conforms 4.8 g unit: mm 0.25 + 0.10 0.05 0 15 15.24 37.3 38.6 max 1.0 14.0 14.6 max 0.51 min 5.10 max 2.54 min 0.48 0.10 1.78 0.25 42 22 1 21 1.38 max
652 hitachi code jedec eiaj weight (reference value) fp-44a conforms 1.2 g unit: mm *dimension including the plating thickness base material dimension 0 8 0.10 0.15 m 17.2 0.3 14 33 23 34 44 111 17.2 0.3 *0.37 0.08 0.8 3.05 max *0.17 0.05 1.6 0.8 0.3 2.70 22 12 3.0 0.10 +0.15 0.10 0.15 0.04 0.35 0.06
653 hitachi code jedec eiaj weight (reference value) dp-64s conforms 8.8 g unit: mm 0.25 + 0.11 0.05 0 15 1.78 0.25 0.48 0.10 0.51 min 2.54 min 5.08 max 19.05 57.6 58.5 max 1.0 1 33 32 64 17.0 18.6 max 1.46 max *dimension including the plating thickness base material dimension
654 hitachi code jedec eiaj weight (reference value) fp-64b 1.7 g unit: mm *dimension including the plating thickness base material dimension 0.20 m 0 10 *0.37 0.08 *0.17 0.05 3.10 max 1.2 0.2 24.8 0.4 20 51 33 32 19 1 64 52 18.8 0.4 14 0.15 1.0 20 2.70 2.4 1.0 1.0 0.20 +0.10 0.20 0.35 0.06 0.15 0.04
hmcs43xx family hardware manual publication date: 1st edition, february 1995 3rd edition, august 2000 published by: electronic devices sales & marketing group semiconductor & integrated circuits hitachi, ltd. edited by: technical documentation group hitachi kodaira semiconductor co., ltd. copyright ? hitachi, ltd., 1995. all rights reserved. printed in japan.

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