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CXA2161R i 2 c bus compatible audio video (av) switch & electronic volume control description the sony CXA2161R is an audio/video switch designed primarily for application in digital set top boxes. it provides video and audio routing from the digital encoder source to the tv and vcr scart (peri- television) connectors. in addition, the tv audio output has a programmable volume control. the chip is programmed by means of an i 2 c interface and can operate from a single or dual power supply. target specifications: canal+, bskyb, tps, nordig, and ecca euro-box features supply single: 0v, +5v, +12v dual: 0v, ?v, +5v and +12v (low number of external parts required) video 2 scart switching (vcr, tv) vcr input supports rgb mode integrated 75 ? drivers for direct video connection y/c mixer with trap for rf modulators switchable clamps on inputs adjustable gain on rgb outputs video output shutdown for low power modes fast blanking switch slow blanking switch for tv and vcr output svhs switch on vcr output y/c auxiliary input audio four stereo audio inputs volume control (?6db to +6db in 2db steps) additional switchable gain on audio dac inputs audio overlay facility volume bypass for tv and phono outputs mono switching on tv, vcr outputs high drive capability (600 ? loads possible) switchable audio limiter function switchable mono output for rf modulators audio output disable i 2 c and logic fast mode compatible i 2 c bus function monitor with loop through interrupt output for function monitor logic output pin sync detector for y/cvbs inputs applications digital set top box integrated digital television structure bipolar silicon monolithic ic absolute maximum ratings (ta = 25?) unless stated supply voltage v cc 14 v storage temperature tstg ?5 to +150 ? allowable power dissipation p d 1.1 w (when mounted on the board) operating conditions single supply 12 0.6 v 5 0.25 v dual supply ? 0.25 v 5 0.25 v 12 0.6 v operating temperature topr ?0 to +75 ? ?1 e00202a12 sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. 56 pin lqfp (plastic)
?2 CXA2161R block diagram (1) video and digital section note) all video outputs contain 75 ? drivers, except vout_7 (pin 38). 0/6/12v 0/6/12v 2 8 9 11 10 12 13 14 15 18 21 24 33 34 35 36 37 38 39 40 41 43 44 45 46 47 48 49 7 50 6 51 1 5 52 53 3 4 54 55 56 fblk_sw video switch1 (tv) rgb gain control (+1, 2, 3db) video switch2 (vcr) dc restore dc restore dc restore/tip dc restore/c bias c bias dc restore/c bias c bias clamp cntl tip tip tip tip tip bias mute sync detect dc restore monitor 3.3v or 5v fast mode compatible logic interrupt control 2 output disable 2 output disable 2 output disable 2 output disable 2 output disable & bi-drection control 2 output disable 2 mix_sw mix_sw tv_fblk fblk_in1 +3.5v 0v fblk_in2 vin_1 vin_2 vin_3 vin_4 vin_5 vin_6 vin_7 vin_13 vin_8 vin_9 vin_10 vin_11 vin_12 sync_id aud_bias vid_bias +5v/12v_v cc a 5v_gnda +5v_dig gnd_dig +5v_vout gnd_vid +5v_vid +12v_dig sda scl fnc_vcr dig vcr dig blue vcr blue dig green/cvbs vcr green dig red/chroma dig chroma vcr red/chroma aux chroma dig cvbs/luma dig cvbs/luma vcr cvbs/luma tv cvbs aux y/cvbs vcr typical connection typical connection vout_1 tv blue vout_2 tv green tv vcr rf mod tv micro vout_3 tv red/c vout_4 tv cvbs/y vout_5 vcr chroma vout_6 vcr cvbs/y trap vout_7 (cvbs) fnc_tv intrupt logic
3 CXA2161R (2) audio section 27 6db vol bypass (tv) audio switch1 (tv) 17 20 23 26 25 30 31 32 42 6/ 3/0/+3db 6db 6db 6/ 11db 16 19 22 29 6/ 3/0/+3db 6db 6db 6db audio switch2 (vcr) rin_1 (dig) mono to rf modulator phono_r rtv ltv phono_l rout1 lout1 vcr rin_2 (vcr) rin_3 (tv/overlay) rin_4 (aux) lin_1 (dig) lin_2 (vcr) lin_3 (tv/overlay) lin_4 (aux) 16db overlay on/off 16db tone mix overlay on/off bias mute limiter 2.2vrms output disable 2db limiter 2.2vrms 2db volume control +6 to 56db zcd vol bypass (phono) mono switch mono and r/l switch mono and r/l switch vol bypass (tv) vol bypass (phono) 6db 6db 6db 6db 6db 6db tv 28
4 CXA2161R pin configuration vout_4 +5v_vout vout_3 vout_2 vout_1 +5v_vid vid_bias vin_1 vin_3 vin_5 vin_6 vin_8 vin_9 vin_12 vin_13 sync_id vin_11 vin_10 vin_7 vln_4 vin_2 gnd_dig tv_fblk fblk_in1 fnc_tv fblk_in2 fnc vcr +5v_dig rin_4 vout_5 gnd_vid vout_6 vout_7 trap intrupt scl sda logic mono phono_r phono_l lln_4 1 2 3 4 5 6 7 8 9 11 12 13 14 15 16 17 18 19 21 22 23 24 25 26 27 28 29 31 32 33 34 35 36 37 38 39 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 10 20 30 40 rout1 lout1 rtv ltv +5v/12v_v cc a rin_1 lin_1 5v_gnda rin_2 lin_2 aud_bias rin_3 lin_3 +12v_dig
5 CXA2161R pin description pin no. symbol pin voltage [v] equivalent circuit description v cc 150 6 7 50 vin_1 vin_2 vin_4 2.4 rgb signal inputs 50 7 6 v cc 150 51 vin_3 2.4 2.35 rgb signal input or cvbs/luminance signal input 51 v cc 150 20k 5 52 vin_5 vin_7 2.4 3.0 rgb signal inputs or chrominance signal inputs 52 5 v cc 150 20k 1 53 vin_6 vin_13 3.0 chrominance signal inputs 53 1 150 3 4 54 55 56 v cc vin_8 vin_9 vin_10 vin_11 vin_12 2.35 cvbs/luminance signal inputs 54 55 4 3 56 v cc 39 43 45 46 47 12k vout_1 vout_2 vout_3 vout_4 vout_6 rgb/cvbs signal outputs (see description of operation for pin voltages) 47 46 45 43 39
6 CXA2161R pin no. symbol pin voltage [v] equivalent circuit description v cc 12k 41 vout_5 1.8 chrominance signal output 41 v cc 12k 0.75ma 38 vout_7 0.4 typically rf modulator signal output minimum load resistance = 20k ? 38 v cc v cc 150 40.8k 18.3k 49 vid_bias 0.9 internal reference bias for video circuits. a capacitor is connected from this pin to gnd. typically 100nf 49 v cc 200 2k 37 trap 2.3 connects trap circuit for subcarrier 37 v cc 150 2 sync_id 2.5 sync detect circuit time constant, resistor and capacitor connection pin 2 v cc v cc /2 60k 60k 16 17 19 20 22 23 29 42 lin_1 rin_1 lin_2 rin_2 lin_3 rin_3 lin_4 rin_4 6.0 (single) 0.0 (dual) audio signal inputs 22 23 19 20 16 17 29 42
7 CXA2161R pin no. symbol pin voltage [v] equivalent circuit description v cc 20k 25 26 27 28 30 31 32 ltv rtv lout1 rout1 phono_l phono_r mono 6.0 (single) 0.0 (dual) audio signal outputs capacitor connected to gnd. (typically 22f) connected directly to gnd. 25 26 27 28 30 31 32 v cc v cc 150 40k 40k 18 aud_bias internal reference bias for audio circuits. 18 v cc 150 10 12 fblk_in1 fblk_in2 fast blanking signal inputs 10 12 v cc 9 tv_fblk fast blanking signal output 9 13 120k fnc_vcr scart function pin 8 input/output to vcr 13 v cc 11 fnc_tv scart function pin 8 output to tv 11 6.0 (single) 0.0 (dual)
8 CXA2161R pin no. symbol pin voltage [v] equivalent circuit description v cc 33 36 logic intrupt open collector logic outputs typically connect to +5v through 10k ? resistor. 33 36 8k 34 35 i 2 c bus clock line i 2 c bus data line +5v_dig +5v_vout +5v_vid +12v_dig 5v_gnda +5v/+12v_v cc a gnd_dig gnd_vid 5.0 12.0 5.0 (dual) 0.0 (single) 5.0 (dual) 12.0 (single) 0.0 0.0 digital supply video output supply video supply digital supply audio supply or audio ground audio supply digital ground video ground 14 44 48 15 21 24 8 40 scl 35 sda 34
9 CXA2161R electrical characteristics nominal conditions (ta = 25 c) +12 supply, no signal, no load +5 supply, no signal, no load +12 supply, no signal, no load +5 supply, no signal, no load 5 supply, no signal, no load current consumption (single ended supply) current consumption (dual supply) i cc1 i cc2 i cc3 i cc4 i cc5 22 50 2 70 20 45 80 6 115 45 ma ma ma ma ma item symbol conditions min. typ. max. unit video system nominal conditions single supply (ta = 25 c, +5v/12v_v cc a = +12v, 5v_gnda = 0v, +5v_vid = +5v, +5v_vout = +5v, +5v_dig = +5v, gnd_vid = 0v) sync tip clamp voltage at input chrominance bias input voltage rgb dc restore input voltage sync tip clamp voltage at output chrominance bias output voltage rgb dc restore output voltage gain (vout1 to 6) gain (vout1, 2, 3) gain (vout7) mixer off gain (vout7) mixer on bandwidth (vout1 to 6) bandwidth (vout7) mixer on no trap components input dynamic range output dynamic range vclmp1 cbias1 cbias2 rgb1 vclmp2 cbias3 rgb2 gvv gv rgb1 gv rgb2 gv rgb3 gv yc gv yc f v3db f v3db v drvi v drvo 5.5 6.5 7.5 8.5 5.5 5.5 15 8 1.4 2.8 2.4 3 2.35 2.4 0.3 1.8 0.6 6.0 7.0 8.0 9.0 6.0 5.75 22 18 6.5 7.5 8.5 9.5 6.5 6.5 v v v v v v v db db db db db db mhz mhz vp-p vp-p item symbol conditions min. typ. max. unit vin3, vin8, vin9, vin10, vin11, vin12 inputs. (vin3 set to cvbs mode) (fig. 1) vin5, vin7 inputs. clamps set to chrominance bias mode. (fig. 1) vin6, vin13 inputs. (fig. 1) vin1, vin2, vin3, vin4, vin5, vin7 inputs. (vin3 & vin5 set to rgb mode) (fig. 1) vout4, vout6 outputs (fig. 1) vout3, vout5 outputs (fig. 1) vout1, vout2, vout3 outputs (fig. 1) f = 200khz, 0.3vp-p input , rgb gain = 0db (fig. 2) f = 200khz, 0.3vp-p input , rgb gain = +1db (fig. 2) f = 200khz, 0.3vp-p input , rgb gain = +2db (fig. 2) f = 200khz, 0.3vp-p input , rgb gain = +3db (fig. 2) f = 200khz, 0.3vp-p input (fig. 2) f = 200khz, 0.3vp-p input (fig. 2) 0.3vp-p input, frequency where output level is 3db with 200khz serving as 0db (fig. 2) 0.3vp-p input, frequency where output level is 3db with 200khz serving as 0db (fig. 2) 200khz input applied to any video (fig. 2) 200khz input applied to any video (fig. 2)
10 CXA2161R cross talk s/n ratio non-linearity differential gain differential phase vctv s/n v lin dg dp 3 3 3 74 0 0 0 50 3 3 3 db db % % deg item symbol conditions min. typ. max. unit f = 4.43mhz, 1vp-p input (fig. 2) ratio of 0.7vp-p white video signal to black line noise. weighted using ccir 567. hpf@5khz, lpf@5mhz. (fig. 2) v1 = pin voltage + 0.5v, v2 = pin voltage + 1v at output, non-linearity = 1 100 (fig. 2) 1.7vp-p 5-step modulated staircase. (chrominance & burst are 150mvp-p, 4.43mhz) (fig. 2) as above. input pin v plus v1 v2 v2 v1 2 audio system unless otherwise stated: input coupling capacitor 1f; output coupling capacitor 10f; load 10k ? . nominal conditions single supply (ta = 25 c, +5v/12v_v cc a = +12v, 5v_gnda = 0v, +5v_vid = +5v, +5v_vout = +5v, +5v_dig = +5v, gnd_vid = 0v) nominal conditions dual supply (ta = 25 c, +5v/12v_v cc a = +5v, 5v_gnda = 5v, +5v_vid = +5v, +5v_vout = +5v, +5v_dig = +5v, gnd_vid = 0v) input/output pin voltage (single supply) input/output pin voltage (dual supply) output pin voltage when disabled (dual supply) input rin1 or lin1 rin1 or lin1 rin1 or lin1 rin1 or lin1 rin1 or lin1 v apin1 v apin2 v apin3 gv a1 gv a2 gv a3 gv a4 gv a5 0.5 2.5 5.5 8.5 0.5 6 0 0 0 3 6 9 0 0.5 3.5 6.5 9.5 0.5 v v v db db db db db item symbol conditions min. typ. max. unit no signal, no load (fig. 3) no signal, no load (fig. 3) no signal, no load (fig. 3) f = 1khz, 0.5vrms input. tv volume set to 0db, rin_1/lin_1 amplifier = 6db (fig. 4) f = 1khz, 0.5vrms input. tv volume set to 0db, rin_1/lin_1 amplifier = 3db (fig. 4) f = 1khz, 0.5vrms input. tv volume set to 0db, rin_1/lin_1 amplifier = 0db (fig. 4) f = 1khz, 0.5vrms input. tv volume set to 0db, rin_1/lin_1 amplifier = +3db (fig. 4) f = 1khz, 1vrms input. tv volume set to 0db, rin_1/lin_1 amplifier = 6db (fig .4) output tv or phono tv or phono tv or phono tv or phono vcr gain
11 CXA2161R rin1 + lin1 rin1 + lin1 rin2, 3, 4 or lin2, 3, 4 rin1 + lin1 rin2 + lin2 rin3 + lin3 rin4 + lin4 rin2, 3, 4 lin2, 3, 4 rin2 + lin2 rin3 + lin3 rin4 + lin4 rin3 lin3 audio frequency response frequency bandwidth distortion input dynamic range rin1, 2, 3, 4/lin1, 2, 3, 4 cross talk (channel separation) dc offset input impedance rin1, 2, 3, 4/lin1, 2, 3, 4 output impedance phase difference s/n ratio gv a6 gv a7 gv a9 gv a8 gv a10 gv a11 gv a12 gv a13 gv a14 f af f bwa1 thd vd a1 vct a voff zin1 zout vpda s/n a 0.5 0.5 0.5 0.5 0.5 0.5 0.5 5.5 0.5 0.3 2.5 30 80 0 0 0 0 0 0 0 5 0 0 1 0.005 2.9 0 120 10 0.05 93 0.5 0.5 0.5 0.5 0.5 0.5 0.5 4.5 0.5 0.3 0.2 76 30 db db db db db db db db db db mhz % vrms db mv k ? ? deg db item symbol conditions min. typ. max. unit f = 1khz, 0.5vrms stereo input. tv volume set to 0db, rin_1/lin_1 amplifier = 6db. tv mono switch on. (fig. 4) f = 1khz, 1vrms stereo input. tv volume set to 0db, rin_1/lin_1 amplifier = 6db. (note 1) (fig. 4) f = 1khz, 1vrms input, tv volume set to 0db (fig. 4) f = 1khz, 1vrms stereo input. rin_1/lin_1 amplifier = 6db. vcr mono switch on. (fig 4) f = 1khz, 1vrms stereo input. tv volume set to 0db (note 2) (fig 4) f = 1khz, 1vrms input (fig 4) f = 1khz, 1vrms stereo input. vcr mono switch on. (fig 4) f = 1khz, 1vrms input, lin3 has no signal audio overlay enabled with 11db attenuation at input rin_3 (fig 4) f = 1khz, 1vrms input audio overlay enabled. (fig 4) 0.3vp-p input. output/input gain at 30khz with 1khz serving as 0db (fig 4) 0.3vp-p input; frequency where output level is 3db with 1khz serving as 0db. no load attached (fig 4) f = 1khz, 0.5vrms, unweighted response; lpf@400hz, hpf@80khz (fig 4) f = 1khz, rin_1/lin_1 input amplifier set to 6db. dual supply mode used. (fig 4) f = 1khz, 1vrms input on one input, measure on any other audio output (fig 4) offset voltage between input and output (excluding any external series resistor) (excluding any external series resistor) f = 1khz, 1vrms input to two channels. phase difference of stereo output measured f = 1khz, 1vrms input (at 0db volume). hpf@20hz, lpf@20khz. (fig 4) tv (mono mix) mono tv or phono vcr (mono mix) mono vcr vcr (mono mix) rtv, rout1, phono_r ltv, lout1, phono_l note 1) mono switch set to mix of rin1 & lin1 inputs. note 2) mono switch set to mix of rtv & ltv after volume control.
12 CXA2161R electronic volume control volume attenuation step mute tv i/p mute or vcr i/p mute audio limiter level a evc amute alimit 1.6 2 90 6.5 2.4 76 db db vp-p item symbol conditions min. typ. max. unit f = 1khz, 0.5vrms input. set by i 2 c (fig 4) f = 1khz, 1vrms input (fig 4) f = 1khz, 2.5vrms input. measure tvp-p output with limiter switched on. (fig 4) digital characteristics i 2 c interface the i 2 c interface is compliant with philips i 2 c fast mode specification (date april 1995). the interface is also capable of interfacing to +3.3v or +5v logic levels. symbol item condition min. typ. max. unit v ih v il v ol v hyst t sp t f t scl t buf t hd;sta t low t high t su;sda t hd;dat t su;dat t su;sto high level input voltage low level input voltage low level output voltage hysteresis of schmitt trigger input spike suppression fall time for sda line scl clock frequency bus free time between a stop and start hold time (repeated start condition) low period of scl clock high period of scl clock setup time for a repeated start condition data hold time data setup time setup time for stop condition with sda, 3ma current supplied with sda, 6ma current supplied v ih v il 400pf bus load i 2 c bus line requirement i 2 c bus line requirement i 2 c bus line requirement i 2 c bus line requirement i 2 c bus line requirement i 2 c bus line requirement i 2 c bus line requirement i 2 c bus line requirement i 2 c bus line requirement 2.3 0 0 0 0 1.3 0.6 1.3 0.6 0.6 0 100 0.6 0.5 5.5 1.5 0.4 0.6 50 300 400 0.9 v v v v ns ns khz s s s s s s ns s t buf t hd;sta s p t low t r t high t su;dat t su;sta t su;dat p sr t su;sto t f t hd;sta
13 CXA2161R logic/interrupt output these outputs are open collector type and normally connected to +5v through a 10k ? resistor. output low voltage dig voutl 0.15 0.4 v item symbol conditions min. typ. max. unit i ol = 1ma
14 CXA2161R fig. 1. video system (dc test) dc measured from pins 1, 3, 4, 5, 6, 7, 38, 39, 41, 43, 45, 46, 47, 50, 51, 52, 53, 54, 55, 56 notes) 1. all supplies de-coupled close to supply pins 14, 15, 24, 44, 48 with 10nf and 10f capacitors. 2. all video outputs are unloaded during tests. 75 ? 100nf 75 ? 100nf 75 ? 100nf 75 ? 100nf 75 ? 100nf 75 ? 100nf 75 ? 100nf 100nf 75 ? 68k ? +5v 75 ? 100nf 100nf 100nf 75 ? 100nf 75 ? 100nf 75 ? 100nf 75 ? 100nf +5v +5v +12v +12v 1 f +5v v i 2 c scl sda output measurement point input measurement point 2 3 4 5 6 7 8 9 11 12 13 14 15 16 17 18 19 21 22 23 24 25 26 27 28 29 31 32 33 34 35 36 37 38 39 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 10 20 30 40 1 v
15 CXA2161R fig. 2. video system (gain, dynamic range, bandwidth, differential gain, differential phase, crosstalk, linearity, sync detection) signal applied to pins 1, 3, 4, 5, 6, 7, 50, 51, 52, 53, 54, 55, 56 output signal measured from pins 38, 39, 41, 43, 45, 46, 47 notes) 1. all supplies de-coupled close to supply pins 14, 15, 24, 44, 48 with 10nf and 10f capacitors. 2. for tests requiring video measuring equipment with 75 ? input impedance, an external video line driver or buffer is used. 3. for video crosstalk tests all video inputs are terminated with 37.5 ? 75 ? 100nf 75 ? 100nf 75 ? 100nf 75 ? 100nf 75 ? 100nf 75 ? 100nf 75 ? 100nf 100nf 75 ? 75 ? 68k ? +5v 100nf 100nf 100nf 75 ? 100nf 75 ? 100nf 75 ? 100nf 75 ? 100nf +5v +5v +12v +12v 1 f +5v v i 2 c scl sda measurement point input signal 2 3 4 5 6 7 8 9 11 12 13 14 15 16 17 18 19 21 22 23 24 25 26 27 28 29 31 32 33 34 35 36 37 38 39 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 10 20 30 40 1 22k ? 150 ? 150 ? 150 ? 150 ? 150 ? 150 ?
16 CXA2161R fig. 3. audio system (dc tests) dc measured from pins 16, 17, 19, 20, 22, 23, 25, 26, 27, 28, 29, 30, 31, 32, 42 notes) 1. single audio supply configuration shown. operate switches for dual supply configuration. 2. all supplies de-coupled close to supply pins 14, 15, 21, 24, 44, 48 with 10nf and 10f capacitors. 5v 100nf +5v +5v +12v +5v +12v 1 f +5v v i 2 c scl sda output measurement point input measurement point 2 3 4 5 6 7 8 9 11 12 13 14 15 16 17 18 19 21 22 23 24 25 26 27 28 29 31 32 33 34 35 36 37 38 39 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 10 20 30 40 1 v
17 CXA2161R fig. 4. audio system (single supply ?gain, bandwidth, signal to noise, electronic volume, zero cross detection, limiter) (dual supply ?distortion, dynamic range, crosstalk) signal applied to pins 16, 17, 19, 20, 22, 23, 29, 42 output signal measured from pins 25, 26, 27, 28, 30, 31, 32 notes) 1. single audio supply configuration shown. operate switches for dual supply configuration. 2. all supplies de-coupled close to supply pins 14, 15, 21, 24, 44, 48 with 10nf and 10f capacitors. 5v 100nf +5v +5v +12v +5v +12v 1 f +5v v i 2 c scl sda measurement point input signal 2 3 4 5 6 7 8 9 11 12 13 14 15 16 17 18 19 21 22 23 24 25 26 27 28 29 31 32 33 34 35 36 37 38 39 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 10 20 30 40 1 10 f 1 f 10 f 10 f 1 f 10 f 10 f 10 f 10 f 1 f 1 f 1 f 1 f 1 f 1 f 10k ? 1k ? 1k ? 1k ? 1k ? 1k ? 1k ? 1k ? 1k ?
18 CXA2161R i 2 c control data format slave address a data1 a data2 a data3 a data4 a datan a p s s: start condition a: acknowledge p: stop condition address = 90h i 2 c data structure (write mode) address data1 data2 data3 data4 data5 data6 data7 b7 1 rin1/lin1 gain control mono switch tv aud mute tv input mute tv vol bypass output limit logic level tv mono switch vcr mono switch fnc level vcr video switch vcr input mute sync sel vin5 clamp vin7 clamp vin3 clamp mixer control zcd vout5 0v enable vout6 enable vout5 enable vout4 enable vout3 enable vout2 enable vout1 rgb gain tv video switch fnc follow fnc dir fast blank tv audio select vcr audio select b6 0 b5 0 volume control b4 1 b3 0 b2 0 b1 0 b0 0 = write tv aud mute phono bypass overlay enable address data b7 1 not used not used zero cross status p.o.d. not used sync detect fnc_vcr b6 0 b5 0 b4 1 b3 0 b2 0 b1 0 b0 1 = read i 2 c data structure (read mode) note) zcd = zero cross detect p.o.d. = power on detect
19 CXA2161R video i 2 c write structure video switch 1: tv output [data 5 bits 0, 1, 2] switch setting blue vout1 green vout2 r/c vout3 cvbs/y vout4 comment 0 xxxxx000 1 xxxxx001 2 xxxxx010 3 xxxxx011 4 xxxxx100 5 xxxxx101 6 xxxxx110 7 xxxxx111 encoder blue vin1 bias vcr blue vin2 bias bias encoder blue vin1 bias bias encoder green vin3 bias vcr green vin4 bias bias encoder green vin3 bias bias encoder red vin5 encoder chrominance vin6 vcr chrominance/red vin7 bias encoder chrominance vin5 encoder red vin5 aux chrominance vin13 bias encoder cvbs vin8 encoder luminance vin9 vcr cvbs/y vin10 tv cvbs vin11 encoder luminance vin3 aux cvbs vin12 aux cvbs/y vin12 bias digital encoder rgb or cvbs digital encoder y/c vcr y/c or rgb tv digital encoder y/c encoder rgb and aux cvbs aux y/c or cvbs video mute (power on default) after power on all tv outputs are off (high impedance output) and muted. tv rgb gain control [data 5 bits 3, 4] i 2 c setting rgb gain extra gain/db 0 xxx00xxx 1 xxx01xxx 2 xxx10xxx 3 xxx11xxx 0 (power on default) +1 +2 +3
20 CXA2161R video switch 2: vcr output [data 5 bits 5, 6, 7] switch setting chrominance vout5 cvbs/y vout6 comment 0 000xxxxx 1 001xxxxx 2 010xxxxx 3 011xxxxx 4 100xxxxx 5 101xxxxx 6 110xxxxx 7 111xxxxx encoder chrominance vin5 encoder chrominance vin6 vcr chrominance vin7 bias encoder chrominance vin5 bias aux chrominance vin13 bias encoder cvbs/y vin8 encoder cvbs/y vin9 vcr cvbs/y vin10 tv cvbs vin11 encoder luminance vin3 aux cvbs vin12 aux cvbs/y vin12 bias digital encoder y/c digital encoder y/c or cvbs vcr y/c tv cvbs encoder y/c aux cvbs aux y/c or cvbs video mute (power on default) after power on vcr outputs are off (high impedance) and muted. mixer control [data 6 bits 0, 1] i 2 c setting mixer output vout7 0 xxxxxx00 1 xxxxxx01 2 xxxxxx10 3 xxxxxx11 no mix, vout7 = vout4 (cvbs) mix of vout4 (y) + vout3 (c) no mix, vout7 = vin8 (cvbs) no mix, vout7 = vout4 (cvbs) (power on default) input clamp control vin3 clamp [data 6 bit 2] xxxxx0xx = green input on vin3. dc restore clamp active. (power on default.) xxxxx1xx = cvbs input on vin3. sync tip clamp active. input clamp control vin7 clamp [data 6 bit 3] xxxx0xxx = chrominance input on vin7. chrominance bias applied. (power on default.) xxxx1xxx = red input on vin7. dc restore clamp applied. input clamp control vin5 clamp [data 6 bit 4] xxx0xxxx = red input on vin5. dc restore clamp applied. (power on default.) xxx1xxxx = chrominance input on vin5. chrominance bias applied.
21 CXA2161R sync select control for rgb dc restore circuits sync_sel [data 6 bits 5, 6] when the tv output is set to rgb + y/cvbs mode. then it is necessary to select the input that contains the sync information for the rgb signal. this will normally be the digital encoder cvbs or vcr cvbs input. i 2 c setting sync sel input with sync 0 x00xxxxx 1 x01xxxxx 2 x10xxxxx 3 x11xxxxx vin8 (power on default) vin9 vin10 vin12 standby mode control [data 7 bits 0, 1, 2, 3, 4, 5] the video outputs vout1, 2, 3, 4, 5, 6 can be individually turned off using data byte 7. 0 = video output off. (power on default) 1 = video output on. note) when switched off, the video outputs are in a high impedance state. with a normal 150 ? load, the outputs will be pulled to 0v. bi-directional line control on vcr scart. vout5_0v [data 7 bit 6] x0xxxxxx = vout5 active. connected to input specified in vcr switch table. x1xxxxxx = vout5 set to 0v (power on default) 6db vout5 0v vcr scart pin 15 red in chrominance in chrominance out vout5 chrominance out red in chrominance in vin_7 i = 6ma (when set to 0v mode) 75 ? fig 5. bi-directional line to vcr as pin 15 on the vcr scart can be bi-directional, either chrominance output or red/chrominance input, it is necessary for output vout5 to be individually controlled. when the vcr inputs red/chrominance signals, the output vout5 is set to 0v giving the required line impedance of 75 ? .
22 CXA2161R i 2 c audio signal control channel select tv (phono), vcr [data 2, 3 bits 1, 2] switch setting rtv, phono_r, rout1 ltv, phono_l, lout1 0 xxxxx00x 1 xxxxx01x 2 xxxxx10x 3 xxxxx11x rin1 rin2 rin3 rin4 lin1 lin2 lin3 lin4 after power on rin4/lin4 are selected. mono switch tv [data 2 bits 3, 4, 5] switch setting connection to r channel output connection to l channel output 0 xx000xxx 1 xx001xxx 2 xx010xxx 3 xx011xxx 4 xx100xxx 5 xx101xxx 6 xx110xxx 7 xx111xxx r (r + l mix) l r l r r r l (r + l mix) r r l l l l comment normal mono mix channel swap right channel only left channel only normal normal normal (power on default) mono switch vcr [data 3 bits 3, 4, 5] switch setting connection to r channel output connection to l channel output 0 xx000xxx 1 xx001xxx 2 xx010xxx 3 xx011xxx 4 xx100xxx 5 xx101xxx 6 xx110xxx 7 xx111xxx r (r + l mix) l r l r r x l (r + l mix) r r l l l x comment normal mono mix channel swap right channel only left channel only normal normal all audio outputs disabled (rtv, ltv, phono_r, phono_l, mono, rout1, lout1) (power on default)
23 CXA2161R phono bypass [data 2 bit 0] xxxxxxx0 = phono outputs connected after volume control block. (power on default) xxxxxxx1 = phono outputs connected before volume control block. tv vol bypass [data 2 bit 6] x0xxxxxx = tv outputs connected after volume control block. (power on default) x1xxxxxx = tv outputs connected before volume control block. mono switch [data 2 bit 7] 0xxxxxxx = mono output connected to mix of tv r + l channels. (power on default) 1xxxxxxx = mono output connected to mix of rin1 + lin1 inputs. volume control [data 1 bits 1, 2, 3, 4, 5] setting volume gain 0 xx00000x 1 xx00001x 2 xx00010x 3 xx00011x 4 xx00100x 5 xx00101x 6 xx00110x 7 xx00111x 8 xx01000x 9 xx01001x 10 xx01010x 11 xx01011x : 31 xx11111x +6db +4db +2db 0db (power on default) 2db 4db 6db 8db 10db 12db 14db 16db : 56db audio rin1/lin1 gain [data 1 bits 6, 7] setting input attenuation 0 00xxxxxx 1 01xxxxxx 2 10xxxxxx 3 11xxxxxx 6db (power on default) (note 1) 3db +0db +3db note 1) the power on default is 6db. as the output amplifiers have a nominal +6db gain the overall input to output gain is 0db.
24 CXA2161R overlay enable [data3 bit 0] xxxxxxx0 = overlay off (power on default) xxxxxxx1 = overlay on: rin3 and lin3 are mixed and added to rin1, lin1 channels. rin1 and lin1 are attenuated by 16db before mixing with the tone. tv mute and zero cross operation when the zero cross is switched on (zcd = 1), volume control changes are only implemented when the audio signal passes though the zero cross point. similarly, when a mute instruction is sent, the tv outputs are only muted when the signal passes the zero cross point. this eliminates any click noise. there are two tv audio mute control bits in the bus map. by having two bits it allows the tv outputs to be muted, the tv channel changed and then un-muted all in one i 2 c write operation. the normal structure for a click free audio channel change is as follows: data 1: mute the tv audio output with the zcd switched on. data 2: change the tv audio source. data 3: un-mute the tv audio output again with the zcd switched on. operation of the mute circuit tv aud mute [data 1 bit 0] [data 3 bit 7] zcd [data 7 bit 7] tv, phono and mono output 0 0 1 1 0 1 0 1 un-mute immediately un-mute on next zero cross mute immediately mute on next zero cross after power on tv audio mute = 1 and zcd are set to 1. tv input mute [data 4 bit 7] 0xxxxxxx = the input to the tv switch is not muted. 1xxxxxxx = the input to the tv switch is muted. (power on default) vcr input mute [data 6 bit 7] 0xxxxxxx = the input to the vcr switch is not muted. 1xxxxxxx = the input to the vcr switch is muted. (power on default) output limit [data 3 bit 6] this will limit the output level of the volume control block to 2.2vrms maximum. 0xxxxxxx = the volume control outputs are not limited. (power on default) 1xxxxxxx = the volume control outputs are limited to 2.2vrms.
25 CXA2161R fast blanking operation (pin 16 on scart), fblk the fast blanking signal instructs the tv to select either the external cvbs information or the external rgb information. this is used to superimpose an on screen display (osd) presentation (normally rgb) upon a cvbs background. fast blanking information has the same nominal phase as the rgb and cvbs signal, and is defined as follows, fast blanking output at scart, 1. cvbs mode: scart pin voltage = 0 to 0.4v 2. rgb mode: scart pin voltage = 1 to 3.0v the threshold voltage is approximately 0.75v at the scart input. fast blanking i 2 c control in the CXA2161R, there are two fast blanking inputs, one associated with the digital encoder input (fblk_in1) and another associated with the vcr rgb/cvbs input (fblk_in2). these can be selected and switched to the output using an i 2 c instruction. in addition, the fast blank output pin can be set to a constant 0v or +3.5v by means of the i 2 c control. hence there are four possible states. these are set according to the following table. fast_blank [data 4 bits 0, 1] i 2 c setting blank_level fast blank output pin voltage 0 xxxxxx00 1 xxxxxx01 2 xxxxxx10 3 xxxxxx11 0v (power on default) same level as fast blank in 1 (0/+3.5v) same level as fast blank in 2 (0/+3.5v) +3.5v fast blank output interface the fast blanking output pin is connected to the scart via a 75 ? resistor. tv_fblk 0v/+3.5v 75 ? 75 ? scart line 16 tv CXA2161R fig. 6. fast blanking output interface
26 CXA2161R function switching operation (pin 8 on scart) the function switch facility is designed to read the status of the scart function pin 8 from the vcr scart connector and store this in the status register. both, vcr and tv function lines can be set to outputs and controlled by i 2 c. the tv function line has two modes, the first being control via i 2 c and secondly the follow mode where the output will follow the same state as the vcr input. setting the direction for the function lines the input and control for the function lines is set by the fnc_dir and fnc_follow bits. fnc_follow [data 4 bit 3] fnc_dir [data 4 bit 2] vcr pin 8 tv pin 8 0 0 1 1 0 1 0 1 input (level stored in read register) output controlled by fnc_level input (level stored in read register) output controlled by fnc_level output holds previous level output follows same level as vcr input output (both set to same voltage controlled by fnc_level) fnc_level [data 4 bits 4, 5] these bits set the voltage at the (tv_fnc or vcr_fnc) outputs. the output is determined by the table above. i 2 c control fnc_level voltage at output 0 xx00xxxx 1 xx01xxxx 2 xx10xxxx 3 xx11xxxx < 2v > 4.5v, < 7v < 2v > 9.5v mode internal tv external scart input 16:9 mode internal tv external scart input 4:3 mode note) after power on the output is internal tv mode ie. 0v at the pin. fnc_vcr +12v_dig inside tv < 2v > 9.5v > 4.5 < 7v 10k ? scart pin 8 scart pin 8 fnc_tv 10k ? fig. 7. tv function switch output
27 CXA2161R logic and interrupt output these open collector output pins can be used for an interrupt line to a microprocessor or as a general purpose logic output. interrupt output the intrupt pin will become a current sink for approximately 2s when the vcr input function line changes from: a) 0 to 6v, 6 to 0v b) 0 to 12v, 12 to 0v c) 6 to 12v, 12 to 6v this pin will normally be connected to +5v through a 10k ? resistor. logic output the logic output level can be changed using the logic output bit in the i 2 c register, logic_level. logic level [data 4 bit 6] x0xxxxxx = current sink mode resulting in < 0.4v saturation voltage on logic pin. (power on default) x1xxxxxx = open collector/high output impedance on logic pin. imax during current sink = 1ma external resistors 10k ? 2 s to microprocessor +3 to 14v intrupt logic 10k ? fig. 8. intrupt and logic line interface
28 CXA2161R read mode status register the following information can be read from the status register: fnc vcr [bits 0, 1] the status register bits 0, 1 hold the level of the input function line input pin voltage fnc_vcr data 8 0 to +2v (default) +4.5 to +7v +9.5 to +12v (internal) (16:9 external) (4:3 external) b1 0 0 1 b0 0 1 1 sync detect [bit 2] once a valid sync signal is detected on the input selected by sync_select this bit is set to 1. the bit is reset to 0 every time the sync_select is changed. it is assumed that when a video input is in-active then the input level will be 0v with minimum noise. pod (power on detect) [bit 4] this bit is set to 1 after power on. it is then changed to 0 after the first i 2 c read. it is used to detect if the supply has been corrupted. if the por bit is read as 1 at any time then the ic should be re-initialized to the correct i 2 c settings. zero cross status [bit 5] this audio function is used to determine if an input audio signal has passed the zero cross point. for dual supply operation the zero cross point is 0v. for single supply, the zero cross point is approximately 6v. input signal bias voltage zero cross point fig. 9. zero cross point 0 = no zero cross detected 1 = signal has passed through zero cross point. scart mode
29 CXA2161R description of operation video section inputs and outputs the video section comprises of thirteen (13) high impedance inputs switched through to seven (7) video outputs. an internal +6db amplifier is connected to each output. the amplifier is required to compensate for the 6db attenuation that occurs at the 75 ? series output resistor. the outputs vout_1 to vout_6 are capable of driving 150 ? loads. output vout_7 is designed to interface to an rf modulator but requires an external buffer to drive a 75 ? load. composite/luminance inputs the 4 composite (or luminance) inputs are ac coupled to the input pins. the signals are first sync tip clamped to a set level. these clamps are permanently active, therefore these inputs should only be used for signals with a sync. 2.4v 0v 1vp-p v cc = +5v input signal 0.3v 0v 2vp-p v cc = +5v output signal fig. 10. cvbs/y waveforms rgb inputs the rgb inputs are ac coupled to the input pins. the inputs have a dc restore circuit, which is used to set the blanking level to a fixed voltage. the clamps are controlled by the timing signal provided by the sync detect circuit. it is necessary to select the correct luma or cvbs signal associated with the rgb inputs for the sync select circuit. it is assumed that a sync signal will not be present on any of the rgb input signals. for inputs that can be either red or chrominance then the clamp can be switched between the dc restore mode (for red input) and average level bias (for chrominance). the rgb signals are fed through additional amplifiers that are controlled via i 2 c. these allow the nominal 0.7vp-p signal to be increased to 0.8vp-p, 0.9vp-p or 1vp-p. when the tv output is in y/c mode, the rgb gain should be set to 0db to prevent over amplification of the chrominance output. 2.4v 0v 0.7vp-p v cc = +5v input signal 0.6v 0v 1.4vp-p v cc = +5v output signal fig. 11. rgb waveforms
30 CXA2161R sync detection circuit the clamp signals, used to restore the rgb level, are generated from the sync detect circuit. by using the sync_select control bits, the 4 different cvbs/y inputs may be selected. once selected, the clamped signal is compared with a threshold voltage 65mv above the tip level. if the signal is less than this threshold it is not passed to the next block. if greater than the threshold, it is passed to the discrimination circuit that checks that the duty cycle is greater than 91%. the discrimination block also contains a time constant which, when a sync is detected, holds the status line high for at least 11 video lines. if a valid sync signal is detected the sync_detect bit in the read register is set to 1. comparator duty discrimination logic dig cvbs/y dig cvbs/y vcr cvbs/y aux cvbs/y rgb input clamp timing sync_select status register sync_detect bit i 2 c sync detect circuit external r/c sync_id gnd_vid +5v_vid 68k ? 0.1 f fig. 12. sync detection circuit chrominance inputs the chrominance signals are ac coupled to the input pins. the inputs have a fixed dc bias that sets the average level to approximately 3v for vin_5 & vin_7 and 2.35v for vin_6 & vin_13. for inputs that can also be red signals the input circuit can be switched to the dc restore mode. typical waveforms: 2.35 or 3v 0v 0.7vp-p v cc = +5v chrominance input pin voltage 1.8v 0v 1.4vp-p v cc = +5v chrominance output pin voltage fig. 13. chrominance waveforms
31 CXA2161R y/c mixer a y/c mixer can be used for mixing luminance and chrominance signals for use with an external rf modulator connected to vout_7. the y/c mixer is controlled via the i 2 c data bus. the signal may be a mix of the tv y/c signals or simply the tv cvbs signal. it is also possible to select the cvbs signal from the digital encoder. the circuit is shown in fig 14. with a trap circuit used to give 6db attenuation at 4.43mhz of the luminance signal. the output vout_7 cannot drive loads higher than 20k ? resistive. if it is necessary to drive a 75 ? load with this output then an external emitter follower arrangement should be used. 6db 0, 1, 2 or 3db vin_8 = cvbs r/c cvbs/y vout_3 vout_4 vout_7 trap mixer switch for recommended values: see application circuit 6db r c l 2k ? 6db fig. 14. internal y/c mixer circuit switching the video outputs off each video output can be individually turned off using the i 2 c. when turned off, the output is set to a high impedance state and hence the current consumption and power dissipation is reduced. after power on, all the video outputs are set to the high impedance state.
32 CXA2161R typical video interface circuits single or dual supply 100nf 75 ? scart vin_1 to vin_13 fig. 15. video input interface 75 ? (line c = 400pf max) 75 ? scart vout_1 to vout_6 fig. 16. video output interface
33 CXA2161R audio section inputs and outputs the audio system consists of 4 stereo inputs, 2 stereo outputs and separate mono and phono outputs. the stereo outputs can be connected to any one of the 4 stereo inputs. all audio inputs have a 6db attenuator except rin_1 and lin_1. therefore, the net gain of the audio system from input to output is 0db, as an amplifier having +6db of gain follows the internal switch. the stereo input rin_1/lin_1 has extra switchable gain as this input is typically connected to an audio dac with full scale of 1vrms or less. the output impedance of each audio amplifier is near zero, and may be directly coupled to the scart in the case of a dual supply but must be ac coupled through a capacitor (typically 10f) for the single supply case. the outputs are capable of driving 600 ? loads. the user may add additional low pass filters to the outputs. tv output switching the tv audio section is composed of an audio switch followed by a volume control stage. the volume is adjustable from +6db to 56db in 2db steps. the volume control block includes a switchable limiter function to prevent the output signals exceeding 2.2vrms. when activated, the output signals from the volume control block will be clamped to 2.2vrms. a mono switch that allows the mixed r + l signal to be switched to the r and l output channels follows the volume control section. the mono switch is also capable of routing the r signal onto both r and l channel and similarly the l signal to the r and l output channels. this may be used if the audio channels consist of two different languages. it is also capable of swapping the r and l channels. tv mute this i 2 c mute function acts only on the tv, phono and mono audio circuits. audio mute will be implemented after an audio zero cross detection to reduce click noise if zcd = 1. zero cross detector (zcd) the zero cross detector reduces the effect of click noise when implementing a volume change or an audio mute. the volume change or mute instruction sent by i 2 c will only be implemented when a minimal (ie zero cross) signal amplitude is detected. it can be seen from the i 2 c write format that the same mute bit occurs in data1 and data3. this allows the software to action a mute, then after a delay (1/audio_freq (min)) make any suitable changes to the audio source and then un-mute the output buffer. such a period provides ample time to allow any audio signals to pass the zero cross point before the signal source is changed. vcr output switching the outputs rout1, lout1 have a fixed gain of 0db from the input. if any attenuation is required then it is possible to insert a series resistance on the input. again, this output has a mono switching block that allows the mixed r + l to be inserted on both output channels.
34 CXA2161R phono outputs there is a stereo phono output that carries the same signal as the tv output. this is typically used for connection to a hi-fi. the signal level of the phono outputs is normally the same as the tv outputs however it is possible to bypass the volume section and set the phono outputs to a fixed level. if any attenuation is required then this can be done externally. mono output the mono output for the rf modulator has two settings. the first is a mix of the tv r + l channels. in this case, the output signal will have the same volume control as the rtv/ltv outputs. the second setting is a mix of the audio dac inputs (rin_1 + lin_1). in this setting the output will always have fixed volume and if the tone overlay is used, this will appear on the output. audio overlay the inputs rin_3, lin_3 may be used for a normal stereo audio input or alternatively to overlay an external audio source onto the tv outputs. this may be a tone or voice. the r and l inputs are mixed and then added equally to the rin_1 and lin_1 inputs. the i 2 c control bit audio overlay enable is used to switch on this facility and control the attenuator block on rin_3 which is set to give an extra 5db of attenuation when switched on. if two tones are used then it is up to the user to switch them individually before the a/v switch. when the tone overlay is activated, the signals rin_1, lin_1 are attenuated by approximately 16db before mixing. audio disable all the audio outputs may be disabled using the audio output disable function in the vcr mono switching block [data byte 3 bits 3, 4, 5 set to 111]. this disable mode is different from the normal mute as it can be used for power reduction in stand by modes.
35 CXA2161R typical audio interface circuits supply type 1: dual supply scart rin_1, 2, 3, 4 lin_1, 2, 3, 4 0.1 f fig. 17. audio input interface scart to rf modulator optional protection resistor 600 ? to 10k ? (line c = 400pf max) 600 ? to 10k ? (line c = 400pf max) optional protection resistor rtv, ltv rout1, lout1 phono_r, phono_l mono fig. 18. audio output interface supply type 2: single supply scart rin_1, 2, 3, 4 lin_1, 2, 3, 4 0.1 f fig. 19. audio input interface scart to rf modulator the user may use larger capacitors if required. 10 f 600 ? to 10k ? (line c = 400pf max) 600 ? to 10k ? (line c = 400pf max) rtv, ltv rout1, lout1 phono_r, phono_l mono 10 f fig. 20. audio output interface
36 CXA2161R application in set top box vin_1 b b vout_1 g vout_2 r/c vout_3 cvbs/y vout_4 tv_fblk tv_fnc fast blanking function switch c vout_5 cvbs/y vout_6 cvbs vout_7 vin_3 g vin_5 r vin_8 cvbs vin_6 c vin_9 fblk_in1 y fast blanking vin_2 b vin_11 cvbs vin_12 cvbs/y vin_13 c vin_4 g vin_7 r/c vin_10 fblk_in2 vcr_fnc cvbs/y fast blanking function switch digtal encoder vcr vcr rf mod. tv tv aux inputs outputs CXA2161R a/v switch fig. 21. video application with 6 output digital encoder vin_1 b b vout_1 g vout_2 r/c vout_3 cvbs/y vout_4 tv_fblk tv_fnc fast blanking function switch c vout_5 cvbs/y vout_6 cvbs vout_7 vin_3 g/cvbs vin_5 r/c vin_8 fblk_in1 cvbs/y fast blanking vin_6 vin_9 c cvbs/y vin_2 b vin_11 cvbs vin12 cvbs/y vin13 c vin_4 g vin_7 r/c vin_10 fblk_in2 vcr_fnc cvbs/y fast blanking function switch digtal encoder vcr analogue sat. vcr rf mod. tv tv aux inputs outputs CXA2161R a/v switch fig. 22. video application with 4 output digital encoder
37 CXA2161R audio application stb audio dac full scale = 2vrms rin_1 lin_1 vcr fs = 2vrms rin_2 lin_2 tv or stb generated voice/ tone rin_3 lin_3 aux fs = 2vrms rin_4 lin_4 rtv ltv rout1 lout1 phono_r phono_l tv (mono) mono tv lr vcr hi-fi rf modulator l r fig. 23. audio application
38 CXA2161R supply connections +12v ( 0.6v) 5v ( 0.25v) +5v ( 0.25v) +5v/12v_v cc a +12v_dig +5v_dig +5v_vid gnd_vid gnd_dig 5v_gnda aud_bias +5v_vout vid_bias 0.1 f fig. 24. dual supply +12v ( 0.6v) +5v ( 0.25v) +5v/12v_v cc a +12v_dig +5v_dig +5v_vid gnd_vid gnd_dig 5v_gnda aud_bias +5v_vout vid_bias 0.1 f 22 f fig. 25. single ended supply
39 CXA2161R application circuit 1 single ended supply +12v +5v tv_fnc tv_fblank 10k ? vcr_fnc +12v tv_lout vcr_rin vcr_lin tv_rin tv_lin tv_rout vcr_lout vcr_rout 100nf 100nf 100nf 100nf 100nf 100nf digital_audio_r digital audio input digital_audio_l 75 ? vcr_fblank 75 ? vcr_blue 75 ? 75 ? 75 ? vcr_green 100nf 75 ? vcr_red/c 100nf vcr_cvbs_in 100nf 75 ? 68k ? tv_cvbs_in 100nf 100nf 100nf +5v 75 ? 100nf 75 ? 100nf CXA2161R 100nf dig_green dig_blue 75 ? 100nf dig_red 75 ? 100nf dig_chroma 75 ? 100nf dig_cvbs 75 ? 100nf dig_luma 75 ? 100nf aux_y/cvbs 75 ? 100nf aux_c dig_fblank gnd gnd gnd tv_cvbs_out vcr_red/c vcr_cvbs_out +5v scl sda +5v 75 ? 75 ? 100nf 75 ? 1.8k ? 12pf 10k ? 10k ? 100nf tv_red/c 75 ? tv_green 75 ? tv_blue +5v +5v 75 ? aux_l 100 h 10 f 100nf +5v 100nf 10 f supplies 100nf 10 f10 f10 f 10 f 10 f 10 f 10 f 22 f tv 21 19 tv_cvbs_out 17 15 tv_red/c 13 11 tv_green 9 7 tv_blue 5 3 tv_lout 1 tv_rout 20 tv_cvbs_in 18 16 tv_fblank 14 12 10 8 tv_fnc 6 tv_lin 4 2 tv_rin gnd gnd gnd gnd gnd gnd gnd gnd vcr 21 19 vcr_cvbs_out 17 15 vcr_red/c 13 11 vcr_green 9 7 vcr_blue 5 3 vcr_lout 1 vcr_rout 20 vcr_cvbs_in 18 16 vcr_fblank 14 12 10 8 vcr_fnc 6 vcr_lin 4 2 vcr_rin gnd gnd gnd gnd gnd gnd gnd gnd digital encoder inputs aux video inputs digital fast blank +12v vout_7 to rf modulator place close to pin 14 place close to pin 44 place close to pin 24 gnd +5v_vout vout_3 vout_2 vout_1 +5v_vid vid_bias vin_1 vin_3 vin_5 vin_6 vin_8 vin_9 sync_id vin_11 vin_10 vin_7 vln_4 vin_2 gnd_dig tv_fblk fblk_in1 fnc_tv fblk_in2 fnc vcr vout_5 gnd_vid vout_6 vout_7 trap intrupt scl sda logic mono phono_r phono_l 1 2 3 4 5 6 7 8 9 11 12 13 14 15 16 17 18 19 21 22 23 24 25 26 27 28 29 31 32 33 34 35 36 37 38 39 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 10 20 30 40 lout1 rtv ltv +5v/12v_v cc a rin_1 lin_1 5v_gnda rin_2 lin_2 aud_bias rin_3 lin_3 +5v_ dig +12v_ dig lln_4 rin_4 vin_13 aux_r vin_12 vout_4 rout1 application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
40 CXA2161R application circuit 2 dual supply +12v +5v tv_fnc tv_fblank 10k ? vcr_fnc 5v +5v tv_lout vcr_rin vcr_lin tv_rin tv_lin tv_rout vcr_lout vcr_rout 100nf 100nf 100nf 100nf 100nf 100nf digital_audio_r digital audio input digital_audio_l 75 ? vcr_fblank 75 ? vcr_blue 75 ? 75 ? 75 ? vcr_green 100nf 75 ? vcr_red/c 100nf vcr_cvbs_in 100nf 75 ? 68k ? tv_cvbs_in 100nf 100nf 100nf +5v 75 ? 100nf 75 ? 100nf 100nf dig_green dig_blue 75 ? 100nf dig_red 75 ? 100nf dig_chroma 75 ? 100nf dig_cvbs 75 ? 100nf dig_luma 75 ? 100nf aux_y/cvbs 75 ? 100nf aux_c dig_fblank vout_7 to rf modulator gnd gnd gnd tv_cvbs_out vcr_red/c vcr_cvbs_out +5v scl sda +5v 75 ? 75 ? 100nf 75 ? 1.8k ? 12pf 10k ? 10k ? 100nf tv_red/c 75 ? tv_green 75 ? tv_blue +5v +5v 75 ? aux_l 100 h 10 f 10 f 100nf 100nf 100nf 100nf 10 f supplies place close to pin 44 5v v cc +5v tv 21 19 tv_cvbs_out 17 15 tv_red/c 13 11 tv_green 9 7 tv_blue 5 3 tv_lout 1 tv_rout 20 tv_cvbs_in 18 16 tv_fblank 14 12 10 8 tv_fnc 6 tv_lin 4 2 tv_rin gnd gnd gnd gnd gnd gnd gnd gnd vcr 21 19 vcr_cvbs_out 17 15 vcr_red/c 13 11 vcr_green 9 7 vcr_blue 5 3 vcr_lout 1 vcr_rout 20 vcr_cvbs_in 18 16 vcr_fblank 14 12 10 8 vcr_fnc 6 vcr_lin 4 2 vcr_rin gnd gnd gnd gnd gnd gnd gnd gnd digital encoder inputs aux video inputs digital fast blank aux_r 1 2 3 4 5 6 7 8 9 11 12 13 14 15 16 17 18 19 21 22 23 24 25 26 27 28 29 31 32 33 34 35 36 37 38 39 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 10 20 30 40 +12v +5v_vout vout_3 vout_2 vout_1 +5v_vid vid_bias vin_1 vin_3 vin_5 vin_6 vin_8 vin_9 sync_id vin_11 vin_10 vin_7 vln_4 vin_2 gnd_dig tv_fblk fblk_in1 fnc_tv fblk_in2 fnc vcr vout_5 gnd_vid vout_6 vout_7 trap intrupt scl sda logic mono phono_r phono_l lout1 rtv ltv +5v/12v_v cc a rin_1 lin_1 5v_gnda rin_2 lin_2 aud_bias rin_3 lin_3 +5v_ dig +12v_ dig lln_4 rin_4 vin_13 vin_12 vout_4 rout1 CXA2161R place close to pin 21 place close to pin 24 place close to pin 14 application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
41 CXA2161R notes on operation 1) supply de-coupling capacitors, 10nf and 10f in parallel should be inserted as close as possible to the supply pins 14, 15, 24 and 44. when using the dual supply configuration apply the capacitors to pin 21 in addition to the listed supply pins. 2) for best results with dual supply configuration, two +5v supplies should be used, audio (pin 24) and video/digital (pins 14, 44 and 49). 3) to minimize crosstalk, attention should be given to the routing of audio and video to the ic inputs. pcb track lengths should be kept as short as possible and preferably, audio placed on a separate layer to the video. 4) attention should be given to the electrolytic capacitors on the output pins. in single supply configuration the audio pin dc bias voltage will be approximately 6.0v, therefore the positive terminal of the capacitors should be orientated towards the device pin. 5) to minimise stray capacitance the 75 ? series resistor on video outputs vout_1 to vout_6 should be mounted as close as possible to the device pins 47, 46, 45, 44, 41 and 39. 6) when driving video loads with impedance of 75 ? , video output vout_7 (pin 38) must be connected to the load via a buffer or line driver. this buffer should be located close to the output (pin 38). 7) in dual supply mode, series protection resistors may be added on audio outputs which are connected scart connectors.
42 CXA2161R typical performance curves 8 7 6 5 1 gain [db] frequency [mhz] video gain vout_1, 2, 3, 4, 5, 6 10 100 4 3 2 1 0 vout_4, 5, 6 vout_1, 2, 3 8 7 6 5 1 gain [db] frequency [mhz] video gain vout_7 10 100 4 3 2 1 0 mixer off mixer on 0.00 1.00 1 gain [db] frequency [khz] audio gain 100 10 10000 1000 2.00 3.00 4.00 1 0.1 0.00 1.00 2.00 3.00 thd [%] input level [vrms] audio output distortion tv outputs 0.01 0.001 single supply configuration 1 0.1 0.00 1.00 2.00 3.00 thd [%] input level [vrms] audio output distortion rout1, lout1 0.01 0.001 single supply configuration
43 CXA2161R package outline unit: mm sony code eiaj code jedec code package material lead treatment lead material package mass epoxy resin palladium plating copper alloy package structure 56pin lqfp(plastic) detail a note: dimension ? does not include mold protrusion. (0.3) 0.32 0.07 + 0.08 (0.125) 0.145 0.025 + 0.04 0 to 10 (0.5) (11.0) 0.6 0.15 0.25 0.1 0.1 detail b 0.1 0.13 m ? 10.0 0.1 12.0 0.2 0.65 a b 1.7max 0.32 0.07 + 0.08 1 56 14 15 28 29 42 43 lqfp-56p-l01 lqfp056-p-1010 0.3g sony corporation

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