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febuary 2013 ? 2011 fairchild semiconductor corporation 1 www.fairchildsemi.com fan6754wa ? rev. 1.0.6 fan6754wa ? highly integrated green-mode pwm controller fan6754wa highly integrated green-mode pwm controller brownout and v limit adjustment by hv pin features ? high-voltage startup ? ac input brownout protection with hysteresis ? monitor hv to adjust v limit ? low operating current: 1.5 ma ? linearly decreasing pwm frequency to 22 khz ? frequency hopping to reduce emi emission ? fixed pwm frequency: 65 khz ? peak-current-mode control ? cycle-by-cycle current limiting ? leading-edge blanking (leb) ? internal open-loop protection ? gate output maximum voltage clamp: 13 v ? v dd under-voltage lockout (uvlo) ? v dd over-voltage protection (ovp) ? programmable over-temper ature protection (otp) ? internal latch circuit (ovp, otp) ? open-loop protection (olp); restart for fan6754wamrmy, latch for FAN6754WAMLMY ? sense short-circuit protection (sscp) ? built-in 8 ms soft-start function applications general-purpose switch-mode power supplies (smps) and flyback power converters, including: ? power adapters description the highly integrated fan6754wa pwm controller provides several features to enhance the performance of flyback converters. to minimize standby power consumption, a proprietary green-mode function provides off-time modulation to continuously decrease the switching frequency under light-load conditions. under zero-load and very light-load conditions, fan6754wa saves pwm pulses by entering "deep" burst mode. burst mode enables the power supply to meet international power conservation requirements. fan6754wa also integrates a frequency-hopping function that helps reduce emi emission of a power supply with minimum line filters. the built-in synchronized slope compensation helps achieve stable peak-current control. to k eep constant output power limit over universal ac input range, the current limit is adjusted according to ac li ne voltage detected by the hv pin. the gate output is clamped at 13 v to protect the external mosfet from over-voltage damage. other protection functions include ac input brownout protection with hysteresis, sense pin short-circuit protection, and v dd over-voltage protection. for over- temperature protection, an ex ternal ntc thermistor can be applied to sense the external switcher s temperature. when v dd ovp or otp are activated, an internal latch circuit is used to latch-off the controller. the latch mode is reset when the v dd supply is removed. fan6754wa is available in an 8-pin sop package. ordering information part number operating temperature range package packing method fan6754wamrmy -40 to +105c 8-pin, small outline package (sop) tape & reel FAN6754WAMLMY
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fan6754wa ? rev. 1.0.6 2 fan6754wa ? highly integrated green-mode pwm controller application diagram figure 1. typical application internal block diagram figure 2. functional block diagram
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fan6754wa ? rev. 1.0.6 3 fan6754wa ? highly integrated green-mode pwm controller f - fairchild logo z - plant code x - 1-digit year code y - 1-digit week code tt - 2-digit die run code t - package type (m=sop) p - y: package (green) m - manufacture flow code marking information figure 3. top mark pin configuration sop-8 gnd sense vdd rt gate hv nc fb 18 7 6 5 4 2 3 figure 4. pin configuration (top view) pin definitions pin # name description 1 gnd ground . this pin is used for the ground potential of all the pins. a 0.1 f decoupling capacitor placed between vdd and gnd is recommended. 2 fb feedback . the output voltage feedback information from the external compensation circuit is fed into this pin. the pwm duty cycle is determined by this pin and the current-sense signal from pin 6. fan6754wa performs open-loop pr otection (olp); if the fb volt age is higher than a threshold voltage (around 4.6 v) for more than 56 ms , the controller latches off the pwm. 3 nc no connection 4 hv high-voltage startup . this pin is connected to the line input via a 1n4007 and 200 k ? resistor to achieve brownout and high/low line compensation. once the voltage on the hv pin is lower than the brownout voltage, pwm output turns off. high/low line compensation dominates the cycle-by-cycle current limiting to achieve cons tant output power limiting with universal input. 5 rt over-temperature protection . an external ntc thermistor is connected from this pin to gnd. the impedance of the ntc decreases at high te mperatures. once the voltage on the rt pin drops below the threshold voltage, the controller la tches off the pwm. if rt pin is not connected to an ntc resistor for over-temperature protection, a 100 k ? resistor is recommend to connect the rt pin to the gnd pin. this pin is limited by an internal clamping circuit. 6 sense current sense . this pin is used to sense the mosf et current for the current-mode pwm and current limiting. 7 vdd supply voltage . ic operating current and mosfet drivin g current are supplied using this pin. this pin is connected to an external bulk capacit or of typically 47 f. the threshold voltages for turn-on and turn-off are 17 v and 10 v, respectively. the operating current is lower than 2 ma. 8 gate gate drive output . the totem-pole output driver for the power mosfet. it is internally clamped below 13 v. zxytt 6754mr w a tpm zxytt 6754ml w a tpm
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fan6754wa ? rev. 1.0.6 4 fan6754wa ? highly integrated green-mode pwm controller absolute maximum ratings stresses exceeding the absolute maximum ratings may dam age the device. the device may not function or be operable above the recommended operating conditions and stressi ng the parts to these levels is not recommended. in addition, extended exposure to stresses above the recomm ended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter min. max. unit v vdd dc supply voltage (1,2) 30 v v fb fb pin input voltage -0.3 7.0 v v sense sense pin input voltage -0.3 7.0 v v rt rt pin input voltage -0.3 7.0 v v hv hv pin input voltage 500 v p d power dissipation (t a 50c) 400 mw ? ja thermal resistance (junction-to-air) 150 ? c/w t j operating junction temperature -40 +125 ? c t stg storage temperature range -55 +150 ? c t l lead temperature (wave soldering or ir, 10 seconds) +260 ? c esd electrostatic discharge capability, all pins except hv pin human body model; jesd22-a114 5000 v charged device model; jesd22-c101 2000 notes : 1. all voltage values, except differential voltages, ar e given with respect to the network ground terminal. 2. stresses beyond those listed under absolute maximu m ratings may cause permanent damage to the device. 3. esd with hv pin: cdm=1250 v and hbm=500 v. recommended operating conditions the recommended operating conditions table defines the conditions for actual device operation. recommended operating conditions are specified to ens ure optimal performance to the datasheet specificatio ns. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter min. typ. max. unit r hv hv startup resistor 150 200 250 k ?
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fan6754wa ? rev. 1.0.6 5 fan6754wa ? highly integrated green-mode pwm controller electrical characteristics v dd =15 v and t a =25 ? c unless otherwise noted. symbol parameter condition min. typ. max. unit v dd section v op continuously operating voltage 24 v v dd-on start threshold voltage 16 17 18 v v dd-off minimum operating voltage 9 10 11 v v dd-olp i dd-olp off voltage 5.5 6.5 7.5 v v dd-lh threshold voltage on vdd pin for latch-off release voltage 3.5 4.0 4.5 v v dd-ac threshold voltage on vdd pin for disable ac recovery to avoid startup failed v dd-off +2.8 v dd-off +3.3 v dd-off +3.8 v i dd-st startup current v dd-on ? 0.16 v 30 a i dd-op1 operating supply current, pwm operation v dd =20 v, fb=3 v gate open 1.5 2.0 ma i dd-op2 operating supply current, gate stop v dd =20 v, fb=3 v 1.0 1.5 ma i lh operating current at pwm-off phase under latch-off conduction v dd =5 v 30 60 90 a i dd-olp internal sink current under latch- off conduction v dd-olp +0.1 v 170 200 230 a v dd-ovp v dd over-voltage protection 24 25 26 v t d-vddovp v dd over-voltage protection debounce time 75 165 255 s hv section i hv supply current from hv pin v ac =90 v(v dc =120 v), v dd =0 v 2.0 3.5 5.0 ma i hv-lc leakage current after startup hv=700 v, v dd =v dd- off +1 v 1 20 a v ac-off brown-out threshold dc source series r=200 k ? to hv pin see equation 1 92 102 112 v v ac-on brown-in threshold dc source series r=200 k ? to hv pin see equation 2 104 114 124 v ? v ac v ac-on - v ac-off dc source series r=200 k ? to hv pin 6 12 18 v t s-cycle line voltage sample cycle fb > v fb-n 220 s fb < v fb-g 650 t h-time line voltage hold period 20 s t d-ac-off pwm turn-off debounce time fb > v fb-n 65 75 85 ms fb < v fb-g 180 235 290 ms continued on the following page?
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fan6754wa ? rev. 1.0.6 6 fan6754wa ? highly integrated green-mode pwm controller figure 5. brownout circuit figure 6. brownout behavior figure 7. v dd-ac and ac recovery
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fan6754wa ? rev. 1.0.6 7 fan6754wa ? highly integrated green-mode pwm controller electrical characteristics (continued) v dd =15 v and t a =25 ? c unless otherwise noted. symbol parameter conditions min. typ. max. units oscillator section f osc frequency in normal mode center frequency 61 65 69 khz hopping range 3.7 4.2 4.7 t hop hopping period 12.0 13.5 15.0 ms f osc-g green-mode frequency 19 22 25 khz f dv frequency variation vs. v dd deviation v dd =11 v to 22 v 5 % f dt frequency variation vs. temperature deviation t a =-40 to +105 ? c 5 % feedback input section a v input voltage to current-sense a ttenuation 1/4.5 1/4.0 1/3.5 v/v z fb input impedance 14 16 18 k ? v fb-open output high voltage fb pin open 4.8 5.0 5.2 v v fb-olp fb open-loop trigger level 4.3 4.6 4.9 v t d-olp delay time of fb pin open-loop protection 50 56 62 ms v fb-n green-mode entry fb voltage pin, fb voltage (fb =v fb-n ) 2.6 2.8 3.0 v hopping range 3.7 4.2 4.7 khz v fb-g green-mode ending fb voltage pin, fb voltage (fb =v fb-g ) 2.1 2.3 2.5 v hopping range 1.27 1.45 1.62 khz v fb-zdcr fb threshold voltage for zero-duty recovery 1.9 2.1 2.3 v v fb-zdc fb threshold voltage for zero-duty 1.8 2.0 2.2 v continued on the following page? figure 8. v fb vs. pwm frequency pwm frequency f osc f osc-g v fb-n v fb-g v fb-zdc v fb v fb-zdcr
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fan6754wa ? rev. 1.0.6 8 fan6754wa ? highly integrated green-mode pwm controller electrical characteristics (continued) v dd =15 v and t a =25 ? c unless otherwise noted. symbol parameter conditions min. typ. max. units current-sense section t pd delay to output 100 250 ns t leb leading-edge blanking time 230 280 330 ns v limit-l current limit at low line (v ac =86 v) v dc =122 v, series r=200 k ? to hv 0.43 0.46 0.49 v v limit-h current limit at high line (v ac =259 v) v dc =366 v, series r=200 k ? to hv 0.36 0.39 0.42 v v sscp threshold voltage for sense short-circu it protection 0.03 0.05 0.07 v t on-sscp on time for v sscp checking 4.0 4.4 4.8 s t d-sscp delay for sense short-circuit protection v sense <0.05 v 60 120 180 s t ss soft-start time startup time 7 8 9 ms gate section dcy max maximum duty cycle 86 89 92 % v gate-l gate low voltage v dd =15 v, i o =50 ma 1.5 v v gate-h gate high voltage v dd =12 v, i o =50 ma 8 v i gate-sink gate sink current (4) v dd =15 v 300 ma i gate- source gate source current (4) v dd =15 v, gate=6 v 250 ma t r gate rising time v dd =15 v, c l =1 nf 100 ns t f gate falling time v dd =15 v, c l =1 nf 50 ns v gate- clamp gate output clamping voltage v dd =22 v 9 13 17 v rt section i rt output current from rt pin 92 100 108 a v rtth1 over-temperature protection threshold voltage 0.7 v v rt 1.05 v, after 12 ms latch off 1.000 1.035 1.070 v v rtth2 v rt 0.7 v, after 100 s latch off 0.65 0.70 0.75 t d-otp1 over-temperature latch-off debounce v rtth2 v rt v rtth1 fb > v fb-n 14 16 18 ms v rtth2 v rt v rtth1 fb < v fb-g 40 51 62 t d-otp2 v rt < v rtth2 , fb > v fb-n 110 185 260 s v rt < v rtth2 , fb < v fb-g 320 605 890 note : 4. guaranteed by design.
? 2011 fairchild semiconductor corp oration www.fairchildsemi.com fan6754wa ? rev. 1.0.6 9 fan6754wa ? highly integrated green-mode pwm controller typical performance characteristics figure 9. startup current (i dd-st ) vs. temperature figure 10. operation supply current (i dd-op1 ) vs. temperature figure 11. start threshold v oltage (v dd-on ) vs. temperature figure 12. minimum operating voltage (v dd-off ) vs. temperature figure 13. supply current drawn f rom hv pin (i hv ) vs. temperature figure 14. hv pin leakage current after startup (i hv-lc ) vs. temperature figure 15. frequency in no r mal mode ( f osc ) vs. temperature figure 16. maximum duty cycle (dcy max ) vs. temperature
? 2011 fairchild semiconductor corp oration www.fairchildsemi.com fan6754wa ? rev. 1.0.6 10 fan6754wa ? highly integrated green-mode pwm controller typical performance characteristics (continued) figure 17. fb open-loop trigger level (v fb-olp ) vs. temperature figure 18. delay time of fb pin open-loop protection (t d-olp ) vs. temperature figure 19. v dd over-voltage protection (v dd-ovp ) vs. temperature figure 20. output current from rt pin (i rt ) vs. temperature figure 21. over-temperature protection threshold voltage (v rtth1 ) vs. temperature figure 22. over-temperature protection threshold voltage (v rtth2 ) vs. temperature figure 23. brownin (v ac-on ) vs. temperature figure 24. brownout (v ac-off ) vs. temperature
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fan6754wa ? rev. 1.0.6 11 fan6754wa ? highly integrated green-mode pwm controller functional description startup current for startup, the hv pin is connected to the line input through an external diode and resistor; r hv , (1n4007 / 200 k ? recommended). peak startup current drawn from the hv pin is ( v ac 2 ) / r hv and charges the hold- up capacitor through the diode and resistor. when the v dd capacitor level reaches v dd-on , the startup current switches off. at this moment, the v dd capacitor only supplies the fan6754wa to keep the v dd until the auxiliary winding of the ma in transformer provides the operating current. operating current operating current is around 1.5 ma. the low operating current enables better efficiency and reduces the requirement of v dd hold-up capacitance. green-mode operation the proprietary green-mode function provides off-time modulation to reduce the switching frequency in light- load and no-load conditions. v fb , which is derived from the voltage feedback loop, is taken as the reference. once v fb is lower than the threshold voltage (v fb-n ), the switching frequency is continuously decreased to the minimum green-mode frequency of around 22 khz. current sensing / pwm current limiting peak-current-mode control is utilized to regulate output voltage and provide pulse-by-pulse current limiting. the switch current is detected by a sense resistor into the sense pin. the pwm duty cycle is determined by this current-sense signal and v fb , the feedback voltage. when the voltage on the sense pin reaches around v comp = (v fb ?0.6)/4, the switch cycle is terminated immediately. v comp is internally clamped to a variable voltage around 0.46 v for low-line output power limit. leading-edge blanking (leb) each time the power mosfet is switched on, a turn-on spike occurs on the sense-re sistor. to avoid premature termination of the switching pulse, a leading-edge blanking time is built in. during this blanking period, the current-limit comparator is disabled and cannot switch off the gate driver. under-voltage lockout (uvlo) the turn-on and turn-off thresholds are fixed internally at 17v and 10v, respectively. during startup, the hold-up capacitor must be charged to 17 v through the startup resistor to enable the ic. the hold-up capacitor continues to supply v dd until the energy can be delivered from auxiliary winding of the main transformer. v dd must not drop below 10 v during startup. this uvlo hysteresis window ens ures that hold-up capacitor is adequate to supply v dd during startup. gate output / soft driving the bicmos output stage is a fast totem-pole gate driver. cross conduction has been avoided to minimize heat dissipation, increase efficiency, and enhance reliability. the output driver is clamped by an internal 13 v zener diode to protect power mosfet transistors against undesirable gate over voltage. a soft driving waveform is implemented to minimize emi. soft-start for many applications, it is necessary to minimize the inrush current at star tup. the built-in 8ms soft-start circuit significantly reduces the startup current spike and output voltage overshoot. slope compensation the sensed voltage across the current-sense resistor is used for peak-current-mode control and cycle-by-cycle current limiting. built-in slope compensation improves stability and prevents sub-harmonic oscillation. fan6754wa inserts a synchronized, positive-going, ramp at every switching cycle. constant output power limit when the sense voltage across sense resistor r sense reaches the threshold voltage, around 0.46 v for low- line condition, the output gate drive is turned off after a small delay, t pd . this delay introduces an additional current proportional to t pd ? v in / l p . since the delay is nearly constant, regardless of the input voltage v in , higher input voltage results in larger additional power. therefore, the maximum out put power at high line is higher than that of low line. to compensate this variation for a wide ac input range, a power-limiter is controlled by the hv pin to solve the unequal power-limit problem. the power limiter is fed to the inverting input of the current limiting comparator. this results in a lower current limit at high-line in puts than at low-line inputs. brownout and constant power limited by the hv pin unlike previous pwm controllers, the fan6754wa hv pin can detect the ac line voltage to perform brownout protection and line compensation for power limit. using a fast diode and startup resi stor to sample the ac line voltage, the peak value refr eshes and is stored in a register at each sampling cycle. when internal update time is met, this peak value is used for brownout and current-limit level judgment. equation (1) and (2) calculate the level of brown-in or brownout converted to rms value. for power saving, fan6754wa enlarges the sampling cycle to lower the power loss from hv sampling at light-load condition. 2 / ) 1.6 1.6) (r 0.9v ( (rms) v hv on - ac ? ? ? (1) 2 / ) 1.6 1.6) (r 0.81v ( (rms) v hv off - ac ? ? ? (2) where r hv is in k ? .
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fan6754wa ? rev. 1.0.6 12 fan6754wa ? highly integrated green-mode pwm controller the hv pin can perform current limit to shrink the tolerance of over-current protection (ocp) under full range of ac voltage, to linea rly current limit curve, as shown in figure 25. fan6754wa also shrinks the v limit level by half to lower the i 2 r sense loss to increase the heavy-load efficiency. figure 25. linearly current limit curve v dd over-voltage protection (ovp) v dd over-voltage protection prevents damage due to abnormal conditions. if the v dd voltage exceeds the over-voltage protection level (v dd-ovp ) and lasts for t d-vddovp , the pwm pulses are disabled and v dd begins to drop. as v dd drops to v dd-olp , the internal hv startup circuit is activated and v dd is charged to v dd-on to restart ic. over-voltage conditions are usually caused by open feedback loops. sense-pin short-circuit protection the fan6754wa provides safety protection for limited power source (lps) tests. when the sense resistor is shorted by soldering during production, the pulse-by- pulse current limiting loses efficiency for the purpose of providing over-power protection for the unit. the unit may be damaged when the loading is larger than the maximum load. to protect against a short circuit across the current-sense resistor, t he controller is designed to immediately shut down if a continuously low voltage (around 0.05 v/120 s) on t he sense pin is detected. thermal protection an ntc thermistor, r ntc , in series with resistor r a , can be connected from the rt pi n to ground. a constant current, i rt , is output from the rt pin. the voltage on the rt pin can be expressed as v rt =i rt ? (r ntc + r ptc ), where i rt is 100 a. at high am bient temperature, the r ntc is smaller and so that v rt decreased. when v rt is less than 1.035 v (v rtth1 ), the pwm turns off after 16 ms (t d-otp1 ). if v rt is less than 0.7 v (v rtth2 ), the pwm turns off after 185 s (t d-otp2 ). if the rt pin is not connected to ntc resistor for over-temperature protection, connecting a series one 100 k ? resistor to ground to prevent from noise interference is recommended. this pin is limited by an internal clamping circuit. limited power control the fb voltage is pulled high once the power supply cannot sustain the output lo ad, such as during output- short or overload conditions. if the fb voltage remains higher than a built-in threshold for longer than t d-olp , pwm output is turned off. as pwm output is turned off, v dd begins decreasing. when v dd goes below the turn- off threshold (10 v) the controller is totally shut down and v dd is continuously discharged to v dd-olp (6.5 v) by i dd-olp to lower the average input power. this is called two-level uvlo. v dd is cycled again. this protection feature continues as long as the overloading condition persists. this prevents the power supply from overheating due to overloading conditions. noise immunity noise on the current sense or control signal may cause significant pulse-width jitter, particularly in continuous- conduction mode. slope com pensation helps alleviate this problem. good placem ent and layout practices should be followed. avoiding long pcb traces and component leads, locating compensation and filter components near the fan6754wa, and increasing the power mos gate resistance improve performance. 0.38 0.39 0.4 0.41 0.42 0.43 0.44 0.45 0.46 0.47 100 120 140 160 180 200 220 240 260 280 300 320 340 360 380 dc voltage on hv pin (v) vlimit (v)
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fan6754wa ? rev. 1.0.6 13 fan6754wa? highly integrated green-mode pwm controller physical dimensions figure 26. 8-pin, small outline package (sop) package package drawings are provided as a service to customers consi dering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packa ging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . 8 0 see detail a notes: unless otherwise specified a) this package conforms to jedec ms-012, variation aa, issue c, b) all dimensions are in millimeters. c) dimensions do not include mold flash or burrs. d) landpattern sta ndard: soic127p600x175-8m. e) drawing filename: m08arev13 land pattern recommendation seating plane 0.10 c c gage plane x 45 detail a scale: 2:1 pin one indicator 4 8 1 c m ba 0.25 b 5 a 5.60 0.65 1.75 1.27 6.20 5.80 3.81 4.00 3.80 5.00 4.80 (0.33) 1.27 0.51 0.33 0.25 0.10 1.75 max 0.25 0.19 0.36 0.50 0.25 r0.10 r0.10 0.90 0.406 (1.04) option a - bevel edge option b - no bevel edge
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fan6754wa ? rev. 1.0.6 14 fan6754wa? highly integrated green-mode pwm controller
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