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typical connection features ? floating channel designed for bootstrap operation fully operational to +500v or +600v tolerant to negative transient voltage dv/dt immune ? gate drive supply range from 10 to 20v ? undervoltage lockout for both channels ? separate logic supply range from 5 to 20v logic and power ground 5v offset ? cmos schmitt-triggered inputs with pull-down ? cycle by cycle edge-triggered shutdown logic ? matched propagation delay for both channels ? outputs in phase with inputs description the ir2110/ir2113 are high voltage, high speed power mosfet and igbt drivers with independent high and low side referenced output channels. pro- prietary hvic and latch immune cmos technologies enable ruggedized monolithic construction. logic in- puts are compatible with standard cmos or lsttl output. the output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. propagation delays are matched to simplify use in high frequency applications. the floating channel can be used to drive an n-channel power mosfet or igbt in the high side configura- tion which operates up to 500 or 600 volts. packages data sheet no. pd60147-l ir2110/ir2113 high and low side driver product summary v offset (ir2110) 500v max. (ir2113) 600v max. i o +/- 2a / 2a v out 10 - 20v t on/off (typ.) 120 & 94 ns delay matching 10 ns hin up to 500v to load v dd v b v s ho lo com hin lin v ss sd v cc lin v dd sd v ss v cc or 600v 14 lead pdip w/o lead 4 IR2110-1/ir2113-1 14 lead pdip ir2110/ir2113 16 lead soic ir2110s/ir2113s 16 lead pdip w/o leads 4 & 5 ir2110-2/ir2113-2 www.irf.com 1
2 ir2110/ir2113 www.irf.com symbol definition min. max. units v b high side floating supply voltage (ir2110) -0.3 525 (ir2113) -0.3 625 v s high side floating supply offset voltage v b - 25 v b + 0.3 v ho high side floating output voltage v s - 0.3 v b + 0.3 v cc low side fixed supply voltage -0.3 25 v lo low side output voltage -0.3 v cc + 0.3 v dd logic supply voltage -0.3 v ss + 25 v ss logic supply offset voltage v cc - 25 v cc + 0.3 v in logic input voltage (hin, lin & sd) v ss - 0.3 v dd + 0.3 dv s /dt allowable offset supply voltage transient (figure 2) ? 50 v/ns p d package power dissipation @ t a +25c (14 lead dip) ? 1.6 (14 lead dip w/o lead 4) ? 1.5 (16 lead dip w/o l eads 4 & 5) ? 1.6 (16 lead soic) ? 1.25 r thja thermal resistance, junction to ambient (14 lead dip) ? 75 (14 lead dip w/o lead 4) ? 85 (16 lead dip w/o l eads 4 & 5) ? 75 (16llead soic) ? 100 t j junction temperature ? 150 t s storage temperature -55 150 c t l lead temperature (soldering, 10 seconds) ? 300 symbol definition min. max. units v b high side floating supply absolute voltage v s + 10 v s + 20 v s high side floating supply offset voltage (ir2110) note 1 500 (ir2113) note 1 600 v ho high side floating output voltage v s v b v cc low side fixed supply voltage 10 20 v lo low side output voltage 0 v cc v dd logic supply voltage v ss + 4.5 v ss + 20 v ss logic supply offset voltage -5 5 v in logic input voltage (hin, lin & sd) v ss v dd t a ambient temperature -40 125 c absolute maximum ratings absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. all voltage param- eters are absolute voltages referenced to com. the thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. additional information is shown in figures 28 through 35. recommended operating conditions the input/output logic timing diagram is shown in figure 1. for proper operation the device should be used within the recommended conditions. the v s and v ss offset ratings are tested with all supplies biased at 15v differential. typical ratings at other bias conditions are shown in figures 36 and 37. note 1: logic operational for v s of -4 to +500v. logic state held for v s of -4v to -v bs . c/w w v v
3 ir2110/ir2113 www.irf.com symbol definition figure min. typ. max. units test conditions v ih logic ?1? input voltage 12 9.5 ? ? v il logic ?0? input voltage 13 ? ? 6.0 v oh high level output voltage, v bias - v o 14 ? ? 1.2 i o = 0a v ol low level output voltage, v o 15 ? ? 0.1 i o = 0a i lk offset supply leakage current 16 ? ? 50 v b =v s = 500v/600v i qbs quiescent v bs supply current 17 ? 125 230 v in = 0v or v dd i qcc quiescent v cc supply current 18 ? 180 340 v in = 0v or v dd i qdd quiescent v dd supply current 19 ? 15 30 v in = 0v or v dd i in+ logic ?1? input bias current 20 ? 20 40 v in = v dd i in- logic ?0? input bias current 21 ? ? 1.0 v in = 0v v bsuv+ v bs supply undervoltage positive going 22 7.5 8.6 9.7 threshold v bsuv- v bs supply undervoltage negative going 23 7.0 8.2 9.4 threshold v ccuv+ v cc supply undervoltage positive going 24 7.4 8.5 9.6 threshold v ccuv- v cc supply undervoltage negative going 25 7.0 8.2 9.4 threshold i o+ output high short circuit pulsed current 26 2.0 2.5 ? v o = 0v, v in = v dd pw 10 s i o- output low short circuit pulsed current 27 2.0 2.5 ? v o = 15v, v in = 0v pw 10 s static electrical characteristics v bias (v cc , v bs , v dd ) = 15v, t a = 25c and v ss = com unless otherwise specified. the v in , v th and i in parameters are referenced to v ss and are applicable to all three logic input leads: hin, lin and sd. the v o and i o parameters are referenced to com and are applicable to the respective output leads: ho or lo. v a v a symbol definition figure min. typ. max. units test conditions t on turn-on propagation delay 7 ? 120 150 v s = 0v t off turn-off propagation delay 8 ? 94 125 v s = 500v/600v t sd shutdown propagation delay 9 ? 110 140 v s = 500v/600v t r turn-on rise time 10 ? 25 35 t f turn-off fall time 11 ? 17 25 mt delay matching, hs & ls turn-on/off ? ? ? 10 figure 5 ns dynamic electrical characteristics v bias (v cc , v bs , v dd ) = 15v, c l = 1000 pf, t a = 25c and v ss = com unless otherwise specified. the dynamic electrical characteristics are measured using the test circuit shown in figure 3.
4 ir2110/ir2113 www.irf.com hin logic input for high side gate driver output (ho), in phase sd logic input for shutdown lin logic input for low side gate driver output (lo), in phase v ss logic ground v b high side floating supply ho high side gate drive output v s high side floating supply return v cc low side supply lo low side gate drive output com low side return functional block diagram lead definitions symbol description v dd logic supply 14 lead pdip 14 lead pdip w/o lead 4 16 lead pdip w/o leads 4 & 5 16 lead soic (wide body) ir2110/ir2113 IR2110-1/ir2113-1 ir2110-2/ir2113-2 ir2110s/ir2113s part number v b sd lin v dd pulse gen r s q v ss uv detect delay hv level shift v cc pulse filter uv detect v dd /v cc level shift v dd /v cc level shift lo v s com r s q r s rq hin ho lead assignments
5 ir2110/ir2113 www.irf.com figure 1. input/output timing diagram figure 2. floating supply voltage transient test circuit figure 3. switching time test circuit figure 4. switching time waveform definition figure 6. delay matching waveform definitions figure 3. shutdown waveform definitions hin lin t r t on t f t off ho lo 50% 50% 90% 90% 10% 10% sd t sd ho lo 50% 90% hin lin ho 50% 50% 10% lo 90% mt ho lo mt (0 to 500v/600v) hv =10 to 500v/600v
6 ir2110/ir2113 www.irf.com figure 9b. shutdown time vs. voltage figure 8a. turn-off time vs. temperature figure 8b. turn-off time vs. voltage figure 7a. turn-on time vs. temperature figure 7b. turn-on time vs. voltage figure 9a. shutdown time vs. temperature 0 50 100 150 200 250 10 12 14 16 18 20 v bias supply volta g e (v) turn-on delay time (ns) max. t y p. 0 50 100 150 200 250 -50 -25 0 25 50 75 100 125 temperature ( c) turn-on delay time (ns) max. t y p. 0 50 100 150 200 250 -50 -25 0 25 50 75 100 125 temperature ( c) turn-off delay time (ns) max. t y p. 0 50 100 150 200 250 10 12 14 16 18 20 v bias supply volta g e (v) turn-off delay time (ns) max. t y p. 0 50 100 150 200 250 10 12 14 16 18 20 v bias supply volta g e (v) shutdown delay time (ns) max. t y p. 0 50 100 150 200 250 -50 -25 0 25 50 75 100 125 temperature ( c) shutdown delay time (ns) max. t y p.
7 ir2110/ir2113 www.irf.com figure 12a. logic ?1? input threshold vs. temperature figure 12b. logic ?1? input threshold vs. voltage figure 10a. turn-on rise time vs. temperature figure 11a. turn-off fall time vs. temperature figure 11b. turn-off fall time vs. voltage figure 10b. turn-on rise time vs. voltage 0 20 40 60 80 100 -50 -25 0 25 50 75 100 125 temperature ( c) turn-on rise time (ns) t y p. 0 20 40 60 80 100 10 12 14 16 18 20 v bias supply volta g e (v) turn-on rise time (ns) max. t y p. 0 10 20 30 40 50 -50 -25 0 25 50 75 100 125 temperature ( c) turn-off fall time (ns) max. t y p. 0 10 20 30 40 50 10 12 14 16 18 20 v bias supply volta g e (v) turn-off fall time (ns) max. t y p. 0.0 3.0 6.0 9.0 12.0 15.0 -50 -25 0 25 50 75 100 125 temperature ( c) logic "1" input threshold (v) min. 0.0 3.0 6.0 9.0 12.0 15.0 5 7.5 10 12.5 15 17.5 20 v dd lo g ic supply volta g e (v) logic "1" input threshold (v) min. max max
8 ir2110/ir2113 www.irf.com figure 13a. logic ?0? input threshold vs. temperature figure 13b. logic ?0? input threshold vs. voltage figure 14a. high level output vs. temperature figure 14b. high level output vs. voltage figure 15b. low level output vs. voltage figure 15a. low level output vs. temperature 0.0 3.0 6.0 9.0 12.0 15.0 -50 -25 0 25 50 75 100 125 temperature ( c) logic "0" input threshold (v) max. 0.0 3.0 6.0 9.0 12.0 15.0 5 7.5 10 12.5 15 17.5 20 v dd lo g ic supply volta g e (v) logic "0" input threshold (v) max. 0.00 1.00 2.00 3.00 4.00 5.00 -50 -25 0 25 50 75 100 125 temperature ( c) high level output voltage (v) max. 0.00 0.20 0.40 0.60 0.80 1.00 -50 -25 0 25 50 75 100 125 temperature ( c) low level output voltage (v) max. 0.00 1.00 2.00 3.00 4.00 5.00 10 12 14 16 18 20 v bias supply volta g e (v) high level output voltage (v) min. min. 0.00 0.20 0.40 0.60 0.80 1.00 10 12 14 16 18 20 v bias supply volta g e (v) low level output voltage (v)
9 ir2110/ir2113 www.irf.com figure 16b. offset supply current vs. voltage figure 16a. offset supply current vs. temperature figure 18a. v cc supply current vs. temperature figure 18b. v cc supply current vs. voltage figure 17a. v bs supply current vs. temperature figure 17b. v bs supply current vs. voltage 0 125 250 375 500 625 10 12 14 16 18 20 v cc fixed supply volta g e (v) v cc supply current (a) max. t y p. 0 125 250 375 500 625 -50 -25 0 25 50 75 100 125 temperature ( c) v cc supply current (a) max. t y p. 0 100 200 300 400 500 -50 -25 0 25 50 75 100 125 temperature ( c) v bs supply current (a) max. t y p. 0 100 200 300 400 500 10 12 14 16 18 20 v bs floatin g supply volta g e (v) v bs supply current (a) max. t y p. 0 100 200 300 400 500 0 100 200 300 400 500 600 v b boost voltage (v) offset supply leakage current (a) max. 0 100 200 300 400 500 -50 -25 0 25 50 75 100 125 temperature ( c) offset supply leakage current (a) max. ir2110 ir2113
10 ir2110/ir2113 www.irf.com figure 21a. logic ?0? input current vs. temperature figure 21b. logic ?0? input current vs. voltage figure 19a. v dd supply current vs. temperature figure 19b. v dd supply current vs. voltage figure 20a. logic ?1? input current vs. temperature figure 20b. logic ?1? input current vs. voltage 0 20 40 60 80 100 -50 -25 0 25 50 75 100 125 temperature ( c) v dd supply current (a) max. t y p. 0 20 40 60 80 100 5 7.5 10 12.5 15 17.5 20 v dd lo g ic supply volta g e (v) v dd supply current (a) max. t y p. 0 20 40 60 80 100 -50 -25 0 25 50 75 100 125 temperature ( c) logic "1" input bias current (a) max. t y p. 0 20 40 60 80 100 5 7.5 10 12.5 15 17.5 20 v dd lo g ic supply volta g e (v) logic "1" input bias current (a) 0.00 1.00 2.00 3.00 4.00 5.00 -50 -25 0 25 50 75 100 125 temperature ( c) logic "0" input bias current (a) max. 0.00 1.00 2.00 3.00 4.00 5.00 5 7.5 10 12.5 15 17.5 20 v dd lo g ic supply volta g e (v) logic "0" input bias current (a) max.
11 ir2110/ir2113 www.irf.com 6.0 7.0 8.0 9.0 10.0 11.0 -50 -25 0 25 50 75 100 125 temperature ( c) v cc undervoltage lockout + (v) max. t y p. min. 6.0 7.0 8.0 9.0 10.0 11.0 -50 -25 0 25 50 75 100 125 temperature ( c) v bs undervoltage lockout + (v) max. t y p. min. figure 22. v bs undervoltage (+) vs. temperature figure 23. v bs undervoltage (-) vs. temperature figure 24. v cc undervoltage (+) vs. temperature figure 25. v cc undervoltage (-) vs. temperature figure 26a. output source current vs. temperature figure 26b. output source current vs. voltage 6.0 7.0 8.0 9.0 10.0 11.0 -50 -25 0 25 50 75 100 125 temperature ( c) v bs undervoltage lockout - (v) max. t y p. min. 6.0 7.0 8.0 9.0 10.0 11.0 -50 -25 0 25 50 75 100 125 temperature ( c) v cc undervoltage lockout - (v) max. t y p. min. 0.00 1.00 2.00 3.00 4.00 5.00 10 12 14 16 18 20 v bias supply volta g e (v) output source current (a) min. t y p. 0.00 1.00 2.00 3.00 4.00 5.00 -50 -25 0 25 50 75 100 125 temperature ( c) output source current (a) min. t y p.
12 ir2110/ir2113 www.irf.com figure 28. ir2110/ir2113 t j vs. frequency (irfbc20) r gate = 33 ? ? ? ? ? , v cc = 15v figure 29. ir2110/it2113 t j vs. frequency (irfbc30) r gate = 22 ? ? ? ? ? , v cc = 15v figure 27b. output sink current vs. voltage figure 27a. output sink current vs. temperature figure 31. ir2110/ir2113 t j vs. frequency (irfpe50) r gate = 10 ? ? ? ? ? , v cc = 15v figure 30. ir2110/ir2113 t j vs. frequency (irfbc40) r gate = 15 ? ? ? ? ? , v cc = 15v 0.00 1.00 2.00 3.00 4.00 5.00 10 12 14 16 18 20 v bias supply volta g e (v) output sink current (a) min. t y p. 0 25 50 75 100 125 150 1e+2 1e+3 1e+4 1e+5 1e+6 frequency (hz) junction temperature (c) 320v
10v

1e+2 1e+3 1e+4 1e+5 1e+6 frequency (hz) junction temperature ( c) 320v 140v 10v 0 25 50 75 100 125 150 1e+2 1e+3 1e+4 1e+5 1e+6 frequency (hz) junction temperature ( c) 320v 140v 10v 0 25 50 75 100 125 150 1e+2 1e+3 1e+4 1e+5 1e+6 frequency (hz) junction temperature ( c) 320v 140v 10v 0.00 1.00 2.00 3.00 4.00 5.00 -50 -25 0 25 50 75 100 125 temperature ( c) output sink current (a) min. t y p.
13 ir2110/ir2113 www.irf.com figure 32. ir2110s/ir2113s t j vs. frequency (irfbc20) r gate = 33 ? ? ? ? ? , v cc = 15v figure 33. ir2110s/ir2113s t j vs. frequency (irfbc30) r gate = 22 ? ? ? ? ? , v cc = 15v figure 36. maximum v s negative offset vs. v bs supply voltage figure 37. maximum v ss positive offset vs. v cc supply voltage figure 34. ir2110s/ir2113s t j vs. frequency (irfbc40) r gate = 15 ? ? ? ? ? , v cc = 15v figure 35. ir2110s/ir2113s t j vs. frequency (irfpe50) r gate = 10 ? ? ? ? ? , v cc = 15v 0 25 50 75 100 125 150 1e+2 1e+3 1e+4 1e+5 1e+6 frequency (hz) junction temperature ( c) 320v 140v 10v 0 25 50 75 100 125 150 1e+2 1e+3 1e+4 1e+5 1e+6 frequency (hz) junction temperature ( c) 320v 140v 10v 0 25 50 75 100 125 150 1e+2 1e+3 1e+4 1e+5 1e+6 frequency (hz) junction temperature ( c) 320v 140v 10v 0 25 50 75 100 125 150 1e+2 1e+3 1e+4 1e+5 1e+6 frequency (hz) junction temperature ( c) 320v 140v 10v -10.0 -8.0 -6.0 -4.0 -2.0 0.0 10 12 14 16 18 20 v bs floatin g supply volta g e (v) v s offset supply voltage (v) t y p. 0.0 4.0 8.0 12.0 16.0 20.0 10 12 14 16 18 20 v cc fixed supply volta g e (v) v ss logic supply offset voltage (v) t y p.
14 ir2110/ir2113 www.irf.com 01-3002 03 14 lead pdip 14 lead pdip w/o lead 4 01-3008 02 case outlines
15 ir2110/ir2113 www.irf.com 16 lead soic (wide body) 01-3014 03 16 lead pdip w/o leads 4 & 5 01-3010 02 4/12/2000

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