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1 16 megabit flashbank memory LE28BW168T 1 sanyo electric co.,ltd. semiconductor company 1-1-1 sakata oizumi gunma japan r.1.10(12/22/99) no.xxxx-1/20 features: ? single 3.0-volt read and write operations ? separate memory banks by address space ? simultaneous read and write capability ? superior reliability ? endurance: 10,000 cycles ? data retention: 10 years ? low power consumption ? active current, read: 10 ma (typical) ? active current, read & write: 30 ma (typical) ? standby current: 5a (typical) ? auto low power mode current: 5a (t ypical) ? fast write operation ? bank erase + program: 8 sec (typical) ? block erase + program: 500 ms (typical) ? sector erase + program: 30 ms (typical) ? fixed erase, program, write times ? does not change after cycling ? read access time ? 80/90 nsec ? latched address and data ? end of write detection ? toggle bit ? data # polling ? flash bank: two small erase element sizes ? 1k words per sector or 32k words per block ? erase either element before word program ? cmos i/o compatibility ? packages available ? 48-pin tsop ? continuous hardware and software data protection (sdp) product description the LE28BW168T consists of two memory banks, 2 each 512k x 16 bits sector mode flash eeprom manufactured with sanyo's proprietary, high performance flashtechnol- ogy. the LE28BW168T writes with a 3.0-volt-only power supply. the LE28BW168T is divided into two separate memory banks, 2 each 512k x 16 flash banks. each flash bank is typically used for program code storage and contains 512 sectors, each of 1k words or 16 blocks, each of 32k words. the flash banks may also be used to store data. any bank may be used for executing code while writing data to a different bank. each memory bank is controlled by separate bank selection address (a19) lines. the LE28BW168T inherently uses less energy during erase, and program than alternative flash technologies. the total energy consumed is a function of the applied voltage, current, and time of application. since for any given voltage range, the flash technology uses less current to program and has a shorter erase time, the total energy consumed during any erase or program operation is less than alternative flash technologies. the auto low power mode automatically reduces the active read current to approximately the same as standby; thus, providing an average read current of approxi- mately 1 ma/mhz of read cycle time. the flash technology provides fixed erase and program times, independent of the number of erase/program cycles that have occurred. therefore the system software or hard- ware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose erase and pro- gram times increase with accumulated erase/program cycles. device operation the LE28BW168T operates as two independent 8 megabit word pogram, sector erase flash eeproms. all memory banks share common address lines, i/o lines, we#, and oe#. memory bank selection is by bank select address. we# is used with sdp to control the erase and program operation in each memory bank. the LE28BW168T provides the added functionality of being able to simultaneously read from one memory bank while erasing, or programming to one other memory bank. once the internally controlled erase or program cycle in a memory bank has commenced, a different memory bank can be accessed for read. also, once we# and ce# are high during the sdp load sequence, a different bank may be accessed to read. LE28BW168T which selectes a bank by a address. it can be used as a normal conventinal flash memory when operats erase or program operation to only a bank at non-concurrent operation. the device id cannot be accessed while any bank is writing, erasing, or programming. the auto low power mode automatically puts the LE28BW168T in a near standby mode after data has been accessed with a valid read operation. this reduces the i dd active read current from typically 10ma to typically 5a. preliminary specifications the flash bank product family was jointly developed by sanyo and sillicon storage technology,inc.(sst),under sst's technology l icense. this preliminary specification is subject to change without notice.
2 16 megabit flashbank memory LE28BW168T 2 sanyo electric co.,ltd. semiconductor company 1-1-1 sakata oizumi gunma japan r.1.10(12/22/99) no.xxxx-2/20 the auto low power mode reduces the typical i dd active read current to the range of 1ma/mhz of read cycle time. if a concurrent read while write is being performed, the i dd is reduced to typically 40ma. the device exits the auto low power mode with any address transition or control signal transition used to initiate another read cycle, with no access time penalty. read the read operation of the LE28BW168T flash banks is controlled by ce# and oe#, a chip enable and output enable both have to be low for the system to obtain data from the outputs. oe# is the output control and is used to gate data from the output pins. the data bus is in high impedance state when oe# is high. refer to the timing waveforms for further details (figure 3). when the read operation is executed without address change after power switch on, ce# should be changed the level high to low. if the read operation is executed after programing , ce# should be changed the level high to low. write all write operations are initiated by first issuing the soft- ware data protect (sdp) entry sequence for bank, block, or sector erase. word program in the selected flash bank. word program and all erase commands have a fixed dura- tion, that will not vary over the life of the device, i.e., are independent of the number of erase/program cycles en- dured. either flash bank may be read to another flash bank during the internally controlled write cycle. the device is always in the software data protected mode for all write operations write operations are controlled by toggling we# or ce#. the falling edge of we# or ce#, whichever occurs last, latches the address. the rising edge of we# or ce#, whichever occurs first, latches the data and initiates the erase or program cycle. for the purposes of simplification, the following descrip- tions will assume we# is toggled to initiate an erase or program. toggling the applicable ce# will accomplish the same function. (note, there are separate timing diagrams to illustrate both we# and ce# controlled program or write commands.) word program the word program operation consists of issuing the sdp word program command, initiated by forcing ce# and we# low, and oe# high. the words to be programmed must be in the erased state, prior to programming. the word program command programs the desired addresses word by word. during the word program cycle, the addresses are latched by the falling edge of we#. the data is latched by the rising edge of we#. ( see figure 4-1 for we# or 4-2 for ce# controlled word program cycle timing waveforms, table 3 for the command sequence, and figure 15 for a flowchart. ) during the erase or program operation, the only valid reads from that bank are data# polling and toggle bit. the other bank may be read. the specified bank, block, or sector erase time is the only time required to erase. there are no preprogramming or other commands or cycles required either internally or externally to erase the bank, block, or sector. erase operations the bank erase is initiated by a specific six-word load sequence (see tables 3). a bank erase will typically be less than 70 ms. an alternative to the bank erase in the flash bank is the block or sector erase. the block erase will erase an entire block (32k words) in typically 15 ms. the sector erase will erase an entire sector (1024 words) in typically 15 ms. the sector erase provides a means to alter a single sector using the sector erase and word program modes. the sector erase is initiated by a specific six-word load sequence (see table 3). during any sector, block, or bank erase within a bank, any other bank may be read. bank erase the LE28BW168T provides a bank erase mode, which allows the user to clear the flash bank to the "1"state. this is useful when the entire flash must be quickly erased. the software flash bank erase mode is initiated by issuing the specific six-word loading sequence, as in the software data protection operation. after the loading cycle, the device enters into an internally timed cycle.( see table 3 for specific codes, figure 5-1 for the timing waveform, and figure12 for a flowchart. ) block erase the LE28BW168T provides a block erase mode, which allows the user to clear any block in the flash bank to the "1"state. the software block erase mode is initiated by issuing the specific six-word loading sequence, as in the software data protect operation. after the loading cycle, the device enters into an internally timed erase cycle. (see table 3 for specific codes, figure 5-2 for the timing waveform, and figure 13 for a flowchart.) during the erase operation, the only valid reads are data# polling and toggle bit from the selected bank, other banks may perform normal read. sector erase the LE28BW168T provides a sector erase mode, which allows the user to clear any sector in the flash bank to the
3 16 megabit flashbank memory LE28BW168T 3 sanyo electric co.,ltd. semiconductor company 1-1-1 sakata oizumi gunma japan r.1.10(12/22/99) no.xxxx-3/20 "1"state. the software sector erase mode is initiated by issuing the specific six-word loading sequence, as in the software data protect operation. after the loading cycle, the device enters into an internally timed erase cycle.( see table 3 for specific codes, figure 5-3 for the timing waveform, and figure 14 for a flowchart.) during the erase operation, the only valid reads are data# polling and toggle bit from the selected bank, other banks may perform normal read. write operation status detection the LE28BW168T provides two software means to detect the completion of a flash bank program cycle, in order to optimize the system write cycle time. the software detection includes two status bits : data# polling (dq 7 ) and toggle bit (dq 6 ). the end of write detection mode is enabled after the rising edge of we#, which initiates the internal erase or program cycle. the actual completion of the nonvolatile write is a synchro- nous with the system; therefore, either a data# polling or toggle bit read may be simultaneous with the completion of the write cycle. if this occurs, the system will possibly get an erroneous result, i.e. valid data may appear to conflict with either dq 7 or dq 6 . in order to prevent spurious device rejec- tion, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. if both reads are valid, then the device has completed the write cycle, otherwise the rejection is valid. there is no provision to abort an erase or program operation, once initiated. for the sanyo flash technology, the associ- ated erase and program times are so fast, relative to system reset times, there is no value in aborting the operation. note, reads can always occur from any bank not performing an erase or program operation. should the system reset, while a block or sector erase or word program is in progress in the bank where the boot code is stored, the system must wait for the completion of the operation before reading that bank. since the maximum time the system would have to wait is 25 ms (for a block erase), the system ability to read the boot code would not be affected. data# polling (dq 7 ) when the LE28BW168T is in the internal flash bank program cycle, any attempt to read dq 7 of the last word loaded during the flash bank word load cycle will receive the complement of the true data. once the write cycle is completed, dq 7 will show true data. the device is then ready for the next operation. (see figure 6 for the flash bank data polling timing waveforms and figure 16 for a flowchart.) toggle bit (dq 6 ) during the flash bank internal write cycle, any consecutive attempts to read dq 6 will produce alternating 0's and 1's, i.e. toggling between 0 and 1. when the write cycle is completed, the toggling will stop. the device is then ready for the next operation. (see figure 7 for flash bank toggle bit timing waveforms and figure 16 for a flowchart.) data protection the LE28BW168T provides both hardware and software features to protect nonvolatile data from inadvertent writes. hardware data protection noise/glitch protection: a we# pulse of less than 5 ns will not initiate a write cycle. v dd power up/down detection: the write operation is inhib- ited when v dd is less than 1.5 volts. write inhibit mode: forcing oe# low, ce# high, or we# high will inhibit the write operation. this prevents inadvertent writes during power-up or power-down. software data protection (sdp) the LE28BW168T provides the jedec approved software data protection scheme as a requirement for initiating a write, erase, or program operation. with this scheme, any write operation requires the inclusion of a series of three word-load operations to precede the word program operation. the three- word load sequence is used to initiate the program cycle, providing optimal protection from inadvertent write opera- tions, e.g., during the system power-up or power-down. the six-word sequence is required to initiate any bank, block, or sector erase operation. the requirements for jedec compliant sdp are in byte format. the LE28BW168T is organized by word; therefore, the con- tents of dq 8 to dq 15 are "don't care"during any sdp (3-word or 6-word) command sequence. during the sdp load command sequence, the sdp load cycle is suspended when we# is high. this means a read may occur to any other bank during the sdp load sequence. the bank reserve in sdp load sequence is reserved by the bus cycle of command materialization. if the command sequence is aborted, e.g., an incorrect address is loaded, or incorrect data is loaded, the device will return to the read mode within t rc of execution of the load error. concurrent read and write operations the LE28BW168T provides the unique benefit of being able to read any bank, while simultaneously erasing, or program- ming one other bank. this allows data alteration code to be executed from one bank, while altering the data in another bank. the next table lists all valid states.
4 16 megabit flashbank memory LE28BW168T 4 sanyo electric co.,ltd. semiconductor company 1-1-1 sakata oizumi gunma japan r.1.10(12/22/99) no.xxxx-4/20 product identification table device id codes are unique to each bank. should a chip id be required, any of the bank ids may be used as the chip id. while in the read software id mode, no other operation is allowed until after exiting these modes. product identification mode exit in order to return to the standard read mode, the product identification mode must be exited. exit is accomplished by issuing the software id exit command, which returns the device to normal operation. this command may also be used to reset the device to the read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g., not read correctly. for details, (see table 3 for software operation and figures 9 for timing waveforms.) concurrent read/write state table note: for the purposes of this table, write means to block, sector, or bank erase, or word program as applicable to the appropriate bank. the device will ignore all sdp commands and toggling of we# when an erase or program operation is in progress. note, product identification entry commands use sdp; therefore, this command will also be ignored while an erase or program, operation is in progress. product identification the product identification mode identifies the device manufacturer as sanyo and provides a code to identify each bank. the manufacturer id is the same for each bank; however, each bank has a separate device id. each bank is individually accessed using the applicable bank address and a software command. users may wish to use the device id operation to identify the write algorithm requirements for each bank. (for details, see table 3 for software operation and figures 8 for timing waveforms. ) 1 k n a b2 k n a b d a e rn o i t a r e p o o n d a e re t i r w e t i r wd a e r n o i t a r e p o o ne t i r w e t i r wn o i t a r e p o o n n o i t a r e p o o nd a e r d r o wa t a d d i r e k a mh 0 0 0 0h 2 6 0 0 ) 1 k n a b ( e d o c e c i v e dh 1 0 0 0h 5 9 5 2 ) 2 k n a b ( e d o c e c i v e dh 1 0 0 0h 6 9 5 2 figure 1 : pin description : tsop-1 (10mm x 14mm) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 a15 a14 a13 a12 a11 a10 a9 a8 we# nc a19 nc nc be#3 nc a18 a17 a7 a6 a5 a4 a3 a2 ce# a 16 v ss d q15 d q7 d q14 d q6 d q13 d q5 d q12 d q4 nc v dd d q11 d q3 d q10 d q2 d q9 d q1 d q8 d q0 o e# v ss a0 a1 tsop 48 (10mm x 14mm) normal bend type - i
5 16 megabit flashbank memory LE28BW168T 5 sanyo electric co.,ltd. semiconductor company 1-1-1 sakata oizumi gunma japan r.1.10(12/22/99) no.xxxx-5/20 note)be3# should be connected to v dd signal as usual. l o b m y se m a n n i pn o i t c n u f 9 1 as s e r d d a t c e l e s k n a b . h g i h n e h w 2 k n a b e h t e t a v i t c a o t , w o l n e h w 1 k n a b e h t e t a v i t c a o t 0 a - 8 1 as e s s e r d d a k n a b h s a l fs s e r d d a k n a b h s a l f e d i v o r p o t 5 1 a - 8 1 as e s s e r d d a k c o l b k n a b h s a l f e s a r e r o f k c o l b k n a b h s a l f a t c e l e s o t 0 1 a - 8 1 as e s s e r d d a r o t c e s k n a b h s a l f e s a r e r o f r o t c e s k n a b h s a l f a t c e l e s o t 0 q d - 5 1 q dt u p t u o / t u p n i a t a d e t i r w g n i r u d a t a d t u p n i e v i e c e r d n a e l c y c d a e r g n i r u d a t a d t u p t u o o t . h g i h s i # e c r o h g i h s i # e o n e h w e t a t s i r t n i e r a s t u p t u o e h t . e l c y c # e ce l b a n e p i h c . w o l s i # e c n e h w k n a b h s a l f e h t e t a v i t c a o t # e oe l b a n e t u p t u o. s r e f f u b t u p t u o a t a d e h t e t a g o t # e we l b a n e e t i r w . s n o i t a r e p o m a r g o r p r o e s a r e , e t i r w e h t l o r t n o c o t v d d y l p p u s r e w o p ) s t l o v 3 . 3 s t l o v 0 . 3 ( . y l p p u s s t l o v 0 . 3 e d i v o r p o t d n gd n u o r g c nn o i t c e n n o c o ns n i p d e t c e n n o c n u table1: pin description figure2: functinaly block diagram a19-a0 ce# oe# we# dq15-dq0 512kx16 flash bank1 512kx16 flash bank2 y-decoder x-decoder control logic i/o buffers & data latches charge pump & vref. address buffers & latches
6 16 megabit flashbank memory LE28BW168T 6 sanyo electric co.,ltd. semiconductor company 1-1-1 sakata oizumi gunma japan r.1.10(12/22/99) no.xxxx-6/20 note: entering illegal state during an erase, program, or write operation will not affect the operation, i.e., the erase, prog ram, or write will continue to normal completion. e d o m g n i t a r e p o y a r r a# e c# e o# e wq d9 1 a0 a - 8 1 a d a e r 1 k n a bv l i v l i v h i d t u o v l i a n i 2 k n a bv l i v l i v h i d t u o v h i a n i e s a r e k c o l b 1 k n a bv l i v h i v l i d n i v l i 3 : e l b a t e e s 2 k n a bv l i v h i v l i d n i v h i 3 : e l b a t e e s e s a r e r o t c e s 1 k n a bv l i v h i v l i d n i v l i 3 : e l b a t e e s 2 k n a bv l i v h i v l i d n i v h i 3 : e l b a t e e s m a r g o r p 1 k n a bv l i v h i v l i d n i v l i 3 : e l b a t e e s 2 k n a bv l i v h i v l i d n i v h i 3 : e l b a t e e s y b d n a t sv h i xx z h g i hxx t i b i h n i e t i r wv h i v l i v l i xxx e s a r e k n a b 1 k n a bv l i v h i v l i d n i v l i 3 : e l b a t e e s 2 k n a bv l i v h i v l i d n i v h i 3 : e l b a t e e s e d o m g n i t a r e p o s u t a t s# e c# e o# e wq d9 1 a0 a - 8 1 a n o i t a c i f i t n e d i t c u d o r p 1 k n a bv l i v l i v h i d t u o v l i a 8 1 a - 1 = v l i 2 k n a bv l i v l i v h i d t u o v h i a 0 = v l i r o v h i table:2 operating modes selection
7 16 megabit flashbank memory LE28BW168T 7 sanyo electric co.,ltd. semiconductor company 1-1-1 sakata oizumi gunma japan r.1.10(12/22/99) no.xxxx-7/20 table:3 software command codes notes for software product id command code: 1. command code address format : a14 - a0 are in hex code. 2.with a14 - a0 = 0; sanyo manufacturer code = 0062h is read with a0 = 0. sanyo LE28BW168T device code 2595h, 2596h is read with a0 = 1. 3.the device does not remain in software product id mode if powered down. 4.address form a14 to a18 are 'don't care' for command sequences. a19 is bank selection address has been reserved in last bus cycle of command sequence. 5.data format dq0 to dq7 are in hex and dq8 to dq15 are "don't care". 6.b ax = bank address: a19, l ax = block address:a18 to a15, s ax = sector address: a18 to a10. e d o c d n a m m o cs u b t s 1e l c y cs u b d n 2e l c y cs u b d r 3e l c y cs u b h t 4e l c y cs u b h t 5e l c y cs u b h t 6e l c y c s s e r d d aa t a ds s e r d d aa t a ds s e r d d aa t a ds s e r d d aa t a ds s e r d d aa t a ds s e r d d aa t a d 4 , 1 e t o n5 e t o n4 , 1 e t o n5 e t o n4 , 1 e t o n5 e t o n4 , 1 e t o n5 e t o n4 , 1 e t o n5 e t o n4 , 1 e t o n5 e t o n y r t n e d i e r a w t f o s 5 5 5 5a aa a a 25 5 5 5 5 5 + b x a 0 9 2 e t o n t i x e d i e r a w t f o s 5 5 5 5a aa a a 25 5 5 5 5 5 + b x a 0 f 3 e t o n m a r g o r p d r o w 5 5 5 5a aa a a 25 55 5 5 50 a d r o w s s e r d d a a t a d n i e s a r e r o t c e s 5 5 5 5a aa a a 25 55 5 5 50 85 5 5 5a aa a a 25 5 s x a + b x a 0 3 e s a r e k c o l b 5 5 5 5a aa a a 25 55 5 5 50 85 5 5 5a aa a a 25 5 l x a + b x a 0 5 e s a r e k n a b 5 5 5 5a aa a a 25 55 5 5 50 85 5 5 5a aa a a 25 5 5 5 5 5 + b x a 0 1
8 16 megabit flashbank memory LE28BW168T 8 sanyo electric co.,ltd. semiconductor company 1-1-1 sakata oizumi gunma japan r.1.10(12/22/99) no.xxxx-8/20 : -65oc to +150oc : -0.5v to v dd + 0.5v : -1.0v to v dd + 1.0v : 1.0w : -40oc to +80oc : 3.0v 0.3v : 5 ns : c l = 30 pf [absolute maximum stress ratings] applied conditions greater than those listed under "absolute maximum stress ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions or conditions greater than those define d in the operational sections of this data sheet is not implied. exposure to absolute maximum stress rating conditions may affect de vice reliability. storage temperature d. c. voltage on any pin to ground potential transient voltage (<20 ns) on any pin to ground potential package power dissipation capability (ta = 25oc) [operating range] ambient temperature v dd [ac condition of test] input rise/fall time output load (see figures 10 and 11) [dc operating characteristics] l o b m y sr e t e m a r a pn i mx a mt i n un o i t i d n o c t s e t i d d t n e r r u c y l p p u s r e w o p d a e r e t i r w / e s a r e + d a e r m a r g o r p 0 2 0 4 0 6 a m a m a m v = # e c l i v = # e w , h i , n e p o s ' o / i , u p n i s s e r d d a = t v l i v / t a , h i z h m 0 1 = f , v d d v = d d ) x a m ( v = # e w = # e c l i , v = # e o , h i v d d v = d d ) x a m ( v = # e c l i v = # e w = # e o , h i , = t u p n i s s e r d d a v l i v / h i , t a z h m 0 1 = f , v = # e w , h i v d d v = d d ) x a m ( i b s t n e r r u c y b d n a t s ) t u p n i s o m c ( 0 4a v = # e c , c h i v d d v = d d ) x a m ( i i l i l o t n e r r u c k a e l t u p n i t n e r r u c k a e l t u p t u o 0 1 0 1 a a v n i v o t d n g = , d d v d d v = d d ) x a m ( v t u o v o t d n g = , d d v d d v = d d ) x a m ( v l i v c l i v h i v c h i e g a t l o v w o l t u p n i ) s o m c ( g a t l o v w o l t u p n i g a t l o v h g i h t u p n i ) s o m c ( e g t l o v h g i h t u p n i v d d 8 . 0 * v d d 2 . 0 - v * d d 2 . 0 2 . 0 v v v v v l o v h o g a t l o v w o l t u p t u o g a t l o v h g i h t u p t u o v d d 2 . 0 - 2 . 0 v v i 0 0 1 = l o a ,v d d v = d d ) n i m ( i 0 0 1 - = h o a v , d d v = d d ) n i m (
9 16 megabit flashbank memory LE28BW168T 9 sanyo electric co.,ltd. semiconductor company 1-1-1 sakata oizumi gunma japan r.1.10(12/22/99) no.xxxx-9/20 [capacitance (ta = 25oc, f = 1mhz, other pins open)] note(1): this parameter is measured only for initial qualirication and after a design or process change that could affect th is parameter. [reliability characteristic] note(1): this parameter is measured only for initial qualirication and after a design or process change that could affect this parameter. l o b m y sr e t e m a r a pn o i t i d n o c t s e tx a m c q d ) 1 ( c n i ) 1 ( e c n a t i c a p a c n i p o / i e c n a t i c a p a c t u p n i v q d v 0 = v n i v 0 = f p 2 1 f p 6 l o b m y sr e t e m a r a pc e p s n i ms t i n u n d n e 1 ( ) t r d ) 1 ( e c n a r u d n e n o i t n e t e r a t a d 0 0 0 , 0 1 0 1 r o t c e s / e l c y c s r a e y [recommend system power-up timings] note(1): this parameter is measured only for initial qualification and after a design or process change that could affect t his parameter l o b m y sr e t e m a r a px a ms t i n u t u p d a e r - ) 1 ( t u p e t i r w - ) 1 ( n o i t a r e p o d a e r o t p u - r e w o p n o i t a r e p o e t i r w o t p u - r e w o p 0 0 2 0 0 2 s s
10 16 megabit flashbank memory LE28BW168T 10 sanyo electric co.,ltd. semiconductor company 1-1-1 sakata oizumi gunma japan r.1.10(12/22/99) no.xxxx-10/20 [ac characteristic] read cycle timing parameters write, erase, program cycle, timing parameters note:(1) this parameter is measured only for initial qualification and after a desgin or process change that could affect this parameter. l o b m y sr e t e m a r a p8090s t i n u n i mx a mn i mx a m t c r e m i t e l c y c d e a r0 80 9s n t e c ce m i t s s e c c a # e0 80 9s n t a a e m i t s s e c c a s s e r d d a0 80 9s n t e o e m i t s s e c c a # e o0 40 5s n t z l c ) 1 ( t u p t u o e v i t c a o t w o l # e b00s n t z l o ) 1 ( t u p t u o e v i t c a o t w o l # e o00s n t z h c ) 1 ( t u p t u o z - h g i h o t h g i h # e b0 30 3s n t z h o ) 1 ( t u p t u o z - h g i h o t h g i h # e o0 30 3s n t h o ) 1 ( e g n a h c s s e r d d a m o r f d l o h t u p t u o00s n l o b m y sr e t e m a r a pn i mx a ms t i n u t p b e m i t m a r g o r p d r o w0 2s t e s e m i t e s a r e r o t c e s5 2s m t e l e m i t e s a r e k c o l b5 2s m t e b e m i t e s a r e k n a b0 0 1s m t s a e m i t p u t e s s s e r d d a0s n t h a e m i t d l o h s s e r d d a0 5s n t s e c # e ce m i t p u t e s0s n t h e c e m i t d l o h # e c0s n t s e w # e we m i t p u t e s0s n t h e w e m i t d l o h # e w0s n t s e o e m i t p u t e s h g i h # e o0s n t h e o e m i t d l o h h g i h # e o0s n t p w h t d i w w o l s l u p # e w0 5s n t h p w e m i t h g i h s l u p # e w0 3s n t s d e m i t p u t e s a t a d0 5s n t h d e m i t d l o h a t a d0s n t r d d v ) 1 ( v d d e m i t e s i r1 . 00 5s m t a d i e m i t e l c y c t i x e / d a e r d i0 5 1s n
11 16 megabit flashbank memory LE28BW168T 11 sanyo electric co.,ltd. semiconductor company 1-1-1 sakata oizumi gunma japan r.1.10(12/22/99) no.xxxx-11/20 figure 3: read cycle timing diagram figure 4-1: we# controlled word program cycle timing diagram 16141\168t\f3_e address a 19- a 0 dq 15- dq 0 we# oe# ce# t ce t rc t aa t oe t olz v ih high-z t clz t oh t chz high-z data valid data valid t ohz 16141\168\f4-1_e address a 19- a 0 dq 15- dq 0 t dh t wph t ds t wp t ah t as t ceh t ces ce# sw0 sw1 sw2 5555 2aaa 5555 addr aa 55 a0 data internal program operation starts word (addr/data) oe# we# t bp
12 16 megabit flashbank memory LE28BW168T 12 sanyo electric co.,ltd. semiconductor company 1-1-1 sakata oizumi gunma japan r.1.10(12/22/99) no.xxxx-12/20 figure 4-2: ce# controlled word program cycle timing diagram figure 5-1: bank erase cycle timing diagram 16141\168t\f5-1_e address a 19- a 0 dq 15- dq 0 we# sw0 sw1 sw2 sw3 sw4 sw5 5555 2aaa 2aaa 5555 5555 55 10 55 aa 80 aa 5555+b ax oe# ce# six-byte code for bank erase t be t wp t ah t as t wph t dh t ds 16141\168\f4-2_e address a 19- a 0 dq 15- dq 0 t dh t wph t ds t wp t ah t as t weh t wes we# sw0 sw1 sw2 5555 2aaa 5555 addr aa 55 a0 data internal program operation starts word (addr/data) oe# ce# t bp
13 16 megabit flashbank memory LE28BW168T 13 sanyo electric co.,ltd. semiconductor company 1-1-1 sakata oizumi gunma japan r.1.10(12/22/99) no.xxxx-13/20 figure 5-3: sector erase cycle timing diagram figure 5-2: block erase c ycle timing diagram 16141\168t\f5-2_e address a 19- a 0 dq 15- dq 0 we# sw0 sw1 sw2 sw3 sw4 sw5 5555 2aaa 2aaa 5555 5555 55 50 55 aa 80 aa l ax +b ax oe# ce# six-byte code for block erase t le t wp t ah t as t wph t dh t ds 16141\168t\f5-3_e address a 19- a 0 dq 15- dq 0 we# sw0 sw1 sw2 sw3 sw4 sw5 5555 2aaa 2aaa 5555 5555 55 30 55 aa 80 aa s ax +b ax oe# ce# six-byte code for sector erase t se t wp t ah t as t wph t dh t ds
14 16 megabit flashbank memory LE28BW168T 14 sanyo electric co.,ltd. semiconductor company 1-1-1 sakata oizumi gunma japan r.1.10(12/22/99) no.xxxx-14/20 figure 6: data polling timing diagram figure 7: toggle bit timing diagram 16141\168t\ f6_e dq 7 data data# data# data t oeh t oe t ce t oes address a 19- a 0 we# oe# ce# 16141\168t\f7_e address a 19- a 0 dq 6 we# oe# ce# t oe t oeh t ce t oes two read cycles with same outputs
15 16 megabit flashbank memory LE28BW168T 15 sanyo electric co.,ltd. semiconductor company 1-1-1 sakata oizumi gunma japan r.1.10(12/22/99) no.xxxx-15/20 figure 9: software id exit 16141\168t\f9_e address a 19- a 0 dq 15- dq 0 t ida t wp t wph we# sw0 sw1 sw2 5555 2aaa 5555 +b ax three-byte sequence for software id exit oe# ce# aa 55 f0 figure 8: software id entry and read 16141\168t\f8_e address a 19- a 0 t ida dq 15- dq 0 we# sw0 sw1 sw2 5555 2aaa 5555+b ax ce# three-byte sequence for software id entry t wp t wph t aa 0062 2595/2596 55 aa 90 oe# 0000+b ax 0001+b ax
16 16 megabit flashbank memory LE28BW168T 16 sanyo electric co.,ltd. semiconductor company 1-1-1 sakata oizumi gunma japan r.1.10(12/22/99) no.xxxx-16/20 ac test inputs are driven at v iht (v dd *0.9) for a logic "1"and v ilt (v dd *0.1) for a logic "0" measurement reference points for inputs and outputs are at v ht (v dd *0.7) and v lt (v dd *0.3) input rise and fall times (10% ? 90%) are <10 ns. figure 10: ac i/o referencewaveforms figure 11: a test load example 16141\168t\f11_e to tester to dut c l r l low r l high v dd 16141\168t\f10_e reference points output input v ht v lt v ht v lt v iht v ilt
17 16 megabit flashbank memory LE28BW168T 17 sanyo electric co.,ltd. semiconductor company 1-1-1 sakata oizumi gunma japan r.1.10(12/22/99) no.xxxx-17/20 figure 12: bank erase flowchart bank erase start software data protect bank erase command wait for end of erase (t be , data #polling, or toggle bit) bank erase complete 16141\168t\ f12_e figure 13: block erase flowchart block erase start software data protect block erase flash bank command set block address wait for end of erase (t le , data# polling, or toggle bit) 16141\168t\f13_e block erase complete
18 16 megabit flashbank memory LE28BW168T 18 sanyo electric co.,ltd. semiconductor company 1-1-1 sakata oizumi gunma japan r.1.10(12/22/99) no.xxxx-18/20 figure 14: sector erase flowchart sector erase start software data protect sector erase command set sector address wait for end of erase (t se, data # polling, or toggle bit) 16141\168t\ f14_e sector erase complete
19 16 megabit flashbank memory LE28BW168T 19 sanyo electric co.,ltd. semiconductor company 1-1-1 sakata oizumi gunma japan r.1.10(12/22/99) no.xxxx-19/20 figure 15: word program flowchart word program start software data protect program command set word address load word data word program complete 16141\168t\f15_e wait for end of program (t bp , data # polling, or toggle bit)
20 16 megabit flashbank memory LE28BW168T 20 sanyo electric co.,ltd. semiconductor company 1-1-1 sakata oizumi gunma japan r.1.10(12/22/99) no.xxxx-20/20 figure 16: end of erase or program wait options flowchart internal timer erase or program operation initiated 16141\168t\ f16_e wait for t bp , t se , t le , t be erase or program completed toggle bit data# polling read a word from a bank, block, sector, or word selected read the same word again is dq6 the same? no no ye s read dq7 of the last address set (or any address within selected bank, block, sector for erase) is dq7 same as bit loaded? erase or program operation initiated erase or program operation initiated erase or program completed erase or program completed ye s

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