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1 lt1970 1970fb 500ma power op amp with adjustable precision current limit 500ma minimum output current independent adjustment of source and sink current limits 2% current limit accuracy operates with single or split supplies shutdown/enable control input open collector status flags: sink current limit source current limit thermal shutdown fail safe current limit and thermal shutdown 1.6v/ s slew rate 3.6mhz gain bandwidth product fast current limit response: 2mhz bandwidth specified temperature range: 40 c to 85 c available in a 20-lead tssop package automatic test equipment laboratory power supplies motor drivers thermoelectric cooler driver a v = 2 amplifier with adjustable 500ma full-scale current limit and fault indication current limited sinewave into 10 ? load v cc common v ee v + en v vc src vc snk isnk isrc sense sense + tsd i out out r cs 1 ? 1/4w 3k +in 15v lt1970 15v 15v ?n load r1 10k r2 10k 1970 ta01 v limit 0v to 5v v in v limit 10 ?r cs i out(limit) = the lt 1970 is a 500ma power op amp with precise externally controlled current limiting. separate control voltages program the sourcing and sinking current limit sense thresholds with 2% accuracy. output current may be boosted by adding external power transistors. the circuit operates with single or split power supplies from 5v to 36v total supply voltage. in normal operation, the input stage supplies and the output stage supplies are con- nected (v cc to v + and v ee to v ). to reduce power dissi- pation it is possible to power the output stage (v + , v ) from independent, lower voltage rails. the amplifier is unity-gain stable with a 3.6mhz gain bandwidth product and slews at 1.6v/ s. the current limit circuits operate with a 2mhz re- sponse between the vc src or vc snk control inputs and the amplifier output. open collector status flags signal current limit circuit activation, as well as thermal shutdown of the amplifier. an enable logic input puts the amplifier into a low power, high impedance output state when pulled low. thermal shut- down and a 800ma fixed current limit protect the chip under fault conditions. the lt1970 is packaged in a 20-lead tssop package with a thermally conductive copper bottom plate to facilitate heat sinking. v load 4v 2v 0v ?v vc src = 4v 20 s/div 1970 ta02 vc snk = 2v r cs = 1 ? descriptio u features applicatio s u typical applicatio u , lt, ltc and ltm are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners.
2 lt1970 1970fb (note 1) supply voltage (v cc to v ee ).................................... 36v positive high current supply (v + ) .................. v to v cc negative high current supply(v ) ................... v ee to v + amplifier output (out) ..................................... v to v + current sense pins (sense + , sense , filter) .......................... v to v + logic outputs (isrc, isnk, tsd) ....... common to v cc input voltage (in, +in) .......... v ee ?0.3v to v ee + 36v input current ....................................................... 10ma current control inputs (vc src , vc snk ) ............. common to common + 7v enable logic input .............................. common to v cc common ..................................................... v ee to v cc output short-circuit duration ......................... indefinite operating temperature range (note 2) .. 40 c to 85 c specified temperature range (note 3) ... 40 c to 85 c maximum junction temperature ......................... 150 c storage temperature range ................. 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c order part number lt1970cfe lt1970ife t jmax = 150 c, ja = 40 c/ w (note 8) exposed pad (pin 21) is connected to v ee the denotes specifications which apply over the full operating temperature range, otherwise specifications are t a = 25 c. see test circuit for standard test conditions. absolute axi u rati gs w ww u package/order i for atio uu w electrical characteristics fe package 20-lead plastic tssop 1 2 3 4 5 6 7 8 9 10 top view 20 19 18 17 16 15 14 13 12 11 v ee v out sense + filter sense v cc ?n +in v ee v ee v + tsd isnk isrc enable common vc src vc snk v ee + 21 consult ltc marketing for parts specified with wider operating temperature ranges. symbol parameter conditions min typ max units power op amp characteristics v os input offset voltage 200 600 v 0 c < t a < 70 c 1000 v ?0 c < t a < 85 c 1300 v input offset voltage drift (note 4) ?0 ? 10 v/ c i os input offset current v cm = 0v 100 100 na i b input bias current v cm = 0v ?00 ?60 na input noise voltage 0.1hz to 10hz 3 v p-p e n input noise voltage density 1khz 15 nv/ hz i n input noise current density 1khz 3 pa/ hz r in input resistance common mode 500 k ? differential mode 100 k ? c in input capacitance pin 8 and pin 9 to ground 6 pf v cm input voltage range typical ?4.5 13.6 v guaranteed by cmrr test ?2.0 12.0 v cmrr common mode rejection ratio ?2v < v cm < 12v 92 105 db psrr power supply rejection ratio v ee = v = 5v, v cc = v + = 3v to 30v 90 100 db v ee = v = 5v, v cc = 30v, v + = 2.5v to 30v 110 130 db v ee = v = 3v to 30v, v cc = v + = 5v 90 100 db v ee = 30v, v = 2.5v to 30v, v cc = v + = 5v 110 130 db order options tape and reel: add #tr lead free: add #pbf lead free tape and reel: add #trpbf lead free part marking: http://www.linear.com/leadfree/
3 lt1970 1970fb the denotes specifications which apply over the full operating temperature range, otherwise specifications are t a = 25 c. see test circuit for standard test conditions. electrical characteristics symbol parameter conditions min typ max units a vol large-signal voltage gain r l = 1k, 12.5v < v out < 12.5v 100 150 v/mv 75 v/mv r l = 100 ? , 12.5v < v out < 12.5v 80 120 v/mv 40 v/mv r l = 10 ? , 5v < v out < 5v, v + = v = 8v 20 45 v/mv 5v/mv v ol output sat voltage low v ol = v out ?v r l = 100, v cc = v + = 15v, v ee = v = ?5v 1.9 2.5 v r l = 10, v cc = v ee = 15v, v + = v = 5v 0.8 v v oh output sat voltage high v oh = v + ?v out r l = 100, v cc = v + = 15v, v ee = v = ?5v 1.7 2.3 v r l = 10, v cc = v ee = 15v, v + = v = 5v 1.0 v i sc output short-circuit current output low, r sense = 0 ? 500 800 1200 ma output high, r sense = 0 ? 1000 800 500 ma sr slew rate ?0v < v out < 10v, r l = 1k 0.7 1.6 v/ s fpbw full power bandwidth v out = 10v peak (note 5) 11 khz gbw gain bandwidth product f = 10khz 3.6 mhz t s settling time 0.01%, v out = 0v to 10v, a v = 1, r l = 1k 8 s current sense characteristics v sense(min) minimum current sense voltage vc src = vc snk = 0v 0.1 4 7 mv 0.1 10 mv v sense(4%) current sense voltage 4% of full scale vc src = vc snk = 0.2v 15 20 25 mv v sense(10%) current sense voltage 10% of full scale vc src = vc snk = 0.5v 45 50 55 mv v sense(fs) current sense voltage 100% of full scale vc src = vc snk = 5v 490 500 510 mv 480 500 520 mv i bi current limit control input bias current vc src , vc snk pins ? 0.2 0.1 a i sense sense input current 0v < (vc src , vc snk ) < 5v 500 500 na i filter filter input current 0v < (vc src , vc snk ) < 5v 500 500 na i sense + sense + input current vc src = vc snk = 0v 500 500 na vc src = 5v, vc snk = 0v 200 250 300 a vc src = 0v, vc snk = 5v 300 250 200 a vc src = vc snk = 5v ?5 25 a current sense change with output voltage vc src = vc snk = 5v, 12.5v < v out < 12.5v 0.1 % current sense change with supply voltage vc src = vc snk = 5v, 6v < (v cc , v + ) < 18v 0.05 % 2.5v < v + < 18v, v cc = 18v 0.01 % 18v < (v ee , v ) < 2.5v 0.05 % 18v < v < 2.5v, v ee = 18v 0.01 % current sense bandwidth 2 mhz r csf resistance filter to sense 750 1000 1250 ? logic i/o characteristics logic output leakage isrc, isnk, tsd v = 15v 1 a logic low output level i = 5ma (note 6) 0.2 0.4 v logic output current limit 25 ma v enable enable logic threshold 0.8 1.9 2.5 v i enable enable pin bias current ? 1 a
4 lt1970 1970fb warm-up drift v io vs time input bias current vs v cm symbol parameter conditions min typ max units i supply total supply current v cc , v + and v , v ee connected 713 ma i cc v cc supply current v cc , v + and v , v ee separate 37 ma i cc(stby) supply current disabled v cc , v + and v , v ee connected, v enable 0.8v 0.6 1.5 ma t on turn-on delay (note 7) 10 s t off turn-off delay (note 7) 10 s the denotes specifications which apply over the full operating temperature range, otherwise specifications are t a = 25 c. see test circuit for standard test conditions. electrical characteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the lt1970c is guaranteed functional over the operating temperature range of 40 c and 85 c. note 3: the lt1970c is guaranteed to meet specified performance from 0 c to 70 c. the lt1970c is designed, characterized and expected to meet specified performance from 40 c to 85 c but is not tested or qa sampled at these temperatures. the lt1970i is guaranteed to meet specified performance from 40 c to 85 c. note 4: this parameter is not 100% tested. note 5: full power bandwidth is calculated from slew rate measurements: fpbw = sr/(2 ? ?v p ) note 6: the logic low output level of pin tsd is guaranteed by correlating the output level of pin isrc and pin isnk over temperature. note 7: turn-on and turn-off delay are measured from v enable crossing 1.6v to the out pin at 90% of normal output voltage. note 8: thermal resistance varies depending upon the amount of pc board metal attached to the device. if the maximum dissipation of the package is exceeded, the device will go into thermal shutdown and be protected. typical perfor a ce characteristics uw total supply current vs supply voltage 0v v os ?1000 (50mv/div) time (100ms/div) 1970 g01 common mode input voltage (v) ?5 ?2 9 6 3 0 3 6 9 12 15 input bias current (na) ?00 ?20 ?40 ?60 ?80 200 220 240 260 1970 g02 v s = 15v ? bias +i bias supply voltage ( v) 0 ?4 total supply current (ma) ?0 ? ? 14 6 4 8 10 18 1970 g03 10 2 ?2 ? ? 12 4 8 0 26 12 14 16 i cc + i v + i ee + i v 25 c 25 c ?5 c ?5 c 125 c 125 c
5 lt1970 1970fb typical perfor a ce characteristics uw gain bandwidth vs supply voltage gain vs frequency supply current vs supply voltage open-loop gain and phase vs frequency phase margin vs supply voltage supply voltage ( v) 246 0 supply current (ma) 0.5 1.5 2.0 2.5 14 16 18 4.5 i v + i v 1870 g04 1.0 81012 20 3.0 3.5 4.0 t a = 25 c v cc = v + = ? ee = ? i vcc i vee frequency (hz) 100 1k 10 open-loop gain (db) phase margin (deg) 20 30 40 50 10k 100k 1m 10m 100m 1970 g05 0 ?0 ?0 ?0 60 70 40 50 60 70 80 30 20 10 0 90 100 phase gain total supply voltage (v) 0 40 phase margin (deg) 42 46 48 50 60 54 8 16 20 36 1970 g06 44 56 58 52 412 24 28 32 a v = ? r f = r g = 1k t a = 25 c v out = v s /2 total supply voltage (v) 0 0 gain bandwidth (mhz) 1 3 4 5 8 16 20 36 1970 g07 2 412 24 28 32 a v = 100 frequency (hz) voltage gain (db) 10 ?0 0 ?0 ?0 10k 1m 10m 1970 g08 ?0 100k v s = 15v v s = 5v a v = 1 gain vs frequency with c load frequency (hz) voltage gain (db) 10 ?0 0 ?0 ?0 10k 1m 10m 1970 g09 ?0 100k 30nf 10nf 1nf 0nf v s = 15v a v = 1 output impedance frequency (hz) 1k 10k 0.001 output impedance ( ? ) 0.1 100 100k 1m 10m 100m 1970 g10 0.01 1 10 v s = 15v a v = 100 a v = 1 a v = 10 disabled output impedance frequency (hz) 1k 1 output impedance ( ? ) 100 100k 600k 10k 100k 1m 10m 100m 1970 g11 10 1k 10k v s = 15v v enable = 0.8v slew rate vs supply voltage supply voltage ( v) 4 slew rate (v/ s) 1.7 10 1970 g12 1.4 1.2 68 12 1.1 1.0 1.8 1.6 1.5 1.3 14 16 18 falling rising a v = ? r f = r g = 1k t a = 25 c
6 lt1970 1970fb typical perfor a ce characteristics uw large-signal response, a v = 1 10v 0v 10v r l = 1k 20 s/div 1970 g15 c l = 1000pf large-signal response, a v = 1 10v 0v 10v r l = 1k 20 s/div 1970 g14 slew rate vs temperature temperature ( c) 50 ?5 0 slew rate (v/ s) 1.0 2.5 0 50 75 1970 g13 0.5 2.0 1.5 25 100 125 v s = 15v falling rising 5v/div 5v/div small-signal response, a v = 1 small-signal response, a v = 1 r l = 1k 500ns/div 1970 g16 r l = 1k 2 s/div 1970 g17 c l = 1000pf 20mv/div 20mv/div output overdriven 0v v s = 5v 200 s/div 1970 g18 a v = 1 0v v out 5v/div % overshoot vs c load undistorted output swing vs frequency full range current sense transfer curve v in 5v/div c load (pf) 10 0 overshoot (%) 40 50 60 100 1k 10k 1970 g19 30 20 10 v s = 15v a v = 1 a v = 1 frequency (hz) 100 0 output swing (v p-p ) 20 25 30 1k 10k 100k 1970 g20 15 10 5 v s = 15v a v = ? 1% thd v csnk = v csrc (v) 0 v sense (mv) 100 300 500 4 1970 g21 ?00 ?00 0 200 400 ?00 ?00 ?00 1 2 3 5 sourcing current sinking current
7 lt1970 1970fb low level current sense transfer curve typical perfor a ce characteristics uw v csnk = v csrc (mv) 0 v sense (mv) 5 15 25 200 1970 g22 ? ?5 0 10 20 ?0 ?0 ?5 50 25 100 75 150 175 225 125 250 sourcing current sinking current sink current (ma) 0.001 0.4 logic output voltage (v) 0.5 0.6 0.7 0.8 0.01 0.1 1 10 100 1970 g23 0.3 0.2 0.1 0 0.9 1.0 v + = 15v v = ?5v 125 c 25 c ?5 c temperature ( c) ?5 output current (ma) 800 1200 125 1970 g24 400 0 ?5 25 75 ?0 0 50 100 1600 600 1000 200 1400 v + = 15v v = ?5v source sink logic output level vs sink current (output low) output stage quiescent current vs supply voltage control stage quiescent current vs supply voltage maximum output current vs temperature supply current vs supply voltage in shutdown safe operating area supply voltage (v) 0 0 i out peak (ma) 200 400 600 800 10 20 30 40 1970 g25 1000 1200 515 25 35 i out at 10% duty cycle supply voltage ( v) 0 output stage current (ma) ?0 ? ? 6 4 8 10 18 1970 g26 10 2 ? ? 4 8 0 26 12 14 16 i v + i v 25 c 25 c ?5 c ?5 c 125 c 125 c supply voltage ( v) 0 supply current (ma) ? ? ? 3 4 8 10 18 1970 g27 5 1 ? ? 2 4 0 26 12 14 16 i cc i ee 25 c 25 c ?5 c ?5 c 125 c 125 c supply voltage (v) 0 total supply current, i cc + i v + ( a) 400 500 600 16 1970 g28 300 200 0 4 8 12 218 6 10 14 100 800 700 85 c 25 c ?5 c v enable = 0v
8 lt1970 1970fb uu u pi fu ctio s v ee (pins 1, 10, 11, 20, package base): minus supply voltage. v ee connects to the substrate of the integrated circuit die, and therefore must always be the most negative voltage applied to the part. decouple v ee to ground with a low esr capacitor. v ee may be a negative voltage or it may equal ground potential. any or all of the v ee pins may be used. unused v ee pins must remain open. v (pin 2): output stage negative supply. v may equal v ee or may be smaller in magnitude. only output stage current flows out of v , all other current flows out of v ee . v may be used to drive the base/gate of an external power device to boost the amplifier? output current to levels above the rated 500ma of the on-chip output devices. unless used to drive boost transistors, v should be decoupled to ground with a low esr capacitor. out (pin 3): amplifier output. the out pin provides the force function as part of a kelvin sensed load connection. out is normally connected directly to an external load current sense resistor and the sense + pin. amplifier feedback is directly connected to the load and the other end of the current sense resistor. the load connection is also wired directly to the sense pin to monitor the load current. the out pin is current limited to 800ma typical. this current limit protects the output transistor in the event that connections to the external sense resistor are opened or shorted which disables the precision current limit function. sense + (pin 4): positive current sense pin. this lead is normally connected to the driven end of the external sense resistor. sourcing current limit operation is activated when the voltage v sense (v sense + v sense ? equals 1/ 10 of the programming control voltage at vc src (pin 13). sinking current limit operation is activated when the voltage v sense equals ?/10 of the programming control voltage at vc snk (pin 12). filter (pin 5): current sense filter pin. this pin is normally not used and should be left open or shorted to the sense pin. the filter pin can be used to adapt the response time of the current sense amplifiers with a 1nf to 100nf capacitor connected to the sense input. an internal 1k resistor sets the filter time constant. sense (pin 6): negative current sense pin. this pin is normally connected to the load end of the external sense resistor. sourcing current limit operation is activated when the voltage v sense (v sense + ?v sense ? equals 1/ 10 of the programming control voltage at vc src (pin 13). sinking current limit operation is activated when the voltage v sense equals ?/10 of the programming control voltage at vc snk (pin 12). v cc (pin 7): positive supply voltage. all circuitry except the output transistors draw power from v cc . total supply voltage from v cc to v ee must be between 3.5v and 36v. v cc must always be greater than or equal to v + . v cc should always be decoupled to ground with a low esr capacitor. in (pin 8): inverting input of amplifier. in may be any voltage from v ee ?0.3v to v ee + 36v. in and + in remain high impedance at all times to prevent current flow into the inputs when current limit mode is active. care must be taken to insure that in or + in can never go to a voltage below v ee ?0.3v even during transient conditions or damage to the circuit may result. a schottky diode from v ee to in can provide clamping if other elements in the circuit can allow in to go below v ee . + in (pin 9): noninverting input of amplifier. + in may be any voltage from v ee ?0.3v to v ee + 36v. in and + in remain high impedance at all times to prevent current flow into the inputs when current limit mode is active. care must be taken to insure that in or + in can never go to a voltage below v ee ?0.3v even during transient conditions or damage to the circuit may result. a schottky diode from v ee to +in can provide clamping if other elements in the circuit can allow + in to go below v ee .
9 lt1970 1970fb current limit is not active. isrc, isnk and tsd may be wired ?r?together if desired. isrc may be left open if this function is not monitored. isnk (pin 17): sinking current limit digital output flag. isnk is an open collector digital output. isnk pulls low whenever the sinking current limit amplifier assumes control of the output. this pin can sink up to 10ma of current. the current limit flag is off when the source current limit is not active. isrc, isnk and tsd may be wired ?r?together if desired. isnk may be left open if this function is not monitored. tsd (pin 18): thermal shutdown digital output flag. tsd is an open collector digital output. tsd pulls low whenever the internal thermal shutdown circuit activates, typically at a die temperature of 160 c. this pin can sink up to 10ma of output current. the tsd flag is off when the die temperature is within normal operating temperatures. isrc, isnk and tsd may be wired ?r?together if desired. isnk may be left open if this function is not monitored. thermal shutdown activation should prompt the user to evaluate electrical loading or thermal environ- mental conditions. v + (pin 19): output stage positive supply. v + may equal v cc or may be smaller in magnitude. only output stage current flows through v + , all other current flows into v cc . v + may be used to drive the base/gate of an external power device to boost the amplifier? output current to levels above the rated 500ma of the on-chip output devices. unless used to drive boost transistors, v + should be decoupled to ground with a low esr capacitor. package base: the exposed backside of the package is electrically connected to the v ee pins on the ic die. the package base should be soldered to a heat spreading pad on the pc board that is electrically connected to v ee . uu u pi fu ctio s vc snk (pin 12): sink current limit control voltage input. the current sink limit amplifier will activate when the sense voltage between sense + and sense equals ?.0 ?v vcsnk /10. vc snk may be set between v common and v common + 6v. the transfer function between vc snk and v sense is linear except for very small input voltages at vc snk < 60mv. v sense limits at a minimum set point of 4mv typical to insure that the sink and source limit amplifiers do not try to operate simultaneously. to force zero output current, the enable pin can be taken low. vc src (pin 13): source current limit control voltage input. the current source limit amplifier will activate when the sense voltage between sense + and sense equals v vcsrc /10. vc src may be set between v common and v common + 6v. the transfer function between vc src and v sense is linear except for very small input voltages at vc src < 60mv. v sense limits at a minimum set point of 4mv typical to insure that the sink and source limit amplifiers do not try to operate simultaneously. to force zero output current, the enable pin can be taken low. common (pin 14): control and enable inputs and flag outputs are referenced to the common pin. common may be at any potential between v ee and v cc ?3v. in typical applications, common is connected to ground. enable (pin 15): enable digital input control. when taken low this ttl-level digital input turns off the amplifier output and drops supply current to less than 1ma. use the enable pin to force zero output current. setting vc snk = vc src = 0v allows i out = 4mv/r sense to flow in or out of v out . isrc (pin 16): sourcing current limit digital output flag. isrc is an open collector digital output. isrc pulls low whenever the sourcing current limit amplifier assumes control of the output. this pin can sink up to 10ma of current. the current limit flag is off when the source
10 lt1970 1970fb 3 19 7 9 8 17 16 18 15 12 13 + + + i sink 1970tc r fil 1k r cs 1 ? r load 1k i src d2 d1 1 q1 q2 4 5 6 2 gm1 enable common vc src vc src vc snk 5v 15v vc snk isrc isnk ?n v in r g 1k +in enable tsd 14 v cc v + 15v ?5v out sense + filter sense v v ee 2, 10, 11, 20 10k 10k 10k r fb 1k v src + v snk + + block diagra a d test circuit w u the lt1970 power op amp with precision controllable current limit is a flexible voltage and current source module. the drawing on the front page of this data sheet is representative of the basic application of the circuit, however many alternate uses are possible with proper understanding of the subcircuit capabilities. circuit description main operational amplifier subcircuit block gm1, the 1x unity-gain current buffer and output transistors q1 and q2 form a standard opera- tional amplifier. this amplifier has 500ma current output capability and a 3.6mhz gain bandwidth product. most applications of the lt1970 will use this op amp in the main signal path. all conventional op amp circuit configurations are supported. inverting, noninverting, filter, summation or nonlinear circuits may be implemented in a conven- tional manner. the output stage includes current limiting at 800ma to protect against fault conditions. the input stage has high differential breakdown of 36v minimum between in and + in. no current will flow at the inputs when differential input voltage is present. this feature is important when the precision current sense amplifiers ? sink ?and ? src ?become active. current limit amplifiers amplifier stages ? sink ?and ? src ?are very high transcon- ductance amplifier stages with independently controlled off- set voltages. these amplifiers monitor the voltage between input pins sense + and sense which usually sense the voltage across a small external current sense resistor. the transconductance amplifiers outputs connect to the same high impedance node as the main input stage gm1 ampli- fier. small voltage differences between sense + and sense , smaller than the user set vc snk /10 and vc src /10 in mag- nitude, cause the current limit amplifiers to decouple from the signal path. this is functionally indicated by diodes d1 and d2 in the block diagram. when the voltage v sense increases in magnitude sufficient to equal or overcome one of the offset voltages vc snk /10 or vc src /10, the appropri- ate current limit amplifier becomes active and because of applicatio s i for atio wu uu
11 lt1970 1970fb applicatio s i for atio wu uu its very high transconductance, takes control from the input stage, gm1. the output current is regulated to a value of i out = v sense /r sense = (vc src or vc snk )/(10 ?r sense ). the time required for the current limit amplifiers to take control of the output is typically 4 s. linear operation of the current limit sense amplifier oc- curs with the inputs sense + and sense ranging be- tween v cc ?1.5v and v ee + 1.5v. most applications will connect pins sense + and out together, with the load on the opposite side of the external sense resistor and pin sense . feedback to the inverting input of gm1 should be connected from sense to in. ground side sensing of load current may be employed by connecting the load between pins out and sense + . pin sense would be connected to ground in this instance. load current would be regulated in exactly the same way as the conventional connection. however, voltage mode accuracy would be degraded in this case due to the voltage across r sense . creative applications are possible where pins sense + and sense monitor a parameter other than load current. the operating principle that at most one of the current limit stages may be active at one time, and that when active, the current limit stages take control of the output from gm1, can be used for many different signals. current limit threshold control buffers input pins vc snk and vc src are used to set the response thresholds of current limit amplifiers ? sink ?and ? src ? each of these inputs may be independently driven by a voltage of 0v to 5v above the common reference pin. the 0v to 5v input voltage is attenuated by a factor of 10 and applied as an offset to the appropriate current limit ampli- fier. ac signals may be applied to these pins. the ac bandwidth from a v c pin to the output is typically 2mhz. for proper operation of the lt1970, these control inputs cannot be left floating. for low v cc supply applications it is important to keep the maximum input control voltages, vc src and vc snk , at least 2.5v below the v cc potential. this ensures linear control of the current limit threshold. reducing the current limit sense resistor value allows high output current from a smaller control voltage which may be necessary if the v cc supply is only 5v. the transfer function from v c to the associated v os is linear from about 0.1v to 5v in, or 10mv to 500mv at the current limit amplifier inputs. an intentional nonlinearity is built into the transfer functions at low levels. this non- linearity insures that both the sink and source limit ampli- fiers cannot become active simultaneously. simultaneous activation of the limit amplifiers could result in uncon- trolled outputs. as shown in the typical performance characteristics curves, the control inputs have a ?ockey stick?shape, to keep the minimum limit threshold at 4mv for each limit amplifier. figure 1 illustrates an interesting use of the current sense input pins. here the current limit control amplifiers are used to produce a symmetrically limited output voltage swing. instead of monitoring the output current, the output voltage is divided down by a factor of 20 and applied to the sense + input, with the sense input grounded. when the threshold voltage between sense + and sense (v clamp /10) is reached, the current limit stage takes control of the output and clamps it a level of 2 ?v clamp . with control inputs v csrc and v csnk tied together, a single polarity input voltage sets the same + and ?output limit voltage for symmetrical limiting. in this circuit the output will current limit at the built-in fail-safe level of typically 800ma. vc src common v ee vc snk v filter v + 12v en v cc isnk isrc sense sense + tsd out +in r3 3k 80mv to 10v ?0mv to ?0v clamp reached output clamps at 2 v clamp v clamp ov to 5v v in lt1970 ?2v ?n r1 21.5k r l 1970 f01 r2 1.13k r f r g figure 1. symmetrical output voltage limiting
12 lt1970 1970fb enable control the enable input pin puts the lt1970 into a low supply current, high impedance output state. the enable pin responds to ttl threshold levels with respect to the common pin. pulling the enable pin low is the best way to force zero current at the output. setting vc snk = vc src = 0v allows the output current to remain as high as 4mv/r sense . in applications such as circuit testers (ate), it may be preferable to apply a predetermined test voltage with a preset current limit to a test node simultaneously. the enable pin can be used to provide this gating action as shown in figure 2. while the lt1970 is disabled, the load is essentially floating and the input voltage and current limit control voltages can be set to produce the load test levels. enabling the lt1970 then drives the load. the lt1970 enables and disables in just a few microseconds. the actual enable and disable times at the load are a function of the load reactance. operating status flags the lt1970 has three digital output indicators; tsd, isrc and isnk. these outputs are open collector drivers re- ferred to the common pin. the outputs have 36v capabili- ties and can sink in excess of 10ma. isrc and isnk indicate activation of the associated current limit ampli- fier. the tsd output indicates excessive die temperature has caused the circuit to enter thermal shutdown. the three digital outputs may be wire ?r??together, moni- tored individually or left open. these outputs do not affect circuit operation, but provide an indication of the present operational status of the chip. for slow varying output signals, the assertion of a low level at the current limit output flags occurs when the current limit threshold is reached. for fast moving signals where the lt1970 output is moving at the slew limit, typically 1.6v/ s, the flag assertion can be somewhat premature at typically 75% of the actual current limit value. the operating status flags are designed to drive leds to provide a visual indication of current limit and thermal conditions. as such, the transition edges to and from the active low state are not particularly sharp and may exhibit some uncertainty. adding some positive feedback to the current limit control inputs helps to sharpen these transitions. with the values shown in figure 3, the current limit threshold is reduced by approximately 0.5% when either current limit status flag goes low. with sharp logic transi- tions, the status outputs can be used in a system control applicatio s i for atio wu uu vc src common v ee vc snk v filter v + 12v en v cc isnk isrc sense sense + tsd out +in 5v 0v 5v enable disable v in lt1970 12v ?n r s 1 ? r l 10 ? 1970 f02 r g 10k r f 10k en 10v/div 0v v out 1v/div 5 s/div 0v v in = 0.5v v in = 0.5v figure 2. using the enable pin
13 lt1970 1970fb loop to take protective measures when a current limit condition is detected automatically. the current limit status flag can also be used to produce a dramatic change in the current limit value of the ampli- fier. figure 4 illustrates a ?nap-back?current limiting characteristic. in this circuit, a simple resistor network initially sets a high value of current limit (500ma). the circuit operates normally until the signal is large enough to enter current limit. when either current limit flag goes low, the current limit control voltage is reduced by a factor of 10. this then forces a low level of output current (50ma) until the signal is reduced in magnitude. when the load current drops below the lower level, the current limit is then restored to the higher value. this action is similar to a self resettable fuse that trips at dangerously high current levels and resets only when conditions are safe to do so. thermal management minimizing power dissipation the lt1970 can operate with up to 36v total supply voltage with output currents up to 500ma. the amount of power dissipated in the chip could approach 18w under worst-case conditions. this amount of power will cause die temperature to rise until the circuit enters thermal shutdown. while the thermal shutdown feature prevents damage to the circuit, normal operation is impaired. thermal design of the lt1970 operating environment is essential to getting maximum utility from the circuit. the first concern for thermal management is minimizing the heat which must be dissipated. the separate power pins v + and v can be a great aid in minimizing on-chip power. the output pin can swing to within 1.0v of v + or v even under maximum output current conditions. using separate power supplies, or voltage regulators, to set v + applicatio s i for atio wu uu vc src common v ee vc snk v filter v + 12v i source flag when current limit is flagged, i limit treshold is reduced by 0.5% i sink flag en v cc isnk isrc sense sense + tsd out +in v in lt1970 12v ?n r s 1 ? r l 1970 f03 r g r f r2 100 ? r1 100 ? current limit control voltage (0.1v to 5v) r4 20k r3 20k vc src common v ee vc snk v filter v + 12v en v cc isnk isrc sense sense + tsd out +in v in lt1970 12v ?n r s 1 ? r l 1970 f04 r g 10k r f 10k r3 2.55k r2 39.2k r1 54.9k i max 500ma 500ma 50ma 0 i out i low v cc ?r2 (r1 + r2) ?10 ?r s i max v cc ?(r2||r3) [r1 + (r2||r3)] ?10 ?r s i low figure 3. adding positive feedback to sharpen the transition edges of the current limit status flags figure 4. ?nap-back?current limiting
14 lt1970 1970fb and v to their minimum values for the required output swing will minimize power dissipation. the supplies v cc and v ee may also be reduced to a minimal value, but these supply pins do not carry high currents, and the power saving is much less. v cc and v ee must be greater than the maximum output swing by 1.5v or more. when v and v + are provided separately from v cc and v ee , care must be taken to insure that v and v + are always less than or equal to the main supplies in magnitude. protec- tion schottky diodes may be required to insure this in all cases, including power on/off transients. operation with reduced v + and v supplies does not affect any performance parameters except maximum output swing. all dc accuracy and ac performance specifications guaranteed with v cc = v + and v ee = v ? are still valid with the reduced output signal swing range. heat sinking the power dissipated in the lt1970 die must have a path to the environment. with 100 c/w thermal resistance in free air with no heat sink, the package power dissipation is limited to only 1w. the 20-pin tssop package with exposed copper underside is an efficient heat conductor if it is effectively mounted on a pc board. thermal resis- tances as low as 40 c/w can be obtained by soldering the bottom of the package to a large copper pattern on the pc board. for operation at 85 c, this allows up to 1.625w of power to be dissipated on the lt1970. at 25 c operation, up to 3.125w of power dissipation can be achieved. the pc board heat spreading copper area must be connected to v ee . figure 5 shows examples of pcb metal being used for heat spreading. these are provided as a reference for what might be expected when using different combinations of metal area on different layers of a pcb. these examples are with a 4-layer board using 1oz copper on each layer. the most effective layers for spreading heat are those closest to the lt1970 junction. soldering the exposed thermal pad of the tssop package to the board produces a thermal resistance from junction-to-case of approximately 3 c/w. as a minimum, the area directly beneath the package on all pcb layers can be used for heat spreading. however, limiting the area to that of the metal heat sinking pad is not applicatio s i for atio wu uu very effective. expanding the area on various layers sig- nificantly reduces the overall thermal resistance. the addition of vias (small 13 mil holes which fill during pcb plating) connecting all layers of metal also helps reduce the operating temperature of the lt1970. these are also shown in figure 5. it is important to note that the metal planes used for heat sinking are connecting electrically to v ee . these planes must be isolated from any other power planes used in the pcb design. another effective way to control the power amplifier oper- ating temperature is to use airflow over the board. airflow can significantly reduce the total thermal resistance as also shown in figure 5. driving reactive loads capacitive loads the lt1970 is much more tolerant of capacitive loading than most operational amplifiers. in a worst-case configu- ration as a voltage follower, the circuit is stable for capaci- tive loads less than 2.5nf. higher gain configurations improve the c load handling. if very large capacitive loads are to be driven, a resistive decoupling of the amplifier from the capacitive load is effective in maintaining stability and reducing peaking. the current sense resistor, usually connected between the output pin and the load can serve as a part of the decoupling resistance. inductive loads load inductance is usually not a problem at the outputs of operational amplifiers, but the lt1970 can be used as a high output impedance current source. this condition may be the main operating mode, or when the circuit enters a protective current limit mode. just as load capaci- tance degrades the phase margin of normal op amps, load inductance causes a peaking in the loop response of the feedback controlled current source. the inductive load may be caused by long lead lengths at the amplifier output. if the amplifier will be driving inductive loads or long lead lengths (greater than 4 inches) a 500pf capacitor from the sense pin to the ground plane will cancel the inductive load and ensure stability.
15 lt1970 1970fb still air ja tssop 100 c/w tssop 50 c/w tssop 45 c/w package top layer 2nd layer 3rd layer bottom layer 1970 f05a airflow (linear feet per minute, lfpm) ?0 ?0 reduction in ja (%) ?0 ?0 0 ?0 ?0 200 400 600 800 1970 f05b 1000 100 0 300 500 typical reduction in ja with laminar airflow over the device 700 900 % reduction relative to ja in still air figure 5. examples of pcb metal used for heat dissipation. driver package mounted on top layer. heat sink pad soldered to top layer metal. metal areas drawn to scale of package size applicatio s i for atio wu uu
16 lt1970 1970fb figure 6 shows the lt1970 driving an inductive load with a controlled amount of current. this load is shown as a generic magnetic transducer, which could be used to create and modulate a magnetic field. driving the current limit control inputs directly forces a current through the load that could range up to 2mhz in modulation. biasing the input stage to the midpoint of the modulation signal allows symmetrical bidirectional current flow through the load. clamp diodes are added to protect the lt1970 output from large inductive flyback potentials caused by rapid di/dt changes. abrupt load short protection an abrupt short-circuit connection, often referred to as screwdriver or crowbar short, to ground or other supply potentials is the worst-case load condition for the lt1970. the current limit sense amplifier normally operates with an input voltage differential equal to the voltage across the sense resistor, which is only 500mv maximum in a typical application. during an abrupt load short to ground, the load end of the sense resistor is immediately connected to ground while the amplifier output remains at the normal output voltage. this can impose a large differential voltage to the sense amplifier inputs for a brief period. if this delta v can be greater than 2v, it is beneficial to add clamps between the current limit sense amplifier inputs. these clamps ensure a smooth transition from the main ampli- fier control to the current limit amplifier control under all load short conditions that may arise. applicatio s i for atio wu uu figure 7 shows the connection of these back-to-back clamp diodes between the filter pin and the sense + pin. with this connection, the internal 1k resistor between the sense pin and the filter pin limits the diode current. the bav99 diodes are small sot-23 packaged general purpose silicon diodes. the maximum current limit sense voltage is now the diode voltage drop, determined by the voltage across the sense resistor and the 1k internal resistor. as the diode begins to conduct current, with a voltage drop of around 300mv, an error in the expected current limit level at the high end of the control becomes vc src common v ee vc snk v filter v + 12v en v cc isnk isrc sense sense + tsd out d2 1n4001 c1 500pf r1 95.3k lt1634-2.5 +in 5v v in 0v lt1970 12v ?n 12v 2.5v r s 1 ? 500ma magnetic transducer 1970 f06 d1 1n4001 figure 6. current modulation of a magnetic transducer 4 5 1k 100 ? * sense + out filter sense *optional?ee text sense + filter 12 3 r sense bav99 load 2n3904 1970 f07 higher clamp voltage alternative 2n3904 1nf to 10nf + 6 3 main amplifier current limit sense amplifier figure 7. adding protection for abrupt load shorts
17 lt1970 1970fb applicatio s i for atio wu uu apparent, as v diode is less than the voltage across r sense . adding an optional external 100 ? resistor in parallel with the internal 1k resistor forces the diode voltage closer to the sensed current limit voltage and reduces the current limit error. alternatively, the base-emitter junctions of back-to-back 2n3904 npn transistors can provide this clamping action. these diodes begin to conduct at a higher voltage level nearer to 600mv. with a 500mv maximum current limit threshold very little error will be noticed. comparisons of typical current limit error with three ways of adding clamping protection are shown in figure 8. scaling the current sense resistor and the current limit control voltage down so that a 0v to 300mv current limit sense voltage range also prevents these accuracy errors caused by the abrupt-short clamping diodes. also shown in figure 7 is a small filtering capacitor. this too provides an extra measure of control under abrupt load shorting conditions. a fast short-circuit makes ap- parent all parasitic interconnect lead inductances between the lt1970 and the load. these distributed parasitic elements can cause significant transient voltage spikes in the short time after the application or removal of a short circuit. these uncontrolled voltage transients could actu- ally couple back to the current limit amplifier and cause polarity reversal from sourcing current limit to sinking or vice versa. this can act as positive feedback and cause the current limit amplifier to go to the incorrect current limit direction and hang up. adding a small filter capacitor between the sense and filter pins, 1nf to 10nf is fairly typical, which charges through the clamp diodes forces the correct current limit polarity at the instant of the load short. this holds the amplifier in current limit until the capacitor discharges through the internal 1k resistor, eliminating transient induced behavior and creating a smooth transition into current limit. supply bypassing the lt1970 can supply large currents from the power supplies to a load at frequencies up to 4mhz. power supply impedance must be kept low enough to deliver these currents without causing supply rails to droop. low esr capacitors, such as 0.1 f or 1 f ceramics, located close to the pins are essential in all applications. when large, high speed transient currents are present additional ca- pacitance may be needed near the chip. check supply rails with a scope and if signal related ripple is seen on the supply rail, increase the decoupling capacitor as needed. to ensure proper start-up biasing of the lt1970, it is recommended that the rate of change of the supply volt- ages at turn-on be limited to be no faster than 6v/ s. application circuit ideas the digitally controlled analog pin driver is shown in figure 9. all of the control signals are provided by an ltc 1664 quad, 10-bit dac by way of a 3-wire serial interface. the lt1970 is configured as a simple difference amplifier with a gain of 3. this gain is required to produce 15v from the 0v to 5v outputs from dacs c and d. to provide voltage headroom, the supplies for the lt1970 are set to the maximum value of 18v. as 18v is the absolute maximum rating of supply voltage for the lt1970, care must be taken to not allow the supply voltage to increase. dacs a and b separately control the sinking and sourcing current limit to the load over the range of 4ma to 500ma. an optional on/off control for the pin driver using the enable input is shown. if always enabled the enable pin should be tied to v cc . v cl sense (mv) 50 ?0 current limit accuracy (%) ? 5 10 15 25 100 300 400 1970 f08 0 20 250 500 150 200 350 450 2n3904 w 1k ? bav99 w 1k ? bav99 w 100 ? figure 8. current limit accuracy with different clamps
18 lt1970 1970fb applicatio s i for atio wu uu vc src common v ee vc snk v filter v + 18v r6 3k 10 f0.1 f en v cc isnk isrc sense sense + tsd out +in r2 10.2k r1 3.4k 0v 5v apply load drive optional test pin on/off control hi-z lt1970 ?8v 10 f 0.1 f sense ?n r s 1 ? force test pin load 1970 f09 r4 10.2k v cc v ref 5v clr dac a dac b cs/ld sck di dac c dac d r3 3.4k ltc1664 quad 10-bit dac decoder 3-wire serial interface + r5 3k + v out = 15v i source(max) = 4ma to 500ma 15v code c ?code d 1024 () 0.5 ?code b 1024 ?r s i sink(max) = 4ma to 500ma 0.5 ?code a 1024 ?r s figure 9. digitally controlled analog pin driver in some applications it may be necessary to know what the current into the load is at any time. figure 10 shows an lt1787 high side current sense amplifier monitoring the current through sense resistor r s . the lt1787 is biased from the v ee supply to accommodate the common mode input range of 10v. the sense resistor is scaled down to provide a 100mv maximum differential signal to the current sense amplifier to preserve linearity. the lt1880 amplifier provides gain and level shifting to produce a 0v to 5v output signal (2.5v dc 5mv/ma) with up to 1khz full-scale bandwidth. an a/d converter could then digitize this instantaneous current reading to provide digital feed- back from the circuit. the lt1970 is just as easy to use as a standard operational amplifier. basic amplification of a precision reference voltage creates a very simple bench dc power supply as shown in figure 11. the built-in power stage produces an adjustable 0v to 25v at 4ma to 100ma of output current. voltage and current adjustments are derived from the lt1634-5 5v reference. the output current capability is 500ma, but this supply is restricted to 100ma for power dissipation reasons. the worst-case output voltage for maximum power dissipated in the lt1970 output stage occurs if the output is shorted to ground or set to a voltage near zero. limiting the output current to 100ma sets the maximum power dissipation to 3w. to allow the output to
19 lt1970 1970fb applicatio s i for atio wu uu figure 11. simple bench power supply figure 10. sensing output current vc src common v ee vc snk v filter v + 12v en v cc isnk isrc sense sense + tsd out +in v cc 0v to 1v lt1970 12v ?n r s 0.2 ? r load 1970 f10 r g r f v s v ee 20k bias ?2v ?2v r1 60.4k r4 255k v out 2.5v 5mv/ma 1khz full current bandwidth r2 10k r3 20k v s + lt1787 + lt1880 12v 12v 0v to 5v a/d optional digital feedback vc src current limit adjust common v ee vc snk v filter v + en v cc isnk isrc sense sense + tsd out c2 10 f c1 10 f r g 2.55k lt1634-5 +in lt1970 ?v ?n r s 1 ? r5 5.49k 30v dc load fault v out 0v to 25v 4ma to 100ma c3 10 f gnd 1970 f11 + + + ltc1046 r f 10.2k r3 10k r4 10k output voltage adjust r1 2.1k r2 40k
20 lt1970 1970fb applicatio s i for atio wu uu range all the way to 0v, an ltc1046 charge pump inverter is used to develop a 5v supply. this produces a negative rail for the lt1970 which has to sink only the quiescent current of the amplifier, typically 7ma. using a second lt1970, a 0v to 12v dual tracking power supply is shown in figure 12. the midpoint of two 10k resistors connected between the + and ?outputs is held at 0v by the lt1881 dual op amp servo feedback loop. to figure 12. dual tracking bench power supply vc src common v ee vc snk r5 13k v filter v + 15v r6 18.2k r7 3k en v cc isnk isrc sense sense + tsd out ?n lt1970 15v r11 10k 15v c1 1 f 15v +in r s1 1 ? +out current limit thermal fault r8 3k 0.1 10 f r13 25.5k ground optional symmetry adjust 100 ? + c2 10 f +out 0v to 12v 4ma to 150ma out 0v to ?2v 4ma to 150ma 1970 f12 + vc src common v ee vc snk r14 10.7k v filter v + 15v r15 3k en v cc isnk isrc sense sense + tsd out ?n lt1970 15v +in r s2 1 ? out current limit to tsd pin of +out c3 10 f r10 10k 1% 10 f 0.1 f + + + + r12 10k 1/2 lt1881 1/2 lt1881 r9 10k 1% v out adjust current limit adjust r1 6.19k r2 10k r4 10k lt1634-5 r3 23.2k 5v ref 18v
21 lt1970 1970fb applicatio s i for atio wu uu figure 13. simple bidirectional dc motor speed controller maintain 0v, both outputs must be equal and opposite in polarity, thus they track each other. if one output reaches current limit and drops in voltage, the other output follows to maintain a symmetrical + and ?voltage across a common load. again, the output current limit is less than the full capability of the lt1970 due to thermal reasons. separate current limit indicators are used on each lt1970 because one output only sources current and the other only sinks current. both devices can share the same thermal shutdown indicator, as the output flags can be or?d together. another simple linear power amplifier circuit is shown in figure 13. this uses the lt1970 as a linear driver of a dc motor with speed control. the ability to source and sink the same amount of output current provides for bidirec- tional rotation of the motor. speed control is managed by sensing the output of a tachometer built on to the motor. a typical feedback signal of 3v/1000rpm is compared with the desired speed-set input voltage. because the lt1970 is unity-gain stable, it can be configured as an integrator to force whatever voltage across the motor as necessary to match the feedback speed signal with the set input signal. additionally, the current limit of the amplifier can be adjusted to control the torque and stall current of the motor. for reliability, a feedback scheme similar to that shown in figure 4 can be used. assuming that a stalled rotor will generate a current limit condition, the stall current limit can be significantly reduced to prevent exces- sive power dissipation in the motor windings. for motor speed control without using a tachometer, the circuit in figure 14 shows an approach. using the enable feature of the lt1970, the drive to the motor can be removed periodically. with no drive applied, the spinning motor presents a back emf voltage proportional to its rotational speed. the lt1782 is a tiny rail-to-rail amplifier vc src common r4 49.9k 15v ?5v reverse forward r2 10k v ee vc snk v filter v + 15v en v cc isnk isrc sense sense + tsd out +in lt1970 15v ?n r s 1 ? 12v dc motor tach feedback 3v/1000rpm gnd 1970 f13 c1 1 f r5 49.9k r3 1.2k r1 1.2k ov to 5v torque/stall current control
22 lt1970 1970fb applicatio s i for atio wu uu figure 14. simple bidirectional dc motor speed controller without a tachometer vc src com v ee vc snk v filter v + fault/stall r3 2k 15v en v cc isnk isrc sense sense + tsd out +in lt1970 15v 12v 12v 12v 12v 12v ?n r s 1 ? 12v dc motor 1970 f14 c1 4.7 f 100 ? c2 0.01 f shdn r14 10k ov to 5v torque/stall current control r2 20k r1 10k r4 100k r5 120k r7 10k r12 10k r13 10k r8 20k r9 20k r10 82.5k c3 0.1 f d1 1n4148 d2 1n4148 ?2v r11 9.09k + + + 1/2 lt1638 1/2 lt1638 lt1782 5v 0v motor speed control rev fwd stop with a shutdown pin. the amplifier is enabled during this interval to sample the back emf voltage across the motor. this voltage is then buffered by one-half of an lt1638 dual op amp and used to provide the feedback to the lt1970 integrator. when re-enabled the lt1970 will adjust the drive to the motor until the speed feedback voltage, compared to the speed-set input voltage, settles the output to a fixed value. a 0v to 5v signal for the motor speed input controls both rotational speed and direction. the other half of the lt1638 is used as a simple pulse oscillator to control the periodic sampling of the motor back emf.
23 lt1970 1970fb u package descriptio fe package 20-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1663, exposed pad variation ca) information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. fe20 (ca) tssop 0204 0.09 ?0.20 (.0035 ?.0079) 0 ?8 0.25 ref recommended solder pad layout 0.50 ?0.75 (.020 ?.030) 4.30 ?4.50* (.169 ?.177) 134 5 6 7 8910 11 12 14 13 6.40 ?6.60* (.252 ?.260) 4.95 (.195) 2.74 (.108) 20 1918 17 16 15 1.20 (.047) max 0.05 ?0.15 (.002 ?.006) 0.65 (.0256) bsc 0.195 ?0.30 (.0077 ?.0118) typ 2 2.74 (.108) 0.45 0.05 0.65 bsc 4.50 0.10 6.60 0.10 1.05 0.10 4.95 (.195) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc
24 lt1970 1970fb ? linear technology corporation 2002 lt 0407 rev b ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com part number description comments lt1010 fast 150ma power buffer 20mhz bandwidth, 75v/ s slew rate lt1206 250ma/60mhz current feedback amplifier shutdown mode, adjustable supply current lt1210 1.1a/35mhz current feedback amplifier stable with c l = 10,000pf related parts applicatio s i for atio wu uu figure 15. a v = 1 amplifier with discrete power devices to boost output current to 5a figure 15 shows how easy it is to boost the output current of the lt1970. this 5a power stage uses complementary external n- and p-channel mosfets to provide the addi- tional current. the output stage power supply inputs, v + and v , are used to provide gate drive as needed. with higher output currents, the sense resistor r cs , is reduced in value to maintain the same easy current limit control. this class b power stage is intended for dc and low frequency, <1khz, applications as crossover distortion becomes evident at higher frequencies. figure 15 shows some optional resistor dividers between the output connections and the current sense inputs. they are required only if the load of this power stage is removed or at a very low current level. large power devices with no load on them can saturate and pull the output voltage very close to the power supply rails. the current sense ampli- fiers operate properly with input voltages at least 1v away from the v cc and v ee supply rails. in boosted current applications, it may be necessary to attenuate the maxi- mum output voltage levels by 1v before connecting to the sense input pins. this only slightly deceases the current limit thresholds. v cc v ee enable v vc src v c snk sense common sense + v + out +in r1 1k r g 2.2k r f 2.2k * * ** r cs 0.1 ? 5w r5 100 ? r4 100 ? lt1970 ?n load 1970 f15 current limit control voltage 0v to 5v v cc 15v v ee ?5v v in 10 f irf9530 irf530 0.1 f 0.1 f 10 f r3 100 ? *optional, see text r2 100 ?

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