View SI3220_7008485.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev. 1.0 6/04 copyright ? 2004 by silicon laboratories SI3220/si3225 this information applies to a product under dev elopment. its characteristics and specifications are s ubject to change without n otice. SI3220/si3225 d ual p ro slic ? p rogrammable cmos slic/c odec features applications description the dual proslic ? is a series of low-voltage cmos devices that integrate both slic and codec functionality into a single ic to provide a complete dual-channel analog telephone interface in accordance with all relevant lssgr, itu, and etsi specifications. the SI3220 includes in ternal ringing generation to eliminate centralized ringers and ringing relays, and the si3225 supports centralized ringing for long loop and legacy applications. on-chip subscriber loop and audio testing allows remote diagnostics and fault detec tion with no external test equipment or relays. the SI3220 and si3225 operate from a single 3.3 v or 5 v supply and interface to standard pcm/spi or gci bus digital interfaces. the si3200 linefeed interface ic performs all high-voltage func tions and operates from a 3.3 v or 5 v supply as well as single or dual battery supplies up to 100 v. the SI3220 and si3225 are available in a 64-pin thin quad flat package (tqfp), and the si3200 is available in a thermally-enhanced 16-pin small outline (soic) package. functional block diagram performs all borscht functions ideal for applications up to 18 kft internal balanced ringing to 65 v rms (SI3220) external bulk ringer support (si3225) low standby power consumption: <70 mw per channel software-programmable parameters: ringing frequency, amplitude, cadence, and waveshape (SI3220) two-wire ac impedance transhybrid balance dc current loop feed (18?45 ma) loop closure and ring trip thresholds ground key detect threshold automatic switching of up to three battery supplies on-hook transmission loop or ground start operation with smooth/abrupt polarity reversal modem/fax tone detection dtmf generation/decoding dual tone generators a-law/-law, linear pcm companding pcm and spi bus digital interfaces with programmable interrupts gci/iom-2 mode support 3.3 or 5 v operation gr-909 loop diagnostics audio diagnostics with loopback 12 khz/16 khz pulse metering (SI3220) fsk caller id generation digital loop carriers central office telephony pair gain remote terminals wireless local loop private branch exchange (pbx) systems cable telephony voice over ip/voice over dsl isdn terminal adapters text dac adc linefeed control linefeed monitor dac adc linefeed control linefeed monitor slic a slic b codec a codec b dsp spi control interface pcm / gci interface pll SI3220/25 si3200 linefeed interface si3200 linefeed interface 2-wire ac impedance hybrid balance pulse metering subscriber line diagnostics dtmf decode programmable audio filters gain adjust dual tone generators modem tone detection ringing generator & ring trip sense loop closure, & ground key detection fsk caller id relay drivers cs sclk sdo sdi dtx drx fsync int reset pclk tip channel a ring tip ring channel b patents pending ordering information see "dual proslic? selection guide" on page 2. part number ringing method SI3220 internal si3225 external ringer
SI3220/si3225 2 rev. 1.0 dual proslic ? selection guide part number description on-chip ringing external ringing support pulse metering lead free temp range package si3200-ks linefeed interface 0 to 70 o csoic-16 si3200-bs linefeed in terface ?40 to 85 o csoic-16 si3200-fs linefeed interface 0 to 70 o csoic-16 si3200-gs linefeed interface ?40 to 85 o csoic-16 SI3220-fq dual proslic 0 to 70 o c tqfp-64 SI3220-gq dual proslic ?40 to 85 o ctqfp-64 si3225-fq dual proslic 0 to 70 o c tqfp-64 si3225-gq dual proslic ?40 to 85 o ctqfp-64
SI3220/si3225 rev. 1.0 3 t able of c ontents section page dual proslic? selection guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 dual proslic architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 dc feed characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 adaptive linefeed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 on-hook to off-hook transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 off-hook to on-hook transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 voctrack and adaptive linefeed hysteres is . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 ground start operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 power monitoring and power fault detecti on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 automatic dual battery switchi ng . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 loop closure detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 ground key detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 ringing generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 internal unbalanced ringing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 ringing coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 9 ring trip detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 0 relay driver considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 two-wire impedance synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 transhybrid balance filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 tone generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 9 dtmf detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 5 modem tone detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 audio path processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 system clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 spi control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 8 pcm interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 pcm companding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 general circuit interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 system testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 pin descriptions: SI3220/25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6 pin descriptions: si3200 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 00 package outline: 64-pin tqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 package outline: 16-pin esoic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 silicon labs SI3220/25 support document ation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 related parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
SI3220/si3225 4 rev. 1.0 electrical specifications table 1. absolute maximum ratings and thermal information 1 parameter symbol test condition value unit supply voltage, si3200 and SI3220/si3225 v dd , v dd1 ?v dd4 ?0.5 to 6.0 v high battery supply voltage, si3200 2 v bath continuous 0.4 to ?104 v 10 ms 0.4 to ?109 low battery supply voltage, si3200 v bat ,v batl continuous v bath v tip or ring voltage, si3205 v tip ,v ring continuous pulse < 10 s pulse < 4 s ?104 v bath ?15 v bath ?35 tip, ring current, si3200 i tip , i ring 100 ma stipac, stipdc, sringac, sringdc current, SI3220/si3225 20 ma input current, digital input pins i in continuous 10 ma SI3220/25 analog ground differential voltage (gnd1 to epad, gnd2 to epad, or gnd1 to gnd2) 5 ? v gnda 50 mv SI3220/25 digital ground differential voltage (gnd3 to gnd4) 5 ? v gndd 50 mv SI3220/25 analog to digital ground differential volt- age (gnd1/gnd2/epad to gnd3/gnd4) 5 ? v gnd,a?d 200 mv digital input voltage v ind ?0.3 to ( v ddd + 0.3) v operating temperature range t a ?40 to 100 c storage temperature range t stg ?40 to 150 c SI3220/si3225 thermal resistance, typical 3 (tqfp-64 epad) ja 25 c/w si3200 thermal resistance, typical 3 (soic-16 epad) ja 55 c/w continuous power dissipation, si3200 4 p d t a =85c, soic-16 1w continuous power dissipation, SI3220/25 p d t a =85c, tqfp-64 1.6 w notes: 1. permanent device damage may occur if the above absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as specified in the oper ational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. the dv/dt of the voltage applied to the vbat, vbath, and vbatl pins must be limited to 10 v/ s. 3. the thermal resistance of an exposed pad package is a ssured when the recommended printed circuit board layout guidelines are followed correctly. the specified performanc e requires that the exposed pad be soldered to an exposed copper surface of equal size and that multiple vias are added to enable heat transfer between the top-side copper surface and a large internal copper groun d plane. refer to ?an55: dual proslic ? user guide? or to the SI3220/3225 evaluation board data sheet for specific layout examples. 4. on-chip thermal limiting circuitry will shut down the circuit at a junction temperature of approximately 150 c. for optimal reliability, junction temperatures above 140 c should be avoided. 5. the pcb pad placed under the device package must be connected with multiple vias to the pcb ground layer and to the gnd1-gnd4 pins via short traces. the tqfp-64 e-pad mu st be properly soldered to the pcb pad during pcb assembly. this type of low-impedance groun ding arrangement is necessary to ensu re that maximum differentials are not exceeded under any operating condition in addition to providing thermal dissipation.
SI3220/si3225 rev. 1.0 5 table 2. recommended operating conditions parameter symbol test condition min * typ max * unit ambient temperature t a k/f-grade 0 25 70 o c ambient temperature t a b/g-grade ?40 25 85 o c supply voltage, SI3220/si3225 v dd1 ?v dd4 3.13 3.3/5.0 5.25 v supply voltage, si3200 v dd 3.13 3.3/5.0 5.25 v high battery supply voltage, si3200 v bath ?15 ? ?99 v low battery supply voltage, si3200 v batl ?15 ? v bath v *note: all minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. typical values apply at nominal supply volt ages and an operatin g temperature of 25 o c unless otherwise stated. table 3. 3.3 v power supply characteristics 1 (v dd , v dd1 ?v dd4 = 3.3 v, t a = 0 to 70 c for k/f-grade, ?40 to 85 c for b/g-grade) parameter symbol test condition min typ max unit v dd1 ?v dd4 sup- ply current (SI3220/ si3225) i vdd1 ?i vdd4 sleep mode, reset = 0 ? 1 ? ma open (high-impedance) ? 15 ? ma active on-hook standby ? 15 ? ma forward/reverse active off-hook, abias = 4 ma ?22 + i lim ?ma forward/reverse active oht obias = 4 ma, v bat =?24v ?44?ma ringing, v ring =45v rms , v bat =?70v, sine wave, 1 ren load 2 ?28?ma notes: 1. all specifications are for a single c hannel based on measurements with both ch annels in the same operating state. 2. see "ringing power considerations" on page 50 for curr ent and power consumption under other operating conditions. 3. power consumption does not in clude additional power required for dc loop feed. to tal system power consumption must include an additional v bat x i loop term.
SI3220/si3225 6 rev. 1.0 v dd supply cur- rent (si3200) i vdd sleep mode, reset = 0 ? 110 ? a open (high-impedance) ? 110 ? a active on-hook standby ? 110 ? a forward/reverse active off-hook, abias = 4 ma, v bat =?24v ?110?a forward/reverse oht, obias = 4 ma, v bat =?70v ?110?a ringing, v ring =45v rms , v bat =?70v, sine wave, 1 ren load ?110?a v bat supply cur- rent (si3200) i vbat sleep mode, reset=0, v bat =?70v ? 100 ? a open (high-impedance), v bat =?70v ? 225 ? a active on-hook standby, v bat =?70v ? 400 ? a forward/reverse active off-hook, abias = 4 ma, v bat =?24v ? 4.4 + i lim ?ma forward/reverse oht, obias = 4 ma, v bat =?70v ?8.4?ma ringing, v ring =45v rms , v bat =?70v, sine wave, 1 ren load 2 ?6?ma table 3. 3.3 v power supply characteristics 1 (continued) (v dd , v dd1 ?v dd4 = 3.3 v, t a = 0 to 70 c for k/f-grade, ?40 to 85 c for b/g-grade) parameter symbol test condition min typ max unit notes: 1. all specifications are for a single c hannel based on measurements with both ch annels in the same operating state. 2. see "ringing power considerations" on page 50 for curr ent and power consumption under other operating conditions. 3. power consumption does not in clude additional power required for dc loop feed. to tal system power consumption must include an additional v bat x i loop term.
SI3220/si3225 rev. 1.0 7 chipset power consumption p sleep sleep mode, reset = 0, v bat =?70v ?8?mw p open open (high-impedance), v bat =?70v ? 65 ? mw p stby active on-hook standby, v bat = ?48 v ? 70 ? mw p stby active on-hook standby, v bat = ?70 v ? 80 ? mw p active 3 forward/reverse active off-hook, abias = 4 ma, v bat =?24v ? 240 ? mw p active 3 forward/reverse active off-hook, abias = 4 ma, v bat =?48v ? 345 ? mw p oht forward/reverse oht, obias = 4 ma, v bat =?48v ? 550 ? mw p oht forward/reverse oht, obias = 4 ma, v bat =?70v ? 735 ? mw p ring ringing, v ring =45v rms , v bat = ?70 v, 1 ren load 2 ? 516 ? mw table 3. 3.3 v power supply characteristics 1 (continued) (v dd , v dd1 ?v dd4 = 3.3 v, t a = 0 to 70 c for k/f-grade, ?40 to 85 c for b/g-grade) parameter symbol test condition min typ max unit notes: 1. all specifications are for a single c hannel based on measurements with both ch annels in the same operating state. 2. see "ringing power considerations" on page 50 for curr ent and power consumption under other operating conditions. 3. power consumption does not in clude additional power required for dc loop feed. to tal system power consumption must include an additional v bat x i loop term.
SI3220/si3225 8 rev. 1.0 table 4. 5 v power supply characteristics 1 (v dd , v dd1 ?v dd4 = 5v, t a = 0 to 70 c for k/f-grade, ?40 to 85 c for b/g-grade) parameter symbol test condition min typ max unit v dd1 ?v dd4 supply current (SI3220/si3225) i vdd1 ?i vdd4 sleep mode, reset = 0 ? 1 ? ma open (high-impedance) ? 20 ? ma active on-hook standby ? 20 ? ma forward/reverse active off-hook, abias = 4 ma ?38 + i lim ?ma forward/reverse active oht obias = 4 ma ?60?ma ringing, v ring =45v rms , v bat = ?70 v, 1 ren load 2 ?32?ma v dd supply current (si3200) i vdd sleep mode, reset = 0 ? 110 ? a open (high-impedance) ? 110 ? a active on-hook standby ? 110 ? a forward/reverse active off-hook, abias = 4 ma, v bat =?24v ?110?a forward/reverse oht, obias = 4 ma, v bat =?70v ?110?a ringing, v ring =45v rms , v bat = ?70 v, 1 ren load ?110?a notes: 1. all specifications are for a single channel based on me asurements with both channels in the same operating state. 2. see "ringing power considerations" on page 50 for current and power consumption under other operating conditions. 3. power consumption does not include additional power requir ed for dc loop feed. total system power consumption must include an additional v bat x i loop term.
SI3220/si3225 rev. 1.0 9 v bat supply current (si3200) i vbat sleep mode, reset = 0, v bat =?70v ?100?a open (high-impedance), v bat = ?70 v ? 225 ? a active on-hook standby, v bat =?70v ? 400 ? a forward/reverse active off-hook, abias = 4 ma, v bat =?24v ? 4.4 + i lim ?ma forward/reverse oht, obias = 4 ma, v bat =?70v ?8.4?ma ringing, v ring =45v rms , v bat = ?70 v, 1 ren load 2 ?6?ma chipset power consumption p sleep sleep mode, reset = 0, v bat =?70v ?12?mw p open open (high-impedance), v bat =?70v ? 115 ? mw p stby active on-hook standby, v bat =?48v ? 120 ? mw p stby active on-hook standby, v bat =?70v ? 130 ? mw p active 3 forward/reverse active off-hook, abias = 4 ma, v bat =?24v ?385?mw p active 3 forward/reverse active off-hook, abias = 4 ma, v bat =?48v ?490?mw p oht forward/reverse oht, obias = 4 ma, v bat =?48v ?700?mw p oht forward/reverse oht, obias = 4 ma, v bat =?70v ?890?mw p ring ringing, v ring =45v rms , v bat = ?70 v, 1 ren load 2 ?585?mw table 4. 5 v power supply characteristics 1 (continued) (v dd , v dd1 ?v dd4 = 5v, t a = 0 to 70 c for k/f-grade, ?40 to 85 c for b/g-grade) parameter symbol test condition min typ max unit notes: 1. all specifications are for a single channel based on me asurements with both channels in the same operating state. 2. see "ringing power considerations" on page 50 for current and power consumption under other operating conditions. 3. power consumption does not include additional power requir ed for dc loop feed. total system power consumption must include an additional v bat x i loop term.
SI3220/si3225 10 rev. 1.0 table 5. ac characteristics (v dd , v dd1 ?v dd4 = 3.13 to 5.25 v, t a = 0 to 70 c for k/f-grade, ?40 to 85 c for b/g-grade) parameter test condition min typ max unit tx/rx performance overload level 2.5 ? ? v pk overload compression 2-wire ? pcm figure 6 ? ? single frequency distortion 1 2-wire ? pcm or pcm ? 2-wire: 200hz to 3.4khz ???65db pcm ? 2-wire ? pcm: 200 hz ? 3.4 khz, 16-bit linear mode ???65db signal-to-(noise + distortion) ratio 2 200hz to 3.4khz d/a or a/d 8-bit active off-hook, and oht, any z t figure 5 ? ? audio tone generator signal-to- distortion ratio 2 0 dbm0, active off-hook, and oht, any z t 46 ? ? db intermodulation distortion ? ? ?41 db gain accuracy 2 2-wire to pcm or pcm to 2-wire 1014 hz, any gain setting ?0.25 ? +0.25 db attenuation distortion vs. freq. 0 dbm 0 figure 7,8 ? ? ? group delay vs. frequency figure 9 ? ? ? gain tracking 3 1014 hz sine wave, reference level ?10 dbm signal level: ???? 3 db to ?37 db ? ? 0.25 db ?37 db to ?50 db ? ? 0.5 db ?50 db to ?60 db ? ? 1.0 db round-trip group delay 1014 hz, within same time-slot ? 600 700 s crosstalk between channels tx or rx to tx tx or rx to rx 0 dbm0, 300hz to 3.4khz 300hz to 3.4khz ? ? ? ? ?75 ?75 db db gain step increment 4 step size around 0 db ? 0.0005 ? db 2-wire return loss 5 200hz to 3.4khz 26 30 ? db notes: 1. the input signal level should be 0 dbm0 for frequencies greater than 100 hz. for 100 hz and below, the level should be ?10 dbm0. the output signal magnitude at any other freq uency will be smaller than the maximum value specified. 2. analog signal measured as v tip ? v ring . assumes ideal line impedance matching. 3. the quantization errors inherent in the /a-law companding process can generate slightly worse gain tracking performance in the signal range of 3 to ?37 db for signal frequencies that are integer divisors of the 8 khz pcm sampling rate. 4. the digital gain block is a linear multiplier that is programmable from ? to +6 db. the step size in db varies over the complete range. see ?audio path processing?. 5. v dd1 ?v dd4 = 3.3 v, v bat = ?52 v, no fuse resistors, r l = 600 ? , z s = 600 ? synthesized using rs register coefficients. 6. the level of any unwanted tones wit hin the bandwidth of 0 to 4 khz does not exceed ?55 dbm. 7. the obias and abias registers program the dc bias current through the slic in the on-hook transmission and off- hook active conditions, respectively. this per-pin total cu rrent setting should be selected so it can accommodate the sum of the metallic and longitudinal currents through each of the tip and ring leads for a given application.
SI3220/si3225 rev. 1.0 11 transhybrid balance 5 300hz to 3.4khz 34 40 ? db noise performance idle channel noise 6 c-message weighted ? 12 15 dbrnc psophometric weighted ? ?78 ?75 dbmp 3 khz flat ? ? 18 dbrn psrr from v dd1 ?v dd4 rx and tx, dc to 3.4 khz 40 ? ? db psrr from v bat rx and tx, dc to 3.4 khz 60 ? ? db longitudinal performance longitudinal to metallic/pcm balance (forward or reverse) 200hz to 1khz 58 63 ? db 1khz to 3.4khz 53 58 ? db metallic/pcm to longitudinal balance 200 hz to 3.4 khz 40 ? ? db longitudinal impedance 7 200 hz to 3.4 khz at tip or ring register-dependent obias/abias 00 = 4 ma 01 = 8 ma 10 = 12 ma 11 = 16 ma ? ? ? ? 50 25 25 20 ? ? ? ? ? ? ? ? longitudinal current per pin 7 active off-hook 200hz to 3.4khz register-dependent obias/abias 00 = 4 ma 01 = 8 ma 10 = 12 ma 11 = 16 ma ? ? ? ? 4 8 8 10 ? ? ? ? ma ma ma ma table 5. ac characteristics (continued) (v dd , v dd1 ?v dd4 = 3.13 to 5.25 v, t a = 0 to 70 c for k/f-grade, ?40 to 85 c for b/g-grade) parameter test condition min typ max unit notes: 1. the input signal level should be 0 dbm0 for frequencies greater than 100 hz. for 100 hz and below, the level should be ?10 dbm0. the output signal magnitude at any other freq uency will be smaller than the maximum value specified. 2. analog signal measured as v tip ? v ring . assumes ideal line impedance matching. 3. the quantization errors inherent in the /a-law companding process can generate slightly worse gain tracking performance in the signal range of 3 to ?37 db for signal frequencies that are integer divisors of the 8 khz pcm sampling rate. 4. the digital gain block is a linear multiplier that is programmable from ? to +6 db. the step size in db varies over the complete range. see ?audio path processing?. 5. v dd1 ?v dd4 = 3.3 v, v bat = ?52 v, no fuse resistors, r l = 600 ? , z s = 600 ? synthesized using rs register coefficients. 6. the level of any unwanted tones wit hin the bandwidth of 0 to 4 khz does not exceed ?55 dbm. 7. the obias and abias registers program the dc bias current through the slic in the on-hook transmission and off- hook active conditions, respectively. this per-pin total cu rrent setting should be selected so it can accommodate the sum of the metallic and longitudinal currents through each of the tip and ring leads for a given application.
SI3220/si3225 12 rev. 1.0 table 6. linefeed characteristics (v dd , v dd1 ?v dd4 = 3.13 to 5.25 v, t a = 0 to 70 c for k/f-grade, ?40 to 85 c for b/g-grade) parameter symbol test condition min typ max unit maximum loop resistance (adaptive linefeed disabled 1 ) r loop r dc,max 2 = 430 ? , i loop =18ma, v bat =?52v, abias = 8 ma vocdelta = 0 1870 ? ? ? maximum loop resistance (adaptive linefeed enabled 1 ) r loop r dc,max 2 = 430 ? , i loop =18ma, v bat =?52v, abias = 8 ma vocdelta 0 2030 ? ? ? dc loop current accuracy i lim =18ma ? ? 10 % dc open circuit voltage accuracy active mode; v oc =48v, v tip ? v ring ??4 v dc differential outp ut resistance r do i loop < i lim ?320? ? dc on-hook voltage accuracy?ground start v ohto i ring SI3220, ac detection, vring = 70 vpk, no offset, i th = 80ma ?45ma SI3220, dc detection, 20 v dc offset, i th =13ma ?1.52 ma si3225, dc detection, 48 v dc offset, r loop =1500 ? ??4.5ma ringing amplitude, SI3220 3 v ring open circuit, v bath =100v 93 ? ? v pk 5 ren load, r loop =0 ?, v bath = 100 v 82 ? ? v pk sinusoidal ringing total harmonic distortion r thd ?2?% ringing frequency accuracy f = 16 hz to 100 hz ? ? 1 % ringing cadence accuracy accuracy of on/off times ? ? 50 ms calibration time cal to cal bit ? ? 600 ms notes: 1. adaptive linefeed is enabled when the vocdelta ram address is set to a non-zero value and is disabled when vocdelta is set to 0. 2. r dc,max is the maximum dc resistance of the cpe; hence the specified total loop resistance is r loop + r dc,max . 3. ringing amplitude is set for 93 v peak using the ringamp ra m address and measured at tip-ring using no series protection resistance.
SI3220/si3225 rev. 1.0 13 loop voltage sense accuracy ac curacy of boundaries for each output code; v tip ? v ring =48v ?24% loop current sense accuracy accuracy of boundaries for each output code; i loop =18ma ?710% power alarm threshold accuracy power threshold = 300 mw ? ? 25 % table 7. monitor adc characteristics (v dd , v dd1 ?v dd4 = 3.13 to 5.25 v, t a = 0 to 70 c for k/f-grade, ?40 to 85 c for b/g-grade) parameter symbol test condition min typ max unit resolution ? 8 ? bits differential nonlinearity dnl ?1.0 0.75 +1.5 lsb lsb integral nonlinearity inl ? 0.6 1.5 lsb gain error ? 0.1 0.25 lsb table 8. si3200 characteristics (v dd = 3.13 to 5.25 v, t a = 0 to 70 c for k/f-grade, ?40 to 85 c for b/g-grade) parameter symbol test condition min typ max unit tip/ring pulldown transistor satura- tion voltage v ov v ring ? v bat (forward) v tip ? v bat (reverse) i lim =22ma, i abias =4ma 1 i lim =45ma, i abias =16ma 1 ? ? 3 4 ? ? v v tip/ring pullup transistor saturation voltage v cm gnd ? v tip (forward) gnd ? v ring (reverse) i lim =22ma 1 i lim =45ma 1 ? ? 3 4 ? ? v v battery switch saturation impedance r sat (v bat ? v bath )/i out (note 2) ? 15 ?? notes: 1. v ac = 2.5 v pk , r load = 600 ? . 2. i out =60ma table 6. linefeed characteristics (continued) (v dd , v dd1 ?v dd4 = 3.13 to 5.25 v, t a = 0 to 70 c for k/f-grade, ?40 to 85 c for b/g-grade) parameter symbol test condition min typ max unit notes: 1. adaptive linefeed is enabled when the vocdelta ram address is set to a non-zero value and is disabled when vocdelta is set to 0. 2. r dc,max is the maximum dc resistance of the cpe; hence the specified total loop resistance is r loop + r dc,max . 3. ringing amplitude is set for 93 v peak using the ringamp ra m address and measured at tip-ring using no series protection resistance.
SI3220/si3225 14 rev. 1.0 open state tip/ring leakage current i lkg r l =0 ??? 100 a internal blocking diode forward voltage v f v bat ? v batl (note 2) ? 0.8 ? v table 9. dc characteristics (v dd , v dd1 ?v dd4 = 5v) (v dd , v dd1 ?v dd4 = 4.75 v to 5.25 v, t a = 0 to 70 c for k/f-grade, ?40 to 85 c for b/g-grade) parameter symbol test condition min typ max unit high level input voltage v ih 0.7 x v dd ?5.25v low level input voltage v il ? ? 0.3 x v dd v high level output voltage v oh i o =8ma v dd ? 0.6 ? ? v low level output voltage v ol dtx, sdo, int , sdithru: i o =?8ma ??0.4v batsela/b, rrda/b, gpoa/b, trd1a/b,trd2a/b: i o =?40ma ? ? 0.72 v sdithru internal pullup resistance 20 30 ? k ? relay driver source impedance r out v dd1 ?v dd4 =4.75v i o < 28 ma ?63 ? ? relay driver sink impedance r in v dd1 ?v dd4 =4.75v i o < 85 ma ?11 ? ? input leakage current i l ??10 a table 8. si3200 characteristics (continued) (v dd = 3.13 to 5.25 v, t a = 0 to 70 c for k/f-grade, ?40 to 85 c for b/g-grade) parameter symbol test condition min typ max unit notes: 1. v ac = 2.5 v pk , r load = 600 ? . 2. i out =60ma
SI3220/si3225 rev. 1.0 15 table 10. dc characteristics (v dd , v dd1 ?v dd4 = 3.3 v) (v dd , v dd1 ?v dd4 = 3.13 v to 3.47 v, t a = 0 to 70 c for k/f-grade, ?40 to 85 c for b/g-grade) parameter symbol test condition min typ max unit high level input voltage v ih 0.7 x v dd ?5.25v low level input voltage v il ? ? 0.3 x v dd v high level output voltage v oh i o =4ma v dd ?0.6 ? ? v low level output voltage v ol dtx, sdo, int , sdithru: i o =?4ma ??0.4v batsela/b, rrda/b, gpoa/b, trd1a/b, trd2a/b: i o =?40ma ??0.72 sdithru internal pullup resistance 35 50 ? k ? relay driver source imped- ance r out v dd1 ?v dd4 =3.13v io < 28 ma ?63? ? relay driver sink impedance r in v dd1 ?v dd4 =3.13v io < 85 ma ?11? ? input leakage current i l ??10 a table 11. switching characteristics?general inputs 1 (v dd , v dd1 ?v dd4 = 3.13 to 5.25 v, t a = 0 to 70 c for k/f-grade, ?40 to 85 c for b/g-grade, c l = 20 pf) parameter symbol min typ max unit rise time, reset t r ?? 5 ns reset pulse width, gci mode 2 t rl 500 ? ? ns reset pulse width, spi daisy chain mode t rl 6?? s notes: 1. all timing (except rise and fall time) is referenced to the 50% level of the waveform. input test levels are v ih = v dd ? 0.4 v, v il = 0.4 v. rise and fall times are referenced to the 20% and 80% levels of the waveform. 2. the minimum reset pulse width assumes the sdithru pin is tied to ground via a pulldown resistor no greater than 10 k ? per device.
SI3220/si3225 16 rev. 1.0 figure 1. spi timing diagram table 12. switching characteristics?spi v dda =v dda = 3.13 to 5.25 v, t a = 0 to 70 c for k/f-grade, ?40 to 85 c for b/g-grade, c l = 20 pf parameter symbol test conditions min typ max unit cycle time sclk t c 62 ? ? ns rise time, sclk t r ? ? 25 ns fall time, sclk t f ? ? 25 ns delay time, sclk fall to sdo active t d1 ? ? 20 ns delay time, sclk fall to sdo transition t d2 ? ? 20 ns delay time, cs rise to sdo tri-state t d3 ? ? 20 ns setup time, cs to sclk fall t su1 25 ? ? ns hold time, cs to sclk rise t h1 20 ? ? ns setup time, sdi to sclk rise t su2 25 ? ? ns hold time, sdi to sclk rise t h2 20 ? ? ns delay time between chip selects t cs 220 ? ? ns sdi to sdithru propagation delay t d4 ? 4 10 ns note: all timing is referenced to the 50% level of the waveform. input test levels are v ih =v ddd ?0.4 v, v il =0.4v sclk cs sdi t h1 t d3 sdo t d1 t d2 t su1 t r t f t su2 t h2 t cs t c sdithru t d4
SI3220/si3225 rev. 1.0 17 table 13. switching characteristics?pcm highway interface (v dd , v dd1 ?v dd4 = 3.13 to 5.25 v, t a = 0 to 70 c for k/f-grade, ?40 to 85 c for b/g-grade, c l = 20 pf) parameter symbol test conditions min 1 typ 1 max 1 units pclk period t p 122 ? 3906 ns valid pclk inputs ? ? ? ? ? ? ? ? ? 256 512 768 1.024 1.536 1.544 2.048 4.096 8.192 ? ? ? ? ? ? ? ? ? khz khz khz mhz mhz mhz mhz mhz mhz fsync period 2 t fs ?125 ? s pclk duty cycle tolerance t dty 40 50 60 % pclk period jitter tolerance t jitter ? ? 120 ns rise time, pclk t r ? ? 25 ns fall time, pclk t f ? ? 25 ns delay time, pclk rise to dtx active t d1 ? ? 20 ns delay time, pclk rise to dtx transition t d2 ? ? 20 ns delay time, pclk rise to dtx tristate 3 t d3 ? ? 20 ns setup time, fsync to pclk fall t su1 25 ? ? ns hold time, fsync to pclk fall t h1 20 ? ? ns setup time, drx to pclk fall t su2 25 ? ? ns hold time, drx to pclk fall t h2 20 ? ? ns fsync pulse width t wfs t p /2 ? 125 s?t p notes: 1. all timing is referenced to the 50% level of the waveform. input test levels are v ih ? v i/o ? 0.4 v, v il = 0.4 v. 2. fsync source is assumed to be 8 khz under all operating conditions. 3. spec applies to pclk fall to dtx tristate when that mode is selected.
SI3220/si3225 18 rev. 1.0 figure 2. pcm highway interface timing diagram pclk drx fsync dtx t d1 t d2 t su2 t h2 t d3 t r t p t su1 t h1 t f t fs t wfs
SI3220/si3225 rev. 1.0 19 table 14. switching characteristics?gci highway serial interface (v dd , v dd1 ?v dd4 = 3.13 to 5.25 v, t a = 0 to 70 c for k/f-grade, ?40 to 85 c for b/g-grade) figure 3. gci highway interface timing diagram (2.048 mhz pclk mode) parameter 1 symbol test conditions min typ max units pclk period (2.048 mhz pclk mode) t p ?488?ns pclk period (4.096 mhz pclk mode) t p ?244?ns fsync period 2 t fs ?125? s pclk duty cycle tolerance t dty 40 50 60 % fsync jitter tolerance t jitter ??120ns rise time, pclk t r ??25ns fall time, pclk t f ??25ns delay time, pclk rise to dtx active t d1 ??20ns delay time, pclk rise to dtx transition t d2 ??20ns delay time, pclk rise to dtx tristate 3 t d3 ??20ns setup time, fsync rise to pclk fall t su1 25 ? ? ns hold time, pclk fall to fsync fall t h1 20 ? ? ns setup time, drx transition to pclk fall t su2 25 ? ? ns hold time, pclk falling to drx transition t h2 20 ? ? ns fsync pulse width t wfs t p /2 ? ? ns notes: 1. all timing is referenced to the 50% level of the waveform. input test levels are v ih = v o ? 0.4 v, v il = 0.4 v, rise and fall times are referenced to the 20% and 80% levels of the waveform. 2. fsync source is assumed to be 8 k hz under all operating conditions. 3. specification applies to pclk fall to dtx tristate when that mode is selected. t su1 t h1 t p t r t f t h2 t d3 t d2 t d1 pclk fsync drx dtx t fs t su 2 frame 0, bit 0 frame 0, bit 0
SI3220/si3225 20 rev. 1.0 figure 4. gci highway interface timing diagram (4.096 mhz pclk mode) figure 5. transmit and receive path sndr t su1 t h1 t c t r t f t su2 t h2 t d3 t d2 t d1 pclk fsync drx dtx t fs frame 0, bit 0 frame 0, bit 0 acceptable region
SI3220/si3225 rev. 1.0 21 figure 6. overload compression performance figure 7. transmit path frequency response 123456789 1 2 3 4 5 6 7 8 9 0 2.6 acceptable region fundamental input power (dbm0) fundamental output power (dbm0) 0 250 500 750 1000 1250 1500 1750 2000 2250 2500 2750 3000 3250 3500 3750 4000 4250 4500 4750 500 0 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 5 tx attenuation distortion gain (db) frequency (hz) 0 250 500 750 1000 1250 1500 1750 2000 2250 2500 2750 3000 3250 3500 3750 4000 4250 4500 4750 500 0 ?1.2 ?1 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 tx pass?band detail gain (db) frequency (hz)
SI3220/si3225 22 rev. 1.0 figure 8. receive path frequency response 0 250 500 750 1000 1250 1500 1750 2000 2250 2500 2750 3000 3250 3500 3750 4000 4250 4500 4750 500 0 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 5 rx attenuation distortion gain (db) frequency (hz) 0 250 500 750 1000 1250 1500 1750 2000 2250 2500 2750 3000 3250 3500 3750 4000 4250 4500 4750 500 0 ?1.2 ?1 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 rx pass?band detail gain (db) frequency (hz)
SI3220/si3225 rev. 1.0 23 figure 9. transmit group delay distortion figure 10. receive group delay distortion 200 400 600 800 1000 1200 1400 1600 1800 2000 2200 2400 2600 2800 3000 3200 340 0 0 100 200 300 400 500 600 700 800 900 1000 1100 tx group delay distortion delay (us) frequency (hz) 200 400 600 800 1000 1200 1400 1600 1800 2000 2200 2400 2600 2800 3000 3200 340 0 0 100 200 300 400 500 600 700 800 900 1000 1100 rx group delay distortion delay (us) frequency (hz) typical response
SI3220/si3225 24 rev. 1.0 d/a interpolation filter + + decimation filter + from billing tone dac h + interpolation filter rpga /a-law expander serial input decimation filter rhpf to ringer circuit thpf modem tone detection dtmf decode digital rx digital tx dlm2 dual tone generator i buf g m dlm3 diagnostics filter tx eq tpga codec loopback dlm1 pcm loopback hybrid loopback transmit path receive path z a a/d /a-law compressor serial output on-chip off-chip rx mute tx mute analog zsynth disable zsdis rx eq + - + z d figure 11. ac signal path block diagram for a single channel
SI3220/si3225 rev. 1.0 25 tipb ringb ringa tipa gpoa gpob vdd vdd vdd vbath vblo vbath vblo ringa_ext ringa ringb_ext dtx tipa_ext tipb tipb_ext tipa sdo ringb gpoa gpob batswa batswb vbatb vbata /reset sdithru /cs drx sclk sdi batselb fsync batsela pclk /int trd2a trd1a gpoa gpob trd1b trd2b protection protection r5 806k r3 4.7k r15 806k r25 39k u3 si3200 tip 1 nc 2 ring 3 vbat 4 vbath 5 vbatl 6 gnd 7 vdd 8 nc 11 nc 10 batsel 9 iringp 13 iringn 12 therm 14 itipp 16 itipn 15 gnd epad r2 402k r12 402k c14 10n 100v r23 15 j1 rj-11 smd 1 2 3 4 5 6 u1 SI3220 qgnd 8 cappb 11 stipdcb 17 nc 28 batselb 32 trd2a 50 trd1a 51 gpob 31 nc 53 rpoa 2 itipnb 21 itippb 23 gnd2 25 vdd2 24 stipaca 63 therma 54 sringaca 62 iringna 59 iringpa 55 itippa 58 cappa 6 sringdca 61 vdd1 57 itipna 60 rpia 3 rnia 4 stipacb 18 sringacb 19 nc 52 iringpb 26 rpob 15 rnoa 5 capma 7 iringnb 22 rpib 14 stipdca 64 gnd1 56 sringdcb 20 capmb 10 iref 9 rnob 12 rnib 13 fsync 34 trd1b 29 trd2b 30 svbata 1 drx 35 svbatb 16 /cs 47 pclk 39 sdo 44 dtx 36 vdd3 37 sdithru 46 thermb 27 sdi 45 gnd3 38 /rst 33 sclk 43 batsela 49 vdd4 42 /int 40 gpoa 48 gnd4 41 c1 0.1u 100v x7r tp1 1 c4 10n 100v tp5 1 c15 1u 6v r6 40.2k r21 15 j6 1 2 c23 0.1u 10v tp8 1 tp6 1 c2 0.1u 100v x7r c3 10n 100v c30 0.1u 100v r18 182 c16 1u 6v r13 4.7k r10 40.2k c5 1u 6v u2 si3200 tip 1 nc 2 ring 3 vbat 4 vbath 5 vbatl 6 gnd 7 vdd 8 nc 11 nc 10 batsel 9 iringp 13 iringn 12 therm 14 itipp 16 itipn 15 gnd epad c33 0.1u 100v r8 182 c11 0.1u 100v x7r r7 182 r11 402k j7 1 2 r24 39k tp7 1 c12 0.1u 100v x7r tp2 1 r22 390 c13 10n 100v c6 1u 6v r14 4.7k r17 182 c31 0.1u 100v c32 0.1u 100v c24 0.1u 10v j11 rj-11 smd 1 2 3 4 5 6 tp3 1 r20 390 j5 1 2 r4 4.7k j2 1 2 j3 1 2 r1 402k tp4 1 j4 1 2 r16 40.2k figure 12. SI3220 application circuit using dual battery supply
SI3220/si3225 26 rev. 1.0 rrda rrda rrdb rrdb rngngb trd1a trd2b trd1b trd2a rngnga vdd vrngsource vblo vrngsource vblo vdd vbhi vdd vdd vdd vbhi sdithru sdo sclk sdi fsync /reset pclk dtx /int /cs drx ringa_ext tipa tipa_ext ringa tipb tipb_ext ringb ringb_ext protection protection trd1b rrdb rrda trd2b trd1a trd2a r10 40.2k c6 1u 6v r25 390 c32 0.1u 100v u1 si3225 qgnd 8 cappb 11 stipdcb 17 rtrpb 28 batselb 32 trd2a 50 trd1a 51 rrdb 31 blkrng 53 rpoa 2 itipnb 21 itippb 23 gnd2 25 vdd2 24 stipaca 63 therma 54 sringaca 62 iringna 59 iringpa 55 itippa 58 cappa 6 sringdca 61 vdd1 57 itipna 60 rpia 3 rnia 4 stipacb 18 sringacb 19 rtrpa 52 iringpb 26 rpob 15 rnoa 5 capma 7 iringnb 22 rpib 14 stipdca 64 gnd1 56 sringdcb 20 capmb 10 iref 9 rnob 12 rnib 13 fsync 34 trd1b 29 trd2b 30 svbata 1 drx 35 svbatb 16 /cs 47 pclk 39 sdo 44 dtx 36 vdd3 37 sdithru 46 thermb 27 sdi 45 gnd3 38 /rst 33 sclk 43 batsela 49 vdd4 42 /int 40 rrda 48 gnd4 41 c15 1u 6v u2 si3200 tip 1 nc 2 ring 3 vbat 4 vbath 5 vbatl 6 gnd 7 vdd 8 nc 11 nc 10 batsel 9 iringp 13 iringn 12 therm 14 itipp 16 itipn 15 gnd epad tp1 tip a 1 c16 1u 6v tp2 ring a 1 k2 dpdt 3 2 4 8 9 7 1 10 tp3 tip b 1 u3 si3200 tip 1 nc 2 ring 3 vbat 4 vbath 5 vbatl 6 gnd 7 vdd 8 nc 11 nc 10 batsel 9 iringp 13 iringn 12 therm 14 itipp 16 itipn 15 gnd epad tp4 ring b 1 tp5 gnd 1 r24 15 c5 1u 6v tp6 gnd 1 j4 1 2 r22 510 j1 rj-11 smd 1 2 3 4 5 6 r21 510 r26 15 r6 40.2k c24 0.1u 10v c30 0.1u 100v j7 1 2 k1 dpdt 3 2 4 8 9 7 1 10 c31 0.1u 100v j11 rj-11 smd 1 2 3 4 5 6 tp8 gnd 1 r16 40.2k r19 806k c3 10n 100v c2 0.1u 100v x7r r27 39k j3 1 2 c4 10n 100v c25 0.1u 10v r23 390 c13 10n 100v c14 10n 100v j6 1 2 c11 0.1u 100v x7r r11 402k r12 402k c12 0.1u 100v x7r r13 4.7k r7 182 r28 39k r14 4.7k j2 1 2 c1 0.1u 100v x7r r15 806k r18 182 tp7 gnd 1 c33 0.1u 100v r17 182 r1 402k r2 402k r3 4.7k r4 4.7k r8 182 r5 806k j5 1 2 r20 806k r9 806k figure 13. si3225 application circuit using centralized ringer and secondary battery supply
SI3220/si3225 rev. 1.0 27 bill of materials table 15. SI3220 + si3200 external component values component value function c1, c2, c11, c12 100 nf, 100 v, x7r, 20% filter capacitors for tip, ring ac-sensing inputs. c3, c4, c13, c14 10 nf, 100 v, x7r, 20% tip/ring compensation capacitors. c5, c6, c15, c16 1 f, 6.3 v, x7r, 20% low-pass filter capacitors to stabilize differential and common-mode slic feedback loops. c30?c33 0.1 f, 100 v, y5v decoupling for battery voltage supply pins. c20?c25 0.1 f, 1 0 v, y 5 v decoupling for analog and digital chip supply pins. r1, r2, r11, r12 402 k ? , 1/10 w, 1% sense resistors for tip, ring voltage-sensing nodes. r3, r4, r13, r14 4.7 k ? , 1/10 w, 1% current limiting resistors for tip, ring ac-sensing inputs. r5, r15 806 k ? , 1/10 w, 1% sense resistor for battery dc-sensing nodes. r6, r16 40.2 k ? , 1/10 w, 5% sets bias current for battery-switching circuit. r7, r8, r17, r18 182 ? , 1/10 w, 1% reference resistors for internal transconductance amplifier. r10 40.2 k ? , 1/10 w, 1% generates a high accuracy reference current. r20, r22 390 ? , 1/10 w, 5% protection against power supply transients. r21, r23 15 ? , 1/8 w, 5% protection against power supply transients. r24, r25 39 k ? , 1/10 w, 5% pull-down resistors. table 16. si3225 + si3200 external component values component value function c1, c2, c11, c12 100 nf, 100 v, x7r, 20% filter capacitors for tip, ring ac sensing inputs. c3, c4, c13, c14 10 nf, 100 v, x7r, 20% tip/ring compensation capacitors. c5, c6, c15, c16 1 f, 6.3 v, x7r, 20% low-pass filter capacitors to stabilize differential and com- mon mode slic feedback loops. c30 1 , c31 1 , c32, c33 0.1 f, 1 0 0 v, y 5 v decoupling for battery voltage supply pins. c20?c25 0.1 f, 1 0 v, y 5 v decoupling for analog and digital chip supply pins. r1, r2, r11, r12 402 k ? , 1/10 w, 1% sense resistors for tip, ring dc sensing nodes. r5, r15 806 k ? , 1/10 w, 1% sense resistors for battery voltage sensing nodes. r3, r4, r13, r14 4.7 k ? , 1/10 w, 1% current limiting resistors for ti p, ring ac sensing inputs. r6 1 , r16 1 40.2 k ? , 1/10 w, 5% sets bias current for battery switching circuit. r7, r8, r17, r18 182 ? , 1/10 w, 1% reference resistors for internal transconductance amplifier. r9, r19, r20 806 k ? , 1/10 w, 1% sense registers for ringing generator feed. r10 40.2 k ? , 1/10 w, 1% generates a high accuracy reference current. r21, r22 510 ? , 2w, 2% 2 feed resistor for ringing generator source. r23, r25 390 ? , 1/10 w, 5% protection against power supply transients. r24, r26 15 ? , 1/8 w, 5% protection against power supply transients. r27, r28 39 k ? , 1/10 w, 5% pull-down resistors. notes: 1. optional. only required when using dual-battery architecture. 2. example power rating.
SI3220/si3225 28 rev. 1.0 functional description the dual proslic ? chipset is a thre e-chip integrated solution that provides all slic, codec, and dtmf detection/decoding functions needed for a complete dual-channel analog telephone interface. intended for multiple-channel long-loop (up to 18 kft) applications requiring high-density line card designs, the dual proslic chipset provides high integration and low- power operation for applications, such as central office (co) and digital loop carrier (dlc) enclosures. the dual proslic chipset is also ideal for short-loop applications requiring a space-effective solution, such as terminal adapters, integrated access devices (iads), pbx/key systems, and voice- over ip systems. the chipset meets all relevant bellcore lssgr, itu, and etsi standards. the SI3220/si3225 ics perform all battery, overvoltage, ringing, supervision, codec, hybrid, and test (borscht) functions on-chip in a low-power, small- footprint solution. dtmf decoding and generation, phase continuous fsk (caller id) signaling, and pulse metering are also integrated. all high-voltage functions are implemented using the si3200 linefeed interface ic allowing a highly-programmable integrated solution that offers the lowest total system cost. the internal linefeed circuitry provides programmable on-hook voltage and off-current loop current, reverse battery operation, loop or ground-start operation, and on-hook transmission. loop current and voltage are continuously monitored using an integrated 8-bit monitor a/d converter. the SI3220 provides on-chip balanced 5 ren ringing with or without a programmable dc offset eliminating the need for an external bulk ring generator and per-channel ringing relay. both sinusoidal and trapezoidal ringing waveshapes are available. ringing parameters, such as frequency, waveshape, cadence, and offset are available in registers to reduce external controller requirements. the si3225 supports external ringing generation with ring relay driver and external ring trip sensing to address legacy systems that implement a centralized ringing architecture. all ringing options are software-programmable over a wide range of parameters to address a wide variety of application requirements. the SI3220/si3225 ics also provide a variety of line monitoring and subscriber loop testing functions. all versions have the ability to generate specific dc and audio signals and continuously monitor and store all line voltage and current parameters. this combination of signal generation and measurement tools allows remote line card and loop diagnostics without requiring additional test equipment. these diagnostic functions are intended to comply with relevant lssgr and itu requirements for line-fault detection and reporting, and measured values are stored in registers for later use or further calculations. the SI3220 and si3225 also include two per-channel relay drivers to support legacy systems implementing centralized test equipment. a complete audio transmit and receive path is integrated, including dtmf generation and decoding, tone generation, modem/fax tone detection, programmable ac impedance synthesis, and programmable transhybrid balance and programmable gain attenuation. these features are software- programmable providing a single hardware design to meet international requirements. digital voice data transfer occurs over a standard pcm bus, and control data is transferred using a standard 4-wire serial peripheral interface (spi). the SI3220 and si3225 can also be configured to support a 4-wire general circuit interface (gci). the SI3220 and si3225 are available in a 64-lead tqfp, and the si3200 is available in a thermally-enhanced 16-lead soic. dual proslic architecture the dual proslic chipset is comprised of a low-voltage cmos device that uses a low-cost integrated linefeed interface ic to control the high voltages needed for operating the terminal equipment connected to the telephone line. figure 15 on page 30 presents a simplified diagram of the linefeed control loop circuit for controlling the tip and ri ng leads. the diagram illustrates a single-ended m odel for simplicity, showing either the tip or the ring lead. the dual proslic chipset produces line voltages and currents on the tip/ring pair using register- programmable settings in the SI3220 and si3225 as well as direct ac and dc voltage/current sensing from the line. the si3200 lfic prov ides a low-cost interface for bridging the low-voltage cmos devices to the high- voltage tip/ring pair. sens e resistors allow the voltage and current to be measured on each lead or across t-r using the low-voltage circuitry inside the SI3220 and si3225 eliminating expensive analog sensing circuitry inside the high-voltage si3200. in addition, the total power inside the si3200 is constantly monitored and controlled to provide optimal reliability under all operating conditions. the sensing circuitry is calibrated for environmental and process variations to guarantee accuracy with standard external resistor tolerances.
SI3220/si3225 rev. 1.0 29 dc feed characteristics the SI3220 and si3225 offer programmable constant- voltage and constant-current operating regions as illustrated in figure 14 and figure . the constant voltage region (defined by the open-circuit voltage, v oc ) is programmable from 0 to 63.3 v in 1 v steps. the constant current region (defined by the loop current limit, i lim ) is programmable from 18 to 45 ma in 0.87 ma steps. the SI3220 and si3225 exhibit a characteristic dc impedance of 640 ? or 320 ? during active mode. (see "adaptive linefeed" on page 32). the tip-ring voltage (v oc ) is offset from ground by a programmable voltage (v cm ) to provide sufficient voltage headroom to the most positive terminal (typically the tip lead in normal polarity or the ring lead in reverse polarity) for carrying audio signals. a similar programmable voltage (v ov ) is an offset between the most negative terminal and the battery supply rail for carrying audio signals. (see figure 14.) the user-supplied battery voltage must have sufficient amplitude under all operating states to ensure sufficient headroom. the si3200 may be powered by a lower secondary battery supply (v batl ) to reduce total power dissipation when driving short-loop lengths. figure 14. dc linefeed overhead voltages (forward state) calculating overhead voltages the two programmable overhead voltages (v ov and v cm ) represent one portion of the total voltage between v bat and ground as illustrated in figure 14. under normal operating conditions, these overhead voltages are sufficiently low to ma intain the desired tip-ring voltage (v oc ). however, there are certain conditions under which the user must exercise care in providing a battery supply with enough amplitude to supply the required tip-ring voltage and enough margin to accommodate these overhead voltages. the v cm voltage is programmed for a given operating condition. therefore, the open-circuit voltage (v oc ) varies according to the required overhead voltage (v ov ) and the supplied battery voltage (v bat ). the user should pay attention to the maximum v ov and v cm that might be required for each operating state. in the off-hook active state, sufficient v oc must be maintained to correctly power the phone from the battery supply that is provided. because the battery supply depends on the state of the input supply (i.e., charging, discharging, or battery backup mode), the user must decide how much loop current is required and determine the maximum loop impedance that can be driven based on the battery supply provided. the minimum battery supply required can be calculated with the following equation: where v cm and v ov are provided in table 8 on page 13. the default v cm value of 3 v provides sufficient overhead for a 3.1 dbm signal into a 600 ? loop impedance with an i lim setting of 22 ma and an abias setting of 4 ma. a v ov value of 4 v provides sufficient headroom to source a maximum i loop of 45 ma with a 3.1 dbm audio signal and an abias setting of 16 ma. for a typical operating condition of v bat = ?56 v and i lim =22ma: these conditions apply when the dc-sensing inputs (stipdca/b and sringdca/b) are placed on the slic side of any protection resistance placed in series with the tip and ring leads. if lin e-side sensing is desired, both v ov and v cm must be increased by a voltage equal to r prot xi lim where r prot is the value of each protection resistor. other safety precautions may also apply. see "linefeed overhead voltage considerations during ringing" on page 50 for details on calculating the overhead voltage during the ringing state. the dual proslic chipset uses both voltage and current information to control tip and ring. sense resistor r dc measures dc line voltages on tip and ring; capacitor c ac couples the ac line voltages on the tip and ring leads to be measured. the SI3220 and si3225 both use the si3200 to drive tip and ring and isolate the high-voltage line from the low-voltage cmos devices. the SI3220 and si3225 measure voltage at various nodes to monitor the linefeed current. r dc and r bat provide these measuring points. the sense circuitry is calibrated on-chip to guarantee measurement accuracy. see "linefeed calibration" on page 35 for details. constant i region constant v region v cm v oc v ov v ov r loop v bath v tip v ring v batl secondary v bat selected v loop closure threshold v bat v oc v cm v ov ++ v oc max , 56 v 3 v 4 v + () ? 49 v ==
SI3220/si3225 30 rev. 1.0 figure 15. simplified dual proslic linefeed architecture for tip and ring leads (diagram illustrates either tip or ring lead of a single channel) dsp a/d d/a d/a a/d slic control audio control slic control loop audio control loop v bat sense r dc r bat tip or ring c ac SI3220/ si3225 monitor a/d slic dac current mirror battery select control v bat v bath si3200 low frequency diagnostic filters audio diagnostic filters audio codec v batl svbat batsel stipdc/sringdc itipp/iringp itipn/iringn stipac/sringac
SI3220/si3225 rev. 1.0 31 linefeed operation states the linefeed interface includes eight different operating states as shown in tabl e 17. the linefeed register settings (lf[2:0], linefeed register) are also listed. the open state is the default c ondition in the absence of any pre-loaded register settings. the device may also automatically enter the open state if excess power consumption is detected in the si3200. see "power monitoring and power fault detection" on page 35 for more details. the register and ram locations used for programming the linefeed parameters are provided in table 18. see ?loop voltage and current monitoring? and "power monitoring and power fault detection" on page 35, and "power dissipation considerations" on page 39 for detailed descriptions and register/ram locations for these functions. table 17. linefeed states open (lf[2:0] = 000). the si3200 output is high-impedance. this mode can be used in the presence of line fault conditions and to generate open-switch intervals (osis). the device can al so automatically enter the open state if excess power consumption is detected in the si3200 or in the discrete bipolar transistors. forward active (lf[2:0] = 001). linefeed is active, but audio paths are powered down un til an off-hook condition is detected. the SI3220 and si3225 automatically enter a low-power state to reduce power consumption during on-hook standby periods. forward on-hook transmission (lf[2:0] = 010). provides data transmission during an on-hook loop co ndition (e.g., transmitting fsk caller id information between ringing bursts). tip open (lf[2:0] = 011). sets the portion of the linefeed interface connected to the tip side of the subscriber loop to high-impedance and provides an active linefeed on the ring side of the loop for ground-start operation. ringing (lf[2:0] = 100). drives programmable ringing waveforms onto the subscriber loop (SI3220) or switches in a centralized ringing generator by driving an external relay (si3225). reverse active (lf[2:0] = 101). linefeed circuitry is active, but audio paths are powere d down until an off-hook condition is detected. the SI3220 and si3225 automatically enter a low-power state to reduce power consumption during on-hook standby periods. reverse on-hook transmission (lf[2:0] = 110). provide data transmission during an on-hook loop condition. ring open (lf[2:0] = 111). sets the portion of the linefeed interface connected to th e ring side of the subscriber loop to high impedance and provides an active linefeed on the tip si de of the loop for ground start operation.
SI3220/si3225 32 rev. 1.0 adaptive linefeed the SI3220/si3225 features a proprietary dc feed design known as adaptive linefeed. figure 16 shows the v/i characteristics of adaptive linefeed. essentially, adaptive linefeed changes the source impedance of the dc feed as well as the apparent open-circuit voltage (voc) in order to ensure the ability to source ext ended loop lengths. the following sections provide a detailed explanation of adaptive linefeed. adaptive linefeed example this section provides a detailed description of adaptive linefeed operation by utilizing an example. the behavior of adaptive linefeed is controlled by the following ram locations: vov, vcm, voc, voclth, vochth and vocdelta (see equation 1). the ilim register also plays a role in determining the behavior of the dc feed as it sets the current limit for the constant current source. ilim is a 5-bit register field, which is programmable from 18 ma to 45 ma in 0.875 ma steps (i.e., ilim = 0x0 corresponds to 18 ma and ilim= 0x1f corresponds to 45 ma). the following equation is used to calculate vov, vcm, voc, voclth, vochth and vocdelta. in the above equation, the round function rounds the result to the nearest integer while the ceiling function rounds-up the result to the nearest integer. the dec2hex function converts a decimal integer into a hexadecimal integer. the ram values shown in table 19 where used to generate the adaptive linefeed v/i curve shown in figure 16. note that a battery voltage of ?56 v was assumed, as shown in table 19. table 18. register and ram locations for linefeed control parameter register/ ram mnemonic register/ram bits programmabl e range lsb size effective resolutio n linefeed linefeed lf[2:0] see table 17 n/a n/a linefeed shadow linefeed lfs[2:0] monitor only n/a n/a battery feed control rly con batsel vbath/vbatl n/a n/a loop current limit ilim ilim[ 4:0] 18?45 ma 0.875 ma 0.875 ma on-hook line voltage voc voc[14:0] 0 to 63.3 v 4.907 mv 1.005 v common mode voltage vcm vcm[14:0] 0 to 63.3 v 4.907 mv 1.005 v v oc delta for off-hook vocdelta vocdelta[14:0] 0 to 63.3 v 4.907 mv 1.005 v v oc delta threshold, low voclth voclth[15:0] 0 to 63.3 v 4.907 mv 1.005 v v oc delta threshold, high vochth vochth[15:0] 0 to 63.3 v 4.907 mv 1.005 v overhead voltage vov vov[14:0] 0 to 63.3 v 4.907 mv 1.005 v ringing overhead voltage vovring vovring[14:0] 0 to 63.3 v 4.907 mv 1.005 v v oc during battery tracking voctrack voct rack[15:0] 0 to 63.3 v 4.907 mv 1.005 v ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = 5 512 005 1 2 2 v . voltage _ desired round ceiling hex dec ramvalue table 19. adaptive linefeed example values vbat vov vcm voc ilim voclth vochth vocdelta ?56 v 4 v 3 v ?48 v 20 ma ?7 v +2 v +6 v
SI3220/si3225 rev. 1.0 33 figure 16. adaptive linefeed v/i behavior when the SI3220/si3225 is used with the si3200 linefeed device, the source impedance of the dc feed is 640 ? before the adaptive linefeed transition and 320 ? after the adaptive linefeed transition, as shown in figure 16. on the other hand, when the SI3220/si3225 is used with a discrete bipolar transistor linefeed the source impedance of the dc feed is 320 ? both before and after the adaptive linefeed transition. the loop closure thresholds are programmable via the lcroffhk and lcronhk ram addresses. the lcrlpf ram address provides filtering of the measured loop current, and the lcrdbi ram address provides de-bouncing. the lcr status bit in register lcrrtp indicates when a loop closure event has been detected. see ?loop closure detection? on page 42 for additional details. on-hook to off-hook transition referring to figure 16, point 1 represents the open- circuit voltage (voc = ?48 v) of the dc feed. at point 1, the source impedance of the dc feed is 640 ? (320 ? for discrete bipolar transistor linefeed) and vtip/ ring = voc, since no current flows in the loop. when a dc load is connected across tip and ring and as dc current begins to flow in the dc loop, the product of the dc loop current and the 640 ? source impedance (320 ? for a discrete bipolar transistor linefeed) causes the vtip/ring voltage to decline linearly with increasing loop current. when the vtip/ring voltage reaches the voclth threshold (point 2), adaptive linefeed switches the source impedance of the dc feed to 320 ? and simultaneously boosts the value of voc by vocdelta (point 3). the source impedance of the dc feed will now remain at 320 ? until the programmed current limit (ilim) is reached (point 4). at point 4, the dc feed has entered into the constant current mode of operation. adaptive linefeed can be disabled by writing a value of zero into the vocdelta ram address. writing a value of zero to vocdelta simp ly eliminates the apparent
SI3220/si3225 34 rev. 1.0 voc voltage boost associated with a non-zero vocdelta value. with vocdelta = 0 in the case of the si3200, the adaptive lin efeed transition still changes the source impedance from 640 ? to 320 ? , and there is a corresponding discontinui ty at the transition point. in the case of the discrete bipolar linefeed, since the source impedance is 320 ? both before and after the adaptive linefeed transition, the v/i curve exhibits no discontinuity at the transition points when vocdelta = 0. off-hook to on-hook transition as the dc loop is opened, the dc feed will exit the constant current region (point 4) and enter the 320 ? source impedance region. as the current in the loop collapses, the vtip/ring voltage will linearly increase until vochth (point 5) is reached. at this point adaptive linefeed w ill transition to a source impedance of 640 ? (320 ? for discrete bipolar transistor linefeed) and decrease the voc voltage by vocdelta (point 6). load lines of 10 k ? , 1930 ?, and 1800 ? are shown in figure 16. these load lines intercept the linefeed v/i curve at the v/i point that would result if a load of that resistance value were connected across tip and ring. voctrack and adaptive linefeed hysteresis the two thresholds, voclth and vochth, control adaptive linefeed hysteresis as seen in figure 16. voctrack is a ram location and is the actual open- circuit voltage that is being fed to the line. voctrack is dependent on the measured vbat voltage. the behavior of voctrack is as shown in the equation below. simply put, as long as vbat is sufficient to supply voc + vov + vcm, vo ctrack is equal to the programmed voc. however, if vbat becomes too small to support voc + vov + vcm, then voctrack will track the battery voltag e so that the programmed vov and vcm are satisfied at the expense of a reduced voc voltage. in the exampl e of figure 16, therefore, voctrack = voc = 48 v. the following equation describes voctrack behavior. the values of voclth and vochth are set relative to voctrack. in the example shown in figure 16, voclth is given as ?7 v and vochth as +2 v. this implies that the voclth thre shold is located 7 v below the prevailing value of voctrack, while the vochth threshold is located 2 v ab ove the prevailing value of voctrack. therefore, the voclth and vochth thresholds will automatically track the battery voltage along with voctrack. in order to provide an adequate level of adaptive linefeed hysteresis between the on-hook to off-transition and the off-hook to on-hook transition, voclth is programmed below voctrack (e.g., ?7 v relative to voctrack), and vochth is programmed above voctrack (e.g., +2 v ab ove voctrack). also, vochth must be less than vov ?1 v to ensure that a proper adaptive linefeed transition will occur in a reduced battery scenario. ground start operation to configure the dc feed for ground start operation, it is necessary to write the linefeed register with the value corresponding to either tip-open (lf[2:0] = 011) or ring-open (lf[2:0] = 1 11). the tip-open and ring-open linefeed modes place the indicated lead in the open state (>150 k ? ) while the othe r lead remains active. in ground start operation, an off-hook condition is signaled by the cpe (customer premise equipment) by connecting the active lead to earth ground. the active lead presents a 640 ? source impedance before the adaptive linefeed transition (320 ? for a discrete bipolar linefeed), and a 320 ? source impedance after the adaptiv e linefeed transition, as shown in figure 17. as for loop start operation, the adaptive linefeed transitions are governed by the contents of the vocl th and vochth ram addresses. the open lead presents a high-impedance (>150 k ? ). figure 17 illustrates the ground-start vring/iring behavior using voc = 48 v and i lim =24ma in the tip-open linefeed state. the ground key current thresholds are programma ble via the longloth and longhith ram addresse s. the longlpf ram address provides filtering of the measured longitudinal currents, and the longdbi ram address provides de- bouncing. the longhi status bit in register lcrrtp indicates when a ground key event has been detected. upon detecting a ground key event, the linefeed automatically transitions to the forward active (if initially in tip-open) or reverse active (if initially in ring-open). see ?ground key detection? on page 43 for additional details. ) v v ( | v | voctrack v v v | v | voc voctrack v v v | v | cm ov bat cm ov oc bat cm ov oc bat + ? = ? + + < = ? + +
SI3220/si3225 rev. 1.0 35 figure 17. ground start v ring /i ring behavior linefeed calibration an internal calibration algorithm corrects for internal and external component errors. the calibration is initiated by setting the cal register bit. this bit automatically resets upon completion of the calibration cycle. a calibration should be executed following system powerup. upon release of the chip reset, the chipset will be in the open state, and calibration may be initiated. only one calibration should be necessary if the system remains powered up. to optimize dual proslic performance, the calibration routine in ?an58: SI3220/si3225 programmer?s guide? should be followed. loop voltage and current monitoring the dual proslic chipset continuously monitors the tip and ring voltages and currents. these values are available in registers. an internal 8-bit a/d converter samples the measured voltages and currents from the analog sense circuitry and translates them into the digital domain. the a/d updates the samples at an 800 hz rate for all inputs except vrngng and irngng, which are sampled at 8 khz to provide higher resolution for zero-crossing detection in external ringing applications. two derived values, the loop voltage (v tip ?v ring ) and the loop current are also reported. for ground start operation, the values reported are v ring and the current flowing in the ring lead. table 20 lists the register set associated with the loop monitoring functions. the dual proslic chipsets also include the ability to perform loop diagnostic functions as outlined in "line test and diagnostics" on page 91. power monitoring and power fault detection the dual proslic line monitoring functions can be used to protect the high-voltage circuitry against excessive power dissipation and thermal overload conditions. the dual proslic devices can prevent thermal overloads by regulating the total power inside the si3200 or in each of the external bipolar transistors (if using a discrete linefeed circuit). the dsp engine performs all power calculatio ns and provides the ability to automatically transition the device into the open state and generate a power alarm interrupt when excessive power is detected. table 21 on page 39 describes the register and ram locations used for power monitoring. 0 ma -48 v -80 v -40 v -20 v -0 v 24 ma voclth vochth 6 4 0 ? 3 2 0 ? voc delta i lim = 24 ma i ring v ring
SI3220/si3225 36 rev. 1.0 figure 18. discrete linefeed circuit for power monitoring table 20. register and ram locations used for loop monitoring parameter register/ram mnemonic register/ram bits measurement range lsb size effective resolution loop voltage sense (v tip ?v ring ) vloop vloop[15:0] 0 to 64.07 v 64.07 to 160.173 v 4.907 mv 251 mv 628 mv tip voltage sense vtip vtip[15:0] 0 to 64.07 v 64.07 to 160.173 v 4.907 mv 251 mv 628 mv ring voltage sense vring vring[15:0] 0 to 64.07 v 64.07 to 160.173 v 4.907 mv 251 mv 628 mv loop current sense iloop iloop[15:0] 0 to 101.09 ma 3.097 a 500 a* battery voltage sense vbat vbat[15:0] 0 to 63.3 v 0 to 160.173 v 4.907 mv 251 mv 628 mv longitudinal current sense ilong ilong[15:0] 0 to 101.09 ma 3.097 a 500 a* external ringing gen- erator voltage sense vrngng vrngng[15:0] 33 2.04 v 10.172 mv 1.302 v external ringing gen- erator current sense irngng irngng[15: 0] 662.83 ma 20.3 a2.6ma *note: i loop and i long are calculated values based on measured i q1 ?i q4 currents. the resulting effective resolution is approximately 500 a. q2 q5 r7 iringp q9 r7*gain iringn q3 ring q1 q6 r6 itipp q10 r6*gain itipn q4 tip vbat rbq6 rbq5 q8 q7 82.5 1.74k 82.5 1.74k
SI3220/si3225 rev. 1.0 37 transistor power equations (using discrete transistors) when using the SI3220 or si3225 along with discrete bipolar transistors, it is po ssible to control the total power of the solution by individually regulating the power in each discrete trans istor. figure 18 illustrates the basic transistor-based linefeed circuit for one channel. the power dissipation of each external transistor is estimated based on the a/d sample values. the approximate power equations for each external bjt are as follows: p q1 ? v ce1 x i q1 ? (|v tip | + 0.75 v) x (i q1 ) p q2 ? v ce2 x i q2 ? (|v ring | + 0.75 v) x (i q2 ) p q3 ? v ce3 x i q3 ? (|v bat | ? r7 x i q5 ) x (i q3 ) p q4 ? v ce4 x i q4 ? (|v bat | ? r6 x i q6 ) x (i q4 ) p q5 ? v ce5 x i q5 ? (|v bat | ? |v ring | ? r7 x i q5 ) x (i q5 ) p q6 ? v ce6 x i q6 ? (|v bat | ? |v tip | ? r6 x i q6 ) x (i q6 ) the maximum power threshold for each device is software-programmable and should be set based on the characteristics of the transistor package, pcb design, and available airflow. if the peak power exceeds the programmed threshold for any device, the power-alarm bit is set for that device. each external bipolar has its own register bit (pq1s?pq6s bits of the irqvec3 register), which goes high on a rising edge of the comparator output and remains high until the user clears it. each transistor power alarm bit is also maskable by setting the pq1e?pq6e bits in the irqen3 register. si3200 power calculation when using the si3200, it is also possible to detect the thermal conditions of the linefeed circuit by calculating the total power dissipated within the si3200. this case is similar to the transistor power equations case, with the exception that the total power from all transistor devices is dissipated within the same package enclosure, and the total power result is placed in the psum ram location. the power calculation is derived using the following set of equations: p q1 ? (|v tip | + 0.75 v) x i q1 p q2 ? (|v ring | + 0.75 v) x i q2 p q3 ? (|v bat |+ 0.75 v) x i q3 p q4 ? (|v bat | + 0.75 v) x i q4 p q5 ? (|v bat | ? |v ring |) x i q5 p q6 ? (|v bat | ? |v tip |) x i q6 psum = total dissipated power = p q1 + p q2 + p q3 + p q4 + p q5 + p q6 note: the si3200 therm pin must be connected to the therm a/b pin of the SI3220/si3225 in order for the si3200 power calculation method to work correctly. power filter and alarms the power calculated during each a/d sample period must be filtered before being compared to a user- programmable maximum power threshold. a simple digital low-pass filter is used to approximate the transient thermal behavior of the package, with the output of the filter representing the effective peak power within the package or, equivalently, the peak junction temperature. for q1, q2, q3, and q4 in sot23 and q5 and q6 in sot223 packages, the settings for thermal low-pass filter poles and power threshold settings are (for an ambient temperature of 70 c) calculated as follows: if the thermal time constant of the package is thermal , the decimal values of ram locations plpf12, plpf34, and plpf56 are given by rounding to the next integer the value given by the following equation: where 4096 is the maximum value of the 12-bit plus sign ram locations plpf 12, plpf34, and plpf56, and 800 is the power calculation clock rate in hz. the equation is an excellent ap proximation of the exact equation for thermal = 1.25 ms ? 5.12 s. with the above equations in mind, ex ample values of the ram locations, pth12, pth34, pth56, plpf12, plpf34, and plpf56 are as follows: pth12 = power threshold for q1, q2 = 0.3 w (0x25a) pth34 = power threshold for q3, q4 = 0.22 w (0x1b5e) pth56 = power threshold for q5, q6 = 1 w (0x7d8) plpf12 = q1/q2 thermal lpf pole = 0x0012 (for sot?89 package) plpf34 = q3/q4 thermal lpf pole = 0x008c (for sot?23 package) plpf56 = q5/q6 thermal lpf pole = 0x000e (for sot?223 package) in the case where the si3200 is used, thermal filtering needs to be performed only on the total power reflected in the psum ram location. when the filter output exceeds the total power threshold, an interrupt is issued. the pth12 ram location is used to preset the total power threshold for the si3200, and the plpf12 ram location is used to preset the thermal low-pass filter pole. plpfxx (decimal value) 4096 800 thermal ------------------------------------ 2 3 =
SI3220/si3225 38 rev. 1.0 when the therm pin is connected from the SI3220 or si3225 to the si3200 (indicating the presence of an si3200), the resolution of the pth12 and psum ram locations is modified from 498 w/lsb to 1059.6 w/ lsb. additionally, the thermal value must be modified to accommodate the si3200. for the si3200, thermal is typically 0.7 s assuming the exposed pad is connected to the recommended ground plane as stated in table 1 on page 4. thermal decreases if the pcb layout does not provide su fficient thermal conduction. see ?an58: SI3220/si3225 programmer?s guide? for details. example calculations for pth12 and plpf12 in si3200 mode are shown below: pth12 = si3200 power threshold = 1 w (0x3b0) plpf12 = si3200 thermal lpf pole = 2 (0x0010) automatic state change based on power alarm if either of the following situations occurs, the device automatically transitions to the open state: any of the transistor power alarm thresholds is exceeded in the case of the discrete transistor circuit. the total power threshold is exceeded when using the si3200. to provide optimal reliabilit y, the device automatically transitions into the open stat e until the user changes the state manually, independent of whether or not the power alarm interrupt has been masked. the pq1e?pq6e bits of the irqen3 register enable the interrupts for each transistor power alarm, and the pq1s to pq6s bits of the irqvec3 register are set when a power alarm is triggered in the respective transistor. when using the si3200, the pq1e bit enables the power alarm interrupt, and the pq1s bit is set when a si3200 power alarm is triggered.
SI3220/si3225 rev. 1.0 39 power dissipation considerations the dual proslic devices rely on the si3200 to power the line from the battery supply. the pcb layout and enclosure conditions should be designed to allow sufficient thermal dissipati on out of the si3200, and a programmable power alarm threshold ensures product safety under all operating conditions. see "power monitoring and power fault detection" on page 35 for more details on power alarm considerations. the si3200?s thermally-enhanced soic-16 package offers an exposed pad that improves thermal dissipation out of the package when soldered to a topside pcb pad connected to inner power planes. using appropriate layout practices, the si3200 can provide thermal performance of 55 c/w. the exposed path should be connected to a low-impedance ground plane via a topside pcb pad directly under the part. see package outlines for pcb pad dimensions. in addition, an opposite-side pcb pad with multiple vias connecting it to the topside pad directly under the exposed pad will further improve the overall thermal performance of the system. refer to ?an55: dual proslic user guide? for optimal thermal dissipation layout guidelines. the dual proslic chipset is designed with the ability to source long loop lengths in excess of 18 kft but can also accommodate short loop configurations. for example, the SI3220 can operate from one of two battery supplies depending on the operating state. when in the on-hook state, the on-hook loop feed is generated from the ringing battery supply, generally ?70 v or more. once the slic transitions to the off-hook state, a lower off- hook battery supply (typically ?24 v) supplies the required current to power the loop if the loop length is sufficiently short to accommodate the lower battery supply. this battery switch ing method allows the slic chipset to dissipate less power than when operating from a ?70 v battery supply. see ?automatic dual battery switching? for more details. in long loop applications, there is generally a single battery supply (e.g., ?48 v) available for powering the loop in the off-hook state. when sourcing loop lengths similar to the maximum specif ied service distance (e.g., 18 kft.), most of the power is dissipated in the impedance of the line. slics used in long-loop applications must also be able to provide phone service to customers who are locate d much closer to the line card than the maximum loop length specified for the system. this situation may cause substantial power to be dissipated inside the slic chipset, often resulting in thermal shutdown or destruction of the device due to thermal runaway. a special power offload circuit is recommended for single-battery extended-loop applications. refer to ?an91: si3200 power off-load circuit? for power offload circuit usage guidelines. table 21. register and ram locations used for power monitoring and power fault detection parameter register/ ram mnemonic register/ram bits measurement range resolution si3200 total power output monitor psum psum[15:0] 0 to 34.72 w 1059.6 w si3200 power alarm interrupt pending irqvec3 pq1s n/a n/a si3200 power alarm interrupt enable irqen3 pq1e n/a n/a q1/q2 power alarm threshold (discrete) q1/q2 power alarm threshold (si3200) pth12 pth12[15:0] 0 to 16.319 w 0 to 34.72 w 498 w 1059.6 w q3/q4 power alarm th reshold pth34 pth34[15:0] 0 to 1.03 w 31.4 w q5/q6 power alarm threshold pth56 pth56[15:0] 0 to 16.319 w 498 w q1/q2 thermal lpf pole plpf12 plpf12[ 15:3] see ?power filter and alarms? q3/q4 thermal lpf pole plpf34 plpf34[ 15:3] see ?power filter and alarms? q5/q6 thermal lpf pole plpf56 plpf56[ 15:3] see ?power filter and alarms? q1?q6 power alarm interrupt pending irqvec3 pq1s?pq6s n/a n/a q1?q6 power alarm interrupt enable irqen3 pq1e?pq6e n/a n/a
SI3220/si3225 40 rev. 1.0 automatic dual battery switching the dual proslic chipsets provide the ability to switch between several user-provided battery supplies to aid thermal management. two specific scenarios where this method may be required follow: ringing to off-hook state transition (SI3220): during the on-hook operating state, the dual proslic chipset must operate from the ringing battery supply to provide the desired ringing signal when required. once an off-hook condition is detected, the dual prosli c chipset must transition to the lower battery supply, typically ?24 v, to reduce power dissipation during the active state. the low current consumed by the dual proslic chipset during the on-hook state results in very little power dissipation while being powered from the ringing battery supply, which can have an amplitude as high as ?100 v depending on the desired ringing amplitude. on-hook to off-hook state, short loop feed (si3225): when sourcing both long and short loop lengths, the dual proslic chipset can automatically switch from the typical ?48 v off-hook battery supply to a lower off-hook battery supply (e.g ., ?24 v) to reduce the total off-hook power dissipation. the dual proslic chipset continuously monitors the tip- ring voltage and selects the lowest battery voltage required to power the loop when transitioning from the on-hook to the off-hook state, thus assuring the lowest power dissipation. the batsela and batselb pins switch between the two battery voltages based on the operating state and the tip-ring voltage. fi gure 19 illustrates the chip connections required to implement an automatic dual battery switching scheme. when batsel is pulled low, the desired channel is powered from the v blo supply. when batsel is pulled high, the v bhi source supplies power to the desired channel. the batsel pins for both channels are controlled using the batsel bit of the rlycon register and can be programmed to automatically switch to the lower battery supply (v blo ) when the off-hook tip-ring voltage is low enough to allow proper operation from the lower supply. when using the SI3220, this mode should always be enabled to allow seamless switching between the ringing and off-hook states. the same switching scheme is used with the si3225 to reduce power by switching to a lower off-hook battery when sourcing a short loop. two thresholds are provided to enable battery switching with hysteresis. the bathth ram location specifies the threshold at which the dual proslic device switches from the low battery (v blo ) to the high battery (v bhi ) due to an off-hook-to-on-hook transition. the batlth ram location specifies the threshold at which the SI3220/si3225 switches from v bhi to v blo due to a transition from the on-hook or ringing state to the off- hook state or because the overhead during active off- hook mode is sufficient to feed the subscriber loop using a lower battery voltage. the low-pass filter coefficient is calculated using the following equation and is entered into the batlpf ram location: batlpf = [(2 f x 4096)/800] x 2 3 where f = the desired cutoff frequency of the filter the programmable range of the filter is from 0h (blocks all signals) to 4000h (unfiltered). a typical value of 10 hz (0a10h) is sufficient to filter out any unwanted ac artifacts while allowing the dc information to pass through the filter. table 22 provides the register and ram locations used for programming the battery switching functions. table 22. register and ram locations used for battery switching parameter register/ram mnemonic register/ram bits programmable range resolution (lsb size) high battery detect threshold bathth bathth[14:7] 0 to 160.173 v* 628 mv (4.907 mv) low battery detect threshold batlth batlth[14:7] 0 to 160.173 v* 628 mv (4.907 mv) ringing battery switch (SI3220 only) rlycon gpo toggle n/a battery select indica tor rlycon bsel toggle n/a battery switching lpf batlpf batlpf[15:3] 0 to 4000h n/a *note: usable range for bathth and batlth is limited to the v bhi voltage.
SI3220/si3225 rev. 1.0 41 when generating a high-voltage ringing amplitude using the SI3220, the power dissipated during the oht state typically increases due to operating from the ringing battery supply in this mode. to reduce power, the SI3220/si3200 chipset provides the ability to accommodate up to three separate battery supplies by implementing a secondary battery switch using a few low-cost external componen ts as illustrated in figure 22. the SI3220?s batsel pin is used to switch between the v bhi (typically ?48 v) and v blo (typically ?24 v) rails using the switch internal to the si3200. the SI3220?s gpo pin is used along with the external transistor circuit to switch the v bring rail (the ringing voltage battery rail) onto the si3200?s v bat pin when ringing is enabled. the gpo signal is driven automatically by the ringing cadence provided that the rrail bit of the rlycon regist er is set to 1 (signifying that a third battery rail is present). figure 19. external battery switching using the SI3220/si3225 figure 20. 3-battery switching with SI3220/si3200 SI3220 si3225 battery sense circuit battery control logic si3200 linefeed circuitry battery select control v blo v bhi svbat batsel batsel 40.2 k ? 806 k ? vbath vbat vbatl svbat gpo batsel si3200 vbat vbath vbatl batsel v bring v blo 0.1 f 0.1 f 806 k ? d1 in4003 r103 cxt5551 q2 r102 q1 cxt5401 r101 10 k ? 402 k ? v bhi r9 40.2 k ? SI3220
SI3220/si3225 42 rev. 1.0 loop closure detection loop closure detection is required to accurately signal a terminal device going off-hook during the active, on- hook transmission (forward or reverse polarity), and ringing linefeed states. the functional blocks required to implement a loop closure detector are shown in figure 21, and the register set for detecting a loop closure event is provided in table 24. the primary input to the system is the loop current sense value from the voltage/current/power monitoring circuitry and is reported in the i loop ram address. the loop current (i loop ) is computed by the isp using the equations shown below. refer to figure 18 on page 36 for the discrete bipolar transistor references) used in the equation below (q1, q2, q5 and q6 ? note that the si3200 has corresponding mos transistors). the same i loop equation applies to the discrete bipolar linefeed as well as the si3200 linefeed device. the following equation is conditioned by the cmh status bit in register lcrrtp and by the linefeed state as indicated by the lfs field in the linefeed register. if the cmhith (ram 36) threshold is exceeded, the cmh bit is 1, and i q1 is forced to zero in the forward-active and tip-open states, or i q2 is forced to zero in the reverse-active and ring- open states. the other currents in the equation are allowed to contribute normally to the i loop value. the conditioning due to the cmh bit (lcrrtp register) and lfs field (linefeed register) states can be summarized as follows: iq1 = 0 if (cmh = 1 and (lfs = 1 or lfs = 3)) iq2 = 0 if (cmh = 1 and (lfs = 5 or lfs = 7)) the output of the isp is the input to a programmable digital low-pass filter, which removes unwanted ac signal components before threshold detection. the low-pass filter coefficient is calculated using the following equation and is entered into the lcrlpf ram location: lcrlpf = [(2 f x 4096)/800] x 2 3 where f = the desired cutoff frequency of the filter. the programmable range of the filter is from 0h (blocks all signals) to 4000h (unfiltered). a typical value of 10 (0a10h) is sufficient to filter out any unwanted ac artifacts while allowing the dc information to pass through the filter. the output of the low-pass filter is compared to a programmable threshold, lcroffhk. hysteresis is enabled by programming a second threshold, lcronhk, to detect the loop going to an open or on- hook state. the threshold comparator output feeds a programmable debounce filter. the output of the debounce filter remains in its present state unless the input remains in the opposite state for the entire period of time programmed by the loop closure debounce interval, lcrdbi. there is also a loop closure mask interval, lcrmask, that is used to mask transients caused when an internal ringing burst (with no offset) ends in the presence of a high ren load. if the debounce interval has been satisfied, the lcr bit is set to indicate that a valid loop closure has occurred. figure 21. loop closure detection circuitry table 23. three-battery switching components component value comments d1 200 v, 200 ma 1n4003 or similar q1 100 v pnp cxt5401 or similar q2 100 v npn cxt5551 or similar r101 1/10 w, 5% 2.4 k ? for v dd =3.3 v 3.9 k ? for v dd =5 v r102 10 k ? ,1/10 w, 5% r103 402 k ? ,1/10 w, 1% i loop i q1 i q6 ? i q5 i q2 in tip-open or ring-open i q1 i q6 ? i q5 i q2 ? + 2 --------------------------------------------------- - in all other states = ? + = i q1 lfs lcrlpf lcroffhk input signal processor digital lpf loop closure threshold debounce filter + ? lcr lcronhk loops loope interrupt logic lcrdbi loop closure mask lcrmask i q2 i q5 i q6 cmh i loop
SI3220/si3225 rev. 1.0 43 ground key detection ground key detection detects an alerting signal from the terminal equipment during the tip open or ring open linefeed states. the functional blocks required to implement a ground key detector are shown in figure 22 on page 45, and the register set for detecting a ground key event is provided in table 27 on page 45. the primary input to the system is the longitudinal current sense value provided by the voltage/current/ power monitoring circuitry and reported in the ilong ram address. the i long value is produced in the isp provided the lfs bits in the linefeed register indicate the device is in the tip open or ring open state. the longitudinal current (i long ) is computed as shown in the following equation. refer to figure 18 on page 36 for the transistor references used in the equation (q1, q2, q5 and q6 ? note that the si3200 has corresponding mos transistors). the same i long equation applies to the discrete bipolar linefeed as well as the si3200 linefeed device. the output of the isp (i long ) is the input to a programmable, digital low-pass filter, which removes unwanted ac signal components before threshold detection. the low-pass filter coefficient is calculated using the following equation and is entered into the longlpf ram location: where f = the desired cutoff frequency of the filter. the programmable range of the filter is from 0h (blocks all signals) to 4000h (unfiltered). a typical value of 10 (0a10h) is sufficient to filter out any unwanted ac artifacts while allowing the dc information to pass through the filter. table 24. register and ram locations used for loop closure detection parameter register/ram mnemonic register/ram bits programmable range lsb size effective resolution loop closure interrupt pending irqvec2 loops yes/no n/a n/a loop closure interrupt enable irqen2 loope yes/no n/a n/a linefeed shadow linefeed lfs[2:0] monitor only n/a n/a loop closure detect status lcrrtp lcr monitor only n/a n/a loop closure detect debounce interval lcrdbi lcrdbi[15:0] 0 to 40.96 s 1.25 ms 1.25 ms loop current sense iloop iloop[15:0] 50.54 to 101.09 ma 3.097 a500 a 1 loop closure threshold (on-hook to off-hook) lcroffhk lcroffhk[15:0] 0 to 101.09 ma 2 3.097 a396.4 a loop closure threshold (off-hook to on-hook) lcronhk lcronhk[15:0] 0 to 101.09 ma 2 3.097 a396.4 a loop closure filter coefficient lcrlpf lcrlpf[15:3] 0 to 4000h n/a n/a loop closure mask interval lcrmask lcrmask[15:0] 0 to 40.96s 1.25 ms 1.25 ms notes: 1. the effective i loop resolution is approximately 500 a. 2. the usable range for lcronhk and lcroffhk is limited to 61 ma. entering a value > 61 ma will disable threshold detection. i long i q1 i q6 ? i q5 ? i q2 + 2 --------------------------------------------------- - = longlpf 2 f 4096 () 800 --------------------------------- 2 3 =
SI3220/si3225 44 rev. 1.0 the output of the low-pass filter is compared to the programmable threshold, longhith. hysteresis is enabled by programming a second threshold, longloth, to detect when the ground key is released. the threshold comparator output feeds a programmable debounce filter. the output of the debounce filter remains in its present state unless the input remains in the opposite state for the entire period of time programmed by the loop closure debounce interval, longdbi. if the debounce inte rval is satisfied, the longhi bit is set to indicate that a valid ground key event has occurred. when the SI3220/25 detects a ground key event, the linefeed automatically transitions from the tip-open (or ring-open) state to the forward-active (or reverse-active) state. ho wever, this automatic state transition is triggered by the lcr bit becoming active (i.e., =1), and not by the longhi bit. while i long is used to generate the longhi status bit, a transition from tip-open to the fo rward-active state (or from the ri ng-open to the reverse- active state) occurs when the ring terminal (or tip terminal) is grounded and is based on the lcr bit and implicitly on exceeding the lcroffhk threshold. as an example of ground ke y detection, suppose that the SI3220/25 has been programmed with the current values shown in table 25. with the settings of table 25, the behavior of i loop , i long , lcr, longhi, and cmhigh is as shown in table 26. the entries under ?loop state? indicate the condition of the loop, as determined by the equipment terminating the loop. the entries under ?linefeed setting? indicate the state initially selected by the host cpu (e.g., tip-open) and the automatic transition to the forward-active state due to a ground key event (when ring is connected to gnd). the transition from state #2 to state #3 in table 26 is the automatic transition from tip-open to fwd-active in response to lcr = 1. table 25. settings for ground key example ilim 21 ma lcroffhk 14 ma lcronhk 10 ma longhith 7 ma longloth 5 ma table 26. state transitions during ground key detection # loop state linefeed state i loop (ma) i long (ma) lcr longhi cmhigh 1loop open lfs = 3 (tip-open) 0000 0 2 ring-gnd lfs = 3 (tip-open) 22 ?11 1 1 0 3 ring-gnd lfs = 1 (fwd-active) 22 ?11 1 1 1 4loop clo- sure lfs = 1 (fwd-active) 21 0 1 0 0 5loop open lfs = 1 (fwd-active) 0000 0
SI3220/si3225 rev. 1.0 45 figure 22. ground key detection circuitry table 27. register and ram locations used for ground key detection parameter register/ ram mnemonics register/ram bits programmable range lsb size resolution ground key interrupt pending irqvec2 longs yes/no n/a n/a ground key interrupt enable irqen2 longe yes/no n/a n/a ground key linefeed shadow linefeed lfs[2:0] monitor only n/a n/a ground key detect status lcrrtp longhi monitor only n/a n/a ground key detect debounce interval longdbi longdbi[15:0] 0 to 40.96 s 1.25 ms 1.25 ms longitudinal current sense ilong il ong[15:0] monitor only see table 20 ground key threshold (enabled) longhith long- hith[15:0] 0 to 101.09 ma* 3.097 a 396.4 a ground key threshold (released) longloth lon- gloth[15:0] 0 to 101.09 ma* 3.097 a 396.4 a ground key filter coeffi- cient longlpf longlpf[15:3] 0 to 4000h n/a n/a *note: the usable range for longhith and longloth is lim ited to 16 ma. setting a value > 16 ma will disable threshold detection. i q1 lfs longlpf longhith input signal processor digital lpf ground key threshold debounce filter + ? longhi longloth longs longe interrupt logic longdbi i q2 i q5 i q6 i long
SI3220/si3225 46 rev. 1.0 ringing generation the SI3220-based dual proslic chipset provides a balanced ringing waveform with or without dc offset. the ringing frequency, cadence, waveshape, and dc offset are register-programmable. using a balanced ringing scheme, the ringing signal is applied to both the tip and the ring lines using ringing waveforms that are 180 out of phase with each other. the resulting ringing signal seen across tip-ring is twice the amplitude of the ringing waveform on either the tip or the ring line, which allows the ringing circuitry to withstand half the total ringing amplitude seen across tip-ring. figure 23. balanced ringing an internal ringing scheme provides >40 vrms into a 5 ren load at the terminal equipment using a user- provided ringing battery supply. the specific ringing supply voltage required depends on the desired ringing voltage. the ringing amplitude at the terminal equipment also depends on the loop impedance and the load impedance in ren. the simplified circuit in figure 24 shows the relationship between loop impedance and load impedance. figure 24. simplified loop circuit during ringing the following equation can be used to determine the tip-ring ringing amplitude re quired for a specific load and loop condition: where and when ringing longer loop lengths, adding a dc offset voltage is necessary to reliably detect a ring trip condition (off-hook phone). adding dc offset to the ringing signal decreases the maximum possible ringing amplitude. adding significant dc offset also increases the power dissipation in the si3200 and may require additional airflow or modified pcb layout to maintain acceptable operating temperatures in the line feed circuitry. the dual proslic chipset automatically applies and removes the ringing signal during v oc - crossing periods to reduce noise and crosstalk to adjacent lines. table 28 provides a list of registers required for internal ringing generation ring tip v ring v tip slic v off gnd v tip v ring v bath v pk v ov v cm v off r loop v ring r load v term + ? r out v term v ring r load r load r loop r out ++ () --------------------------------------------------------------------- = r loop 0.09 ? per foot for 26awg wire () = r out 320 ? = r load 7000 ? #ren ------------------- - =
SI3220/si3225 rev. 1.0 47 table 28. register and ram locations used for ringing generation parameter register/ram mnemonic register/ram bits programmable range resolution (lsb size) ringing waveform ringcon t rap sinusoid/trapezoid n/a ringing active timer enable ringcon taen enabled/disabled n/a ringing inactive timer enable ringcon tien enabled/disabled n/a ringing oscillator enable monitor ringcon ringen enabled/disabled n/a ringing oscillator active timer ringtalo/ ringtahi ringta[15:0] 0 to 8.19 s 125 s ringing oscillator inactive timer ringtilo/ ringtihi ringti[15:0] 0 to 8.19 s 125 s linefeed control (initiates ringing state) linefeed lf[2:0] 000 to 111 n/a on-hook line voltage voc voc[15:0] 0 to 63.3 v 1.005 v (4.907 mv) ringing voltage offset ringof ringof[15:0] 0 to 63.3 v 1.005 v (4.907 mv) ringing frequency ringfrhi/ ringfrlo ringfrhi[14:3]/ ringfrlo[14:3] 4 to 100 hz ringing amplitude ringamp ringamp[15:0] 0 to 160.173 v 628 mv (4.907 mv) external ringing generator voltage sense vrngng vrngng[15:0] 332.04 v 1.302 v (10.172 mv) external ringing generator current sense irngng irngng[15:0] 662.83 ma 2.6 ma (20.3 a) ringing initial phase sinusoidal trapezoid external ringing ringphas ring phas[15:0] n/a 0 to 1.024 s 0 to 662.83 ma n/a 31.25 s 2.6 ma (20.3 a) ringing relay driver enable (si3225 only) relaycon rdoe enabled/disabled n/a ringing overhead voltage vovring vovrin g[15:0] 0 to 63.3 v 1.005 v (4.907 mv) ringing speedup timer speedupr speedupr[15:0] 0 to 40.96 s 1.25 ms
SI3220/si3225 48 rev. 1.0 internal sinusoidal ringing a sinusoidal ringing waveform is generated by the on- chip digital tone generator. the tone generator used to generate ringing tones is a two-pole resonator with a programmable frequency and amplitude. since ringing frequencies are low compared to the audio band signaling frequencies, the sinusoid is generated at a 1 khz rate. the ringing generator is programmed via the ringfreq, ringamp, and ringphas registers. the equations are as follows: for example, to generate a 60 v rms (87 v pk ), 20 hz ringing signal, the equations are as follows: in addition to the variable frequency and amplitude, a selectable dc offset (v off ), which can be added to the waveform, is included. the dc offset is defined in the ringof ram location. as with the tone generators, the ringing generator has two timers which function as described above. they allow on/off cadence settings up to 8 s on/8 s off. in addition to controlling ringing cadence, these timers control the transition into and out of the ringing state. to initiate ringing, th e user must program the ringfreq, ringamp, and ringphas ram addresses as well as the ringta and ringti registers and select the ringing waveshape and dc offset. after this is done, taen and tien bits are set as desired. the ringing state is invoked by a write to the linefeed register. at the expiration of ringta, the dual proslic turns off the ringing waveform and goes to the on-hook transmission state. at the ex piration of ringti, ringing is initiated again. this proc ess continues as long as the two timers are enabled and the linefeed register remains in the ringing state. internal trapezoidal ringing in addition to the traditional sinusoidal ringing waveform, the dual proslic can generate a trapezoidal ringing waveform similar to the one illustrated in figure 26 on page 49. the ringfreq, ringamp, and ringphas ram addresses are used for programming the ringing wave shape as follows: ringphas = 4 x period x 8000 ringamp = (desired v/160.8 v) x (2 15 ) ringfreq = (2 x ringamp)/(t rise x 8000) ringfreq is a value that is added or subtracted from the waveform to ramp the signal up or down in a linear fashion. this value is a func tion of rise time, period, and amplitude, where rise time and period are related through the following equation for the crest factor of a trapezoidal waveform. where so, for a 90 v pk , 20 hz trapezoidal waveform with a crest factor of 1.3, the period is 0.05 s, and the rise time requirement is 0.015 s. ringphas = 4 x 0.05 x 8000 = 1600 (0x0640) ringamp = 90/160.8 x (2 15 ) = 18340 (0x47a5) ringfreq = (2 x ringamp)/(0.0153 x 8000) = 300 (0x012c) the time registers and interrupts described in the sinusoidal ring description al so apply to the trapezoidal ring waveform: internal unbalanced ringing the SI3220 also provides the ability to generate a traditional battery-backed unbalanced ringing waveform for ringing terminating devices that require a high dc content or for use in ground-start systems that cannot tolerate a ringing waveform on both the tip and ring leads. the unbalanced ringing scheme applies the ringing signal to the ring lead; the tip lead remains at the programmed vcm voltag e that is very close to ground. a programmable dc offset can be preset to provide dc current for ri ng trip detection. figure 25 illustrates the internal un balanced ringing waveform. coeff 2 f 1000hz -------------------- - ?? ?? ringfreq = coeff 2 23 cos = ringamp 1 4 -- - 1 coeff ? 1coeff + ----------------------- - 2 15 () desiredv pk 160.173v --------------------------------- = ringphas 0 = coeff 2 20 1000hz -------------------- - ?? ?? 0.9921 = cos = ringfreq 0.9921 2 23 () 8322461 0x7efd9d === ringamp 1 4 -- - 00789 1.99211 --------------------- 2 15 () 85 160.173 --------------------- 273 0x111 = = = t rise 3 4 -- - t1 1 cf 2 ---------- - ? ?? ?? = tperiod 1 f ring -------------- cf desired crest factor = ==
SI3220/si3225 rev. 1.0 49 figure 25. internal unbalanced ringing to enable unbalanced ringing, set the ringunb bit of the ringcon register. as with internal balanced ringing, the unbalanced ringing waveform is generated by using one of the two on-chip tone generators provided in the SI3220. the tone generator used to generate ringing tones is a two-pole resonator with programmable frequency and amplitude. since ringing frequencies are low compared to the audio band signaling frequencies, the ringing waveform is generated at a 1 khz rate. the ringing generator is programmed via the ringamp, ringfreq, and ringphas registers. the ringof register is used in to set the dc offset position around which the ring lead will oscillate. the dc offset is set at a dc point equal to vcm ? (?80 v + voff), where voff is the value that is input into the ringof ram location. positive voff valu es will cause the dc offset point to move closer to ground (lower dc offset), and negative voff values will ha ve the opposite effect. the dc offset can be set to any value; however, the ringing signal will be clipped digitally if the dc offset is set to a value that is less than half the ringing amplitude. in general, the following equation must hold true to ensure the battery voltage is sufficient to provide the desired ringing amplitude: |v batr | > |v ring,pk + (?80 v + v off ) + v ovring | it is possible to create reverse polarity unbalanced ringing waveforms (the tip lead oscillates while the ring lead stays constant) by setting the unbpolr bit of the ringcon register. in this mode, the polarity of voff must also be reversed (in normal ringing polarity voff is subtracted from ?80 v, and in reverse polarity, ringing voff is added to ?80 v). ringing coefficients the ringing coefficients are calculated in decimals for sinusoidal and trapezoidal waveforms. the ringphas and ringamp hex values are decimal to hex conversions in 16-bit 2?s complement representations for their respective ram locations. to obtain sinusoidal ringfreq ram values, the ringfreq decimal number is converted to a 24-bit 2?s complement value. the lower 12 bits are placed in ringfrlo bits 14:3. ringfrlo bits 15 and 2:0 are cleared to 0. the upper 12 bits are set in a similar manner in ringfrhi, bits 13 :3. ringfrhi bit 14 is the sign bit, and ringfrhi bits 2:0 are cleared to 0. for example, the register values for ringfreq = 0x7efd9d are as follows: ringfrhi = 0x3f78 ringfrlo = 0x6ce8 to obtain trapezoidal ringfreq ram values, the ringfreq decimal number is converted to an 8-bit, 2?s complement value. this valu e is loaded into ringfrhi. ringfrlo is not used. figure 26. trapezoidal ringing waveform ringing dc offset voltage a dc offset voltage can be added to the SI3220?s ac ringing waveform by programming the ringof ram location to the appropriate setting. the value of ringof is calculated as follows: ring tip v ring SI3220 dc offset gnd v tip v ring v batr -80v v ovring v cm dc offset v off v tip-ring v off t rise t = 1/freq time ringof v off 160.8 -------------- - 2 15 =
SI3220/si3225 50 rev. 1.0 external unbalanced ringing the si3225 supports centralized, battery-backed unbalanced ringing schemes by providing a ringing relay driver as well as inputs from an external ring trip circuit. using this scheme, line-card designers can use the dual proslic chipset in existing system architectures with minimal system changes. linefeed overhead voltage considerations during ringing the ringing mode output impedance allows ringing operation without overhead voltage modification (vovr = 0). if an offset of the ringing signal from the ring lead is desired, vovr can be used for this purpose. ringing power considerations the total power consumpti on of the SI3220/si3200 chipset using internal ringing generation is dependent on the vdd supply voltage, the desired ringing amplitude, the total loop impedance, and the ac load impedance (number of ren). the following equations can be used to approximate the total current required for each channel during ringing mode: where: r load = 7000/ren (for north america) r loop = loop impedance r out = proslic output impedance = 320 ? i dd,oh =i dd overhead current =22ma for v dd =3.3v =26ma for v dd =5v ring trip detection a ring trip event signals that the terminal equipment has transitioned to an off-hook state after ringing has commenced, ensuring that the ringing signal is removed before normal speech begins. the dual proslic is designed to implement either an ac or dc-based internal ring trip detection scheme or a combination of both schemes. the system design is flexible to address varying loop lengths of different applications. an ac ring trip detection scheme cannot reliably detect an off-hook condition when sourcing longer loop lengths, as the 20 hz ac impedance of an off-hook long loop is indistinguishable from a heavily-loaded (5 ren) short loop in the on-hook state. therefore, a dc ring trip detection scheme is required when sourcing longer loop lengths. the SI3220 can implement eith er an ac or dc-based ring trip detection scheme depending on the application. the si3225 allows external dc ring trip detection when using a battery-backed external ringing generator by monitoring the ringing feed path through two sensing inputs on each channel. by monitoring this path, the dual proslic detects a dc current flowing in the loop once the end equipment has gone off-hook. table 29 provides recommended register and ram settings for various applications, and table 30 lists the register and ram addresses that must be written or monitored to correctly detect a ring trip condition. figure 27 illustrates the intern al functional blocks that correctly detect and process a ring trip event. the primary input to the system is the loop current sense (iloop) value provided by the loop monitoring circuitry and reported in the iloop ram location register. the iloop ram location value is processed by the isp block when the lfs bits in the linefeed register indicate the device is in the ringing state. the output of the isp then feeds into a pair of programmable, digital, low-pass filters: one for the ac ring trip detection path and one for the dc path. the ac path also includes a full-wave rectifier block prior to the lpf block. the outputs of each low-pass filter block are then passed on to a programmable ring trip threshold (rtacth for ac detection and rtdcth for dc detection). each threshold block output is then fed to a programmable debounce filter to ensure a valid ring trip event. the output of each debounce filter remains constant unless the input remains in the opposite state for the entire period of time set using the ac and dc ring trip debounce interval registers, rtacdb and rtdcdb, respectively. the outputs of both debounce filter blocks are then ored together. if either the ac or the dc ring trip circuits indicate a valid ring trip event has occurred, the rtp bit is set. either the ac or dc ri ng trip detection circuits are disabled by setting the respective ring trip threshold sufficiently high so that it does not trip under any condition. a ring trip interrupt is also generated if the rtripe bit is enabled. i dd,ave v ring,pk z loop ---------------------- - 2 -- - i dd,oh + = i bat,ave v ring,pk z loop ---------------------- - 2 -- - = v ring,pk v ring,rms 2 = z loop r loop r load r out ++ =
SI3220/si3225 rev. 1.0 51 ringtrip timeout counter the dual proslic incorporates a ringtrip timeout counter, rtcount, that will monitor the st atus of the ringing control. when exiting ringing, the dual proslic will allow the ringtrip timeou t counter a sufficient amount of time (rtcount x 1.25 ms/lsb) for the mode to switch to on-hook transmission or active. the mode that is being exited to is governed by whether the command to exit ringing is a ringing active timer expiration (on-hook transmission) or ringtrip/manual mode change (active mode). the ringtrip timeout counter ensures ringing is exited within its time setting (rtcount x 1.25 ms/lsb, typically 200 ms). ringtrip debounce interval the ac and dc ring trip debounce intervals can be calculated based on the following equations: rtacdb = t debounce (1600/rtper) rtdcdb = t debounce (1600/rtper) figure 27. ring trip detect processing circuitry input signal processor digital lpf + _ ac ring trip threshold rtper lfs iloop rtacth debounce filter_ac interrupt logic rtrips rtp rtripe + _ dc ring trip threshold rtdcth debounce filter_dc rtacdb rtdcdb digital lpf full wave rectifier
SI3220/si3225 52 rev. 1.0 loop closure mask the dual proslic implements a loop closure mask to ensure mode change between ringing and active or on- hook transmission without causing an erroneous loop closure detection. the loop closure mask register, lcrmask, should be set su ch that loop closure detection is ignored for the time (lcrmask 1.25 ms/ lsb). the programmed time is set to mask detection of transitional currents that occur when exiting the ringing mode while driving a reactive load (i.e., 5 ren). a typical setting is 80 ms (lcrmask = 0x40). SI3220 ring trip detection the SI3220 provides the ability to process a ring trip event using an ac-based det ection scheme. using this scheme eliminates the need to add dc offset to the ringing signal, which reduces the total power dissipation during the ringing state and maximizes the available ringing amplitude. this scheme is valid for shorter loop lengths only since it cannot reliably detect a ring trip event if the off-hook line impedance overlaps the on- hook impedance at 20 hz. table 29. recommended values for ring trip registers and ram addresses 1 ringing method ringing frequency dc offset added? rtper rtacth rtdcth rtacdb/ rtdcdb internal (SI3220) 16?32 hz yes 800/f ring 221 x rtper 0.577(rtper x v off ) see note 2 no 800/f ring 1.59 x v ring,pk x rtper 32767 33?60 hz yes 2(800/ f ring ) 221 x rtper 0.577(rtper x v off ) no 2(800/ f ring ) 1.59 x v ring,pk x rtper 32767 external (si3225) 16?32 hz yes 800/f ring 32767 0.067 x rtper x v off 33?60 hz yes 2(800/ f ring ) 32767 0.067 x rtper x v off notes: 1. all calculated values should be rounded to the nearest integer. 2. refer to ring trip debounce interval for rtacdb and rtdcdb equations. table 30. register and ram locations used for ring trip detection parameter register/ram mnemonic register/ram bits programmable range resolution ring trip interrupt pending irqvec2 rtrips yes/no n/a ring trip interrupt enable irqen2 rtripe enabled/disabled n/a ac ring trip threshold rtacth rtacth[15:0] see table 29 dc ring trip threshold rtdcta rtdcth[15:0] see table 29 ring trip sample period rtper rtper[15:0] see table 29 linefeed shadow (monitor only) linefeed lfs[2:0] n/a n/a ring trip detect status (monitor only) lcrrtp rtp n/a n/a ac ring trip detect debounce interval rtacdb rtacdb[15:0] 0 to 40.96 s 1.25 ms dc ring trip detect debounce interval rtdcdb rtdcdb[15:0] 0 to 40.96 s 1.25 ms loop current sense (monitor only) iloop iloop[15:0] 0 to 101.09 ma see table 20
SI3220/si3225 rev. 1.0 53 the SI3220 also can add a dc offset component to the ringing signal and detect a ring trip event by monitoring the dc loop current flowing once the terminal equipment transitions to the off-hook state. although adding dc offset reduces the maximum available ringing amplitude (using the same ringing supply), this method is required to reliably detect a valid ring trip event when sourcing longer loop lengths. the dc offset can be programmed from 0 to 64.32 v in the ringof ram address as required to produce adequate dc loop current in the off- hook state. depending on the loop length and the ring trip method, the ac or dc ring trip detection circuits are disabled by setting their respective ring trip thresholds, rtacth or rtdcth, sufficiently high so that they do not trip under any condition. si3225 ring trip detection the si3225 implements an external ring trip detection scheme when using a standard battery-backed external ringing generator. in this application, the centralized ringing generator produces an unbalanced ringing signal that is distributed to individual tip/ring pairs. a per-channel ringing relay is required to disconnect the si3225 from the tip/ring pair and apply the ringing signal. by monitoring the ringing feed path across a ring feed sense resistor (r ring in figure 31 on page 56) in series with the ringing source, the si3225 can detect the dc current path created when the hook switch inside the terminal equipment closes. the internal ring trip detection circuitry is iden tical to that illustrated in figure 27. figure 31 illustrates the typical external ring trip circuitry required for the si3225. because of the long loop nature of these applications, a dc ring trip detection scheme is typically used. the user can disable the ac ring trip detection circuitry by setting the rtacth threshold sufficiently high so it does not trip under any condition. relay driver considerations the dual proslic devices include up to three dedicated relay drivers to drive external ringing and/or test relays. test relay dr ivers trd1a, trd1b, trd2a, and trd2b are provided in all product versions, and ringing relay drivers rrda and rrdb are included for the si3225 only. in most applications, the relay can be driven directly from the dual proslic with no external relay drive circuitry required. figure 28 illustrates the internal relay driver circuitry using a 3 v or 5 v relay. figure 28. dual proslic internal relay drive circuitry the internal driver logic and drive circuitry are powered by the same v dd supply as the chip?s main v dd supply (vdd1?vdd4 pins). when operating external relays from a v cc supply equal to the chip?s v dd supply, an internal diode network provides protection against overvoltage conditions from flyback spikes when the relay is opened. either 3 v or 5 v relays can be used in the configuration shown in figure 28, and either polarized or non-polarized relays are acceptable if the v cc and v dd supplies are identical. the input impedance, r in , of the relay driver pins is a constant 11 ? while sinking less than the maximum rated 85 ma into the pin. if the operating voltage of the relay (v cc ) is higher than the dual proslic v dd supply voltage, an external drive circuit is required to eliminate leakage from v cc to v dd through the internal protection diode. in this configuration, a polarized relay will provide optimal overvoltage protection and minimal external components. figure 29 illustra tes the required external drive circuit, and table 31 provides recommended values for r drv for typical relay characteristics and v cc supplies. the output impedance, r out , of the relay driver pins is a constant 63 ? while sourcing less than the maximum rated 28 ma out of the pin. SI3220/ si3225 relay driver logic v dd gdd rrda/b trd1a/b trd2a/b v cc 3 v/5 v relay (polarized or non-polarized)
SI3220/si3225 54 rev. 1.0 figure 29. driving relays with v cc > v dd the maximum allowable r drv value can be calculated with the following equation: where q1,min ~ 30 for a 2n2222. table 31. recommended r drv values proslic v dd relay v cc relay r coil maximum r drv recommended 5% value 3.3 v 5% 3.3 v 5% 64 ? not required ? 5 v 5% 5 v 5% 178 ? not required ? 3.3 v 5% 5 v 5% 178 ? 2718 ? 2.7 k ? 3.3v 5% 12v 10% 1028 ? 6037 ? 5.6 k ? 3.3v 5% 24v 10% 2880 ? 8364 ? 8.2 k ? 3.3v 5% 48v 10% 7680 ? 11092 ? 11 k ? 5v 5% 12v 10% 1028 ? 9910 ? 9.1 k ? 5v 5% 24v 10% 2880 ? 13727 ? 13 k ? 5v 5% 48v 10% 7680 ? 18202 ? 18 k ? SI3220/ si3225 v dd rrda/b trd1a/b trd2a/b v cc polarized relay r drv i drv q1 maxr drv v dd,min 0.6 v ? () r relay () q1,min () v cc,max 0.3 v ? ------------------------------------------------------------------------------------------------ - r source ? =
SI3220/si3225 rev. 1.0 55 6 11 10 9 8 7 0 5 4 3 2 1 6 11 10 9 8 7 0 5 4 3 2 1 6 11 10 9 8 7 0 5 4 3 2 1 6 0 5 4 3 2 1 0 5 4 3 2 1 0 5 4 3 2 1 6 11 10 9 8 7 0 5 4 3 2 1 6 11 10 9 8 7 0 6 11 10 9 8 7 iringxscal counter0 counter1 ringen rrd on off on off lf ringing active ringing oht ringing active lfsdelay lfsdelay lfs zerdelay d figure 30. timing characteristics for ringing relay control
SI3220/si3225 56 rev. 1.0 figure 31. si3225 external ring trip circuitry ringing relay activation during zero crossings the si3225 is for applications that use a centralized ringing generator and a per-channel ringing relay to connect the ringing signal to the tip/ring pair. the si3225 has one relay driver output per channel (rrda and rrdb) that can drive a mechanical or solid-state dpdt relay. to reduce impulse noise that can couple into adjacent lines, the relay should be closed when there is zero voltage across the relay contacts and opened during periods when there is zero current through the contacts. closing the relay at zero voltage internal voltage monitoring circuitry closes the relay at zero voltage with respect to the line voltage. by observing the phase of the ringing signal and constantly monitoring the open-circuit t-r voltage, v oc , the si3225 can detect the next time when there is zero voltage across the relay contacts. opening the relay at zero current opening the ringing relay at zero current also is accomplished using the internal monitoring circuitry and prevents arcing from excess current flow when the relay contacts are opened. the current flowing through the ringing relay is continuously monitored in the irngng ram address, and two internal counters (counter0 and counter1) detect time elapsed since the last two zero current crossings based on the ringing period and predict when the next zero crossing occurs. the ringing relay current and internal counters are both updated at an 8 khz rate. to account for the mechanical delay of the relay, a programmable advance firing timer allows the user to initiate relay opening up to 10 ms prior to the zero current crossing even t. figure 30 illustrates the timing sequence for a typical ringing relay control application. during a typical ringing sequence, the si3225 monitors both the ringing relay current (irngng) and the ringen bit of the ringcon register. the ringen bit toggles because of pre-programmed ringing cadence or a change in operating state. counter0 and counter1 are restarted at each alternating zero current crossing event, and the delay period, zerdelay, equal to the ringing frequency period less the desired advance firing ti me, d, is entered by the user. if either counter reaches the same value as zerdelay, the relay control signal is enabled when the ringen bit transition ha s already occurred. during typical ringing bursts, the lfs bits of the linefeed register toggle between the ringing and oht states based on the pre-programmed ringing cadence. the transition from oht to ringing is synchronized with the rrd state transitions, so the ringing burst starts immediately. the transition from ringing to oht is gated by a user-programmed delay period, lfsdelay, which ensures the ringing burst has ceased before going to the oht state or to the active state in response to a linefeed state change. polarity reversal the dual proslic devices suppo rt polarity reversal for message-waiting functionality and various signaling modes. the ramp rate can be programmed for a smooth transition or an abrupt transition to accommodate different application requirements. a wink function is provided for special equipment that responds to a smooth ramp to v oc = 0 v. table 32 illustrates the register bits required to program the polarity reversal modes. v ring v off 806 k ? 806 k ? 510 ? + _ si3200 ring tip protection si3225 blkring rtrp relay hook switch phone vdd rrd
SI3220/si3225 rev. 1.0 57 setting the linefeed register to the opposite polarity immediately reverses (hard reversal) the line polarity. for example, to transition from forward active mode to reverse active mode changes lf[2:0] from 001 to 101. polarity reversal is accommodated in the oht and ground start modes. the polrev bit is a read-only bit that reflects if the device is in polarity reversal mode. for smooth polarity reversal, set the pren bit to 1 and the ramp bit to 0 or 1 depending on the desired ramp rate (see table 32). polarity reversal is then accomplished by toggling the linefeed register from forward to reverse modes as desired. a wink function slowly ramps down the tip-ring voltage (v oc ) to 1 followed by a re turn to the original voc value (set in the voc ram location). this scheme lights a message-waiting lamp in certain handsets. no change to the linefeed register is necessary to enable this function. instead, the user sets the voczero bit to 1 so that the tip-ring voltage collapses to 0 v at the rate programmed by the ramp bit. setting the voczero bit back to 0 returns the tip-ring voltage to its normal setting. with a software timer, the user can automate the cadence of th e wink function. figure 32 illustrates the wink function. figure 32. wink function with programmable ramp rate table 32. register and ram locations used for polarity reversal parameter programmable range register/ram bits register/ram mnemonic linefeed see table 17 lf[2:0] linefeed polarity reversal status read only polrev polrev wink function (smooth transition to voc=0v) 1 = ramp to 0 v 0 = return to previous v oc voczero polrev smooth polarity reversal enable 0 = disabled 1 = enabled pren polrev smooth polarity reversal ramp rate 0 = 1 v/1.25 ms 1 = 2 v/1.25 ms ramp polrev v tip/ring (v) 0 -10 -20 -30 -40 -50 time (ms) 50 40 30 20 10 60 70 80 0 2v/1.25ms slope set by ramp bit set voczero bit to 1 set voczero bit to 0 v cm v ov v oc v tip v bat v ring
SI3220/si3225 58 rev. 1.0 two-wire impedance synthesis two-wire impedance synthesis is performed on-chip to optimally match the output impedance of the dual proslic to the impedance of the subscriber loop to minimize the receive path signal reflected back onto the transmit path. the dual proslic chipset provides on- chip digitally-programmable, two-wire impedance synthesis to meet return loss requirements against virtually any global two-wire impedance requirement. refer to ?an196: dual proslic digital impedance synthesis? for important considerations about impedance synthesis initializat ion and control. real and complex two-wire impedances are realized by a programmable digital filter block. (see z a and z d blocks in figure 11 on page 24.) figure 33. two-wire impedance synthesis configuration the two-wire impedance is programmed by loading the desired real or complex impedance value into the si322x coefficient generator software in the format r s + r p ||c p , as shown in figure 33. the software calculates the appropriate hex coefficients and loads them into the appropriate control registers (registers 33?52). the two-wire impedance can be set to any real or complex value within the boundaries set in table 33. the actual impedance presented to the subscriber loop varies with series impedance from protection devices placed between the dual proslic chipset outputs and the tip/ring pair according to the following equation: where: z t is the termination impedance presented to the tip/ring pair r prot is the series resistance caused by protection devices r s is the series portion of the synthesized impedance r p ||c p is the parallel portio n of the synthesized impedance the user must enter the value of r prot into the software so the equalizer block can compensate for additional series impedance. (see figure 11 on page 24.) figure 34 illustrates the simplified two-wire impedance circuit including external protection resistors, where z l is the actual line impedance for the specific geographical region . the dual proslic devices can accomodate up to 50 ? of series protection impedance per leg. the ac impedance generation scheme is comprised of analog and dsp-based coefficients. to turn off the analog coefficients (rs, zp, and zz bits in the zrs and zz registers), the user can simply set the zsdis bit of the zz register to 0. to turn off the dsp coefficients (za1h1 through zb3lo registers), each register must be loaded with 0x00. figure 34. two-wire impedance simplified circuit transhybrid balance filter the dual proslic devices provide a transhybrid balance function via a digitally-programmable balance filter block. (see ?h? block in figure 11.) the dual proslic devices implement an 8-tap fir filter and a second-order iir filter, both running at a 16 khz sample rate. these two filters combine to form a digital replica of the reflected signal (echo) from the transmit path inputs. the user can filter settings on a per-line basis by loading the desired impedance cancellation coefficients into the appropriate regist ers. the si322xcoefficient generator software interface is provided for calculating table 33. two-wire impedance synthesis limitations desired configuration programmable limits r s only 100?1000 ? r s + c p r s x c p > 0.5 ms r s + r p ||c p r s /(r s + r p ) > 0.1 r p c p r s z t 2r prot r s r p c p || + () + = dual proslic z t z l r prot r prot si3200 tip ring
SI3220/si3225 rev. 1.0 59 the appropriate coefficients for the fir and iir filter blocks. the transhybrid balance filters can be disabled to implement loopback diagnostic modes. to disable the transhybrid balance filter (zero cancellation), set the hybdis bit in the digcon register to 1. note: the user must enter values into each register location to ensure correct operation when the hybrid balance block is enabled. tone generators dual proslic devices have two digital tone generators that allow a wide variety of single or dual tone frequency and amplitude combinations that spare the user the effort of generating the required pots signaling tones on the pcm highway. dtmf, fsk (caller id), call progress, and other tones can all be generated on-chip. the tones are sent to the receive or transmit paths. (see figure 11 on page 24.) tone generator architecture a simplified diagram of the tone generator architecture is shown in figure 35. the oscillator, active/inactive timers, interrupt block, and signal routing block are connected for flexibility in creating audio signals. control and status register bits are placed in the figure to indicate their association with the tone generator architecture. the register set for tone generation is summarized in table 34. oscillator frequency and amplitude each of the two tone generators contains a two-pole resonant oscillator circ uit with a programmable frequency and amplitude, which are programmed via ram addresses osc1freq , osc1amp, osc1phas, osc2freq, osc2amp, and osc2phas. the sample rate for the two oscillators is 8000 hz. the equations are as follows: coeff n =cos(2 f n /8000 hz), where f n is the frequency to be generated; oscnfreq = coeff n x (2 14 ); where desired vrms is the amplitude to be generated; oscnphas = 0, n = 1 or 2 for oscillator 1 or oscillator 2, respectively. for example, to generate a dtmf digit of 8, the two required tones are 852 hz and 1336 hz. assuming we want to generate half-scale values (ignoring twist), the following values are calculated: figure 35. tone generator diagram oscnamp 1 4 -- - 1coeff ? 1coeff + ----------------------- - 2 15 1 ? () desired vrms 1.11 vrms --------------------------------------- - = zeroenn ensyncn *tone generator 1 only n = "1" or "2" for tone generator 1 and 2, respectively two-pole resonant oscillator 16-bit modulo counter oscnta oscnti oscntien oscntaen oscnfreq oscnphas oscnamp load logic zero cross logic signal routing routn to tx path to rx path int logic osntis osntie int logic osntas osntae rel* register load enable 8 khz clock zero cross oscnen oscnta expire oscnti expire 8 khz clock
SI3220/si3225 60 rev. 1.0 osc1phas = 0 coeff 2 =cos (2 1336 / 8000) = 0.49819 osc2freq = 0.49819 (2 14 ) = 8162 = 0x1fe2 osc2phas = 0 the preceding computed values are written to the corresponding registers to in itialize the oscillators. once the oscillators are initializ ed, the oscillator control registers can be accessed to enable the oscillators and direct their outputs. tone generator cadence programming each of the two tone genera tors contains two timers, one for setting the active period and one for setting the inactive period. the oscillato r signal is g enerated during the active period and su spended during the inactive period. both the active and inactive periods can be programmed from 0 to 8 seconds in 125 s steps. the active period time interval is set using osc1ta for tone generator 1 and osc2ta for tone generator 2. to enable automatic cadence for tone generator 1, define the osc1ta and osc1ti registers and set the osc1taen and osc1tien bits. this enables each of the timers to control the stat e of the oscillator enable bit, osc1en. the 16-bit counter counts until the active timer expires, at which time the 16-bit counter resets to zero and begins counting until the inactive timer expires. the cadence continues until the user clears the osc1ta and osc1tien control bits. setting the zeroen1 bit implements the zero crossing detect feature. this ensu res that each oscillator pulse ends without a dc component. the timing diagram in figure 36 is an example of an output cadence that uses the zero crossing feature. one-shot oscillation is possible with osc1en and osc1taen. direct control over the cadence is achieved by setting the osc1en bit directly if osc1taen and osc1tien are disabled. the operation of tone generato r 2 is identical to that of tone generator 1 using its respective control registers. note: tone generator 2 should not be enabled simulta- neously with the ringing oscillator because of resource sharing within the hardware. coeff 1 2 852 8000 ---------------- - ?? ?? cos 0.78434 == osc1freq 0.78434 2 14 () 12851 0x3233 = == osc1amp 1 4 -- - 0.21556 1.78434 --------------------- 2 15 1 ? () 0.5 1424 0x590 = = = osc2amp 1 4 -- - 0.50181 1.49819 --------------------- 2 15 1 ? () 0.5 2370 0x942 = = =
SI3220/si3225 rev. 1.0 61 table 34. register and ram locations used for tone generation tone generator 1 parameter register/ram mnemonics register/ram bits description/range (lsb size) oscillator 1 frequency coefficient osc1freq osc1freq[15:3] sets oscillator frequency oscillator 1 amplitude coefficient osc1amp osc1amp[15:0] sets oscillator amplitude oscillator 1 initial phase coefficient osc1phas osc1phas[15:0] sets initial phase (default = 0) oscillator 1 active timer o1talo/o1tahi osc1ta[15:0] 0 to 8.19 s (125 s) oscillator 1 inactive timer o1tilo/o1tihi osc1ti[15:0] 0 to 8.19 s (125 s) oscillator 1 control omode, ocon fskssen, osc1fsk, zeroen1, rout1, ensync1, osc1taen, osc1tien, osc1en enables all oscillator 1 param- eters oscillator 1 interrupts irqvec1, irqen1 os1tas, os1tis, os1tae, os1tie interrupt enable/status tone generator 2 parameter location register/ram address description/range oscillator 2 frequency coefficient osc2freq osc2freq[15:3] sets oscillator frequency oscillator 2 amplitude coefficient osc2amp osc2amp[15:0] sets oscillator amplitude oscillator 2 initial phase coefficient osc2phas osc2phas[15:0] sets initial phase (default = 0) oscillator 2 active timer o2talo/o2tahi osc2ta[15:0] 0 to 8.19 s (125 s) oscillator 2 inactive timer o2tilo/o2tihi osc2ti[15:0] 0 to 8.19 s (125 s) oscillator 2 control omode, ocon zeroen2, rout2, ensync2, osc2taen, osc2tien, osc2en enables all oscillator 2 param- eters oscillator 2 interrupts irqvec1, irqen1 os2tas, os2tis, os2tae, os2tie interrupt enable/status
SI3220/si3225 62 rev. 1.0 figure 36. tone generator timing diagram figure 37. on-hook caller id transmission sequence ... ... 0,1 ... 0,1 ... ... , osc1ta ... , osc1ta ... , osc1ti 0,1 ... 0,1 ... osc1en ensync1 tone gen. 1 signal output first ring burst channel seizure mark data packet second ring burst message type message length parameter 1 checksum parameter type data length data content parameter n parameter 2 message header message body
SI3220/si3225 rev. 1.0 63 tone generator interrupts both the active and inactive timers can generate an interrupt to signal ?on/off? transitions to the software. the timer interrupts for tone generator 1 can be individually enabled by setting the os1tae and os1tie bits. timer interrupts for tone generator 2 are os2tae and os2tie. a pending interrupt for each of the timers is determined by reading the os1tas, os1tis, os2tas, and os2tis bits in the irqvec1 register. caller id generation the dual proslic devices generate caller id signals in compliance with various bellcore and itu specifications as described in table 35 by providing continuous phase binary frequency shift keying (fsk) modulation. oscillator 1 is required be cause it pres erves phase continuity during frequency shifts whereas oscillator 2 does not. figure 37 illustra tes a typical caller id transmission sequence in accordance with bellcore requirements. the register and ram locations for caller id generation are listed in table 36. caller id data is entered into the 8-bit fskdat register. the data byte is double buffered so that the dual proslic can generate an interrupt indicating the next data byte can be written when processing begins on the current data byte. the caller id data can be transmitted in one of two modes controlled by the o1fsk8 register bit. when o1fsk8 = 0 (default case), the 8-bit caller id data is transmitted with a start bit and stop bit to create a 10-bit data sequence. if o1fsk8 = 1, the caller id data is transmitted as a raw 8-bit sequence with no start or stop bits. the value programmed into the osc1ta register determines the bit rate, and the interrupt rate is equal to the bit rate divided by the data sequence length (8 or 10 bits). table 35. fsk modulation requirements parameter itu-t v.23 bellcore gr-30-core mark frequency (logic 1) 1300 hz 1200 hz space frequency (logic 0) 2100 hz 2200 hz transmission rate 1200 baud table 36. register and ram locations used for caller id generation parameter register/ram mnemonic register/ram bits description/range (lsb size) fsk start & stop bit enable omode o1fsk8 enable/disable oscillator 1 active timer o1talo/o1 tahi osc1ta[15:0] 0 to 2.73 s (41.66 s)* fsk data byte fskdat fskdat[7:0] caller id data fsk frequency for space fskfreq0 fskfreq0[15:3] audio range fsk frequency for mark fskfreq1 fskfreq1[15:3] audio range fsk amplitude for space fskamp0 fskamp0[15:3] fsk amplitude for ma rk fskamp1 fskamp1[15:3] fsk 0-1 transition freq, high fsk01hi fsk01hi[15:3] fsk 0-1 transition freq, low fsk01lo fsk01lo[15:3] fsk 1-0 transition freq, high fsk10hi fsk10hi[15:3] fsk 1-0 transition freq, low fsk10lo fsk10lo[15:3] *note: oscillator 1 active timer range and lsb stage valid only for fsk mode.
SI3220/si3225 64 rev. 1.0 pulse metering generation the SI3220 offers an additional tone generator to generate tones above the audio frequency band. this oscillator generate s billing tones that are typically 12 khz or 16 khz. the generator follows the same algorithm as described in "tone generator architecture" on page 59 with the exception that the sample rate for computation is 64 khz instead of 8 khz. the equation is as follows: where full scale v pk =0.5v. the pulse metering oscilla tor has a volume envelope (linear ramp) on the on/off tr ansitions of the oscillator. the ramp is controlled by the value in the pmramp ram address, and the sinusoidal generator output is multiplied by this vo lume before it is sent to the pulse metering dac. the volume value is incremented by the value in pmramp at an 8 khz rate. the volume will ramp from 0 to 7fff in increments of pmramp to allow the value of pmramp to set the slope of the ramp. the clip detector stops the ramp once the signal seen at the transmit path exceeds the amplitude threshold set by pmampth, which provides an automatic gain control (agc) function to prevent the audio signal from clipping. when the pulse metering signal is turned off, the volume ramps down to 0 by decrementing according to the value of pmramp. figure 38 illustrates the functional blocks involved in pulse metering generation, and table 37 presents the required register and ram locations that must be set to generate pulse metering signals. coeff 2 f 64000 hz ------------------------- - ?? ?? cos = pmfreq coeff 2 14 1 ? () = pmampl 1 4 -- - 1coeff ? 1 coeff + ----------------------- - 2 15 1 ? () desired v pk fullscale v pk ---------------------------------------- = table 37. register and ram locations used for pulse metering generation parameter register/ram mnemonic register/ram bits description/range (lsb size) pulse metering frequency coefficient pmfreq pmfreq[15:3] sets oscillator frequency pulse metering amplitude coefficient pmampl pmampl[15:0] sets oscillator amplitude pulse metering attack/decay ramp rate pmramp pmramp[15:0] 0 to pmampl (full amplitude) pulse metering active timer pmtalo/pmtahi pulseta[15:0] 0 to 8.19 s (125 s) pulse metering inactive timer pmtilo/pmtihi pulseti[15:0] 0 to 8.19 s (125 s) pulse metering, control interrupt irqvec1, irqe n1 pulstae, pulstie, pulstas, pulstis interrupt status and control registers pulse metering agc amplitude threshold pmampth pmampth[15:0] 0 to 500 mv pm waveform present pmcon ensync indicates signal present pm active timer enable pmcon taen enable/disable pm inactive timer enable pmcon tien enable/disable pulse metering enable pmcon pulse1 enable/disable
SI3220/si3225 rev. 1.0 65 figure 38. pulse metering generation block diagram dtmf detection on-chip dtmf detection, also known as touch tone, is available in the SI3220 and si3225. it is an in-band signaling system that replaces the pulse- dial signaling standard. in dtmf, two tones generate a dtmf digit. one tone is chosen from the four possible row tones, and one tone is chosen from the four possible column tones. the sum of these tones constitutes one of 16 possible dtmf digits. the row and column tones and corresponding digits are shown in table 38. dtmf detection is performed using a modified goertzel algorithm to compute the dft for each of the eight dtmf frequencies and their second harmonics. at the end of the dft computation, the squared magnitudes of the dft results for the 8 dtmf fundamental tones are computed. the row results are sorted to determine the strongest row frequency, and the column frequencies are sorted as well. upon completion of this process, checks are made to determine if the strongest row and column tones constitute a dtmf digit. the detection process occurs twice within the 45 ms minimum tone time. a digit must be detected on two consecutive tests after a pause to be recognized as a new digit. if all tests pass, an interrupt is generated, and the dtmf digit value is loaded into the dtmf register according to table 38. if tones occur at the maximum rate of 100 ms per digit, the interrupt must be serviced within 85 ms so that the current digit is not overwritten by a new one. there is no buffering of the digit information. decimation filter adc dac pulse metering dac pulse metering oscillator volume pmramp peak detector pmampth z a i buf 8 khz 7fff or 0 clip logic ? + 12/16 khz bandpass + + + x + table 38. dtmf row/column tones 697 hz 1 2 3 a 770 hz 4 5 6 b 852 hz 7 8 9 c 941 hz * 0 # d 1209 hz 1336 hz 1477 hz 1633 hz
SI3220/si3225 66 rev. 1.0 table 39 outlines the hex codes corresponding to the detected dtmf digits. modem tone detection the dual proslic devices are capable of detecting a 2100 hz modem tone as described in itu-t recommendation v.8. the detection scheme can be implemented in both transmit and receive paths and is enabled by programming the appropriate register bit. the detection scheme should be disabled for power conservation after the modem tone window has passed. once a valid modem tone is detected, a register bit is set accordingly, and the user can check the results by reading the register value. a programmable debounce interval is provided to eliminate false detection and can be programmed in increments of 67 ms by writing to the appropriate register. audio path processing unlike traditional slics, the dual proslic devices integrate the codec function into the same ic. the on- chip 16-bit codec offers programmable gain/attenuation blocks and multiple loopback modes for self testing. the signal path block diagram is shown in figure 11 on page 24. transmit path in the transmit path, the analog signal fed by the external ac coupling capacitors is passed through an anti-aliasing filter before being processed by the a/d converter. an analog mute function is provided directly prior to the a/d converter input. the output of the a/d converter is an 8 khz, 16-bit wide, linear pcm data stream. the standard requirements for transmit path attenuation for signals abov e 3.4 khz are part of the combined decimation filter characteristic of the a/d converter. one more digital filter, thpf, is available in the transmit path. thpf implements the high-pass attenuation requirements for signals below 65 hz. an equalizer block then equalizes the transmit signal path to compensate for series protection resistance, r prot , outside of the ac-sensing inputs. the linear pcm data stream output from the equalizer block is amplified by the transmit-path programmable gain amplifier, tpga, which can be programmed from ? to 6 db. the dtmf decoder receives the linear pcm data stream and performs the digit extraction if enabled by the user. the final step in the transmit path signal processing is the a-law or -law compression, which can reduce the data stream word width to 8 bits. depending on the pcm mode select register selection, every 8-bit compressed serial data word occupies one time slot on the pcm highway, or every 16-bit uncompressed serial data word occupies two time slots on the pcm highway. receive path in the receive path, the optionally-compressed 8-bit data is first expanded to 16-bit words. the pcmf register bit can bypass the expansion process so that two 8-bit words are assembled into one 16-bit word. rpga is the receive path programmable ga in amplifier, which can be programmed from ? db to 6db. an 8 khz, 16-bit signal is then provided to a d/a converter. an analog mute function is provided directly after the d/a converter. when not muted, the resulting analog signal is applied at the input of the transconductance amplifier, gm, which drives the off-chip current buffer, i buf . tpga/rpga gain/attenuation blocks the tpga and rpga blocks are essentially linear multipliers with the struct ure illustrated in figure 39. both blocks can be independe ntly programmed from ? to +6 db (0 to 2 linear sca le). the txgain and rxgain ram locations are used to program each block. a setting of 0000h mutes all audio signals; a setting of 4000h passes the audio signal with no gain or attenuation (0 db), and a setting of 7fffh provides the maximum 6 db of gain to the incoming audio signal. the dtxmute and drxmute bits in the digcon register table 39. dtmf hex codes digit hex code 1 0x1 2 0x2 3 0x3 4 0x4 5 0x5 6 0x6 7 0x7 8 0x8 9 0x9 0 0xa * 0xb # 0xc a 0xd b 0xe c 0xf d 0x0
SI3220/si3225 rev. 1.0 67 are also available to allow muting of the transmit and receive paths without requir ing modifications to the txgain or rxgain settings. txeq/rxeq equalizer blocks the txeq and rxeq blocks (see figure 11 on page 24) represent 4-tap filters that can be used to equalize the transmit and receive paths, respectively. the transmit path equalizer is controlled by the txeqco0- txeqco3 ram locations, and the receive path equalizer is controlled by the rxeqco0-rxeqco3 ram locations. the si322x coefficient generator software uses these filt ers in calculating the ac impedance coefficients for optimal ac performance. refer to ?an63: si322x coefficient generator user?s guide? for more detailed information regarding the calculation of ac impedance coefficients. figure 39. tpga and rpga structure audio characteristics the dominant source of distortion and noise in both the transmit and receive paths is the quantization noise introduced by the -law or the a-law compression process. figure 5 on page 20 specifies the minimum signal-to-noise and distortion ratio for either path for a sine wave input of 200 hz to 3400 hz. both the -law and the a-law speech encoding allow the audio codec to transfer and process audio signals larger than 0 dbm0 without clipping. the maximum pcm code is generated for a -law encoded sine wave of 3.17 dbm0 or an a-law encoded sine wave of 3.14 dbm0. the device overload clipping limits are driven by the pcm encoding process. figure 6 on page 21 shows the acceptable limits for the analog-to-analog fundamental power transfer-function, which bounds the behavior of the device. the transmit path gain distortion versus frequency is shown in figure 7 on page 21. the same figure also presents the minimum required attenuation for out-of- band analog signals applied on the line. the presence of a high-pass filter transfer function ensures at least 30 db of attenuation for signals below 65 hz. the low- pass filter transfer function attenuates signals above 3.4 khz. it is implemented as part of the a-to-d converter. the receive path transfer function requirement, shown in figure 8 on page 22, is very similar to the transmit path transfer func tion. the pcm data rate is 8 khz; so, no frequencies greater than 4 khz are digitally-encoded in the data stream. at frequencies greater than 4 khz, the plot in figure 8 is interpreted as the maximum allowable magnitude of spurious signals that are generated when a pcm data stream representing a sine wave signal in the range of 300 hz to 3.4 khz at a level of 0 dbm0 is applied at the digital input. the group delay distortion in either path is limited to no more than the levels indicated in figure 9 on page 23. the reference in figure 9 is the smallest group delay for a sine wave in the range of 500 hz to 2500 hz at 0dbm0. the block diagram for the voice-band signal processing paths is shown in figure 11 on page 24. both the receive and the transmit paths employ the optimal combination of analog and digital signal processing for maximum performance while maintaining sufficient flexibility for users to optimize their particular application of the device. the two-wire (tip/ring) voice-band interface to the device is implemented with a small number of external components. the receive path interface consists of a unity-gain current buffer, i buf , while the transmit path in terface is an ac coupling capacitor. signal paths, although implemented differentially, are shown as single-ended for simplicity. system clock generation the dual proslic devices generate the internal clock frequencies from the pclk input. pclk must be synchronous to the 8 khz fsync clock and run at one of the following rates: 256 khz, 512 khz, 786 khz, 1.024 mhz, 1.536 mhz, 1.544 mhz, 2.048 mhz, 4.096 mhz, or 8.192 mhz. the ratio of the pclk rate to the fsync rate is determin ed by a counter clocked by pclk. the three-bit ratio information is transferred into an internal register, pll_mult, after a device reset. the pll_mult controls the internal pll, which multiplies pclk to generate the rate required to run the internal filters and other circuitry. the pll clock synthesizer settles quickly after power- up or update of the pll-mult register. the pll lock process begins immediatel y after the reset pin is pulled high and takes approximately 5 ms to achieve lock after reset is released with stable pclk and fsync. however, the settling time depends on the pclk frequency and can be predicted based on the following equation: tpga or rpga pcm in pcm out x m where m = {0, 1/16384, 2/16384,...32767/16384}
SI3220/si3225 68 rev. 1.0 note: therefore, the reset pi n must be held low during powerup and should only be released when both pclk and fsync signals are known to be stable. figure 40. pll frequency synthesizer interrupt logic the dual proslic devices are capable of generating interrupts for the following events: loop current/ring ground detected ring trip detected ground key detected power alarm dtmf digit detected active timer 1 expired inactive timer 1 expired active timer 2 expired inactive timer 2 expired ringing active timer expired ringing inactive timer expired pulse metering active timer expired pulse metering inactive timer expired ram address access complete receive path modem tone detected transmit path modem tone detected the interface to the interrupt logic consists of six registers. four interrupt status registers (irq0?irq3) contain 1 bit for each of the above interrupt functions. these bits are set when an interrupt is pending for the associated resource. three interrupt mask registers (irqen1?irqen3) also contain 1 bit for each interrupt function. for interrupt mask re gisters, the bits are active high. refer to the appropriate functional description text for operational details of the interrupt functions. when a resource reaches an interrupt condition, it signals an interrupt to the interrupt control block. the interrupt control block sets the associated bit in the interrupt status register if t he mask bit for that interrupt is set. the int pin is a nor of the bits of the interrupt status registers. therefore, if a bit in the interrupt status registers is asserted, irq asserts low. upon receiving the interrupt, the interrupt handler should read interrupt status registers to determi ne which resource requests service. all interrupt bits in the interrupt status registers irq0?irq3 are cleared following a register read operation. if the interrupt status registers are non-zero, the int pin remains asserted. spi control interface the control interface to the dual proslic devices is a 4-wire spi bus modeled after microcontroller and serial peripheral devices. the interface consists of a clock, sclk, chip select, cs , serial data input, sdi, and serial data output, sdo. in addition, the dual proslic devices include a serial data through output (sdi_thru) to support daisy-chain operation of up to eight devices (up to sixteen channels). figu re 41 illustrates the daisy- chain connections. note that the sdithru pin of the last device in the chain must not be connected to ground (sdithru = 0 indicated gci mode). the device operates with both 8-bit and 16-bit spi controllers. each spi operation consists of a control byte, an address byte (of which only the seven lsbs are used internally), and either one or two data bytes depending on the width of the controller and whether the access is to an 8-bit register or 16-bit ram address. bytes are always transmitted msb first. the variations of usage on this four-wire interface are as follows: continuous clocking . during continuous clocking, the data transfers are controlled by the assertion of t settle 64 f pclk -------------- - = pfd div m pll_mult vco 2 2 reset 28.672 mhz pclk
SI3220/si3225 rev. 1.0 69 the cs pin. cs must be asserted before the falling edge of sclk on which the first bit of data is expected during a read cycle and must remain low for the duration of the 8-bit transfer (command/ address or data), going high after the last rising of sclk after the transfer. clock during transfer only . in this mode, the clock is cycling only during the actual byte transfers. each byte transfer consists of ei ght clock cycles in a return to ?1? format. sdi/sdo wired operation . independent of the clocking options described, sdi and sdo can be treated as two separate lines or wired together if the master is capable of tri-stating its output during the data byte transfer of a read operation. soft reset . the spi state machine resets whenever cs asserts during an operation on an sclk cycle that is not a multiple of eight. this is a mechanism for the controller to force the state machine to a known state when the controller and the device are out of synchronization. the control byte has the following structure and is presented on the sdi pin msb first. see table 40 for bit definitions. 76543210 brdcst r/w reg/ram reserved cid[0] cid[1] cid[2] cid[3] table 40. spi control interface 7 brdcst indicates a broadcast operat ion that is intended for all devices in the daisy chain. this is only valid for write operations since it would cause contenti on on the sdo pin during a read. 6r/w read/write bit. 0 = write operation. 1 = read operation. 5 reg/ram register/ram access bit. 0 = ram access. 1 = register access. 4 reserved 3:0 cid[3:0] indicates the channel that is targeted by the operation. note that the 4-bit channel value is provided lsb first. the devices reside on the daisy chain such that device 0 is nearest to the controller, and device 15 is furthest do wn the sdi/sdu_thru c hain. (see figure 41.) as the cid information propagates down the daisy chain, each channel decrements the cid by 1. the sdi nodes between devices reflect a decrement of 2 per device since each device contains two channels. the device receiving a value of 0 in the cid field responds to the spi transaction. (see figure 42.) if a br oadcast to all devices connected to the chain is requested, the cid does not decrement. in this case, the same 8-bit or 16-bit data is pre- sented to all channels regardless of the cid values.
SI3220/si3225 70 rev. 1.0 figure 41. spi daisy-chain mode cpu channel 0 channel 1 sdo sdi sdi sdithru dual proslic #8 dual proslic #2 dual proslic #1 cs cs sdo channel 2 channel 3 sdi sdithru cs sdo channel 14 channel 15 sdi sdithru sdo cs sdi0 sdi1 sdi2 sdi3 sdi4 sdi15 sdi14 sclk sclk sclk spi clock
SI3220/si3225 rev. 1.0 71 in figure 42, the cid field is zero. as this field is decremented (in lsb to msb order), the value decrements for each sdi down the line. the brdcst, r/w, and reg/ram bits remain unchanged as the control word passes through the entire chain. the odd sdis are internal to the device and represent the sdi to sdi_thru connection between channels of the same device. a unique cid is presented to each channel, and the channel receiving a cid valu e of zero is the target of the operation (channel 0 in this case). the last line of figure 42 illustrates that in broadcast mode, all bits pass through the chain without permutation. figure 42. sample spi control word to address channel 0 figures 43 and 44 illustrate write and read operations to register addresses via an 8-bit spi controller. these operations are performed as a 3-byte transfer. cs is asserted between each byte, which is required for cs to be asserted bef ore the first falling edge of sclk after the data byte to indicate to the state machine that one byte only should be transferred. the state of sdi is a ?don?t care? during the data byte of a read operation. figure 43. register write operation via an 8-bit spi port spi control word brdcst r/w reg/ram reserved cid[0] cid[1] cid[2] cid[3] 0 a b c 0 0 0 0 0 a b c 1 1 1 1 0 a b c 0 1 1 1 0 a b c 1 0 1 1 0 a b c 0 1 0 0 0 a b c 1 0 0 0 1 a b c d e f g sdi0 sdi1 (internal) sdi2 sdi3 (internal) sdi 14 sdi15 (internal) sdi0-15 control address data [7:0] sclk sdi sdo hi-z cs
SI3220/si3225 72 rev. 1.0 figure 44. register read operation via an 8-bit spi port figures 45 and 46 illustrate write and read operations to register addresses via a 16-bit spi controller. these operations require a 4-byte transfer arranged as two 16-bit words. the absence of cs going high after the eighth bit of data indicates to the spi state machine that eight more sclk pulses follow to complete the operation. for a write operation, the last eight bits are ignored. for a read operation, the 8-bit data value repeats so that the data is captured during the last half of a data transfer if required by the controller. during register accesses, the control, address, and data are captured in the spi module. at the completion of the address byte of a read access, the contents of the addressed register move into the data register of the spi data register. at the completion of the data byte of a write access, the data is transferred from the spi to the addressed register. figures 47?50 illustrate the va rious cycles for accessing ram addresses. ram addresses are 16-bit entities; therefore, the accesses always require four bytes. during ram address accesses, the control, address, and data are capt ured in the spi module. at the completion of t he address byte of a read access, the contents of the channel-based data buffer move into the data register in the spi for shifting out during the data portion of the spi transfer. this is the data loaded into the data buffer in response to the previous ram address read re quest. therefore, there is a one-deep pipeline nature to ram address read operations. at the completion of the data portion of the read cycle, the address is transferred to the channel-based address buffer register, and a ram address is logged for that channel. the ramstat bit in each channel is polled to monitor the status of ram address accesses that are serviced twice per sample period at dedicated windows in the dsp algorithm. figure 45. register write operation via a 16-bit spi port figure 46. register read operation via a 16-bit spi port control address x x x x x x x x cs sclk sdi sdo data [7:0] x x x x x x x x cs sclk sdi sdo control address data [7:0] hi - z x x x x x x x x cs sclk sdi sdo data [7:0] control address x x x x x x x x data [7:0] same byte repeated twice.
SI3220/si3225 rev. 1.0 73 a ram access interrupt in each channel indicates that the pending ram access request is serviced. for a ram access, the address and data is transferred from the spi registers to the address and data buffers in the appropriate channel. the ram write request is logged. as for read operations, the status of the pending request is monito red by either polling the ramstat bit for the channel or enabling the ram access interrupt fo r the channel. by keeping the address, data buffers, and ramstat register on a per- channel basis, ram address accesses can be scheduled for both channels without interface. figure 47. ram write operation via an 8-bit spi port figure 48. ram read operation via an 8-bit spi port figure 49. ram write operation via a 16-bit spi port sclk sdi sdo control address data [15:8] data [7:0] hi-z cs cs sclk sdi sdo control address x x x x x x x x x x x x x x x x data [15:8] data [7:0] cs sclk sdi sdo control address data [15:8] hi - z data [7:0]
SI3220/si3225 74 rev. 1.0 figure 50. ram read operation via a 16-bit spi port pcm interface the dual proslic devices contain a flexible programmable interface for the transmission and reception of digital pcm samples. pcm data transfer is controlled by the pclk and fsync inputs, pcm mode select, pcm transmit start count (pcmtxhi/ pcmtxlo), and pcm receive start count (pcmrxhi/ pcmrxlo) registers. the interface can be configured to support from 4 to 128 8-bit timeslots in each frame. this corresponds to pclk frequencies of 256 khz to 8.192 mhz in power-of-2 increments. (768 khz, 1.536 mhz, and 1.544 mhz are also available for t1 and e1 support.) timeslots for data transmission and reception are independently configured with the pcmtxhi, pcmtxlo, pc mrxhi, and pcmrxlo. setting the correct starting point of the data configures the part to support long fsync and short fsync variants, idl2 8-bit, 10-bit, and b1 and b2 channel time slots. dtx data is high-impedance except for the duration of the 8-bit pcm transmit. dtx returns to high- impedance on the negative edge of pclk during the lsb or on the positive edge of pclk following the lsb. this is based on the setting of the pcmtri bit of the pcm mode select register. tr istating on the negative edge allows the transmission of data by multiple sources in adjacent timeslots without the risk of driver contention. in addition to 8-bit data modes, a 16-bit mode is provided for testing. this mode can be activated via the pcmf bi ts of the pcm mode select register. setting the pcmtxhi/pcmtxlo or pcmrxhi/pcmrxlo register greater than the number of pclk cycles in a sample period stops data transmission because neither pcmtxhi/pcmtxlo nor pcmrxhi/pcmrxlo equal the pclk count. figures 51?54 illustrate the usage of the pcm highway interface to adapt to common pcm standards. figure 51. example, timeslot 1, short fsync (txs/rxs = 1) cs sclk sdi sdo control address data [15:8] data [7:0] 01 7 6 5 4 3 2 16 15 14 13 12 11 10 9 818 17 msb lsb msb lsb hi-z hi-z pclk fsync pclk_cnt drx dtx
SI3220/si3225 rev. 1.0 75 figure 52. example, timeslot 1, long fsync (txs/rxs = 0) pcm companding the dual proslic devices support both -255 law (- law) and a-law companding formats in addition to linear data mode. the data format is selected via the pcmf bits of the pcm mode select register. -law mode is more commonly used in north america and japan, and a-law is primarily used in europe and other countries. these 8-bit companding schemes follow a segmented curve formatted as a sign bit (msb) followed by three chord bits and four step bits. a-law typically uses a scheme of inverting all even bits while -law does not. dual proslic devices also support a-law with inversion of even bits, inversion of all bits, or no bit inversion by programming the alaw bits of the pcm mode select register to the appropriate setting. table 41 on page 77 and table 42 on page 78 define the -law and a-law encoding formats. the dual proslic devices also support a 16-bit linear data format with no companding. this linear mode is typically used in systems that convert to another companding format, such as adaptive delta pcm (adpcm) or systems that perform all companding in an external dsp. the data format is 2s complement with msb first (sign bit). transmitting and receiving data via linear mode requires two continuous time slots. an 8-bit linear mode enables 8-bit transmission without companding. figure 53. example, idl2 long fsync, b2, 10-bit mode (txs/rxs = 10) 01 7 6 5 4 3 2 16 15 14 13 12 11 10 9 818 17 msb lsb msb lsb hi-z hi-z pclk fsync pclk_cnt drx dtx 01 7 6 5 4 3 2 16 15 14 13 12 11 10 9 818 17 msb lsb msb lsb hi-z hi-z pclk fsync pclk_cnt drx dtx
SI3220/si3225 76 rev. 1.0 figure 54. 16-bit linear mode example, timeslots 1 and 2, long fsync 01 7 6 5 4 3 2 16 15 14 13 12 11 10 9 818 17 msb lsb msb lsb hi-z hi-z pclk fsync pclk_cnt drx dtx
SI3220/si3225 rev. 1.0 77 table 41. -law encode-decode characteristics * segment number #intervals x interval size value at segment endpoints digital code decode level 8 16 x 256 8159 . . . 4319 4063 10000000b 1000 1111b 8031 4191 7 16 x 128 . . . 2143 2015 100 11111b 2079 6 16 x 64 . . . 1055 991 1010 1111b 1023 5 16 x 32 . . . 511 479 10111111b 495 4 16 x 16 . . . 239 223 11001111b 231 3 16 x 8 . . . 103 95 11011111b 99 2 16 x 4 . . . 35 31 11101111b 33 1 15 x 2 __________________ 1 x 1 . . . 3 1 0 11111110b 11111111b 2 0 *note: characteristics are symmetrical about analog ze ro with sign bit = 0 for negative analog values.
SI3220/si3225 78 rev. 1.0 table 42. a-law encode-decode characteristics 1,2 segment number #intervals x interval size value at segment endpoints digital code decode level 7 16 x 128 4096 3968 . . 2176 2048 10101010b 10100101b 4032 2112 6 16 x 64 . . . 1088 1024 10110101b 1056 5 16 x 32 . . . 544 512 10000101b 528 4 16 x 16 . . . 272 256 10010101b 264 3 16 x 8 . . . 136 128 11100101b 132 2 16 x 4 . . . 68 64 11110101b 66 1 32 x 2 . . . 2 0 11010101b 1 notes: 1. characteristics are symmetrical about analog zero with sign bit = 0 for negative values. 2. digital code includes inversion of even-nu mbered bits. other available formats in clude inversion of odd bits, inversion of all bits, or no bit inversion. see "pcm companding" on page 75 for more details.
SI3220/si3225 rev. 1.0 79 general circuit interface the dual proslic devices also contain an alternate communication interface to the spi and pcm control and data interface. the general circuit interface (gci) is used for the transmission and reception of both control and data information onto a gci bus. the pcm and gci interfaces are both four-wir e interfaces and share the same pins. the spi control interface is not used as a communication interface in the gci mode but rather as hard-wired channel selector pins. the selection between pcm and gci modes is performed out of reset using the sdithru pin. tabl es 43 and 44 illustrate how to select the communication mode and how the pins are used in each mode. if gci mode is selected, the following pins must be tied to the correct state to select one of eight subframe timeslots in the gci frame (described below). these pins must remain in this state while the dual proslic is operating. selecting a particular subframe causes that individual dual proslic device to transmit and receive on the appropriate subframe in the gci frame, which is initiated by an fsync pulse. no further register settings are needed to select which sub-frame a device uses, and the sub-frame for a particular device cannot be changed while in operation. in gci mode, the pclk input requires either a 2.048 mhz or a 4.096 mhz clock signal, and the fsync input requires an 8 khz frame sync signal. the overall unit of data used to communicate on the gci highway is a frame 125 s in length. each frame is initiated by a pulse on the fsync pin whose rising edge signifies the beginning of the next frame. in 2x pclk mode, the user sees twice as many pclk cycles during each 125 s frame versus 1x pclk mode. each frame consists of eight fix ed timeslot subframes that are assigned by the sub-frame select pins as described above (sdi, sdo, and cs ). within each sub-frame are four channels (bytes) of data including two voice data channels, b1 and b2, one monitor channel, m, used for initialization and setup of the device, and one signaling and control channel, sc, used for communicating the status of the device and initiating commands. within the sc channel are six command/indicate (c/i) bits and two table 43. pcm or gci mode selection sdithru sclk mode selected 0 0 gci mode?1x pclk (2.048 mhz) 0 1 gci mode?2x pclk (4.096 mhz) 1 x pcm mode note: values shown are the states of the pins at the rising edge of reset . table 44. pin functionality in pcm or gci mode pin name pcm mode gci mode cs spi chip select channel selector, bit 0 sclk spi clock input pclk rate selector sdi spi serial data input channel selector, bit 2 sdo spi serial data output channel selector, bit 1 sdithru spi data throughput pin for daisy chaining operation (connects to the sdi pin of the subsequent device in the daisy chain) pcm/gci mode selector fsync pcm frame sync input gci frame sync input pclk pcm input clock gci input clock dtx pcm data transmit gci data transmit drx pcm data receive gci data receive note: this table denotes pin functionality after the rising edge of reset and mode selection. table 45. gci mode sub-frame selection sdi sdo cs gci subframe 0 selected (voice channels 1?2) 11 1 gci subframe 1 selected (voice channels 3?4) 11 0 gci subframe 2 selected (voice channels 5?6) 10 1 gci subframe 3 selected (voice channels 7?8) 10 0 gci subframe 4 selected (voice channels 9?10) 01 1 gci subframe 5 selected (voice channels 11?12) 01 0 gci subframe 6 selected (voice channels 13?14) 00 1 gci subframe 7 selected (voice channels 15?16) 00 0
SI3220/si3225 80 rev. 1.0 handshaking bits, mr and mx. the c/i bits indicate status and command communication while the handshaking bits monitor receive, mr, and monitor transmit, mx, exchange data in the monitor channel. figure 55 illustrates the co ntents of a gci highway frame. 16-bit gci mode in addition to the standard 8-bit gci mode, the dual proslic devices also offer a 16-bit gci mode for passing 16-bit voice data to the upstream host processor. this mode can be used for testing purposes or for passing non-companded voice data to an upstream dsp for further processing. in 16-bit gci mode, both of the 8-bit voice data channels (b1 and b2 in figure 56) of each sub-frame are required to pass the 16-bit voice data to the host. each 125 s frame can, therefore, accommodate up to eight voice channels (the dual proslic can accommodate up to sixteen voice channels in 8-bit gci mode). table 46 describes the gci mode sub-frame selection for 16-bit gci mode. figure 55. time-multiplexed gci highway frame structure table 46. sub-frame selection 16-bit gci mode sdi sdo gci subframe 0 selected (voice channels 0?1) 11 gci subframe 1 selected (voice channels 2?3) 10 gci subframe 2 selected (voice channels 4?5) 01 gci subframe 3 selected (voice channels 6?7) 00 sf0 sf1 sf7 sf6 sf5 sf4 sf3 sf2 sc b1 b2 m 0123 11 channel sub-frame 8 88 fs c/i mr mx 125 s = 1 frame
SI3220/si3225 rev. 1.0 81 monitor channel the monitor channel is used for initialization and setup of the dual proslic devices. it is also used for general communication with the dual proslic by allowing read and write access to the dual proslic devices registers. use of the monitor channel requires manipulation of the mr and mx handshaking bits located in bits 1 and 0 of the sc channel described. for purposes of this specification, ?downstream? is identified as the data sent by a host to the dual proslic. ?upstream? is identified as the data sent by the dual proslic devices to a host. the following diagram illustrates the monitor channel communication protocol. for successful communication with the dual proslic, the transmitter should anticipate the falling edge of the re ceiver?s ackn owledgement. this also maximizes communication speed. because of the handshaking protocol required for successful communication, the data transfer rate using the monitor channel is less than 8 kbps. figure 56. gci highway frame structure for 16-bit gci mode figure 57. monitor handshake timing sub-frame 16 8 fs 125 s = 1 frame ch0 ch1 ch3 ch2 61 1 16 m b1 c/i mr mx b2 unused 16 transmitter receiver 1st byte 2nd byte 3rd byte mx mx mr ack 1st byte ack 2nd byte ack 3rd byte 125 s mr
SI3220/si3225 82 rev. 1.0 the idle state is achieved by the mx and mr bits being held inactive for two or more frames. when a transmission is initiated by a host device, an active state is seen on the downstream mx bit. this signals the dual proslic that a transmission has begun on the monitor channel and it should begin accepting data from it. after reading the data on the monitor channel, the dual proslic acknowledges the initial transmission by placing the upstream mr bit in an active state. the data is received, and the upstream mr becomes active in the frame immediately following the downstream mx activation. the upstream mr then remains active until either the next byte is receiv ed or an end of message is detected (signaled by the downstream mx being held inactive for two or more consecutive frames). upon receiving acknowledgement from the dual proslic that the initial data was receiv ed (signaled by the upstream mr bit transitioning from an inactive to an active state), the host device places the downstream mx bit in the inactive state for one frame and then either transmits another byte by placing the downstream mx bit in an active state again or signals an end of message by leaving the downstream mx bit inactive for a second frame. when the host is performi ng a write command, the host only manipulates the downstream mx bit, and the dual proslic only manipulates the upstream mr bit. if a read command is performed, the host initially manipulates the downstream mx bit to communicate the command but then manipulates the downstream mr bit in response to the dual proslic responding with the requested data. similarly, the dual proslic initially manipulates its upstream mr bit to receive the read command and then manipulates its upstream mx bit to respond with the requested data. if the host is transmitting data, the dual proslic always transmits a $ff value on its monitor data byte. while the dual proslic is transmitting data, the host should always transmit a $ff value on its monitor byte. if the dual proslic is transmitting data and detects a value other than a $ff on the downstream monitor byte, the dual proslic signals an abort. for read and write commands, an initial address must be specified. the dual pros lic responds to a read or a write command at this address and then subsequently increments this address after every register access. in this manner, multiple consec utive registers can be read or written in one transmission sequence. by correctly manipulating the mx and mr bits, a transmission sequence can continue from the beginning specified address until an invalid memo ry location is reached. to end a transmission sequence, the host processor must signal an end-of-message (eom) by placing the downstream mx and mr bits inactive for two consecutive frames. the transmission can also be stopped by the dual proslic by signaling an abort. this is signaled by placing the upstream mr bit inactive for at least two consecutive cycles in response to the downstream mx bit going active. an abort is signaled by the dual proslic for the following reasons: a read or write to an invalid memory address is attempted. an invalid command sequence is received. a data byte was not received for at least two consecutive frames. a collision occurs on the monitor data bytes while the dual proslic is transmitting data. downstream monitor byte not $ff while upstream monitor byte is transmitting. mr/mx protocol violation. whenever the dual proslic aborts due to an invalid command sequence, the stat e of the dual proslic does not change. if a read or write to an invalid memory address is attempted, all prev ious reads or writes in that transmission sequence are valid up to the read or write to the invalid memory address. if an end-of-message is detected before a valid command sequence is communicated, the dual proslic returns to the idle state and remains unchanged. the data presented to the dual proslic in the downstream monitor bits must be present for two consecutive frames to be considered valid data. the dual proslic is designed to ensure it has received the same data in two consecutive frames. if it does not, it does not acknowledge receipt of the data byte and waits until it does receive two cons ecutive identical data bytes before acknowledging to the transmitter it has received the data. if the transmitter attempts to signal transmission of a subsequent data byte by placing the downstream mx bit in an inactive state while the dual proslic is still waiting to receive a valid data byte transmission of two consecutive identical data bytes, the dual proslic signals an abort and ends the transmission. figure 58 shows a state diagram for the receiver monitor channel for the dual proslic. figure 59 shows a state diagram for the transmitter monitor channel for the dual proslic.
SI3220/si3225 rev. 1.0 83 figure 58. dual proslic monitor receiver state diagram idle mr = 1 1st byte rec eiv ed mr = 0 byte v alid mr = 0 new byte mr = 1 nth byte received mr = 1 wait for ll mr = 0 wait for ll mr = 0 abort mr = 1 mx mx mx mx mx mx mx mx mx * ll mx * ll mx * ll mx * ll mx * ll initial state any state mx * ll abt mr: mr bit calculated and transmitted on data upstream (dtx) line. mx: mx bit received data downstream (drx) line. ll: last look of monitor byte received on drx line. abt: abort ind ication to in terna l s ource. mx mx
SI3220/si3225 84 rev. 1.0 figure 59. dual proslic monitor transmitter state diagram initial state mr: mr bit received on drx line. mx: mx bit calculated and expected on dtx line. mxr: mx bit sampled on dtx line. cls: collision within the monitor data byte on dtx line. rqt: request for transmission from internal source. abt: abort request/indication. idle mr = 1 1st byte mx = 0 nth byte ack mx = 1 wait for ack mx = 0 eom mx = 1 mr mr cls/abt abort mx = 1 wait mx = 1 mxr mr * mxr mr * mxr mr * mxr mr mr * rqt mr * rqt mr * rqt mr * rqt mr * rqt mr any state
SI3220/si3225 rev. 1.0 85 figures 60 and 61 are example timing diagrams of a register read and a register write to the dual proslic using the gci. as noted in figure 59, the transmitter should always anticipate the acknowledgement of the receiver for correct communication with the dual proslic. devices that do not accept this ?best case? timing scenario will not be able to communicate with the dual proslic. m onitor da ta dow nstre a m $ff $ff $91 $91 $81 $81 $10 $10 $ff $ff $ff $ff $ff $ff $ff $ff $ff 125 s 1 frame mx dow nstream bit mr dow nstream bit m onitor da ta upstre a m $ff $ff $ff $ff $ff $ff $ff $ff $ff $91 $91 c ontents of r eg ister $10 c ontents of r eg ister $10 c ontents of r eg ister $11 c ontents of r eg ister $11 c ontents of r eg ister $12 (ig nored by host) $ff mx upstream bit mr upstream bit sends address before data eom acknowledge eom signalled = acknowledgement of data reception figure 60. example read of registers $10 and $11 in channel 0 of the dual proslic
SI3220/si3225 86 rev. 1.0 figure 61. example write to registers $10 and $11 in channel 0 of the dual proslic monitor data downstream $ff $ff $91 $91 $01 $01 $10 $10 data to be written to $10 data to be written to $10 data to be written to $11 data to be written to $11 $ff $ff 125 s 1 frame mx downstream bit mr downstream bit monitor data upstream $ff $ff $ff $ff $ff $ff $ff $ff $ff $ff $ff $ff $ff $ff mx upstream bit mr upstream bit eom acknowledge eom signalled = acknowledgement of data reception
SI3220/si3225 rev. 1.0 87 programming the dual proslic using the monitor channel the dual proslic devices use the monitor channel to transfer status or operating mode information to and from the host processor. communication with the dual proslic should be in the following format: byte 1: device address byte byte 2: command byte byte 3: register address byte bytes 4-n: data bytes bytes n+1, n+2: eom device address byte the device address byte identifies which device receives the particular message. this address must be the first byte sent to the dual proslic at the beginning of each transmission sequence. the device address byte has the following structure: a = 1: channel a receives the command. a = 0: channel a does not receive the command. b = 1: channel b receives the command. b = 0: channel b does not receive the command. c = 1: normal command follows. c = 0: channel identification command. when c = 1, bits a and b are channel enable bits. when these bits are set to 1, the corresponding channels receive the command in the next command byte. the channels with corresponding bits set to 0 ignore the subsequent command byte. channel identification (cid) command the lowest programmable bit of the device address byte, c, enables a special channel identification command to identify themselves by software. when c = 0, the structure of this command is as follows: a = 1: channel a is the destination a = 0: channel b is the destination immediately after the last bit of the cid command is received, the dual proslic responds with a fixed two- byte identification code as follows: a = 1: channel a is the source a = 0: channel b is the source upon sending the two-byte cid command, the dual proslic sends an eom signal (mr = mx = 1) for two consecutive frames. when c = 0, b must be 0, or the dual proslic signals an abort due to an invalid command. in this mode, only bit c is programmable. command byte the command byte has the following structure: rw = 1: a read operation is performed from the dual proslic rw = 0: a write operation is performed to the dual proslic cmd[6:0] = 0000001: read or write from the dual proslic cmd[6:0] = 0000010-1111111: reserved register address byte the register address byte has the following structure: this byte contains the actual 8-bit address of the register to be read or written. sc channel the downstream and upstream sc channels are continuously carrying i/o information to and from the dual proslic during every frame. the upstream processor has immediate access to the receive (downstream) and transmit (upstream) data present on the dual proslic digital i/o port when used in gci mode. the sc channel consists of six c/i bits and two handshaking bits as described in the tables below. the functionality of the handshak ing bits is defined in the msb lsb 7 6543210 100ab00c msb lsb bit 7 654321 0 address byte 1 0 0 a 0 0 0 0 command byte 0 0 0 0 0 0 0 0 msb lsb bit 7 654321 0 address byte 1 0 0 a 0 0 0 0 command byte 1 0 1 1 1 1 1 0 msb lsb rw cmd[6:0] msb lsb address[7:0]
SI3220/si3225 88 rev. 1.0 monitor channel section. this section defines the functionality of the six c/i bits whether they are being transmitted to the gci bus via the dtx pin (upstream) or received from the gci bus via the drx pin (downstream). the structure of the sc channel is shown in figure 62. figure 62. sc channel structure downstream (receive) sc channel byte the first six bits in the downstream sc channel control both channels of the dual proslic where the c/i bits are defined as follows: figure 63 illustrates th e transmission prot ocol for the c/i bits within the downstream sc channel. new data received by either channel must be present and match for two consecutive frames to be considered valid. when a new command is communicated via the downstream c/i bits, this data must be sent for at least two consecutive frames to be recognized by the dual proslic. the current state of the c/i bits is stored in a primary register, p. if the received c/i bits are identical to the current state, no action is ta ken. if the received c/i bits differ from those in register p, the new set of c/i bits is loaded into secondary register s, and a latch is set. when the next set of c/i bits is received during the frame that immediately follows, the following rules apply: if the received c/i bits are identical to the contents of register s, the stored c/i bits are loaded into register p, and a valid c/i bit transition is recognized. the latch is reset, and the dual proslic responds accordingly to the command represented by the new c/i bits. if the received c/i bits differ from both th e contents of register s and the contents of register p, the newly- received c/i bits are loaded into register s, and the latch remains set. this cycle continues as long as any new set of c/i bits differs from the contents of registers s and p. if the newly-received c/i bi ts are identical to the contents of register p, the contents of register p remain unchanged, and the latch is reset. msb lsb 76543210 ci2a ci1a ci0a ci2b ci1b ci0b mr mx ci2a, ci1a, ci0a used to select operating mode for channel a ci2b, ci1b, ci0b used to select operating mode for channel b mr, mx monitor channel handshake bits table 47. programming operating modes using downstream sc channel c/i bits channel specific c/i bits dual proslic operating mode ci2x ci1x ci0x 0 0 0 open (high impedence, no line monitoring) 0 0 1 forward active 0 1 0 forward on-hook trans- mission 0 1 1 ground start (tip open) 100ringing 1 0 1 reverse active 1 1 0 reverse on-hook trans- mission 1 1 1 ground start (ring open) note: x = a or b, corresponding to channel a or channel b.
SI3220/si3225 rev. 1.0 89 figure 63. protocol for receiving c/i bits in the dual proslic when the dual proslic is set to gci mode at initialization, the default setting ignores the downstream sc channel byte and allows linefeed state commands to be directed through the monitor channel. this default configuration is enabled by initializing the gciline bit of the pcmmode register to 0, which prevents the dual proslic from transitioning between linefeed operating states due to invalid data that may exist within the downstream sc channel byte. to transfer direct linefeed control to the downstream sc channel, the user must set the gciline bit to 1. once the gciline bit has been set, the dual prosli c follows the commands that are contained in the downstream sc channel byte as described in figure 62. the dual proslic architecture also enables automatic transitions between linefeed operating states to reduce the amount of interaction required between the host processor and the dual proslic. when a gci bus is implemented, the user mu st ensure that these automatic linefeed state transitions are consistent with the linefeed commands contained within the downstream sc channel byte. in normal operation, thes e automatic linefeed state transitions are accompanied by the setting of a threshold detection flag and an interrupt bit, if enabled. to allow the dual proslic to automatically detect the appropriate thresholds and control the linefeed transitions, the downstream sc channel byte should be updated accordingly once the interrupt bit is read from the upstream sc channel byte. to disable the automatic transitions, the user must set the gciline bit. enabling this manual mode requires the host processor to read the upstream sc channel information and provide the appropriate downstream sc channel byte command to program the correct linefeed state. table 48 presents the automatic linefeed state transitions and their associated registers that cause the transition. the transition to the open state stemming from power alarm detection is intended to protect the dual proslic circuit in the event that too much power is dissipated in the si3200 lfic. this alarm is typically due to a fault in the application circuit or on the subscriber loop but can be caused by intermittent power spikes depending on the threshold to which the alarm is set. the user can re- initialize the linefeed operating state that was in effect just prior to the power alarm by toggling the downstream sc channel byte to the open state for two consecutive cycles and then resetting the downstream sc channel byte to the intended linefee d state for two consecutive receive new c/i code store in s receive new c/i code = p? = p? = s? load c/i register with new c/i bits yes no yes yes no no p: c/i primary register contents s: c/i secondary register contents
SI3220/si3225 90 rev. 1.0 cycles. if the dual proslic continues to automatically transition to the open state, the power alarm threshold might be set incorrectly. if this problem persists after the power alarm settings are verified, a system fault is probable, and the user should take measures to diagnose the problem. upstream (transmit) sc channel byte the upstream sc channel byte looks similar to the downstream sc channel byte except that the information quickly transfers the most time-critical information from the dual proslic to the gci bus. each upstream sc channel byte transfer from the dual proslic lasts for at least two consecutive frames to represent a valid transfer. the upstream c/i bits are defined as follows: ci2a, ci1a, ci0a monitors status data for channel a ci2b, ci1b, ci0b monitors status data for channel b mr, mx monitor channel handshake bits (see monitor channel section) table 48. automatic linefeed state transitions initiating action automatic linefeed state transition detection/control bits in terrupt enable/status bits loop closure detected on-hook active off-hook active, off-hook active on-hook active lcr (register 9) loope, loops (register 16/19) ring trip detected ringing off-hook active rtp (register 9) rtripe, rtrips (register 16/19) ringing burst cadence ringing on-hook transmission on-hook transmission ringing t1en, t2en (register 23) ringt1e, ringt2e, ringt1s, ringt2s (register 15/18) power alarm detected any state open pq1dl (ram 50) pq1e, pq1s (registers 17/20) table 49. monitored data via upstream sc channel c/i bits c/i bit information provided mirrored register bits context ci2a interrupt information on channel a irq0[0]+ irq0[1]+ irq0[2] ci2a = 0: no interrupt on channel a ci2a = 1: interrupt present on channel a ci1a hook status information on channel a lcrrtp[0] (lcr bit) ci1a = 0: channel a is on-hook ci1a = 1: channel a is off-hook ci0a ground key information on channel a lcrrtp[2] (longhi bit) ci0a = 0: no longitudinal current detected ci0a = 1: longitudinal current detected in chan- nel a ci2b interrupt information on channel b irq0[4]+ irq0[5]+ irq0[6] ci2a = 0: no interrupt on channel b ci2a = 1: interrupt present on channel b ci1b hook status information on channel b lcrrtp[0] (lcr bit) ci1a = 0: channel b is on-hook ci1a = 1: channel b is off-hook ci0b ground key information on channel b lcrrtp[2] (longhi bit) ci0a = 0: no longitudinal current detected ci0a = 1: longitudinal current detected in chan- nel b
SI3220/si3225 rev. 1.0 91 the interrupt information for channels a and b is a single bit that indicates that one or more interrupts might exist on the respective channel. each of the individual interrupt flags (see registers 18?20) can be individually masked by writing the appropriate bit in registers 21?23 to ignore specific interrupts. when using the gci mode, the user should verify that each of the desired interrupt bits are set so the upstream sc channel byte includes the required interrupt functions. system testing the dual proslic devices include a complete suite of test tools to test the functionality of the line card and detect fault conditions present on the tip/ring pair. using one of the loopback test modes with the signal generation and measurement tools eliminates the need for per-line test relays and centralized test equipment. loopback modes three loopback test options are available for the dual proslic devices: the codec loopback path encompasses almost entirely the electronics of both the transmit and receive paths. the analog signal at the output of the receive path is fed back to the input of the transmit path through a feedback path on the analog side of the audio codec. both the impedance synthesis and transhybrid balance functions are disabled in this mode. (see dlm3 path in figure 11 on page 24.) the signal path starts with 8-bit pcm data input to the receive path and ends with 8-bit pcm data at the output of the transmit path. the user can bypass the companding process and interface directly to the 16- bit data. a second digital loopback takes the receive path digital stream and routes it back to the transmit path via the transhybrid feedback path. (see dlm2 path through block h in figure 11.) this mode characterizes the transhybrid filter response. the transhybrid block can also be disabled (set to unity gain) in this mode for diagnosing the digital gain blocks and filter stages in both transmit and receive paths. the signal path starts with 8-bit pcm data input to the receive path and ends with 8-bit pcm data at the output of the transmit path. the user can bypass the companding process and interface directly to the 16-bit data. a third digital loopback takes the digital stream at the output of the -law/a-law expander and feeds it back to the input of the -law/a-law compressor. (see dlm1 path in figure 11.) this path verifies that the host is connected correctly with the dual proslic through the pcm interface and that the pclk and fsync signals are correctly set. this mode also can test the -law/a-law companding process. the signal path starts with 8-bit pcm data input to the rece ive path and ends with 8-bit pcm data at the output of the transmit path. the user can also connect directly to the 16-bit data to eliminate the -law/a-law companding process when testing the pcm interface. line test and diagnostics the dual proslic devices provide a variety of signal generation and meas urement tools that facilitate fault detection and parametric diagnostics on the tip/ring pair and line card functionality verification. the dual proslic generates test signals, measures the appropriate voltage/current/signal levels, and processes the results to provide a meaningful result to the user. interaction is required from the host microprocessor to load the test parameters into the appropriate registers, initiate the test(s), and read the results from the registers. in some cases, the host processor might also be required to perform some simple mathematics to achieve the results. softwa re modules are available to simplify integration of the di agnostics functions into the system. the need for test relays and a separate test head is eliminated in most applications. to address legacy applications, all versions of the dual proslic include test-in and test-out re lay drivers to switch in a centralized test head. the dual proslic line test and diagnostics capabilities are categorized into three sections: signal generation tools, measure ment tools, and diagn ostics capabilities. using these signal generation and measurement tools, a variety of other diagnost ic functions can be performed to meet the unique requirements of specific applications. table 50 summarizes the ranges and capabilities of the signal generation and measurement tools.
SI3220/si3225 92 rev. 1.0 signal generation tools tip/ring dc signal generation. the dual proslic line feed d/a converter can program a constant current linefeed from 18?45 ma in 0.87 ma steps with a 10% total accuracy. in addition, the open- circuit tip/ring voltage can be programmed from 0 to 63 v in 1 v steps. the linefeed circuitry can also generate a controlled polarity reversal. tone generation. the dual proslic devices can generate single or dual tones over the entire audio band and can direct them into either the transmit or receive path depending on the diagnostic requirements. ringing signals from 4?100 hz can also be generated. diagnostics mode ringing generation. the dual proslic devices can generate an internal low-level ringing signal to test for the presence of ren without causing the terminal equipment to ring audibly. this ringing signal can be either balance or unbalanced depending on the state of the ringunb bit of the ringcon register. this fe ature is also available with the si3225 provided that a sufficient battery voltage is present. table 50. summary of signal generation and measurement tools function range accuracy/resolution comments signal generation tools dc current generation 18 to 45 ma 0.875 ma dc voltage generation 0 to 63.3 v 1.005 v audio tone generation 200 to 3400 hz ringing signal generation 4 to 15 hz 16 to 100 hz 5% 1% measurement tools 8-bit dc/low-frequency monitor a/d converter high range: 0 to 160.173 v 0 to 101.09 ma 628 mv 396.4 a 800 hz update rate ac rms , ac pk , and dc post-processing blocks low range: 0 to 64.07 v 0 to 50.54 ma 251 mv 198.2 a programmable timer 0 to 8.19 s 125 s ac low-pass filter 3 to 400 hz 16-bit audio a/d converter 0 to 2.5 v 38 v transmit path notch filter 300 to 3400 hz single or dual notch, 90 db attenuation transmit path bandpass filter 300 to 3400 hz
SI3220/si3225 rev. 1.0 93 figure 64. slic diagnostic filter structure measurement tools 8-bit monitor a/d converter. this 8-bit a/d converter monitors all dc and low-frequency voltage and current data from tip to ground and ring to ground. two additional values, tip ? ring and tip + ring, are calculated and stored in on-chip registers to analyze metallic and longitudinal effects. the a/d operates at an 800 hz update rate to allow measurement bandwidth from dc to 400 hz. a dual- range capability allows hi gh-voltage/high-current measurement in the high range but can also measure lower voltages and currents with a tighter resolution. programmable bandpass filter. a bandpass filter discriminates certain frequency ranges, such as ringing frequencies and 50 hz/60 hz induction, from nearby or crossed power leads. slic diagnostics filter. several post-processing filter blocks monitor peak dc and ac characteristics of the monitor a/d converter outputs and values derived from these outputs. setting the sdiag bit in the diag register enable s the filters. there are separate filters for each channel, and their control is independent. these filters require dsp processing, which is available only when voice band processing is not being performed. if an off-hook or ring trip condition is detected while the sdiag bit is set, the bit is cleared, and the di agnostic information is not processed. the following parameters can be selected as inputs to the diagnostic block by setting the sdiag bits in the diag register to values 0?7 corresponding to the order below: v tip = voltage on the tip lead v ri ng = voltage on the ring lead v loop =v tip -v ring = metallic (loop) voltage v long =(v tip +v ring )/2 = longitudinal voltage i loop =i tip -i ring = metallic (loop) current i long =(i tip +i ring )/2 = longitudinal current v ring, ext = ringing voltage when using an external ringing source (si3225 only) i ring,ext = ringing current when using an external ringing source (si3225 only) the slic diagnostic capability consists of a peak detect block and two filter blocks, one for dc and one for ac. the topology is illu strated in figure 64. the peak detect filter block reports the magnitude of the largest positive or negative value without sign. the dc filter block consists of a single pole iir low-pass filter with a coefficient held in the diagdcco ram location. the filter output is read from the diagdc ram location. the ac filter block consists of a full-wave rectifier followed by a single-pole iir low-pass filter with a coefficient held in the diagacco ram location. the peak value is read from the diagpk ram location. the peak value is cleared and the filters are flushed on the 0-1 transition of the sdiag bit and when the input source changes. the user can write 0 to the diagpk ram location to get peak information for a specific time interval. 16-bit audio a/d converter. the a/d converter portion of the audio codec is made available for processing test data received back through the transmit audio path. the audio path offers a 2.5 v peak voltage measurement capability and a coarse attenuation stage for scenarios where the incoming signal amplitude must be attenuated by as much as 3 db to bring it into the allowable input range without clipping. vtip vring vloop vlong iloop ilong vring,ext iring,ext lpf peak detect full wave rectify lpf diagac diagdc diagpk diagacco diagdcco
SI3220/si3225 94 rev. 1.0 programmable timer. the dual proslic devices incorporate se veral digital oscilla tor circuits to program the on and off times of the ringing and pulse-metering signals. the tone generation oscillator can be used to program a time period for averaging specific measured test parameters. transmit audio path diagnostics filter. transmit path audio diagnostics are facilitated by implementing a sixth-order iir filter followed by peak detection and power estimation blocks. this filter can be programmed to eliminate or amplify specific signals for the purpose of measuring the peak amplitude and power content of individual components in the audio spectrum. figure 11 on page 24 illustrates the lo cation of the diagnostics filter block. the sixth order iir filter operates at an 8 khz sample rate and is implemented as three second-order filter stages in cascade. each second-order filter offers five fully-programmable coefficients (a1, a2, b0, b1, and b2) with 25-bit precision by providing several user-accessible registers. each filter stage is implemented with the following format: if any of the second-order filter stages are not required, they can be programmed to h(z) = 1 by setting a1 = 0, a2 = 0, b0 = 1, b1 = 0, and b2 = 0. this flexible filter block can be programmed with the following characteristics: single notch. used for measuring noise/distortion in the presence of a single tone. 90 db attenuation is provided at the notched frequency. implemented by placing two 0s on the unit circle at the notch frequency and two poles inside the unit circle at the notch frequency. dual notch. used for measuring noise/distortion in the presence of dual tones. single notch/single peak. used for measuring particular harmonic in the presence of a single tone. dual notch/single peak. used to measure particular intermodulation product in the presence of dual tones. because each second-order filter stage is fully- programmable, there are many other possible filter implementations. the iir filter output is measured for power and peak post-processing. the peak measurement window duration is programmable by entering a value into the testwln ram address. the peak value (testpko) is updated at the end of each window period. power measurement is performed by using a single-pole iir filter to average the output of the sixth-order iir filter. the power averaging filter time constant is absolute value programmable, and the average power result is read from the testavo ram location. diagnostics capabilities foreign voltages test. the dual proslic devices can detect the presence of foreign voltages according to gr-909 requirements of ac voltages > 10 v and dc voltages > 6 v from t-g or r-g. this test is performed when it has been determined that a hazardous voltage is not present on the line. resistive faults (leakage current) test. resistive fault conditions are measured from t-g, r-g, or t-r for dc resistance per gr-909 specifications. if the dc resistance is < 150 k ? , it is considered a resistive fault. to perform this test, program the dual proslic chipset to generate a constant open-circuit voltage, and measure the resulting current. the resistance is then calculated. receiver off-hook test. uses a similar procedure as described in the resistive faults test above but is measured across t-r only. in addition, two measurements must be performed at different open- circuit voltages to verify t he resistive linearity. if the calculated resistance has more than 15% nonlinearity between the two calculated points and the voltage/current origin, it is determined to be a resistive fault. ringers (ren) test. verifies the presence of ren at the end of the tip/ring pair per gr-909 specifications. it can be implemented by generating a 20 hz ringing signal between 7 v rms and 17 v rms and measuring the 20 hz ac current using the 8-bit monitor adc. the resistance (ren) can then be calculated using the software module. the acceptable ren range is > 0.175 ren (< 40 k ? ) or < 5 ren (> 1400 ? ). a returned value of < 1400 ? is determined to be a resistive fault from t-r, and a returned value > 40 k ? is determined to be a loop with no handset attached. ac line impedance measurement. determines the ac loop impedence across t-r. it can be implemented by sending out multiple discrete tones, one at a time, and measuring the returned amplitude with the hybrid balance filter disabled. by calculating the voltage difference between the initial amplitude and the received amplitude and dividing the result by the audio current, the line impedance can then be calculated. hz () b0 b1z 1 ? b2z 2 ? ++ () 1a1z 1 ? ? a2z 2 ? ? () ------------------------------------------------------- - =
SI3220/si3225 rev. 1.0 95 line capacitance measurement. implemented like the ac line impedance measurement test above, but the frequency band of interest is between 1 khz and 3.4 khz. knowing the synthesized 2-wire impedance of the dual proslic, the roll-off effect can be used to calculate the ac line capacitance. ringing voltage verification. verifies that the desired ringing signal is correctly applied to the tip/ ring pair and can be measured in the 8-bit monitor adc, which senses low-frequency signals directly across t-r. idle channel noise measurement. given any transmission mode with no tone generated and the hybrid balance filter turned off, the voice band energy can be measured through the normal audio path and read through the appropriate register. echo path gain measurement. harmonic distortion measurement. detects the power content of a particular harmonic. it can be implemented by programming two of the iir diagnostics filter stages to provide a notch at the fundamental frequency and a peak at the harmonic of interest. performing this procedure on all relevant harmonics individually and summing the results provides the total harmonic distortion. intermodulation distortion measurement (two- tone method). measures the intermodulation distortion product in the presence of two tones. it can be implemented by programming the three iir diagnostic filter stages to provide two notches at the two tone frequencies and a peak at the frequency of interest.
SI3220/si3225 96 rev. 1.0 pin descriptions: SI3220/25 pin number(s) symbol input/ output description SI3220 si3225 1, 16 1, 16 svbata, svbatb i battery sensing input. analog current input used to sense battery voltage. 2,15 2,15 rpoa, rpob o transconductance amplifier external resistor connec- tion. 3, 14 3, 14 rpia, rpib i transconductance amplifier external resistor connec- tion. 4, 13 4, 13 rnia, rnib i transconductance amplifier resistor connection. 5, 12 5, 12 rnoa, rnob o transconductance amplifier resistor connection. 6, 11 6, 11 cappa, cappb differential capacitor. capacitor used in lo w-pass filter to st abilize slic feedback loops. 7, 10 7, 10 capma, capmb common mode capacitor. capacitor used in lo w-pass filter to st abilize slic feedback loops. 88 qgnd component reference ground. return path for differential and common-mode capacitors. do not connect to system ground. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 20 19 18 24 23 22 21 31 30 29 28 27 26 25 32 64 61 62 63 57 58 59 60 50 51 52 53 54 55 56 49 rpoa svbata rpia rnia rnoa cappa capma qgnd iref capmb cappb rnob rnib rpib rpob svbatb stipacb stipdcb sringacb sringdcb itipnb iringnb itippb vdd2 gnd2 iringpb thermb rtrpb trd1b trd2b rrdb batselb cs rrda sdithru sdi sdo sclk vdd4 gnd4 int pclk gnd3 vdd3 dtx drx reset fsync stipaca stipdca sringaca sringdca itipna iringna itippa vdd1 gnd1 iringpa therma blkrng rtrpa trd1a batsela trd2a si3225 64-lead tqfp (epad) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 20 19 18 24 23 22 21 31 30 29 28 27 26 25 32 64 61 62 63 57 58 59 60 50 51 52 53 54 55 56 49 rpoa svbata rpia rnia rnoa cappa capma qgnd iref capmb cappb rnob rnib rpib rpob svbatb stipacb stipdcb sringacb sringdcb itipnb iringnb itippb vdd2 gnd2 iringpb thermb nc trd1b trd2b gpob batselb cs gpoa sdithru sdi sdo sclk vdd4 gnd4 int pclk gnd3 vdd3 dtx drx reset fsync stipaca stipdca sringaca sringdca itipna iringna itippa vdd1 gnd1 iringpa therm a nc nc trd1a batsela trd2a SI3220 64-lead tqfp (epad)
SI3220/si3225 rev. 1.0 97 99 iref i iref current reference. connects to an external resistor to provide a high accuracy ref- erence current. return path for iref resistor should be routed to qgnd pin. 17, 64 17, 64 stipdcb, stipdca i tip sense. analog current input senses dc voltage on tip side of sub- scriber loop. 18, 63 18, 63 stipacb, sti- paca i tip transmit input. analog input senses ac voltage on tip side of subscriber loop. 19, 62 19, 62 sringacb, sringaca i ring transmit input. analog input senses ac voltage on ring side of subscriber loop. 20, 61 20, 61 sringdcb, sringdca i ring sense. analog current input senses dc voltage on ring side of subscriber loop. 21, 60 21, 60 itipnb, itipna o negative tip current control. analog current output provides dc current return path to v bat from tip side of the loop. 22, 59 22, 59 iringnb, iringna o negative ring current control. analog current output provides dc current return path to v bat from ring side of loop. 23, 58 23, 58 itippb, itippa o positive tip current control. analog current output drives dc current onto tip side of sub- scriber loop in normal polarity. also modulates ac current onto tip side of loop. 24, 37, 42, 57 24, 37, 42, 57 v dd2 ,v dd3 , v dd4 ,v dd1 supply voltage. power supply for internal analog and digital circuitry. connect all v dd pins to the same supply and decouple to adjacent gnd pin as close to the pins as possible. 25, 38, 41, 56 25, 38, 41, 56 gnd2,gnd3, gnd4,gnd1 ground. ground connection for internal analog and digital circuitry. connect all pins to low-impedance ground plane. 26, 55 26, 55 iringpb, iringpa o positive ring current control. analog current output drives dc current onto ring side of sub- scriber loop in reverse polarity. also modulates ac current onto ring side of loop. 27,54 27,54 thermb, therma i temperature sensor. senses internal temperature of si3200. connect to therm pin of si3200 or to v dd when using discrete linefeed circuit. 29, 51 29, 51 trd1b, trd1a o test relay driver output. drives test relays for connecting loop test equipment. pin number(s) symbol input/ output description SI3220 si3225
SI3220/si3225 98 rev. 1.0 28, 52, 53 nc no internal connection. leave unconnected or connect to ground plane. 28, 52 rtrpb, rtrpa i external ring trip sensing input. used to sense ring-trip conditi on when using centralized ring generator. connect to low side of ring sense resistor. 30, 50 30, 50 trd2b, trd2a o test relay driver output. drives test relays for conne cting loop test equipment. 31, 48 rrdb, rrda o ring relay driver output. connects an external centra lized ring generator to the sub- scriber loop. 31, 48 gpob, gpoa o general purpose output driver. used as a relay driver or as a second battery select pin when using a third battery supply. 32, 49 32, 49 batselb, batsela o battery voltage select pin. switches between high and low external battery supplies. 35 35 drx i receive pcm data. input data from pcm/gci bus. 36 36 dtx o transmit pcm data. output data to pcm/gci bus. 39 39 pclk i pcm bus clock. clock input for pcm/gci bus timing. 33 33 reset i reset. active low. hardware reset used to place all control registers in known state. an internal pulldown resistor asserts this pin low when not driven externally. 34 34 fsync i frame sync. 8 khz frame synchronization sign al for pcm/gci bus. may be short or long pulse format. 40 40 int o interrupt. maskable interrupt output. open drain output for wire-ored operation. 43 43 sclk i serial port bit clock input. controls serial data on sdo and latches data on sdi. 44 44 sdo o serial port data out. serial port control data output. 45 45 sdi i serial port data in. serial port control data input. pin number(s) symbol input/ output description SI3220 si3225
SI3220/si3225 rev. 1.0 99 46 46 sdithru o serial data daisy chain. enables multiple devices to use a single cs for serial port con- trol. connect sdithru pin from master device to sdi pin of slave device. an internal pullup resistor holds this pin high dur- ing idle periods. 47 47 cs i chip select. active low. when inactive, sclk and sdi are ignored, and sdo is high impedance. when acti ve, serial port is operational. 53 blkrng i ring generator sensing input. senses ring-trip condition when using centralized ring genera- tor. connect to high side of ring sense resistor. shared by channels a and b. epad epad gnd exposed die paddle ground. connect to a low-impedance ground plane via top side pcb pad directly under the part. see package outlines: 64-pin tqfp for pcb pad dimensions. pin number(s) symbol input/ output description SI3220 si3225
SI3220/si3225 100 rev. 1.0 pin descriptions: si3200 pin #(s) symbol input/ output description 1 tip i/o tip output. connect to the tip lead of the subscriber loop. 2, 10, 11 nc ? no internal connection. do not connect to any electrical signal. 3 ring i/o ring output. connect to the ring lead of the subscriber loop. 4vbat? operating battery voltage. si3200 internal system battery supply. connect svbata/b pin from SI3220/ 25 and decouple with a 0.1 f/100 v filter capacitor. 5vbath? high battery voltage. connect to the system ringing batt ery supply. decouple with a 0.1 f/100 v filter capacitor. 6 vbatl ? low battery voltage. connect to lowest system battery supply for off-hook operation driving short loops. an internal diode prevents leakage current when operating from vbath. 7gnd? ground. connect to a low-impedance ground plane. 8vdd? supply voltage. main power supply for all in ternal circuitry. connect to a 3.3 v or 5 v supply. decouple locally with a 0.1 f/10 v capacitor. 9 batsel i battery voltage select. connect to the batsel pin of the SI3220 or si3225 through an external resistor to enable automatic battery switching. no connection is required when used with the si3225 in a single battery system configuration. si3200 16-lead soic (epad) 116 215 314 413 512 611 710 89 itipp therm iringp iringn nc nc batsel itipn tip nc ring vbath gnd vbatl vdd vbat
SI3220/si3225 rev. 1.0 101 12 iringn i negative ring current control. connect to the iringn lead of the SI3220 or si3225. 13 iringp i positive ring current drive. connect to the iringp lead of the SI3220 or si3225. 14 therm o thermal sensor. connect to therm pin of SI3220 or si3225. 15 itipn i negative tip current control. connect to the itipn lead of the SI3220 or si3225. 16 itipp i positive tip current control. connect to the itipp lead of the SI3220 or si3225. epad gnd exposed die paddle ground. for adequate thermal management, the exposed die paddle should be sol- dered to a pcb pad that is connected to low-impedance inner and/or back- side ground planes using multiple vias. see ?package outline: 16-pin esoic? for pcb pad dimensions. pin #(s) symbol input/ output description
SI3220/si3225 102 rev. 1.0 package outline: 64-pin tqfp figure 65 illustrates the package details for the dual proslic. table 51 lists the values for the dimensions shown in the illustration. figure 65. 64-pin thin quad flat package (tqfp) table 51. 64-pin package diagram dimensions symbol millimeters min nom max a? ?1.20 a1 0.05 ? 0.15 a2 0.95 1.00 1.05 d 12.00 bsc d1 10.00 bsc e 12.00 bsc e1 10.00 bsc l 0.45 0.60 0.75 e 0.50 bsc b 0.17 0.22 0.27 b1 0.17 0.20 0.23 d d1 e e1 1 16 a 17 32 33 48 49 64 bottom side exposed pad 6.0 x 6.0 mm e see detail a see detail b 0 min. 0.08/0.20 r l detail a gauge plane a2 a1 0-7 1.00 ref 0.08 r. min. 0.20 min. detail b 0.09/0.20 0.09/0.16 b b1 with lead finish base metal
SI3220/si3225 rev. 1.0 103 package outline: 16-pin esoic figure 66 illustrates the package details for the si3200. table 52 lists the va lues for the dimensions shown in the illustration. figure 66. 16-pin thermal enhanced small outline integrated circuit (esoic) package table 52. package diagram dimensions symbol millimeters typical* min max a1.351.75 3 a1 0.03 0.13 b.33.51 c.19.25 3 d 9.80 10.00 e3.804.00 e 1.27 bsc h5.806.20 h.25.50 l .40 1.27 ?0.10 0o 8o 3 *note: typical parameters are for information purposes only. e h a1 b c h l e see detail f detail f a 16 9 8 1 gauge plane 0.010 d seating plane bottom side exposed pad 2.3 x 3.6 mm weight: approximate device weight is 0.15 grams.
SI3220/si3225 104 rev. 1.0 silicon labs SI3220/25 su pport documentation ?an39: connecting the proslic to the w&g pcm-4? ?an55: dual proslic user guide? ?an58: SI3220/si3225 programmer's guide? ?an63: si322x coefficient generator user's guide? ?an64: dual proslic linc user guide? ?an68: 8-bit microcontroller board hardware reference guide? ?an71: SI3220/si3225 gr-909 testing? ?an73: SI3220/si3225 system d emonstration kit user's guide? ?an74: silinkps-evb user's guide? ?an75: dual proslic software interface? ?an86: ringing / ringtrip operation and architecture on the SI3220/si3225? ?an88: dual proslic line card design? ?an91: si3200 power offload circuit? ?an196: dual proslic digi tal impedance synthesis? SI3220ppt0-evb data sheet si3225ppt0-evb data sheet note: refer to www.silabs.com for a current list of support documents for this chipset.
SI3220/si3225 rev. 1.0 105 related parts part number description comments si3210 programmable cmos slic/codec with ringing/battery voltage generation integrated dynamic battery supply saves power and cost si3216 programmable wideband cmos slic/ codec with ringing/battery voltage gener- ation wideband codec with 16-bit, 16 khz sam- pling for enhanced audio quality. si3232 dual cmos programmable slics with line monitoring 4-wire differential audio interface; compati- ble with broadcom vob ics with integrated codecs. si3050/si3019 global voice/data daa globally-programmable fxo port; up to 5000 v isolation. si2456/si2433/ si2414 isomodem? with integrated global daa data rates from 300 bps up to 56 kbps; supports v.90, v.34, v.32 bis, and others si3000 voice band codec with microphone/ speaker driver 16-bits, 84 db dynamic range; direct dsp interface; 3:1 analog input mixer.
SI3220/si3225 106 rev. 1.0 document change list revision 0.91 to revision 0.95 table 1 on page 4 changed si3200 thermal impedance to 55 c/w changed si3200 continuous power dissipation limit to 1w modified note 3 table 3 on page 5 added notes 2 and 3 modified values for ivdd1-ivdd4 and ivbat table 4 on page 8 added notes 2 and 3 modified values for ivdd1-ivdd4 and ivbat table 5 on page 10 modified round trip group delay to 600 s max table 7 on page 13 modified monitor adc specifications table 8 on page 13 eliminated reference to vbat, vtip, and vring in note table 13 on page 17 changed fsync jitter tolerance to pclk period jitter to l e r a n c e changed minimum fsync pulse width spec to tp/2 table 14 on page 19 changed minimum fsync pulse width spec to tp/2 figure 11 on page 24 modified transmit path block flow figure 12 on page 25 modified names of battery supply pins table 18 on page 32 corrected mnemonic of rlycon register "linefeed calibration" on page 35 modified calibration sequence modified operating state requirement to open state "power monitoring and power fault detection" on page 35 eliminated reference to si3200 on-chip thermal diode corrected transistor power equations added note requiring connection of therm pin when using si3200 modified equation for plpfxx modified pthxx and plpfxx examples added value for thermal for si3200 table 21 on page 39 added pth12 range and resolution for si3200 mode modified psum range and resolution modified bit range for plpf12-plpf56 "loop closure detection" on page 42 modified equation for lcrlpf "ground key detection" on page 43 modified equation for longlpf "automatic dual battery switching" on page 40 modified equation for batlpf figure 20 on page 41 modified circuit schematic and battery supply terminal names table 28 on page 47 added vrngng, irngng, and speedupr registers to table "ringing generation" on page 46 corrected equation results for sinusoidal ringing coefficients added ?internal unbalanced ringing? functional description corrected equations for trapezoidal ringing corrected equation for ringof corrected equations for ringing current consumption figure 31 on page 56 modified figure to show absolute tip, ring voltages "two-wire impedance synthesis" on page 58 corrected reference to za and zd blocks in figure 11 removed reference to 600w initial setting following reset table 36 on page 63 corrected lsb size for osc1ta register added note for lsb size in fsk mode figure 40 on page 68 added spi clock line to diagram "system clock generation" on page 67 added note describing requirement for pclk and fsync to be low at power-up ?8-bit control register summary?, on page 90 eliminated register summary table. refer to ?an58: SI3220/si3225 programmer?s guide?. ?16-bit ram address summary?, on page 94 eliminated ram address summary table. refer to ?an58: SI3220/si3225 programmer?s guide?. "package outline: 16-pin esoic" on page 103 changed a1 specification to .076 ref. revision 0.95 to revision 0.96 table 1, ?absolute maximum ratings and thermal information 1 ,? on page 4 added new items fixed miscellaneous typos added new section, "txeq /rxeq equalizer blocks" on page 67. "spi control interface" on page 68 added text.
SI3220/si3225 rev. 1.0 107 revision 0.96 to revision 1.0 the following changes are specific to rev. g of the SI3220/25 silicon: figure 21 on page 42: added cmh input to isp block. added iq1, iq2, iq5 and iq6 inputs to isp block. showed iloop as output of isp block. "loop closure detection" on page 42: added iloop equation and explanatory text. "ground key detection" on page 43: added i long equation and explanatory text. added table 25, ?settings for ground key example,? on page 44. added table 26, ?state transitions during ground key detection,? on page 44. "txeq/rxeq equalizer blocks" on page 67. removed note concerning txeqco0 coefficient. table 49 on page 90: added ?mirrored register bit(s)? column. the following changes are corrections and omis- sions to rev. 0.96: "dual proslic? selection guide" on page 2 added lead-free packages. table 6, ?linefeed characteristics,? on page 12 corrected r loop specification. table 12, ?switching characteristics?spi,? on page 16: added td1, td4 and tcs. changed tsu1 from 15ns. (min.) to 25ns. (min.). figure 1, ?spi timing diagram,? on page 16: added td1 and tcs. figures 7, 8, 9, and 10 on pages 21?23: corrected y-axis labels figure 11, ?ac signal path block diagram for a single channel,? on page 24: corrected digital impedance synthesis block (zd) location. correctly labeled analog impedance synthesis disable switch (zsdis). deleted modem tone detection block from the rx path. figure 12, ?SI3220 application circuit using dual battery supply,? on page 25: added resistors r20, r21, r22, r23, r24 and 25 figure 13, ?si3225 application circuit using centralized ringer and secondary battery supply,? on page 26: added resistors r23, r24, r25, r26, r27 and r28. table 15, ?SI3220 + si3200 external component values,? on page 27 added resistors r20?r25. table 16, ?si3225 + si3200 external component values,? on page 27 added resistors r23?r28. "adaptive linefeed" on page 32 improved text describing loop start and ground start operation. replaced figures 16, 17, and 18 with new figure 16 and figure 17. figure 41, ?spi daisy-chain mode,? on page 70: added missing connection between cpu sdo pin and dual proslic sdi pin. "silicon labs si 3220/25 support do cumentation" on page 104: added an88: dual proslic line card design. added an91: si3200 power offload circuit. added an196: dual proslic digital impedance synthesis deleted duplicate ordering guide from back of document.
SI3220/si3225 108 rev. 1.0 contact information silicon laboratories inc. 4635 boston lane austin, tx 78735 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 email: productinfo@silabs.com internet: www.silabs.com silicon laboratories, silicon labs, and prosli c are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademark s or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. a dditionally, silicon laboratorie s assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon labor atories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

▲Up To Search▲

Price & Availability of SI3220

	To Download SI3220 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .