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ez-usb series 2100 trm v1.8 table of contents i ez-usb series 2100 technical reference manual table of contents 1 introducing ez-usb ...................................................................... 1-1 1.1 introduction ............................................................................................. 1-1 1.2 ez-usb block diagrams ....................................................................... 1-2 1.3 the usb specification ........................................................................... 1-3 1.4 tokens and pids ..................................................................................... 1-4 1.5 host is master ......................................................................................... 1-5 1.5.1 receiving data from the host .................................................. 1-6 1.5.2 sending data to the host ......................................................... 1-6 1.6 usb direction ......................................................................................... 1-6 1.7 frame ...................................................................................................... 1-6 1.7.1 bulk transfers .......................................................................... 1-7 1.7.2 interrupt transfers ................................................................... 1-7 1.8 ez-usb transfer types ......................................................................... 1-7 1.8.1 isochronous transfers ............................................................. 1-8 1.8.2 control transfers ..................................................................... 1-8 1.9 enumeration ............................................................................................ 1-9 1.10 the usb core ....................................................................................... 1-10 1.11 ez-usb microprocessor ...................................................................... 1-11 1.12 renumeration ? ................................................................................... 1-12 1.13 ez-usb endpoints ............................................................................... 1-12 1.13.1 ez-usb bulk endpoints ......................................................... 1-13 1.13.2 ez-usb control endpoint zero ............................................ 1-13 1.13.3 ez-usb interrupt endpoints ................................................. 1-14 1.13.4 ez-usb isochronous endpoints ............................................ 1-14 1.14 fast transfer modes ............................................................................. 1-14 1.15 interrupts ............................................................................................... 1-15 1.16 reset and power management .............................................................. 1-15 1.17 ez-usb product family ....................................................................... 1-16 1.18 summary of an2122, an 2126 features ............................................. 1-16 1.19 revision id ........................................................................................... 1-17
ii table of contents ez-usb series 2100 trm v1.8 1.20 pin descriptions .................................................................................... 1-18 2 ez-usb cpu .................................................................................. 2-1 2.1 introduction ............................................................................................. 2-1 2.2 8051 enhancements ................................................................................ 2-1 2.3 ez-usb enhancements .......................................................................... 2-2 2.4 ez-usb register interface ..................................................................... 2-2 2.5 ez-usb internal ram ........................................................................... 2-3 2.6 i/o ports .................................................................................................. 2-3 2.7 interrupts ................................................................................................. 2-4 2.8 power control ......................................................................................... 2-5 2.9 sfrs ........................................................................................................ 2-6 2.10 internal bus ............................................................................................. 2-7 2.11 reset ........................................................................................................ 2-7 3 ez-usb memory ............................................................................ 3-1 3.1 introduction ............................................................................................. 3-1 3.2 8051 memory .......................................................................................... 3-2 3.3 expanding ez-usb memory ................................................................. 3-4 3.4 cs# and oe# signals .............................................................................. 3-5 3.5 ez-usb rom versions ......................................................................... 3-7 4 ez-usb input/output ................................................................... 4-1 4.1 introduction ............................................................................................. 4-1 4.2 io ports ................................................................................................... 4-2 4.3 io port registers ..................................................................................... 4-5 4.4 i 2 c controller .......................................................................................... 4-6 4.5 8051 i 2 c controller ................................................................................. 4-6 4.5.1 start ...................................................................................... 4-8 4.5.2 stop ........................................................................................ 4-8 4.6 control bits ............................................................................................. 4-8 4.6.1 lastrd ................................................................................... 4-9 4.6.2 done ....................................................................................... 4-9 4.6.3 ack .......................................................................................... 4-9 4.7 status bits ............................................................................................... 4-9 4.7.1 berr ...................................................................................... 4-10 4.7.2 id1, id0 ................................................................................. 4-10 4.8 sending i 2 c data .................................................................................. 4-10 4.9 receiving i 2 c data ............................................................................... 4-11 4.10 i 2 c boot loader .................................................................................... 4-12
ez-usb series 2100 trm v1.8 table of contents iii 5 ez-usb enumeration and renumeration ? ? ? ? ...............................5-1 5.1 introduction ............................................................................................. 5-1 5.2 the default usb device ........................................................................ 5-2 5.3 ez-usb core response to ep0 device requests .................................. 5-4 5.4 firmware load ........................................................................................ 5-5 5.5 enumeration modes ................................................................................ 5-7 5.6 no serial eeprom ................................................................................ 5-8 5.7 serial eeprom present, first byte is 0xb0 .......................................... 5-9 5.8 serial eeprom present, first byte is 0xb2 ........................................ 5-10 5.9 renumeration ? ................................................................................... 5-11 5.10 multiple renumerations ? ................................................................... 5-13 5.11 default descriptor ................................................................................. 5-13 6 ez-usb bulk transfers ................................................................. 6-1 6.1 introduction ............................................................................................. 6-1 6.2 bulk in transfers ................................................................................... 6-4 6.3 interrupt transfers .................................................................................. 6-5 6.4 ez-usb bulk in example ..................................................................... 6-5 6.5 bulk out transfers ............................................................................... 6-6 6.6 endpoint pairing ..................................................................................... 6-8 6.7 paired in endpoint status ....................................................................... 6-9 6.8 paired out endpoint status ................................................................. 6-10 6.9 using bulk buffer memory .................................................................. 6-10 6.10 data toggle control ............................................................................. 6-11 6.11 polled bulk transfer example .............................................................. 6-14 6.12 enumeration note ................................................................................. 6-15 6.13 bulk endpoint interrupts ...................................................................... 6-16 6.14 interrupt bulk transfer example .......................................................... 6-17 6.15 enumeration note ................................................................................. 6-22 6.16 the autopointer .................................................................................... 6-23 7 ez-usb endpoint zero .................................................................. 7-1 7.1 introduction ............................................................................................. 7-1 7.2 control endpoint ep0 ............................................................................. 7-2 7.3 usb requests ......................................................................................... 7-5 7.3.1 get status ................................................................................. 7-7 7.3.2 set feature ............................................................................. 7-10 7.3.3 clear feature ......................................................................... 7-12 7.3.4 get descriptor ....................................................................... 7-12
iv table of contents ez-usb series 2100 trm v1.8 7.3.4.1 get descriptor-device ...............................................................7-14 7.3.4.2 get descriptor-configuration ....................................................7-15 7.3.4.3 get descriptor-string ................................................................7-16 7.3.5 set descriptor ........................................................................ 7-16 7.3.6 set configuration ................................................................... 7-19 7.3.7 get configuration .................................................................. 7-19 7.3.8 set interface ........................................................................... 7-20 7.3.9 get interface .......................................................................... 7-21 7.3.10 set address ............................................................................. 7-21 7.3.11 sync frame ............................................................................ 7-22 7.3.12 firmware load ...................................................................... 7-23 8 ez-usb isochronous transfers .................................................... 8-1 8.1 introduction ............................................................................................. 8-1 8.1.1 initialization ............................................................................. 8-2 8.2 isochronous in transfers ........................................................................ 8-2 8.2.1 in data transfers .................................................................... 8-3 8.3 isochronous out transfers .................................................................... 8-3 8.3.1 initialization ............................................................................. 8-4 8.3.2 out data transfer .................................................................. 8-4 8.4 setting isochronous fifo sizes ............................................................. 8-5 8.5 isochronous transfer speed .................................................................... 8-8 8.6 fast transfers .......................................................................................... 8-9 8.6.1 fast writes ............................................................................. 8-10 8.6.2 fast reads .............................................................................. 8-11 8.7 fast transfer timing ............................................................................ 8-11 8.7.1 fast write waveforms ........................................................... 8-12 8.7.2 fast read waveforms ............................................................ 8-13 8.8 fast transfer speed .............................................................................. 8-14 8.8.1 disable iso ............................................................................ 8-15 8.9 other isochronous registers ................................................................. 8-15 8.9.1 zero byte count bits .............................................................. 8-16 8.10 iso in response with no data ............................................................ 8-17 8.11 using the isochronous fifos ............................................................... 8-17 9 ez-usb interrupts ......................................................................... 9-1 9.1 introduction ............................................................................................. 9-1 9.2 usb core interrupts ............................................................................... 9-1 9.3 wakeup interrupt .................................................................................... 9-2 9.4 usb signaling interrupts ........................................................................ 9-4
ez-usb series 2100 trm v1.8 table of contents v 9.5 sutok, sudav interrupts ................................................................... 9-8 9.6 sof interrupt .......................................................................................... 9-9 9.7 suspend interrupt .................................................................................... 9-9 9.8 usb reset interrupt ............................................................................ 9-9 9.9 bulk endpoint interrupts ........................................................................ 9-9 9.10 usb autovectors .................................................................................. 9-10 9.11 autovector coding ................................................................................ 9-11 9.12 i 2 c interrupt .......................................................................................... 9-13 9.13 in bulk nak interrupt - (an2122/an2126 only) ............................... 9-13 9.14 i 2 c stop complete interrupt - (an2122/an2126 only) .................... 9-15 10 ez-usb resets .............................................................................. 10-1 10.1 introduction ........................................................................................... 10-1 10.2 ez-usb power-on reset (por) .......................................................... 10-1 10.3 releasing the 8051 reset ...................................................................... 10-3 10.3.1 ram download ...................................................................... 10-4 10.3.2 eeprom load ...................................................................... 10-4 10.3.3 external rom ........................................................................ 10-4 10.4 8051 reset effects ................................................................................ 10-4 10.5 usb bus reset ...................................................................................... 10-5 10.6 ez-usb disconnect ............................................................................. 10-7 10.7 reset summary ..................................................................................... 10-8 11 ez-usb power management ...................................................... 11-1 11.1 introduction ........................................................................................... 11-1 11.2 suspend ................................................................................................. 11-2 11.3 resume .................................................................................................. 11-3 11.4 remote wakeup .................................................................................... 11-4 12 ez-usb registers ......................................................................... 12-1 12.1 introduction ........................................................................................... 12-1 12.2 bulk data buffers ................................................................................. 12-3 12.3 isochronous data fifos ....................................................................... 12-4 12.4 isochronous byte counts ...................................................................... 12-6 12.5 cpu registers ....................................................................................... 12-8 12.6 port configuration ................................................................................ 12-9 12.7 input-output port registers ................................................................ 12-11 12.8 230-kbaud uart operation - an2122, an2126 ............................. 12-14 12.9 isochronous control/status registers ................................................. 12-14 12.10 i 2 c registers ....................................................................................... 12-16
vi table of contents ez-usb series 2100 trm v1.8 12.11 interrupts ............................................................................................. 12-19 12.12 endpoint 0 control and status registers ............................................ 12-29 12.13 endpoint 1-7 control and status registers ......................................... 12-31 12.14 global usb registers ......................................................................... 12-37 12.15 fast transfers ...................................................................................... 12-46 12.16 setup data ........................................................................................ 12-49 12.17 isochronous fifo sizes ...................................................................... 12-50 13 ez-usb ac/dc parameters ....................................................... 13-1 13.0.1 absolute maximum ratings ................................................... 13-1 13.0.2 operating c onditions ............................................................ 13-1 13.0.3 dc characteristics ................................................................ 13-1 13.1 electrical characteristics ...................................................................... 13-1 13.1.1 ac electrical characteristics ................................................ 13-2 13.1.2 general memory timing ........................................................ 13-2 13.1.3 program memory read ......................................................... 13-2 13.1.4 data memory read ................................................................ 13-2 13.1.5 data memory write ............................................................... 13-3 13.1.6 fast data write ..................................................................... 13-3 13.1.7 fast data read ...................................................................... 13-3 14 ez-usb packaging ....................................................................... 14-1 14.1 44-pin pqfp package ........................................................................... 14-1 14.2 80-pin pqfp package ........................................................................... 14-3 14.3 48-pin pqfp package ........................................................................... 14-5 appendix a: 8051 introduction ........................................................... a-1 a.1 introduction ............................................................................................ a-1 a.2 8051 features ......................................................................................... a-1 a.3 performance overview .......................................................................... a-2 a.4 software compatibility .......................................................................... a-3 a.5 803x/805x feature comparison ............................................................. a-4 a.5.1 serial ports ..............................................................................a-5 5.1.1 timer 2 .....................................................................................a-5 5.1.2 timed access protection ..........................................................a-5 5.1.3 watchdog timer .......................................................................a-5 a.6 8051 core/ds80c320 differences ........................................................ a-5 appendix b: 8051 architectural overview .......................................... b-1 b.1 introduction .............................................................................................b-1 b.1.1 memory organization ..............................................................b-2
ez-usb series 2100 trm v1.8 table of contents vii b.1.1.1 program memory ...................................................b-2 b.1.1.2 external ram ........................................................b-2 b.1.1.3 internal ram .........................................................b-2 b.1.2 instruction set ..........................................................................b-3 b.1.3 instruction timing ..................................................................b-10 b.1.4 cpu timing ...........................................................................b-11 b.1.5 stretch memory cycles (wait states) ....................................b-11 b.1.6 dual data pointers ................................................................b-12 b.1.7 special function registers ....................................................b-13 appendix c: 8051 hardware descri ption ............................................ c-1 c.1 introduction .............................................................................................c-1 c.2 timers/counters ......................................................................................c-1 c.2.1 803x/805x compatibility ..........................................................c-1 c.2.2 timers 0 and 1 .........................................................................c-2 c.2.2.1 mode 0 ...................................................................c-2 c.2.2.2 mode 1 ...................................................................c-3 c.2.2.3 mode 2 ...................................................................c-6 c.2.2.4 mode 3 ...................................................................c-7 c.2.3 timer rate control ..................................................................c-8 c.2.4 timer 2 .....................................................................................c-9 c.2.4.1 timer 2 mode control .........................................c-10 c.2.5 16-bit timer/counter mode ...................................................c-10 c.2.5.1 6-bit timer/counter mode with capture ............c-12 c.2.6 16-bit timer/counter mode with auto-reload .....................c-12 c.2.7 baud rate generator mode ...................................................c-13 c.3 serial interface ......................................................................................c-14 c.3.1 803x/805x compatibility ........................................................c-15 c.3.2 mode 0 ...................................................................................c-15 c.3.3 mode 1 ...................................................................................c-21 c.3.3.1 mode 1 baud rate ...............................................c-21 c.3.3.2 mode 1 transmit ..................................................c-24 c.3.4 mode 1 receive ......................................................................c-24 c.3.5 mode 2 ...................................................................................c-26 c.3.5.1 mode 2 transmit ..................................................c-27 c.3.5.2 mode 2 receive ...................................................c-27 c.3.6 mode 3 ...................................................................................c-29 c.3.7 multiprocessor communications ...........................................c-30 c.3.8 interrupt sfrs ........................................................................c-30
viii table of contents ez-usb series 2100 trm v1.8 c.4 interrupt processing ..............................................................................c-36 c.4.1 interrupt masking ..................................................................c-37 c.4.2 interrupt priorities .................................................................c-38 c.4.3 interrupt sampling .................................................................c-39 c.4.4 interrupt latency ...................................................................c-40 c.4.5 single-step operation ............................................................c-40 c.5 reset ......................................................................................................c-40 c.5.1 idle mode ...............................................................................c-41 c.6 power saving modes ............................................................................c-41
ix t a b le of c o nt e n t s e z - u s b s e r i e s 2 1 00 t r m v1 . 8 f i gu r es figure 1-1. an2131s (44 pin) si m plified block diagra m .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . 1-2 figure 1-2. an2131q (80 p i n ) simpli f ied block diagra m .......................................... . 1-3 figure 1-3. usb p a c ket s ............................................................................................... . 1-4 figure 1-4. t wo b ulk transfers, in and ou t ............................................................. . 1-7 figure 1-5. an interrupt t ran s f e r ................................................................................. . 1-7 figure 1-6. an isochronous t r ansfe r ............................................................................ . 1-8 figure 1-7. a control t ransfe r ..................................................................................... . 1-8 figure 1-8. what the si e doe s ................................................................................... . 1-10 figure 1-9. 80-pin p q fp packa g e (an2131q ) .......................................................... . 1-18 figure 1-10. 44-pin p q fp package with p o r t b (an2121s, an2122s, and a n2131 s ) ....................................................................................................... . 1-19 figure 1-11. 44-pin package with da t a b u s (an2125s, an2126s, AN2135S, and a n213 6 ........................................................................................................... . 1-20 figure 1-12. 48-pi n tqfp packa g e (an2122t ) ........................................................ . 1-21 figure 1-13. 48-pin p q fp packa g e (a n 2126t ) ........................................................ . 1-22 figure 2-1. 8051 r egister s ............................................................................................ . 2-3 figure 3-1. e z-u s b 8-kb memory m ap - add r e s s es a r e in hexadecima l ................. . 3-1 figure 3-2. e z-u s b 4-kb memory m ap - add r e s s es a r e in hexadecima l ................. . 3-1 figure 3-3. unused bulk endpoint bu f fers ( shaded ) used as data m e mor y .............. . 3-3 figure 3-4. e z-u s b m emory map with ea= 0 ............................................................ . 3-4 figure 3-5. e z-u s b m emory map with ea= 1 ............................................................ . 3-6 figure 3-6. 8 - kb rom, 2-kb r a m versio n . . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . ... . 3-7 figure 3-7. 3 2 - kb rom, 4-kb r a m versio n . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . 3-8 figure 4-1. e z-u s b input/output p i n .......................................................................... . 4-2 figure 4-2. alternate function i s an o u t pu t ............................................................ . 4-4 figure 4-3. alternate function i s an inpu t ................................................................ . 4-4 figure 4-4. regi s te r s a s soci a t ed with po r t s a , b, and c ......................................... . 4-5 figure 4-5. general i 2 c t ran s f e r . . .. . . .. . . .. . . .. . . .. . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . . . 4-6 figure 4-6. general f c t r an s fe r ................................................................................... . 4-7 figure 4-7. fc r egister s ............................................................................................... . 4-8 figure 5-1. usb control and stat u s re g i ste r ............................................................. . 5-11 figure 5-2. disconne c t pin logi c ............................................................................... . 5-12 figure 5-3. typic a l disconnect c i r cui t (discoe=1 ) ................................................ . 5-12 figure 6-1. t wo bulk transfers, in and ou t .......................................................... . 6-1 figure 6-2. regi s te r s a s soci a t ed with bulk endpoin t s ................................................ . 6-3 figure 6-3. anatomy of a bul k i n t ra n s f e r ................................................................. . 6-4 figure 6-4. anatomy of a bulk o u t t r a n sfe r ............................................................. . 6-7 figure 6-5. bulk endpoint toggle contro l ................................................................. . 6-11
ez-usb series 2100 trm v1.8 table of contents x figure 6-6. example code for a simple (polled) bulk transfer .............................. 6-14 figure 6-7. interrupt jump table ................................................................................. 6-18 figure 6-8. int2 interrupt vector ............................................................................... 6-19 figure 6-9. interrupt service routine (isr) for endpoint 6-out .............................. 6-19 figure 6-10. background program transfers endpoint 6-out data to endpoint 6-in ......................................................................................................... 6-20 figure 6-11. initialization routine ............................................................................... 6-21 figure 6-12. autopointer registers ............................................................................. 6-23 figure 6-13. use of the autopointer ............................................................................ 6-24 figure 6-14. 8051 code to transfer external data to a bulk in buffer ..................... 6-25 figure 7-1. a usb control transfer (this one has a data stage) .............................. 7-2 figure 7-2. the two interrupts associated with ep0 control transfers ............... 7-3 figure 7-3. registers associated with ep0 control transfers ...................................... 7-4 figure 7-4. data flow for a get_status request ........................................................... 7-7 figure 7-5. using the setup data pointer (sudptr) for get_descriptor requests .. 7-13 figure 8-1. ez-usb isochronous endpoints 8-15 ......................................................... 8-1 figure 8-2. isochronous in endpoint registers ............................................................ 8-2 figure 8-3. isochronous out registers ........................................................................ 8-4 figure 8-4. fifo start address format ......................................................................... 8-5 figure 8-5. assembler translates fifo sizes to addresses .......................................... 8-7 figure 8-6. 8051 code to transfer data to an isochronous fifo (in8data) ............ 8-8 figure 8-7. 8051 movx instructions ............................................................................ 8-9 figure 8-8. fast transfer, ez-usb to outside memory ............................................. 8-10 figure 8-9. fast transfer, outside memory to ez-usb ............................................. 8-11 figure 8-10. the fastxfr register controls frd# and fwr# strobes ................. 8-11 figure 8-11. fast write timing ................................................................................... 8-12 figure 8-12. fast read timing .................................................................................... 8-13 figure 8-13. 8051 code to transfer 640 bytes of external data to an isochronous in fifo ................................................................................................................... 8-14 figure 8-14. isoctl register .................................................................................... 8-15 figure 8-15. zbcout register .................................................................................. 8-16 figure 9-1. ez-usb wakeup interrupt ......................................................................... 9-2 figure 9-2. usb interrupts ............................................................................................ 9-4 figure 9-3. the order of clearing interrupt requests is important .............................. 9-6 figure 9-4. ez-usb interrupt registers ........................................................................ 9-7 figure 9-5. sutok and sudav interrupts ................................................................. 9-8 figure 9-6. a start of frame (sof) packet .................................................................. 9-9 figure 9-7. the autovector mechanism in action ...................................................... 9-12 figure 9-8. i 2 c interrupt enable bits and registers .................................................... 9-13 figure 9-9. in bulk nak interrupt requests register ............................................... 9-14 figure 9-10. in bulk nak interrupt enables register ............................................... 9-14 figure 9-11. i 2 c mode register ................................................................................... 9-15
xi table of contents ez-usb series 2100 trm v1.8 figure 9-12. i 2 c control and status register .............................................................. 9-15 figure 9-13. i 2 c data ................................................................................................... 9-15 figure 10-1. ez-usb resets ....................................................................................... 10-1 figure 11-1. suspend-resume control ........................................................................ 11-1 figure 11-2. ez-usb suspend sequence .................................................................... 11-2 figure 11-3. ez-usb resume sequence .................................................................... 11-3 figure 11-4. usb control and status register ............................................................ 11-4 figure 12-1. register description format ................................................................... 12-2 figure 12-2. bulk data buffers ................................................................................... 12-3 figure 12-3. isochronous data fifos ......................................................................... 12-4 figure 12-4. isochronous byte counts ........................................................................ 12-6 figure 12-5. cpu control and status register ............................................................ 12-8 figure 12-6. io port configuration registers ............................................................. 12-9 figure 12-7. output port configuration registers ..................................................... 12-11 figure 12-8. pinsn registers .................................................................................... 12-12 figure 12-9. output enable registers ........................................................................ 12-13 figure 12-10. 230-kbaud uart operat ion register ............................................... 12-14 figure 12-11. isochronous out endpoint error register ........................................ 12-14 figure 12-12. isochronous control register .............................................................. 12-15 figure 12-13. zero byte count register ................................................................... 12-15 figure 12-14. i 2 c transfer registers ......................................................................... 12-16 figure 12-15. i 2 c mode register ............................................................................... 12-18 figure 12-16. interrupt vector register .................................................................... 12-19 figure 12-17. in/out interrupt request (irq) registers ........................................ 12-20 figure 12-18. usb interrupt request (irq) registers .............................................. 12-21 figure 12-19. in/out interrupt enable registers .................................................... 12-23 figure 12-20. usb interrupt enable registers .......................................................... 12-24 figure 12-21. breakpoint and autovector register ................................................... 12-26 figure 12-22. in bulk nak interrupt request register ........................................... 12-27 figure 12-23. in bulk nak interrupt enable register ............................................. 12-27 figure 12-24. in/out interrupt enable registers .................................................... 12-28 figure 12-25. port configuration registers ............................................................... 12-29 figure 12-26. in control and status registers .......................................................... 12-32 figure 12-27. in byte count registers ..................................................................... 12-34 figure 12-28. out control and status registers ...................................................... 12-35 figure 12-29. out byte count registers ................................................................. 12-36 figure 12-30. setup data pointer high/low registers ............................................. 12-37 figure 12-31. usb control and status registers ...................................................... 12-38 figure 12-32. data toggle control register ............................................................. 12-40 figure 12-33. usb frame count high/low registers .............................................. 12-41 figure 12-34. function address register .................................................................. 12-42 figure 12-35. usb endpoint pairing register .......................................................... 12-43
e z - u s b s e r ie s 2 1 00 t rm v 1 . 8 t a b l e o f c o n t e n ts x i i figure 12-36. i n / o u t v alid bi t s registe r .............................................................. . 12-44 figure 12-37. i sochronous i n/out endpoint valid bits r e g i ste r .......................... . 12-45 figure 12-38. fast t r ansfer control registe r ........................................................... . 12-46 figure 12-39. auto pointer register s ....................................................................... . 12-48 figure 12-40. s e tup data buf f e r ........................................................................... . 12-49 figure 12-41. s e tup data buf f e r ........................................................................... . 12-50 figure 13-1. external memory timing ....................................................................... . 13-4 figure 13-2. program m emory r e ad timin g ............................................................. . 13-4 figure 13-3. data memory r ead timin g ................................................................... . 13-5 figure 13-4. data memory writ e timin g .................................................................. . 13-5 figure 13-5. fast t r ansfer mode b l ock diag r a m ....................................................... . 13-6 figure 13-6. fast t r ansfer r e ad t iming [mode 00 ] ................................................... . 13-7 figure 13-7. fast t r ansfer w r i te t iming [mode 00 ] .................................................. . 13-7 figure 13-8. fast t r ansfer r e ad t iming [mode 01 ] ................................................... . 13-8 figure 13-9. fast t r ansfer w r i te t iming [ m ode 01 ] ............................................... . 13-8 figure 13-10. fast t r ansfer r e ad t iming [mode 10 ] ................................................. . 13-9 figure 13-11. fast t r ansfer w r i te t iming [mode 10 ] ................................................ . 13-9 figure 13-12. fast t r ansfer r e ad t iming [mode 11 ] ............................................... . 13-10 figure 13-13. fast t r ansfer w r i te t iming [mode 11 ] .............................................. . 13-10 figure 14-1. 4 4 -pi n pq f p packag e (top view ) ........................................................ . 14-1 figure 14-2. 4 4 -pi n pq f p packag e (side view ) ........................................................ . 14-1 figure 14-3. 4 4 -pi n pq f p packag e (de t a il view ) ..................................................... . 14-2 figure 14-4. 8 0 -pi n pq f p packag e (top view ) ........................................................ . 14-3 figure 14-5. 8 0 -pi n pq f p packag e (side view ) ........................................................ . 14-3 figure 14-6. 8 0 -pi n pq f p packag e (de t a il view ) ..................................................... . 14-4 figure 14-7. 4 8 -pi n pq f p packag e (side view ) ........................................................ . 14-5 figure 14-8. 4 8 -pi n pq f p packag e (top view ) ........................................................ . 14-5 figure 14-9. 4 8 -pi n pq f p packag e (de t a il view ) ..................................................... . 14-6 figure a-1. comparativ e timing of 8051 a n d indu s try s tandard 805 1 ...................... . a-3 figure b-1. 8051 block dia g ra m . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . ... . b-1 figure b-2. internal ram organizatio n .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . . . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . ... . b-3 figure b-3. cpu t iming for single -cycle inst r uct i o n ................................................b-11 figure c-1. time r 0 /1 - modes 0 and 1 .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . . . c-3 figure c-2. time r 0 /1 - mode 2 . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . ..c-6 figure c-3. time r 0 - mode 3 . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . . . c-7 figure c-4. time r 2 - timer/ c ounter wi th c a ptur e . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . ..c-12 figure c-5. time r 2 - timer/ c ounter wi th auto reloa d .. . . .. . . . . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . ..c-13 figure c-6. time r 2 - ba u d ra t e generator m o d e . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . ... . c-14 figure c-7. ser i a l port mode 0 rece i ve timing - low speed operation . . .... . . .. . . .. . . .. . c-19 figure c-8. serial port mode 0 recei v e t i mi n g - high s peed operatio n .. . . .. . . .. . . .. . . . . c-20 figure c-9. serial port mode 0 transmit timing - low speed operatio n . . .. . . .. . . .. . . .. . c-20 figure c-10. serial port mode 0 transmit timing - high speed ope r a t io n .. . . .. . . .. . . . . c-21
xiii table of contents ez-usb series 2100 trm v1.8 figure c-11. serial port 0 mode 1 transmit timing ..................................................c-25 figure c-12. serial port 0 mode 1 receive timing ....................................................c-26 figure c-13. serial port 0 mode 2 transmit timing ..................................................c-28 figure c-14. serial port 0 mode 2 receive timing ....................................................c-28 figure c-15. serial port 0 mode 3 transmit timing ..................................................c-29 figure c-16. serial port 0 mode 3 receive timing ....................................................c-29
ez-usb series 2100 trm v1.8 table of contents xiv tables table 1-1. usb pids ..................................................................................................... 1-4 table 1-2. ez-usb series 2100 family ...................................................................... 1-16 table 1-3. ez-usb series 2100 pinouts by pin function ........................................... 1-23 table 2-1. ez-usb interrupts ....................................................................................... 2-4 table 2-2. added registers and bits ............................................................................. 2-6 table 4-1. io pin functions for portxcfg=0 and portxcfg=1 ............................ 4-3 table 4-2. strap boot eeprom address lines to these values ............................... 4-13 table 4-3. results of power-on i 2 c test .................................................................... 4-14 table 5-1. ez-usb default endpoints .......................................................................... 5-2 table 5-2. how the ez-usb core handles ep0 requests when renum=0 ............... 5-4 table 5-3. firmware download ..................................................................................... 5-5 table 5-4. firmware upload .......................................................................................... 5-6 table 5-5. ez-usb core action at power-up .............................................................. 5-7 table 5-6. ez-usb device characteristics, no serial eeprom ................................. 5-8 table 5-7. eeprom data format for b0 load ......................................................... 5-9 table 5-8. eeprom data format for b2 load ....................................................... 5-10 table 5-9. usb default device descriptor ................................................................. 5-13 table 5-10. usb default configuration descriptor .................................................... 5-14 table 5-11. usb default interface 0, alternate setting 0 descriptor ......................... 5-14 table 5-12. usb default interface 0, alternate setting 1 descriptor ......................... 5-15 table 5-13. usb default interface 0, alternate setting 1, interrupt endpoint descriptor ................................................................................................ 5-15 table 5-14. usb default interface 0, alternate setting 1, bulk endpoint descriptors .............................................................................................. 5-16 table 5-15. usb default interface 0, alternate setting 1, bulk endpoint descriptors .............................................................................................. 5-17 table 5-16. usb default interface 0, alternate setting 1, isochronous endpoint descriptors .............................................................................................. 5-18 table 5-17. usb default interface 0, alternate setting 2 descriptor ......................... 5-19 table 5-18. usb default interface 0, alternate setting 1, interrupt endpoint descriptor ................................................................................................ 5-19 table 5-19. usb default interface 0, alternate setting 2, bulk endpoint descriptors .............................................................................................. 5-20
xv table of contents ez-usb series 2100 trm v1.8 table 5-20. usb default interface 0, alternate setting 2, isochronous endpoint descriptors .............................................................................................. 5-21 table 6-1. ez-usb bulk, control, and interrupt endpoints ......................................... 6-1 table 6-2. endpoint pairing bits (in the usb pair register) ..................................... 6-8 table 6-3. ez-usb endpoint 0-7 buffer addresses ................................................... 6-10 table 6-4. 8051 int2 interrupt vector ....................................................................... 6-16 table 6-5. byte inserted by ez-usb core at location 0x45 if aven=1 .................. 6-16 table 7-1. the eight bytes in a usb setup packet ................................................... 7-5 table 7-2. how the 8051 handles usb device requests (renum=1) ........................ 7-6 table 7-3. get status-device (remote wakeup and self-powered bits) ..................... 7-8 table 7-4. get status-endpoint (stall bits) ................................................................... 7-8 table 7-5. get status-interface .................................................................................... 7-10 table 7-6. set feature-device (set remote wakeup bit) ........................................... 7-10 table 7-7. set feature-endpoint (stall) ....................................................................... 7-11 table 7-8. clear feature-device (clear remote wakeup bit) .................................... 7-12 table 7-9. clear feature-endpoint (clear stall) .......................................................... 7-12 table 7-10. get descriptor-device .............................................................................. 7-14 table 7-11. get descriptor-configuration ................................................................... 7-15 table 7-12. get descriptor-string ............................................................................... 7-16 table 7-13. set descriptor-device .............................................................................. 7-16 table 7-14. set descriptor-configuration ................................................................... 7-17 table 7-15. set descriptor-string ................................................................................ 7-17 table 7-16. set configuration ..................................................................................... 7-19 table 7-17. get configuration ..................................................................................... 7-19 table 7-18. set interface (actually, set alternate setting as for interface if) ......... 7-20 table 7-19. get interface (actually, get alternate setting as for interface if) ........ 7-21 table 7-20. sync frame ............................................................................................... 7-22 table 7-21. firmware download ................................................................................. 7-23 table 7-22. firmware upload ...................................................................................... 7-23 table 8-1. isochronous endpoint fifo starting address registers ............................. 8-6 table 8-2. addresses for rd# and wr# vs. isodisab bit ....................................... 8-15 table 9-1. ez-usb interrupts ....................................................................................... 9-1 table 9-2. 8051 jump instruction .............................................................................. 9-10 table 9-3. a typical usb jump table ....................................................................... 9-11 table 10-1. ez-usb states after power-on reset (por) ......................................... 10-2
ez-usb series 2100 trm v1.8 table of contents xvi table 10-2. ez-usb states after a usb bus reset ................................................... 10-6 table 10-3. effects of an ez-usb disconnect and re-connect .................................. 10-7 table 10-4. effects of various ez-usb resets (u means unaffected) .............. 10-8 table 12-1. bulk endpoint buffer memory addresses ............................................... 12-3 table 12-2. isochronous endpoint fifo register addresses ..................................... 12-4 table 12-3. isochronous endpoint byte count register addresses ............................ 12-6 table 12-4. io pin alternate functions ..................................................................... 12-10 table 12-5. control and status register addresses for endpoints 0-7 ..................... 12-31 table 12-6. isochronous fifo start address registers ............................................ 12-51 table 13-1. dc characteristics .................................................................................... 13-1 table 13-2. general memory timing .......................................................................... 13-2 table 13-3. program memory read ............................................................................ 13-2 table 13-4. data memory read ................................................................................... 13-2 table 13-5. data memory write .................................................................................. 13-3 table 13-6. fast data write ......................................................................................... 13-3 table 13-7. fast data read .......................................................................................... 13-3 table a-1. feature summary of 8051 core and common 803x/805x configurations a-4 table b-1. legend for instruction set table .................................................................b-4 table b-2. 8051 instruction set .....................................................................................b-5 table b-3. data memory stretch values .....................................................................b-12 table b-4. special function registers ........................................................................b-14 table b-5. special function register reset values ....................................................b-16 table b-6. psw register - sfr d0h ..........................................................................b-18 table c-1. timer/counter implementation comparison ...............................................c-2 table c-2. tmod register - sfr 89h ..........................................................................c-4 table c-3. tcon register - srf 88h ...........................................................................c-5 table c-4. ckcon register - srf 8eh .......................................................................c-8 table c-5. timer 2 mode control summary ..............................................................c-10 table c-6. t2con register - sfr c8h ......................................................................c-10 table c-7. serial port modes ......................................................................................c-15 table c-8. scon0 register - sfr 98h .......................................................................c-16 table c-9. scon1 register - sfr c0h ......................................................................c-18 table c-10. timer 1 reload values for common serial port mode 1 baud rates ....c-23 table c-11. timer 2 reload values for common serial port mode 1 baud rates ....c-24 table c-12. ie register - sfr a8h .............................................................................c-31
xvii table of contents ez-usb series 2100 trm v1.8 table c-13. ip register - sfr b8h .............................................................................c-32 table c-14. exif register - sfr 91h .........................................................................c-33 table c-15. eicon register - sfr d8h ....................................................................c-34 table c-16. eie register - sfr e8h ...........................................................................c-35 table c-17. eip register - sfr f8h ...........................................................................c-36 table c-18. interrupt natural vectors and priorities ..................................................c-37 table c-19. interrupt flags, enables, and priority control .........................................c-38 table c-20. pcon register - sfr 87h .......................................................................c-41
ez-usb series 2100 trm v1.8 table of contents xviii
ez-u s b s er i e s 2 1 0 0 t rm v 1.8 c h a p t e r 1 . i n tr o d u c i n g ez - usb p a g e 1-1 1 in t r oducing e z-usb like a well d esigned automobi l e or appl i ance, a u sb peri p h erals ou t w ar d simplicity hides intern a l complexi t y. th e r e s a lot going on und e r the hood o f a usb d e v i ce, which giv e s the u s e r a n ew level o f convenien c e. for example: ? a usb device c an be plugge d in anytime, even w h e n the p c is turned on. ? when the p c d e t e cts tha t a usb device has been plugge d in, it automatica l l y inter- rog a t e s the device to l e arn its capabilities and requirements. f r om th i s informa- tion, t h e pc automatically l oads the d e vices d river into the opera t ing system. when t h e device is unplugged, the op e r ating s y s t em automatical l y l o g s it off and unloads its driv e r. ? usb devices do not u se dip switch e s, jumpers, or confi g u r a tion p r o g rams. there is never an ir q , dma, m e m o r y , o r io confl i ct with a usb d evice. ? u sb expansion hub s make the bus available to dozens of d e vices. ? usb is fa s t enough for printers, cd-quality audio, a nd scanners. usb is defined in the universal s e rial bus specifi c a t i on version 1.1 ( h t tp: / /us b .org ) , a 268-page document that d e scribes all aspects of a u sb device in elabor a te detai l . this e z - u s b t echn i c al r e f e r en c e m anual d e scribes the e z -usb chip along with usb topics that should provide help in understanding the specification. the cypre s s semicondu c tor e z - usb is a compact integrated c ir c uit that provides a highly integrated solution fo r a usb peripheral devic e . th r ee key ez - u s b features are: ? the ez-usb family provides a soft (ram - ba s ed) solution that a llows unlimited configuration and upgra d es. ? the e z -usb fami l y de l i vers f ull usb thr oughpu t . d e s i g n s t h a t u s e e z - u s b are not limited by number of endpo i nts, buf f er sizes, or transfer s peeds. ? the e z -usb fami l y does much of the u sb housekeeping i n t he e z-usb core, simplifying code a nd accelerating the usb learn i n g curve. 1.1 i n t roduction
p a ge 1 - 2 c h a p t er 1 . in t r o d u c i n g e z - u s b e z - u s b s e r i e s 2 1 00 t r m v1 . 8 this chapt e r in t roduces some key usb conc e pts a n d termino l ogy that should m ake read- ing the r e st of this t echn i c al r e f e r en c e m anual e asie r . f i g u re 1 - 1 . a n 21 3 1 s (44 p i n) s i m p l i f i e d b l o c k diagram the cypre s s semicondu c tor e z - usb chip packs the intelli g ence r equired by a usb periph e r al int e rf a ce into a co m pact integrate d circuit. as figure 1 - 1 i l lustrates, an inte- g r a t ed usb t r ansceiver connects to the usb bus p i ns d+ a n d d-. a serial interface engine ( sie) decod e s and encod e s the serial d ata and performs erro r correct i on, b i t stuff- ing, and other signaling-level det a i ls r e quired by usb, and ultimately transfers data bytes to and f rom t h e usb i n t e rf a ce. the internal microp r oces s or is enhanced 8051 wi th fast exec u tion t ime a n d added fea- tu r e s . it u s es internal r a m for prog r a m and data st o rage, making the e z - u s b family a soft solution. the usb host downloads 8051 p r o g ram cod e and dev i c e personality into ram over the usb bus, and then the ez-u s b chip r e - conn e cts as the c u stom devi c e as defined by the loaded code. the e z - u s b family u s es an enhance d sie / u sb in t er f ace (call e d the usb core) which has the intelligence to func t ion as a f ull usb d evice ev e n before the 8051. the enhanced core s implifies 8051 code by imp l e me n ting much of t he usb protocol itself. e z - u s b chips operate at 3. 3 v. th i s simplifies t h e design of bus - powered usb d e vices, since the 5v power available in the usb c o n n ect o r (which the u s b s pe c if i cation allows to be as l o w a s 4.4v) can drive a 3.3v regu l ator to deliver clean is o l ated power to the ez- usb chip. 1.2 e z -usb b lock diagrams serial interface engine (sie) usb transceiver +5v gnd d+ d- usb connector bytes bytes io ports general purpose microprocessor usb interface program & data ram ez-usb
ez-usb series 2100 trm v1.8 chapter 1. introducing ez-usb page 1-3 figure 1-2. an2131q (80 pin) simplified block diagram figure 1-2 illustrates the an2131q, an 80-pin version of the ez-usb family. in addition to the 24 io pins, it contains a 16-bit address bus and an 8-bit data bus for external mem- ory expansion. a special fast transfer mode moves data directly between external logic and internal usb fifos. the fast transfer mode, along with abundant endpoint resources, allows the ez- usb family to support transfer bandwidths beyond the maximum required by the univer- sal serial bus specification version 1.1 . the universal serial bus specification version 1.1 is available on the internet at http:// usb.org . published in january 1998, the specification is the work of a f ounding commit- tee of seven industry heavyweights: compaq, dec, ibm, intel, microsoft, nec, and northern telecom. this impressive list of implementers secures usb as the low to medium speed pc connection met hod of the future. a glance at the usb specification makes it immediately apparent that usb is not nearly as simple as the customary serial or parallel port. the specification uses new terms like endpoint, isochr onous, and enumerati on, and finds new uses for old terms like con- figuration, interface, and interrupt. woven into the usb fabric is a software abstrac- tion model that deals with things such as pipes. the specification also contains detail about the connector types and wire colors. 1.3 the usb specification serial interface engine (sie) usb transceiver +5v gnd d+ d- usb connector bytes bytes io ports address bus data bus external memory, fifos, etc. general purpose microprocessor usb interface program & data ram ez-usb
p a ge 1 - 4 c h a p t er 1 . in t r o d u c i n g e z - u s b e z - u s b s e r i e s 2 1 00 t r m v1 . 8 in this manual, you wil l read statements like, whe n the host sends a n in token... or t h e devic e r esponds with an ac k . what do th e se t e rms mean? a u s b t r ansaction consists of data packe t s iden t ified by special c odes called p a cket ids or pids . a pi d signifies what kin d of packet is bei n g tr a n s mitted. there a re four pid t y p es, as s h ow n in t able1-1. f i g u r e 1 -3 . u s b p a c ket figur e 1-3 illu s t rates a u sb trans f er. packe t is an o u t token, indicated by the out p i d. the out token signi f i es t h at dat a from the host is a bou t t o b e t r a n s mitted over the bus. p a c ke t contains d a ta, as indicated by the d a ta1 pid. pac k e t is a handshake packet, sent b y the device u s ing the ack (acknowledge) p i d to s ignify to th e host tha t the devic e r eceived the data er r or-free. continuing wit h figure 1-3, a second trans a c tion begins with anothe r out toke n , fol- lowed by mo r e data , this time using th e d ata0 pid. fin a lly, the d e vice again indi- cates s u cc e ss by transmitt i ng th e ack pid in a hand s hake packe t . why two dat a p i d s, d at a 0 and dat a 1 ? its b ecau s e the usb a r ch i t e cts took error cor r e c t ion v ery s e ri o u s l y. as mentioned prev i ousl y , the ack handsha k e is a signal to the host th a t the p e riphera l r e ceived d a ta wi t hou t e r r o r ( t h e c r c p o r tion of the packet is used to det e ct er r o r s). but what if a handshake pack e t i t se l f is garbled in t r ansmission? t o de t ect this, ea c h side, host and de v ice mainta i ns a data toggle b it, which is toggled between data packet t r a ns f ers. t he state of t his internal togg l e bit is compared with the 1.4 t okens and pids t ab l e 1 - 1 . u s b pi d s p i d type p i d name t o k en d a ta i n, ou t , so f , s e t u p , d a t a 0 , d a t a1 ha n dshake a c k , na k , s t all sp e cial p re o u t a d d r e n d p c r c 5 token packet d a t a 1 payload data c r c 1 6 data packet a c k o u t a d d r e n d p c r c 5 token packet d a t a 0 payload data c r c 1 6 data packet a c k h/s pkt h/s pkt 1 2 3 4 5 6
ez-u s b s er i e s 2 1 0 0 t rm v 1.8 c h a p t e r 1 . i n tr o d u c i n g ez - usb p a g e 1-5 p i d that arrives with the data, eithe r d at a 0 o r da t a1. when se n d ing data, t he host or device se n d s alterna t i n g da t a 0 - dat a 1 pids. by c o m pari n g the da t a pid with the state o f the int e rnal t o g g le bit, the host or d e v i c e can d e tect a corrupted handsha k e packet. s e tu p tokens a r e unique to control transfers. they preface e ight bytes of data from which the periphe r a l dec o d es h o st de v i ce reques t s. so f tokens occur o n ce pe r mi l lisecond, denoting a us b f rame . there are three handsh a ke pid s : ack, nak , and s tall. ? ack means su c cess; the da t a w as recei v e d e r r o r -free. ? n a k means b u sy, try again. i t s tempting t o assume t hat nak me a ns error, but it doe s nt. a usb d e vice ind i cates an error b y not r espondin g . ? s t al l me a n s that something unf o r eseen went wrong (probably as a re s ult of mis- communicatio n or lac k of c ooperation betwe e n t h e softwar e a n d f i r mware w r i t e rs) . a dev i c e s ends the s t all han d shake to indicate that it do e snt und e rstand a devic e reques t , that something went wrong on the peripheral end, or that the h o st t r ied to a c ce s s a resource that i sn t t here . its like halt, but b ett e r, because usb provides a way to recove r from a stall. a pre (preamble) p id prec e d es a low-speed (1.5 m b p s ) usb tr a nsmission . the ez- usb famil y supports h i gh-speed (12 mbps) u s b t r a n s fer s only, so it i g n o res pr e packets and the sub s equent lo w - speed tra n s f e r. this is a fundament a l usb concept. ther e i s exactly one master in a usb system: the host compu t e r . usb devi c e s respond to ho s t re q u e s ts . usb devic e s ca nnot send in f orma- tion between them s e l v e s , a s they could if u s b were a p e er-to - p e er topo l ogy. actual l y, th e r e is one ca s e where a usb device ca n ini t i ate s ignaling without p r ompting f rom the host. a f t er being put into a l ow-power suspend mode by the host, a device can signal a remote wakeup. but tha t s the only way to yank the h o s t s chain . everything else happens be c ause the ho s t ma k es de v i ce requ e sts and the devi c e responds to them. there s an excelle n t reason for this h o st-centric m odel . the usb architects w ere keenly mindfu l of co s t, an d the best way to m a k e low-cost per i p h erals is to put most o f the sm a r t s 1.5 ho s t is m a ster
p a ge 1 - 6 c h a p t er 1 . in t r o d u c i n g e z - u s b e z - u s b s e r i e s 2 1 00 t r m v1 . 8 into the host s ide, the p c . i f usb h ad been defin e d as pe e r-to- p eer, every usb device would ha v e requ i red more intelligence, rais i n g cost. here a r e two important cons e quences of the ho s t is mas t e r concept: 1.5.1 receiving da t a f r om the host t o s end d a t a to a usb periph e r a l, the host issues an o ut token followed by the d ata. if the periphe r a l has space for the da t a, and a c c epts it wi thou t error, it r etu r ns an ack to the host. i f i t is b u s y , it instead s e nds a n a k . if i t find s a n e r ror, it sends nothing back. for the latte r two c ases, the ho s t r e -sends the d a ta at a l a t e r time. 1.5. 2 send i ng data to t h e host a usb device never spontan e ously s e nds d a ta to the h o st. neverthe l ess, in t h e ez-usb chip, there s nothing to s top the 8051 from loading data for the host into an endpoint bu f fer (sect i on 1.13, " e z -usb endpoints " ) and arming it fo r tra n s f e r. but the data will sit in th e buffer until the host se n d s an in token to t h a t particular endpoin t . i f the ho s t never s ends the in token, the data si t s there indefinately. once you a ccept that t he host is the bus m as t e r , i ts easy to remember u sb d irection: o u t me a ns from t h e host to the d e vice, and in m e ans from the device to the h o st. ez- usb nomen c latu r e us e s this naming convention. for example, an endpoint t hat sends data to the ho s t i s a n in endpoint. this can be confusing at first, b ecause the 805 1 sends data by loading an in endpoint bu f fe r , but keeping in mind th a t an 805 1 out is in to the host, it m a kes s ense. the usb host provides a t i me b a se to all usb device s by t r a n smi t ti n g a sof (start of f r ame) packe t every mi l l i second . the so f packet in c ludes an incrementing , 1 1 - bi t frame count. the 8051 ca n r ead th i s f ra m e coun t from two e z - usb registers. sof - ti m e has signif i c ance for isochronous endpoi n t s ; its the time that th e ping-ponging b u ffers switch pla c es. th e ez-usb core provides the 8051 with an sof interr u p t r e quest f o r ser v icing isochronous endpoint data. 1.6 usb dire c tion 1.7 f rame
ez-u s b s er i e s 2 1 0 0 t rm v 1.8 c h a p t e r 1 . i n tr o d u c i n g ez - usb p a g e 1-7 usb d e f ines four transfer type s . these match the requi r e ments of di f ferent d a t a types delivered over the bus. ( section 1 .13, " e z-u s b endpoint s " explains how the e z -usb f a m ily suppor t s t h e f o u r t ra n sfer type s .) 1.8. 1 bulk t ransfers f i g u r e 1 - 4 . t w o bu l k t ra n sf e r s , i n and out bulk data is bur s t y , traveling i n packet s of 8, 16 , 32 , o r 64 bytes . bulk dat a ha s guar a nteed accu r acy, due to an automatic re-try mec h a ni s m for erroneous data. t he host schedules bulk pa c kets when there is availab l e bus time. bulk transfers are typically used for p r inte r , s c anne r , or m odem data. bulk data h a s built-in flow control provided by hand- shake pac k e t s. 1.8.2 inter ru p t transfers f i g u r e 1- 5 . a n i n ter r u pt t r a n s f e r interrupt data is like bul k d ata, but exi s ts only for i n endpoints in the universa l s e r ial bus specifica t ion version 1.1. interrupt d ata c a n have packet sizes of 1-64 by t es. inter- rupt endpoints have an a s sociated polling interval that en s ures that they will b e pinged ( wil l r e ceive an in token) by the host on a regula r b asis. 1.8 e z -usb t ra n s f e r t yp e s i n a d d r e n d p c r c 5 token packet d a t a 1 payload data c r c 1 6 data packet a c k o u t a d d r e n d p c r c 5 token packet d a t a 0 payload data c r c 1 6 data packet a c k h/s pkt h/s pkt i n a d d r e n d p c r c 5 token packet d a t a 1 payload data c r c 1 6 data packet a c k h/s pkt
p a ge 1 - 8 c h a p t er 1 . in t r o d u c i n g e z - u s b e z - u s b s e r i e s 2 1 00 t r m v1 . 8 1.8.3 isochronou s t r ansfers f i g u re 1 - 6 . an i s o c h r on o u s t r an s f e r i sochronous data is time - critical and used for s t r e a ming data li k e audio and video . t ime o f delivery is the mo s t im p o rta n t requ i r emen t for isochronou s d a t a . i n every usb frame, a certain amount o f usb bandwidth is allocated to isochr onous tra n s f e r s. to li ghten the overhead, isochronous t ransfers have no handsh a ke (ack/na k / s t a l l ), and no retries. e rror detect i on is limited t o a 16 - bit crc. iso c h r onous tran s fers do not use the data tog- gle mechanism; isochronous d ata uses only th e d ata0 pid. 1.8.4 con t ro l t ransfers f igu r e 1-7 . a c o nt r ol t r a n s f e r contro l transfers a r e used to con f igure a n d send comm a nds to a d e v ice. bein g mis s ion critical , they employ the most exten s ive er r or checking u s b offers . control trans f ers are delivered on a b e st e f fo r t b a sis by the host ( be s t effort is defined by a s ix - s t ep pro c ess in the univ e rsal se r ial bus spe c i ficat i on v e rsion 1.1, section 5.5.4 ) . the host r e serves a part of eac h us b fram e tim e fo r contro l transfers. i n a d d r e n d p c r c 5 token packet d a t a 0 payload data c r c 1 6 data packet i n a d d r e n d p c r c 5 token packet d a t a 0 8 bytes setup data c r c 1 6 data packet a c k h/s pkt s e t u p a d d r e n d p c r c 5 token packet d a t a 1 payload data c r c 1 6 data packet a c k h/s pkt d a t a 1 o u t a d d r e n d p c r c 5 token packet c r c 1 6 data pkt a c k h/s pkt setup stage data stage (optional) status stage
ez-usb series 2100 trm v1.8 chapter 1. introducing ez-usb page 1-9 control transfers consist of two or three stages. the setup stage contains eight bytes of usb control data. an optional data stage contains more data, if required. the status (or handshake ) stage allows the device to indicate successful completion of a control operation. your computer is on. you plug in a usb device, and the windows ? cursor switches to an hourglass, and then back to a cursor. and magically, your device is c onne cted and its windows ? driver is loaded! anyone who has installed a sound card into a pc and had to configure countless jumpers, drivers, and io/interrupt/dma settings knows that a usb connection can be like a miracle. weve all heard about plug and play, but usb delivers the real thing. how does all this happen automatically? inside every usb device is a table of descrip- tors that are the sum total of the devices requirements and capabilities. when you plug into usb, the host goes through a sign-on sequence: 1. the host sends a get_descriptor/device request to address zero (devices must respond to address zero when first attached). 2. the device dutifully responds to this request by sending id data back to the host telling what it is. 3. the host sends the device a set_address request, which gives it a unique address to distinguish it from the other devices connected to the bus. 4. the host sends more get_descriptor requests, asking more device information. from this, it learns everything else about the device, like how many endpoints the device has, its power requirements, what bus bandwidth it requires, and what driver to load. this sign-on process is called enumeration . 1.9 enumeration
p a g e 1 - 1 0 c h a p t e r 1 . i n t r o d u c i n g ez - usb e z -usb s e r i e s 2 1 0 0 t r m v 1.8 f i gu r e 1 - 8 . w h a t t h e s i e d o e s every usb device h a s a serial interface e n g in e (sie). t he sie c onnects to the usb data lines d+ and d-, a n d del i v ers by t es to and from the usb de v ice. f igure 1-8 illustrates a usb bulk t r ans f e r , with time movi n g fro m left t o right . the s i e decodes th e packe t p i ds, performs e r ror ch e cking on the data using the transmitted crc bits, and delivers payload data to the u s b devic e . i f the sie encounters an e r ror in the data, it aut o m a t i cally indi- cates no r esponse instead of supplying a handshake p id. th i s i n s truc t s the host t o re- t r an s mit the d a t a at a l a ter time. bulk tran s f ers such as the one il l u strated in figure 1-8 ar e asynch r onou s , m e aning that they include a flow control mech a nism using ack a nd nak handsh a ke pids . the sie indicates busy to the host by s ending a nak handshake p a c ket. when t h e peripheral device has s u cc e ssfu l ly t r a n s ferred the data, it com m a nds t he sie to send an ack hand- shake pac k e t, indi c a ting su c ce s s. t o s end d a t a to the host, the s ie accepts bytes and control signals from the usb device, formats it for usb t ransf e r, a n d sends it over the two-wir e u sb. beca u se the usb u s e s a self-clocking data f orm a t ( n rzi), t h e sie also inse r ts bits at a ppropriate places in the bit stream to guarant e e a certain number of transitions in the s erial dat a . this is called bit stu f fing, and is transparentl y handled by t h e sie. 1.10 the usb core serial interface engine (sie) d+ d- usb tranceiver o u t a d d r e n d p c r c 5 token packet d a t a 1 payload data c r c 1 6 data packet a c k o u t a d d r e n d p c r c 5 token packet d a t a 0 payload data c r c 1 6 data packet a c k h/s pkt payload data payload data a c k h/s pkt
ez-u s b s er i e s 2 1 0 0 t rm v 1.8 c h a p t e r 1 . i n tr o d u c i n g ez - usb p a g e 1 - 11 one o f the mo s t im p o rtan t f eat u res of t h e e z-usb fami l y is that it i s soft . in s tead of r equ i ring r om or other fixed memo r y, i t contains internal pr o g r a m/ d a t a r a m that is downloaded over the usb itsel f to give th e dev i ce its unique pe r s o n a l it y . t his m ake mod- i f ic a t ion s , spe c i ficat i on re v isions, and updates a snap. the e z - usb family can c o nnect as a usb de v ice and download code into in t e r nal ram, all while it s i nternal 8051 is held i n re s et. this is done b y an enha n ce d s ie, whic h does all of the work shown in figure1-8, and m o re. i t contains additional logic t o perform a full enumeration, using an internal table of d e scriptor s . it a l s o responds to a vendor spe- ci f ic firmw a r e d o wnload device r e quest to load i ts internal r am. an adde d bonus i s that the adde d sie functionality is also made available to the 8051. this saves 8051 code and pro c essi n g t i me. throughout this manua l , th e sie and its enhancem e nts a re referred to as t h e usb core. the e z -usb microproces s or is an enhanced 8051 core. u s e of an 8051 compatible pro- c e ssor mak e s e x tensive softwa r e suppo r t tools immediately available to t h e ez-usb designe r . this enhanced 8051 core, des c r ibed in c h apter 2, "e z -usb cpu" and appen- dices a-c, has t he following fe a t u res: ? 4 - c lock cy c l e , as compared to t h e 12-clock cycle of a s tandard 8051, giving a 3x speed impr o v ement. ? dual d a t a pointers for f a st e r memor y -to-memory t ra n sf e r s. ? t wo u a r t s. ? three count e r-timers. ? an expanded interr u p t s y stem. ? 24 - m hz clock. ? 256 bytes of interna l reg i st e r r a m. ? s t andard 8051 in s truction setif you know the 8051, you kno w ez-usb. the enhance d 805 1 c ore u se s on - chi p r am as progr a m and dat a memor y , giving ez - usb its soft feature. chapter 3, " e z -usb m emory" de s c r ibes the various m e mory o p ti o n s . 1. 1 1 e z -usb m icroproc e ssor
page 1-12 chapter 1. introducing ez-usb ez-usb series 2100 trm v1.8 the 8051 communicates with the sie using a set of registers, which occupy the top of the on-chip ram address space. these registers are grouped and described by function in individual chapters of this reference manual, and summarized in register order in chapter 12, "ez-usb registers." the ez-usb 8051 has two duties. first, it participates in the protocol defined in the uni- versal serial bus specification version 1.1, chapter 9, usb device framework. thanks to ez-usb enhancements to the sie and usb interface, the 8051 firmware asso- ciated with usb overhead is simplified, leaving code space and bandwidth available for the 8051s primary duty, to help implement your device. on the device side, abundant input/output resources are available, including io ports, uarts, and an i 2 c bus master controller. these resources are described in chapter 4, "ez-usb input/output." because it is soft , the ez-usb chip can take on the identities of multiple distinct usb devices. the first device downloads your 8051 firmware and usb descriptor tables over the usb cable when the peripheral device is plugged in. once downloaded, another device comes on as a totally different usb peripheral as defined by the downloaded infor- mation. this two-step process, called renumeration ? , happens instantly when the device is plugged in, with no hint that the initial load step has occurred. chapter 5, "ez-usb enumeration and renumeration" describes this feature in detail, along with other ez-usb boot (startup) modes. the universal serial bus specification version 1.1 defines an endpoint as a source or sink of data. since usb is a serial bus, a device endpoint is actually a fifo which sequentially empties/fills with usb bytes. the host selects a device endpoint by sending a 4-bit address and one direction bit. therefore, usb can uniquely address 32 endpoints, in0 through in15 and out0 through out15. from the ez-usb point of view, an endpoint is a buffer full of bytes received or to be transmitted over the bus. the 8051 reads endpoint data from an out buffer, and writes endpoint data for transmission over usb to an in buffer. four usb endpoint types are defined as: bulk, control, interrupt, and isochronous. 1.12 renumeration ? ? ? ? 1.13 ez-usb endpoints
ez-usb series 2100 trm v1.8 chapter 1. introducing ez-usb page 1-13 1.13.1 ez-usb bulk endpoints bulk endpoints are unidirectionalone endpoint address per direction. therefore end- point 2-in is addressed differently than endpoint 2-out. bulk e ndpoints use m aximum packet sizes (and therefore buffer sizes) of 8, 16, 32, or 64 bytes. ez-usb provides four- teen bulk endpoints, divided into seven in endpoints (endpoint 1-in thr ough 7-i n), and seven out endpoints (endpoint 1-out through 7-out). each of the fourteen endpoints has a 64-byte buffer. bulk data is available to the 8051 in ram form, or as fifo data using a special ez-usb autopointer (chapter 6, "ez-usb bulk transfers"). 1.13.2 ez-usb control endpoint zero control endpoints transfer mission-critical control information to and from the usb device. the universal serial bus specification version 1.1 requires every usb device to have a default control endpoint, endpoint zero. device enumeration, the process that the host initiates when the device is first plugged in, is conducted over e ndpoint zero. the host sends all usb requests over endpoint zero. control endpoints are bi-directional; if you have an endpoint 0 in control endpoint, you automatically have an endpoint 0 out endpoint. control endpoints alone accept setup pids. a control transfer consists of a two or three stage sequence: ?setup ? data (if needed) ? handshake eight bytes of data in the setup portion of the control transfer have special usb significance, as defined in the universal serial bus specification version 1.1, chapter 9. a usb device must respond properly to the requests described in this chapter to pass usb compliance testing (usually referred to as the usb chapter nine test). endpoint zero is the only control endpoint in the ez-usb chip. the 8051 res ponds to device requests issued by the host over endpoint zero. the ez-usb core is significantly enhanced to simplify the 8051 code required to service these requests. chapter 7, "ez- usb endpoint zero" provides a detailed roadmap for writing usb chapter 9 compliant 8051 code.
page 1-14 chapter 1. introducing ez-usb ez-usb series 2100 trm v1.8 1.13.3 ez-usb interrupt endpoints interrupt endpoints are almost identical to bulk endpoints. fourteen ez-usb endpoints (ep1-ep7, in, and out) may be used as interrupt endpoints. interrupt endpoints have maximum packet sizes up to 64, and contain a polling interval byte in their descriptor to tell the host how often to service them. the 8051 transfers data over interrupt endpoints in exactly the same way as for bulk endpoints. interrupt endpoints are described in chapter 6, "ez-usb bulk transfers." 1.13.4 ez-usb isochronous endpoints isochronous endpoints deliver high bandwidth, time critical data over usb. isochronous endpoints are used to stream data to devices such as audio dacs, and from devices such as cameras and scanners. time of delivery is the most critical requirement, and isochro- nous endpoints are tailored to this requirement. once a device has been granted an isoch- ronous band width slot by the host, it is guaranteed to be able to send or receive its data every frame. ez-usb contains 16 isochronous endpoints, numbered 8-15 (8in-15in, and 8out- 15out). 1,024 bytes of fifo memory are available to the 16 endpoints, and may be fifo memory to provide double-buffering. using double buffering, the 8051 reads out data from isochronous endpoint fifos containing data from the previous frame while the host writes current frame data into the other buffer. similarly, the 8051 loads in data into isochronous endpoint fifos that will be transmitted over usb during the next frame while the host reads current frame data from the other buffer. at every sof the usb fifos and 8051 fifos switch, or ping-pong . isochronous transfers are described in chapter 8, "ez-usb isochronous transfers." the following versions of the ez-usb have a fast transfer mode: an2125sc, an2126sc, an 2135sc, an 2136sc, and an2131qc, that is, those versions that have a data bus (see table1-2). the fast transfer mode minimizes the transfer time from ez-usb core also supplies external fifo read and write strobes to synchronize the transfers. using the fast transfer mode, the 8051 transfers a byte of data between an internal fifo and the external bus using a single 8051 movx instruction, which ta kes two cycles or 333 ns. both isochronous and bulk endpoints can use this fast transfer mode. 1.14 fast transfer modes
ez-usb series 2100 trm v1.8 chapter 1. introducing ez-usb page 1-15 the ez-usb enhanced 8051 adds seven interrupt sources to the standard 8051 i nterrupt system. three of the added interrupts are used internally, and the others are available on device pins. int2 is used for all usb interrupts. int3 is used by the i 2 c interface. a third interrupt is used for remote wakeup indication. the ez-usb core automatically supplies jump vectors (autovectors) for its usb inter- rupts to save the 8051 from having to test bits to determine the source of the interrupt. each bulk/control/interrupt endpoint has its own vector, so when an endpoint requires service, the proper interrupt service routine is automatically invoked. the 8051 services all isochronous endpoints in response to a sof (start of frame) interrupt request. chapter 9, "ez-usb interrupts" describes the ez-usb interrupt system. the ez-usb chip contains four resets: ? power-on-reset (por) ? usb bus reset ? 8051 reset ? usb disconnect/re-connect the functions of the various ez-usb resets are described in chapter 10, "ez-usb resets." a usb peripheral may be put into a low power state when the host signals a suspend oper- ation. the universal serial bus specification version 1.1 states that a bus powered device cannot draw more than 500 ma of current from the vcc wire while in suspend. the ez- usb chip contains logic to turn off its internal oscillator and enter a sleep state. a special interrupt, triggered by a wakeup pin or wakeup signaling on the usb bus, starts the oscil- lator and interrupts the 8051 to resume operation. low power operation is described in chapter 11, "ez-usb power management." 1.15 interrupts 1.16 reset and power management
page 1-16 chapter 1. introducing ez-usb ez-usb series 2100 trm v1.8 the ez-usb family is available in various pinouts to serve different system requirements and costs. table 1-2 shows the feature set for each member of the ez-usb series 2100 family. this section summarizes the features of the an2122 and an2126 packages. these fea- tures are not available in the other packages of the ez-usb family. power saving option to reduce power, the 8051 processor can be run at half speed. when the cpu12mhz pin is tied high, the 8051 processor core runs at 12 mhz. when tied low, the 8051 runs at the normal 24 mhz. the logic state of this pin should never be changed while the 8051 is running. 230 kbaud uart operation two control bits in a register, uart230, allow 230-kbaud operation by uart0 and uart1 (see section 12.8, "230-kbaud uart operation - an2122, an2126"). 1.17 ez-usb product family table 1-2. ez-usb series 2100 family part number ram size key features package max uart (async) speed (kbaud) power saving option ibn/ stop iso support endpoints data bus or port b i/o rate bytes/s max prog i/os an2121s 4kb y 32 port b 600k 16 s = 44 pqfp 115.2 n n an2122s 4kb n 13 port b 600k 16 s = 44 pqfp 230.4 n y an2122t 4kb n 13 port b 600k 19 t = 48 tqfp 230.4 y y an2125s 4kb y 32 data bus 2m 8 s = 44 pqfp 115.2 n n an2126s 4kb n 13 data bus 2m 8 s = 44 pqfp 230.4 n y an2126t 4kb n 13 data bus 2m 11 t = 48 tqfp 230.4 y y an2131q 8kb y 32 both 2m 24 q = 80 pqfp 115.2 n n an2131s 8kb y 32 port b 600k 16 s = 44 pqfp 115.2 n n AN2135S 8kb y 32 data bus 2m 8 s = 44 pqfp 115.2 n n an2136s 8kb n 16 data bus 2m 8 s = 44 pqfp 115.2 n n 1.18 summary of an 2122, an 2126 features
ez-u s b s er i e s 2 1 0 0 t rm v 1.8 c h a p t e r 1 . i n tr o d u c i n g ez - usb p a g e 1 - 17 48 - pin v arian t s there are two 48-pin devi c es: an2122t an2126t the fou r ext r a pins are u s ed as follo w s: ? p a7, p a6, and p a0 are gpio pin s . th i s mak e s f ive o f the e igh t po r t a pins availabl e ( a ll exce p t pa 1 -pa3). ? cpu12mhz - this input controls the spee d of the 8051: - tied high 1 2 mhz - tied low 2 4 mhz bulk endp o ints the an2122 and an2126 have a reduc e d set of t h i rteen bulk endpo i n ts ( s ee section 6.1, "introduction " ) . inter ru pts the an2122 and an2126 contain two interrupts not pre s ent in the other an21xx f a mily members. ? a n ibn ( i n-bulk nak ) interrup t request activa t es when an i n packet is nakd by the s i e bec a use the 8051 has not loaded t he b u ffer (and byte count register) for an i n endpoint. this is useful fo r applications th a t need to know when the host is pinging an i n endpoint (see section 9.13, "in bulk nak interrupt"). ? an i 2 c interrupt sour c e is added to the i 2 c in t e r rupt (int3), indicating t h at t rans- miss i on o f a stop bit i s c o m ple t e (see section 9.14, "i 2 c s t o p compl e t e inte r - rupt - (an2122/an2126 only)"). the revision id fo r each part is sho w n in table 1.2. the re v is i on value i s reported in the intern a l did (device i d ), which is the val u e read by the host dur i ng en u m eration if no e eprom is connected to the i 2 c bu s . this value also a p p e a rs in t h e c p ucs re g i s te r bits. 1.19 r evision id
page 1-18 chapter 1. introducing ez-usb ez-usb series 2100 trm v1.8 figures 1-9 through 1-13 are pin descriptions by package type. table 1-3 describes the pins by pin function. figure 1-9. 80-pin pqfp package (an2131q) 1.20 pin descriptions 40 38 37 36 35 34 33 32 31 30 29 28 27 26 25 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 80 pqfp 14 x 20 mm sda gnd vcc bkp d7 d6 d5 d4 gnd pb7/t2out pb6/int6 pb5/int5# pb4/int4 d3 d2 d1 d0 pb3/txd1 pb2/rxd1 pb1/t2ex pb0/t2 gnd vcc pc7/rd# pc0/rxd0 pc1/txd0 pc2/int0# pc3/int1# pc4/t0 pc6/wr# a8 a9 a15 a14 a13 a12 a11 a10 pc5/t1 rese scl wakeup# gnd usbd+ pa0/t0out pa1/t1out pa2/oe# pa3/cs# pa4/fwr# pa5/frd# pa6/rxd0out pa7/rxd1out nc usbd- psen# gnd 123456789 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 64 63 62 61 39 gnd a6 a7 gnd agnd xin xout avcc vcc gnd ea discon# vcc gnd clk24 gnd gnd a0 a1 a2 a3 a4 a5 gnd
ez-usb series 2100 trm v1.8 chapter 1. introducing ez-usb page 1-19 figure 1-10. 44-pin pqfp package with port b (an2121s, an2122s, and an2131s) gnd rese vcc pc0/rxd0 pc1/txd0 pc2/int0# pc3/int1# pc4/t0 pc6/w r# pc7/rd# pc5/t1 avcc xout xin agnd gnd vcc clk24 gnd gnd gnd gnd gnd pb1/t2ex pb2/rxd2 pb3/txd2 pb4/int4 pb5/int5# pb6/int6 pb0/t2 vcc pb7/t2ou bkp scl sda gnd vcc wakeup# discon# usbd+ pa4/f wr# pa5/frd# gnd usbd- 12 13 14 15 16 17 20 18 19 21 22 44 43 42 41 40 39 36 38 37 35 34 33 32 31 30 29 28 25 27 26 24 23 1 2 3 4 5 6 9 7 8 10 11 44 pqfp 10 x 10 mm
p a g e 1 - 2 0 c h a p t e r 1 . i n t r o d u c i n g ez - usb e z -usb s e r i e s 2 1 0 0 t r m v 1.8 f i g u r e 1 - 1 1 . 44 - p i n p a c k a ge w i th d a t a bus ( a n 2 1 2 5 s, a n 2 1 2 6 s , a n 21 3 5 s, and an2136 ) gn d re s e vc c pc 0 / r x d 0 pc 1 / t x d 0 pc 2 / i n t 0 # pc 3 / i n t 1 # pc 4 / t 0 pc 6 / w r # p c 7/rd# pc 5 / t 1 a vcc x o u t x i n a g n d g n d v c c cl k 24 g n d g n d g n d g n d sc l sd a gn d vc c w a ke up# disc o n # us bd+ pa 4 / f w r # p a 5/ frd# gn d us bd- g n d d1 d2 d3 d4 d5 d6 d0 v c c d7 b k p 12 13 14 15 16 17 2 0 18 19 21 22 44 43 42 41 40 39 3 6 38 37 35 34 33 32 31 30 29 28 25 27 26 24 23 1 2 3 4 5 6 9 7 8 10 11 44 pqfp 1 0 x 1 0 mm
ez-usb series 2100 trm v1.8 chapter 1. introducing ez-usb page 1-21 figure 1-12. 48-pin tqfp package (an2122t) cpu12mhz 13 14 15 16 17 18 21 19 20 22 23 48 47 46 45 44 43 40 42 41 39 38 36 35 34 33 32 31 28 30 29 27 26 1 2 3 4 5 6 9 7 8 10 11 48 tqfp 7 x 7 mm 12 pa7/rxd1ou 25 24 37 pb3/txd1 pb4/int4 pb5/int5# pb6/int6 pb7/t2ou pa0/t0ou bkp pa6/rxd0ou rese vcc pc0/rxd0 pc1/txd0 pc2/int0# pc3/int1# pc4/t0 pc6/w r# pc7/rd# pc5/t1 avcc xout xin agnd gnd vcc clk24 gnd gnd gnd gnd scl sda w akeup# discon# usbd+ pa4/f wr# pa5/frd# gnd usbd- gnd pb1/t2ex pb2/rxd1 pb0/t2 vcc gnd gnd vcc analog vcc and gnd digital vcc digital gnd extra pins in 48-pin package
p a g e 1 - 2 2 c h a p t e r 1 . i n t r o d u c i n g ez - usb e z -usb s e r i e s 2 1 0 0 t r m v 1.8 f i gu r e 1 - 1 3 . 4 8 - p i n t q f p p a c k a g e ( a n 2 1 26t) 13 14 15 16 17 18 2 1 19 20 22 23 48 47 46 45 44 43 4 0 42 41 39 38 36 35 34 33 32 31 28 30 29 27 26 1 2 3 4 5 6 9 7 8 10 11 4 8 tqfp 7 x 7 mm 12 p a 7 / r x d 1 o u 25 24 37 cp u1 2 m hz d3 d4 d5 d6 d7 pa0 / t 0 o u b k p pa 6 / rx d 0 o u re s e vc c pc 0 / r x d 0 pc 1 / t x d 0 pc 2 / i n t 0 # pc 3 / i n t 1 # pc 4 / t 0 pc 6 / w r # p c 7/rd# pc 5 / t 1 a vcc x o u t x i n a g n d g n d v c c cl k 24 g n d g n d g n d g n d sc l sd a w ak eu p # disc o n # us bd+ pa 4 / f w r # p a 5/ frd# gn d us bd- g n d d1 d2 d0 v c c gn d gn d vc c a n a l o g v cc and gnd d i g i tal v cc d i g i tal g nd e x t r a p i n s in 4 8 - p in package
ez-u s b s e r i e s 2 1 0 0 t r m v 1.8 c h a p t e r 1 . i n tr o d u c i n g ez - usb p a g e 1 - 23 t a b le 1- 3 . ez-u s b s e r i e s 2 10 0 p i nou t s b y pin f u n c t i o n 2131q 2121s 2122s 2131s 2125s 2126s 2135s 2136s 2122t 2126t n a me type de f a u l t d es c r i p t ion 21 10 10 11 11 a v c c po w er n / a ana l o g vc c . t his s ignal p r ovides p o w e r to the ana- log s e c ti o n o f th e chip. 18 7 7 7 7 a g nd po w er n / a a n a l o g gr o u n d . c o n n ect to g rou n d w ith as short a p a th as possible. 1 43 43 47 47 d i scon# outp u t hi d i s c o n nec t . t his pin i s c o n t r oll e d by t wo bits, d i s coe a n d d iscon. w hen d i s c oe = 0 , the pin f lo a t s. w h en dis c oe = 1 , it dri v es. w h e n d i s c o e=1, t h e dr i v e n l ogic l ev e l is the i nvers e of t he d i scon b i t. 77 41 41 45 45 u s bd i / o/z z u s b d- s i gna l . co n n e c t to the usb d- signal t hrough a 2 4-o h m r e sistor. 79 42 42 46 46 u s bd i / o/z z u s b d+ s igna l . c o n n e c t to t h e usb d+ pin through a 24 - oh m re s i s tor. 7-1 2 , 1 5 , 16, 26-29, 34-37 n / a n / a n / a n / a a0 - a 5, a 6, a 7 , a 8 - a 1 1 , a 12 - a15 outp u t 0x0 0 00 8 0 51 a dd r e ss bu s . t h i s b u s i s dr i v e n a t a l l times. wh e n t h e 8051 i s ad d r e ssing i n t e r n a l ram i t reflects t h e i n terna l a d dress. 48-51, 57-60 n / a 24-27, 28-31 n / a 26-29, 30-33 d0-d3, d 4 - d7 i / o/z z 8 0 51 d a ta bu s . t his bi-dire c t ional b u s is high- i m pe d anc e w h en i n ac t ive, in p u t for bus reads, and o u t p ut for bu s w r it e s. t he data bus is also used to t ra n s fer d ata d i r e c t ly t o and f r om in t e r nal ez-usb f i f os u n d e r c o n t r ol of t h e frd # an d fwr# s t r o bes . d0-d 7 are active onl y f o r externa l bus a c ce s ses, a n d a r e dr i ven low i n suspend. 80 n / a n / a n / a n / a p s en# outp u t h p r o g r a m s t o r e e n a bl e . t his ac t ive-low signal indi- c a t es a c o d e f e t c h fro m e xter n al me m or y . i t is active f or progr a m m e mory f e t ches abo v e 0 x1b40 when t he e a pi n i s l o , o r a b o ve 0 x 0000 when the ea pin is h i . 61 32 32 35 35 b k p t outp u t 0 br e a k p o i nt . t his pin g oes a c t i ve ( h i g h) w h e n the 8 0 51 addr e s s b u s m at c hes t h e bpaddrh/ l regis- t ers and b rea k p oints are e n a b l e d in the usbbav r egi s t e r ( b p en=1) . i f the bpp u lse b it i n the u s b b a v r e g i s t er is h i , this signal puls e s high for eig h t 24- m hz clo c ks. i f t he bpp u l s e b i t i s lo , the s i g nal r e mains hi g h u n t i l the 8 0 51 c l ears the break bit ( b y w ri t ing 1 t o i t ) i n the u s b b av r e g i s t er. 25 13 13 14 14 r e s e t i nput n / a a c t i ve h i g h reset . re s e t s t he 80 5 1 a n d the usb s i e . t his pin i s n o rmal l y t i ed to g roun d through a 1 0 k- o h m res i stor and t o vcc through a 1 m f c a p a c i - t o r .
p a g e 1 - 2 4 c h a p t e r 1 . i n t r o d u c i n g ez - usb e z -usb s e r i e s 2 1 0 0 t r m v 1.8 24 n / a n / a n / a n / a ea i nput n / a e x terna l ac c ess . i f th i s si g n al is a c t i v e ( h ig h ) , the 8 0 51 f e t che s c ode f r om exte r nal mem o ry instead of t h e i n ternal pr o gram ra m . if e a = 0, the 8051 f e t c hes c ode fr o m exter n al m e m ory startin g at 0 x 1b40 ( an2131). 19 8 8 9 9 x i n i nput n / a cr y sta l i npu t . con n e ct this s ign a l to a 12-mhz s eries reso n a n t , f u n d a m e n t al m o de c rystal and 22- 3 3 - p f c a pac i t o r to g n d . this pin may also be driven by a 12-mhz clock. 20 9 9 10 10 xo u t outp u t n / a cr y stal o u t p u t . co n ne c t th i s si g nal to a 12-mhz s eries reso n a n t , f u n d a m e n t al m o de c rystal and 22- 3 3 - p f c a pac i t o r to g n d . i f x i n i s d r i v e n by a 12- m hz cl o c k , t h i s pin sho u ld n o t be connected. 68 n / a n / a n / a 34 p a0 or t0out i / o i ( p a0) m ul t iplex e d pin who s e fu n c t i on is se l ec t ed by the t 0out bi t of t he p o r t a c fg re g i s t e r . if t 0 out=0, t h e p i n i s the bi- d i rec t i onal i / o p ort b i t pa0 . if t 0 o u t =1, the pi n is t he activ e - h i g h t0out signal f rom 8 0 5 1 t im e r / c o u nter0. t 0out o u t p uts a high l e v e l for o n e c l k24 clock c ycle w h en t i m e r0 o ver f lo w s . if ti m e r 0 i s operated in mo d e 3 ( t wo sep a r a te t i m er / c o un t e r s), t0out is a c t ive wh e n the low b y te t i m e r / c o u n te r ove r flows. 69 n / a n / a n / a n / a p a1 or t1out i / o i ( p a1) m ul t iplex e d pin who s e fu n c t i on is se l ec t ed by the t 1out bi t of t he p o r t a c fg re g i s t e r . if t 1 out=0, t h e p i n i s the bi- d i rec t i onal i / o p ort b i t pa1 . if t 1 o u t =1, the pi n is t he activ e - h i g h t1out signal f rom 8 0 5 1 t ime r - c o u nter1 . t 1out o u t p uts a high l e v e l for o n e c l k24 clock c ycle w h en t i m e r1 o ver f lo w s . if ti m e r 1 i s operated in mo d e 3 ( t wo sep a r a te t i m er / c o un t e r s), t1out is a c t ive wh e n the low b y te t i m e r / c o u n te r ove r flows. 70 n / a n / a n / a n / a p a 2 o r o e # i / o i ( p a2) m ul t iplex e d p i n who s e f u nc t i on is s e le c t e d b y th e oe bit of the p o r t a cfg r e g i s te r . if o e =0, th e pi n is t h e b i-dir e cti o n al i / o po r t pin p a 2. if oe=1, the pin is an a c t ive-lo w o u t put e nable for ext e rn a l memory. i f t h e o e # p i n i s u s e d , i t s h o u l d b e e x t e r nall y pulled up to v c c to ens u re t h at t he w rite st r o be i s inactiv e ( h i g h) at p ower-on. t a b le 1- 3 . ez-u s b s e r i e s 2 10 0 p i nou t s b y pin f u n c t i o n 2131q 2121s 2122s 2131s 2125s 2126s 2135s 2136s 2122t 2126t n a me type de f a u l t d es c r i p t ion
ez-usb series 2100 trm v1.8 chapter 1. introducing ez-usb page 1-25 71 n/a n/a n/a n/a pa3 or cs# i/o i (pa3) multiplexed pin whose function is selected by the cs bit of the portacfg register. if cs=0, the pin is the bi-directional i/o port pin pa3. if cs=1, the pin is an active-low chip select for external memory. if the cs# pin is used, it should be externally pulled up to vcc to ensure that the write strobe is inactive (high) at power-on. 73 39 39 n/a n/a pa4 or fwr# i/o i (pa4) multiplexed pin whose function is selected by the fwr (fast write) bit of the portafcg register. if fwr=0, the pin is the bi-directional i/o port pin pa4. if fwr=1, the pin is the write strobe for an external fifo. if the fwr# pin is used, it should be exter- nally pulled up to vcc to ensure that the write strobe is inactive (high) at power-on. 74 40 40 n/a n/a pa5 or frd# i/o i (pa5) multiplexed pin whose function is selected by the frd (fast read) bit of the portafcg register. if frd=0, the pin is the bi-directional i/o port pin pa5. if frd=1, the pin is the read strobe for an external fifo. if the frd# pin is used, it should be exter- nally pulled up to vcc to ensure that the write strobe is inactive (high) at power-on. 75 n/a n/a 44 44 pa6 or rxd0out i/o i (pa6) multiplexed pin whose function is selected by the rxd0out bit of the portafcg register. if rxd0out=0 (default), the pin is the bi-directional i/o port bit pa6. if rxd0out=1, the pin is the active-high rxd0out signal from 8051 uart0. if rxd0out is selected and uart0 is in mode 0, this pin provides the output data for uart0 only when it is in sync mode. otherwise, it is a 1. 76 n/a n/a 8 8 pa7 or rxd1out i/o i (pa7) multiplexed pin whose function is selected by the rxd1out bit of the portafcg register. if rxd1out=0 (default), the pin is the bi-directional i/o port bit pa7. if rxd1out=1, the pin is the active-high rxd1out signal from 8051 uart1. when rxd1out is selected and uart1 is in mode 0, this pin provides the output data for uart1 only when it is in sync mode. in modes 1, 2, and 3, this pin is a 1. table 1-3. ez-usb series 2100 pinouts by pin function 2131q 2121s 2122s 2131s 2125s 2126s 2135s 2136s 2122t 2126t name type default description
p a g e 1 - 2 6 c h a p t e r 1 . i n t r o d u c i n g ez - usb e z -usb s e r i e s 2 1 0 0 t r m v 1.8 44 24 n / a 26 n / a p b 0 or t2 i / o i ( p b0) m ul t iplex e d p i n w hose fu n c t i on is se l ec t e d by the t2 bit of the p o r t bf c g r e g i s te r . if t 2 =0, th e pi n is t he bi-d i r e ct i o n a l i/o po r t b it p b 0 . if t 2=1, the pin is t he a c t ive-h i gh t2 s i g n al f r o m 80 5 1 t i m er2, which p r ovide s t he i n p u t t o timer 2 w hen c/t2=1. when c / t2=0 , t i m e r2 d o e s n ot u s e t h is pin. 45 25 n / a 27 n / a p b 1 or t2ex i / o i ( p b1) m ul t iplex e d pin who s e fu n c t i on is se l ec t ed by the t 2 e x b i t of t h e p o r t b cf g re g i s te r . if t2e x =0 , the pin is t he bi-dir e cti o n al i / o p o r t bit p b 1 . if t2ex=1, t h e p i n i s t h e act i v e - hi g h t2ex si g nal from 8051 t i m e r 2 . 46 26 n / a 28 n / a p b 2 or rxd1 i / o i ( p {b2) m ul t iplex e d pin who s e fu n c t i on is se l ec t ed by the r x d1 b i t o f t h e p o r t b cfg re g i s te r . if r xd 1 =0, t h e p i n i s the bi- d i rec t i o nal i / o p o r t b it pb2. if r x d1=1, t h e pi n is t he active - high r xd1 input sig- na l f o r 8 0 5 1 u a r t 1 , w h i ch prov i d e s d ata to the u a r t in all m odes. 47 27 n / a 29 n / a p b 3 o r t x d1 i / o i ( p b3) m ul t iplex e d pin who s e fu n c t i on is se l ec t ed by the t x d1 b i t o f the p o r t b c fg r e g i st e r . if txd1=0, t h e p i n i s the bi- d i rec t i o nal i / o p o r t b it pb3. if t x d 1 = 1 , t h e p i n i s t h e a c t i v e - h i g h t x d 1 output pin f or 8051 u art1 w h i ch pro v i d es t h e ou t put clock in a s ync m ode. 52 28 n / a 30 n / a p b 4 o r i n t4 i / o i ( p b4) m ul t iplex e d pin who s e fu n c t i on is se l ec t ed by the i n t 4 b i t o f the p o rt b c f g re g i s te r . i f in t 4 =0, the pin is t he bi-dir e cti o n al i / o p o r t bit p b 4 . if int4=1, t h e p i n i s t h e 805 1 i n t4 i nt e rr u pt request signal. t h e i n t4 pin is edge - sen s i t i ve , activ e high. 53 29 n / a 31 n / a p b5 o r i n t5# i / o i ( p b5) m ul t iplex e d pin who s e fu n c t i on is se l ec t ed by the i n t 5 b i t o f the p o rt b c f g re g i s te r . i f in t 5 =0, the pin is t he bi-dir e cti o n al i / o p o r t bit p b 5 . if int5=1, t h e p i n i s t h e i nt5# int e r rup t r e g i s t e r s i gnal. the i n t 5# p in i s e d ge- s e n s i ti v e , a c t i v e low. 54 30 n / a 32 n / a p b 6 o r i n t6 i / o i ( p b6) m ul t iplex e d pin who s e fu n c t i on is se l ec t ed by the i n t 6 b i t o f the p o rt b c f g re g i s te r . i f in t 6 =0, the pin is t he bi-dir e cti o n al i / o p o r t bit p b 6 . if int6=1, t h e p i n i s t h e i nt6 int e r r upt r e q u e s t s i gnal. the i n t 6 pin is ed g e-s e n s i t iv e , a c t i ve high. t a b le 1- 3 . ez-u s b s e r i e s 2 10 0 p i nou t s b y pin f u n c t i o n 2131q 2121s 2122s 2131s 2125s 2126s 2135s 2136s 2122t 2126t n a me type de f a u l t d es c r i p t ion
ez-u s b s er i e s 2 1 0 0 t rm v 1.8 c h a p t e r 1 . i n tr o d u c i n g ez - usb p a g e 1 - 27 55 31 n / a 33 n / a p b7 or t2out i / o i ( p b7) m ul t iplex e d pin who s e f u n c t io n is s e le c ted by the t 2out bi t o f t he p o r t b c f g r e g i s t e r . if t 2 out=0, t h e p i n i s the bi- d i rec t i o nal i / o p o rt b i t pb7. if t 2 o u t =1, the pi n is t he activ e - h i g h t2out signal f rom 8 0 5 1 t i mer2. t2out i s a c t ive (high) fo r o ne c l o ck cycle w h e n t i m er / co u nter 2 o v erf l ows. 30 14 14 16 16 p c0 o r r xd0 i / o i ( p c0) m ul t iplex e d pin who s e f u n c t io n is s e le c ted by the r x d0 b i t o f t h e p o r t c c fg r e g i st e r . if rxd0=0, t h e p i n i s the bi- d i rec t i onal i / o port b i t pc0. if r x d0=1, t h e pi n is t he ac t i ve - hi g h r x d0 from 8051 u a r t 0, which provi d es d a t a to t h e uart in all m odes. 31 15 15 17 17 pc1 or txd0 i / o i ( p c1) m ul t iplex e d pin who s e f u n c t io n is s e le c ted by the t x d0 b i t o f the p o r t c cfg r e g i st e r . if txd0=0, t h e p i n i s the bi- d i rec t i onal i / o port b i t pc1. if t x d0=1 , t he p i n i s t h e a ctive - h igh txd0 signa l for 8 0 5 1 u a r t 0 , w h i c h p r o v i d e s t h e o u t p u t clock in s ync m o d e , a n d t h e o utput d at a i n asyn c mode. 32 16 16 18 18 p c2 or i n t0# i / o i ( p c2) m ul t iplex e d pin who s e f u n c t io n is s e le c ted by the i n t 0 b i t o f the p o r t ccfg r e g i st e r . i f i n t 0=0, the pin is t he bi-dir e cti o n al i / o p o r t bit p c 2. if int0=1, t h e p i n i s t h e activ e - l o w 805 1 i n t0 i nterrupt input s i g na l , w h i ch is e i th e r e d ge tr i g g ered ( it0=1 ) or level t r i g g e r e d ( i t 0 = 0 ) . 33 17 17 19 19 p c3 or i n t1# i / o i ( p c3) m ul t iplex e d pin who s e f u n c t io n is s e le c ted by the i n t 1 b i t o f the p o r t ccfg r e g i st e r . i f i n t 1=0, the pin is t he bi-dir e cti o n al i / o p o r t bit p c 3. if int1=1, t h e p i n i s t h e activ e - l o w 805 1 i n t1 i nterrupt input s i g na l , w h i ch is e i th e r e d ge tr i g g ered ( it1=1 ) or level t r i g g e r e d ( i t 1 = 0 ) . 38 18 18 20 20 p c4 o r t0 i / o i ( p c4) m ul t iplex e d p in who s e f u n c t i o n is s e le c t e d by the t0 bit of the p o r t c c fg r e g i s te r . if t 0 = 0 , th e pi n is t he bi-di r e cti o n al i / o po r t b i t p c 4. i f t0=1, the pin is t he a ctive-h i gh t0 s i gna l f o r 80 5 1 t i m er0, which pro- v i d es t he i n p u t t o ti m e r 0 w hen c/t0 is 1. when c/ t 0 is 0, t i m er0 d o e s n ot use th i s bit. 39 19 19 21 21 p c5 o r t1 i / o i ( p c5) m ul t iplex e d p in who s e f u n c t i o n is s e le c t e d by the t1 bit of the p o r t c c fg r e g i s te r . if t 1 = 0 , th e pi n is t he bi-di r e cti o n al i / o po r t b i t p c 5. i f t1=1, the pin is t he a c t ive-h i gh t1 s i g n al f r o m 80 5 1 timer1, which p r ovide s t he i n p u t t o timer 1 w hen c/t1 is 1. when c / t 0 is 0, t i m er1 do e s n o t u s e th i s bit. t a b le 1- 3 . ez-u s b s e r i e s 2 10 0 p i nou t s b y pin f u n c t i o n 2131q 2121s 2122s 2131s 2125s 2126s 2135s 2136s 2122t 2126t n a me type de f a u l t d es c r i p t ion
p a g e 1 - 2 8 c h a p t e r 1 . i n t r o d u c i n g ez - usb e z -usb s e r i e s 2 1 0 0 t r m v 1.8 40 20 20 22 22 p c 6 o r wr# i / o i ( p c6) m ul t iplex e d pin who s e fu n c t i on is se l ec t ed by the wr bi t of t h e p o r t ccfg r e g i st e r . i f w r=0 , th e pin is t he bi-d i r e cti o n al i / o po r t b i t p c 6 . if w r =1, the pin is t he a ctive-low w r i t e s i g n al f o r e xt e rnal mem- o r y . i f t he wr# signal is u s ed, i t s h ould be exter- nally p u l l ed u p to v cc t o ensu r e t h at the write strobe is ina c tiv e at po w er-on. 41 21 21 23 23 p c7 or rd# i / o i ( p c7) m ul t iplex e d p i n who s e f u nc t i on is s e le c ted by the rd bit of the p o r t c c fg r e g i s te r . if r d #=0, th e pi n is t h e b i-dir e cti o n al i / o p o r t bit p c 7. if r d#=1, the pin is t he a ct i ve-low r ead s ignal f or ex t ern a l m e mory. if t he rd# si g n a l i s u sed, it should be externall y pulled u p to v cc to ens u re t h a t the read str o be i s inactiv e at p o wer-on. 4 2 2 2 2 cl k 24 outp u t 2 4 -m h z c l oc k , p h as e l o c k e d to t he 12-mh z input c l o c k . i t op e rat e s at 12 mhz in 1 2-mhz mode (48-pin p a ck a ge) . o u tput is disa b l ed b y setting the ou t cl k en bi t = 0 in t he c p ucs reg i s t er. 66 37 37 40 40 w a k e u p # i nput n / a u s b wa k eu p . i f the 8051 i s i n su s pend, a high to low e d g e on this p i n s t ar t s u p t h e o s cilla t or and inter- r u p t s t h e 8 051 to a llow it to e x i t th e suspen d mode. h o l din g w a ke u p# l ow inh i b i ts t he e z-usb chip f rom e n teri n g the su s p e n d state. 65 36 36 39 39 s c l od z i 2 c c l ock . p ull u p t o vc c w i th a 2 . 2k - ohm r e sistor, e v en i f no i 2 c dev i ce is c on ne cted. 64 35 35 38 38 sda od z i 2 c d a t a . c on n e c t t o v c c wi t h a 2. 2 k-ohm r esistor e v en i f no i 2 c dev i ce is c on ne cted. 2 , 22, 4 2 , 62 1 1 , 22, 3 3 , 44 1 1 , 2 2 , 3 3 , 44 1 2 , 24, 3 6 , 48 1 2 , 24, 3 6 , 48 vcc n / a v c c . 3 . 3 v p ow e r s o urce. 3, 5, 6, 1 3 , 14, 1 7 , 23, 4 3 , 56, 6 3 , 72, 78 1 , 3 , 4, 5 , 6, 1 2 , 23, 3 4 , 38 1, 3, 4, 5, 6, 1 2 , 23, 3 4 , 38 1 , 3 , 4, 5 , 6, 1 3 , 25, 3 7 , 41 1, 3, 4, 5, 6, 1 3 , 25, 3 7 , 41 g n d n / a gr o und. n o t e: o n the 80 - p i n pack a g e , pins 5, 6, 13, 1 4 , and 7 2 a r e test p i n s th a t m u s t b e grounde d for n o rmal op e rati o n. driving pi n 7 2 h i gh floats all func- t ional p i n s f o r a u t o m a t e d b oa r d test. t he co r responding pins on t h e 44-pin package a r e pins 3, 4, 5 , 6 , and 3 8 . driv i n g p in 3 8 high floats all f un c tional p i ns f o r a u t o m a t e d b o ard test. t he co r responding pins on t h e 48-pin package a r e pins 3, 4, 5 , 6 , and 4 1 . driv i n g p in 4 1 high floats all f un c tional p i ns f o r a u t o m a t e d b o ard testing. n / a n / a n / a 15 15 c pu1 2 mhz n / a t his in p ut c ontr o ls t h e speed of the 8051: - t i e d high - 1 2 mhz - t i e d low - 24 mhz 67 n / a n / a n / a n / a nc n / a t his pin m ust b e le f t unc o n n e cted. t a b le 1- 3 . ez-u s b s e r i e s 2 10 0 p i nou t s b y pin f u n c t i o n 2131q 2121s 2122s 2131s 2125s 2126s 2135s 2136s 2122t 2126t n a me type de f a u l t d es c r i p t ion
ez-usb series 2100 trm v1.8 chapter 2. ez-usb cpu page 2-1 2 ez-usb cpu the ez-usb built-in microprocessor, an enhanced 8051 core, is fully described in appen- dices a-c. this chapter introduces the processor, its interface to the ez-usb core, and describes architectural differences from a standard 8051. the enhanced 8051 core uses the standard 8051 instruction set. instructions execute faster than with the standard 8051 due to two features: ? wasted bus cycles are eliminated. a bus cycle uses four clocks, as compared to 12 clocks with the standard 8051. ? the 8051 runs at 24 mhz. in addition to the speed improvement, the enhanced 8051 core also includes architectural enhancements: 1. a second data pointer. 2. a second uart. 3. a third, 16-bit timer (timer2). 4. a high-speed memory interface with a non-multiplexed 16-bit address bus. 5. eight additional interrupts (int2-int5, pfi, t2, and uart1). 6. variable movx timing to accommodate fast/slow ram peripherals. 7. 3.3v operation. 2.1 introduction 2.2 8051 enhancements
page 2-2 chapter 2. ez-usb cpu ez-usb series 2100 trm v1.8 the ez-usb chip provides additional enhancements outside the 8051. these include: ? fast external transfers (autopointer, fast transfer mode) ? vectored usb interrupts (autovector) ? separate buffers for setup and data portions of a control transfer. ? breakpoint facility. the 8051 communicates with the ez-usb core through a set of memory mapped regis- ters. these registers are grouped as follows: ? endpoint buffers and fifos ? 8051 control ? io ports ? fast transfer ?i 2 c controller ? interrupts ? usb functions these registers and their functions are described throughout this manual. a full descrip- tion of every register and bit appears in chapter 12, ez-usb registers. 2.3 ez-usb enhancements 2.4 ez-usb register interface
ez-u s b s e r i e s 2 1 0 0 t r m v 1.8 c h a p t e r 2. e z-usb cpu p a g e 2-3 f i g u r e 2 - 1 . 8 0 5 1 r eg i s t ers l ike the standard 8051, th e e z - u sb 8051 c o r e contain s 12 8 b y t e s o f r e g i s t e r r a m a t 0 0 - 7 f , and a part i a lly populate d sfr register space a t 80-ff. an a d d itional 128 indirectly addres s ed regist e r s (someti m es calle d idata) are also availab l e at 80-ff. all internal e z-usb r am, w hich includes p r o g ram / d a ta mem o ry, bulk endpoint b u ffer memo r y , and the ez-usb r eg i s ter s et, i s add r e s sed a s add-on 8051 m e mo r y . the 8051 r e ads o r wr i t e s th e se bytes as data using the mo v x (move external) i nstruction. even though the movx instruction implies externa l mem o r y , the ez-u s b ram and register set is actually inside t h e e z - usb chip. exter n a l memory attached to the an2131q address and data bu s ses c a n a l so be a ccessed by the movx i nstruc t ion. the ez-usb core encodes its memory st r obe and s e le c t s i g n a ls (rd#, wr#, cs#, and oe#) to elimi- nate the need f o r external logic to se p a rate the inte r n al and exte r nal memory s paces. a stand a rd 8051 communi c ates with its i o ports 0 -3 th r ough four s p eci a l fun c tion regis- te r s ( s fr s ). standar d 8051 io p i ns ar e quasi-bid i r ectional with weak pu l lups th a t briefly d r ive high only when the pin ma k es a zero-to - one transition. th e e z- usb c o re i m p l ement s io p o rts d i f fe r ent l y t ha n a standard 805 1 , a s de s cribed in chapter 4 , "e z -usb input/output. " instead of using the 8051 io p o rts and s f rs, the e z - u s b co r e implements a flexible io system th a t is controlle d via e z -usb register set. e ach e z -usb i o pin functions iden t i ca l ly, having the following resou r c e s: ? an outpu t l atch. u sed when the pin is an outpu t port. ? a bi t t hat indi c ates the state o f the io p in, rega r dl e ss of i ts configuration (input or output ) . 2.5 e z -usb internal r am 2.6 i /o ports lower 128 bytes direct addr sfr space direct addr upper 128 bytes indirect addr 00 7f 80 ff
p a g e 2 -4 c h a p t e r 2. e z-usb cpu e z -usb s e r i e s 2 1 0 0 t r m v 1.8 ? an output enable bit that ca u ses t he io pin to be driven from t he output latch. ? an alternate function bit that det e rmines whether the pin is general io o r a special 8051 or e z-usb f u n c tion. the sfrs associated with 8051 ports 0-3 a r e not implement e d i n e z -usb. these sfr addres s es include p0 (0x80), p1 (0x90 ) , p2 (0xa0), and p3 (0xb0 ) . be c ause p2 is not im p l e mented, the movx @ r0/r1 instruction takes the upp e r addres s byte from an added special funct i on register (sfr ) at locatio n 0x92. t h i s r e gi s t e r is c a l l e d mpage in the appendic e s. all s t andard 8051 interr u p ts a re supported in the enhanced 8051 core . table 2-1 shows the e x i s ting and added 8051 interrup t s, and indicates how the added o n e s are used. the e z - u s b chi p u s es 8051 i nt 2 fo r 2 1 di f feren t usb in t e r rupts: 16 bulk endpoint s plus so f , suspend, s e tup data, s e tup t oken, and usb bus re s et. to help the 8051 d eter- mine w h ich interr u p t is active, t he ez-u s b core pr o v i des a feature called autovectoring. the core i n serts an addr e ss by t e into the low byte o f the 3-byte jump instruction f ound at the 8051 i nt2 vector addr e ss . t his s e cond level of v ec t oring automatically transfers con- trol to the appropriate usb isr. the autovector me c h anism, as well a s the ez-usb inte r rupt system is t h e s u b j ect of chapter 9, " e z-usb interrupts." 2.7 i n t e rrupts t a b le 2- 1 . ez-u s b in t e r r upts s ta n da r d 8051 i n ter r upts e n h a n c ed 8051 i n ter r upts u s e d a s i n t 0 d ev i ce p i n in t 0# i n t 1 d ev i ce p i n in t 1# t i m er 0 i n t erna l , t i m e r 0 t i m er 1 i n t erna l , t i m e r 1 tx0 & r x 0 i n t erna l , u a rt0 i n t2 i n t e r n a l , u s b i n t3 i n t e r n a l , i 2 c c o ntroller i nt4 d evice pin, p b4 / i n t 4 i nt5 d evice pin, p b5 / i n t 5 # i nt6 d evice pin, p b6 / i n t 6 p f1 d evice pin, u s b w a k eu p # t x 1 & r x 1 i n t erna l , u a rt1 t i m er 2 i n t erna l , t i m er 2
ez-usb series 2100 trm v1.8 chapter 2. ez-usb cpu page 2-5 the ez-usb core implements a power-down mode that allows it to be used in usb bus powered devices that must draw no more than 500 m a when suspended. power control is accomplished using a combination of 8051 and ez-usb core resources. the mechanism by which ez-usb powers down for suspend, and then re-powers to resume operation, is described in detail in chapter 11, ez-usb power management. a suspend operation uses three 8051 resources, the idle mode and two interrupts. many enhanced 8051 architectu res provide power control similar (or identical) to the ez-usb enhanced 8051 core. a usb suspend operation is indicated by a lack of bus activity for 3 ms. the ez-usb core detects this, and asserts an interrupt request via the usb interrupt (8051 int2). the isr (interrupt service routine) turns off external sub-systems that draw power. when ready to suspend operation, the 8051 sets an sfr bit, pcon.0. this bit causes the 8051 to suspend, waiting for an interrupt. when the 8051 sets pcon.0, a control signal from the 8051 to the ez-usb core causes the core to shut down the 12-mhz oscillator and internal pll. this stops all internal clocks to allow the ez-usb core and 8051 to enter a very low power mode. the suspended ez-usb chip can be awakened two ways: usb bus activity may resume, or an ez-usb pin (wakeup#) can be asserted to activate a usb remote wakeup . either event triggers the following chain of events: ? the ez-usb core re-starts the 12-mhz oscillator and pll, and waits for the clocks to stabilize ? the ez-usb core asserts a special, high-priority 8051 interrupt to signal a resume interrupt. ? the 8051 vectors to the resume isr, and upon completion resumes executing code at the instruction following the instruction that set the pcon.0 bit to 1. 2.8 power control
page 2-6 chapter 2. ez-usb cpu ez-usb series 2100 trm v1.8 the ez-usb family was designed to keep 8051 coding as standard as possible, to allow easy integration of existing 8051 software development tools. the added 8051 sfr regis- ters and bits are summarized in table2-2. 2.9 sfrs table 2-2. added registers and bits 8051 enhancements sfr addr function dual data pointers dpl0 0x82 data pointer 0 low addr dph0 0x83 data pointer 0 high addr dpl1 0x84 data pointer 1 low addr dph1 0x85 data pointer 1 high addr dps 0x86 data pointer select (lsb) mpage 0x92 replaces standard 8051 port 2 for indirect external data memory addressing timer 2 t2con.6-7 0xc8 timer 2 control rcap2l 0xca t2 capture/reload value l rcap2h 0xcb t2 capture/reload value h t2l 0xcc t2 count l t2h 0xcd t2 count h ie.5 0xa8 et2-enable t2 interrupt bit ip.5 0xb8 pt2-t2 interrupt priority control uart1 scon1.0-1 0xc0 serial port 1 control sbuf1 0xc1 serial port 1 data ie.6 0xa8 es1-sio1 interrupt enable bit ip.6 0xb8 ps1-sio1 interrupt priority control eicon.7 0xd8 smod1-sio1 baud rate doubler interrupts int2-int5 exif 0x91 int2-int5 interrupt flags eie 0xe8 int2-int5 interrupt enables eip.0-3 0xf8 int2-int5 interrupt priority control int6 eicon.3 0xd8 int6 interrupt flag eie.4 0xe8 int6 interrupt enable eip.4 0xf8 int6 interrupt priority control wakeup# eicon.4 0xd8 wakeup# interrupt flag eicon.5 0xd8 wakeup# interrupt enable idle mode pcon.0 0x87 ez-usb power down (suspend)
ez-usb series 2100 trm v1.8 chapter 2. ez-usb cpu page 2-7 members of the ez-usb family that provide pins to expand 8051 memory provide sepa- rate non-multiplexed 16-bit address and 8-bit data busses. this differs from the standard 8051, which multiplexes eight device pins between three sources: io port 0, the external data bus, and the low byte of the address bus. a standard 8051 system with external mem- ory requires a de-multiplexing address latch, strobed by the 8051 ale (address latch enable) pin. the external latch is not required by the non-multiplexed ez-usb chip, and no ale signal is needed. in addition to eliminating the customary external latch, the non- multiplexed bus saves one cycle per memory fetch cycle, further improving 8051 perfor- mance. a standard 8051 user must choose between using port 0 as a memory expansion port or an io port. the an2131q provides a separate io system with its own control registers (in external memory space), and provides the io port signals on dedicated (not shared) pins. this allows the external data bus to be used to expand memory without sacrificing io pins. the 8051 is the sole master of the memory expansion bus. it provides read and write sig- nals to external memory. the address bus is output-only. a special fast transfer mode gives the ez-usb family the capability to transfer data to and from external memory over the expansion bus using a single movx instruction, which takes only two cycles (eight clocks) per byte. the internal 8051 reset signal is not directly controlled by the ez-usb reset pin. instead, it is controlled by an ez-usb register bit accessible to the usb host. when the ez-usb chip is powered, the 8051 is held in reset. using the default usb device (enu- merated by the usb core), the host downloads code into ram. finally, the host clears an ez-usb register bit that takes the 8051 out of reset. the ez-usb family also operates with external non-volatile memory, in which case the 8051 exits the reset state automatically at power-on. the various ez-usb resets and their effects are described in chapter 10, "ez-usb resets." 2.10 internal bus 2.11 reset
page 2-8 chapter 2. ez-usb cpu ez-usb series 2100 trm v1.8
ez-usb series 2100 trm v1.8 chapter 3. ez-usb memory page 3-1 3 ez-usb memory ez-usb devices divide ram into two reg ions, one for code and data, and the other for usb buffers and control registers. figure 3-1. ez-usb 8-kb memory map - addresses are in hexadecimal figure 3-2. ez-usb 4-kb memory map - addresses are in hexadecimal 3.1 introduction 1b40/7b40 data (rd/wr) ram code(psen) ram i ea=0 (6,976 bytes) registers/bulk buffers 7fff 7b40 0000 16 x 64-byte bulk endpoint buffers (1,024 bytes) usb control registers (192 bytes) 1f40/7f40 1fff/7fff 1f3f/7f3f 1b3f data (rd/wr) ram if isodisab=1 2000 27ff registers/bulk buffers 1fff 1b40 7c00 code(psen) and data (rd/wr) ram (4096 bytes) registers/bulk buffers 7fff 7b40 0000 13 x 64-byte bulk endpoint buffers (832 bytes) usb control registers (192 bytes) 7f40 7fff 7f3f 0fff
p a g e 3 -2 c h a p t e r 3 . e z-usb m e m o ry e z -usb s e r i e s 2 1 0 0 t r m v 1.8 figur e 3-1 illu s t rates the two in t e rnal e z-u s b ra m regi o n s. 6,976 bytes of g e neral-pur- pose ram occupy addres s es 0x0000-0x1b3 f . this r am is loadable by the e z -usb core or i 2 c bus e e p r om, and contains 8051 code and data. the e z-usb ea (extern a l ac c ess) pin controls w h e re th e bottom segmen t of code ( pse n ) memory is l o catedinsid e (ea=0) or ou t side (ea= 1 ) the e z-usb chip. if the e z pin is t ied lo w , the e z -usb co r e internally o rs t h e two 805 1 read signals p sen and rd for this region , so that code and data share the 0x0000-0x1b3f memory spac e . if ea=1, all cod e (ps e n) memory is external. 1,02 4 byte s o f ram a t 0x7b40-0x7f3f impl e m e n t th e s ixteen bulk endpoin t bu f fe r s . 192 additiona l byt e s a t 0x7f40-0x7f f f contain t h e usb contro l registers . th e 805 1 re a d s and w r it e s this m emory u sing the m o vx instruction . in th e 8 - kb r a m e z-usb version, the 1,024 bulk endpoin t bu f fer bytes a t 0x7b40-0x7f3f also appear at 0x1b40-0x1 f 3f . this aliasing allows unused bulk endpoi n t bu f fer memory to be added contiguou s ly to the data memo r y , as illustrat e d figur e 3-3. the memory s p a ce at 0x1f40-0x1fff should not be used. even though the 8051 can a c ce s s e z-usb endpoint b u f f e rs at either 0x1b40 or 0x7b40, the fi r mware shoul d b e written to a ccess this memor y only at 0x7b40-0x7 f f f to maintain compatib i lity with fu t ure versions o f ez-usb t hat contain m ore than 8 k b of r am. future versions will have the bul k buffer space at 0x7b40 - 0 x 7 f3f only. 3.2 8051 memo r y abo u t 8051 m emory spaces the 8051 par t it i ons its me m ory spaces in t o code memory and d ata m emory. the 8051 rea d s code memory u sing the signal p sen# (program s t ore enable), reads data memory u s ing the signal r d# (data read) and w r ites d a t a memory using the sign a l wr# (data w rite). the 8051 movx ( m ove external) i nstruction generat e s rd# or wr# strobes. p s en# is a de d i cated pin, while t he rd# and wr# signals share pins wit h two io port s ignals: pc7/rd and p c6/wr. therefo r e , i f expanded m e mory i s u s ed, the po r t pins pc7 and p c6 are no t available to the s y stem.
ez-u s b s e r i e s 2 1 0 0 t r m v 1.8 c h a p t e r 3. e z-u s b m e mory p a g e 3-3 f i g u r e 3 - 3 . u nu s ed b u l k e n d p o int b u f f ers ( s h ad e d) u s e d a s d a t a memory in the example shown in f igur e 3-3, only endpoint s 0-in through 3 - i n are used for the usb function, so th e d ata ra m (shaded) can be extended t o 0x1d7f. i f an applica t ion use s none of the 16 ez- u s b isochronous endpoin t s, the 8051 c a n set the i sodisab b i t in the i s o c tl regis t e r to dis a b le all 16 isoc h ronous endpoints, and make the 2-kb o f iso c h ronous f i fo ram av a i lable as 8051 data ram at 0x2000-0x27 f f. setting i s odisa b = 1 is a n all or nothing choice, as al l 1 6 isochro nou s endpoin t s are dis- abled. an application that s ets this bit must never attempt to tr a nsf e r d a ta over an isochro- nous endpoint. the memory map f igures in the r e mainder of this chapter a s sume that isod i s a b=0, the default (and normal) case. ep0in ep0out ep1in ep1out ep2in ep2out ep3in ep3out ep4in ep4out ep5in ep5out ep6in ep06ut ep7in ep07ou t 1b40 code/data ram 0000 1b3f 1b80 1bc0 1c00 1c40 1c80 1cc0 1d00 1d40 1d80 1dc0 1e00 1e40 1e80 1ec0 1f00 1f40
page 3-4 chapter 3. ez-usb memory ez-usb series 2100 trm v1.8 the 80-pin ez-usb package provides a 16-bit address bus, an 8-bit bus, and memory control signals psen#, rd#, and wr#. these signals are used to expand ez-usb memory. figure 3-4. ez-usb memory map with ea=0 figure 3-4 shows that when ea=0, the code/data memory is internal at 0x0000-0x1b40. external code memory can be added from 0x0000-0xffff, but it appears in the memory map only at 0x1b40-0xffff. addressing external code memory at 0x0000-0x1b3f when ea=0 causes the ez-usb core to inhibit the #psen strobe. this allows program memory to be added from 0x0000-0xffff without requiring decoding to disable it between 0x0000 and 0x1b3f. 3.3 expanding ez-usb memory code & data (psen,rd,wr) registers(rd,wr) external code memory (psen) external data memory (rd, wr) external data memory (rd,wr) 1b40 inside ez-usb outside ez-usb 8000 7b40 0000 1f3f ffff (note 2) note 1: ok to populate dat a m emory here--rd# , wr#, cs# and oe# pins are inactive. (note 1) unused bulk buffers (rd,wr) note 2: ok to populate code memory h ere--no psen# st robe is gene rated. (note 1) 1fff 2000
ez-u s b s e r i e s 2 1 0 0 t r m v 1.8 c h a p t e r 3. e z-u s b m e mory p a g e 3-5 the internal block a t 0x7b40-0x7fff (labeled r e g i s ters) con t a i n s the bulk bu f fer mem- ory and e z - usb control registers. as p r evio u s ly mentioned, they are a l i ased at 0x1b40- 0x1f f f to allow adding unused b u lk b u ffe r ram to gener a l-purpos e memory. 8051 code shoul d a c ce s s this memory onl y a t the 0x7b40-0x7bf f addr e ss e s . ext e r nal r a m ma y be added from 0x0000 to 0x f f f f, bu t the regions shown by note 1 i n f i gure 3 - 4 are ignored; no external strobes o r s e l e ct s ig n a ls a r e generated when the 8051 execut e s a movx instruction that a d d r e s ses t he s e reg i ons. th e e z -usb core automatically gates th e standard 8051 rd# a n d wr # signal s to exclude sele c tio n of externa l memory that e x i sts inter n a l to t h e e z-us b pa r t . the p s en# signa l is also available on a pin f o r connection to external code me m ory. so m e 8051 systems implement exter n al memory th a t is us e d as both data and program memo r y . the s e systems must logical l y or t h e psen# and rd# si g n als to qualify the chip e n able and output ena b l e s i g n als of t he extern a l mem o ry. to s a ve this logic, th e ez- usb core provides two additional con t rol s ignals, cs# and oe#. the equations for these signals ar e as foll o ws: ? cs# = rd# or wr# o r psen# ? oe# = rd# o r psen# because the rd#, wr#, and p sen# signals are a lready qu a lified by the a ddr e sses allo- cated to externa l m emo r y, the s e strob e s are active only when ex t ernal memory is a c cessed. 3.4 c s# and oe# signals
page 3-6 chapter 3. ez-usb memory ez-usb series 2100 trm v1.8 figure 3-5. ez-usb memory map with ea=1 when ea=1 (figure 3-5), all code (psen) memory is external. all internal ez-usb ram is data memory. this gives the user over 6-kb of general-purpose ram, accessible by the movx instruction. note figures 3-4 and 3-5 assume that the ez-usb chip uses isochr onous endpoints, and there- fore that the isodiab bit (isoctl.0) is lo. if isodisab=1, additional data ram appears internally at 0x2000- 0x27ff, and the rd#, wr#, cs#, and oe# signals are modified to exclude this memory space from external data memory. data (rd,wr) registers(rd,wr) external code memory (psen) external data memory (rd, wr) external data memory (rd,wr) 1b40 inside ez-usb outside ez-usb 8000 7b40 0000 1f3f ffff note 1: ok to populate data memory here--rd#, wr#, cs# and oe# are inactive. (note 1) unused bulk buffers (rd,wr) (note 1) 1fff 2000
ez-usb series 2100 trm v1.8 chapter 3. ez-usb memory page 3-7 the ez-usb 8-kb masked rom and 32-kb masked rom memory maps are shown in figures 3-6 and 3-7. figure 3-6. 8-kb rom, 2-kb ram version ez-usb rom versions contain program memory starting at 0x0000. in these versions, the internal ram is implemented as data-only memory. code for this rom version can be developed and tested using the an2131q with an external code memory (ea=1, figure 3-5). as long as the 8051 limits internal ram access to 0x0000 -0x07ff and accesses the ez-usb registers and bulk data at 0x7b40- 0x7fff, the code in the external memory will be the identical image of the code that will ultimately be internal at 0x0000- 0x1fff in the rom ve rsion. 3.5 ez-usb rom versions data (rd,wr) registers(rd,wr) external code memory (psen) external data memory (rd, wr) external data memory (rd,wr) 07ff inside ez-usb outside ez-usb 8000 7b40 0000 2000 ffff note 1: ok to populate data memory here, but no rd# or wr# strobes are generated. (note 1) (note 1) internal code memory(psen) (note 2) note 2: ok to populate code memory here, but no psen# strobe is generated. 0800
page 3-8 chapter 3. ez-usb memory ez-usb series 2100 trm v1.8 figure 3-7. 32-kb rom, 4-kb ram version the ez-usb 32-kb rom version contains program memory from 0x0000 through 0x7fff, and data memory from 0x0000 thr ough 0x0fff. code for this rom version can be developed and tested using the an2131q with an external code memory (ea=1, figure 3-5). as long as the 8051 limits internal ram access to 0x0000- 0x0fff and accesses the ez-usb registers and bulk data at 0x7b40- 0x7fff, the code in the external memory will be the identical image of the code that will ultimately be internal at 0x0000- 0x7fff in the rom ve rsion. data (rd,wr) registers(rd,wr) external code memory (psen) external data memory (rd, wr) external data memory (rd,wr) 0fff inside ez-usb outside ez-usb 8000 7b40 0000 1000 ffff note 1: ok to populate data memory here, but no rd# or wr# strobes are generated. (note 1) (note 1) internal code memory(psen) (note 2) note 2: ok to populate code memory here, but no psen# strobe is generated. 7fff
ez-usb series 2100 trm v1.8 chapter 4. ez-usb input/output page 4-1 4 ez-usb input/output the ez-usb chip provides two input-output systems: ? a set of programmable io pins ? a programmable i 2 c controller this chapter begins with a description of the programmable io pins, and shows how they are shared by a variety of 8051 and ez-usb alternate functions such as uart, timer and interrupt signals. the i 2 c controller uses the scl and sda pins, and performs two functions: ? general-purpose 8051 use ? boot loading from an eeprom this chapter describes both the programming information for the 8051 i 2 c interface, and the operating details of the i 2 c boot loader. the role of the boot loader is described in chapter 5, "ez-usb enumeration and renumeration ? ." 4.1 introduction note 2.2-kb to 4.7-kb pullups are required on the sda and scl lines.
p a g e 4 - 2 c h a p t e r 4 . e z - u s b i n p u t/ o u t pu t e z - u s b s e r i es 2 1 0 0 t rm v 1 . 8 f i g u re 4 - 1 . ez- u sb i n p u t / o u t p ut pin the e z-usb family implem e nt s its io po r ts using me m ory - mapped registers . t h is is in cont r a st to a standard, which u s es sfr bi t s for i nput/output. figur e 4-1 shows the basic structure of an e z -usb i o pin. t wenty-f o u r io pins are grouped into three 8-bi t ports named p o r t a , p o r tb, and p ortc. t he an2131q has all t hre e po r ts, while the an 2131 s h a s p o r t b , p o r t c , a nd two p o r t a b i ts. the 8051 a c c e s s es io pins using th e t hree contr o l bits shown in figure 4 - 1: o e, out, a nd pins. the o ut bit wri t e s output data to a registe r , t h e oe bit turns on the output b u f f er, and the p i ns b i t indicates the stat e of the pin. t o configure a pin as an input, the 8051 se t s oe=0 to tur n off the out p u t bu f fe r . to con- f igure a pin as an output, the 8051 set s oe=1 to turn on the outpu t bu f f er, and writes data to the out regist e r . t h e pins b i t ref l ects the actual p i n value r egardless of the value of oe. a fourth control bit (in p o r tacfg, p o r t b cfg , p o r t ccfg regis t e r s) determi n es whether a port pin is general-purpo s e input/output (gpi o ) as shown in figu r e 4-1, or connected to an alte r n at e 805 1 o r ez-us b func t i on . t a ble4-1 li s ts the a lter n a t e functions available on th e io pins . figure 4-1 sho w s th e re g i sters and bi t s associated with t he io po r ts. 4.2 i o ports reg out pin pins oe
ez-usb series 2100 trm v1.8 chapter 4. ez-usb input/output page 4-3 depending on whether the alternate function is an input or output, the io logic is slightly different, as shown in figure 4-2 (output) and figure 4-3 (input). the last column of table 4-1 indicates which figure applies to each pin. table 4-1. io pin functions for portxcfg=0 and portxcfg=1 portxcfg bit = 0 portxcfg bit = 1 signal signal direction description figure pa0 t0out out timer 0 overflow pulse 4-2 pa1 t1out out timer 1 overflow pulse 4-2 pa2 oe# out ez-usb output enable 4-2 pa3 cs# out ez-usb chip select 4-2 pa4 fwr# out ez-usb fast write strobe 4-2 pa5 frd out ez-usb fast read strobe 4-2 pa6 rxd0out out uart0 mode 0 data out 4-2 pa7 rxd1out out uart1 mode 0 data out 4-2 pb0 t2 in timer 2 clock input 4-3 pb1 t2ex in timer 2 capture/reload 4-3 pb2 rxd1 in uart1 receive data 4-3 pb3 txd1 out uart1 transmit data 4-2 pb4 int4 in interrupt 4 4-3 pb5 int5 in interrupt 5 4-3 pb6 int6 in interrupt 6 4-3 pb7 t2out out timer 2 overflow pulse 4-2 pc0 rxd0 in uart0 receive data 4-3 pc1 txd0 out uart0 transmit data 4-2 pc2 int0# in interrupt 0 4-3 pc3 int1# in interrupt 1 4-3 pc4 t0 in timer 0 clock input 4-3 pc5 t1 in timer 1 clock input 4-3 pc6 wr# out write strobe 4-2 pc7 rd# out read strob 4-2
p a g e 4 - 4 c h a p t e r 4 . e z - u s b i n p u t/ o u t pu t e z - u s b s e r i es 2 1 0 0 t rm v 1 . 8 f i g u re 4 - 2 . a l t e r n a t e f u n c t i o n i s a n ou t put refer r ing to figur e 4-2, when p o r t c f g =0, the io po r t is selected. in th i s case t he a lter- nate function (shade d ) is d i sconnected and the pin functions exactly as shown in figure 4 - 1. when po r tcfg=1, the alternate funct i on is connected to the io pin and the output r eg i s ter and b u ff e r are dis c onnected. n o te that t h e 8051 c a n s t i ll read the state of the pin, and thus the alternate func t ion v alue. f i g u re 4- 3 . a l t e rn a t e f u n ct i o n i s a n in pu t refer r ing to figu r e 4-3, when po r t c f g=0, the io port i s selected. this is the g e n eral i o por t shown in figur e 4-1 with one important d if f erence t h e a lter n ate function is always listening . whether the po r t pin is s e t for output or input, the pin sign a l also drives the a l ternate fu n c tion. 8051 fir m w a r e s hould ensure that if the alternate function is not used ( if the pin is gpio only), the a l t e rnate input function is disa b led. fo r example, suppo s e the pb4/int4 pin is confi g u red f o r pb4. th e pin signal is also routed to int4. i f i nt 4 is not used by the application, it s hould not be enabled. alterna- tive l y, enabling int4 could be u seful, allowing io b i t pb4 to t rigger an inter r upt. when po r txcfg=1, the a l ternate function is s e lected. the output registe r a nd buffer are disconne c ted. the pins bit can s t i l l read the pin, and t hus the i nput to the alternate func- tion. r e g out p i n p i n s oe a l t er n ate f u nc t ion o ut p ut out p i n s a l t er n ate f u nc t ion o ut p ut oe r e g p i n portcfg=0 ( port ) portcfg=1 ( alternate function ) r e g out p i n p i n s oe a l t er n ate f u nc t ion i nput out p i n s a l t er n ate f u nc t ion i n put oe r e g p i n portcfg=0 (port) portcfg=1 (altern ate function)
ez-usb series 2100 trm v1.8 chapter 4. ez-usb input/output page 4-5 figure 4-4. registers associated with ports a, b, and c figure 4-4 shows the registers associated with the ez-usb io ports. the power-on default for the portcfg bits is 0, selecting the io port function. the power-on default for the oe bits is 0, selecting the input direction. 4.3 io port registers rxd1out rxd0out frd fw r cs oe t1out t0out portacfg d7 d6 d5 d4 d3 d2 d1 d0 outa pinsa oea t2out int6 int5 int4 txd1 rxd1 t2ex t2 portbcfg outb pinsb oeb rd wr t1 t0 int1 int0 txd0 rxd0 portccfg outc pinsc oec d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0
p a g e 4 - 6 c h a p t e r 4 . e z - u s b i n p u t/ o u t pu t e z - u s b s e r i es 2 1 0 0 t rm v 1 . 8 the e z-u s b core contains an i 2 c controlle r for boot loading and general- p u rpose i 2 c bus inte r fa c e. t h i s c o n troller uses the scl (serial cloc k ) and s d a (serial data) pins. chap- ter 5, "ez - usb enumeratio n an d r e nume r a tio n ? ," de s cribes ho w the boot load operates at pow e r -on to r e ad the contents o f an external s e ria l eepr o m in order to de t er m ine the ini t i a l e z-u s b configuration. the boot loader operates automaticall y w hile the 8051 is held in r e set. the last sect i on of this chapter desc r ibes the oper a t i ng d etails of the boot loade r . a f t e r the boot sequen c e complet e s and the 8051 is brought out of r eset, the g e n eral-pur- pose i 2 c control l e r is available to the 8051 f o r i n t e rface t o e xternal i 2 c devices su c h as othe r e epro m s , io chips, audio/video control chips, etc. f igu r e 4-5 . g e n e r a l i 2 c t r a n s f e r figur e 4-5 illu s t rates the waveforms for an i 2 c transfe r . s c l and s da are open-drain e z - u s b pins, wh i ch must be pulled up to vcc with external r esistors. t h e e z - u sb chip is an i 2 c bus ma s ter onl y , m e aning that i t synchronizes d a ta transfers by generating clock pulses on s c l by driving l o w. o n ce the master d riv e s scl l o w, external slave devices can als o drive s cl low to extend clock c ycle times. t o synchronize i 2 c data, s e r ial data (sda) is p e rmitted to change state only while scl is lo w , an d mu s t b e valid whil e scl is high . t w o excepti o n s to t h i s r u l e ar e used t o gene r a te s t a r t and s t o p conditions. a s t art condition is defin e d as sda going low while sc l is high, an d a s t o p condition is d e fine d a s sda going high while s c l is hi g h . data is sent ms b first. d u ring the l a st bi t t ime (clock #9 i n figu r e 4-5) t he m a s t er ( ez-usb) f loats the sda line to allow t he slave to acknowledge t he t r a nsfer by pull i ng sda low. 4.4 i 2 c c o ntro l l er 4.5 8051 i 2 c controller 123 4 56 7 8 9 d7 ac k d6 d5 d4 d3 d2 d1 d0 start stop sda scl
e z - u s b s e r i e s 2 1 0 0 t rm v 1 . 8 c h a p t e r 4 . e z - u s b i n p u t/ o u t p u t p a g e 4 - 7 f igu r e 4 - 6 . g e n e r a l f c t r a n s f e r the fi r s t byte o f an i 2 c bus tran s action conta i ns the address of the desir e d p e r ipheral. figur e 4-6 shows the format for this fi r s t byte, which is sometimes called a con t r o l byte. a ma s ter s ends t h e bit sequen c e shown in figure4-6 a fter sending a s t a r t condition. the mast e r uses this 9-b i t sequence to s e l ect an i 2 c periphe r a l at a particular addr e ss, to establish the t ra n sfer d i r ection (us i ng r/ w #), and t o d e term i ne if t h e periph e ral is present by te s ting f o r ack#. the fou r most s igni f icant bit s sa3-sa0 a re the p e ripheral chi p s slave add r ess. i 2 c devic e s a re pre-as s ig n e d s lav e addre s ses b y device type, f or examp l e slav e a ddress 1010 is as s igned to e eproms. the th r e e bi t s da2-da0 usually re f le c t t he states of i 2 c device address pins. devic e s with t h r e e addr e ss pi n s can be strapped to allow eight distinct addres s es for the s ame devi c e type. the eighth b i t (r/ w #) s e ts the d i rec t io n for t h e ensu- ing data t ransf e r, 1 f o r master read, and 0 for master write. mo s t a ddr e ss tra n s f e rs a r e fol- lowed by one o r m o re data t ra n s f e r s, with th e s top cond i tion generate d after t he l as t data byte is transfer r ed. in figu r e 4-6, a read t ra n s f er fol l ows the addres s b y t e (at clock 8, t he m a s t e r sets the r/ w# bit high, ind i cating read). at clock 9, the p eripheral d e v ice responds to it s a ddress by a s serting a ck. at clock 10, the m a ster floats s d a and issues scl pul s es to clock in sda data supplied by t h is slave. assuming the 1 2 - m hz c ry s t a l used by the e z -usb f am i ly, the s c l frequency is 90.9 khz, giving an i 2 c transfer rate o f 11 ms per b it. m u ltiple i 2 c bus m a s ters the e z -usb chip acts on l y a s an i 2 c bus maste r , never a s l ave. how e ve r, the 8051 can det e ct a second ma s t e r by ch e cking fo r berr=1 (section 4.5, "8051 i 2 c controller"). 1 2 3 4 56 7 8 9 sa3 ac k sa2 sa1 sa0 da2 da1 da0 start sda scl d7 d6 10 11 r/w
page 4-8 chapter 4. ez-usb input/output ez-usb series 2100 trm v1.8 figure 4-7. fc registers the 8051 uses the two registers shown in figure4-7 to conduct i 2 c transfers. the 8051 transfers data to and from the i 2 c bus by writing and reading the i2dat register. the 12cs register controls i 2 c transfers and reports various status conditions. the three con- trol bits are start, stop, and lastrd. the remaining bits are status bits. writing to a status bit has no effect. 4.6.1 start the 8051 sets the start bit to 1 to prepare an i 2 c bus transfer. if start=1, the next 8051 load to i2dat will generate the start condition followed by the serialized byte of data in i2dat. the 8051 loads data in the format shown in figure 4-5 after setting the start bit. the i 2 c controller clears the start bit during the ack interval (clock 9 in figure 4-5). 4.6.2 stop the 8051 sets stop=1 to terminate an i 2 c bus transfer. the i 2 c controller clears the stop bit after completing the stop condition. if the 8051 sets the stop bit during a byte transfer, the stop condition will be generated immediately following the ack phase of the byte transfer. if no byte transfer is occurring when the stop bit is set, the stop condition will be carried out immediately on the bus. data should not be written to i2cs or i2dat until the stop bit returns low. in the 2122/ 2126 only, an interrupt request is available to signal that stop bit transmission is complete. 12cs i 2 c control and status 7fa5 b7 b6 b5 b4 b3 b2 b1 b0 start stop lastrd id1 id0 berr ack done 12dat i 2 c data 7fa6 b7 b6 b5 b4 b3 b2 b1 b0 d7 d6 d5 d4 d3 d2 d1 d0 4.6 control bits
ez-usb series 2100 trm v1.8 chapter 4. ez-usb input/output page 4-9 4.6.3 lastrd to read data over the i 2 c bus, an i 2 c master floats the sda line and issues clock pulses on the scl line. after every eight bits, the master drives sda low for one clock to indicate ack. to signal the last byte of the read transfer, the master floats sda at ack time to instruct the slave to stop sending. this is controlled by the 8051 by setting la strd=1 before reading the last byte of a read transfer. the i 2 c controller clears the lastrd bit at the end of the transfer (at ack time). after a byte transfer the ez-usb controller updates the three status bits berr, ack, and done. if no stop condition was transmitted, they are updated at ack ti me. if a stop condition was transmitted they are updated after the stop c ondition is transmitted. 4.7.1 done the i 2 c controller sets this bit whenever it completes a byte transfer, right after the ack stage. the controller also generates an i 2 c interrupt request (8051 int3) when it sets the done bit. the i 2 c controller clears the done bit when the 8051 reads or writes the i2dat register, and the i 2 c interrupt request bit whenever the 8051 reads or writes the i2cs or i2dat register. 4.7.2 ack every ninth scl of a write transfer, the slave indicates reception of the byte by asserting ack. the ez-usb controller floats sda during this time, samples the sda line, and updates the ack bit with the complement of the detected value. ack=1 indicates acknowledge, and ack=0 indicates not-acknowledge. the ez-usb core updates the ack bit at the same time it sets done=1. the ack bit s hould be ignored for read trans- fers on the bus. note setting lastrd does not automatically generate a stop condition. the 8051 should also set the stop bit at the end of a read transfer. 4.7 status bits
p a g e 4 - 1 0 c h a p t e r 4 . ez-u s b i n p ut / o u t put e z -usb s e r i e s 2 1 0 0 t r m v 1.8 4.7.3 b e rr this bit ind i c a tes an i 2 c bus err o r. be r r=1 indica t es that the r e w a s bu s contention, which resul t s when an outside devic e dri v es the b u s lo w h en it s hou l dn t , or when another bus ma s t e r wins arbitration, taking control of the bus. berr is cleared when the 8051 reads or writes the i 2 d a t r e g is t er. 4.7.4 id1, i d 0 the s e bits are s e t by the boot load e r (section 4.10, "i 2 c boo t loader") t o indicat e whether an 8-bit a dd r ess or 16-bit add r e s s ee p rom at s l ave address 000 o r 001 was detected at power-on. they are normally used only for debug pu r pos e s . tabl e 4-3 shows the encod- ing fo r these bits. t o s end a mult i ple byte data reco r d over the i 2 c bus, follow these s t eps: 1 . set the s t a r t bit. 2 . w r i te the pe r ipheral address and d i r e ction=0 (for w rite) to i 2 d at. 3 . w ait for done= 1 * . i f ber r =1 or ack=0, g o to step 7. 4 . load i2d a t with a data byte. 5 . w ait for done= 1 * . i f ber r =1 or ack=0 go to step 7. 6 . repe a t steps 4 and 5 fo r each byte until all bytes ha v e b e en t ransferred. 7 . set stop=1. * if the i 2 c in t e r rupt (8051 int3 ) is enabled, each w a i t f o r d one = 1 s t ep can be i nter- rupt driven, and handled by an interrupt serv i ce rout i ne. see section 9.12, "i 2 c inter- rupt for more d e t a i l s regarding the i 2 c interrupt. 4.8 sending i 2 c data
ez-usb series 2100 trm v1.8 chapter 4. ez-usb input/output page 4-11 to read a multiple-byte data record, follow these steps: 1. set the start bit. 2. write the peripheral address and direction=1 (for read) to i2dat. 3. wait for done=1*. if berr=1 or ack=0, terminate by setting stop=1. 4. read i2dat and discard the data. this initiates the first burst of nine scl pulses to clock in the first byte from the slave. 5. wait for done=1*. if berr=1, terminate by setting stop=1. 6. read the data from i2dat. this initiates another read transfer. 7. repeat steps 5 and 6 for each byte until ready to read the second-to-last byte. 8. before reading the second-to-last i2dat byte, set lastrd=1. 9. read the data from i2dat. with lastrd=1, this initiates the final byte read on the i 2 c bus. 10. wait for done=1*. if berr=1, terminate by setting stop=1. 11. set stop=1. 12. read the last byte from i2dat immediately (the next instruction) after setting the stop bit. this retrieves the last data byte without initiating an extra read transac- tion (nine more scl pulses) on the i 2 c bus. * if the i 2 c interrupt (8051 int3) is enabled, each wait for done=1 step can be inter- rupt-driven, and handled by an interrupt service routing. see section 9.12, "i 2 c inter- rupt for more details regarding the i 2 c interrupt. 4.9 receiving i 2 c data
page 4-12 chapter 4. ez-usb input/output ez-usb series 2100 trm v1.8 when the ez-usb chip comes out of reset, the ez-usb boot loader checks for the pres- ence of an eeprom on its i 2 c bus. if an eeprom is detected, the loader reads the first eeprom byte to determine how to enumerate (specifically, whether to supply id infor- mation from the ez-usb core or from the eeprom). the various enumeration modes are described in chapter 5, "ez-usb enumeration and renumeration ? ." prior to reading the first eeprom byte, the boot loader must set an address counter inside the eeprom to zero. it does this by sending a control byte (write) to select the eeprom, followed by a zero address to set the internal eeprom address pointer to zero. then it issues a control byte (read), and reads the first eeprom byte. the ez-usb boot loader supports two i 2 c eeprom types: ? eeproms with address a[7..4]= 1010 that use an 8-bit address (example: 24lc00, lc01/a, lc02/a). ? eeproms with address a[7..4]= 1010 that use a 16-bit address (example: 24lc00, lc01/a, lc02/a). eeproms with densities up to 256 bytes re quire loading a single address byte. larger eeproms require loading two address bytes. the ez-usb i 2 c controller needs to determine which eeprom type is connectedone or two address bytesso that it can properly reset the eeprom address pointer to zero before reading the eeprom. for the single-byte address part, it must send a single zero byte of address, and for the two-byte address part it must send two zero bytes of address. because there is no direct way to detect which eeprom typesingle or double addressis connected, the i 2 c controller uses the eeprom address pins a2, a1, and a0 to determine whether to send out one or two bytes of address. this algorithm requires that the eeprom address lines are strapped as shown in table4-2. single-byte-address eeproms are strapped to address 000 and double-byte-address eeproms are s trapped to address 001. 4.10 i 2 c boot loader
ez-u s b s er i e s 2 1 0 0 t r m v 1.8 c h a p t e r 4 . ez-u s b i n p ut / o u t put p a g e 4 - 13 * t hi s e e pro m d o es n o t h a ve a d d r e s s pi n s the i 2 c con t rolle r p e r fo r ms a three-step test at power-on to d e t e rmine whether a o n e-byte- address or a two-byte - a d d ress e epr o m is attached. this test pr o c eeds a s follows: 1 . the i 2 c contr o ller sends out a read c urrent addr e ss command to i 2 c s ub-addre s s 00 0 (10100001). if n o a ck i s r eturned, t h e controller proceeds t o ste p 2. if ack is r eturned, the one-byt e - addre s s device i s indic a t ed. the controller d is c ards the data and pro c eeds to step 3. 2 . the i 2 c contr o ller sends out a read c urrent addr e ss command to i 2 c s ub-addre s s 001 (101000 1 1). i f ack is r eturned, the two-byte-address devic e i s i n d icated. the c ontrolle r di s cards the data and pr o ce e ds to s tep 3. if no ack is returned, the controller assumes that a vali d ee p rom is not connect e d, as s umes the no serial e eprom mode, and ter m in a t e s the boot l o a d . 3 . the i 2 c con t rolle r r ese t s th e eepr o m address point e r to ze r o ( u sing the app r opri- ate numb e r o f address byte s ) , then reads the first e e p rom b y t e. i f it does not r e ad 0xb0 or 0xb2, t he contro l ler assumes t he no seria l ee p rom mode. if it r e ads either 0xb0 or 0xb2, the controller copies the next six bytes into i n ternal storage, and i f it reads 0xb2, it p r oceeds to load t h e ee p ro m con t e nts int o i n ter- nal r am. t a b l e 4 - 2 . s t r a p b o o t e e p r o m a d d r ess l i n e s t o t h e s e values by t es ex a m p le e e p r om a2 a1 a0 16 24 l c00* n / a n / a n / a 128 24 l c01 0 0 0 256 24 l c02 0 0 0 4k 24 l c32 0 0 1 8k 24 l c64 0 0 1
page 4-14 chapter 4. ez-usb input/output ez-usb series 2100 trm v1.8 the results of this power-on test are reported in the id1 and id0 bits, as shown in table 4-3. other eeprom devices (with device address of 1010) can be attached to the i 2 c bus for general purpose 8051 use, as long as they are strapped for address other than 000 or 001. if a 24lc00 eeprom is used, no other eeproms with device address 1010 may be used, because the 24lc00 responds to all eight sub-addresses. table 4-3. results of power-on i 2 c test id1 id0 meaning 0 0 no eeprom detected 0 1 one-byte-address load eeprom detected 1 0 two-byte-address load eeprom detected 1 1 not used
ez-u s b s e r i e s 2 1 0 0 t r m v 1.8 c h a p t er 5. ez- u sb e n u m e r a t i o n a n d r e n u m e r a tion p a g e 5-1 5 e z-usb enum e ra t i o n and r e numeration ? ? ? ? the e z -usb chip i s soft . 8051 code a n d d a ta is stored in intern a l ram, wh i c h is l oaded f rom the host using t h e usb int e rf a ce. periph e r al devi c es that use t h e e z-usb ch i p can operate without rom, epro m , or f l ash memor y , shortening production lead times and making f irmware upda t es a bree z e. t o suppo r t the s o f t f eat u re, t h e e z-usb chip automatically e n u m e rates as a usb device without f ir m ware , so the usb inte r fa c e i t s e l f may be used to download 8051 code and des c r iptor table s . t he e z-us b cor e performs this i n itia l (power-on ) enu m e r atio n an d code download while the 8051 is held i n r e set. this i n i t ial usb device, which supports code download, is called th e " default usb device." a f t e r the code d e scriptor ta b l es have b een downloaded from t h e hos t to ez- u sb ram, the 8051 is brought out of re s e t and begins executing the device cod e . t h e ez-usb device enumerates aga i n, thi s t i m e as the loaded device. this second enumeration is called "renumeratio n ? ," which the e z - usb chip a ccomplishes by electri c ally si mul at ing a phy s ica l d i sconnection and re-connectio n t o t he usb. an e z -usb control bit called "r e num" (renumerated) determines which e n tity, the core o r the 8051, handl e s device reque s ts over endpoint z ero. at powe r - on, the r e n um bit ( us b cs.1) is z e ro, indicating t hat t h e ez-usb core a u t o m a tically handles device r equest s . once the 8051 is running, it c an s et renum=1 to indicate t h at user 8051 code handles subsequent device requ e s ts using its downloade d firmwar e . chapter 7 , "ez - usb endpoint z ero" des c r ibes how the 8051 handles devi c e reque s ts while renum=1. i t is also possibl e for the 8051 to run with renum=0 a n d hav e t h e e z -usb core handle certain endpoint zero re q u e s ts ( see the text box, anoth e r use fo r the d e f ault usb devic e on page 5-2). this chapter deals wit h the various e z - us b sta r t up modes, and de s cribes the def a ul t u sb device that is created at initi a l e numeration. 5.1 i n t roduction
p a g e 5 -2 c h a p t e r 5 . e z-u s b e n u m e r a t i o n a n d r e n u m e r a tion e z -usb s e r i e s 2 1 0 0 t r m v 1.8 the default u s b devi c e c o n sists o f a single u s b configuration containi n g one int e r face ( interfa c e 0) with three a l t ernate settings 0, 1, and 2. the endpoints reported for this device are shown i n table 5-1. n o te that alt e r n a te setti n g zero uses no interrupt or isoch- ronous band w i d th, as r e commend e d by the usb spe c i fication. a nother u se for the def a ult usb device the d e f au l t usb devic e i s established at po w er-on to set up a usb device capable of downloading f irmware into e z - u sb r am. another useful feature of the e z -usb default device is that 8051 code can be writte n t o support t h e a l ready-configured generic usb device. before bringing the 8051 ou t o f reset, t h e ez - usb core enables certain endpoints and r epo r ts them to the h o st via de s c riptors. by utili z ing the usb default machine (b y keeping renum=0), th e 8051 can, with ve r y littl e code, perfor m meaningful usb transfers that use t hese d efaul t endpoint s . th i s ac c e ler a tes t h e usb learnin g curve . t o see an example of how little c ode is a ctu a lly n ecessary, take a look at section 6.11, " polled bul k tra n s fer example." 5.2 the de f ault usb device t a b l e 5 - 1 . ez - usb d e f au lt e n d points e n d p o int type a l t e r n a t e s e t t i n g 0 1 2 m ax i m um pa c ket s i ze ( b y t es) 0 ctl 64 64 64 1 - i n i n t 0 16 64 2 - i n bu l k 0 64 64 2 - out bu l k 0 64 64 4 - i n bu l k 0 64 64 4 - out bu l k 0 64 64 6 - i n bu l k 0 64 64 6 - out bu l k 0 64 64 8 - i n i s o 0 16 256 8 - out i s o 0 16 256 9 - i n i s o 0 16 16 9 - out i s o 0 16 16 10 - in i s o 0 16 16 10 out i s o 0 16 16
ez-u s b s e r i e s 2 1 0 0 t r m v 1.8 c h a p t er 5. ez- u sb e n u m e r a t i o n a n d r e n u m e r a tion p a g e 5-3 for purpo s es of downloading 8051 code, the default usb devi c e re q u ires only con- t r ol endpoint z e ro. nevertheles s , the usb default mach i ne is enhanced to support othe r endpoints as shown i n figure 5-1 (note the alt e rn a te setti n g s 1 and 2 ) . this enhance- ment is provided to allow the developer to get a head start g enerating u s b t raffic and learning the u s b system. al l the descripto r s are automatical l y handl e d b y the ez-usb core, so the developer c an immediate l y st a rt w r iting code t o tr a n s fer data o v e r usb using these pre - con f igured endpoint s . when the e z -usb co r e e s tablish e s the default usb device, it also sets the proper end- point configu r a t ion bits to match the d e s criptor d a ta s upplied b y t h e ez-us b core. for example, bulk endpoints 2, 4, and 6 are i mplemented in the de f a ult u s b dev i c e, so the e z - u s b core sets the co r responding e p val bits. chapter 6 , e z-bulk t ransfers con- tains a d e t a i led explanati o n of the e pval b its. t ables 5-9 through 5-13 show the various d escript o r s returned to the host by th e ez- u sb core when r e nu m =0. these tables de s c r ibe the u s b e ndpoints defined in t abl e 5-1, along with oth e r usb details, and should b e useful to h e lp under s tand the structure of usb d e scripto r s .
p a g e 5 -4 c h a p t e r 5 . e z-u s b e n u m e r a t i o n a n d r e n u m e r a tion e z -usb s e r i e s 2 1 0 0 t r m v 1.8 t abl e 5-2 shows how the e z -usb co r e responds to endpoint zer o re q u ests when renum=0. the usb host enume r a t e s by issuing: ? set_addr e s s ? g et_de s c r iptor ? set_configuration ( to 1) 5.3 e z -usb core response to ep0 d evice req u e sts t a b le 5 - 2 . h ow th e ez-usb c o r e h and l es e p 0 re q ue s t s w he n r e n u m=0 b re q u est name ac t i on: renum=0 0 x00 get s t a t us / device re t urns t w o z e ro b y tes 0 x00 get s t a t us / endpoint su p p l ies e p s ta l l b i t for ind i c ate d ep 0 x00 get s t a t us / i n t er f ace re t urns t w o z ero b y tes 0 x01 clear f e a t u r e / device none 0 x01 clear f e a t u r e /endpoin t clea r s s ta l l b i t for in d i c ate d ep 0 x02 ( r ese r ved) none 0 x03 s e t f e a t ure / de v i c e none 0 x03 s e t f e a t ure e ndpoint se t s s t all b i t f o r i n d i cated ep 0 x04 ( r ese r ved) none 0 x05 s e t ad d ress up d at e s fn a d d r e g ister 0 x06 get de s crip t or su p p l ies in t ernal table 0 x07 s e t des c rip t or none 0 x08 get co n figu r ation re t urn s in t e r nal v a l ue 0 x09 s e t co n f i g u r ation se t s in t e r nal v a lu 0x0a get i n t e r face re t urns in t e r nal v a l ue ( 0 -3) 0x0b s e t i n te r face se t s in t e r nal v a l u e ( 0 -3) 0x0c s ync f rame none v e n d or r e quests 0x0a f irm w are l oad uplo a d/download ram 0x a 1-0x a f re s erved re s erved by c y pre s s sem i co n d uctor all o ther none
ez-u s b s e r i e s 2 1 0 0 t r m v 1.8 c h a p t er 5. ez- u sb e n u m e r a t i o n a n d r e n u m e r a tion p a g e 5-5 as shown i n table5-2, a fter enum e r ati o n , the ez-usb c o r e r e s pond s t o t h e f o l l o wing host r equ e sts. ? set or cle a r a n endpoint s tall ( set/cl e a r feature - endpoint ) . ? read the sta l l status for an endpoi n t (get_status_endpoi n t). ? set/read an 8-bit configuration number (set/get_ c onfiguration). ? set/read a 2-bit interfa c e a l terna t e s et t i n g (set/ge t _ interface). ? download or upload 8051 ram. t o ensure proper operation of the defau l t k eil m o n itor, w h ich u ses s i o -1 (rxd1 and t xd1), never change the following por t config bit s from 1: ? po r tbcfg b its 2 ( r xd 1 ) and 3 ( txd1). t o ensu r e the 8051 pro c ess o r can ac c ess the external sram (i n cluding the kei l monitor), do not change the following bi t s from 1: ? po r tccfg b its 6 ( wr#) and 7 (rd#). t o ensure that no bits are unintentionally change d , all writ e s t o the portxc f g r e gisters should use a read-modify-wr i t e s e ries of ins t ruc t ions. the usb specification pr o v ides fo r v e ndo r - s p e c i f i c re quest s to be sent over c o ntrol endpoint z e ro. the e z-u s b chip us e s th i s feature t o tr a n s fer data between the h o st and ez - u s b ra m . the e z- u sb co r e responds to two fi r mware load requests, a s shown in t ables 5-3 and 5-4. 5.4 f irmwa r e load t a b le 5 - 3. f ir m w a r e d o w nload byte fi e l d v a l u e m e a n ing 8 0 51 r e sponse 0 b m request 0x40 v e n dor re q u e st, out none required 1 bre q uest 0 x a0 f i r mwa r e l oad 2 w v aluel ad d rl s t ar t ing a ddress 3 w v alueh addrh 4 w i ndexl 0x00 5 w i ndexh 0x00 6 wl e nghtl le n l num b er of b y t es 7 wl e ngthh l e n h
page 5-6 chapter 5. ez-usb enumeration and renumeration ez-usb series 2100 trm v1.8 these requests are always handled by the ez-usb core (renum=0 or 1). this means that 0xa0 is reserved by the ez-usb chip, and therefore should never be used for a vendor request. cypress semiconductor also reserves brequest values 0xa1 through 0xaf, so your system should not use these brequest values. a host loader program typically writes 0x01 to the cpucs register to put the 8051 into reset, loads all or part of the ez-usb ram with 8051 code, and finally reloads the cpucs register with 0 to take the 8051 out of reset. the cpucs register is the only usb register that can be written using the firmware download command. firmware loads are restricted to internal ez-usb memory table 5-4. firmware upload byte field value meaning 8051 response 0 bmrequest 0xc0 vendor request, i none required 1 brequest 0xa0 firmware load 2 wvaluel addrl starting address 3 wvalueh addrh 4 windexl 0x00 5 windexh 0x00 6 wlengthl lenl number of bytes 7 wlengthh lenh when renum=1 at power-on at power-on, the renum bit is normally set to zero so that the ez-usb handles device requests over control endpoint zero. this allows the core to download 8051 firm- ware and then reconnect as the target device. at power-on, the ez-usb core checks the i 2 c bus for the presence of an eeprom. if it finds one, and the first byte of the eeprom is 0xb2, the core copies the contents of the eeprom into internal ram, sets the renum bit to 1, and un-resets the 8051. the 8051 wakes up ready-to-run firmware in ram. the required data form at for this load module is described in the next section.
ez-u s b s e r i e s 2 1 0 0 t r m v 1.8 c h a p t er 5. ez- u sb e n u m e r a t i o n a n d r e n u m e r a tion p a g e 5-7 when the e z -usb chip comes ou t o f re s et, th e e z -usb co r e makes a dec i sion abou t how to enumerate based on the contents of an external e e p r om on its i 2 c bus. t abl e 5-5 shows the choi c es . i n table 5- 5 , pid means pr odu c t id, v i d m e ans v e r si o n i d , and did means device id. i f no e e prom is present, or if one i s present but the f irst byte is neither 0xb0 nor 0xb2, the e z -usb core enumerates u sing internal l y stored d e scriptor data, which cont a ins the cypress s e m i c onducto r v id, pid, and did. these i d bytes c ause the ho s t ope r a ting sys- tem to load a cypre s s semiconductor de v i ce driv e r. the e z -u s b core also establ i shes the d e fault usb devic e . this mode is only used f o r code development and debug. i f a s e r ial e eprom is attached to the i 2 c bus and i t s fi r s t byte is 0xb0, the e z -usb co r e enumerates with the same internally stored descriptor data as f o r the no-eepr o m case, but with one d i f f er e nce. it s upp l i e s t h e p i d / v i d / d i d d a t a f r o m s i x b y t e s i n t h e e x t e rnal e eprom rather tha n f rom th e e z - u s b c o r e . the cust o m v id/pid/did in the e ep r om ca u ses the h o st operating system to load a device driver t h at is matched t o the eeprom v i d / p id/did. this ez - u s b operating mode provides a soft usb dev i c e u s ing r e nu- me r a tion ?. i f a s e r ial e eprom is attached to the i 2 c bus and i t s fi r s t byte is 0xb2, the e z -usb co r e t r an s fe r s the contents o f the e e p rom into i n t ernal r a m. the e z-usb c o r e a l s o s e t s the renum bit to 1 to indicate that the 8051 (a n d no t the ez-usb co r e) responds to device r equests over c o n t r o l endpoint z er o ( see the text box, when renum=1 at power- on on page 5- 6 ). theref o r e, all descriptor data, including vid/ d id/pid value s , a r e sup- plied by the 805 1 f i r m w a r e. t h e l a st b y t e loaded f rom th e eepr o m (to the cpuc s reg- ister ) rele a ses th e 8051 r e s e t s i gn a l, a l l owing the e z-u s b chip to come up a s a fully custom device with f i rmware in ram. the fo l lowing sect i ons disc u ss t h ese e nume r a t ion methods in detail. 5.5 e n umeration modes t a b l e 5 - 5. ez- u s b c o r e a c t i o n a t p ower-up fi r s t e e p r om b y t e e z - usb c ore ac t ion not 0 x b0 or 0 x b2 supplies des c r i p t o r s, p i d / v i d / d id f r om ez-usb core. se t s renu m =0. 0x b 0 supplies des c r i p t ors f r o m e z-usb c o r e , p i d / v i d/did f rom e e p ro m . s e t s re n um=0. 0x b 2 lo a ds eeprom in t o e z -u s b r am. sets ren u m=1; t he r e fore 8051 su p pli e s de s c r i p t o r s , p i d/vid/did.
p a g e 5 -8 c h a p t e r 5 . e z-u s b e n u m e r a t i o n a n d r e n u m e r a tion e z -usb s e r i e s 2 1 0 0 t r m v 1.8 in the s implest c a se, no s eri a l eeprom i s p resent on the i 2 c bus, or an e e prom i s p r e sent but its f i rst byte is not 0xb0 or 0xb2. in t his cas e , d e scriptor data is supplied by a table internal to t he e z -u s b core. the e z - u s b chip comes on a s th e usb default devic e , w i t h the id byt e s shown in t abl e 5-6. the usb host qu e r ies the device d u ring enumerati o n , reads the device d e scri p tor, and uses the t abl e 5-6 byt e s to d e t ermine which software driver to load into the operating sys- tem. this i s a major usb f e atu r ed r ivers are dynami c ally matched with dev i ces and automatically loaded when a device is plugged in. the no_ e eprom c a se is t h e simp l est conf i g u ration, but also the m o s t l imiting. this mode is u s ed only for c o de de v elopment, utilizi n g c ypress software tools matched to the i d values in t abl e 5-6. the other ha l f of the i 2 c story the e z -usb i 2 c control l e r serves two purpos e s. fi r s t , as described in this chapte r, it man a g e s t h e s e r i a l eeprom inter f a ce that operates automatic a lly at powe r - o n t o deter- mine the enumera t i on method. second, once the 8051 is up and r unning, t h e 8051 can a c ce s s the i 2 c controll e r for general-purpose u s e. thi s makes a wide r ange o f standard i 2 c p e r ipherals available to a n ez- u s b system. other i 2 c devic e s can be attache d t o the scl and s d a lines of the i 2 c bus a s long as there is no address con f lict wit h the seria l eeprom d e scribed i n this chapte r . chap t e r 4, " e z - usb input / o u tpu t " de s crib e s the gen e r al-purpo s e natu r e of the i 2 c inte r fa c e. 5.6 no serial eeprom t a b le 5 - 6 . e z - u sb dev i c e cha r a c t e r i s t i c s , n o s e r ia l e e p rom ve n d o r id 0 x0 5 4 7 (cy p ress sem i c o n ductor) p r o d u ct id 0 x 2131 (e z -usb) de v ice r elease 0 x x x yy (d e pen d s on revision)
ez-u s b s e r i e s 2 1 0 0 t r m v 1.8 c h a p t er 5. ez- u sb e n u m e r a t i o n a n d r e n u m e r a tion p a g e 5-9 i f, at power-on, the ez - usb core detects an e e p rom connected to its i 2 c port with the value 0xb0 a t addres s 0, th e e z - usb core cop i e s the v endo r i d ( v id), p r odu c t i d ( p i d ) , and d evice i d (did) f rom t h e ee p r o m ( t a bl e 5-7) into inte r na l st o rage . the ez-usb core then suppli e s th e se byt e s to the h o st as part of t h e get_d e script o r-devi c e request. ( the s e s ix byt e s replace only t h e v id/pid/did byt e s in the default usb device d e scrip- to r .) th i s ca u se s a drive r m atched to th e vid/ p id/did value s in the eep r o m , ins t e a d of those in the e z - usb core, to b e loaded into the os. a f t e r in i tial enumeration, the driver downloads 8051 code and usb d e s criptor data into ez - u s b ram an d s tarts the 8051. the code then renumerate s ? to come on as the fully custom device. a recommend e d eep r om f or this applic a tion is the microchip 24lc00, a small (5-pin sot package) inexpensive 16-byte s e ria l eeprom. a 24lc01 (128 bytes) o r 24lc02 (256 bytes) may be s u b stituted for the 24lc00, but as with the 24lc00, only t h e f i r st seven byt e s are used. r emin d er th e e z -usb core us e s th e t a ble 5-6 dat a fo r e num e r a t i on only i f th e renu m bi t is zero . if r enum=1, enumeration data is supplied by 8051 code. 5.7 ser i al e e p rom pr e s en t, first b yte is 0x b 0 t a b l e 5 - 7 . e e pr o m d a t a f or m a t for b0 load e e p r o m a d dress c o nt e nts 0 0xb0 1 v en d o r i d ( v id) l 2 v en d o r i d ( v id) h 3 p r od u ct id (pid) l 4 p r od u ct id (pid) h 5 de v i c e i d (d i d ) l 6 de v i c e i d (d i d ) h 7 not u s ed
p a g e 5 - 1 0 c h a p t e r 5 . e z-u s b e n u m e r a t i o n a n d r e n u m e r a tion e z -usb s e r i e s 2 1 0 0 t r m v 1.8 i f, at powe r -on, the ez - usb core detects an e e p rom connected to its i 2 c port with the valu e 0xb2 at address 0; the e z -usb co r e loads the e e p r om data into e z-u s b ram. i t als o s ets th e r enum bi t t o 1, causing device re q u e s ts to b e f ielde d b y th e 805 1 i nstea d of the e z -usb core. the e e p r om data format is shown i n table 5-8. th e first byt e tells th e e z -usb cor e t o cop y e eprom da t a i nto r a m. the nex t s i x bytes (1-6) are igno r ed ( s ee the text box, vid/p i d/did in a b 2 eepr o m on page 5-11). 5.8 ser i al e e p rom pr e s en t, first b yte is 0x b 2 t a b l e 5 - 8 . e e pr o m d a t a f or m a t for b2 load e e p r om a d dress c o nt e nts 0 0xb2 1 v e n dor id ( v i d ) l 2 v e n dor id ( v i d ) h 3 pro d uct id ( p id) 4 pro d uct id ( p id) 5 device i d ( d i d) l 6 device i d ( d i d) h 7 l e ngth h 8 l e ngth l 9 s t ar t addr h 10 s t ar t addr l - - - da t a block - - - - - - l e ngth h - - - l e ngth l - - - s t ar t addr h - - - s t ar t addr l - - - da t a block - - - - - - 0x80 - - - 0x01 - - - 0x7f - - - 0x92 - - - l a st 00000000
ez-usb series 2100 trm v1.8 chapter 5. ez-usb enumeration and renumeration page 5-11 one or more data records follow, starting at eeprom address 7. the maximum value of length h is 0x03, allowing a maximum of 1,023 bytes per record. each data record con- sists of a length, a starting address, and a block of data bytes. the last data record must have the msb of its length h byte set to 1. the last data record consists of a single-byte load to the cpucs register at 0x7f92. only the lsb of this byte is significant 8051res (cpucs.0) is set to zero to bring the 8051 out of reset. serial eeprom data can be loaded into two ez-usb ram spaces only. ? 8051 program/data ram at 0x0000-0x1b40. ? the cpucs register at 0x7f92 (only bit 0, 8051 reset, is host-loadable). three ez-usb control bits in the usbcs (usb control and status) register control the renumeration ? process: discon, discoe, and renum. figure 5-1. usb control and status register vid/pid/did in a b2 eeprom bytes 1-6 of a b2 eeprom can be loaded with vid/pid/did bytes if it is desired at some point to run the 8051 program with renum=0 (ez-usb core handles device requests), using the eeprom vid/pid/did rather than the cypress semiconductor val- ues built into the ez-usb core. 5.9 renumeration ? ? ? ? usbcs usb control and status 7fd6 b7 b6 b5 b4 b3 b2 b1 b0 wa k e s r c - - - discon discoe renum sigrsume r/w r r r r/w r/w r/w r/w 00000100
p a g e 5 - 1 2 c h a p t e r 5 . e z-u s b e n u m e r a t i o n a n d r e n u m e r a tion e z -usb s e r i e s 2 1 0 0 t r m v 1.8 f i g u r e 5 - 2. d is c o n ne c t p i n logic the logic for the d i s c on and d i s coe bi t s is shown in figure5-2 . to s i m u late a usb disconne c t, the 8051 w r it e s the value 00001010 t o us b cs. t h i s floa t s the d i s con# pin, and provid e s an i n t ernal d i s c o n signal to the usb core that cau s es it t o perform discon- nect h o u sekeeping. t o re-connect to usb, the 8051 writes t h e value 00000110 to u s bcs. this presents a logic hi to the discon# pin, enab l es the outpu t bu f f er, and s ets the ren u m bit hi to indicate t h a t the 8051 (and not t he usb co r e ) is now in control fo r u s b tr a nsf e rs. this ar r ang e m en t a l lows connectin g the 1,500-oh m r e sisto r directl y between th e discon # pin and the usb d+ line ( figure 5-3). f i g u r e 5 - 3 . t y p i c al d i s co n n e c t c i r c u i t ( d i s c o e =1) i n t e r na l log i c discon discoe discon# pin dis c o n # d- d+ ez - usb t o 3. 3 v r e gulator 1500 j1 u s b-b v c c 1 d- 2 d+ 3 g n d 4
ez-u s b s e r i e s 2 1 0 0 t r m v 1.8 c h a p t er 5. ez- u sb e n u m e r a t i o n a n d r e n u m e r a tion p a g e 5 - 13 the 8051 c an r enumerat e ? anytime. o nce use for this capability might be t o fine tun e an isochronous endpoint s bandwidth re q ue s t s by trying various des c r i ptor values and renumerating. t ables 5-9 through 5-19 show the de s c riptor data bu i lt into t h e e z - u sb core. the tables are pre s ented in the order that t he byt e s are stored. the device de s criptor specifies a maxpacketsize of 6 4 bytes for endpoint 0, contains cypress semiconductor v endo r , p roduct and r ele a se number i ds, a nd us e s n o string indices . rele a s e numb e r ids ( x x an d yy ) ar e foun d in individua l cypress s e m i conduc t or data shee t s. the ez-usb core returns th i s inf o rmat i o n res p o n se t o a ge t _descrip t or/ device ho s t request. 5.10 m u ltiple renumerations ? ?? ? 5 . 1 1 d e fault d es c riptor t a b l e 5 - 9 . us b d e fau l t d e vi c e de s c r ip t or o f f s e t f i eld d es c r i p t ion v a l u e 0 b l e ngth l e n g t h of this des c r ipt o r = 1 8 bytes 12 h 1 b des c r i p to r t ype de s crip t or t y pe = de v ice 01 h 2 b cdu s b (l) u s b s p e c ifi c at i on v er s ion 1.00 (l) 00 h 3 b cdu s b (h) u s b s p e c ifi c at i on v er s ion 1.00 (h) 01 h 4 b device c l a s s de v i c e cla s s ( f f is v e nd o r-s p e c ific) f f h 5 b device s ubclass de v i c e s ub-cl a ss ( f f i s v e nd o r-s p e c ific) f f h 6 b device p ro t ocol de v i c e p ro t ocol ( f f is v e n do r -sp e c i fic) f f h 7 b ma x pac k e t s ize0 m a ximum pac k e t si z e f o r e p 0 = 64 byte 40 h 8 id v e n dor (l) v en d o r id (l ) cy p r e ss s e mi c ondu c tor = 05 47h 47 h 9 id v e n d o r (h) v en d o r id (h) 05 h 10 id p ro d u ct (l) p r od u ct id (l) e z -usb = 2131h 31 h 1 1 id p ro d u ct (h) p r od u ct id (h) 21 h 12 b cdde v i c e ( l) de v i c e r e l e a se numb e r ( b c d,l) (see ind i v i dual data sheet) 21 h 13 b cdde v i c e ( h) de v i c e r e l e a se numb e r ( b c d,h) ( see indiv i dual data sheet) y y h 14 i m a n uf a cturer m a n u f a c t ur e r i n d ex str i ng = none 00 h 15 i p ro d uct p r od u ct i n dex str i ng = none 00 h 16 i s erialnu m ber s e ria l nu m be r i n d e x s t ring = none 00 h 17 b numc o n f igur a tions nu m ber o f c o nfig u r a t io n s in t h i s i n t e rface = 1 01h
p a g e 5 - 1 4 c h a p t e r 5 . e z-u s b e n u m e r a t i o n a n d r e n u m e r a tion e z -usb s e r i e s 2 1 0 0 t r m v 1.8 the configurat i on descri p t o r includes a total l e ngth fie l d (offset 2-3) that e n c o mpasses all inte r fa c e and endpoint d e scriptors that follow the con f iguration desc r iptor. t h is configu- r a t io n describ e s a singl e interfa c e (offse t 4). t h e host s elects t his con f iguration by issuing a set_conf i guration reque s ts specifying confi g u r ation #1 ( o f fset 5). interfac e 0, alt e r n ate setting 0 des c ribes endpo i nt 0 only. thi s i s a z e r o band w idth s etting. the inter f a c e has no string index. t a b l e 5- 1 0 . us b d e fa u l t c o nf i g u r a t ion d e s c r i pt o r o f f s e t f i eld d es c r i p t ion v a l u e 0 b l e n gth l e n g t h of this des c r ipt o r = 9 bytes 09 h 1 b d es c r i p to r t ype de s crip t or t y pe = c o n f i gur a t ion 02 h 2 w t o t a l l e n gt h (l) t o t al l e n g th (l ) i n clud i n g i n t e r f a c e an d end p oin t d escriptors d a h 3 w t o t a l l e n gth (h) t o t a l l e n g th (h) 0 0 h 4 b n um i n t e r f a c es nu m ber o f i nt e rfa c es i n this c onfi g u r ation 01 h 5 b c o n fi g u r at i onvalue co n figu r a t i o n value u s e d b y s e t _ conf i gu r at i on request to sele c t th i s c o nfig u ration 01 h 6 ico n f igur a tion i n dex o f s tri n g d e s c r i b i ng t h i s con f i guration = none 00 h 7 b m a t t rib u tes a t t r ib u t e s - b us - power e d , n o w a keup 80 h 8 m ax p ower m aximum power - 10 0 m a 32 h t a b l e 5 - 1 1. u sb d e f a u lt i n t e r f a c e 0, a l t e r n a te s e t t i ng 0 d e s c riptor o f f s e t f i eld d es c r i p t ion v a l u e 0 b l e n gth l e n g t h o f t he i nterfa c e de s criptor 09 h 1 b d es c r i p to r t ype de s crip t or t y pe = i n t e rface 04 h 2 b i n t er f a cenu m ber z ero-b a s e d i n d ex o f t h is i nterface = 0 00 h 3 b a l t e r n a t e s e t ting al t ern a te s e t ti n g valu e = 0 00 h 4 b n um e ndp o ints nu m ber o f e n d p o i nts i n th i s i nt e rface ( n ot c o unt i ng epo) = 0 00 h 5 b i n t er f a ceclass i n t er f ac e class = v endor s p ecific f f h 6 b i n t er f a ces u bclass i n t er f ac e s u b-class = v endor s p ecific f f h 7 b i n t er f a cep r o t o c ol i n t er f ace p r o t o c ol = v e nd o r sp e cific f f h 8 i i n t e r f a c e i n de x to s tri n g d e s c r ip t o r f or t h is in t erface = n o ne 00h
ez-u s b s e r i e s 2 1 0 0 t r m v 1.8 c h a p t er 5. ez- u sb e n u m e r a t i o n a n d r e n u m e r a tion p a g e 5 - 15 interface 0, al t e r n a t e set t ing 1 h as thirteen e ndpoi n ts, whose indi v idual des c r iptors follow the interface descri p tor. t h e a lterna t e s ettings have n o string indices. interface 0, alter n ate setting 1 has on e interrupt endpoint, in 1 , which has a maximum packet size of 16 and a polling interval of 10 ms. t ab l e 5 - 1 2 . u s b d e f au l t i n t e r f a c e 0, a l t e r n a t e s e t t i n g 1 d e s c r i p t o r o f f s e t f i eld d es c r i p t ion v a l u e 0 b l e ngth l e n g t h o f t he i nterfa c e de s c riptor 09 h 1 b des c r i p to r t ype de s crip t or t y pe = i n t erface 04 h 2 b i n t er f a cenu m ber z ero-b a s e d i n d ex o f t h is i nterface = 0 00 h 3 b al t e r n a t e s e t ting al t ern a te s e t ti n g valu e = 1 01 h 4 b num e ndp o ints nu m ber o f e n d po i nts i n th i s i nt e rface ( n ot c o unt i ng epo) = 13 0dh 5 b i n t er f a ceclass i n t er f ac e class = v endor s p ecific f f h 6 b i n t er f a ces u bclass i n t er f ac e s u b-class = v endor s p ecific f f h 7 b i n t er f a cep r o t o c ol i n t er f ace p r o t o c ol = v e ndor s p e cific f f h 8 i i n t e r f a c e i n de x to s tring d e sc r ip t o r f or t h is in t erface = n o ne 00h t a b l e 5 - 13 . u s b d e f a u l t i n t e r f a c e 0 , a l t e r n a t e s e t t i ng 1, i n t e r r u p t e n d p o i n t descr ipto r o f f s e t f i eld d es c r i p t ion v a l u e 0 b l e ngth l e n g t h of th i s e n d poi n t de s criptor 07 h 1 b des c r i p to r t ype de s crip t or t y pe = e n d p oint 05 h 2 b endp o in t address e n dpo i nt dir e ct i on (1 is i n ) and address = i n 1 81 h 3 b m a t t rib u tes x f r t ype = i n t 03 h 4 w m a x pa c ke t s ize (l) m axi m um pac k e t si z e = 16 bytes 10 h 5 w m a x pa c ke t s ize (h ) m axi m um pac k e t si z e - high 00h 6 b i n t erval p o l li n g i nte r v al i n m i l lis e conds = 10 ms 0ah
p a g e 5 - 1 6 c h a p t e r 5 . e z-u s b e n u m e r a t i o n a n d r e n u m e r a tion e z -usb s e r i e s 2 1 0 0 t r m v 1.8 t a b l e 5 - 1 4 . u s b d e f a u l t i n t e r f a c e 0 , a l t e r n a t e se t t i n g 1 , b u l k e n d p o i n t descriptor o f f s e t f i eld d es c r i p t ion v a l u e 0 b l e n gth l e n g t h of th i s e n d poi n t de s criptor 07 h 1 b d es c r i p to r t ype de s crip t or t y pe = e n d p oint 05 h 2 b e ndp o in t address en d poi n t dire c ti o n (1 is in) and a ddress = i n 2 82 h 3 b m a t t rib u tes x f r t ype = b u l k 02 h 4 w m a x pa c ke t s ize (l) m axi m um pac k e t si z e = 64 bytes 40 h 5 w m a x pa c ke t s ize (h ) m axi m um pac k e t si z e - high 00h 6 b i n t erval poll i ng int e r val i n mi l li s ec o n ds (1 fo r iso) 00 h 0 b l e n gth l e n g t h of th i s e n d poi n t de s criptor 07 h 1 b d es c r i p to r t ype de s crip t or t y pe = e n d p oint 05 h 2 b e ndp o in t address en d poi n t dire c ti o n (1 is in) and a ddress = out2 02 h 3 b m a t t rib u tes x f r t ype = b u l k 02 h 4 w m a x pa c ke t s ize (l) m axi m um pac k e t si z e = 64 bytes 40 h 5 w m a x pa c ke t s ize (h ) m axi m um pac k e t si z e - high 00h 6 b i n t erval poll i ng int e r val i n mi l li s ec o n ds (1 fo r iso) 00 h 0 b l e n gth l e n g t h of th i s e n d poi n t de s criptor 07 h 1 b d es c r i p to r t ype de s crip t or t y pe = e n d p oint 05 h 2 b e ndp o in t address en d poi n t dire c ti o n (1 is in) and a ddress = i n 4 84 h 3 b m a t t rib u tes x f r t ype = b u l k 02 h 4 w m a x pa c ke t s ize (l) m axi m um pac k e t si z e = 64 bytes 40 h 5 w m a x pa c ke t s ize (h ) m axi m um pac k e t si z e - high 00h 6 b i n t erval poll i ng int e r val i n mi l li s ec o n ds (1 fo r iso) 00 h 0 b l e n gth l e n g t h of th i s e n d poi n t de s criptor 07 h 1 b d es c r i p to r t ype de s crip t or t y pe = e n d p oint 05 h 2 b e ndp o in t address en d poi n t dire c ti o n (1 is in) and a ddress = out4 04 h 3 b m a t t rib u tes x f r t ype = b u l k 02 h 4 w m a x pa c ke t s ize (l) m axi m um pac k e t si z e = 64 bytes 40 h 5 w m a x pa c ke t s ize (h ) m axi m um pac k e t si z e - high 00h 6 b i n t erval poll i ng int e r val i n mi l li s ec o n ds (1 fo r iso) 00 h 0 b l e n gth l e n g t h of th i s e n d poi n t de s criptor 07 h 1 b d es c r i p to r t ype de s crip t or t y pe = e n d p oint 05 h 2 b e ndp o in t address en d poi n t dire c ti o n (1 is in) and a ddress = i n 6 86 h 3 b m a t t rib u tes x f r t ype = b u l k 02 h 4 w m a x pa c ke t s ize (l) m axi m um pac k e t si z e = 64 bytes 40 h 5 w m a x pa c ke t s ize (h ) m axi m um pac k e t si z e - high 00h 6 b i n t erval poll i ng int e r val i n mi l li s ec o n ds (1 fo r iso) 00 h
ez-u s b s e r i e s 2 1 0 0 t r m v 1.8 c h a p t er 5. ez- u sb e n u m e r a t i o n a n d r e n u m e r a tion p a g e 5 - 17 interface 0, alter n ate setting 1 has six bulk endpoints with max packet sizes of 64 bytes. even numbered endpoin t s were chosen t o allow endpoint p airing. for more on endpoint pai r ing, s ee chapter 6, " e z - u s b bul k t ra n sf e r s." t a b l e 5 - 1 4 . u s b d e f a u l t i n t e r f a c e 0 , a l t e r n a t e se t t i n g 1 , b u l k e n d p o i n t descriptor o f f s e t f i eld d es c r i p t ion v a l u e 0 b l e ngth l e n g t h of th i s e n d poi n t de s criptor 07 h 1 b des c r i p to r t ype de s crip t or t y pe = e n d p oint 05 h 2 b endp o in t address e n dpo i nt dir e ct i on (1 is i n ) and address = out6 06 h 3 b m a t t rib u tes x f r t ype = b u l k 02 h 4 w m a x pa c ke t s ize (l) m axi m um pac k e t si z e = 64 bytes 40 h 5 w m a x pa c ke t s ize (h ) m axi m um pac k e t si z e - high 00h 6 b i n t erval p o l li n g i nte r v al i n m i l lis e co n d s (1 f or iso) 00 h
p a g e 5 - 1 8 c h a p t e r 5 . e z-u s b e n u m e r a t i o n a n d r e n u m e r a tion e z -usb s e r i e s 2 1 0 0 t r m v 1.8 t a b l e 5 - 1 5 . u s b d e f a u l t i n t e r f a c e 0 , a l t e r n a t e s e t t i n g 1 , i s o c h r o n o u s e n d p o i n t descriptor o f f s e t f i eld d es c r i p t ion v a l u e 0 b l e n gth l e n g t h of th i s e n d poi n t de s criptor 07 h 1 b d es c r i p to r t ype de s crip t or t y pe = e n d p oint 05 h 2 b e ndp o in t address en d poi n t dire c ti o n (1 is in) and a ddress = i n 8 88 h 3 b m a t t rib u tes x f r t ype = iso 01 h 4 w m a x pa c ke t s ize (l) m axi m um pac k e t si z e = 16 bytes 10 h 5 w m a x pa c ke t s ize (h ) m axi m um pac k e t si z e - high 00h 6 b i n t erval poll i ng int e r val i n mi l li s ec o n ds (1 fo r iso) 01 h 0 b l e n gth l e n g t h of th i s e n d poi n t de s criptor 07 h 1 b d es c r i p to r t ype de s crip t or t y pe = e n d p oint 05 h 2 b e ndp o in t address en d poi n t dire c ti o n (1 is in) and a ddress = out8 08 h 3 b m a t t rib u tes x f r t ype = iso 01 h 4 w m a x pa c ke t s ize (l) m axi m um pac k e t si z e = 16 bytes 10 h 5 w m a x pa c ke t s ize (h ) m axi m um pac k e t si z e - high 00h 6 b i n t erval poll i ng int e r val i n mi l li s ec o n ds (1 fo r iso) 01 h 0 b l e n gth l e n g t h of th i s e n d poi n t de s criptor 07 h 1 b d es c r i p to r t ype de s crip t or t y pe = e n d p oint 05 h 2 b e ndp o in t address en d poi n t dire c ti o n (1 is in) and a ddress = i n 9 89 h 3 b m a t t rib u tes x f r t ype = iso 01 h 4 w m a x pa c ke t s ize (l) m axi m um pac k e t si z e = 16 bytes 10 h 5 w m a x pa c ke t s ize (h ) m axi m um pac k e t si z e - high 00h 6 b i n t erval poll i ng int e r val i n mi l li s ec o n ds (1 fo r iso) 01 h 0 b l e n gth l e n g t h of th i s e n d poi n t de s criptor 07 h 1 b d es c r i p to r t ype de s crip t or t y pe = e n d p oint 05 h 2 b e ndp o in t address en d poi n t dire c ti o n (1 is in) and a ddress = out9 09 h 3 b m a t t rib u tes x f r t ype = iso 01 h 4 w m a x pa c ke t s ize (l) m axi m um pac k e t si z e = 16 bytes 10 h 5 w m a x pa c ke t s ize (h ) m axi m um pac k e t si z e - high 00h 6 b i n t erval poll i ng int e r val i n mi l li s ec o n ds (1 fo r iso) 01 h 0 b l e n gth l e n g t h of th i s e n d poi n t de s criptor 07 h 1 b d es c r i p to r t ype de s crip t or t y pe = e n d p oint 05 h 2 b e ndp o in t address en d poi n t dire c ti o n (1 is in) and a ddress = i n 1 0 8ah 3 b m a t t rib u tes x f r t ype = iso 01 h 4 w m a x pa c ke t s ize (l) m axi m um pac k e t si z e = 16 bytes 10 h 5 w m a x pa c ke t s ize (h ) m axi m um pac k e t si z e - high 00h 6 b i n t erval poll i ng int e r val i n mi l li s ec o n ds (1 fo r iso) 01 h 0 b l e n gth l e n g t h of th i s e n d poi n t de s criptor 07 h 1 b d es c r i p to r t ype de s crip t or t y pe = e n d p oint 05 h 2 b e ndp o in t address en d poi n t dire c ti o n (1 is in) and a ddress = out 1 0 0ah 3 b m a t t rib u tes x f r t ype = iso 01 h 4 w m a x pa c ke t s ize (l) m axi m um pac k e t si z e = 16 bytes 10 h 5 w m a x pa c ke t s ize (h ) m axi m um pac k e t si z e - high 00h 6 b i n t erval poll i ng int e r val i n mi l li s ec o n ds (1 fo r iso) 01 h
ez-u s b s e r i e s 2 1 0 0 t r m v 1.8 c h a p t er 5. ez- u sb e n u m e r a t i o n a n d r e n u m e r a tion p a g e 5 - 19 interface 0, alter n ate setti n g 1 has six isoc h r onous endpoints with maximum packet sizes of 16 byt e s. this is a low bandwidth s etting. interface 0, al t e r n a t e set t ing 2 h as thirteen e ndpoi n ts, whose indi v idual des c r iptors follow the interface descri p tor. alternate set t ing 2 differs fr o m a l ternate setting 1 in the maxi- mum pac k e t si z es o f i t s interrupt endpoint and two o f i t s isochrono u s endpoin t s ( ep8in and ep8o u t). altern a te s etting 2 for the i n terrupt 1-in i n creases t h e maximum packet si z e for the inter- rupt endpoint to 64. t ab l e 5 - 1 6 . u s b d e f au l t i n t e r f a c e 0, a l t e r n a t e s e t t i n g 2 d e s c r i p t o r o f f s e t f i eld d es c r i p t ion v a l u e 0 b l e ngth l e n g t h o f t he i nterfa c e de s c riptor 09 h 1 b des c r i p to r typ de s crip t or t y p e = i n t erface 04 h 2 b i n t er f a cenu m ber z ero-b a s e d i n d ex o f t h is i nterface = 0 00 h 3 b al t e r n a t e s e t ting al t ern a te s e t ti n g valu e = 2 02 h 4 b num e ndp o ints nu m ber o f e n d p o i nts i n th i s i nt e rface ( n ot c o unt i ng epo) = 13 0dh 5 b i n t er f a ceclass i n t er f ac e class = v endor s p ecific f f h 6 b i n t er f a ces u bclass i n t er f ac e s u b-class = v endor s p ecific f f h 7 b i n t er f a cep r o t o c ol i n t er f ace p r o t o c ol = v e ndor s p e cific f f h 8 i i n t e r f a c e i n de x to s tring d e sc r ip t o r f or t h is in t erface = n o ne 00h t a b l e 5 - 17 . u s b d e f a u l t i n t e r f a c e 0 , a l t e r n a t e s e t t i ng 1, i n t e r r u p t e n d p o i n t descr ipto r o f f s e t f i eld d es c r i p t ion v a l u e 0 b l e ngth l e n g t h of th i s e n d poi n t de s criptor 07 h 1 b des c r i p to r t ype de s crip t or t y pe = e n d p oint 05 h 2 b endp o in t address e n dpo i nt dir e ct i on (1 is i n ) and address = i n 1 81 h 3 b m a t t rib u tes x f r t ype = i n t 03 h 4 w m a x pa c ke t s ize (l) m axi m um pac k e t si z e = 64 bytes 40 h 5 w m a x pa c ke t s ize (h ) m axi m um pac k e t si z e - high 00h 6 b i n t erval p o l li n g i nte r v al i n m i l lis e conds = 10 ms 0ah
p a g e 5 - 2 0 c h a p t e r 5 . e z-u s b e n u m e r a t i o n a n d r e n u m e r a tion e z -usb s e r i e s 2 1 0 0 t r m v 1.8 the bulk e ndpoints fo r alternate setting 2 are identical to alternate setting 1. t a b l e 5 - 1 8 . u s b d e f a u l t i n t e r f a c e 0 , a l t e r n a t e se t t i n g 2 , b u l k e n d p o i n t descriptor o f f s e t f i eld d es c r i p t ion v a l u e 0 b l e n gth l e n g t h of th i s e n d poi n t de s criptor 07 h 1 b d es c r i pto r typ de s crip t or t y pe = e n d p oint 05 h 2 b e ndp o in t address en d poi n t dire c ti o n (1 is in) and a ddress = i n 2 82 h 3 b m a t t rib u tes x f r t ype = b u l k 02 h 4 w m a x pa c ke t s ize (l) m axi m um pac k e t si z e = 64 bytes 40 h 5 w m a x pa c ke t s ize (h ) m axi m um pac k e t si z e - high 00h 6 b i n t erval poll i ng int e r val i n mi l li s ec o n ds (1 fo r iso) 00 h 0 b l e n gth l e n g t h of th i s e n d poi n t de s criptor 07 h 1 b d es c r i p to r t ype de s crip t or t y pe = e n d p oint 05 h 2 b e ndp o in t address en d poi n t dire c ti o n (1 is in) and a ddress = out2 02 h 3 b m a t t rib u tes x f r t ype = b u l k 02 h 4 w m a x pa c ke t s ize (l) m axi m um pac k e t si z e = 64 bytes 40 h 5 w m a x pa c ke t s ize (h ) m axi m um pac k e t si z e - high 00h 6 b i n t erval poll i ng int e r val i n mi l li s ec o n ds (1 fo r iso) 00 h 0 b l e n gth l e n g t h of th i s e n d poi n t de s criptor 07 h 1 b d es c r i p to r t ype de s crip t or t y pe = e n d p oint 05 h 2 b e ndp o in t address en d poi n t dire c ti o n (1 is in) and a ddress = i n 4 84 h 3 b m a t t rib u tes x f r t ype = b u l k 02 h 4 w m a x pa c ke t s ize (l) m axi m um pac k e t si z e = 64 bytes 40 h 5 w m a x pa c ke t s ize (h ) m axi m um pac k e t si z e - high 00h 6 b i n t erval poll i ng int e r val i n mi l li s ec o n ds (1 fo r iso) 00 h 0 b l e n gth l e n g t h of th i s e n d poi n t de s criptor 07 h 1 b d es c r i p to r t ype de s crip t or t y pe = e n d p oint 05 h 2 b e ndp o in t address en d poi n t dire c ti o n (1 is in) and a ddress = out4 04 h 3 b m a t t rib u tes x f r t ype = iso 02 h 4 w m a x pa c ke t s ize (l) m axi m um pac k e t si z e = 64 bytes 40 h 5 w m a x pa c ke t s ize (h ) m axi m um pac k e t si z e - high 00h 6 b i n t erval poll i ng int e r val i n mi l li s ec o n ds (1 fo r iso) 00 h 0 b l e n gth l e n g t h of th i s e n d poi n t de s criptor 07 h 1 b d es c r i p to r t ype de s crip t or t y pe = e n d p oint 05 h 2 b e ndp o in t address en d poi n t dire c ti o n (1 is in) and a ddress = i n 6 86 h 3 b m a t t rib u tes x f r t ype = b u l k 02 h 4 w m a x pa c ke t s ize (l) m axi m um pac k e t si z e = 64 bytes 40 h 5 w m a x pa c ke t s ize (h ) m axi m um pac k e t si z e - high 00h 6 b i n t erval poll i ng int e r val i n mi l li s ec o n ds (1 fo r iso) 00 h 0 b l e n gth l e n g t h of th i s e n d poi n t de s criptor 07 h 1 b d es c r i p to r t ype de s crip t or t y pe = e n d p oint 05 h 2 b e ndp o in t address en d poi n t dire c ti o n (1 is in) and a ddress = out6 06 h 3 b m a t t rib u tes x f r t ype = b u l k 02 h 4 w m a x pa c ke t s ize (l) m axi m um pac k e t si z e = 64 bytes 40 h 5 w m a x pa c ke t s ize (h ) m axi m um pac k e t si z e - high 00h 6 b i n t erval poll i ng int e r val i n mi l li s ec o n ds (1 fo r iso) 00 h
ez-u s b s e r i e s 2 1 0 0 t r m v 1.8 c h a p t er 5. ez- u sb e n u m e r a t i o n a n d r e n u m e r a tion p a g e 5 - 21 the only d i ff e rences between altern a te settings 1 and 2 are the maximum pa c ket sizes for e p8in and e p8o u t. th i s is a high-bandwidth sett i ng using 256 bytes each. t a b l e 5 - 1 9 . u s b d e f a u l t i n t e r f a c e 0 , a l t e r n a t e s e t t i n g 2 , i s o c h r o n o u s e n d p o i n t descriptor o f f s e t f i eld d es c r i p t ion v a l u e 0 b l e ngth l e n g t h of th i s e n d poi n t de s criptor 07 h 1 b des c r i p to r t ype de s crip t or t y pe = e n d p oint 05 h 2 b endp o in t address e n dpo i nt dir e ct i on (1 is i n ) and address = i n 8 88 h 3 b m a t t rib u tes x f r t ype = iso 01 h 4 w m a x pa c ke t s ize (l) m axi m um pac k e t si z e = 2 5 6 bytes 10 h 5 w m a x pa c ke t s ize (h ) m axi m um pac k e t si z e - high 01h 6 b i n t erval p o l li n g i nte r v al i n m i l lis e co n d s (1 f or iso) 01 h 0 b l e ngth l e n g t h of th i s e n d poi n t de s criptor 07 h 1 b des c r i p to r t ype de s crip t or t y pe = e n d p oint 05 h 2 b endp o in t address e n dpo i nt dir e ct i on (1 is i n ) and address = out8 08 h 3 b m a t t rib u tes x f r t ype = iso 01 h 4 w m a x pa c ke t s ize (l) m axi m um pac k e t si z e = 2 5 6 bytes 00 h 5 w m a x pa c ke t s ize (h ) m axi m um pac k e t si z e - high 10h 6 b i n t erval p o l li n g i nte r v al i n m i l lis e co n d s (1 f or iso) 01 h 0 b l e ngth l e n g t h of th i s e n d poi n t de s criptor 07 h 1 b des c r i p to r t ype de s crip t or t y pe = e n d p oint 05 h 2 b endp o in t address e n dpo i nt dir e ct i on (1 is i n ) and address = i n 9 89 h 3 b m a t t rib u tes x f r t ype = iso 01 h 4 w m a x pa c ke t s ize (l) m axi m um pac k e t si z e = 16 bytes 10 h 5 w m a x pa c ke t s ize (h ) m axi m um pac k e t si z e - high 00h 6 b i n t erval p o l li n g i nte r v al i n m i l lis e co n d s (1 f or iso) 01 h 0 b l e ngth l e n g t h of th i s e n d poi n t de s criptor 07 h 1 b des c r i p to r t ype de s crip t or t y pe = e n d p oint 05 h 2 b endp o in t address e n dpo i nt dir e ct i on (1 is i n ) and address = out9 09 h 3 b m a t t rib u tes x f r t ype = iso 01 h 4 w m a x pa c ke t s ize (l) m axi m um pac k e t si z e = 16 bytes 10 h 5 w m a x pa c ke t s ize (h ) m axi m um pac k e t si z e - high 00h 6 b i n t erval p o l li n g i nte r v al i n m i l lis e co n d s (1 f or iso) 01 h 0 b l e ngth l e n g t h of th i s e n d poi n t de s criptor 07 h 1 b des c r i p to r t ype de s crip t or t y pe = e n d p oint 05 h 2 b endp o in t address e n dpo i nt dir e ct i on (1 is i n ) and address = i n 1 0 8ah 3 b m a t t rib u tes x f r t ype = iso 01 h 4 w m a x pa c ke t s ize (l) m axi m um pac k e t si z e = 16 bytes 10 h 5 w m a x pa c ke t s ize (h ) m axi m um pac k e t si z e - high 00h 6 b i n t erval p o l li n g i nte r v al i n m i l lis e co n d s (1 f or iso) 01 h 0 b l e ngth l e n g t h of th i s e n d poi n t de s criptor 07 h 1 b des c r i p to r t ype de s crip t or t y pe = e n d p oint 05 h 2 b endp o in t address e n dpo i nt dir e ct i on (1 is i n ) and address = out 1 0 0ah 3 b m a t t rib u tes x f r t ype = iso 01 h 4 w m a x pa c ke t s ize (l) m axi m um pac k e t si z e = 16 bytes 10 h 5 w m a x pa c ke t s ize (h ) m axi m um pac k e t si z e - high 00h 6 b i n t erval p o l li n g i nte r v al i n m i l lis e co n d s (1 f or iso) 01 h
page 5-22 chapter 5. ez-usb enumeration and renumeration ez-usb series 2100 trm v1.8
ez-usb series 2100 trm v1.8 chapter 6. ez-usb bulk transfers page 6-1 6 ez-usb bulk transfers figure 6-1. two bulk transfers, in and out ez-usb provides sixteen endpoints for bulk, control, and interrupt transfers, numbered 0-7 as shown in table 6-1. this chapter describes bulk and interrupt transfers. interrupt transfers are a special case of bulk transfers. ez-usb con- trol endpoint zero is described in chapter 7, "ez-usb endpoint zero." * the highlighted endpoints do not exist in the an2122 or an2126. see also table 1-2. 6.1 introduction table 6-1. ez-usb bulk, control, and interrupt endpoints endpoint direction type size 0 bidir control 64/64 1inbulk/int64 1 out bulk/int 64 2inbulk/int64 2 out bulk/int 64 3inbulk/int64 3 out bulk/int 64 4inbulk/int64 4 out bulk/int 64 5inbulk/int64 5 out bulk/int 64 6inbulk/int64 *6 out bulk/int 64 7 in bulk/int 64 7 out bulk/int 64 i n a d d r e n d p c r c 5 token packet payload data c r c 1 6 data packet a c k i n a d d r e n d p c r c 5 token packet d a t a 0 payload data c r c 1 6 data packet a c k h/s pkt h/s pkt d a t a 1
page 6-2 chapter 6. ez-usb bulk transfers ez-usb series 2100 trm v1.8 the usb specification allows maximum packet sizes of 8, 16, 32, or 64 bytes for bulk data, and 1 - 64 bytes for interrupt data. ez-usb provides the maximum 64 bytes of buffer space for each of its sixteen e ndpoi nts 0-7 in and 0-7 out. six of the bulk end- points, 2-in, 4-in, 6-in, 2-out, 4-out, and 6-out may be paired with the next consec- utively numbered endpoint to provide double-buffering, which allows one data packet to be serviced by the 8051 while another is in transit over usb. six endpoint pairing bits (usbpair register) control double-buffering. the 8051 sets fourteen endpoint valid bits (in07val, out07val registers) at initializa- tion time to tell the ez-usb core which endpoints are active. the default control endpoint zero is always valid. bulk data appears in ram. each bulk endpoint has a reserved 64-byte ram space, a 7- bit count register, and a 2-bit control and status (cs) register. the 8051 can read one bit of the cs register to determine endpoint busy , and write the other to force an endpoint stall condition. the 8051 should never read or write an endpoint buffer or byte count register while the endpoints busy bit is set. when an endpoint becomes ready for 8051 service, the ez-usb core sets an interrupt request bit. the ez-usb vectored interrupt system separates the interrupt requests by endpoint to automatically transfer control to the isr (interrupt service routine) for the endpoint requiring service. chapter 9, "ez-usb interrupts" fully describes this mecha- nism. figure 6-2 illustrates the registers and bits associated with bulk transfers.
ez-u s b s e r i e s 2 1 0 0 t r m v 1.8 c h a p t e r 6 . ez-u s b b u l k t r a n s f ers p a g e 6-3 f i g u r e 6 - 2. r e g i s t e r s a s s o c i a t e d w i t h b u l k e n d points 64 b y t e e ndpo i nt b u ff e r 5 i n 0 7 val u s bpa i r endpoint valid (1=valid) endpoint pairing (1=paired) byte count control & status s b i n 0 7 i r q interrupt r equest (w rite 1 to clear) i n 0 7 i e n interrupt enable (1=enabled) i n 2 b c 7 6 4 3 2 1 0 5 7 6 4 3 2 1 0 i 2 3 i 4 5 i 6 7 o23 o45 o67 5 7 6 4 3 2 1 0 i n iti a li z a t i o n i n 2 b u f d a ta t r a n s f e r i n 2cs i n t e r r up t c on t r o l b u s y an d s t a l l r eg i s t e r s asso c i a t e d w i t h a b u l k i n e ndpo i nt ( e p 2 i n s hown a s e x a m p l e ) 64 b y t e e ndpo i nt b u ff e r 5 o u t 0 7 val u s bpa i r byte count control & status s b o u t 07 i r q o u t 0 7 i e n o u t 4 b c 7 6 4 3 2 1 0 5 7 6 4 3 2 1 0 i 2 3 i 4 5 i 6 7 o23 o45 o67 5 7 6 4 3 2 1 0 o u t 4 b uf d a ta t r a n s f e r o u t 4 cs i n t e r r up t c on t r o l b u s y an d s t a l l r eg i s t e r s asso c i a t e d w i t h a b u l k o u t endpo i nt ( e p 4 o u t s hown a s e x a m p l e) i n iti a li z a t i o n endpoint valid (1=valid) endpoint pairing (1=paired) interrupt enable (1=enabled) interrupt r equest (w rite 1 to clear)
p a g e 6 - 4 c h a p t e r 6 . ez-u s b b u l k t r a n s f ers e z -usb s e r i e s 2 1 0 0 t r m v 1.8 f i g u r e 6- 3 . a n a tom y o f a b u l k i n t r a n s f er usb bul k in data travels from device to host . t h e host r e que s t s an in t r ans f e r by issuing an in token to the e z -usb co r e , wh i ch responds with data when i t is r eady. the 8051 indicate s r eady b y loadin g the endpoi n t s byt e count regis t e r . if t h e ez-us b core receives an i n token for a n endpoint that is not r e ad y , it responds t o the in token with a n a k hand- shak e . in the bulk i n transfer illustrated in f i gur e 6-3, the 8051 h a s pre v iously loaded an end- point buf f er with a data packet, an d then loade d the endpoin t s byte count registe r with the number of bytes in the packet to arm the next i n t r a n s fer . t his sets the endp o i nts busy bit. the h o st issues a n in toke n , to which the e z -usb core responds b y transmitting the da t a in the i n endpoin t buff e r . when th e ho s t i ssu e s a n a c k , indicating t h a t the data h a s been r e ceived e r r o r - fr e e , the ez-u s b core c l ears the e ndpoi n t s b usy bit and sets its interrup t re q u est bit. this n o ti f ies the 8051 that the endpo i nt bu f f er i s empty. if this is a multi-pac k et tra n sfer, the host t hen i ssues a nother in token to get the next packet. i f the second in toke n arrives before the 8051 has h a d time to fill th e e ndpo int buffer, th e e z usb co r e issues a na k handshake, i n d i catin g busy . the host conti n u es t o send 6.2 b u lk in t ransfers i n a d d r e n d p c r c 5 t o k e n p a c k e t d a t a 1 p a y l o a d d a t a c r c 1 6 d a t a p a c k e t a c k i n a d d r e n d p c r c 5 t o k e n p a c k e t h / s p k t epnin interrupt, innbsy=0 n a k (innbc loaded) .. . h d hd h 1 2 3 4 5 i n a d d r e n d p c r c 5 t o k e n p a c k e t n a k i n a d d r e n d p c r c 5 t o k e n p a c k e t d a t a 0 p a y l o a d d a t a c r c 1 6 d a t a p a c k e t a c k h / s p k t ... load innbc epnin interrupt, innbsy=0 h dh d h 4 5 6 8 7 ... h / s p k t n o t e : h= ho s t , d= de v i c e ( e z - us b ) ... h / s p k t
ez-u s b s e r i e s 2 1 0 0 t r m v 1.8 c h a p t e r 6 . ez-u s b b u l k t r a n s f ers p a g e 6-5 i n token s and un t il the data is r e ady. event u a ll y , t he 8051 fills the e ndpoint buffer with data, and then loads t h e endpoin t s byte c ount r e g i s t e r ( i n n b c ) with the number of bytes in the packe t . loading the byte coun t re-arms t he given endpoint. whe n the next i n token a r rive s the e z - usb core t ran s f e r s the next data packe t . interrupt transfers are handled just like bulk t r a nsfers. the only d i ff e rence between a bulk endpo i nt and an interrupt endpoint e x ists in the end- point des c ript or, w h e r e t h e endpoin t is iden t ified as typ e inte r rup t , and a polling in t erva l is spe c i fied. the pol l ing interv a l determines how often the us b hos t i ssues i n tokens t o the inte r rupt endpoint. suppose 220 byt e s are to b e tr a n s f erred to the h ost using endpoint 6-in. fur t h e r assume that m axpacketsize of 64 by t es f or endpoint 6-in has been reported to t h e host during enumeration. b eca u se the t o tal trans f e r s i z e exceed s th e maximum packet size, the 8051 divides the 220-byte tran s f er into four tran s f ers of 64, 64, 64, and 28 bytes. a f t e r loading the f irst 64 byt e s into in6 b u f ( at 0x7c00), the 8051 loads the by t e count r eg i s ter in6 b c with the value 64 . writing the byt e coun t r egister instruct s t h e ez-usb core to r espond to the next host i n token by t r ansmitting the 64 bytes in t h e buffer. until the byte count regi s t e r is l oaded t o arm the in tran s f e r , any i n tokens issued by the ho s t are answered by e z -usb wit h nak (not-acknowledge ) toke n s, tellin g the u s b hos t that the endpoint is not y e t ready with data. the host con t inues to i s sue in tokens to endpoint 6 - in un t il dat a i s ready f o r tr a n s ferwhereupon th e ez-usb core rep l a c es naks with valid data. when the 8051 i n itia t es an in transfer by loading the endpo i nt s byte c ount r e gi s ter, the e z - u s b core sets a busy b i t to instruc t th e 805 1 t o ho l d of f load i n g i n 6bu f un t i l t h e usb t r an s fe r is f inished. when the in transfer is complete and su c cessfully acknowledged, the e z - u s b core r e sets the endpoint 6 - in busy b it and generates an endpoi n t 6-i n i n terrupt r equest. i f the endpoint 6-in interrupt is enabled, p r ogram cont r ol automati c all y vectors to the data tran s f er routine for furt h er a c tion (autovect o ring i s enabled by setting a ven=1; r efer to chapter 9, " e z-u s b interrupt s "). 6.3 in t e rrup t transfers 6.4 e z -usb b ulk in example
page 6-6 chapter 6. ez-usb bulk transfers ez-usb series 2100 trm v1.8 the 8051 now loads the next 64 bytes into in6buf and then loads the epinbc register with 64 for the next two transfers. for the last portion of the transfer, the 8051 loads the final 28 bytes into in6buf, and loads in6bc with 28. this completes the transfer. the ez-usb core takes care of usb housekeeping chores such as handshake verification. when an endpoint 6-in interrupt occurs, the user is assured that the data loaded by the 8051 into the endpoint buffer was received error-free by the host. the ez-usb core auto- matically checks the handshake information from the host and re-transmits the data if the host indicates an error by not acking. usb bulk out data travels from host to device. the host requests an out transfer by issuing an out token to ez-usb, followed by a packet of data. the ez-usb core then responds with an ack, if it correctly received the data. if the e ndpoint buffer is not ready to accept data, the ez-usb core discards the hosts out data and returns a nak token, indicating not ready. in response, the host continues to send out tokens and data to the endpoint until the ez-usb core res ponds with an ack. initialization note when the ez-usb chip comes out of reset, or when the usb host issues a bus reset, the ez-usb core unarms in endpoint 1-7 by setting their busy bits to 0. any in trans- fer requests are nakd until the 8051 loads the appropriate inxbc register(s). the end- point valid bits are not affected by an 8051 reset or a usb re set. chapter 10, "ez-usb resets" describes the various reset conditions in detail. 6.5 bulk out transfers
ez-u s b s e r i e s 2 1 0 0 t r m v 1.8 c h a p t e r 6 . ez-u s b b u l k t r a n s f ers p a g e 6-7 f i g u r e 6 - 4. a n a t o m y o f a b u l k o u t t r ansfer e ach e z -usb bulk out endpoint has a byte count reg i s t er, which serves two purposes. the 8051 r eads the byt e coun t r e gis t e r t o deter m ine ho w man y bytes were r e ceived during the la s t out tra n s fe r from the host. the 8051 w r i t e s the byte coun t reg i st e r (with any value) to t e l l the e z-usb core that is h as finished re a d i n g bytes fr o m t he buffer, making the bu f fer available to a ccept the ne x t o ut t ra n sfer. the o u t e ndpo i n t s c o m e u p (after r e se t ) armed , so the byt e count register w ri t es ar e required onl y for ou t trans f e rs a f t e r the f irst one. in the bulk out transfer illustrated in f igure 6-4. anatomy of a bu l k out tr a nsfer, the 8051 has previously loaded t h e endpoin t s byte c ount r e g i s t e r with any va l ue t o arm r e ceip t of the nex t ou t tra n s f e r. loading th e byte count regis t e r ca u se s t h e ez-us b c ore to s et the o ut endpoi n ts bu s y bit to 1, indi c ating that the 8051 should not use the end- point s bu f fe r . the host i s sues a n o u t toke n , followe d b y a p acke t o f data , which the e z -usb core acknowledge s , clears the endpoin t s busy bit and gene r ates an i nterrupt r eques t . this not i fi e s the 8051 that the endpoi n t buffer c ontai n s valid u s b data. the 8051 reads the endpoint s byte count r egi s te r to find out how many bytes we r e sent in the packet, and t r an s fe r s that many bytes ou t of the e ndpoin t buf f er. o u t a d d r e n d p c r c 5 t o k e n p a ck e t d a t a 1 p a y l oad d a t a c r c 1 6 d a t a p a c k e t a c k o u t a d d r e n d p c r c 5 t o k e n p a ck e t h / s pkt epno ut interrupt, outnbsy=0 n a k .. . d d h h 1 2 3 4 6 o u t a d d r e n d p c r c 5 t o k e n p a ck e t d a t a 0 p a y l oad d a t a c r c 1 6 d a t a p a c k e t a c k h / s pkt load outnbc (any value), causes outnbsy=1 epno ut interrupt, outnbsy=0 d hh 7 9 8 h / s pkt h d a t a 0 p a y l oad d a t a c r c 1 6 d a t a p a c k e t 5 h o u t a d d r e n d p c r c 5 t o k e n p a ck e t n a k .. . d h 4 6 h / s pkt d a t a 0 p a y l oad d a t a c r c 1 6 d a t a p a c k e t 5 h (outnbc loaded, outnbsy=1) ... n o t e : h= ho s t , d= dev i ce ( e z - u s b)
page 6-8 chapter 6. ez-usb bulk transfers ez-usb series 2100 trm v1.8 in a multi-packet transfer, the host then issues another out token along with the next data packet . if the 8051 has not finished emptying the endpoint buffer, the ez-usb host issues a nak, indicating busy . the data at is shaded to indicate that the ez- usb core discards it, and does not over-write the data in the endpoints out buffer. the host continues to send out tokens ( , , and ) that are greeted by naks until the buffer is ready. eventually, the 8051 empties the e ndpoint buffer data, and then loads the endpoints byte count register with any value to re-arm the ez-usb core. once armed, when the next out token arrives the ez-usb core accepts the next data packet . the ez-usb core takes care of usb housekeeping chores such as crc checks and data toggle pids. when an endpoint 6-out interrupt occurs and the busy bit is cleared, the user is assured that the data in the endpoint buffer was received error-free from the host. the ez-usb core automatically checks for errors and requests the host to re-transmit data if it detects any errors using the built-in usb error checking mechanisms (crc checks and data toggles). the 8051 sets endpoint pairing bits to 1 to enable double-buffering of the bulk endpoint buffers. with double buffering enabled, the 8051 can operate on one data packet while another is being transferred over usb. the endpoint busy and interrupt request bits func- tion identically, so the 8051 code requires little code modification to support double-buff- ering. initializing out endpoints when the ez-usb chip comes out of reset, or when the usb host issues a bus reset, the ez-usb core arms out endpoints 1-7 by setting their busy bits to 1. therefore, they are initially ready to accept one out transfer from the host. subsequent out transfers are nakd until the appropriate outnbc register is loaded to re-arm the endpoint. 6.6 endpoint pairing table 6-2. endpoint pairing bits (in the usb pair register) bit 543210 name pr6out pr4out pr2out pr6in pr4in pr2in paired 6 out 4 out 2 out 6 in 4 in 2 in endpoints 7 out 5 out 3 out 7 in 5 in 3 in
ez-u s b s e r i e s 2 1 0 0 t r m v 1.8 c h a p t e r 6 . ez-u s b b u l k t r a n s f ers p a g e 6-9 when an endpoint i s p a i red, the 8051 u ses only the even-numbered endpoi n t of the p air. the 8051 should not use the paired odd endpoint. for exam p l e, suppo s e it is d e sired to use endpoint 2-in as a double - buffered endpoint. this pairs the in 2 b uf and i n 3buf bu f fers, although th e 8051 a c c e s se s t h e i n 2 b u f b u f f e r o n ly. the 8051 sets pr2in = 1 (in the us b p a ir r egiste r ) to enabl e pair i ng , s e t s i n 2va l = 1 ( i n the i n 07val r e g i s t e r ) t o mak e the endpoin t valid, and then u ses the in2bu f bu f fer for al l dat a transfers. th e 8051 should n o t wr i t e th e in 3 val bit, enab l e in3 interr u p ts, access t h e e p 3i n buffer, or load the in3bc byte count regis t e r. i nn b sy=1 indica t es t h a t both endpoint bu f fers are in us e , and the 8051 should not load new i n data into the endpoint b u ff e r . when in n b sy=0, e i t her one or both of t h e buffers is avai l able fo r loading by the 8051. the 8051 can keep an in t e rnal count that increments on e pnin interrupts and decrements on byte count loads t o de t ermine whether one or two bu f fers are f r e e. o r, the 8051 c a n simply c heck f o r innbsy=0 a f t e r loading a b u f fer (and loading its byte count register t o r e -arm the endpoint) t o d eter m ine if the o t h er buffer is f r e e . a bulk i n endpoint inter r upt request is generated whenever a packet i s successfully trans- m i tted o v e r u s b. the i n t err u p t request is i ndepende n t of the busy bit . if bo t h buffers are f illed a nd one i s sent , the b u sy b it t r ansitions fro m 1-0; i f one buffer is f illed and then sent , the busy b i t starts and remains at 0. in eith e r case an interrupt r equest is generated to tell the 8051 that a bu f fe r i s free. note b i ts 2 and 5 must be s et to 0 in the an2122 and an2126 d e vices. 6.7 paired in endpoin t stat u s important note if a n in endpoint is paired and it i s d esired to clear t h e busy bit for that endpoint, do the following: (a) w rit e a ny value to the even endpoint s byte count registe r t w i c e , and (b) cl e a r the busy bi t for both endpoin t s i n th e pair . this is the only cod e differ e nc e b etween paired and unpaired us e of a n in endpoint.
page 6-10 chapter 6. ez-usb bulk transfers ez-usb series 2100 trm v1.8 outnbsy=1 indicates that both endpoint buffers are empty, and no data is available to the 8051. when outnbsy=0, either one or both of the buffers holds usb out data. the 8051 can keep an internal count that increments on epnout interrupts and decre- ments on byte count loads to determine whether one or two buffers contain data. or, the 8051 can simply check for outnbsy=0 after unloading a buffer (and loading its byte count register to re-arm the endpoint) to determine if the other buffer contains data. table 6-3 shows the ram locations for the sixteen 64-byte buffers for endpoints 0-7 in and out. these buffers are positioned at the bottom of the ez-usb register space so that any buffers not used for endpoints can be reclaimed as general purpose data ram. the top of memory for the 8-kb ez-usb part is at 0x1b3f. however, if the endpoints are allocated in ascending order starting with the lowest numbered endpoints, the higher num- bered unused endpoints can effectively move the top of memory to utilize the unused end- point buffer ram as data memory. for example, an application that uses endpoint 1-in, 6.8 paired out endpoint status 6.9 using bulk buffer memory table 6-3. ez-usb endpoint 0-7 buffer addresses endpoint buffer address mirrored in0buf 7f00-7f3f 1f00-1f3f out0buf 7ec0-7eff 1ec0-1eff in1buf 7e80-7ebf 1e80-1ebf out1buf 7e40-7e7f 1e40-1e7f in2buf 7e00-7e3f 1e00-1e3f out2buf 7dc0-7dff 1dc0-1dff in3buf 7d80-7dbf 1d80-1dbf out3buf 7d40-7d7f 1d40-1d7f in4buf 7d00-7d3f 1d00-1d3f out4buf 7cc0-7c3f 1cc0-1cff in5buf 7c80-7cbf 1c80-1cbf out5buf 7c40-7c7f 1c40-1c7f in6buf 7c00-7c3f 1c00-1c3f out6buf 7bc0-7bff 1bc0-1bbf in7buf 7d80-7bbf 1b80-1bbf out7buf 7b40-7b7f 1b40-1b7f
ez-u s b s e r i e s 2 1 0 0 t r m v 1.8 c h a p t e r 6 . ez-u s b b u l k t r a n s f ers p a g e 6 - 11 2 - in/out (paired ) , 4-in and 4 - o u t can use 0x1b40- 0 x 1 cbf as data m e mory. chapter 3 giv e s full details of the e z - usb memory map. the e z -usb co r e automatica l ly main t ains the data toggle b its during bulk, control and inte r rupt tra n s fers. as explained in cha p t er 1, "introduci n g ez- u s b , " the t o g g le bits are used to det e ct certa i n tr a n s m ission errors so that erroneous d ata ca n b e re-sent. in certain c ircu m s tances, the ho s t res e ts its data t oggle t o data0: ? af t e r sending a c lear _ f e atu r e: endpoint s tal l request to an endpoint. ? af t e r setting a new int e r f ace. ? af t e r sele c ting a new alternate setting. in these c a s e s, the 8051 can directly clear the data t oggl e for each of the bulk/interrupt/ control endpoints, us i ng the to g c t l register ( figur e 6-5 ) . f i g u re 6 - 5 . b u l k e nd p o i nt t ogg l e c o ntrol note an2122 endpoint memo r y st a r t s at 0x1c00 and an2126 endpoint me m ory s t a rts at addre s s 0x7c00. note uploads or downloads to unused bulk memo r y can be done only at th e mir r o r ed (low) addre s ses shown i n table 6-3. 6.10 data t oggle co n trol t ogc t l data t oggle con t r ol 7fd7 b7 b6 b5 b4 b3 b2 b1 b0 q s r io 0 ep2 ep1 ep0 r r/w r/w r/w r/w r/w r/w r/w x x x x x x x x
page 6-12 chapter 6. ez-usb bulk transfers ez-usb series 2100 trm v1.8 the io bit selects the endpoint direction (1=in, 0=out), and the ep2-ep1-ep0 bits select the endpoint number. the q bit, which is read-only, indicates the state of the data toggle for the selected endpoint. writing r=1 sets the data t oggle to data0, and writing s=1 sets the data toggle to data1. note at the present writing, there appears to be no reason to set a data toggle to data1. the s bit is provided for generality.
ez-usb series 2100 trm v1.8 chapter 6. ez-usb bulk transfers page 6-13 to clear an endpoints data toggle, the 8051 performs the following sequence: ? select the endpoint by writing the value 000d0eee to the togctl register, where d is the direction and eee is the endpoint number. ? clear the toggle bit by writing the value 001d0eee to the togctl register. after step 1, the 8051 may read the state of the data toggle by reading the togctl regis- ter checking bit 7.
page 6-14 chapter 6. ez-usb bulk transfers ez-usb series 2100 trm v1.8 the following code illustrates the ez-usb registers used for a simple bulk transfer. in this example, 8051 register r1 keeps track of the number of endpoint 2-in transfers and register r2 keeps track of the number of endpoint 2-out transfers (mod-256). every endpoint 2-in transfer consists of 64 bytes of a decrementing count, with the first byte replaced by the number of in transfers and the sec ond byte replaced by the number of out transfers. figure 6-6. example code for a simple (polled) bulk transfer 6.11 polled bulk transfer example 1 start: mov sp,#stack-1 ; set stack 2 mov dptr,#in2buf ; fill ep2in buffer with 3 mov r7,#64 ; decrementing counter 4 fill: mov a,r7 5 movx @dptr,a 6 inc dptr 7 djnz r7,rill 8; 9 mov r1,#0 ; r1 is in token counter 10 mov r2,#0 ; r2 is out token counter 11 mov dptr,#in2bc ; point to ep2 byte count register 12 mov a,#40h ; 64-byte transfer 13 movx @dptr,a ; arm the in2 transfer 14 ; 15 loop: mov dptr,#in2cs ; poll the ep2-in status 16 movx a,@dptr 17 jnb acc.1,servicein2 ; not busy--keep looping 18 mov dptr,#out2cs 19 movx a,@dptr 20 jb acc.1,loop ; ep2out is busy--keep looping 21 ; 22 serviceout2: 23 inc r2 ; out packet counter 24 mov dptr,#out2bc ; load byte count register to re-arm 25 movx @dptr,a ; (any value) 26 sjmp loop 27 ; 28 servicein2: 29 inc r1 ; in packet counter 30 mov dptr,3in2buf ; update the first data byte 31 mov a,r1 ; in ep2in buffer 32 movx @dptr,a 33 inc dptr ; second byte in buffer 34 mov a,r2 ; get number of out packets 35 movx @dptr,a 36 mov dptr,#in2bc ; point to ep2in byte count register 37 mov a,#40h 38 movx @dptr,a ; load bc=64 to re-arm in2 39 sjmp loop 40 ; 41 end
ez-usb series 2100 trm v1.8 chapter 6. ez-usb bulk transfers page 6-15 the code at lines 2-7 fills the endpoint 2-in buffer with 64 bytes of a decrementing count. two 8-bit counts are initial ized to zero at lines 9 and 10. an endpoint 2-in transfer is armed at lines 11-13, which load the endpoint 2-in byte count register in2bc with 64. then the program enters a polling l oop at l ines 15-20, where it checks two flags for end- point 2 servicing. lines 15-17 check the endpoint 2-in busy bit in in2cs bit 1. lines 18- 20 check the endpoint 2-out busy bit in out2cs bit 1. when busy=1, the ez-usb core is currently using the endpoint buffers and the 8051 should not access them. when busy=0, new data is ready for service by the 8051. for both in and out endpoints, the busy bit is set when the ez-usb core is using the buffers, and cleared by loading the endpoints byte count register. the byte count value is meaningful for in transfers because it tells the ez-usb core how many bytes to transfer in response to the next in token. the 8051 can load any byte count out transfers, because only the act of loading the register is significantloading outnbc arms the out transfer and sets the endpoints busy bit. when an out packet arrives in out2buf, the service routine at lines 22-26 increments r2, loads the byte count (any value) into out2bc to re-arm the endpoint (lines 24-25), and jumps back to the polling routine. this program does not use out2buf data; it sim- ply counts the number of endpoint 2-out transfers. when endpoint 2-in is ready for the 8051 to load another packet into in2buf, the polling loop jumps to the endpoint 2-in service routine at lines 28-39. first, r1 is incremented (line 29). the data pointer is set to in2buf at line 30, and register r1 is loaded into the first byte of the buffer (lines 31-32). the data pointer is advanced to the second byte of in2buf at line 33, and register r2 is loaded into the buffer (lines 34-35). finally, the byte count 40h (64 decimal bytes) is loaded into the byte count register in2bc to arm the next in transfer at lines 36-38, and the routine returns the polling loop. the code in this example is complete, and runs on the ez-usb chip. you may be won- dering about the missing step , which reports the endpoint characteristics to the host during the enumeration process. the reason this code runs without any enumeration code is that the ez-usb chip comes on as a fully-functional usb device with certain endpoints already configured and reported to the host. endpoint 2 is included in this default config- uration. the full default configuration is described in chapter 5, "ez-usb enumeration and renumeration ? " 6.12 enumeration note
p a g e 6 - 1 6 c h a p t e r 6 . ez-u s b b u l k t r a n s f ers e z -usb s e r i e s 2 1 0 0 t r m v 1.8 all usb interrupts a ctivat e th e 805 1 int 2 inte r rupt. if enabled, int2 interrup t s cause the 8051 to push t h e cu r rent pr o g ram counter onto t h e s t ack, and then exec u t e a jump to l o ca- tion 0x43, where the p r o g r ammer has insert e d a jump i nstruction to the i n ter r upt se r vice routin e (isr). if th e aven (autovector enable) b it is set , the ez- u s b core inserts a spe- cial byte at l o cation 0x45, whi c h d i r ects the jump instruction t o a table of j u mp i n struc- tions w h ich transfer control the endpo i nt-specific isr. * re p l a c e d b y e z - us b c o r e i f av e n =1. the byte in s erted by the e z -usb co r e at address 0x45 depends on which bulk endpoint r equ i res serv i ce . table 6-5 shows all int2 vectors, with the bulk endpoint vectors un- shaded. the shaded interrupts apply to a l l the bulk endpoints. 6.13 b u lk endpoin t interrupts t ab l e 6- 4 . 8051 int2 i n t e r rup t v ec t o l o c a t ion op - co d e i nstruct i on 0 x 43 02 lj m p 0 x 44 a ddrh 0 x 45 ad d rl* t a b l e 6 - 5. b y te i n se r t e d b y ez - u sb c o re at l o c a t i on 0 x 4 5 i f a ven=1 i n ter r upt i nserted b yte at 0 x 4 s u d a v 0x00 s o f 0x04 s u t ok 0x08 s u s p e n d 0 x 0 c us b r es 0x10 ibn 0x14 e p 0 - in 0x18 e p 0 - o u t 0x1c e p 1 - in 0x20 e p1out 0x24 e p 2 in 0x28 e p2out 0 x 2 c e p 3 - in 0x30 e p 3 - o u t 0x34 e p 4 - in 0x38 e p 4 - o u t 0 x 3 c e p 5 - in 0x40 e p 5 - o u t 0x44 e p 6 - in 0x48 e p 6 - o u t 0 x 4 c e p 7 - in 0x50 e p 7 - o u t 0x54
ez-u s b s e r i e s 2 1 0 0 t r m v 1.8 c h a p t e r 6 . ez-u s b b u l k t r a n s f ers p a g e 6 - 17 the vector v al u es a r e four bytes apart. this all o ws the pr o g rammer to build a jump table to e a ch of the int e rrupt service rout i nes. note that the jump tab l e must begin on a page (256 byte) boundary b ecause t h e first ve c tor starts at 00 . if autovectoring is not used ( a ven=0), the ivec register m ay be d i r e ctly insp e cted to de t ermine t h e usb interrupt sourc e ( s e e sect i on 9.11, "autovector coding"). e ach bulk endpoi n t interrupt has an a ss o c i ated interrupt enable b i t (in in 0 7 ien and out07ie n ), a n d an i n t e rrupt requ e st bit (in in07irq and out07irq). the interrupt service routine. i rq b i ts a r e cle a r e d by w riting a 1. b ec a use all usb r e g i s ters are a c ces s ed using m ovx @ dptr instructi o n s, usb interrupt service routines m ust save and r e store both data pointer s , the dps regis t er, and t he accu m u lator before clearing interrupt r equest b i t s . this s imple ( b u t f u lly-functi o n al) exam p le i l l ust r ates the bulk transfer mechanism using inte r rupts. in the example program, bulk endpoint 6 is used to loop data b ack to the host. data s ent by the ho s t over endpoint 6-o u t is sent b a c k over endpoi n t 6-in. note any usb isr shoul d clear the 805 1 int2 int e rrup t reques t bi t before cl e a ring an y of the e z -usb endpoint irq bit s , to avoid losing interrupts. interrupts are discu s sed in more det a i l in chapter 9, " e z-usb interrupts." individual interrup t request b i t s a re cleared by writing 1 to them to simplify code. for ex a mp l e , to clea r the endpoin t 2 -i n i r q, s imply write 0000100 t o i n 0 7 irq. t h i s will not disturb the oth e r in t e r rupt reque s t bits . do no t r ead the con t ents of i n 07irq, log i - cal-or t h e content s w i th 01, a n d write it b a c k . this c l e ars all oth e r pendin g interrupts be c ause you a r e wri t ing 1s to th e m . 6.14 in t e rrupt bul k transfer example
page 6-18 chapter 6. ez-usb bulk transfers ez-usb series 2100 trm v1.8 1. set up the jump table. figure 6-7. interrupt jump table this table contains all of the usb interrupts, even though only the jumps for endpoint 6 are used for the example. it is convenient to include this table in any usb application that uses interrupts. be sure to locate this table on a page boundary ( xx00). cseg at 300h ; any page boundary usb_jump_table: ljmp sudav_isr ; setup data available db 0 ; make a 4-byte entry ljmp sof_isr ; sof db 0 ljmp sutok_isr ; setup data loading db 0 ljmp susp_isr ; global suspend db 0 ljmp ures_isr ; usb reset db 0 ljmp spare_isr db 0 ljmp ep0in_isr db 0 ljmp ep0out_isr db 0 ljmp ep1in_isr db 0 ljmp ep1out_isr db 0 ljmp ep2in_isr db 0 ljmp ep2out_isr db 0 ljmp ep3in_isr db 0 ljmp ep3out_isr db 0 ljmp ep4in_isr db 0 ljmp ep4out_isr db 0 ljmp ep5in_isr db 0 ljmp ep5out_isr db 0 ljmp ep6in_isr ; used by this example db 0 ljmp ep6out_isr ; used by this example db 0 ljmp ep7in_isr db 0 ljmp ep7out_isr db 0
ez-u s b s e r i e s 2 1 0 0 t r m v 1.8 c h a p t e r 6 . ez-u s b b u l k t r a n s f ers p a g e 6 - 19 2. w rite t h e int2 inte r rupt vec t or. f i g u r e 6 - 8. i n t 2 i n t e r r u pt v e ctor 3. w rite t h e int e rrupt se r v i ce routine. pu t it anyw h e re in memory and the j ump table in step 1 will automatically jump to it. f i g u r e 6 -9. i n t e r r upt s e r v i ce r out i n e (i s r) f o r e n dpoi n t 6- o u t in this example, the isr s imply sets the 8051 flag got_ep6_d a t a to indicate to the back- ground program that the endpoint r e quires service. note that both d a t a pointers and the dp s (data pointer selec t ) r e gis t er s m ust be saved and r e s t or e d in addit i on to the accumu- lato r . ; ----------------- ; interrupt vectors ; ----------------- org 43h ; int2 is the usb vector ljmp usb_jump_table ; autovector will replace byte 45 ; ----------------------------- ; usb interrupt service routine ; ----------------------------- ep6out_isr push dps ; s ave both dptrs, dps, and acc push dpl push dph push dpl1 push dph1 push acc mov a,exif ; clear usb irq (int2) clr acc.4 mov exif,a mov dptr,#out07irq mov a,#01000000b ; a 1 clears the irq bit movx @dptr,a ; clear out6 int request setb got_ep6_data ; set my flag pop acc ; restore vital registers pop dph1 pop dpl1 pop dph pop dpl pop dps reti
p a g e 6 - 2 0 c h a p t e r 6 . ez-u s b b u l k t r a n s f ers e z -usb s e r i e s 2 1 0 0 t r m v 1.8 4. w rite t h e endpoint 6 tr a n sfer program. f i g u r e 6 - 10 . b a c k g r o u n d p r o g r a m t r a n sfe r s e n d p o i n t 6 - o u t d a t a t o endpoin t 6-in t h e m a i n p r og r a m l oo p t e s t s t h e go t _ep6_da t a fl a g, wai t ing until it is set by the end- point 6 o u t in t e r rupt s erv i c e routine in figure 6-10. th i s indica t es that a new data packet has a r rived in out6 b uf. then t h e se r v ice routi n e is ente r ed, w here the flag is cleared in line 2. the number of by t es r eceived in ou t 6 bu f is retrie v ed from the out 6 bc registe r (endpoin t 6 b y t e coun t ) and saved in reg i s t e r s r6 and r7 i n lines 7-10. the dual d a t a pointers a r e initi a l i z e d t o the s o u rce (out6 b uf ) an d de s tinat i on (in6buf) bu f fers fo r the data t r ansfer in lines 15-18. th e se la b e l s represe n t the start of the 64-byte bu f fers fo r endpoint 6-o u t and endpoint 6 - in, respecti v ely. each b y t e is r e ad from the out 6 buf b u f f er a n d written to the in6 b uf buffer in lines 19 - 2 5 . the saved value of 1 loop: jnb got_ep6_data,loop 2 clr got_ep6_data ; clear my flag 3; 4 ; t he user sent bytes to out6 endpoint using the usb control panel. 5 ; find out how many bytes were sent. 6; 7 mov dptr,#out6bc ; point to out6 byte count register 8 movx a,@dptr ; get the value 9 mov r7,a ; stash the byte count 10 mov r6,a ; save here also 1 1 ; 1 2 ; t ransfer the bytes received on the out6 endpoint to the in6 endpoint 1 3 ; buffer. number of bytes in r6 and r7. 1 4 ; 15 mov dptr,#out6buf ; first data pointer points to ep2out buffer 16 inc dps ; select the second data pointer 17 mov dptr,#in6buf ; second data pointer points to ep2in buffer 18 inc dps ; back to first data pointer 1 9 transfer: movx movx get out byte 20 inc dptr ; bump the pointer 21 inc dps ; second data pointer 22 movx @dptr,a ; put into in buffer 23 inc dptr ; bump the pointer 24 inc dps ; first data pointer 25 djnz r7,transfer 2 6 ; 2 7 ; load the byte count into in6bc. this arms in in transfer 2 8 ; 29 mov dptr,#in6bc 30 mov a,r6 ; get other saved copy of byte count 31 movx @dptr,a ; this arms the in transfer 3 2 ; 3 3 ; l oad any byte count into out6bc. this arms the next out transfer. 3 4 ; 35 mov dptr,#out6bc 36 movx @dptr,a ; use whatever is in acc 37 sjmp loop ; start checking for another out6 packet
ez-usb series 2100 trm v1.8 chapter 6. ez-usb bulk transfers page 6-21 out6bc is used as a loop counter in r7 to transfer the exact number of bytes that were received over endpoint 6-out. when the transfer is complete, the program loads the endpoint 6-in byte c ount regis ter in6bc with the number of loaded bytes (from r6) to arm the next endpoint 6-in transfer in lines 29-31. finally, the 8051 loads any value into the endpoint 6 out byte count reg- ister out6bc to arm the next out transfer in lines 35-36. then the program loops back to check for more endpoint 6-out data. 5. initialize the endpoints and enable the interrupts. figure 6-11. initialization routine the initialization routine sets the stack pointer, and enables the ez-usb autovector by setting usbbav.0 to 1. then it enables the endpoint 6-out interrupt, all usb interrupts (int2), and the 8051 global interrupt (ea) and finally clears the flag indicating that end- point 6-out requires service. once this structure is put into place, it is quite easy to service any or all of the bulk end- points. to add service for endpoint 2-in, for example, simply write an endpoint 2-in interrupt service routine with starting address ep2in_isr (to match the address in the jump table in step 1), and add its valid and interrupt enable bits to the init routine. start: mov sp,#stack-1 ; set stack ; ; enable usb interrupts and autovector ; mov dptr,#usbbav ; enable autovector movx a,@dptr,a setb acc.0 ; aven bit is bit 0 movx @dptr,a ; mov dptr,#out07ien ; ep0-7 out int enables register ; mov a,#01000000b ; set bit 6 for ep6out interrupt enable movx @dptr,a ; enable ep6out interrupt ; ; enable int2 and 8051 global interrupts ; setb ex2 ; enable int2 (usb interrupt) setb ea ; enable 8051 interrupts clr got_ep6_data ; clear my flag
page 6-22 chapter 6. ez-usb bulk transfers ez-usb series 2100 trm v1.8 the code in this example is complete, and runs on the ez-usb chip. you may be won- dering about the missing step , which reports the endpoint characteristics to the host during the enumeration process. the reason this code runs without any enumeration code is that the ez-usb chip comes on as a fully-functional usb device with certain endpoints already configured and reported to the host. endpoint 6 is included in this default config- uration. the full default configuration is described in chapter 5, "ez-usb enumeration and renumeration ? " portions of the above code are not necessary for the default configuration (such as setting the endpoint valid bits) but the code is included to illustrate all of the ez-usb registers used for bulk transfers. 6.15 enumeration note
ez-usb series 2100 trm v1.8 chapter 6. ez-usb bulk transfers page 6-23 bulk endpoint data is available in 64-byte buffers in ez-usb ram. in some cases it is preferable to access bulk data as a fifo register rather than as a ram. the ez-usb core provides a special data pointer which automatically increments when data is transferred. using this autopointer, the 8051 can access any contiguous block of internal ez-usb ram as a fifo. figure 6-12. autopointer registers the 8051 first loads autoptrh and autoptrl with a ram address (for example the address of a bulk endpoint buffer). then, as the 8051 r eads or writes data to the data reg- ister autodata, the address is supplied by autoptrh/l, which automatically incre- ments after every read or write to the autodata register. the autoptrh/l registers may be written or read at anytime. these registers maintain the current pointer address, so the 8051 can read them to determine where the next byte will be read or written. 6.16 the autopointer autoptrh autopointer address high 7fe3 b7 b6 b5 b4 b3 b2 b1 b0 a15 a14 a13 a12 a11 a10 a9 a8 r/w r/w r/w r/w r/w r/w r/w r/w x x x x x x x x autoptrl autopointer address low 7fe4 b7 b6 b5 b4 b3 b2 b1 b0 a7 a6 a5 a4 a3 a2 a1 a0 r/w r/w r/w r/w r/w r/w r/w r/w x x x x x x x x autodata autopointer data 7fe5 b7 b6 b5 b4 b3 b2 b1 b0 d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w x x x x x x x x
p a g e 6 - 2 4 c h a p t e r 6 . ez-u s b b u l k t r a n s f ers e z -usb s e r i e s 2 1 0 0 t r m v 1.8 the 8051 code e x amp l e in figure 6- 1 3 u s e s the autopoin t e r to transfer a block o f eight data byt e s f rom the endpoint 4 o u t buffer to in t ern a l 8051 m e mory. f i g u r e 6 - 13. u s e o f t h e a u t o po i nter as the co m ment in the penu l t imate li n e indic a tes, the autopo i nter sav e s an inc dptr instruction that would be n ecessary if one of the 8051 data p o i n t e rs were u s ed to access the out4buf ram data. th i s improves the transfer time. as des c ribed in chapte r 8, "e z - u s b i s o chronous t r a n sf e r s , " t h e ez - u s b c o re p rovides a method fo r t r ansfer r ing data direc t ly between an internal fifo and external memory in two 8051 cycles ( 333 n s ) . the fast t r ans f e r m ode is a ctive for bulk data when: ? the 8051 s ets fblk=1 in the f astxfr regi s t e r , enab l ing f a st b u lk t r ansfe r s , ? the 8051 d p tr poi n ts to the aut o d ata regis t er, and ? the 8051 executes a movx a,@ d p tr or a movx @ d p t r,a instruction. th e 805 1 code e x ample i n figure 6-14 shows a tra n s fer loop for moving 6 4 bytes of ex t e r- nal fi f o data into the e ndpoint 4 - in bu f fe r . the f astxfr regi s t e r bits a re explained in chapter 8, " e z-u s b isochronous t r ansfers." init: mov dptr,#autoptrh mov a,#high(out4buf) ; high portion of out4buf buffer movx @dptr,a ; load outoptrh mov dptr,#autoptrl mov a,#low(out4buf) ; low portion of out4buf buffer address movx @dptr,a ; load autoptrl mov dptr,#autodata ; point to the fifo register mov r0,#80h ; store data in upper 128 bytes of 8051 ram mov r2,#8 ; loop counter ; loop: movx a,@dptr ; get a fifo byte mov @r0,a ; store it inc r0 ; bump destination pointer ; (note: no inc dptr required here) djnz r2,loop ; do it eight times note fas t est bulk tr a nsfer spe e d in and out o f e z-u s b bulk b u ffers is achieved when the autopointer is u s ed in conjunction with th e ez-usb fa s t t ransfer mode.
ez-usb series 2100 trm v1.8 chapter 6. ez-usb bulk transfers page 6-25 figure 6-14. 8051 code to transfer external data to a bulk in buffer this transfer loop takes 19 cycles per loop times 8 passes, or 22 ms (152 cycles). a usb bulk transfer of 64 bytes takes more that 42 ms (64*8*83 ns) of bus time to transfer the data bytes to or from the host. this calculation neglects usb overhead time. from this simple example, it is clear that by using the autopointer and the ez-usb fast transfer mode, the 8051 can transfer data in and out of ez-usb endpoint buffers signifi- cantly faster than the usb can transfer it to and from the host. this means that the ez- usb chip should never be a speed bottleneck in a usb system. it also gives the 8051 ample time for other processing duties between endpoint buffer loads. the autopointer can be used to quickly move data anywhere in ram, not just the bulk endpoint buffers. for example, it can be used to good effect in an application that calls for transferring a block of data into ram, processing the data, and then transferring the data to a bulk endpoint buffer. note the autopointer works only with internal program/data ram. it does not work with memory outside the chip, or with internal ram that is made available when iso- disab=1. see section 8.9.1, "disable iso" for a description of the isodisab bit. mov dptr,#fastxfr ; set up the fast bulk transfer mode mov a,#01000000b ; fblk=1, rpol=0, rm1-0 = 00 movx @dptr,a ; load the fastxfr register init: mov dptr,#autoptrh mov a,high(in4buf) ; high portion of in4buf movx @dptr,a ; load autoptrh mov dptr,#autoptrl mov a,low(in4buf) ; low portion of in4buf buffer address movx @dptr,a ; load autoptrh mov dptr,#autodata ; point to the fifo register mov r7,#8 ; r7 is loop counter, 8 bytes per loop ; loop: movx @dptr,a ; (2) write in fifo using byte from external bus movx @dptr,a ; (2) again movx @dptr,a ; (2) again movx @dptr,a ; (2) again movx @dptr,a ; (2) again movx @dptr,a ; (2) again movx @dptr,a ; (2) again movx @dptr,a ; (2) again djnz r7,loop ; (3) do eight more, r7 times
page 6-26 chapter 6. ez-usb bulk transfers ez-usb series 2100 trm v1.8
ez-usb series 2100 trm v1.8 chapter 7. ez-usb endpoint zero page 7-1 7 ez-usb endpoint zero endpoint zero has special significance in a usb system. it is a control endpoint, and is required by every usb device. only control endpoints accept special setup tokens that the host uses to signal transfers that deal with device control. the usb host sends a repertoire of standard device requests over endpoint zero. these standard requests are fully defined in chapter 9 of the usb specification. this chapter describes how the ez-usb chip handles endpoint zero requests. because the ez-usb chip can enumerate without firmware (see chapter 5, "ez-usb enumeration and renumeration ? "), the ez-usb core contains logic to perform enumer- ation on its own. this hardware assist of endpoint zero operations is make available to the 8051, simplifying the code required to service device requests. this chapter deals with 8051 control of endpoint zero (renum=1, chapter 5), and describes ez-usb resources such as the setup data pointer that simplify 8051 code that handles endpoint zero requests. endpoint zero is the only control endpoint in the ez-usb chip. although con- trol endpoints are bi-directional , the ez-usb chip provides two 64-byte buffers, in0buf and out0buf, which the 8051 handles exactly like bulk e ndpoint buf fers for the data stages of a control transfer. a second 8-byte buffer, setupdat, which is unique to endpoint zero, holds data that arrives in the setup stage of a control trans- fer. this relieves the 8051 programmer of having to keep track of the three control transfer phasessetup, data, and status. the ez-usb core also generates sepa- rate interrupt requests for the various transfer phases, further simplifying code. the in0buf and out0buf buffers have two special properties that result from being used by control endpoint zero: ? endpoints 0-in and 0-out are always valid, so the valid bits (lsb of in07val and out07val registers) are permanently set to 1. writing any value to these two bits has no effect, and reading these bits always returns a 1. ? endpoint 0 cannot be paired with endpoint 1, so there is no pairing bit in the usb- pair register for endpoint 0 or 1. 7.1 introduction
p a ge 7-2 c h ap t er 7. ez- u sb e n d p oint zero e z -usb se r i e s 2 1 00 t r m v1.8 f i g u r e 7 - 1 . a u sb c o n t r o l t ra n sf e r ( th i s o n e h as a d a ta stage) endpoint zero a ccepts a spec i a l setup packet, which contains an 8-byte data s t ructure that provides host information about t h e c o n t r ol t ransa c t i o n . c o ntrol transfers include a final s t a tus pha s e, constructed f rom s tandard p i d s (in/o u t, d a ta1, and ack/nak). so m e c o n t r o l t ran s actions incl u d e all re q u ired data in their 8-byt e setup data packet. other c ontrol tran s acti o n s require m ore out data tha n will fit in t o the eight bytes, or require in data from the device. t h ese tra n sacti o n s u se standard bulk - like trans- f e r s to move the data. note in figure 7-1 that t h e d a ta s tage looks e x actly like a bulk t r an s fe r . as with bulk endpoints, the endpoin t zero byte c ount r e g i s t e r s m u s t b e loaded to a c k the data tran s f er stage o f a control transf e r. 7.2 co n trol endpoint e p0 80 5 1 c l ea r s h s n a k b i t ( w r i t es 1 t o i t ) o r se t s t he s t a l l b i t . i n a d d r e n d p c r c 5 t o k e n p a c k e t d a t a 0 8 b y t e s s e t up d a t a c r c 1 6 d a ta p a c k e t a c k h / s p k t s e t u p a d d r e n d p c r c 5 t o k e n p a c k e t d a t a 1 p a y l o a d d a t a c r c 1 6 d a ta p a c k e t d a t a 1 d a ta p kt a c k i n a d d r e n d p c r c 5 t o k e n p a c k e t d a t a 0 p a y l o a d d a t a c r c 1 6 d a ta p a c k e t a c k h / s p k t s y n c n a k h / s p k t o u t a d d r e n d p c r c 5 t o k e n p a c k e t c r c 1 6 s et u p s t a ge s u t o k i n t e rr up t c o r e s e t s h s n a k = 1 s u d a v i n t e rr up t d a t a s t a g e e p 0 -in i n t e rr up t e p 0 -in i n t e rr up t s t a t us s t a g e d a t a 1 o u t a d d r e n d p c r c 5 t o k e n p a c k e t c r c 1 6 .... h / s p k t d a ta p kt a c k h / s p k t
e z - u s b s e r i e s 2 1 0 0 t rm v 1 . 8 c h a p t e r 7 . e z - u s b e n d p o i n t z e r o p a g e 7 - 3 the s t a t us stage c o n s i sts o f an empty data packet with the opposite dir e ction of the data stage, or an in if there was no data s t age. this empty data packet gives the dev i ce a chance to a c k or na k the ent i re c ont r o l t ra n sfer. th e 8051 w rites a 1 to a bit call hsna k (handsha k e n ak ) t o c l e a r it a n d ins t r uc t t h e ez-usb core to a c k t h e s t atus stage. the hsna k bit is used t o hold off comple t i n g t h e c o nt r ol transfer until the device has had t ime to respond to a request. f o r example, if the host iss u e s a set_ i n t e rface r equest, the 8051 per f orms various housekeeping chores such as adjust i n g internal modes and re - initializing endpoints. duri n g t h i s time the host issues h a n d s h a ke ( s tatus stage) packe t s to w h ich the e z -u s b cor e responds with n aks, indica t i ng busy. when the 805 1 completes the desire d op e r ation, i t sets hsnak=1 (b y writing a 1 to the b i t) to ter- minate the control trans f er. this handshake preve n ts the host from attempting to use a p a r tially c onfigured interface. t o per f orm an endpoint stall for t h e da t a o r s tatus sta g e of an e ndpo i n t z e r o t r a nsfer ( th e se t u p stage can never sta l l), th e 805 1 m u s t set both t h e s t a ll an d hsna k b i ts for endpoint z e ro. so m e c o n t r o l t ran s f e r s do not have a d a ta stage. theref o re the 8051 code that pro- c e ss e s th e setup data should check the length field in t he setup data (in the 8-byte bu f fer a t s e tupd a t) and ar m endpoint z e ro for the d a t a phase (by loading i n0 b c or out 0 bc) only i f the length is non-zero. t wo 8051 inte r rupts provide not i f i cation that a s etup packet h a s a rrived, as shown in figur e 7-2. f i g u r e 7 - 2 . t h e t w o i n t e r r upts a s s o c i a t ed w i t h e p0 cont r ol t r a nsfers the e z -usb co r e s e t s the su t o k i r bit (s e tup t oken int e r rupt r equest) when the e z- usb co r e detec t s the s etup token at the beginning of a control t r a n sfer . this inter- rupt is n o rmally used only for debug. the ez-usb co r e s e t s the su d a v ir bit (setup d a t a a v a i l able interrupt reque s t ) when the e ight bytes o f s e tup data have bee n r e ceived er r o r - fre e and tra n sferred to e ight ez- d a t a 0 8 bytes setup data c r c 1 6 data packet a c k h/s pkt s e t u p a d d r e n d p c r c 5 token packet setup stage sutok interrupt sudav interrupt 8 ram bytes setupdat
p a ge 7-4 c h ap t er 7. ez- u sb e n d p oint zero e z -usb se r i e s 2 1 00 t r m v1.8 usb regi s t e r s st a rting at s etu p d at. t h e ez-usb c o re ta k es c are of a n y r e-trie s if it f inds any errors in the setup data. the s e two interrupt re q u est bits a re set by the ez- usb co r e, and must be c leared b y firmware. an 8051 progra m responds to th e s u d av int e rrupt requ e st by either directly i nspecting the eight byt e s at s etup d at or by transfe r ring them to a loca l buffer fo r further p r ocess- ing. servicing the se t up data should be a high 8051 p rior i t y , since the usb s p ecifica- tion stipula t es that control transfers m u st always b e accepted a n d neve r nakd. it is the r e fore possible that a c o n t r o l tra n s f e r could arrive while the 8051 i s still servicing a previous one. in this ca s e the p revi o u s c o n t r o l tr a n s f er service should be aborted and the new one serviced. the s u t o k i n terrupt gives advance warning th a t a new con- t r o l t r an s fe r is about to o v er-write the ei g h t se t up d a t bytes. i f the 8051 s talls endpoint zero ( b y s e tting the ep 0 s t all and hsn a k bits to 1 ) , the ez- usb co r e automatically clea r s this stall bit when t he next set u p tok e n arrives. l ike al l ez-usb in t errupt re q u ests, t h e s utokir and s udav ir b i ts can b e d irectly tested and r e s et by the c p u (they are r e set by writing a 1). t h u s, if th e corresponding inte r rupt enable bi t s are zero, the inter r u p t r e quest c ondi t ions c a n still be directly polled. figur e 7-3 shows the ez-u s b registers that d e al with control trans a ctions over ep0. f i g u r e 7- 3. r eg i s t e r s a s s o c ia t e d w i t h e p 0 c ont r o l t r a n s f e r the s e r egi s te r s aug m ent tho s e a ssociated with normal bul k tr a n s f ers over endpo i nt zero, which a r e de s c r ibed in chapter 6, "e z -usb bul k transfers." 8 bytes of setup data usbirq interrupt request: t=setup token sutokir d=setup data sudavir usbien global enable: t=setup token sutokie d=setup data sudavie t initialization setupdat data transfer interrupt control registers associated with endpoint zero for handling setup transactions d t d 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sudptrh sudptrl
e z - u s b s e r i e s 2 1 0 0 t rm v 1 . 8 c h a p t e r 7 . e z - u s b e n d p o i n t z e r o p a g e 7 - 5 t wo b i ts in t he us b i en ( u s b interrupt enable ) reg i st e r enable the s e tup token ( su t ok i e) and s etup d a t a interrup t s. the actual interr u p t reques t b i t s are in the usbirq ( u sb inte r r upt r e quests) r egiste r . they a r e calle d s t o k ir ( s e t u p token interrupt request) and s u d a v ir ( se t up data interrupt request). the e z -usb co r e t r ansfers the eight se t up bytes into eight bytes of r am at se t up- d a t . a 16-bit point e r, s u dptrh/l gives h ardware a ssista n ce for hand l ing c ontrol i n tran s f er s , in par t ic u l a r , the usb get_d e scriptor requests d e s cribed later in this chap t er. th e univ e rsal serial bus specifi c a t i on ver s ion 1.1, chapter 9, "u s b device framework" defin e s a s et of standa r d d e vice requ e st s . when the 8051 i s in control ( r e num=1), the e z - u s b core handles one of these r equests (set address) dir e c tl y , and relies on the 8051 to suppo r t the others. the 8051 a cts on device requests by decoding the ei g h t bytes con- tained in the se t up packet . table 7-1 shows the meaning of t h ese eight bytes. th e byt e column in th e p r evious table shows th e by t e o f f set from s e tup d a t. th e fi e l d column shows t h e di f f e rent bytes in th e request, where the bm p r efix mean s bit-map, b means byte, and w m eans word (16 bits). t a b l e 7-2 shows the di f f e rent values defined for brequ e st , and how the 8051 re s pond s t o e a c h r e q u e st . t h e r e m a i n d e r o f this chapter d e scribes ea c h of t he table 7-2 r e quests in detail. 7.3 usb reque s ts t a b l e 7 - 1. t h e e i ght b y t e s in a u s b set u p p acket byte f i e ld m e a n ing 0 b m re q u e s ttype r eq u e s t t ype, d i re c tio n , a n d recipient 1 b r equest t he a ct u al r e quest (se e t able 7-2) 2 w v aluel word - size valu e , varies ac c ord i ng to brequest 3 w v a l u e h 4 w i n d exl word - siz e f ield, v a rie s acc o r d i ng to brequest 5 w i n d exh 6 w l e n gthl n umb e r o f b y t e s to tr a n s f e r i f th e r e i s a data phase 7 w l e n g th note t abl e 7-2 applies when r en u m= 1 , which si g n ifies that the 8051, and not t h e ez-usb core, handles devi c e reques t s. t a ble 5-2 shows how the c ore handles eac h of these devi c e reque s ts when r enum=0, for example when the chip i s f i r st powered and the 8051 is no t running.
page 7-6 chapter 7. ez-usb endpoint zero ez-usb series 2100 trm v1.8 in the renumerated condition (renum=1), the ez-usb core passes all usb requests except set address onto the 8051 via the sudav interrupt. this, in conjunction with the usb disconnect/c onnect feature, all ows a completely new and different usb device (yours) to be characterized by the downloaded firmware. the ez-usb core implements one vendor-specific request, namely firmware load, 0xa0. (the brequest value of 0xa0 is valid only if byte 0 of the request, bmrequest- type, is also x10xxxxx, indicating a vendor-specific request.) the load request is valid at all times, so even after renumeration the load feature maybe used. if your appl ication implements vendor-specific usb requests, and you do not wish to use the firmware load feature, be sure to refrain from using the brequest value 0xa0 for your custom requests. the firmware load feature is fully described in chapter 5, "ez-usb enumeration and renumeration ? ." table 7-2. how the 8051 handles usb device requests (renum=1) brequest name action 8051 response 0x00 get status sudav interrupt supply remwu, selfpwr or stall bits 0x01 clear feature sudav interrupt clear remwu, selfpwr or stall bits 0x02 (reserved) none stall ep0 0x03 set feature sudav interrupt set remwu, selfpwr or stall bits 0x04 (reserved) none stall ep0 0x05 set address update fnaddr register none 0x06 get descriptor sudav interrupt supply table data over ep0-in 0x07 set descriptor sudav interrupt application dependent 0x08 get configuration sudav interrupt send current configuration number 0x09 set configuration sudav interrupt change current configuration 0x0a get interfac sudav interrupt supply alternate setting no. from ram 0x0b set interface sudav interrupt change alternate setting no. 0x0c sync frame sudav interrupt supply a frame number over ep0-in vendor requests 0xa0 (firmware load) up/download ram --- 0xa1 - 0xaf sudav interrupt reserved by cypress semiconductor all except 0xa0 sudav interrupt depends on application note to avoid future incompatibilities, vendor requests a0-af (hex) are reserved by cypress semiconductor.
ez-usb series 2100 trm v1.8 chapter 7. ez-usb endpoint zero page 7-7 7.3.1 get status the usb specification version 1.0 defines three usb status requests. a fourth request, to an interface, is indicated in the spec as reserved. the four status requests are: ? remote wakeup (device request) ? self-powered (device request) ? stall (endpoint request) ? interface request (reserved) the ez-usb core activates the sudav interrupt request to tell the 8051 to decode the setup packet and supply the appropriate status information. figure 7-4. data flow for a get_status request i n a d d r e n d p c r c 5 token packet d a t a 0 8 bytes setup data c r c 1 6 data packet s e t u p a d d r e n d p c r c 5 token packet d a t a 1 2 bytes c r c 1 6 data packet d a t a 1 data pkt a c k h/s pkt o u t a d d r e n d p c r c 5 token packet c r c 1 6 setup stage sutok interrupt sudav interrupt data stage status stage 8 ram bytes setupdat in0buf 64-byte buffer 2 in0bc a c k h/s pkt a c k h/s pkt
p a ge 7-8 c h ap t er 7. ez- u sb e n d p oint zero e z -usb se r i e s 2 1 00 t r m v1.8 as f igur e 7 -4 illustra t es, the 8051 re s pond s to the s udav interrupt by decoding the eight bytes the e z -usb core has co p ied into r am at se t upd a t . the 8051 answers a get_status r equ e st (brequest=0) by loading two bytes into the i n 0b u f buf f er and load- ing the byte coun t re g i ster in 0 bc with the value 2. t h e ez - usb co r e t r a n s mits these two bytes in response to an i n token. final l y, the 8051 c l e a r s t h e h s n a k b i t ( b y writing 1 t o i t ) to i n s truct th e ez-usb c o re to ack t h e s t a t us sta g e of the tran s fer. the fo l lowing tables show the e i ght s etup bytes f or g et_status r e qu e s ts. get_status- device queries the state o f two bit s , remot e w akeup and sel f -powered. the remote w akeup bit indi c ates whether or not the d e vi c e is cu r r ently en a bl e d to request r e mote wakeup. remote wakeup is explained in chapter 1 1 , "e z -usb power manag e - ment." the self - powered bit ind i cates whether or not the dev i ce i s self-powered (as opposed to usb bus-powered). the 8051 returns these two bits by loading two bytes i nto i n 0b u f , and then loading a byte count o f two into i n 0b c . t ab l e 7- 3 . g et s t at u s- d e v i c e ( rem o t e w a ke u p an d s e lf - p o w e re d b i t s ) byte f i eld v a l ue m e an i n g 8051 r e spons 0 bm r eq u e sttype 0 x 8 0 i n , d e v i ce 1 bre q uest 0 x0 0 get s t a t us l o ad t w o byt e s i n to i n 0buf 2 w v aluel 0x 0 0 3 w v a l u e h 0 x 0 0 b y t e 0 : bit 0 = s el f p o w ered bit 4 w i n d e x l 0 x 00 : bi t 1 = re m o t e w a keup 5 w i n d e x h 0 x 00 b y t e 1 : z ero 6 wl e ngthl 0 x02 t wo b y tes r e q uested 7 wl e ngthh 0 x 0 0 t a b l e 7 - 4 . g e t s t a tus - e n d p o i n t (s t a l l bits) byte f i eld v a l ue m e an i n g 8051 r e spons 0 bm r eq u e sttype 0 x 8 2 i n , endpoint l o ad t w o byt e s i n to i n 0buf 1 bre q uest 0 x 0 0 get s t a t us b y t e 0 : bit 0 = s t a l l bi t f o r ep(n) 2 w v aluel 0x 0 0 b y t e 1 : z ero 3 w v a l u e h 0 x 0 0 4 w i n d e x l ep en d p o i n t num b er e p (n): 5 w i n d e x h 0 x 00 0x00 - 0x 0 7: o ut0- o ut7 6 wl e ngthl 0 x 0 2 t wo b y tes r e q uested 0x80 - 0x 8 7: i n 0-in7 7 wl e ngthh 0 x 0 0
e z - u s b s e r i e s 2 1 0 0 t rm v 1 . 8 c h a p t e r 7 . e z - u s b e n d p o i n t z e r o p a g e 7 - 9 e ac h bul k endpoin t ( i n o r ou t ) ha s a s t a l l b i t i n its control an d status register (bit 0) . i f the cpu sets this bit, any requ e sts to the endpo i nt retur n a s t all handshake rather than ack or nak. the get status-endpoint request returns t h e s t a l l sta t e for the end- poin t ind i cated i n byt e 4 of the request . not e that bit 7 o f the endpoin t numb e r e p (byt e 4) spe c i fies direction. endpoint zero is a control endpoint, which by usb defin i tion i s bi-di r e ctional . therefore, it has only o n e s tall bit. abo u t s t a l l the u s b s t a l l handshake indi c ates that so m e thing unexpected has happened. for in s t anc e , if the host requ e sts an invalid alterna t e setting or attempts to send data to a non- exi s tent endpoint, the devic e responds with a s tall handshake over endpoi n t zero in s t e ad of ack or nak. stalls are d e fined for a l l endpoint t y p es except is o chronous, which do not employ handshake s . every e z -usb bulk endpoint has its own stall bit. t h e 8051 sets t he stall condition for an endpoint b y s etting the stall bit in t h e endpo i nts cs r egister. the host tel l s th e 8051 to se t or clear the s t a ll condition for an endpoint usin g th e set_feature/stall and cle a r_feature/stall requ e s t s. an example o f the 8051 setti n g a stall bit would be in a rou t ine that handles endpoint z e ro devi c e requests. if a n undefine d o r non - supported request is decoded, the 8051 should st a l l e p0. ( ep0 h a s a single stal l bit b e cause it is a b i-di r ectional endpoint.) on c e the 8051 s talls an endpoint, it should not remove t he stall until t h e host issues a c l e ar_ f e a tu r e/stall requ e st. an exce p tion to th i s rul e i s endpoint 0, which reports a stall condition onl y for the current transaction, and then autom a t i c ally clears the stall condi- tion . this prevents endpoint 0, the default c o n t r o l endpoint, fro m locking out device reque s ts.
p a g e 7 - 1 0 c h a p t e r 7. ez- u sb e n d p o int zero e z -usb s e r i e s 2 1 0 0 t r m v 1.8 get_status/inte r fa c e is easy: the 8051 ret u rns two zero b y tes through in0buf a n d c l ears th e h s nak bit. the requested bytes are shown as rese r v ed ( r e set to zero) i n the usb s pe c i fication. 7.3.2 set f e at u r e set feature is us e d to enable r e m ote wakeup or st a l l an endpoin t . no d ata stage is r equ i red. the only set_feature/device request pr e s ently d e fined in the usb specifica t ion is to set the remote wakeup b it. th i s is the same b i t re p o rted back to the host as a result of a get s t a tus-devic e re q u est ( table 7-3). the host us e s this bit to enable o r disa b le remote wakeup by the device. t a b l e 7 - 5 . g e t sta t u s -i n t e r f a c e byte f i eld v a l ue m e an i n g 8051 r e spons 0 bm r eq u e sttype 0 x 8 1 i n , endpoint l o ad t w o byt e s i n to i n 0buf 1 bre q uest 0 x 0 0 get s t a t us b y t e 0 : z ero 2 w v aluel 0x 0 0 b y t e 1 : z ero 3 w v a l u e h 0 x 0 0 4 w i n d e x l 0 x 00 5 w i n d e x h 0 x 00 6 wl e ngthl 0 x 0 0 t wo b y tes r e q uested 7 wl e ngthh 0 x 0 0 t a b l e 7 - 6 . s e t fe a t u r e -d e v i c e ( s e t r emo t e wa k eu p b i t ) byte f i eld v a l ue m e an i n g 8051 r e spons 0 bm r eq u e sttype 0 x 0 0 o u t , d e v i ce set the re m o t e w akeup bit 1 bre q uest 0 x 0 3 s e t f e a t ur e 2 w v aluel 0 x 0 1 f e a t u re sele c tor: re m o t e w akeup 3 w v a l u e h 0 x 0 0 4 w i n d e x l 0 x 00 5 w i n d e x h 0 x 00 6 wl e ngthl 0x 0 0 7 wl e ngthh 0x 0 0
ez-u s b s er i e s 2 1 0 0 t r m v 1.8 c h a p t er 7. ez-u s b e n d p o i nt z ero p a g e 7 - 11 the only set_feature/endpoint r e quest pr e s e ntly defined in the u s b spec i f ication is to stall an endpoint. the 8051 should respond to thi s request b y setting t h e stall bit in the contro l an d s tatus r egi s ter for the i n d i cated endpoin t ep ( b y t e 4 of th e request). th e 8051 can eit h er stall an endpoint on its own, o r in response to the de v ice request. endpoint stal l s are cleared by t h e host clear _ feature/stall r e quest. the 8051 should respond to the set_fe a t ure / s t all r e que s t by performing the following step s : 1 . set the stal l bit in th e i ndicated endpo i n t s cs r e gi s ter. 2 . re s et the data togg l e f o r the indi c a ted endpoint. 3 . fo r an in endpoin t , c lear the bus y bit in th e i ndicated endpo i n t s cs r e gi s ter. 4 . fo r an o u t endpoin t , load any value into the endpoi n ts byte count regis t er. 5 . clear t h e hsna k bit in t he e p 0 cs register (by writ i ng 1 to it) to terminate the set_fe a t ure / s t all control transfe r . s t eps 3 and 4 restore the s talled endpoint to its defa u lt condi t i on, ready t o send or accept data after the stall condition is removed b y t he h o st ( using a clear_fe a t u r e/sta l l r equest). the s e steps are als o required when the host se n d s a set_interf a ce request. t a b le 7 - 7 . s e t f e a t ur e - e n d p o i n t ( s tall) byte f i eld v a l ue m e an i n g 8051 r e spons 0 bm r eq u e sttype 0 x 0 2 o u t , e ndpoint set th e s ta l l b i t for the 1 bre q uest 0 x 0 3 s e t f e a t ur e i n d i c a ted e n dpoint: 2 w v aluel 0 x 0 0 f e a t u re sele c tor: s t all 3 w v alueh 0 x 00 4 w i n d e x l ep e p (n): 5 w i n dexh 0 x 00 0x0 0 -0x 0 7: o ut0- o ut7 6 wl e ngthl 0 x 00 0x8 0 -0x 8 7: i n 0-in7 7 wl e ngthh 0 x 00 data t oggles the e z -usb core auto m a ti c ally maintains the endpoint t oggle bits to ensure data integ- rity f o r usb t ra n s f e r s. the 8051 shoul d di r e ctly manipulate t h es e bits only for a very lim i ted set o f ci r cums t ances: ? set_feature/stall ? set_configuration ? set_inter f ace
p a g e 7 - 1 2 c h a p t er 7. ez- u sb e n d p o int zero e z -usb s e r i e s 2 1 0 0 t r m v 1.8 7.3.3 clear feature clear fe a tu r e is used to disable remote wakeup or to cle a r a stalled endpoint. i f the usb device support s remote wake u p ( a s reported in its descrip t or table when the device is enum e r a te d ), the clear_feature/remo t e wak e up request disab l es the wakeup capab i lity. the cle a r_feature/stall removes the stall cond i tion from an endpoint. the 8051 should r e spond by clearing the stall bit in the indicated e ndpoint s c s r e g ister. 7.3.4 ge t de s criptor du r ing enumeration, the h o st queries a u sb devi c e t o l earn its capabilities and require- ments using g et_descriptor reques t s. u sing tables o f d e sc r ipto r s , the device sends back t a b le 7- 8. c l e a r fe a t u r e-d e v i ce ( c le a r r emo t e wa k eu p b i t ) byte f i eld v a l ue m e an i n g 8051 r e spons 0 bm r eq u e sttype 0 x 0 0 o u t , d e v i ce clea r the r e m ote w akeup bit 1 bre q uest 0 x 0 1 clear f e a t ure 2 w v aluel 0 x 0 1 f e a t u re sele c tor: re m o t e w akeup 3 w v a l u e h 0 x 0 0 4 w i n d e x l 0 x 00 5 w i n d e x h 0 x 00 6 wl e ngthl 0x 0 0 7 wl e ngthh 0x 0 0 t ab l e 7-9 . c l e ar f e a t u r e -e n dp o int ( c l e a r s t a l l) byte f i eld v a l ue m e an i n g 8051 r e spons 0 bm r eq u e sttype 0 x 0 2 o u t , e ndpoint clea r th e s t a l l bi t f o r t h 1 bre q uest 0 x 0 1 clear f e a t ure i n d i c a ted e n d point: 2 w v aluel 0 x 0 0 f e a t u re sele c tor: s t all 3 w v a l u e h 0 x 0 0 4 w i n d e x l ep e p (n): 5 w i n d e x h 0 x 00 0x00 - 0x 0 7: o ut0- o ut7 6 wl e ngthl 0x 0 0 0x80 - 0x 8 7: i n 0-in7 7 wl e ngthh 0x 0 0
ez-usb series 2100 trm v1.8 chapter 7. ez-usb endpoint zero page 7-13 (over ep0-in) such information as what device driver to load, how many endpoints it has, its different configurations, alternate settings it may use, and informative text strings about the device. the ez-usb core provides a special setup data pointer to simplify 8051 service for get_descriptor requests. the 8051 loads this 16-bit pointer with the beginning address of the requested descriptor, clears the hsnak bit (by writing 1 to it), and the ez-usb core does the rest. figure 7-5. using the setup data pointer (sudptr) for get_descriptor requests figure 7-5 illustrates use of the setup data pointer. this pointer is implemented as two registers, sudptrh and sudptrl. most get_descriptor requests involve transferring more data than will fit into one packet. in the figure 7-5 example, the descriptor data con- sists of 91 bytes. i n a d d r e n d p c r c 5 token packet d a t a 0 8 bytes setup data c r c 1 6 data packet a c k h/s pkt s e t u p a d d r e n d p c r c 5 token packet d a t a 1 payload data c r c 1 6 data packet a c k i n a d d r e n d p c r c 5 token packet d a t a 0 payload data c r c 1 6 data packet a c k h/s pkt setup stage sudav interrupt data stage ep0in interrupt ep0in interrupt status stage d a t a 1 o u t a d d r e n d p c r c 5 token packet c r c 1 6 h/s pkt data pkt a c k h/s pkt sudptrh/l 64 bytes 27 bytes 8 ram bytes setupdat
p a g e 7 - 1 4 c h a p t er 7. ez- u sb e n d p o int zero e z -usb s e r i e s 2 1 0 0 t r m v 1.8 the contro l trans a ction starts in th e usua l wa y , wit h th e e z -usb co r e transfer r in g the eight bytes in the s e tup p a cket into ram at s e tup d a t a n d activating t he s udav inte r rup t reque s t . th e 805 1 d ecodes t h e get_d e scriptor re q u est , a nd respond s by clearing the hsnak bit (by wri t ing 1 to it), and then lo a di n g t h e sudptr registers with the address of the r equested de s c ript o r. loading t h e s u d p t r l re g ister c auses t h e ez-usb core to automati c a lly respond to two i n transfers with 64 bytes and 27 bytes of data using su d ptr as a base addr e ss, and then to respond to ( a c k) th e s tat u s stage. the usu a l endpoint z ero inte r rupts, su d av and ep 0 in, remain active during t his auto- mated tran s f e r . the 8051 normally disables t h ese interrupts because the transfer requires no 8051 in t e rvention. three types of d e s c riptors are defined: device, conf i g u rat i on, and s tring. 7.3.4.1 ge t de s cript o r -dev i c e as ill u s t r a ted i n figure 7-5, the 8051 loa d s the 2-byte s u d ptr with the starting a d d ress o f the d evice descript o r table. when s u dptrl is loaded, t h e e z- u sb co r e p erf o rms the following operations: 1 . rea d s the requested number of by t es for t h e tr a n s f er from bytes 6 and 7 of the s e tup pac k e t ( lenl an d l enh in t abl e 7 - 1 1). 2 . rea d s the requested stri n g s descript o r to d e t ermine t he ac t u al string length. 3 . sends the s m al l e r o f ( a ) the r equested number of bytes or (b) t h e actual number of bytes in the string, ov e r i n0buf u s ing the s e t up data pointer as a da t a table t a b l e 7 - 10 . g e t d es c r i p tor - d e v i ce byte f i eld v a l ue m e an i n g 8051 r e spons 0 bm r eq u e sttype 0 x 8 0 i n , d e v i ce set s ud p tr h-l to s t a r t of 1 bre q uest 0 x 0 6 ge t _des c rip t o r device de s crip t or t abl e i n r am 2 w v aluel 0x 0 0 3 w v a l u e h 0 x 0 1 des c rip t o r t y pe: devi c e 4 w i n d e x l 0 x 00 5 w i n d e x h 0 x 00 6 wl e ngthl l e nl 7 wl e ngthh lenh
ez-u s b s er i e s 2 1 0 0 t r m v 1.8 c h a p t er 7. ez-u s b e n d p o i nt z ero p a g e 7 - 15 index. this constitutes t h e second phase of t h e t hre e -phase control tr a nsfer. the core packetizes the data into multiple data transfers a s n e c essary. 4 . automatically checks f o r errors and r e -t r a n sm i t s data packets if n e cessary. 5 . responds to the third (handshake) pha s e of the c o n t r o l t r an s f e r to terminate the op e r ation. the setup da t a p ointer can be used for any get_d e script o r r e quest; for example, get_desc r iptor - string. it can also be used for v e ndor- s pe c ific requests (that you de f i ne), as long as bytes 6-7 contain the num b e r of bytes in the t r ansfe r (for s tep 1). i t is possible f or the 8051 to d o manual control tra n s fe r s, directly loading the i n0 b uf bu f fe r with the various p a ckets and k eeping tra c k of whic h set u p phase is in e f f ect. this would be a good u s b trainin g exercise, bu t no t n e cessar y due to the hardware support built into t h e ez-us b c or e for control transfers. fo r d a t a stag e t r ansfe r s o f f e we r than 64 byte s , moving th e dat a int o th e i n0 b u f buf f e r and then l o adin g the ep0 i n b c r eg i s ter with th e byte count woul d b e equi v alen t to loading the setup data pointe r. howeve r, this would was t e 8051 overh e ad b e cause th e setup data pointer requires no byte transfers into the in0bu f buf f er. 7.3.4.2 ge t de s cript o r -confi g urat i on t a b le 7 - 1 1. get d e s c rip t o r - c o n f igu r at i on byte f i eld v a l ue m e an i n g 8051 r e spons 0 bm r eq u e sttype 0 x 8 0 i n , d e v i ce s e t s u d p t r h - l t o s t a r t o f 1 bre q uest 0 x 0 6 ge t _des c rip t o r co n f i g ur a tion d e scr i p t o r table in 2 w v aluel cfg co n fig n u mber ram 3 w v a l u e h 0 x 0 2 des c rip t o r t y pe: co n figu r ation 4 w i n dexl 0 x 00 5 w i n dexh 0 x 00 6 wl e ngthl l e nl 7 wl e ngthh lenh
p a g e 7 - 1 6 c h a p t er 7. ez- u sb e n d p o int zero e z -usb s e r i e s 2 1 0 0 t r m v 1.8 7.3.4.3 ge t de s cript o r -string configu r atio n and strin g d e scr i ptors are handled similarl y to device d e scriptors. the 8051 f irmware reads byte 2 of t h e s etup da t a to d e t ermine whic h configura t i o n or s tring is being reque s ted, loads the co r responding table pointer into s u d p trh-l, and the ez- usb co r e does the r e s t. 7.3.5 set d es c riptor t ab l e 7 -12 . g e t des c r i p tor - s t r i ng byte f i eld v a l ue m e an i n g 8051 r e spons 0 bm r eq u e sttype 0 x 8 0 i n , d e v i ce set s ud p tr h-l to s t a r t of 1 bre q uest 0 x 0 6 ge t _des c rip t o r co n f i g ur a tion d e scr i p t o r table in 2 w v aluel cfg s t ring num b er ram 3 w v a l u e h 0 x 0 2 des c rip t o r t y pe: s t r i ng 4 w i n d e x l 0 x 00 ( l a n g u a g e id l ) 5 w i n d e x h 0 x 00 ( l a n g u a g e id h ) 6 wl e ngthl l e nl 7 wl e ngthh lenh t ab l e 7-13 . s e t des c ri p to r d e v i ce byte f i eld v a l ue m e an i n g 8051 r e spons 0 bm r eq u e sttype 0 x 0 0 o u t , d e v i ce read dev i ce d e s cr i ptor data over 1 bre q uest 0 x 0 7 s e t _de s crip t or out0 b uf 2 w v aluel 0x 0 0 3 w v a lueh 0x 0 1 des c rip t o r t y pe: devi c e 4 w i n d e x l 0 x 00 5 w i n d e x h 0 x 00 6 wl e ngthl l e nl 7 wl e ngthh lenh
ez-u s b s er i e s 2 1 0 0 t r m v 1.8 c h a p t er 7. ez-u s b e n d p o i nt z ero p a g e 7 - 17 the 8051 ha n d l e s s e t_ d escripto r requests by clearing the h s nak bit ( by writing 1 to i t ), the n r eading d escriptor data directly from t he o u t 0 buf bu f f e r. the e z-usb core kee p s trac k o f the numbe r of byes transferr e d f r o m the host int o out 0 b u f, and com p a res this numb e r wit h the l engt h field in by t es 6 and 7. when the proper number of bytes has bee n t ra n sf e rred, th e ez-usb c o r e automati c a lly responds t o t h e status phas e , wh i c h i s the third and final s tage o f the c o n t r o l t ra n sf e r. t a b le 7- 1 4 . s e t de s c r i pto r - c onfigura t ion byte f i eld v a l ue m e an i n g 8051 r e spons 0 bm r eq u e sttype 0 x 0 0 o u t , d e v i ce read c onfi g ur a tion d escriptor 1 bre q uest 0 x 0 7 s e t _de s crip t or d a ta o ver o u t 0buf 2 w v aluel 0 x 00 3 w v alueh 0 x 02 des c rip t o r t y pe: co n figu r ation 4 w i n dexl 0 x 00 5 w i n dexh 0 x 00 6 wl e ngthl l e nl 7 wl e ngthh lenh t a b le 7 - 15. set de s c r i ptor- s t r i ng byte f i eld v a l ue m e an i n g 8051 r e spons 0 bm r eq u e sttype 0 x 0 0 i n , d e v i ce read str i n g de s cri p to r dat a over 1 bre q uest 0 x 0 7 ge t _des c rip t o r out0 b uf 2 w v aluel 0 x 00 co n fig n u mber 3 w v alueh 0 x 03 des c rip t o r t y pe: s t r i ng 4 w i n dexl 0 x 00 (l a n g u a ge id l) 5 w i n dexh 0 x 00 (l a n g u a ge id h) 6 wl e ngthl l e nl 7 wl e ngthh lenh note the 8051 contro l s the flow of data in the data s t age of a control t ransfe r . a f ter the 8051 pro c e s ses e ach out packet, it l oads any value i nto th e out e ndpoints byte count regist e r to re - a r m the endpoint.
page 7-18 chapter 7. ez-usb endpoint zero ez-usb series 2100 trm v1.8 configurations, interfaces, and alternate settings configurations, interfaces, and alternate settings a usb device has one or more configu- ration . only one configuration is active at any time. a configuration has one or more inter- face , all of which are concurrently active. multiple interfaces allow different host- side device drivers to be associated with different portions of a usb device. each interface has one or more alternate setting . each alternate setting has a col- lection of one or more endpoints. this structure is a software model; the ez-usb core takes no action when these settings change. however, the 8051 must re-initialize endpoints when the host changes config- urations or interfaces alternate settings. as far as 8051 firmware is concerned, a configuration is simply a byte variable that indi- cates the current setting. the host issues a set_coniguration request to select a configuration, and a get_configuration request to determine the current configuration. device config 2 low power config 1 high power interface 1 audio interface 0 cdrom control alt setting 0 alt setting 1 alt setting 3 interface 2 video interface 3 data storage ep ep ep
ez-u s b s er i e s 2 1 0 0 t r m v 1.8 c h a p t er 7. ez-u s b e n d p o i nt z ero p a g e 7 - 19 7.3.6 set c onf i guration when the ho s t issues the set_conf i guration reque s t , the 8051 s aves the configuration numbe r (by t e 2 i n t able t abl e 7-16), performs any internal op e r a t i ons nec e ss a ry to sup- po r t the configu r ation, and finall y c l e a rs th e hsn a k bi t (by wr i tin g 1 t o i t ) t o terminate the set_con f iguration c o n t r o l t ran s f e r . 7.3. 7 ge t con f iguration the 8051 returns th e cu r re n t configuratio n num b e r . it l oads t he configur a t ion number into e p0in, loads a byte count of one into e p0inbc, and fi n ally clears t h e h s hak bit (by w r iting 1 t o it) to terminate the set_con f iguration control tr a nsfer. t ab l e 7 -16 . s e t con f igu r a t i o n byte f i eld v a l ue m e an i n g 8051 r e spons 0 bm r eq u e sttype 0 x 0 0 o u t , d e v i ce read a nd s t a sh b y t e 2 , change 1 bre q uest 0 x 0 9 s e t _co n f igur a tion co n figu r a t i ons i n f i rmw a r 2 w v aluel cfg co n fig n u mber 3 w v alueh 0 x 00 4 w i n dexl 0 x 00 5 w i n dexh 0 x 00 6 wl e ngthl 0 x 00 7 wl e ngthh 0 x 00 note after s ett i ng a configuration, t he host issue s set_interface comma n d s to set up the v a ri- ous inter f a ces contained in the c onfiguration. t a b l e 7 - 17 . g e t c on f i g u r ation byte f i eld v a l ue m e an i n g 8051 r e spons 0 bm r eq u e sttype 0 x 8 0 i n , d e v i ce send cfg ov e r i n 0 b uf a f ter 1 bre q uest 0 x 0 8 ge t _co n fi g u r ation re- c o n figuring 2 w v aluel 0 x 00 3 w v alueh 0 x 00 4 w i n dexl 0 x 00 5 w i n dexh 0 x 00 6 wl e ngthl 1 lenl 7 wl e ngthh 0 lenh
p a g e 7 - 2 0 c h a p t er 7. ez- u sb e n d p o int zero e z -usb s e r i e s 2 1 0 0 t r m v 1.8 7.3.8 set i nterface this confusingly named usb co m man d a ctually sets and reads bac k a lternate settings for a specified interface. usb devices can have multipl e concurr e nt i nterfa c e s . f o r example a de v ice may have an audi o system that s uppo r t s d i f f e r e n t s a m p l e r a te s , and a graphi c con t ro l pane l that supports di f ferent languages . each inte r f ace has a c o l le c tion of endpoints. exc e pt for endpoint 0, which e ach interface uses for device contro l , endpoints may n o t be shared between inter- f a ce s . interf a ces m ay r eport al t er n ate s e ttings in the i r descriptors. for example, the audio inter- f a ce may have setting 0, 1, and 2 for 8-khz, 2 2 -khz, and 44-kh z sa m ple rates, and the panel int e rf a c e ma y have settings 0 and 1 for english and span i s h. t he set/ge t _ interface r equests s e lect betw e en the various a l t e rnate s e t t ings in an interface. the 8051 should respond to a set_inte r f ace request by pe r form i ng the f o llowing st e ps: ? per f orm the int e rnal operation requested (such as adjusti n g a sampling rate). ? re s et the data togg l es for e v ery endpoint in t he int e r face. ? fo r an in endpoin t , c lear the bus y bit for every endpoint in the interface. ? fo r an o u t endpoin t , lo a d any value into the byte count regi s ter for every end- point in the inte r f a ce. ? clear t h e hsna k bit (by writing 1 to i t ) to terminate the set_feature/stall control transf e r. t a b le 7 - 1 8 . s et in t e r f ac e ( a c t u a l l y, s et a l t e r nat e s et t ing a s for i nte r f ac e if) byte f i eld v a l ue m e an i n g 8051 r e spons 0 bm r eq u e sttype 0 x 0 0 o u t , d e v i ce read a nd s t a s h b y te 2 (as ) for 1 bre q uest 0x0b s e t _ i n t e r f a c e i n t e r f a ce i f , c h a n g e s e t t i n g f o r 2 w v aluel as alt s e t t ing number i n t er f ace i f i n f i r mwa r e 3 w v a l u e h 0 x 0 0 4 w i n d e x l if for this in t erface 5 w i n d e x h 0 x 00 6 wl e ngthl 0x 0 0 7 wl e ngthh 0x 0 0
ez-u s b s er i e s 2 1 0 0 t r m v 1.8 c h a p t er 7. ez-u s b e n d p o i nt z ero p a g e 7 - 21 7.3.9 ge t interface the 8051 s imp l y retur n s the altern a te set t ing for the requested i n t e rface if, and clears the hsnak bit by w r iting 1 to it. 7.3.1 0 set a dd r ess when a usb device i s first plugged in, it responds to device addr e ss 0 un t il the host as s igns i t a unique addre s s u s ing the set_addr e s s request. the e z -usb co r e copi e s this device addr e ss into the fnaddr (funct i on a d d res s ) r e g iste r , and subsequently responds only to reque s ts to this addres s . this add r e ss is in e ffect unt i l the usb device is unplugged, the ho s t issu e s a usb re s e t, or the ho s t powers down. the fnaddr register c a n be read, but n o t written by the 8051. wh e neve r the ez-usb core r enumerate s ? , it automatic a l l y resets t h e fnaddr to zero allowing the device to come b a ck a s n e w . an 8051 program does not need to know the d e vice a ddres s , because t h e ez-usb core automatically responds only to the host - assigned fnad d r value . the ez - usb core makes it readable by the 8051 for debug/di a gnostic pur p o ses. t a b l e 7 - 19. g et i n t e r f ace ( a c t u a l l y , g e t a l t e r n a t e s e t t i ng a s f o r i n t e r face if) byte f i eld v a l ue m e an i n g 8051 r e spons 0 bm r eq u e sttype 0 x 8 1 i n , d e v i ce send a s f o r i nt e rfa c e if over 1 bre q uest 0x0a ge t _ i n t er f ace out0 b u f ( 1 b y t e ) 2 w v aluel 0 x 00 3 w v alueh 0 x 00 4 w i n d e x l if for this in t erface 5 w i n dexh 0 x 00 6 wl e ngthl 1 lenl 7 wl e ngthh 0 lenh
p a g e 7 - 2 2 c h a p t er 7. ez- u sb e n d p o int zero e z -usb s e r i e s 2 1 0 0 t r m v 1.8 7.3. 1 1 sy n c f rame the sync_ f rame reque s t is u sed to e stablis h a marker in time so t h e host and usb device can synchronize mu l ti-fr a me tra n sf e r s over isochronous endpoints. supp o s e an isochr onous tra n sm i ssion consists o f a repe a ting sequence of five 300 byte packe t s transmi t ted f r o m ho s t to devi c e ov e r e p 8-out. both host a nd device maintain sequence c oun t e r s t h a t c ount repeated l y from 1 to 5 to keep track of t h e pac k ets inside a t r an s mi s sion. to start up in sync , both h o s t an d devic e need to reset their count s to 1 at the same time (in the s a m e f r a m e). t o get in sync, the ho s t is s ues the s y n c_fr a me request wi t h ep=e p - o u t (byte 4 ). the 8051 f irmwar e r esponds by loading in0buf w i th a two-byte fram e c ount for some future t i m e; f o r example, the c urre n t frame plus 20. t h is mark s frame current+20 as the sync f rame , du r ing which both sides will initiali z e thei r seque n ce counters t o 1. the 8051 reads the c u rrent frame c ount in the usbf r a mel and usbfr a m e h r egisters. multiple isochronous endpoi n ts can be synchronized in this m anner. the 8051 keeps sep- arate internal sequence counts fo r each endpoint. t a b le 7 - 20. sync frame byte f i eld v a l ue m e an i n g 8051 r e spons 0 bm r eq u e sttype 0 x 8 2 i n , endpoint se n d a f rame n u mber over 1 bre q uest 0x0c s ync_ f ra m e i n0 b uf t o sy n chronize endpoint 2 w v aluel 0x 0 0 ep 3 w v a l u e h 0 x 0 0 4 w i n d e x l ep en d p o i n t number 5 w i n d e x h 0 x 00 e p (n): 6 wl e ngthl 2 lenl 0x08 - 0x 0 f : o u t8-o u t15 7 wl e ngthh 0 lenh 0x88 - 0x 8 f : in 8 - in15 abo u t usb f rames th e usb host issues a sof (st a rt of f r a m e ) packet onc e ever y m i llisecond . ever y sof packet contains an 1 1-bi t (mod-2048) f r ame numb e r. the 8051 s e r v i c e s a l l isochronous transfers at sof t ime, u s ing a single so f inte r rupt reque s t and vec t or . if t h e ez-usb core detects a m issing sof packet, it uses an int e r nal counter to genera t e the sof inter- rupt.
ez-usb series 2100 trm v1.8 chapter 7. ez-usb endpoint zero page 7-23 7.3.12 firmware load the usb endpoint zero protocol provides a mechanism for mixing vendor-specific requests with the previously described standard device requests. bits 6:5 of the bmre- quest field are set to 00 for a standard device request, and to 10 for a vendor request. the ez-usb core responds to two endpoint zero vendor requests, ram download and ram upload. these requests are active in all modes (renum=0 or 1). because bit 7 of the first byte of the setup packet specifies direction, only one brequest value (0xa0) is required for the upload and download requests. these ram load com- mands are available to any usb device that uses the ez-usb chip. a host loader program typically writes 0x01 to the cpucs register to put the 8051 into reset, loads all or part of the ez-usb internal ram with 8051 code, and finally reloads the cpucs register with 0 to take the 8051 out of reset. the cpucs register is the only usb register that can be written using the firmware download command. table 7-21. firmware download byte field value meaning 8051 response 0 bmrequesttype 0x40 vendor request, out none required 1 brequest 0xa0 firmware load 2 wvaluel addrl starting address 3wvalue addrh 4 windexl 0x00 5 windexh 0x00 6 wlengthl lenl number of bytes 7 wlengthh lenh table 7-22. firmware upload byte field value meaning 8051 response 0 bmrequesttype 0xc0 vendor request, in none required 1 brequest 0xa0 firmware load 2 wvaluel addrl starting address 3wvalue addrh 4 windexl 0x00 5 windexh 0x00 6 wlengthl lenl number of bytes 7 wlengthh lenh
page 7-24 chapter 7. ez-usb endpoint zero ez-usb series 2100 trm v1.8
ez-usb series 2100 trm v1.8 chapter 8. ez-usb isochronous transfers page 8-1 8 ez-usb isochronous transfers isochronous endpoints typically handle time-critical, streamed data that is delivered or consumed in byte-sequential order. examples might be audio data sent to a dac over usb, or teleconferencing video data sent from a camera to the host. due to the byte- sequential nature of this data, the ez-usb chip makes isochronous data available as a sin- gle byte that represents the head or tail of an endpoint fifo. the ez-usb chips that support isochronous transfers implement sixteen isochronous end- points, in8-in15 and out8-out15. 1, 024 bytes of fifo memory may be distributed over the 16 endpoint addresses. fifo sizes for the isochronous endpoints are programma- ble. figure 8-1. ez-usb isochronous endpoints 8-15 the 8051 reads or writes isochronous data using sixteen fifo data registers, one per end- point. these fifo registers are shown in figure 8-1 as inndata (endpoint n in data) and outndata (endpoint n out data). the ez-usb core provides a total of 2,048 bytes of fifo memory (1,024 bytes, double- buffered) for iso endpoints. this memory is in addition to the 8051 program/data mem- ory, and normally exists outside of the 8051 memory space. the 1,024 fifo bytes may be divided among the sixteen isochronous endpoints. the 8051 writes sixteen ez-usb reg- isters to allocate the fifo buffer space to the isochronous e ndpo ints. the 8051 also sets endpoint valid bits to enable isochronous endpoints. 8.1 introduction outndata register usb out data usb in data 8051 fifo usb fifo 8051 fifo usb fifo inndata register sof sof (n=8-15) (n=8-15)
p a g e 8 - 2 c h a p t e r 8 . e z - u s b i s o c h r o n o u s t r a n s f er s e z - u s b s e r i es 2 1 0 0 t rm v 1 . 8 i n transfers t ravel f rom device to host . figur e 8-2 s h o ws t h e e z- u sb registers a nd bits associated with iso c h ronous in transfers. f i g u r e 8 - 2. i s o c h r o n o us in e n d p o i n t re g i sters 8.2.1 initialization t o initialize an isochronous i n endpoint, t he 8051 p erform s the following: ? sets the e ndpoint valid bit for the endpo i nt. ? sets the e ndpoint s fi f o size by loading a s tar t ing address ( section 8.4, "setting i sochronous f ifo size s "). ? sets the i sos e nd0 b it in the u s bpa i r re g i ster f or the desired re s p o nse. ? enabl e s the sof interrupt. all isochr onou s endpoin t s are serviced in re s ponse to the sof interrupt. 8.2 i sochronous i n t r ansfers 1 3 inisoval 0 endpoint valid (1=valid) usbien sofie (1=enabled) in8data 15 14 12 11 8 10 9 5 7 6 4 3 1 2 0 initialization data transfer registers associated with an iso in endpoint (ep8in shown as example) usbirq sofir (1=clear request) 5 7 6 4 3 1 2 0 1 2 3 4 5 6 7 data to usb usbpair isosend0 (see text) 5 2 6 4 3 7 1 0 in8addr fifo start address (see text) a7 a4 a8 a6 a5 a9 0 0
ez-u s b s er i e s 2 1 0 0 t r m v 1.8 c h a p t e r 8 . ez-u s b i s o c h r o n o u s t r a n s f ers pa g e 8-3 the ez-usb co r e uses the i s o s end0 bit to determine w h at to do if: ? the 8051 d o es n ot load any b y tes to an i n n d a ta r e gister during the previous f rame, and ? an in token fo r that e ndpoint ar r ives from the h o st. i f i sos e nd0=0 (the d e f ault value), t h e e z-usb c o re does not respond to t h e in token. i f i sosend0=1, the ez-usb co r e s ends a z ero-length d ata packet i n response to t h e in token. which action to take depends on the overall system design. t he isosend0 bit applies to al l of the isochronous in endpoin t s , ep8in through e p 15in. 8.2.2 in da t a transfers when an sof interrupt occurs, the 8051 is p r esented with empty in f i fos t h at it fills wit h d a t a t o b e transfer r e d t o the host d u ring the nex t fr a me . th e 805 1 has 1 ms t o transf e r data into these f i fos before the next sof int e r rupt arrives. t o respond to the sof interrupt, the 8051 cle a r s the usb interrupt (8051 int2), and clears the s o fir (s t a r t of frame interrupt request) bi t writin g a 1 to it. then, the 8051 loads dat a into th e a ppropriat e i s ochronou s endpoint . th e e z -usb core keeps trac k o f the number of bytes t he 8051 loads t o eac h inn d a t a reg i st e r, and subseque n tly tra n s fe r s the cor r e c t number of bytes in r esponse to the usb i n token during the next frame. the e z-u s b fi f o swap occurs ever y s o f , even if during th e previous f rame the host did not issue an in token to read the isochronous fifo d ata, o r if the host encountered an error in the dat a . usb isochronous data h a s n o r e - t r y m e chanism like bulk data. o u t tra n s fe r s travel from h o s t t o devi c e . figur e 8-3 shows t h e ez-us b register s and bits associated with isochronous out transfers. 8.3 i sochronous o ut t ran s f e r s
page 8-4 chapter 8. ez-usb isochronous transfers ez-usb series 2100 trm v1.8 figure 8-3. isochronous out registers 8.3.1 initialization to initialize an isochronous out endpoint, the 8051: ? sets the endpoint valid bit for the endpoint. ? sets the endpoints fifo size by loading a starting address (section 8.4, "setting isochronous fifo sizes"). ? enables the sof interrupt. all isochr onous endpoints are serviced in response to the sof interrupt. 8.3.2 out data transfer when an sof interrupt occurs, the 8051 is presented with fifos containing out data sent from the host in the previous frame, along with 10-bit byte counts, indicating how many bytes are in the fifos. the 8051 has 1 ms to transfer data out of these fifos before the next sof interrupt arrives. registers associated with an iso out endpoint (ep15out shown as example) 13 outisoval endpoint valid (1=valid) usbien sofie (1=enabled) 8 14 12 11 15 10 9 5 7 6 4 3 1 2 0 initialization 0 out15data data transfer usbirq sofir (1=clear request) 5 7 6 4 3 1 2 0 1 2 3 4 5 6 7 received byte count (h) 8 9 2 3 4 5 6 7 received byte count (l) 0 1 2 3 4 5 6 7 out15bch out15bcl isoerr out15 crc error (1=error) 13 10 14 12 11 15 9 8 data from usb out15addr fifo start address (see text) a7 a4 a8 a6 a5 a9 0 0
ez-u s b s er i e s 2 1 0 0 t r m v 1.8 c h a p t e r 8 . ez-u s b i s o c h r o n o u s t r a n s f ers pa g e 8-5 t o respond to the sof interrupt, the 8051 cle a r s the usb interrupt (8051 int2), and clears the sofir bit by writing one to it. then, the 8051 rea d s data fro m the appropriate out n d a ta f ifo register(s). the 8051 can check an erro r bit i n t he isoerr register to determine if a c r c e rror occurre d for the endpoint da t a. isoch r onous data is never p r e sent, so the f irmware must decide what to do wit h bad - c r c data. up to sixtee n e z - u s b isochr onou s endpoin t s s h a re a n e z-usb 1,024-byte r am which can be configured a s one to six t een fifos. the 8051 in i tializes t h e endpoi n t fifo sizes by sp e cifying th e starti n g a d d r e s s for e ach f ifo w i thin th e 1,024 byte s , s tar t in g at address zero. the isochronous fifos can exist anywhere in the 1,024 b y te s , but the user m ust take care to ensure t h at there i s sufficient space between s tar t a dd r esses t o accommodate the endpoint f i fo size. sixt e en s ta r t address registers s e t the isochronou s fifo size s (table 8-1). t h e ez-usb core c o n str u c t s the addr e ss writing the 1,024 byt e range from the regist e r value as shown in figu r e 8-4. f i g u re 8 - 4 . f i f o s t art a d dre s s f o rmat 8.4 setting isochronous fifo s izes a9 a8 a7 a6 a5 a4 0 0 0 0 register address
p a g e 8 - 6 c h a p t e r 8 . e z - u s b i s o c h r o n o u s t r a n s f er s e z - u s b s e r i es 2 1 0 0 t rm v 1 . 8 the size of an isochronous endpoint fifo is determined by subtracting consecutive addres s es in t abl e 8-1, and multiplying by f our . val u es written t o t h es e r egisters should have the two ls b s s e t to zero. the l a st endpoint, ep15in, has a size of 1,024 minus i n15 a dd r t i me s four . because th e 10- b it e ff e ctive addr e ss has th e f our lsbs se t t o zero ( figur e 8-4), the fi f o siz e s a r e allocated in increments of 16 bytes . for example, if out 8 addr=0x00 and ou t 9ad d r=0x04, ep 8 ou t has a fifo size o f the difference mul t iplied by four or 1 6 b y tes. an 8051 as s embler or c compiler may be used t o transla t e fi f o s i zes i n to s t arting addres s es. the a ssembler e x am p l e in figure 8-5 shows a block of e q uates for the 16 iso- chronous fifo s izes, followed b y assembler equat i ons to compute the c o rresponding f i fo r elative address va l ues. to ini t i a l i ze all six t een fi f o sizes, the 8051 merely copies the table starti n g at 8 o utad to t he s i xteen ez- u sb r e gisters starting at o ut8addr. t a b l e 8 - 1. i s o c h r o n ous e n d p o i nt f i fo s t a r t ing a d d r e ss registers reg i ster f u n c t i o n b7 b6 b5 b4 b3 b2 b1 b0 o u t 8 a ddr e ndp o i n t 8 o u t s t a rt address a9 a 8 a 7 a6 a 5 a4 0 0 o u t 9 a ddr e ndp o i n t 9 o u t s t a rt address a9 a 8 a 7 a6 a 5 a4 0 0 o u t 1 0 add r e ndp o i n t 1 0 o u t s t ar t a ddress a9 a 8 a 7 a6 a 5 a4 0 0 ou t 1 1a d dr e ndp o i nt 11 o u t s t a r t address a9 a 8 a 7 a6 a 5 a4 0 0 o u t 1 2 add r e ndp o i n t 1 2 o u t s t ar t a ddress a9 a 8 a 7 a6 a 5 a4 0 0 o u t 1 3 add r e ndp o i n t 1 3 o u t s t ar t a ddress a9 a 8 a 7 a6 a 5 a4 0 0 o u t 1 4 add r e ndp o i n t 1 4 o u t s t ar t a ddress a9 a 8 a 7 a6 a 5 a4 0 0 o u t 1 5 add r e ndp o i n t 1 5 o u t s t ar t a ddress a9 a 8 a 7 a6 a 5 a4 0 0 i n8a d dr e ndp o i n t 8 i n s t a rt address a9 a 8 a 7 a6 a 5 a4 0 0 i n9a d dr e ndp o i n t 9 i n s t a rt address a9 a 8 a 7 a6 a 5 a4 0 0 i n1 0 addr e ndp o i n t 10 in s t art address a9 a 8 a 7 a6 a 5 a4 0 0 i n 1 1ad d r e ndp o i nt 11 i n s t art address a9 a 8 a 7 a6 a 5 a4 0 0 i n1 2 addr e ndp o i n t 12 in s t art address a9 a 8 a 7 a6 a 5 a4 0 0 i n1 3 addr e ndp o i n t 13 in s t art address a9 a 8 a 7 a6 a 5 a4 0 0 i n1 4 addr e ndp o i n t 14 in s t art address a9 a 8 a 7 a6 a 5 a4 0 0 i n1 5 addr e ndp o i n t 15 in s t art address a9 a 8 a 7 a6 a 5 a4 0 0
ez-u s b s er i e s 2 1 0 0 t r m v 1.8 c h a p t e r 8 . ez-u s b i s o c h r o n o u s t r a n s f ers pa g e 8-7 f i g u r e 8 - 5. a ss e m b l e r t r an s l ates f i f o sizes to a d d r esses the a ssembler c omput e s st a rting addr e sses in f i gure 8-5 by adding th e prev i ous end- point s add r e s s to the desired s ize shifted right twice. t h is a l igns a9 with bit 7 as shown in t abl e 8-1. the low o p e r a tor t akes the low byte of the resulting 16 bit e xpression the us e r o f this code mu s t ensu r e that t h e s i zes given in t h e f i r st e q u a te block a r e all mul- ti p l es o f 16. th i s i s easy to tell by ins p e ctionthe l e a s t s i gnifican t digit of the h e x values in the f irst column should be zero. 0100 ep8insz equ 256 ; i so fifo sizes in bytes 0100 ep8outsz equ 256 0010 ep9insz equ 16 0010 ep9outsz equ 16 0010 ep10insz equ 16 0010 ep10outsz equ 16 0000 ep11insz equ 0 0000 ep11outsz equ 0 0000 ep12insz equ 0 0000 ep12outsz equ 0 0000 ep13insz equ 0 0000 ep13outsz equ 0 0000 ep14insz equ 0 0000 ep14outsz equ 0 0000 ep15insz equ 0 0000 ep15outsz equ 0 ; 0000 8outad equ 0 ; load these 16 bytes into addr regs starting out8addr 0040 9outad equ 8outad + low(ep8outsz/4) 0044 10outad equ 9outad + low(ep9outsz/4) 0048 11outad equ 10outad + low(ep10outsz/4) 0048 12outad equ 11outad + low(ep11outsz/4) 0048 13outad equ 12outad + low(ep12outsz/4) 0048 14outad equ 13outad + low(ep13outsz/4) 0048 15outad equ 14outad + low(ep14outsz/4) 0048 8inad equ 15outad + low(ep15outsz/4) 0088 9inad equ 8inad + low(ep8insz/4) 008c 10inad equ 9inad + low(ep9insz/4) 0090 11inad equ 10inad + low(ep10insz/4) 0090 12inad equ 11inad + low(ep11insz/4) 0090 13inad equ 12inad + low(ep12insz/4) 0090 14inad equ 13inad + low(ep13insz/4) 0090 15inad equ 14inad + low(ep14insz/4)
p a g e 8 - 8 c h a p t e r 8 . e z - u s b i s o c h r o n o u s t r a n s f er s e z - u s b s e r i es 2 1 0 0 t rm v 1 . 8 the amount o f d ata usb ca n transfer during a 1 - m s fr a me is slightly more than 1,000 bytes per f r a m e (1,500 bytes th e o r e t ical, without accounting for usb overhead and bus ut i l i zation). a devi c e s actual isoch r onous transfer band wi dth is usually d e termined by how fa s t the cpu can move data in and out o f i t s isochronous endpoin t fi f os. the 8051 code e x amp l e in figure 8-6 shows a t y p i cal transfer loop for moving ext e r nal f i fo data into an in endpoint f i fo. this code assumes that the 8051 i s mov i n g data f rom an externa l fif o a t t a ched t o the e z -us b data bu s and strobed by th e rd s ignal , into an internal i sochronous i n f i fo. f i g u r e 8 - 6 . 8 0 5 1 c od e t o t r an s fe r d a t a to a n i s o c h rono u s f i f o ( i n8data) the numbers in parenthe s es ind i cate 8051 cycl e s. one cycle is f o u r clocks, and th e ez- usb 8051 i s clocked at 24 mhz (4 2 n s ). t h u s, an 8051 cycle takes 4*42 = 168 ns, and the loop takes 9 cycles or 1. 5 m s. this loop c an transfer about 660 byt e s into an i n fifo every millisecond (1 ms/1. 5 m s ) . i f more speed is r equi r ed, the loop can b e un r olled by in-line coding the f i rst four instruc- tions in the loop. then, a byte is tra n s ferred in 6 c ycles (24 clocks) which e q u a tes to 1 m s per byte. using this method, the 8051 could t r an s f e r 1,000 bytes into a n in f ifo every m i l l isecond. i n p r actice, a bette r s o lution is to in- l ine code onl y a portio n o f t h e loo p code, which decr e ase s f ull i n -l i n e per f ormance o n l y slight l y and uses f a r fewe r bytes of program code. 8.5 i sochronous tr ansfer s peed mov d p tr,#8000h ; p ointer to any outside address inc d p s ; switch to second data pointer mov d p tr,#in8data ; pointer to an in endpoint fifo (in8 as example) inc d p s ; b ack to first data pointer mov r 7 ,#nbytes ; r 7 is loop countertransfer this many bytes ; loop: movx a , @dptr ; ( 2) read byte from external bus to acc inc d p s ; ( 1) switch to second data pointer movx @ d ptr,a ; (2) write to iso fifo inc d p s ; ( 1) switch back to first data pointer djnz r 7 ,loop ; ( 3) loop nbytes times
ez-u s b s er i e s 2 1 0 0 t r m v 1.8 c h a p t e r 8 . ez-u s b i s o c h r o n o u s t r a n s f ers pa g e 8-9 e z - u s b has a sp e cia l fa s t tran s fer mode for applica t ions th a t use ex t er n al f ifos con- nected to th e e z -usb data bus. th e se a p p l ications t y p ically r e quire very h igh t r a nsfer speeds in and out of e z-usb endpoint b u ffers. f i g u r e 8 - 7 . 8 0 51 mo v x i n s t r u c tions the 8051 transfers data to and from e z-usb regi s t e rs and ram using the movx (move external ) instruction (figure 8-7). the 8051 loads one o f its two 16-bit data poi n t e rs ( d p tr) with an address in ram, and then executes a m o vx i n str u c tion to transfer data between the a ccumulat o r and the byte a d d r e ssed b y d ptr. t he @ symbo l i n dicates that the addr e ss is supplie d i n d i r e ctly, b y t he dptr. the e z -usb co r e monit o r s movx transfers between the accum u lator and any of the s i x - tee n isochronous fif o r e g i ster s . if an enable b i t is s e t (fiso=1 in t h e f astx f r re g is- te r ), any r e a d or write to a n isochr onous fi f o r e g i s t er c a u s e s t h e ez - u s b c o r e t o c onnect the d a t a to the ez-usb d a t a bus d[7..0], a n d generate external read/write str o b es . o ne movx instructi o n thus transfers a byte of data in o r out of an endpo i nt fifo a n d gener- ates t im i n g str o b es for an out s i de fifo or m e m ory. the 2-cycle m o vx instruction takes 2 cy c les or 333 n s. fi g u r es 8-8 and 8-9 show the da t a flow f o r f ast write s and rea d s over the e z -usb data bu s . 8.6 fast t ra n s f e r s movx @dptr,a accumulator dptr ez-usb registers (addressed as external ram) movx a,@dptr
page 8-10 chapter 8. ez-usb isochronous transfers ez-usb series 2100 trm v1.8 8.6.1 fast writes figure 8-8. fast transfer, ez-usb to outside memory fast writes are illustrated in figure 8-8. when the fast mode is enabled, the dptr points to an isochronous out fifo register, and the 8051 executes the movx a,@dptr instruc- tion, the ez-usb core broadcasts the data from the isochronous fifo to the outside world via the data bus d[7..0], and generates a write strobe fwr# (fast write). a choice of eight waveforms is available for the write strobe, as shown in the next section. fast bulk transfers the ez-usb core provides a special auto-incrementing data pointer that makes the fast transfer mechanism available for bulk transfers. the 8051 loads a 16-bit ram address into the autoptrh/l registers, and then accesses ram data as a fifo using the autodata register. section 6.16, "the autopointer" describes this special pointer and register. accumulator dptr iso out fifo fwr# movx a,@dptr d[7..0] external fifo or asic
ez-u s b s er i e s 2 1 0 0 t r m v 1.8 c h a p t e r 8 . ez-u s b i s o c h r o n o u s t r a n s f ers p a ge 8-11 8.6.2 fa s t reads f i g u re 8 - 9 . f a s t t r an s f e r , o u t s i d e m e m o r y t o e z - u sb fast r e ads ar e i llustrated in figure 8-9. when the f a s t mode i s enabled, the d ptr points to an isochronous out f if o regist e r, and the 8051 executes t h e m ovx @ d p tr,a instruc- tion, t h e e z-usb c o re breaks the data pa t h from the accumulator to t he in fifo r e g ister, and instead w rites t h e i n fifo using outsi d e d ata from d[7..0]. th e e z - u s b core syn- chron i z es this transfer by gen e r a ting a f i fo rea d str o b e frd # ( fast read). a choice of eight wav e form i s availa b le f or the read strobe, as shown in the next section. the 8051 sets bits in th e fa s tx f r register to s e l ec t the fa s t iso and / or fast bul k mode and to adjust the timing and polarit y of the r e ad and wri t e strobes frd# and fwr#. f i g u r e 8 - 10. t h e f a s t x f r r e g i s t e r c ont r o l s f r d# a n d f w r # strobes the 8051 s ets f i so=1 to s elect t he fa s t iso mode and fblk=1 to s e l ect t he fast bulk mode. the 8051 s e l e cts r ead and w r ite strobe p u l se p o l a ri t ies with the rpol and wpol bits, where 0=acti v e low, and 1=act i ve high. r e ad and wri t e s tr o b e timings are set by 8.7 fast t ra n s f e r t iming f a s t x f r fast t ransfer co n trol 7 f e2 b7 b6 b5 b4 b3 b2 b1 b0 fi s o fblk rpol rmod1 rmod0 w p ol w m o d 1 w m o d 0 accumulator dptr iso in fifo d[7..0] movx @dptr,a frd# external fifo or asic
p a ge 8- 1 2 c h a p t e r 8 . ez-u s b i s o c h r o n o u s t r a n s f ers e z -usb se r i e s 2 1 00 t r m v1.8 r m od 1 - r mod0 for read st r obes and wmo d 1-wmod0 for write st r obes, as shown in figur e 8 - 1 1 ( w rite) and f i gure 8- 1 2 ( re a d). 8.7.1 fa s t w rite w avefo r m s f i g u re 8 - 1 1. f a s t w r i t e t i ming note when u sing the f a st transfer feature, be sure to enable the frd # a nd fw r # strobe sig- nals in the po r t acfg r eg i s te r . c l k 2 4 f w r # [ 00] d [ 7 . . 0 ] o u t p u t t c l 41 . 66 ns f w r # [ 01] f w r # [ 10] f w r # [ 11] f w r # [ 00] d [ 7 . . 0 ] o u t p u t f w r # [ 01] f w r # [ 10] f w r # [ 11] n o t e : i f w p o l = 1 t h e w a v e f o r m s a r e i n v e r t e d s t re t c h=0 0 0 s t re t c h=0 0 0 s t re t c h=0 0 0 s t re t c h=0 0 0 s t re t c h=0 0 0 s t re t c h=0 0 1 s t re t c h=0 0 1 s t re t c h=0 0 1 s t re t c h=0 0 1 s t re t c h=0 0 1 [ nn ] = w m o d 1 : w m o d 0 , w p o l = 0
ez-u s b s er i e s 2 1 0 0 t r m v 1.8 c h a p t e r 8 . ez-u s b i s o c h r o n o u s t r a n s f ers p a ge 8-13 the t i ming c h o i ces fo r f ast write pu l ses (fwr#) are shown in figure 8 -11. the 8051 can extend the output data and widths of these pulses by setting cycle s t r e t ch values greater than z ero in the 8051 c lock control r egister c kco n ( a t sfr l o cat i on 0x8e). the top f ive waveforms show t h e fast e st write t i mings, wi t h a stretch value of 000, w hich per- forms the write i n eight 8051 cloc k s. the bottom five wave f orms show the same wave- forms with a stretch value of 001. 8.7.2 fa s t rea d w avefo r m s f i g u r e 8 - 12 . f a s t r e a d timing the timing c h o ices fo r f ast r ea d pulse s (frd#) are s hown in figure 8-12 . read strobe wavefo r ms for s t retch values of 000 and 001 a r e indicated. although two o f the read strobe widths c a n be extended usi n g s t r e tch values greater t h an 000 , the times that the input data is sampled by the e z -u s b cor e remai n s the sa m e as shown. o s c 2 4 f rd # [ 0 0 ] d [ 7 . . 0 ] in t c l 41 . 66 ns f rd # [ 1 0 ] f rd # [ 1 1 ] d [ 7 . . 0 ] in d [ 7 . . 0 ] d [ 7 . . 0 ] in in f rd # [ 0 1 ] f rd # [ 1 0 ] f rd # [ 1 1 ] s t re t c h=0 0 0 , 0 0 1 s t re t c h=0 0 0 , 0 0 1 s t re t c h=0 0 0 s t re t c h=0 0 1 s t re t c h=0 0 0 s t re t c h=0 0 1 n o t e : i f w p o l = 1 t h e w a v e f o r m s a r e i n v e r t e d [ nn ] = r m o d 1 : r m o d 0 , r p o l=0
p a ge 8- 1 4 c h a p t e r 8 . ez-u s b i s o c h r o n o u s t r a n s f ers e z -usb se r i e s 2 1 00 t r m v1.8 frd# s trob e s [00 ] and [01], along with the osc24 clock signal a r e typical l y used to con- nect to an exter n al synchr onous f i f o. the on-clock-wide read strobe ensures that the f i fo add r e s s advances only on c e per clock. t he s econd s tr o b e [01] is f or f ifos that put data on the bus one clock afte r the read strobe . stretch values above 000 serve only to extend the 8051 cycle ti m es, wi t hou t affecting the width of the f r d# s t robe. frd# s trob e s [10] and [ 1 1 ] are typically connected to an external a s ynch r onou s f ifo, where no clock i s required. strobe [10] s amp l e s t h e data at t h e same time as strobe [11], but provides a wider p u lse width (for stre t c h = 0 0 0 ), wh i ch i s required by s ome audio codecs . timing v alues for t h ese s t robe s i g n a ls are given in chapt e r 13 , e z - u sb ac/ d c pa r a m e t e r s . the 8051 code e x amp l e in figure 8-13 shows a t ra n s f e r loop f o r moving externa l fifo data into the endpoint 8 - in f ifo. this code mov e s data fr o m an exter n al f ifo attached to the e z -usb d a ta bus and s t robed by the frd# signal, into the fi f o r eg i s ter in8 d a ta f i g u r e 8 - 13 . 805 1 c o d e to t r a n s f e r 6 4 0 b y t es o f e x te r n a l d a ta t o an i s o c h r o n ous i n fifo this rout i ne u ses a combi n a ti o n of i n-line and looped code to transfer 640 bytes into the e p8in fi f o from an ex t e rnal f i fo. the loop transfers eight bytes in 19 cycle s , and it takes 80 ti m es through the loop to tr a n sfer 640 b y tes. t h erefore, the t o t a l transfer time is 80 t imes 19 cycles, or 1,520 cyc l e s . the 640 byte transfer thus takes 1,520*166 ns o r 252 m s , or a pproxim a t el y one-fourth o f the 1-ms usb frame time. using th i s routine, the time to complet e ly fill one is o ch r onou s fifo with 1,024 bytes ( a ssuming all 1,024 isochronou s fifo bytes a re assign e d to one endpoint) would be 128 8.8 fast t ra n s f e r speed (init) mov d p tr,#fastxfr ; s et up the fast iso transfer mode mov a , #10000000b ; f iso=1, rpol=0, rm1-0 = 00 movx @ d ptr,a ; load the fastxfr register mov d p tr,#in8data ; p ointer to in endpoint fifo mov r 7 ,#80 ; r 7 is loop counter, 8 bytes per loop ; loop: movx @ d ptr,a ; ( 2) write in fifo using byte from external bus movx @ d ptr,a ; (2) again movx @ d ptr,a ; (2) again movx @ d ptr,a ; (2) again movx @ d ptr,a ; (2) again movx @ d ptr,a ; (2) again movx @ d ptr,a ; (2) again movx @ d ptr,a ; (2) again djnz r 7 ,loop ; ( 3) do eight more, r7 times
ez-usb series 2100 trm v1.8 chapter 8. ez-usb isochronous transfers page 8-15 times 19 cycles, or 2,432 cycles. the 1,024 byte transfer would take 403 m s, less than half of the 1-ms usb frame time. if still faster time is required, the routine can be modified to put more of the movx instructions in-line. for example, with 16 in-line movx instructions, the transfer time for 1,024 bytes would be 35 cycles times 64 loops or 2,240 cycles, or 371 m s, an 8% speed improvement over the eight instruction loop. two additional registers, isoctl and zbcout, provide additional isochronous end- point features. 8.9.1 disable iso figure 8-14. isoctl register bit zero of the isoctl register is called isodisab. when the 8051 sets isodisab=1, all sixteen of ez-usb endpoints are disabled. if isodisab=1, ep8in=ep15in and ep8out-ep15out should not be used. isodisab is cleared at power-on. when isodisab=1, the 2,048 bytes of ram normally used for isochr onous buf fers is available to the 8051 as xdata ram ( not program memory), from 0x2000 to 0x27ff in internal memory. when isodisab=1, the behavior of the rd# and wr# strobe signals changes to reflect the additional 2 kb of memory inside the ez-usb chip. this is shown in table 8-2. 8.9 other isochronous registers isoctl isochronous control 7fa1 b7 b6 b5 b4 b3 b2 b1 b0 - - - - ppstat mbz mbz isodisab table 8-2. addresses for rd# and wr# vs. isodisab bit isodisab rd#, wr# 0 (default) 2000-7b40, 8000-ffff 1 2800 -7b40, 8000-ffff
p a ge 8- 1 6 c h a p t e r 8 . ez-u s b i s o c h r o n o u s t r a n s f ers e z -usb se r i e s 2 1 00 t r m v1.8 i so c tl register b i ts shown a s mbz (must be zero) m ust b e written with zeros. the p p s t a t bit toggles ever y s o f, and may b e written with an y val u e (n o effect). t h e refore, to disabl e the isochronous endpoints, th e 805 1 should writ e the v a lue 0x01 to th e i soctl r eg i s te r . 8.9.2 zero byte co u nt b i ts when the sof interr u p t is a s serted, the 8051 n o r mally c h ecks the isoch r onous out end- point f i fos for data. before reading the byte count registers and unloading an isochro- nous f ifo, the firmwar e m ay wish to check for a z e r o byte count. in this ca s e, the 8051 ca n c h eck bits in the z b c ou t reg i s ter. any endpoi n t bit set to 1 i n d icate s that no out bytes were re c eived f o r that endpoint d u ring the previous f rame. fi g u re 8-15 sho w s this r eg i s te r . f igu r e 8 -15 . z b c out r e gist e r the e z-usb co r e updates the s e bits every s o f. ca u tion! if you use this option, be absolutely certain th a t the host never sends isochronous data to your dev i c e. isochronous data di r e cted to a di s abled isochronous endpoint sy s tem will cause unp r ed i c table operation. note the autopointer is not usable f rom 0x2000-0x27ff (the reclai m ed i s o buffer ram) when i s o d i sab=1. z b cout z e r o byte count bits 7 f a2 b7 b6 b5 b4 b3 b2 b1 b0 e p 15 e p 14 e p 13 e p 12 ep 1 1 ep10 ep9 ep8
ez-usb series 2100 trm v1.8 chapter 8. ez-usb isochronous transfers page 8-17 the isosend0 bit (bit 7 in the usbpair register) is used when the ez-usb chip receives an isochronous in token while the in fifo is empty. if isosend0=0 (the default value) the ez-usb core does not respond to the in token. if isosend0=1, the ez-usb core sends a zero-length data packet in response to the in token. which action to take depends on the overall system design. the isosend0 bit applies to all of the isoch- ronous in endpoints, in-8 through in-15. there is a window of time before and after each sof (start of frame) when accessing the isochronous fifos will cause data corruption or loss of data. this is because each isochronous endpoint is actually a pair of fifos, and the fifos are swapped at sof time. the swap occurs about 10 m s before the sof interrupt signals the 8051 code. (between sofs, one fifo of the pair is accessible to the 8051, while the other fifo of the pair transfers data to or from the usb.) workaround#1: if you can pre-assemble the data into a buffer, blast the data (in a tight loop) into the new fifo just after the sof interrupt, typically inside the sof isr (inter- rupt service routine). workaround#2: if you cant pre-assemble the data into a buffer, prevent access during sofs by setting a time (in the sof isr) to time out and halt access just before the next sof. set the timer for about 950 m s (ms minus 50 m s). be careful of interrupt latency delaying the timeout isr. that is, the timeout isr may be prevented from halting access by getting preempted by a higher priority interrupt(s), made worse by the necessary practice of disabling interrupts to manage shared resources, resources that are shared between the isrs and backgr ound p rocess. to prevent drift of the timer relative to sofs, restart the timer after each sof (typically in the sof isr). 8.10 iso in response with no data 8.11 using the isochronous fifos
page 8-18 chapter 8. ez-usb isochronous transfers ez-usb series 2100 trm v1.8
ez-u s b s er i e s 2 1 0 0 t rm v 1.8 c h a p t e r 9 . ez-u s b i n t e r r u pts p a g e 9-1 9 e z- usb interrupts the e z -usb enhanced 8051 res pond s t o t h e i n t e r r up t s shown i n table 9-1. interrupt sourc e s that a re not pr e sent in t h e standa r d 8051 are sho w n as checked in t he new col- umn. the three i n t e rrupts used by the ez- u s b core are shown i n bol d typ e . the n a t ural p r i o r i t y column in t abl e 9-1 shows the 8051 interrupt p r iori t i es. as explained in appendix c, the 8051 can a s sign e ach interrupt to a high or l o w priority group. the 8051 resolves p r iorities within the groups using the natura l prio r i ties. the e z -usb co r e provid e s three int e rrupt requ e st t y p es, whi c h are d e s cribed in th e fol- lowing se c tions: w akeup - after the e z - u sb chip detects usb suspend and the 8051 has entered i t s id l e s t at e , the e z - u s b c o re r esponds to an ex t er n a l si g n al on its w a k eup# pi n or resumpt i o n of u sb bus acti v i ty by r e-starting the ez- usb o s cilla t or a nd resumi n g 8051 o p eration. 9.1 i n t roduction t a b le 9- 1 . ez-u s b in t e r r upts n e w 8 0 5 1 i nt e r r u pt ( ir q name) s o urce vec t or ( hex) n at u ral pr i o r i ty i e0 i nt0# pin 03 1 tf0 t i m er 0 o v er f l ow 0b 2 i e1 i nt1# pin 13 3 tf1 t i m er 1 o v er f l ow 1b 4 r i _0 & t i_0 uar t 0 rx & t x 23 5 tf2 t i m er 2 o v er f l ow 2b 6 r e s u me (p f i) wak e up# p i n or u s b c o r e 33 0 r i _1 & t i_1 uar t 1 rx & t x 3b 7 u s b ( i n t 2) u s b c o r e 43 8 i 2 c ( i nt3) usb c ore 4b 9 i e4 i n4 pin 53 10 i e5 i nt5# pin 5 b 1 1 i e6 i nt6 pin 63 12 9.2 usb c o re inte r rupts
page 9-2 chapter 9. ez-usb interrupts ez-usb series 2100 trm v1.8 usb signaling - these include 16 bulk e ndpoint interrupts, three interrupts not specific to a particular endpoint (sof), suspend, usb reset), and two interrupts for control transfers (sutok, sudav). these interrupts share the usb interrupt (int2). the an2122/26 versions have an inter- rupt indicating that a bulk packet was nakd. i 2 c transfers - (int3). chapter 10, "ez-usb resets" describes suspend-resume signaling in detail, along with a code example that uses the wakeup interrupt. briefly, the usb host puts a device into suspend by stopping bus activity to the device. when the ez-usb core detects 3 ms of no bus activity, it activates the usb suspend inter- rupt request. if enabled, the 8051 takes the suspend interrupt, does power management housekeeping (shutting down power to external logic), and finishes by setting sfr bit pcon.0. this signals the ez-usb core to enter a very low power mode by turning off the 12-mhz oscillator. when the 8051 sets pcon.0, it enters an idle state. 8051 execution is resumed by activa- tion of any enabled interrupt. the ez-usb chip uses a dedicated interrupt for usb resume. when external logic pulls wakeup# low (for example, when a keyboard key is pressed or a modem receives a ring signal) or usb bus activity resumes, the ez-usb core re-starts the 12-mhz oscillator, allowing the 8051 to recognize the interrupt and con- tinue executing instructions. figure 9-1. ez-usb wakeup interrupt figure 9-1 shows the 8051 sfr bits associated with the resume interrupt. the ez-usb core asserts the resume signal when the ez-usb core senses a usb global resume, or when the ez-usb wakeup# pin is pulled low. the 8051 enables the resume inter- rupt by setting eicon.5. 9.3 wakeup interrupt eicon.5 eicon.4(rd) eicon.4(0) s r 8051 "resume" interrupt resume signal from ez-usb core
ez-usb series 2100 trm v1.8 chapter 9. ez-usb interrupts page 9-3 the 8051 reads the resume interrupt request bit in eicon.4, and clears the interrupt request by writing a zero to eicon.4. tb eicon.5 ; enable resume interrupt resume_isr: clr eicon.4 ; clear the 8051 w/u ; interrupt request reti
page 9-4 chapter 9. ez-usb interrupts ez-usb series 2100 trm v1.8 figure 9-2 shows the 21 usb requests that share the 8051 usb (int2) interrupt. the bot- tom irq, ep7-out, is expanded in the diagram to show the logic associated with each usb interrupt request. vector 05, not shown in the diagram, exists only in the an2122/ an2126, and is described later in this chapter. figure 9-2. usb interrupts 9.4 usb signaling interrupts 8051 ez-usb ep0-in ep0-ou ep1-in ep1-ou ep2-in ep2-ou ep3-in ep3-ou sutok sudav sof susp eie.0 exif.4(rd) exif.4(0) s r 8051 "usb" interrupt out07ien.7 in07irq.7(1) s r in07irq.7 (rd) ures ep4-in ep4-ou ep5-in ep5-ou ep6-in ep6-ou ep7-in ep7-ou 0 iv4 iv3 iv2 iv1 iv0 0 0 avec 00 01 02 03 04 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 interrupt request latch ibn int 05
ez-u s b s er i e s 2 1 0 0 t rm v 1.8 c h a p t e r 9 . ez-u s b i n t e r r u pts p a g e 9-5 refer r ing to the log i c inside the do t ted lines, ea c h u sb interrupt source has an interrupt r equest latch. t h e ez-usb core s e ts an irq bit, an d the 8051 clears a n irq b i t by w r iting a 1 t o it . the output o f e a c h latch is anded with an ie n (interrup t e nab l e ) bi t and then ord with all the other usb interr u p t r e quest s o u rces. the e z -usb co r e priorit i zes t h e usb int e r r upts, and constructs an a u tov e ctor, which appears in th e a v ec regist e r . the i n t e rrup t ve c t o r values i v [4..0] are shown t o the left o f the interr u p t sour c es (shaded b o x es) . 00 is the highe s t pri o rity, 15 is the l owes t . if two usb inte r rupts occu r s imultaneous l y, the prioritiz a t ion affects which one is first indicated in the a vec r eg i s te r . if the 8051 h as enabled aut o v ectoring, t h e ave c b y te replaces byte 0x45 in 8051 program mem o ry. this c a uses the us b i n terrupt autom a tically to vec- to r to d i f f erent addr e sses for e a c h usb in t errupt sourc e . this me c hanism is explained in detail i n section 9.10, "usb autovect o r s ." due to the o r g a t e in figur e 9-2, any o f the u s b interrupt sour c es sets the 805 1 us b inte r rupt reque s t latch, w h o se state appears as an interrupt r e quest in the 8051 sfr bit e xi f .4. the 8051 enables the usb interrupt by s etting s fr b i t e ie.0. to clear the usb inte r rupt reque s t the 8051 writes a zero to t he e xi f .4 bit. note that this i s the opposite of cleari n g any of the individua l usb interrupt sour c es , whic h the 805 1 does by writing a 1 to the i r q bit. whe n a u s b resou r ce requi r e s servi c e (fo r e xa m p le , a so f tok e n arrives or a n ou t token ar r ives on a b u l k endpoint ) , two things happen. first, the cor r esponding inter r upt reque s t latch i s set. second, a pul s e is generated, ord with the other usb interrupt logic, and routed to the 8051 int2 input. t h e pu l se is requ i red b eca u se int2 is edg e trig- gered. when the 8051 f inish e s servicing a usb i n t e rrupt, it cl e ars th e partic u l ar irq bit b y writ- in g a 1 to it . if a n y o t her usb inter r upts are pending, the a c t of clearing the irq causes the e z - u s b co r e logic to generat e anot h er pulse for th e high e s t-pr i orit y pendin g interrupt. i f more that one is pending, they are serviced in the p riority order shown in figure 9-2, starting wit h s u d a v (pr i or i ty 00) as the highest p r i o rity, and endi n g with e p 7-out (pri- o r it y 15) as the l o west. important it i s im p o rt a nt in any usb interrupt service r o u t i ne ( isr) to c l ear t h e 8051 int2 inter- rupt be fo re clearing the par t icul a r usb in t e rrupt requ e s t latch. this is be c a u se as soon as the usb in t e r rupt i s cl e a red, any pendi n g u sb interrupt will p u lse the 8051 int2 input, and i f t h e int2 inte r rup t reque s t latch has no t been previously cleare d the pending interr u pt will be lost.
page 9-6 chapter 9. ez-usb interrupts ez-usb series 2100 trm v1.8 figure 9-3 illustrates a typical usb isr for endpoint 2-in. figure 9-3. the order of clearing interrupt requests is important usb_isr: push dps push dpl push dph push dpl1 push dph1 push acc ; mov a,exif ; first clear the usb (int2) interrupt request clr acc.4 mov exif,a ; note: exif reg is not 8051 bit-addressable ; mov dptr,#in07irq ; now clear the usb interrupt request mov a,#00000100b ; use in2 as example movx @dptr,a ; ; (perform interrupt routine stuff) ; pop acc pop dph1 pop dpl1 pop dph pop dpl pop dps ; reti
ez-usb series 2100 trm v1.8 chapter 9. ez-usb interrupts page 9-7 figure 9-4. ez-usb interrupt registers figure 9-4 shows the registers associated with the usb interrupts. each interrupt source has an enable (ien) and a request (irq) bit. the 8051 sets the ien bit to enable the inter- rupt. the usb core sets an irq bit high to request an interrupt, and the 8051 clears an irq bit by writing a 1 to it. in07irq endpoints 0-7 in interrupt requests 7fa9 b7 b6 b5 b4 b3 b2 b1 b0 in7ir in6ir in5ir in4ir in3ir in2ir in1ir in0ir out07irq endpoints 0-7 out interrupt requests 7faa b7 b6 b5 b4 b3 b2 b1 b0 out7ir out6ir out5ir out4ir out3ir out2ir out1ir out0ir usbirq usb interrupt request 7fab b7 b6 b5 b4 b3 b2 b1 b0 - - - usesir suspir sutokir sofir sudavir in07ien endpoints 0-7 in interrupt enables 7fac b7 b6 b5 b4 b3 b2 b1 b0 in7ien in6ien in5ien in4ien in3ien in2ien in1ien in0ien out07ien endpoints 0-7 out interrupt enables 7fad b7 b6 b5 b4 b3 b2 b1 b0 out7ien out6ien out5ien out4ien out3ien out2ien out1ien out0ien usbien usb interrupt enables 7fae b7 b6 b5 b4 b3 b2 b1 b0 - - - uresie suspie sutokie sofie sudavie
p a g e 9 - 8 c h a p t e r 9 . ez-u s b i n t e r r u pts e z -usb s e r i e s 2 1 0 0 t r m v 1.8 the usbie n and usbirq registers control the f i r s t f i v e i n terrupts shown in figure 9-2. the in07i e n and out07 reg i s t e r s control the remaining 16 usb int e r rupts, whi c h corre- spond to the 16 bulk endpoin t s in0 - in7 a n d out0-out7. the 21 u s b interrupts are now de s cribed in detail. f i g u r e 9 - 5 . s u t o k a n d s u d a v i n t e rrupts su t ok a n d s u d av are supp l ied to the 8051 b y ez-usb c o n t r ol endpoint zero. the f i r s t por t ion o f a usb c o n t r o l trans f er is the s etup stage shown in f i gure 9-5. ( a full c o n t r ol transfer i s t he s etu p st a g e shown i n f i gure 7-1.) when th e ez-usb core decodes a se t up packet, i t a s s e rts t h e s u to k (setup t oken) inte r rupt request. a f t e r the e z -usb co r e has received the eight b y te s e r ror-free and copied them into eight intern a l registers at se t upd a t , it a s serts t h e s u dav interr u p t request. the 8051 program res pond s t o t h e s u d a v i n terr u p t by reading t he e ight setup data bytes in order to decode t he u s b reque s t ( c hapter 7, " e z-usb endpoint zero"). the su t o k interrupt is provided to give advance warning th a t the e ight r egister bytes at s e tu p d a t are about to be ov e r-wri t ten. it is useful for d e bug and diagno s tic purposes. 9.5 su t ok, su d av inte r ru p ts d a t a 0 8 bytes setup data c r c 1 6 data packet a c k h/s pkt s e t u p a d d r e n d p c r c 5 token packet setup stage sutok interrupt sudav interrupt
ez-u s b s er i e s 2 1 0 0 t rm v 1.8 c h a p t e r 9 . ez-u s b i n t e r r u pts p a g e 9-9 f i g u r e 9-6. a s tart o f frame (so f ) p a c k e t usb start of frame in t e r rupt reque s ts occur ever y mi l lisecond. whe n t h e e z -usb core r e ceives a n s of packet, it copies t h e eleve n -bit fra m e nu m ber ( frno in figure 9-6) into the us b f r ameh and usbframel r egister s , a nd act i vat e s the sof interrupt r equest. the 8051 s ervices all isoc h ronous endpoint data as a r es u lt o f the s o f i nterrupt. i f the e z -usb detects 3 ms of no bus ac t ivity, it activates the susp (suspend) interrupt r equest. a full description of suspend-resu m e s ignaling appe a r s in chapter 1 1 , "e z -usb powe r management." the usb signals a bus r e s et by driving both d+ a nd d- lo w fo r a t least 10 ms. when the ez - u s b core detects the o n se t of u sb b u s re s et , it activ a tes the u res inter r upt r equest. the remaining 16 u s b interr u pt reques t s are indexed to the 1 6 e z - u sb bulk endpoi n t s. the e z - usb co r e activa t es a bulk interrupt re q u est when the endpoin t buff e r re q u i r es s er- vice. f o r an o ut endpoint, the interr u p t request sign i f ies t h at out data has b e e n sent f ro m the host , validated by th e e z -usb co r e, and is si t tin g i n th e e ndpo i n t b u f f e r m e mory. fo r an in endpoin t , the interrupt r equ e st s igni f ies that the d a ta previously loaded by the 8051 into the in endpoint bu f fer h a s b e en read a n d val i d ated b y the h o st, making the in endpoint bu f fe r r eady to accept new data. 9.6 sof inte r rupt 9.7 suspend interr u p t 9.8 usb r e s e t int e rrupt 9.9 b u lk endpoin t interrupts s o f f r n o c r c 5 token pkt
page 9-10 chapter 9. ez-usb interrupts ez-usb series 2100 trm v1.8 the ez-usb core sets an endpoints interrupt request bit when the endpoints busy bit (in the endpoint cs register) goes low, indicating that the endpoint buffer is available to the 8051. for example, when endpoint 4-out receives a data packet, the busy bit in the out4cs register goes low, and out07irq.4 goes high, requesting the endpoint 4-out interrupt. the usb interrupt is shared by 21 interrupt sources. to save the code and processing time required to sort out which usb interrupt occurred, the ez-usb core provides a second level of interrupt vectoring, called autovectoring. when the 8051 takes a usb inter- rupt, it pushes the program counter onto its stack, and then executes a jump to address 43, where it expects to find a jump instruction to an interrupt service routine. the 8051 jump instruction is encoded as follows: if autovectoring is enabled (aven=1 in the usbbav register), the ez-usb core substi- tutes its avec byte for the byte at address 0x0045. therefore, if the programmer pre- loads the high byte (page) of a jump table address at location 0x0044, the core-inserted byte at 0x45 will automatically direct the jump to one of 21 addresses within the page. in the jump table, the programmer then puts a series of jump instructions to each particular isr. 9.10 usb autovectors table 9-2. 8051 jump instruction address op-code hex valu 0043 jump 0x02 0044 addrh 0xhh 0045 addrl 0xll
ez-usb series 2100 trm v1.8 chapter 9. ez-usb interrupts page 9-11 a detailed example of a program that uses autovectoring is presented in section 6.14, "interrupt bulk transfer example." the coding steps are summarized here. to employ ez-usb autovectoring: 1. insert a jump instruction at 0x43 to a table of jump instructions to the various usb interrupt service routines. table 9-3. a typical usb jump table table offset instruction 00 jmp sudav_isr 04 jmp sof_isr 08 jmp sutok_isr 0c jmp suspend_isr 10 jmp usbreset_isr 14 jmp ibn_isr (2122/2126 only, otherwise nop) 18 jmp ep0in _isr 1c jmp ep0out_isr 20 jmp in1buf_isr 24 jmp ep1out_isr 28 jmp ep2in_is 2c jmp ep2out_isr 30 jmp ep3in_is 34 jmp ep3out_isr 38 jmp ep4in_is 3c jmp ep4out_isr 40 jmp ep5in_is 44 jmp ep5out_isr 48 jmp ep6in_is 4c jmp ep6out_isr 50 jmp ep7in_is 54 jmp ep7out_isr 9.11 autovector coding
p a g e 9 - 1 2 c h a p t e r 9 . ez-u s b i n t e r r u pts e z -usb s e r i e s 2 1 0 0 t r m v 1.8 2 . code the jump t able with jump instructions to each individual usb i n ter r upt ser- vice routine . t h is tabl e h a s two impo r tan t r equ i rement s , ar i s in g fro m th e forma t of the a vec byte (zero-b a se d , with 2 l s bs set t o 0): ? i t must begin on a page boundary (address 0xnn00). ? the jump in s t ructions must be four byt e s apart. ? the interrupt service routi n es can be placed anywhere i n memory. ? w r i te initializa t ion code to enable the u s b interrupt (int2), a nd au t ovector- ing. f i g u r e 9 - 7 . t h e aut o ve c t o r m e c h a n i s m i n a c ti o n figur e 9-7 illu s t rates an is r t h a t serv i ces endpoint 2 - out. when endpoint 2-out r equ i res service, the e z - u sb core act i vates the usb int e rrupt reque s t, vectoring the 8051 to location 0x43. the jump ins t r uction at this location, which was o r iginally coded as lj m p 04 - 00 becom e s lj m p 04- 2c due to the e z -usb co r e sub s ti t utin g 2c a s the autovector byte for endpoint 2 -ou t (tabl e 9-3). the 8051 ju m ps to 042c, w he r e it exe- cutes the jump instruction to the endpoint 2-out isr shown in this exam p l e at address 0 1 19. o n ce th e 805 1 takes th e ve c tor a t 0043 , initiatio n o f t he endpo i nt-sp e c i fic is r takes only eight 805 1 cycle s . ep2out_isr: usb_jmp_table: ljmp 04 (00)2c 0043 0044 0045 2 c avec usb core ljmp ep2out_isr 01 19 042c 042d 042e 0400 0119 8051 usb interrupt vector
ez-usb series 2100 trm v1.8 chapter 9. ez-usb interrupts page 9-13 figure 9-8. i 2 c interrupt enable bits and registers chapter 4, "ez-usb input/output" describes the 8051 interface to the ez-usb i 2 c con- troller. the 8051 uses two registers, i2cs (i 2 c control and status) and i2dat (i 2 c data) to transfer data over the i 2 c bus. the ez-usb core signals completion of a byte transfer by setting the done bit (i2cs.0) high, which also sets an i 2 c interrupt request latch (figure 9-8). this interrupt request is routed to the 8051 int3 interrupt. the 8051 enables the i 2 c interrupt by setting eie.1=1. the 8051 determines the state of the interrupt request flag by reading exif.5, and resets the int3 interrupt request by writ- ing a zero to exif.5. any 8051 read or write to the i2dat or i2cs register automatically clears the i 2 c interrupt request. the ez-usb family responds to an in token from the host by loading an in endpoint buffer and then arming the endpoint by loading a byte count for the endpoint. after the host successfully receives the in data, the 8051 receives an ep-in interrupt, signifying that the in endpoint buffer is once again ready to accept data. 9.12 i 2 c interrupt 9.13 in bulk nak interrupt - (an2122/an2126 only) eie.1 exif.5(rd) exif.5(0) s r 8051 i 2 c interrupt (int3) i 2 c interrupt request done s r rd or wr i2dat register i2cs i2dat start stop lastrd id1 id0 berr ack d7 d6 d5 d4 d3 d2 d1 d0 done ez-usb 8051
p a g e 9 - 1 4 c h a p t e r 9 . ez-u s b i n t e r r u pts e z -usb s e r i e s 2 1 0 0 t r m v 1.8 in some situations, the host may s e nd in tokens b e f ore the 8051 has loaded and armed an i n endpoint. t o aler t the 8051 that an in endpoint is bein g pinged , the an2122/26 add a set of interrupt s , one pe r in endpoint, that indicate that an in endpoint just sent a nak to the host . th i s happens whe n the host s e nd s an in token and th e i n endpoin t doe s no t have data (yet) for the host. the new in t e r rupt i s c a lled ibn, for in bulk na k . its int2 autovector is 05, which was previously re s erved in the e z -usb f am i ly. the ibn interrupt reque s t s and enables a r e contr o lled b y two n e w r e g isters. n o te that bec a use the ibn interrupt e x ists only in the an2122/an2126, wh i ch has 6 bulk in end- points, there a r e ir q and ie n bits endpoin t s in0 through i n6. f i g u r e 9-9. in b ul k n a k i n t e r r upt r e q u e s t s r e g i s t e r f i g u r e 9 - 1 0 . in bu l k nak i n t e r r u pt e n a b l es r eg i ster e ac h of th e individu a l in endpoints ma y be enabled for an ibn interrup t u s in g th e ibnen r eg i s te r . the 8051 s ets an interr u p t enabl e bi t to 1 to enabl e th e corresponding interrupt . the i s r te s ts the ibnirq bits to determine which endpoint or e ndpoints gen e r ated the inte r rupt reque s t. as with all other ez-usb in t e rrupt requ e sts, the 8051 cle a rs an i b n ir q b it by writing a 1 to it. i b nirq in b u lk nak i n t e r r u pt r eque s ts 7 f b0 b7 b6 b5 b4 b3 b2 b1 b0 - ep6 i n ep5 i n ep4 i n ep3 i n ep2 i n ep1 i n ep0 i n r/w r/w r/w r/w r/w r/w r/w r/w x x x x x x x x i b nen in bulk n a k i n terrupt enables 7 f b1 b7 b6 b5 b4 b3 b2 b1 b0 - ep6 i n ep5 i n ep4 i n ep3 i n ep2 i n ep1 i n ep0 i n r/w r/w r/w r/w r/w r/w r/w r/w x 0 0 0 0 0 0 0
ez-u s b s er i e s 2 1 0 0 t rm v 1.8 c h a p t e r 9 . ez-u s b i n t e r r u pts p a g e 9 - 15 f i g u r e 9 - 1 1. i 2 c mod e re g is t e r the i 2 c interrupt includes one a d d itional i n terrup t s ource in the an2122/an2126, a 1-0 t r an s ition of t h e st o p bit. to enable this interrup t , se t t he sto p ie bit in t he i2cmode r eg i s te r . the 8051 det e rmi n es the in t errupt source by checking t h e don e and stop bits in the i2 c s registe r . f i g u re 9 - 12. i 2 c c o n t r o l a nd st a t u s r e g i s t e r f igu r e 9-13 . i 2 c da t a 9.14 i 2 c s t o p complet e inter r up t - (an2122/an212 6 o n l y ) i2c m ode i 2 c mode 7 f a7 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 s t opie 0 r r r r r r r/w r 0 0 0 0 0 0 0 0 i2cs i 2 c co n trol and s tatus 7 f a5 b7 b6 b5 b4 b3 b2 b1 b0 s t a r t s t op lastrd id1 id0 berr ack done r/w r/w r/w r r r r r 0 0 0 x x 0 0 0 i2d a t i 2 c dat 7 f a6 b7 b6 b5 b4 b3 b2 b1 b0 d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w x x x x x x x x
page 9-16 chapter 9. ez-usb interrupts ez-usb series 2100 trm v1.8 the two registers that the 8051 uses to control i 2 c transfers are shown above. in the ez- usb family, an i 2 c interrupt request occurs on int3 whenever the done bit (i2cs.0) makes a 0-to-1 transition. this interrupt signals the 8051 that the i 2 c controller is ready for another command. the 8051 concludes i 2 c transfers by setting the stop bit (i2cs.6). when the stop con- dition has been sent over the i 2 c bus, the i 2 c controller resets i2cs.6 to zero. during the time the i 2 c controller is generating the stop condition, it ignores accesses to the i2cs and i2dat registers. the 8051 code should therefore check the stop bit for zero before writing new data to i2cs or i2dat. in the ez-usb family, it does this by polling the i2cs.6 bit.
ez-usb series 2100 trm v1.8 chapter 10. ez-usb resets page 10-1 10 ez-usb resets the ez-usb chip has three resets: ? a power-on reset (por), which turns on the ez-usb chip in a known state. ? an 8051 reset, controlled by the ez-usb core. ? a usb bus reset, sent by the host to reset a device. this chapter describes the effects of these three resets. figure 10-1. ez-usb resets when power is first applied to the ez-usb chip, the external r-c circuit holds the ez- usb core in reset until the on-chip pll stabilizes. the clk24 pin is active as soon as power is applied. the 8051 may clear an ez-usb control bit, clk24oe, to inhibit the clk24 output pin for emi-sensitive applications that do not need this signal. external logic can force a chip reset by pulling the reset pin hi. the reset pin is normally 10.1 introduction 10.2 ez-usb power-on reset (por) reset res ez-usb core 8051 res cpucs.0 (1 at pw r on) oscillator xin xout pll 2 12 mhz clk24 24 mhz 48 mhz usb bus reset vcc
p a g e 1 0 -2 c h a p t e r 1 0 . ez-usb r e s e ts e z -usb s e r i e s 2 1 0 0 t r m v 1.8 connected t o vcc throug h a 1 m f ca p aci t o r an d to gnd through a 10-k r e si s to r (figure10- 1 ) . the o s ci l l a tor and pl l a r e una f fected by the state o f the r eset pin. the clk2 4 sign a l is a ctive whi l e re s e t = hi. wh e n re s e t retur n s lo, t h e activit y on the c l k24 pin depends on whether or not t h e ez-usb ch i p is in suspe n d s t ate . if in sus- pend, clk24 stops. resumpt i on of usb b u s activi t y or asser t i ng the wakeup# pin lo r e - s ta r ts th e clk2 4 s ignal. powe r -on d e fa u lt valu e s f o r al l ez-u s b re g ister bits are shown in chapter 12, " e z - usb regi s t e r s . " t a ble 10- 1 summariz e s r e set s t a t es t h a t a ffec t us b devic e operation . note that the te r m power- o n res e t r e f e rs to a reset ini t i a t ed by application o f power , or by as s ertion of the reset pin. * when the 8051 is released fro m r eset, th e e z -u s b automatica l ly arms the bulk out endpoints by setting the i r cs registers to 000000010b. t ab l e 10-1 . ez-u s b s t a t e s a f t e r p o w e r-on r e s e t ( p o r ) i t e m r e g i ster defau l t va l u e comment 1 e ndp o int data x x x x x xxx 2 b y t e c o u nts x x x x x xxx 3 c pucs r r rr 0 011 r r rr=r e v n u m b er, b1 = c l k 24oe, b0=8051res 4 p o r t co n f igs 0 0 000000 i o , n o t a l t e r n a t e fu n c t i ons 5 p o r t regi s ters x x x x x xxx 6 p o r t o es 0 0 000000 i n p uts 7 i n t err u p t enables 0 0 000000 di s a b l ed 8 i n t err u pt reqs 0 0 000000 cle a red 9 b ulk i n c / s 0 0 000000 b ulk i n end p oi n t s not b usy (unarmed) 10 b ulk o u t c / s* 0 0 000000 b ulk o u t end p oi n ts n ot b usy ( u narmed) 1 1 t ogg l e b its 0 0 000000 da t a t ogg l es = 0 12 u s b cs 0 0 000100 r e n u m= 0 , d isc o e=1 ( d i scon p i n drives) 13 f n a ddr 0 0 000000 u s b f un c t i on address 1 4 i n 0 7 v a l 0 1 0 1 0 1 1 1 e p 0 , 1 , 2 , 4 , 6 i n v a l i d 15 ou t 0 7 val 0 1 010101 e p0 , 2 , 4 , 6 o u t valid 16 i n i so v a l 0 0 0 0 0 1 11 e p8 , 9 , 10 i n v a l i d 17 out i so v a l 0 0 0 0 0 111 e p8 , 910o u t v a lid 18 u s b p a i r 0 x 000000 i sos e n d 0 (b7) = 0, no pairing 19 u s b b a v 0 0 000000 b reak c o n di t ion c l ear e d, no a utovector 20 c o n figu r ation 0 i n t e r nal e z -u s b cor e value 21 a l t e r n a te s e t ting 0 i n t e r nal e z -u s b core value
ez-usb series 2100 trm v1.8 chapter 10. ez-usb resets page 10-3 from table 10-1, at power-on: ? endpoint data buffers and byte counts are un-initialized (1,2). ? the 8051 is held in reset, and the clk24 pin is enabled (3). ? all port pins are configured as input ports (4-6). ? usb interrupts are disabled, and usb interrupt requests are cleared (7-8). ? bulk in and out endpoints are unarmed, and their stall bits are cleared (9). the ez-usb core will nak in or out tokens while the 8051 is reset. out end- points are enabled when the 8051 is released from reset. ? endpoint toggle bits are cleared (11). ? the renum bit is cleared. this means that the ez-usb core, and not the 8051, initially responds to usb device requests (12). ? the usb function address register is set to zero (13). ? the endpoint valid bits are set to match the endpoints used by the default usb device (14-17). ? endpoint pairing is disabled. also, isosend0=0, meaning that if an isochronous endpoint receives an in token without being loaded by the 8051 in the previous frame, the ez-usb core does not generate any response (18). ? the breakpoint condition is cleared, and autovectoring is turned off (19). ? configuration zero, alternate setting zero is in effect (20-21). the ez-usb register bit cpucs.0 resets the 8051. this bit is hi at power-on, initially holding the 8051 in reset. there are three ways to release the 8051 from reset: ? by the host, as the final step of a ram download. ? automatically, as part of an eeprom load. ? automatically, when external rom is used (ea=1). 10.3 releasing the 8051 reset
page 10-4 chapter 10. ez-usb resets ez-usb series 2100 trm v1.8 10.3.1 ram download once enumerated, the host can download code into the ez-usb ram using the firm- ware load vendor request (chapter 7, "ez-usb endpoint zero"). the last packet loaded writes 0 to the cpucs register, which clears the 8051 reset bit. 10.3.2 eeprom load chapter 5 describes the eeprom boot loads in detail. briefly, at power-on, the ez-usb core checks for the presence of an eeprom on its i 2 c bus. if found, it reads the first eeprom byte. if it reads 0xb2 as the first byte, the ez-usb core downloads 8051 code from the eeprom into internal ram. the last byte of a b2 load writes 0x00 to the cpucs register (at 0x7f92), which releases the 8051 from reset. 10.3.3 external rom ez-usb systems can use external program memory containing 8051 code and usb device descriptors, which include the vid/did/pid bytes. because these systems do no require and i 2 c eeprom to supply the vid/did/pid, the ez-usb core automatically releases 8051 reset when: 1. ea=1 (external code memory), and 2. no b0/b2 eeprom is detected on the i 2 c bus. the ez-usb core also sets the renum bit to 1, giving usb control to the 8051. once the 8051 is running, the usb host may reset the 8051 by downloading the value 0x01 to the cpucs register. the host might do this in preparation for loading code over- lays, effectively magnifying the size of the internal ez-usb ram. for such applications it is important to know the state of the ez-usb chip during and after an 8051 reset. in this note the other bit in the cpucs register, clk24oe, is writable only by the 8051, so the host writing a zero byte to this register does not turn off the clk24 signal. 10.4 8051 reset effects
ez-u s b s er i e s 2 1 0 0 t rm v 1.8 c h a p t e r 1 0 . ez-u s b r e s e ts p a g e 1 0-5 se c t ion, th i s par t icu l a r res e t is c alled an 805 1 r e set, an d shoul d no t b e confused wit h the por d e scribed i n section 10.2, "e z -usb pow e r -on r es e t ( p or ) ." this d i s cu s sion applies only to the condition whe r e t h e e z -usb chip is powered, and t h e 8051 is reset by the ho s t s etting the cpucs regis t e r to 0. the ba s i c usb device configura t ion rem a ins intact through an 8051 re s et. v a lid end- points remain valid, the usb function add r ess rem a ins the same, and t he i o p o rts retain thei r configu r ati o n s and values. stalled endpo i nts rem a in stalle d , and data t o g g les dont change. the only e f fects of an 8051 reset ar e as follows: ? usb interrupts a re disa b led, but pending interrupt reques t s remain pending. ? during the 8051 re s et, all bulk endpoin t s a re un a rmed, c a using t h e ez - u sb core to nak a nd i n or out t o k ens. ? af t er the 8051 r e set i s removed, the out bulk endpoin t s are automatically ar m ed. out endpoin t s are thus rea d y to accep t one out p acket before 8051 interven t ion is r equired. ? the breakpoint condi t i o n i s c l eared. the renum bit is n o t affected by an 8051 reset. when the 8051 comes out of r e set, t he pending i n t e rrupts are kept pending, but disabled (1). t h is giv e s the f i rmware w r iter the c h o i ce of acting on p r e - 8051-reset usb events, or igno r ing them by clearing the pending interrupt(s). du r ing the 8051 r e set t i m e, t h e e z-usb c o re holds o ff any u sb t r affic by n a king in and o u t tokens (2). the e z - usb core auto m a t i c ally arms the out endpoi n ts w h en the 8051 exi t s th e r eset state (3). usb b av.3, the b reakpoint b r eak b it, is c l e ared ( 4). the other bits in the u sbbav r eg i s ter are una f f e c ted. th e host s ign a l s a usb bus re s et by driving an se0 s tate (bot h d + and d- dat a l in e s low) for a minimum of 1 0 m s. t h e ez-usb core sen s es t h is c ondit i on, r equests the 8051 usb interrupt ( int2), and supp l i es t h e interrupt vecto r fo r a usb reset. a u s b r e set affects the e z -usb r e sources a s shown i n t a ble10-2. 10.5 usb bus r eset
p a g e 1 0 -6 c h a p t e r 1 0 . ez-usb r e s e ts e z -usb s e r i e s 2 1 0 0 t r m v 1.8 a u sb bu s r eset le a ves mo s t ez-usb resources unchanged . from table 1 0 - 2 , after usb bus r e s et: ? the ez - u s b cor e una r ms a l l bulk in endpoints (9). dat a loaded by the 8051 into an i n endpoin t buf f er remains there, and the 8051 fi r mware can either re-send it by loadin g the endpoin t byt e coun t r egister t o re-arm th e tra n s f e r , or sen d new data by r e - loading the in bu f fer before re-ar m ing the endp o int. ? bulk o u t endpoin t s retain th e i r bu s y states (10 ) . dat a s ent by the host t o an out endpoint bu f fe r r emains in the b u ff e r , and the 8051 fi r m w a re can either read the data o r re j ect it a s stale s imply b y n o t reading it. in e i t her case, the 8051 loads a dummy value to the endpoint byte count register t o r e -a r m o ut t ra n s fers. ? t oggle bi t s are cleared (11). ? the device addr e ss is r e s et to zero (13). t ab l e 10-2 . e z-us b s t at e s a f t e r a us b b u s r e s et i t e m reg i s t er de f a u l t v a l ue c o m m e n t 1 en d p t d ata uuuuuuu u u = unc h anged 2 b y t e co u nts uuuuuuuu 3 cp u cs uuuuuuuu 4 por t co n figs uuuuuuuu 5 p o r t regi s ters uuuuuuuu 6 p o r t o es uuuuuuuu 7 i n t err u p t enables uuuuuuuu 8 i n t err u p t reqs uuuuuuuu 9 bulk i n c / s 0000000 0 unarm 10 bulk o ut c / s uuuuuuu u re t a i n a r m e d/ u n a r m e d state 1 1 t oggle b its 00000000 12 us b cs uuuuuuu u renum bit u n changed 13 f n add 0000000 0 usb f u n c tion a ddress 14 i n0 7 v al uuuuuuuu 15 o u t 0 7 val uuuuuuuu 16 i n i s o v al uuuuuuuu 17 o u t i s o v al uuuuuuuu 18 us b p a i r uuuuuuuu 19 co n f i g ur a tion 0 2 0 a lt e r n a t e s e tt in g 0
ez-usb series 2100 trm v1.8 chapter 10. ez-usb resets page 10-7 note from item 12 that the renum bit is unchanged after a usb bus reset. therefore, if a device has renumerated ? and loaded a new personality, it retains the new personality through a usb bus reset. although not strictly a reset, when the ez-usb simulates a disc onnect-re connect in order to renumerate ? , there are effects on the ez-usb core: ? bulk in endpoints are unarmed, and bulk out endpoints are armed (9-10). ? endpoint stall bits are cleared (9-10). ? data toggles are reset (11). 10.6 ez-usb disconnect table 10-3. effects of an ez-usb disconnect and re-connect item register default value comment 1 endpt data uuuuuuuu u = unchanged 2 byte counts uuuuuuuu 3 cpucs uuuuuuuu 4 port configs uuuuuuuu 5 port registers uuuuuuuu 6 port oes uuuuuuuu 7 interrupt enables uuuuuuuu 8 interrupt reqs uuuuuuuu 9 bulk in c/s 00000000 unarm, clear stall bit 10 bulk out c/s 00000000 arm, clear stall bit 11 toggle bits 00000000 reset 12 usbcs uuuuuuuu renum bit unchanged 13 fnadd 00000000 usb function address 14 in07val uuuuuuuu 15 out07val uuuuuuuu 16 inisoval uuuuuuuu 17 outisoval uuuuuuuu 18 usbpair uuuuuuuu 19 configuration 0 20 alternate setting 0
p a g e 1 0 -8 c h a p t e r 1 0 . ez-usb r e s e ts e z -usb s e r i e s 2 1 0 0 t r m v 1.8 ? the function addre s s i s re s et t o zero ( 13). ? the confi g u ration i s r eset to zero (19). ? altern a te s ett i n g s are reset t o zero (20). t abl e 10-4 summarizes t h e effects of th e fou r ez - usb r e s ets. 10.7 r eset s u mmary t ab l e 1 0 - 4 . e f f e c t s o f v a r i o u s ez - u sb r e sets ( u mea n s u n a f f ected) res o urc r e s e t p in u s b b us reset d i s c onnect 8 0 51 r e set 8051 r eset reset u u n / a e p 0-7 i n e ps u n arm u n arm unarm u n arm e p 0-7 out e ps u n arm u a rm u n arm / arm b r eakpoint reset u u r eset s t all bits reset u re s et u i n t er r u p t e n a b les reset u u r eset i n t er r u p t reqs reset u u u cl k 24 run u u u da t a t o ggles reset reset re s et u f un c ti o n ad d ress reset reset re s et u co n figu r a t ion 0 0 0 u renum 0 u u u note the i 2 c controller is no t r e set for a n y of the c ondi t ions lai d out in table 10-4. only the e z -usb r e set pin r e set s it.
e z - u s b s e r i e s 2 1 0 0 t rm v 1 . 8 c h a p t e r 1 1 . e z - u s b p o w e r m a n a ge m e n t p a g e 1 1 - 1 1 1 e z- usb pow e r manag e m e n t the usb host c an suspend a device to put it in t o a power- d o wn mode. when the usb signals a su s pend o p e rat i on, the e z - u sb chip goes th r ough a sequence of steps to allow the 8051 t o first tu r n off ext e rnal power-consumi n g subsystems, and th e n enter an ul t ra-low-power mode by turni n g off i ts osc i llato r . once suspend e d, t h e ez-usb chip is awakened eithe r by resum p tion of usb bus acti v ity , or by a s serti o n o f it s wakeup# pin. this chapt e r describes th e suspend - resu m e mecha n i sm. f i g u r e 1 1 - 1 . s u s p en d - r e su m e c o ntrol figur e 1 1-1 illustrates th e ez-usb logic that i m p le m e n t s usb suspend and r e s ume. the s e ope r a t ions are explained in the next sections. 1 1 .1 i n t roduction pll oscillator div by 2 8051 48 mhz clk24 12 mhz start usb resume wakeup pin pcon.0 stop usb "suspend" interrupt no usb activity for 3 msec. resume int signal resume (usbcs.0) restart delay
page 11-2 chapter 11. ez-usb power management ez-usb series 2100 trm v1.8 figure 11-2. ez-usb suspend sequence a usb device recognizes suspend as 3 ms of a bus idle (j) state. the ez-usb core alerts the 8051 by asserting the usb (int2) interrupt and the suspend interrupt vector. this gives the 8051 code a chance to perform power suspend interrupt vector. this gives the 8051 code a chance to perform power conservation housekeeping before shut- ting down the oscillator. 11.2 suspend pll oscillator div by 2 8051 48 mhz clk24 12 mhz stop usb "suspend" interrupt no usb activity for 3 msec. int2 pcon.0
ez-usb series 2100 trm v1.8 chapter 11. ez-usb power management page 11-3 the 8051 code responds to the suspend interrupt by taking the following steps: 1. performs any necessary housekeeping such as shutting off external power-con- suming devices. 2. sets bit 0 of the pcon sfr (special function register). this has two effects: ? the 8051 enters its idle mode, which is exited by any interrupt. ? the 8051 sends an internal signal to the ez-usb core which causes it to turn off the oscillator and pll. these actions put the ez-usb chip into a low-power mode, as required by the usb spec- ification. figure 11-3. ez-usb resume sequence 11.3 resume pll oscillator div by 2 8051 48 mhz clk24 12 mhz start usb resume wakeup# pin resume int signal resume (usbcs.0) restart delay
p a g e 1 1 -4 c h a p t e r 1 1. ez- u s b p o w e r m a n a g ement e z -usb s e r i e s 2 1 0 0 t r m v 1.8 the ez-usb o s cilla t or r e -st a r ts when: usb bus a cti v it y r esum e s (shown as usb re s u me in figure 1 1-3), or external logic a s serts the e z -usb w akeup# pin l ow. a f t e r an o scill a tor stabil i z a tion t i m e, the e z - u s b core asserts the 8051 resume interrupt ( figur e 9-1). this causes the 8051 to exi t it s idle mo d e . the r e sum e int e r rupt is the high- est p r iority 8051 i n t e rrupt . it is alwa y s e n a b led, una f f e cted by th e ea bit. the r e sume isr c lears the i n t e rrupt requ e s t fla g , and execu t es a n r e t i (return from i n t er- rupt) in s truction. th i s c a uses the 8051 to c ontinue p rogram execution at the instruction following the one that s e t pcon . 0 to init i a te the suspend operation. f i g u r e 11- 4 . u s b co n t ro l a n d sta t u s r e g i s t e r t wo b i ts in t he u s b c s register are used f o r remote wake u p , w a k esrc and sigr- s ume. a f t e r exiting the i d le s t a te, th e 8051 reads t h e wa k esrc bit i n t he usbcs r e g ister to discover how the wakeup was ini t i a t ed. w ake s rc=1 indi c ates a s se r ti o n of the w a k e up# pin, a n d w a ke s rc=0 ind i c a tes a resump t ion of u s b bus ac t ivity. the 8051 cle a r s the w a kesrc bit by w r iting a 1 t o it. abo u t t h e res u m e i nterr u pt the 8051 enters the idle mode when pcon.0 i s set to 1. although the 8051 e x its its idle stat e w h en any interrup t occurs, the e z-usb l o g ic supports only the resume inter- rupt for the u s b resu m e operation. this is bec a use th e e z - usb co r e a s s erts this partic- ular interrupt after restarting t h e 8051 clock. 1 1.4 r emote w akeup usbcs usb cont r ol a n d s tat u s 7fd6 b7 b6 b5 b4 b3 b2 b1 b0 w a k e s r c - - - d i s c o n d i scoe renum sigrsume
e z - u s b s e r i e s 2 1 0 0 t rm v 1 . 8 c h a p t e r 1 1 . e z - u s b p o w e r m a n a ge m e n t p a g e 1 1 - 5 when a usb device is suspended, the hub d r i ve r is tri-stated, and the bus pullup and pull- dow n resi s tors ca u se th e bus t o assum e th e j, o r id l e state. a suspended devi c e signals a r e mote wakeup by a s s e rting t he k s tate for 10-15 ms. the 8051 contr o ls this using the s i g r s u m e bit in t h e us b c s regist e r. i f the 8051 f inds w akes r c=1 a fter ex i ting the idle mode, it drives t h e k state for 10- 15 ms to s ignal the us b remote wakeup . it does this by s e t ting s i g r s u m e=1, waiting 10-15 ms, an d then s e t t ing s i g r sume=0. when s igrsu m e = 0 , th e ez - usb bu s buffer r eve r ts to n o rmal op e r ation. t h e resume r o u ti n e should also w r ite a 1 to the w a k e src bit to clear it. the usb default device does not s uppo r t re m o te wakeup. t h is fa c t is reported at enu- me r a tion time in by t e 7 of the built-i n c onfigur a t i on desc r iptor (table 5-10). note if your d e sign does not u s e remote wak e up, tie t he wakeup# pin high. holding the w akeup# pin low inh i b i ts t h e ez - u sb ch i p from suspending. j and k s t a t es the u s b specifica t ion us e s differenti a l data signals d+ and d-. instead of defining a logical 1 a n d 0, it defines t h e j a nd k states . for a high speed d e vic e , the j s tate means (d+ > d-). r emote w akeup: the big picture addition a l f actors b esides th e ez-usb susp e nd-re s u me mec h a nism described in this s ect i o n d e termine whether r e mote wak e up is possible. these are: 1. the device m u st repo r t that it i s capabl e of signa l ing a rem o te wakeup in t h e bat- tributes f i e ld of its conf i guration d e scri p tor . s e e tabl e 5-10 f or an exa m ple of this de s c r ipto r . 2. the ho s t m u s t issue a set_feature/device reque s t with the f e atu r e s elect o r field s et to 0x01 to enable remote wakeup . s e e t abl e 7-6 fo r the d e tailed requ e st.
page 11-6 chapter 11. ez-usb power management ez-usb series 2100 trm v1.8
ez-usb series 2100 trm v1.8 chapter 12. ez-usb registers page 12-1 12 ez-usb registers this section describes the ez-usb registers in the order they appear in the ez-usb mem- ory map. the registers are named according to the follo wing conventions. most registers deal with endpoints. the general register format is dddnfff, where: ddd is endpoint direction, in or out with respect to the usb host. n is the endpoint number, where: ? 07 refers to endpoints 0-7 as a group. ? 0-7 refers to each individual bulk/interrupt/control endpoint. ? iso indicates isochr onous endpoints as a group. fff is the function, where: ? cs is a control and status register ? irq is an interrupt request bit ? ie is an interrupt enable bit ? bc, bcl, and bch are byte count registers. bc is used for single byte counts, and bcl/h are used as the low and high bytes of 16-bit byte c ounts. ? data is a single-register access to a fifo. ? buf is the start address of a buffer. examples: ? in7bc is the endpoint 7 in byte count. ? out07irq is the register containing interrupt request bits for out endpoints 0-7. ? inisoval contains valid bits for the isochronous in e ndpoints (ep8in-ep15 in). 12.1 introduction
page 12-2 chapter 12. ez-usb registers ez-usb series 2100 trm v1.8 figure 12-1. register description format figure 12-1 illustrates the register description format used in this chapter. ? the top line shows the register name, functional description, and address in the ez-usb memory. ? the second line shows the bit position in the register. ? the third line shows the name of each bit in the register. ? the fourth line shows 8051 accessibility: r(ead), w(rite), or r/w. ? the fifth line shows the default value. these values apply after a power-on-reset (por). other conventions usb indicates a global (not endpoint-specific) usb function. addr is an address. val means valid. frame is a frame count. ptr is an address pointer. register name register function address b7 b6 b5 b4 b3 b2 b1 b0 bitname bitname bitname bitname bitname bitname bitname bitname r, w access r, w access r, w access r, w access r, w access r, w access r, w access r, w access default val default val default val default val default val default val default val default val
ez-usb series 2100 trm v1.8 chapter 12. ez-usb registers page 12-3 * see table 12-1 for individual endpoint buffer addresses. figure 12-2. bulk data buffers sixteen 64-byte bulk data buffers appear at 0x1b40 and 0x7b40 in the 8k version of ez- usb, and only at 0x7b40 in the 32k version of ez-usb. the endpoints are ordered to permit the reuse of the buffer space as contiguous ram when the higher numbered end- points are not used. these registers default to unknown sta tes. 12.2 bulk data buffers innbuf,outnbuf endpoint 0-7 in/out data buffers 1b40-1f3f* b7 b6 b5 b4 b3 b2 b1 b0 d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w x x x x x x x x table 12-1. bulk endpoint buffer memory addresses address address name size 1f00-1f3f 7f00-7f3f in0buf 64 1ec0-1eff 7ec0-7eff out0buf 64 1e80-1ebf 7e80-7ebf in1buf 64 1e40-1e7f 7e40-7e7f out1buf 64 1e00-1e3f 7e00-7e3f in2buf 64 1dc0-1dff 7dc0-7dff out2buf 64 1d80-1dbf 7d80-7dbf in3buf 64 1d40-1d7f 7d40-7d7f out3buf 64 1d00-1d3f 7d00-7d3f in4buf 64 1cc0-1cff 7cc0-7cff out4buf 64 1c80-1cbf 7c80-7cbf in5buf 64 1c40-1c7f 7c40-7c7f out5buf 64 1c00-1c3f 7c00-7c3f in6buf 64 1bc0-1bff 7bc0-7bff out6buf 64 1b80-1bbf 7b80-7bbf in7buf 64 1b40-1b7f 7b40-7b7f out7buf 64
page 12-4 chapter 12. ez-usb registers ez-usb series 2100 trm v1.8 * see table 12-2 for individual endpoint buffer addresses. figure 12-3. isochronous data fifos 12.3 isochronous data fifos outndat ep8out-ep15out fifo registers 7f60-7f67* b7 b6 b5 b4 b3 b2 b1 b0 d7 d6 d5 d4 d3 d2 d1 d0 r r r r r r r r x x x x x x x x inndata ep8in-ep15in fifo registers 7f68-7f6f* b7 b6 b5 b4 b3 b2 b1 b0 d7 d6 d5 d4 d3 d2 d1 d0 w w w w w w w w x x x x x x x x table 12-2. isochronous endpoint fifo register addresses address isochronous data name 7f60 endpoint 8 out data out8data 7f61 endpoint 9 out data out9data 7f62 endpoint 10 out data out10data 7f63 endpoint 11 out dat out11data 7f64 endpoint 12 out data out12data 7f65 endpoint 13 out data out13data 7f66 endpoint 14 out data out14data 7f67 endpoint 15 out data out15data 7f68 endpoint 8 in data in8data 7f69 endpoint 9 in data in9data 7f6a endpoint 10 in data in10data 7f6b endpoint 11 in dat in11data 7f6c endpoint 12 in data in12data 7f6d endpoint 13 in data in13data 7f6e endpoint 14 in data in14data 7f6f endpoint 15 in data in15data
ez-usb series 2100 trm v1.8 chapter 12. ez-usb registers page 12-5 sixteen addressable data registers hold data from the eight isochronous in e ndpoints and the eight isochronous out endpoints. reading a data register reads a receive fifo byte (usb out data); writing a data register loads a transmit fifo byte (usb in data).
page 12-6 chapter 12. ez-usb registers ez-usb series 2100 trm v1.8 * see table 12-3 for individual endpoint buffer addresses. figure 12-4. isochronous byte count 12.4 isochronous byte counts outnbch out(8-15) byte count high 7f70-7f7f* b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 bc9 bc8 r r r r r r r r x x x x x x x x innbcl out(8-15) byte count low 7f70-7f7f* b7 b6 b5 b4 b3 b2 b1 b0 bc7 bc6 bc5 bc4 bc3 bc2 bc1 bc0 r r r r r r r r x x x x x x x x table 12-3. isochronous endpoint byte count register addresses address isochronous data name 7f70 endpoint 8 byte count high out8bch 7f71 endpoint 8 byte count low out8bcl 7f72 endpoint 9 byte count high out9bch 7f73 endpoint 9 byte count low out9bcl 7f74 endpoint 10 byte count high out10bch 7f75 endpoint 10 byte count low out10bcl 7f76 endpoint 11 byte count high out11bch 7f77 endpoint 11 byte c ount lo out11bcl 7f78 endpoint 12 byte count high out12bch 7f79 endpoint 12 byte count low out12bcl 7f7a endpoint 13 byte count high out13bch 7f7b endpoint 13 byte count low out13bcl 7f7c endpoint 14 byte count high out14bch 7f7d endpoint 14 byte count low out14bcl 7f7e endpoint 15 byte count high out15bch 7f7f endpoint 15 byte count low out15bcl
ez-u s b s er i e s 2 1 0 0 t rm v 1.8 c h a p t er 1 2 . ez- u s b r e g i s ters p a g e 1 2-7 the e z -usb co r e uses the byte count registers to report isochronous data payload sizes for ou t data transfer r e d fr o m the host to t h e u sb c ore . ten bits o f byte count data allow payload s izes up to 1,023 bytes. a byte c ount o f z e r o i s v a lid, me a ning that the host sent no isochronous data durin g the p r evious f r a me. the d e f ault values o f the s e registers are unknown. byte counts a re valid onl y f o r out e ndpoints. the byte counts i n d i cate the number of bytes r e m a ining in the endpoin t s rec e i v e fifo . eve r y t ime the 8051 rea d s a byte from the iso d a t a reg i st e r , the byte count decrements by one. t o read usb out dat a , the 8051 f ir s t reads byte c ount re g i st e rs o u tnbcl and outn- b c h to d e t ermine how many bytes to transfe r out of t h e out fifo. (the 8051 can also quickly te s t iso output endpoints fo r zero byte counts using the z b c ou t r eg i ster.) then, the cpu r e ads that number of bytes from t h e i s o d a t a regi s ter. sep a r a t e b y t e counts are maintained for each endpoint, so t he cpu c an read t he fifos in a discontinu- ous manne r . for ex a mpl e , if e p8 indica t es a byte count of 100 , a n d ep9 indicate s a byte count of 50, the cpu could read 50 by t es fr o m ep8, th e n rea d 1 0 by t es from ep9, and r e sume r eading e p8. at this moment the byte c o u nt f o r ep8 would read 50. there are no byte coun t registers fo r t h e in endpoin t s. t h e us b c or e auto m a tic a lly tracks the number of by t e s l o aded by the 8051. i f the 8051 does n o t load an in isochron o u s endpoint f ifo d u ring a 1 - m s f r a m e, and the host r equ e sts data f rom that endpoint during the next f r ame ( i n token), the u s b core r e sponds according to t h e setting o f the iso s end 0 b i t (usbpa i r . 7 ). if isosend0=1, the co r e r e turns a ze r o-l e ngth data packet in r esponse to t he host in tok e n . if isos- e nd=0, the core does not respond to t h e in token. i t is the res p o n sib i li t y of the 8051 p r og r ammer to ensure that the number of by t es written to the in fifo does not exceed the maximum packet s i z e as r epor t ed during e n u m eration.
page 12-8 chapter 12. ez-usb registers ez-usb series 2100 trm v1.8 figure 12-5. cpu control and status register this register enables the clk24 output and permits the host to reset the 8051 using a firmware download. bit 7-4: rv[3..0] silicon revision these register bits define the silicon revision. consult individual cypress semiconductor data sheets for values. bit 1: clk24oe output enable - clk24 pin when this bit is set to 1, the internal 24-mhz clock is connected to the ez-usb clk24 pin. when this bit is 0, the clk24 pin drives hi. this bit can be written by the 8051 only. bit 0: 8051res 8051 reset the usb host writes 1 to this bit to reset the 8051, and 0 to run the 8051. only the usb host can write this bit. 12.5 cpu registers cpucs cpu control and status 7f92 b7 b6 b5 b4 b3 b2 b1 b0 rv3 rv2 rv1 rv0 0 0 clk24oe 8051res r r r r r r r/w r rv3 rv2 rv1 rv0 0 0 1 1
ez-u s b s er i e s 2 1 0 0 t rm v 1.8 c h a p t er 1 2 . ez- u s b r e g i s ters p a g e 1 2-9 f i g u r e 1 2 -6. i o p ort c o n f i g u r a t i on r e gisters the s e th r e e r egi s te r s control the t h r e e io ports on th e e z -usb chip. they s e l ect between i o por t s and various alt e r nate functions. they are read/write by the 8051. when p o r tn c f g =0, the port pin functi o n s a s io, using the o u t, pins, and oe c o ntrol bits . data written to an o u tn r e gi s t ers appear s on an i o port pin if t he corresponding output enable bit (oen ) i s hi. when p o r tn c f g =1, the pin assumes the alternate f u n ction shown i n table 12-4 on the following page. 12.6 port con f iguration p o r t a c f g i o port a c o nfiguration 7f93 b7 b6 b5 b4 b3 b2 b1 b0 rxd 1 o u t rxd 0 o u t f r d fwr cs oe t1out t0out r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 p o r tb c f g io port b config u r a ti o n 7f94 b7 b6 b5 b4 b3 b2 b1 b0 t2out i n t 6 i n t 5 i n t 4 txd1 r x d 1 t2ex t2 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 p o r tc c f g i o port c c o nfiguration 7f95 b7 b6 b5 b4 b3 b2 b1 b0 rd wr t1 t0 i n t 1 i n t 0 txd0 r x d 0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
p a g e 1 2 - 1 0 c h a p t er 1 2 . ez- u s b r e g i s ters e z -usb s e r i e s 2 1 0 0 t r m v 1.8 t a b l e 1 2 -4 . io p in a l t e r n a t e f un c t ions i / o na m e a l ternate f unc t i o ns p a0 t 0out t i m er 0 ou t put p a1 t 1out t i m er 1 ou t put p a2 oe# e x t ernal m e mory o u t p u t enable p a3 c s # e x t ernal m e mory chip select p a4 f w r# f ast a c c es s w r i te s trobe p a5 f r d# f ast a c c es s re a d strobe p a6 r xd0out m o d e 0: u a r t 0 s y nch r on o us d a t a output p a7 r xd1out m o d e 0: u a r t 1 s y nch r on o us d a t a output p b0 t 2 t i m er / c o u n t er 2 cl o c k input p b1 t 2 e x t i m er / c o u n t er 2 c apt u re/r e load input p b 2 r xd1 s erial p or t 1 i nput p b3 t xd1 m o d e 0: cl o ck o utput m odes 1 - 3 : seri a l p o rt 1 d ata o utput p b4 i n t 4 i n t 4 i n t e r ru p t r e quest p b5 i n t 5 # i n t 5 i n t e r ru p t r e quest p b6 i n t 6 i n t 6 i n t e r ru p t r e quest p b7 t 2out t i m er / c o u n t er 2 ov e rfl o w ind i cation p c0 r xd0 s erial p or t 0 i nput pc1 t xd0 m o d e 0: cl o ck o utput m odes 1 - 3 : seri a l p o rt 0 d ata o utput pc2 i n t 0 # i n t 0 i n t e r ru p t r e quest pc3 i n t 1 # i n t 1 i n t e r ru p t r e quest pc4 t 0 t i m er / c o u n t er 0 e x t e r n al input pc5 t 1 t i m er / c o u n t er 1 e x t e r n al input pc6 wr# e x t ernal m e mor y wr i te s t robe pc7 rd# e x t ernal m e mor y re a d strobe
ez-usb series 2100 trm v1.8 chapter 12. ez-usb registers page 12-11 figure 12-7. output port configuration registers the outn registers provide the data that drives the port pin when oe=1 and the port- ncfg pin is 0. if the port pin is selected a an i nput (oe=0), the value st ored in the corre- sponding outn bit is stored in an output latch but not used. 12.7 input-output port registers out port a outputs 7f96 b7 b6 b5 b4 b3 b2 b1 b0 outa7 outa6 outa5 outa4 outa3 outa2 outa1 outa0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 outb port b outputs 7f97 b7 b6 b5 b4 b3 b2 b1 b0 outb7 outb6 outb5 outb4 outb3 outb2 outb1 outb0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 outc port c outputs 7f98 b7 b6 b5 b4 b3 b2 b1 b0 outc7 outc6 outc5 outc4 outc3 outc2 outc1 outc0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
page 12-12 chapter 12. ez-usb registers ez-usb series 2100 trm v1.8 figure 12-8. pinsn registers the pinsn registers contain the current value of the port pins, whether they are selected as io ports or alternate functions. pinsa port a pins 7f99 b7 b6 b5 b4 b3 b2 b1 b0 pina7 pina6 pina5 pina4 pina3 pina2 pina1 pina0 r r r r r r r r x x x x x x x x pinsb port b pins 7f9a b7 b6 b5 b4 b3 b2 b1 b0 pinb7 pinb6 pinb5 pinb4 pinb3 pinb2 pinb1 pinb0 r r r r r r r r x x x x x x x x outc port c pins 7f98 b7 b6 b5 b4 b3 b2 b1 b0 pinc7 pinc6 pinc5 pinc4 pinc3 pinc2 pinc1 pinc0 r r r r r r r r x x x x x x x x
ez-usb series 2100 trm v1.8 chapter 12. ez-usb registers page 12-13 figure 12-9. output enable registers the oe registers control the output enables on the tri-state drivers connected to the port pins. when these bits are 1, the port is an output, unless the corresponding portncfg bit is set to a 1. oea port a output enable 7f9c b7 b6 b5 b4 b3 b2 b1 b0 oea7 oea6 oea5 oea4 oea3 oea2 oea1 oea0 r/w r/w r/w r/w r/w r/w r/w r/w x x x x x x x x oeb port b output enable 7f9d b7 b6 b5 b4 b3 b2 b1 b0 oeb7 oeb6 oeb5 oeb4 oeb3 oeb2 oeb1 oeb0 r/w r/w r/w r/w r/w r/w r/w r/w x x x x x x x x oec port c output enable 7f9e b7 b6 b5 b4 b3 b2 b1 b0 oec7 oec6 oec5 oec4 oec3 oec2 oec1 oec0 r/w r/w r/w r/w r/w r/w r/w r/w x x x x x x x x
p a g e 1 2 - 1 4 c h a p t er 1 2 . ez- u s b r e g i s ters e z -usb s e r i e s 2 1 0 0 t r m v 1.8 f i g u r e 12-1 0 . 2 30-k b a u d u art o p e r at i o n re g i s t e r bit 1: u a r t1 univ e rsal 115/ 2 3 0 kbaud operat i o n f or uart1 bit 0: u a r t0 univ e rsal 115/ 2 3 0 kbaud operat i o n f or uart0 the s e b i t s , when set to 1, c onn e c t a n i n t e r n a l 3 . 6 9- m h z clock t o u art0 and/or u a rt1. the u a r ts divide th i s f requency by 16, giving a 230 - khz baud clo c k if the cor r espondin g smo d bit is set , o r 11 5 baud cloc k i f th e c orresponding smod bit i s clear . ( n o te: sm o d 0 is bit 7 or sfr 0x87, smod1 is b i t 7 or s f r 0xd8 ) . whe n the uart0 o r u a rt1 b i t i s clear, the no r m al uart clock sour c es are used. f i g u r e 1 2 - 1 1. i s o c h r on o us o u t e n d p o i n t e r r o r r e g ister the isoerr bi t s are u p d ated at eve r y s o f. they i n d i c ate that a crc err o r w a s received on a data packet for the c u rr e n t frame. t he i s o err bit statu s r e f ers to the usb data r e ceived in th e previous f r a m e , an d which is cur r ently in the endpoi n t s o u t fifo. if the i soerr b i t = 1, indicatin g a bad c rc check, t h e data i s s til l availabl e in th e o utndata r eg i s te r . 12.8 230-kbaud ua r t operatio n - a n 2122, a n2126 u a r t230 230-kbaud u a rt co n trol 7f9f b7 b6 b5 b4 b3 b2 b1 b0 - - - - - - u a rt1 u a rt0 r r r r r r r/w r/w 0 0 0 0 0 0 0 0 12.9 isochronous control/status registers i s o err isochronous o u t e p er r o r 7 f a0 b7 b6 b5 b4 b3 b2 b1 b0 i s o 1 5err i s o 1 4err i s o 1 3err i s o 1 2err i s o 1 1 e r r i s o 1 0err iso 9 e r r iso 8 e r r r r r r r r r r x x x x x x x x
ez-usb series 2100 trm v1.8 chapter 12. ez-usb registers page 12-15 figure 12-12. isochronous control register bit 3: ppstat ping-pong status this bit indicates the isochronous buffer currently in use by the ez-usb core. it is used only for diagnostic purposes. bits 2,1: mbz must be zero these bits must always be written with zeros. bit 0: isodisab iso endpoints disable isodisab=0 enables all 16 isochronous endpoints isodisab=1 disables all 16 isochronous endpoints, making the 2,048 bytes of isochro- nous fifo memory available as 8051 data memory at 0x2000-0x27ff. figure 12-13. zero byte count register bits 0-7: ep(n) zero byte count for iso out endpoints the 8051 can check these bits as a fast way to check all of the out isochr onous endpoints at once for no data received during the previous frame. a 1 in any bit position means that a zero byte isochronous out packet was received for the indicated endpoint. isoctl isochronous control 7fa1 b7 b6 b5 b4 b3 b2 b1 b0 - - - - ppstat mbz mbz isodisab r r r r r r/w r/w r/w 0 0 0 0 0 0 0 0 zbcout zero byte count bits 7fa2 b7 b6 b5 b4 b3 b2 b1 b0 ep15 ep14 ep13 ep12 ep11 ep10 ep9 ep8 r r r r r r r r x x x x x x x x
page 12-16 chapter 12. ez-usb registers ez-usb series 2100 trm v1.8 figure 12-14. i 2 c transfer registers the 8051 uses these registers to transfer data over the ez-usb i 2 c bus. bit 7: start signal start condition the 8051 sets the start bit to 1 to prepare an i 2 c bus transfer. if start=1, the next 8051 load to i2dat will generate the start condition followed by the serialized byte of data in i2dat. the 8051 loads byte data into i2dat after setting the start bit. the i 2 c controller clears the start bit during the ack interval. bit 6: stop signal stop condition the 8051 sets stop=1 to terminate an i 2 c bus transfer. the i 2 c controller clears the stop bit after completing the stop condition. if the 8051 sets the stop bit during a byte transfer, the stop condition will be generated immediately following the ack phase of the byte transfer. if no byte transfer is occurring when the stop bit is set, the stop condition will be carried out immediately on the bus. data should not be written to i2cs or i2dat until the stop bit returns low. 12.10 i 2 c registers i2cs i 2 c control and status 7fa5 b7 b6 b5 b4 b3 b2 b1 b0 start stop lastrd id1 id0 berr ack done r/w r/w r/w r r r r r 0 0 0 x x 0 0 0 i2dat i 2 c data 7fa6 b7 b6 b5 b4 b3 b2 b1 b0 d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w x x x x x x x x
ez-usb series 2100 trm v1.8 chapter 12. ez-usb registers page 12-17 bit 5: lastrd last data read to read data over the i 2 c bus, an i 2 c master floats the sda line and issues clock pulses on the scl line. after every eight bits, the master drives sda low for one clock to indicate ack. to signal the last byte of the read transfer, the master floats sda at ack time to instruct the slave to stop sending. this is controlled by the 8051 by setting la strd=1 before reading the last byte of a read transfer. the i 2 c controller clears the lastrd bit at the end of the transfer (at ack time). bit 4-3: id1,id0 boot eeprom id these bits are set by the boot loader to indicate whether an 8-bit address or 16-bit address eeprom at slave address 000 or 001 was detected at power -on. normally, they are used for debug purposes only. bit 2: berr bus error this bit indicates an i 2 c bus error. berr=1 indicates that there was bus contention, which results when an outside device drives the bus lo when it s houl dnt, or when another bus master wins arbitration, taking control of the bus. berr is cleared when 8051 reads or writes the idata register. bit 1: ack acknowledge bit every ninth scl or a write transfer the slave indicates reception of the byte by asserting ack. the ez-usb controller floats sda during this time, samples the sda line, and updates the ack bit with the complement of the detected value. ack=1 indicates acknowledge, and ack=0 indicates not-acknowledge. the ez-usb core updates the ack bit at the same time it sets done=1. the ack bit s hould be ignored for read trans- fers on the bus. note setting lastrd does not automatically generate a stop condition. the 8051 should also set the stop bit at the end of a read transfer.
p a g e 1 2 - 1 8 c h a p t er 1 2 . ez- u s b r e g i s ters e z -usb s e r i e s 2 1 0 0 t r m v 1.8 bit 0: done i 2 c t ran s fer done the i 2 c controll e r s e t s this bit whenever it comp l etes a by t e t r an s fer, right after the ack stage. the controll e r also genera t es an i 2 c interrupt r equ e st (8051 int3 ) when i t sets the done bit. the i 2 c controller auto m a t i cally cle a rs the done bit and the i 2 c interrupt r equest b i t whenever the 8051 r eads o r w r it e s the i 2 d at regist e r. f i g u r e 12-1 5 . i 2 c m o d e re g i s t e r the i 2 c interrupt includes one a d d itional i n terrup t s ource in the an2122/an2126, a 1-0 t r an s ition of t h e st o p bit. to enable this interrup t , se t t he sto p ie bit in t he i2cmode r eg i s te r . the 8051 det e rmi n es the in t errupt source by checking t h e do n e and stop bits in the i2 c s registe r . i2c m o d e i 2 c mode 7 f a7 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 s t opie 0 r r r r r r r/w r 0 0 0 0 0 0 0 0
ez-u s b s er i e s 2 1 0 0 t rm v 1.8 c h a p t er 1 2 . ez- u s b r e g i s ters p a g e 1 2 - 19 fi g u r e 1 2 - 1 6 . i nt e r r up t v e c t o r r e g i s t e r i vec ind i c ates the source o f an interrup t from th e u sb core. when the usb core g e ner- ates an i nt2 (usb) interrup t request, it update s ivec to indicate the source of the inter- rupt. the interrupt sources are encoded on iv[4..0] as shown in figu r e 9-2. 12. 1 1 i n t e rrupts iv e c i n t e r rup t v e ctor 7 f a8 b7 b6 b5 b4 b3 b2 b1 b0 0 iv4 iv3 iv2 iv1 iv0 0 0 r r r r r r r r 0 0 0 0 0 0 0 0
page 12-20 chapter 12. ez-usb registers ez-usb series 2100 trm v1.8 figure 12-17. in/out interrupt request (irq) register these interrupt request (irq) registers indicate the pending interrupts for each bulk end- point. an interrupt request (ir) bit becomes active when the bsy bit for an endpoint makes a transition from one to zero (the endpoint becomes un-busy , giving access to the 8051). the ir bits function independently of the interrupt enable (ie) bits, so interrupt requests are held whether or not the interrupts are enabled. the 8051 clears an interrupt request bit by writing a 1 to it (see the following note). in07irq endpoint 0-7 in interrupt request 7fa9 b7 b6 b5 b4 b3 b2 b1 b0 in7ir in6ir in5ir in4ir in3ir in2ir in1ir in0ir r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 out07irq endpoint 0-7 out interrupt requests 7faa b7 b6 b5 b4 b3 b2 b1 b0 out7ir out6ir out5ir out4ir out3ir out2ir out1ir out0ir r/w r/w r/w r/w r/w r/w r/w r/w x x x x x x x x note do not clear an irq bit by reading an irq register, oring its contents with a bit mask, and writing back the irq register. this will clear all pending interrupts. instead, sim- ply write the bit mask value (with the irq you want to clear) directly to the irq register.
ez-usb series 2100 trm v1.8 chapter 12. ez-usb registers page 12-21 * an2122/an2126 only. figure 12-18. usb interrupt request (irq) registers usbirq indicates the interrupt request status of the usb reset, suspend, setup token, start of frame, and setup data available interrupts. bit 5: ibnir in bulk nak interrupt request this bit is in the an2122 and an2126 versions only. the ez-usb core sets this bit when any of the in bulk endpoints responds to an in token with a nak. this interrupt occurs when the host sends an in token to a bulk in endpoint which has not been armed by the 8051 writing its byte count register. individual enables and requests (per e ndpoint) are controlled by the ibnirq and ibnien registers (7fb0, 7fb1). bit 4: uresir usb reset interrupt request the ez-usb core sets this bit to 1 when it detects a usb bus reset. because this bit can change state while the 8051 is in reset, it may be active when the 8051 comes out of reset, although it is reset to 0 by a power-on reset. write a 1 to this bit to clear the interrupt request. see chapter 10, "ez-usb resets" for more information about this bit. bit 3: suspir usb suspend interrupt request the ez-usb core sets this bit to 1 when it detects usb suspend signaling (no bus activity for 3 ms). write a 1 to this bit to clear the interrupt request. because this bit can change state while the 8051 is in reset, it may be active when the 8051 comes out of reset, alt hough it is reset to 0 by a power-on reset. see chapter 11, "ez- usb power management" for more information about this bit. usbirq usb interrupt request 7fab b7 b6 b5 b4 b3 b2 b1 b0 - - ibnir* uresir suspir sutokir sofir sudavir r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
page 12-22 chapter 12. ez-usb registers ez-usb series 2100 trm v1.8 bit 2: sutokir setup token interrupt request the ez-usb core sets this bit to 1 when it receives a setup token. write a 1 to this bit to clear the interrupt request. see chapter 7, "ez-usb endpoint zero" for more infor- mation on the handling of setup tokens. because this bit can change state while the 8051 is in reset, it may be active when the 8051 comes out of reset, alt hough it is reset to 0 by a power-on reset. bit 1: sofir start of frame interrupt request the ez-usb core sets this bit to 1 when it receives a sof packet. write a 1 to this bit to clear the interrupt condition. because this bit can change state while the 8051 is in reset, it may be active when the 8051 comes out of reset, alt hough it is reset to 0 by a power-on reset. bit 0: sudavir setup data available interrupt request the ez-usb core sets this bit to 1 when it has transferred the eight data bytes from an endpoint zero setup packet into internal registers (at setupdat). write a 1 to this bit to clear the interrupt condition. because this bit can change state while the 8051 is in reset, it may be active when the 8051 comes out of reset, alt hough it is reset to 0 by a power-on reset.
ez-usb series 2100 trm v1.8 chapter 12. ez-usb registers page 12-23 figure 12-19. in/out interrupt enable registers the endpoint interrupt enable registers define which endpoints have active interrupts. they do not affect the endpoint action, only the generation of an interrupt in response to endpoint events. when the ien bit for an endpoint is 0, the interrupt request bit for that endpoint is ignored, but saved. when the ien bit for an endpoint is 1, any irq bit equal to 1 gen- erates an 8051 int2 request. in07en endpoint 0-7 in interrupt enables 7fac b7 b6 b5 b4 b3 b2 b1 b0 in7ien in6ien in5ien in4ien in3ien in2ien in1ien in0ien r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 out07ien endpoint 0-7 out interrupt enables 7fad b7 b6 b5 b4 b3 b2 b1 b0 out7ien out6ien out5ien out4ien out3ien out2ien out1ien out0ien r/w r/w r/w r/w r/w r/w r/w r/w x x x x x x x x note the int2 interrupt (eie.0) and the 8051 global interrupt enable (ea) must be enabled for the endpoint interrupts to propagate to the 8051. once the int2 interrupt is active, it must be cleared by software.
page 12-24 chapter 12. ez-usb registers ez-usb series 2100 trm v1.8 * an2122/an2126 only. figure 12-20. usb interrupt enable registers usbien bits gate the interrupt request to the 8051 for usb reset, suspend, setup token, start of frame, and setup data available. bit 5: ibnie in bulk nak interrupt enable this bit is in the an2122 and an2126 versions only. the 8051 sets this bit to enable the in-bulk-nak interrupt. this interrupt occurs when the host sends an in token to a bulk in endpoint which has not been armed by the 8051 writing its byte count register. indi- vidual enables and requests (per endpoint) are controlled by the ibnirq and ibnien reg- isters (7fb0, 7fb1). bit 4: uresie usb reset interrupt enable this bit is the interrupt mask for the uresir bit. when this bit is 1, the interrupt is enabled, when it is 0, the interrupt is disabled. bit 3: suspie usb suspend interrupt enable this bit is the interrupt mask for the suspir bit. when this bit is 1, the interrupt is enabled, when it is 0, the interrupt is disabled. bit 2: sutokie setup token interrupt enable this bit is the interrupt mask for the sutokir bit. when this bit is 1, the interrupt is enabled, when it is 0, the interrupt is disabled. usbien usb interrupt enables 7fae b7 b6 b5 b4 b3 b2 b1 b0 - - ibnie* uresie suspie sutokie sofie sudavie r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
ez-usb series 2100 trm v1.8 chapter 12. ez-usb registers page 12-25 bit 1: sofie start of frame interrupt enable this bit is the interrupt mask for the sofie bit. when this bit is 1, the interrupt is enabled, when it is 0, the interrupt is disabled. bit 0: sudavie setup data available interrupt enable this bit is the interrupt mask for the sudavie bit. when this bit is 1, the interrupt is enabled, when it is 0, the interrupt is disabled.
page 12-26 chapter 12. ez-usb registers ez-usb series 2100 trm v1.8 figure 12-21. breakpoint and autovector register bit 3: break breakpoint enable the break bit is set when the 8051 a ddress bus matches the address held in the bit breakpoint address registers (next page). the bkpt pin reflects the state of this bit. the 8051 writes a 1 to the break bit to clear it. it is not necessary to clear the break bit if the pulse mode bit (bppulse) is set. bit 2: bppulse breakpoint pulse mode the 8051 sets this bit to 1 to pulse the break bit (and bkpt pin) high for 8 clk24 cycles when the 8051 address bus matches the address held in the breakpoint address reg- isters. when this bit is set to 0, the break bit (and bkpt pin) remains high until it is cleared by the 8051. bit 1: bpen breakpoint enable if this bit is 1, a break signal is generated whenever the 16-bit address lines match the value in the breakpoint address registers (bpaddrh/l). the behavior of the break bit and associated bkpt pin signal is either latched or pulsed, depending on the state of the bppulse bit. bit 0: aven auto-vector enable if this bit is 1, the ez-usb auto-vector feature is enabled. if it is 0, the auto-vector fea- ture is disabled. see chapter 9, "ez-usb interrupts" for more information on the auto- vector feature. usbbav breakpoint and autovector 7faf b7 b6 b5 b4 b3 b2 b1 b0 - - - - break bppulse bpen av e n r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
ez-usb series 2100 trm v1.8 chapter 12. ez-usb registers page 12-27 * an2122/an2126 only. figure 12-22. in bulk nak interrupt request register these bits are set when a bulk in endpoint (0-6) received an in token while the endpoint was not armed for data transfer. in this case the sie automatically sends a nak response, and sets the corresponding ibnirq bit. if the ibn interrupt is enabled (usbien.5=1), and the endpoint interrupt is enabled in the ibnien register, an interrupt is request gener- ated. the 8051 can test the ibnirq register to determine which of the endpoints caused the interrupt. the 8051 clears an ibnirq bit by writing a 1 to it. figure 12-23. in bulk nak interrupt enable register each of the individual in endpoints may be enabled for an ibn interrupt using the ibnen register. the 8051 sets an interrupt enable bit to 1 to enable the corresponding interrupt. ibnirq in bulk nak interrupt requests 7fb0 b7 b6 b5 b4 b3 b2 b1 b0 - ep6in ep5in ep4in ep3in ep2in ep1in ep0in r/w r/w r/w r/w r/w r/w r/w r/w x x x x x x x x ibnien in bulk nak interrupt enables 7fb1 b7 b6 b5 b4 b3 b2 b1 b0 - ep6in ep5in ep4in ep3in ep2in ep1in ep0in r/w r/w r/w r/w r/w r/w r/w r/w x x 0 0 0 0 0 0
page 12-28 chapter 12. ez-usb registers ez-usb series 2100 trm v1.8 figure 12-24. in/out interrupt enable registers when the current 16-bit address (code or xdata) matches the bpaddrh/bpaddrl address, a breakpoint event occurs. the bppulse and bpen bits in the usbbav regis- ter control the action taken on a breakpoint event. if the bpen bit is 0, address breakpoints are ignored. if bpen is 1 and bppulse is 1, an 8 clk24 wide pulse appears on the bkpt pin. if bpen is 1 and bppulse is 0, the bkpt pin remains active until the 8051 clears the break bit by writing 1 to it. bpaddrh breakpoint address high 7fb2 b7 b6 b5 b4 b3 b2 b1 b0 a15 a14 a13 a12 a11 a10 a9 a8 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 bpaddrl breakpoint address low 7fb3 b7 b6 b5 b4 b3 b2 b1 b0 a7 a6 a5 a4 a3 a2 a1 a0 r/w r/w r/w r/w r/w r/w r/w r/w x x x x x x x x
ez-usb series 2100 trm v1.8 chapter 12. ez-usb registers page 12-29 figure 12-25. port configuration registers these registers control ez-usb control endpoint zero. because endpoint zero is a bi- directional endpoint, the in and out functionality is controlled by a single control and status (cs) register, unlike endpoints 1-7, which have separate incs and outcs regis- ters. bit 3: outbsy out endpoint busy outbsy is a read-only bit that is automatically cleared when a setup token arrives. the 8051 sets the outbsy bit by writing a byte count to epoutbc. 12.12 endpoint 0 control and status registers ep0cs endpoint zero control and status 7fb4 b7 b6 b5 b4 b3 b2 b1 b0 - - - - outbsy inbsy hsnak ep0stall r r r r r r r/w r/w 0 0 0 0 1 0 0 0 in0bc endpoint zero in byte count 7fb5 b7 b6 b5 b4 b3 b2 b1 b0 - bc6 bc5 bc4 bc3 bc2 bc1 bc0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 out0bc endpoint zero out byte count 7fc5 b7 b6 b5 b4 b3 b2 b1 b0 - bc6 bc5 bc4 bc3 bc2 bc1 bc0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
page 12-30 chapter 12. ez-usb registers ez-usb series 2100 trm v1.8 if the control transfer uses an out data phase, the 8051 must load a dummy byte count into out0bc to arm the out endpoint buffer. until it does, the ez-usb core will nak the out tokens. bit 2: inbsy in endpoint busy inbsy is a read-only bit that is automatically cleared when a setup token arrives. the 8051 sets the inbsy bit by writing a byte count to in0bc. if the control transfer uses an in data phase, the 8051 loads the requested data into the in0buf buffer, and then loads the byte count into in0bc to arm the data phase of the control transfer. alternatively, the 8051 can arm the data transfer by loading an address into the setup data pointer registers sudptrh/l. until armed, the ez-usb core will nak the in tokens. bit 1: hsnak handshake nak hsnak (handshake nak) is a read/write bit that is automatically set when a setup token arrives. the 8051 clears hsnak by writing a 1 to the register bit. while hsnak=1, the ez-usb core naks the handshake (status) phase of the con- trol transfer. when hsnak=0, it acks the handshake phase. the 8051 can clear hsnak at any time during a control transfer. bit 0: ep0stall endpoint zero stall ep0stall is a read/write bit that is automatically cleared when a setup token arrives. the 8051 sets ep0stall by writing a 1 to the register bit. while ep0stall=1, the ez-usb core sends the stall pid for any in or out token. this can occur in either the data or handshake phase of the control transfer. note to indicate an endpoint stall on endpoint zero, set both ep0stall and hsnak bits. setting the ep0stall bit alone causes endpoint zero to nak forever because the host keeps the control transfer pending.
ez-u s b s er i e s 2 1 0 0 t rm v 1.8 c h a p t er 1 2 . ez- u s b r e g i s ters p a g e 1 2 - 31 endpoints 1-7 in and out are used for bul k or interrupt data . t a ble 12-5 shows the addres s es for the control/status a n d b y te c ount r e g i s t e r s a s s o c i a t ed with these endpoints. the bi-directional control endpoint zero registers a re described in section 12.12, "endpoint 0 control and status regi s ters." 12.1 3 e ndpoint 1-7 control and s tatus regi s ters t a b l e 1 2 -5. c o n t r o l a n d s t at u s re g i s t e r a dd r esses for e n d p o int s 0-7 a d dress f u n c t ion na m e 7 f b4 co n t rol a n d s t a t u s - e n d point in0 e p 0cs 7 f b5 by t e co u nt - e n d p o int in0 i n 0bc 7 f b6 co n t rol a n d s t a t u s - e n d point in1 i n 1cs 7 f b7 by t e co u nt - e n d p o int in1 i n 1bc 7 f b8 co n t rol a n d s t a t u s - e n d point in2 i n 2cs 7 f b9 by t e co u nt - e n d p o int in2 i n 2bc 7 f ba co n t rol a n d s t a t u s - e n d point in3 i n 3cs 7 f bb by t e co u nt - e n d p o int in3 i n 3bc 7 f b c co n t rol a n d s t a t u s - e n d point in4 i n 4cs 7 f b d by t e co u nt - e n d p o int in4 i n 4bc 7 f be co n t rol a n d s t a t u s - e n d point in5 i n 5cs 7 f bf by t e co u nt - e n d p o int in5 i n 5bc 7 f c0 co n t rol a n d s t a t u s - e n d point in6 i n 6cs 7 f c1 by t e co u nt - e n d p o int in6 i n 6bc 7 f c2 co n t rol a n d s t a t u s - e n d point in7 i n 7cs 7 f c3 by t e co u nt - e n d p o int in7 i n 7bc 7fc4 reser v ed 7 f c5 by t e co u nt - e n d p o i n t out0 ou t 0bc 7 f c6 co n t rol a n d s t a t u s - e n dp o int out1 ou t 1cs 7 f c7 by t e co u nt - e n d p o i n t out1 ou t 1bc 7 f c8 co n t rol a n d s t a t u s - e n dp o int out2 ou t 2cs 7 f c9 by t e co u nt - e n d p o i n t out2 ou t 2bc 7 f ca co n t rol a n d s t a t u s - e n dp o int out3 ou37cs 7 f cb by t e co u nt - e n d p o i n t out3 ou t 3bc 7 f cc co n t rol a n d s t a t u s - e n dp o int out4 ou t 4cs 7 f cd by t e co u nt - e n d p o i n t out4 ou t 4bc 7 f ce co n t rol a n d s t a t u s - e n dp o int out5 ou t 5cs 7 f cf by t e co u nt - e n d p o i n t out5 ou t 5bc 7 f d0 co n t rol a n d s t a t u s - e n dp o int out6 ou t 6cs 7 f d1 by t e co u nt - e n d p o i n t out6 ou t 6bc 7 f d2 co n t rol a n d s t a t u s - e n dp o int out7 ou t 7cs 7 f d3 by t e co u nt - e n d p o i n t out7 ou t 7bc
page 12-32 chapter 12. ez-usb registers ez-usb series 2100 trm v1.8 * see table 12-5 for individual control/status register addresses. figure 12-26. in control and status register bit 1: innbsy in endpoint (1-7) busy the bsy bit indicates the status of the endpoints in buffer innbuf. the ez-usb core sets bsy=0 when the endpoints in buffer is empty and ready for loading by the 8051. the 8051 sets bsy=1 by loading the endpoints byte count register. when bsy=1, the 8051 should not write data to an in endpoint buffer, because the end- point fifo could be in the act of transferring data to the host over the usb. bsy=0 when the usb in transfer is complete and endpoint ram data is available for 8051 access. usb in tokens for the endpoint are nakd while bsy=0 (the 8051 is still loading data into the endpoint buffer). a 1-to-0 transition of bsy (indicating that the 8051 can access the buffer) generates an interrupt request for the in endpoint. after the 8051 writes the data to be transferred to the in endpoint buffer, it loads the endpoints byte c ount register with the number of bytes to transfer, which automatically sets bsy=1. this enables the in transfer of data to the host in response to the next in token. again, the cpu should never load endpoint data while bsy=1. the 8051 writes a 1 to an in endpoint busy bit to disarm a previously armed endpoint. (this sets bsy=0.) the 8051 program should do this only after a usb bus reset, or when the host selects a new interface or alternate setting that uses the e ndpoint. this prevents stale data from a previous setting from being accepted by the hosts first in transfer that uses the new setting. to disarm a paired in endpoint, write a 1 to the busy bit for both endpoints in the pair. inncs endpoint (1-7) in control and status 7fb6-7fc2* b7 b6 b5 b4 b3 b2 b1 b0 - - - - - - innbsy innstl r r r r r r r/w r/w 0 0 0 0 0 0 0 0 note: even though the register description shows bit 1 as r/w, the 8051 can only clear this bit by writing a 1 to it. the 8051 can not directly set this bit.
ez-u s b s er i e s 2 1 0 0 t rm v 1.8 c h a p t er 1 2 . ez- u s b r e g i s ters p a g e 1 2 - 33 bit 0: innstl i n e ndpoint (1-7) stall the 8051 s ets this b i t to 1 t o s tal l an endpoint, and to 0 to clear a s t a l l. when the stall b i t is 1 , th e ez-usb core retu r n s a s t all handshake for a ll r equests to the endpoint. this not i f i es the host that something un e x p ected has happened. the 8051 s ets an endpoin t s stall bit under two circumsta n ces: 1 . the host sends a set_featureendpoint s t a l l request to the spe c i fic endpoint. 2 . the 8051 encounte r s an y s how s toppe r error on the endpoint, and s e t s the stall bit to tell the host to h a l t traffic to the endpoint. the 8051 c l e ars an endpoint s stall bit under two ci r cu m stances: 1 . the host sends a c l e ar_fea t ure--endpoint stall re q u est to the specific endpoint. 2 . the 8051 re c eives some o t h er indication from the host t hat the stall should be cleare d (this i s r e ferred to as host inter v en t ion in the usb specification). this indication could be a us b bus reset. all stall b i ts are autom a t ically cleared w h e n the ez-usb chip renumerate s ? by pulsing the discon bit hi.
page 12-34 chapter 12. ez-usb registers ez-usb series 2100 trm v1.8 * see table 12-5 for individual byte count register addresses. figure 12-27. in byte count registers the 8051 writes this register with the number of bytes it loaded into the in endpoint buffer innbuf. writing this register also arms the endpoint by setting the endpoint bsy bit to 1. legal values for these registers are 0-64. a zero transfer size is used to terminate a trans- fer that is an integral multiple of maxpacketsize. for example, a 256-byte transfer with maxpacketsize = 64, would require four packets of 64 bytes each plus one packet of 0 bytes. the in byte count should never be written while the e ndpoints busy bit is set. when the register pairing feature is used (section 6, "ez-usb bulk transfers") in2bc is used for the ep2/ep3 pair, in4bc is used for the ep4/ep5 pair, and in6bc is used for the ep6/ep7 pair. in the paired (double-buffered) mode, after the first write to the even-num- bered byte count register, the endpoint bsy bit remains at 0, indicating that only one of the buffers is full, and the other is still empty. the odd numbered byte count register is not used when endpoints are paired. innbc endpoint (1-7) in byte count 7fb7-7fc3* b7 b6 b5 b4 b3 b2 b1 b0 - d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w x x x x x x x x
ez-usb series 2100 trm v1.8 chapter 12. ez-usb registers page 12-35 * see table 12-5 for individual control/status register addresses. figure 12-28. out control and status registers bit 1: outnbsy out endpoint (1-7) busy the bsy bit indicates the status of the endpoints out buffer outnbuf. the ez-usb core sets bsy=0 when the host data is available in the out buffer. the 8051 sets bsy=1 by loading the endpoints byte count register. when bsy=1, endpoint ram data is invalid--the endpoint buffer has been emptied by the 8051 and is waiting for new out data from the host, or it is the process of being loaded over the usb. bsy=0 when the usb out transfer is complete and endpoint ram data in outnbuf is available for the 8051 to read. usb out tokens for the e ndpoint are nakd while bsy=1 (the 8051 is st ill reading data from the out endpoint). a 1-to-0 transition of bsy (indicating that the 8051 can access the buffer) generates an interrupt request for the out endpoint. after the 8051 reads the data from the out end- point buffer, it loads the endpoints byte count register with any value to re-arm the end- point, which automatically sets bsy=1. this enables the out transfer of data from the host in response to the next out token. the cpu should never read endpoint data while bsy=1. bit 0: outnstl out endpoint (1-7) stall the 8051 sets this bit to 1 to stall an endpoint, and to 0 to clear a stall. when the stall bit is 1, the ez-usb core returns a stall handshake for all requests to the endpoint. this notifies the host that something unexpected has happened. the 8051 sets an endpoints stall bit under two circumstances: 1. the host sends a set_featureendpoint stall request to the specific endpoint. outncs endpoint (1-7) out control and status 7fc6-7fd2* b7 b6 b5 b4 b3 b2 b1 b0 - - - - - - outnbsy outnstl r r r r r r r r/w 0 0 0 0 0 0 0 0
p a g e 1 2 - 3 6 c h a p t er 1 2 . ez- u s b r e g i s ters e z -usb s e r i e s 2 1 0 0 t r m v 1.8 2 . the 8051 encounte r s an y show s toppe r error on the endpoint, and s e t s the stall bit to tell the host to h a l t traffic t o the endpoint. the 8051 c l e ars an endpoint s stall bit under two ci r cu m stances: 1 . the ho s t sends a clear_featureendpoin t s t a l l re q u est to th e specifi c endpoint. 2 . the 8051 re c eives some o t h er indication from the host t hat the stall should be cleare d (this i s r e ferred to as host inter v en t ion in the usb specification). all s t a ll bits a r e automatically cleared when t h e e z-usb chip renumerate s ? . * se e t ab l e 12 - 5 f o r in d iv i du a l cont r ol/ s t a t u s regi s ter a ddress e s . f i g u r e 1 2 - 29 . o u t b y t e c ou nt r e g i s ters the 8051 rea d s th i s register to determ i ne the number of bytes s ent to an out endpoint. l eg a l si z es are 0 - 64 byt e s . e ach e z -usb bulk out endpoin t h as a byte count reg i s t er, which serves two purposes. the 8051 r eads the byt e coun t r e gis t e r t o deter m ine ho w man y bytes we r e r e ceived during the la s t out tra n s fe r from the host. the 8051 w r i t e s the byte coun t reg i st e r ( w ith any value) to t e l l the e z-usb core that i t has fini s h ed read i ng bytes fr o m t h e bu f f er, making the bu f fer available to a ccept the ne x t o ut t ra n sf e r. writ i n g the b y t e c ount r e g is ter sets the e ndpoint s bsy bit to 1. when the register-pa i ri n g f eat u re is used, o ut2 b c is used f o r the ep2 / ep3 p a ir, out 4 b c is u sed for th e ep4/ep5 p a ir, and ou t 6bc is use d for the e p 6/ep 7 pair. the odd-numbered byt e coun t reg i st e r s shoul d no t b e us e d. when the 8051 w r it e s a b y te to the even numbered byte c ount regi s ter, t h e ez - usb co r e swit c he s buf f e rs . if the o t he r b u ffer al r e ady co n t a ins d a t a to b e read by the 8051, the outnbs y b i t remains at 0. a ll out toke n s a r e nakd unt i l the 8051 is released f r om re s et, w h ereupon the ack/ nak behavior i s ba s ed on pairing. outnbc e n d poin t (1-7) ou t b y te cou n t 7 f c7-7fd3* b7 b6 b5 b4 b3 b2 b1 b0 - d6 d5 d4 d3 d2 d1 d0 r r r r r r r r/w 0 0 0 0 0 0 0 0
ez-u s b s er i e s 2 1 0 0 t rm v 1.8 c h a p t er 1 2 . ez- u s b r e g i s ters p a g e 1 2 - 37 f i gu r e 1 2 - 3 0 . s e t up d a ta p o i n ter h ig h / l ow r eg i sters when the e z -usb chip recei v e s a get _ descrip t or request on endpoint zer o , it can instruct t h e e z-usb core to handle t he multi-p a c ket in transfer by load i ng t he s e registers with the a d d r ess of an inter n al table containing the d e scriptor data. the d e script o r data tables ma y be placed i n internal pr o g r am/ d at a r a m or in unuse d endpoint 0-7 r a m . the su d ptr does not operate with ex t ernal me m o ry. t h e s u dp t r registers should be loaded in high/ l ow orde r . in addition to loading s u d p t rl, the 8051 must also clear the h snak bit in the ep0cs r eg i s ter (by writing a 1 to it) to co m plete the control t r ansfer. 12.1 4 global usb r e gisters su d p trh set u p d a ta poin t e r high 7fd4 b7 b6 b5 b4 b3 b2 b1 b0 a15 a14 a13 a12 a 1 1 a10 a9 a8 r/w r/w r/w r/w r/w r/w r/w r/w x x x x x x x x su d p trl setup data poi n ter low 7fd5 b7 b6 b5 b4 b3 b2 b1 b0 a7 a6 a5 a4 a3 a2 a1 a0 r/w r/w r/w r/w r/w r/w r/w r/w x x x x x x x x note any hos t re q u est t hat u ses t h e ez-usb setup data pointer to t ransf e r in data must indi- c a te the number of bytes to tran s f er in bytes 6 (wlenght h l) and 7 (wlengthh) of the se t up pa c ket. these bytes a re pr e -as s igned i n t h e u s b s peci f i c ation to b e lengt h bytes in a l l s tandard devi c e r e quests s u ch as g e t_descri p tor . if vendor-specific requests are u s ed to t r an s fe r large blocks of d a ta u s in g the se t up data pointe r, they must include this pre-defined length field in b y t e s 6-7 to tell t h e ez-usb core how ma n y bytes to transfer u s ing the s e t up data pointer.
page 12-38 chapter 12. ez-usb registers ez-usb series 2100 trm v1.8 figure 12-31. usb control and status registers bit 7: wakesrc wakeup source this bit indicates that a high to low transaction was detected on the wakeup# pin. writ- ing a 1 to this bit resets it to 0. bit 3: discon signal a disconnect on the discon# pin the ez-usb discon# pin reflects the complement of this bit. this bit is normally set to 0 so that the action of the discoe bit (below) either floats the discon# pin or drives it hi. bit 2: discoe disconnect output enable discoe controls the output buffer on the discon# pin. when discoe=0, the pin floats, and when discoe=1, it drives to the complement of the discon bit (above). discoe is used in conjunction with the renum bit to perform renumeration ? (chap- ter 5, "ez-usb enumeration and renumeration ? "). usbcs usb control and status 7fd6 b7 b6 b5 b4 b3 b2 b1 b0 wa k e s r c - - - discon discoe renum sigrsume r/w r r r r/w r/w r/w r/w 0 0 0 0 0 1 0 0
ez-usb series 2100 trm v1.8 chapter 12. ez-usb registers page 12-39 bit 1: renum renumerate this bit controls which entity, the usb core or the 8051, handles usb device requests. when renum=0, the ez-usb core handles all device requests. when renum=1, the 8051 handles all device requests except set_address. the 8051 sets renum=1 during a bus disconnect to transfer usb control to the 8051. the ez-usb core automatically sets renum=1 under two conditions: 1. completion of a b2 boot load (chapter 5, "ez-usb enumeration and renumer- ation ? "). 2. when external memory is used (ea=1) and no boot i 2 c eeprom is used (see section 10.3.3, "external rom"). bit 0: sigrsume signal remote device resume the 8051 sets sigrsume=1 to drive the k state onto the usb bus. this should be done only by a device that is capable of remote wakeup, and then only during the sus- pend state. to signal resume, the 8051 sets sigrsume=1, waits 10-15 ms, then sets sigrsume=0.
page 12-40 chapter 12. ez-usb registers ez-usb series 2100 trm v1.8 figure 12-32. data toggle control register bit 7: q data toggle value q=0 indicates data0 and q=1 indicates data1, for the endpoint selected by the io and ep[2..0] bits. the 8051 writes the endpoint select bits (io and ep[2..0]), before reading this value. bit 6: s set data toggle to data1 after selecting the desired endpoint by writing the e ndpoint select bits (io and ep[2..0]) the 8051 sets s=1 to set the data toggle to data1. the endpoint selection bits should not be changed while this bit is written. bit 5: r set data toggle to data0 after selecting the desired endpoint by writing the e ndpoint select bits (io and ep[2..0]) the 8051 sets r=1 to set the data t oggle to data0. the endpoint selection bits should not be changed while this bit is written. for advice on when to reset the data toggle, see chap- ter 7, "ez-usb endpoint zero." bit 4: io select in or out endpoint the 8051 sets this bit to select an endpoint direction prior to setting its r or s bit. io=0 selects an out endpoint, io=1 selects an in endpoint. togctl data toggle control 7fd7 b7 b6 b5 b4 b3 b2 b1 b0 q s r io 0 ep2 ep1 ep0 r r/w r/w r/w r/w r/w r/w r/w x x x x x x x x note at this writing there is no known reason to set an endpoint data t oggle to 1. this bit is provided for generality and testing only.
ez-usb series 2100 trm v1.8 chapter 12. ez-usb registers page 12-41 bit 2-0: ep select endpoint the 8051 sets these bits to select an endpoint prior to setting its r or s bit. valid values are 0-7 to correspond to bulk endpoints in0-in7 and out0-out7. figure 12-33. usb frame count high/low register every millisecond the host sends a sof token indicating start of frame, along with an 11-bit incrementing frame count. the ez-usb copies the frame count into these registers at every sof. one use of the frame count is to respond to the usb sync_frame request (chapter 7, "ez-usb endpoint zero"). if the usb core detects a missing or garbled sof, it generates an internal sof and incre- ments usbframel-usbrameh. usbframel usb frame count low 7fd8 b7 b6 b5 b4 b3 b2 b1 b0 fc7 fc6 fc5 fc4 fc3 fc2 fc1 fc0 r r r r r r r r x x x x x x x x usbframeh usb frame count high 7fd9 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 fc10 fc9 fc8 r r r r r r r r x x x x x x x x
page 12-42 chapter 12. ez-usb registers ez-usb series 2100 trm v1.8 figure 12-34. function address registe during the usb enumeration process, the host sends a device a unique 7-bit address, which the ez-usb core copies into this register. there is normally no reason for the cpu to know its usb device address because the usb core automatically responds only to its assigned address. fnaddr function address 7fdb b7 b6 b5 b4 b3 b2 b1 b0 0 fa6 fa5 fa 4 fa 3 fa 2 fa 1 fa0 r r r r r r r r x x x x x x x x note during renumeration ? the usb core sets register to 0 to allow the ez-usb chip to respond to the default address 0.
ez-u s b s er i e s 2 1 0 0 t rm v 1.8 c h a p t er 1 2 . ez- u s b r e g i s ters p a g e 1 2 - 43 f i gu r e 12 - 3 5 . u s b e n d p o i n t p a i r i n g r e g i s t e r bit 7: isosend0 i soch r onous send zero length data pack e t the i s osend0 bit is used whe n the ez-usb chip r e ceives an is o c hronous in token while the in f i fo is emp t y. i f is o s end0=0 (the d e f ault value), t h e ez-us b core does not respond to the i n token. i f iso s end0=1, t h e ez-usb c ore se n d s a zero-length data packet in re s ponse to the in token. which action to take depends on the overall system design. the i s os e nd0 bit applies t o all of the is o chronous i n e ndpo i nts, in8buf through i n15 b u f . bit 5-3: p rnout pair bul k ou t endpoints set the endpoint pairing bi t s (p r xout) to 1 to enable doub l e-buffering of the bulk o u t endpoint b u ffers . with doubl e buffering enabled, the 8051 can operate on one bu f fer wh i le another is being t ra n sf e rred o v er usb. the endpoint busy and i n terrupt r equest b i ts function ident i c a l l y , so the 8051 code re q u ires no code m odification to sup- po r t double bu f fe r ing. when an endpoint i s p a i red, the 8051 u ses only the even-numbered endpoi n t of the p air. the 8051 should not use the paired odd endpoin t s i r q, i en, v a l id b i ts or the bu f fer associated with the odd numbered endpoint. bit 2-0: p rnin pair bul k in endpoints set the endpoint pairing bi t s ( p rxin) to 1 to enable doubl e -buffering of the bulk in endpoint bu f fe r s . w ith doubl e buf f ering enabled, the 8051 can operate o n one buffer while ano t h er i s being transf e rred over usb. when an endpoint i s p a i red, the 8051 should a ccess only the even-numbered endpoint of the pai r . the 8051 should not use t h e i rq , ie n , valid b it s o r th e buffer associated with the odd numb e red endpoint. usb p air u s b e ndpo i n t pairing 7fdd b7 b6 b5 b4 b3 b2 b1 b0 i s o s e n d 0 - pr6out pr4out pr2out pr6 i n pr4 i n pr2 i n r/w r/w r/w r/w r/w r/w r/w r/w 0 x 0 0 0 0 0 0
p a g e 1 2 - 4 4 c h a p t er 1 2 . ez- u s b r e g i s ters e z -usb s e r i e s 2 1 0 0 t r m v 1.8 f i g u re 1 2 -36. in / o u t v a l id b i t s r e g ister the 8051 s e ts v a l =1 fo r any active endpo i nts , a n d val= 0 fo r inactive endpoin t s. these bits instruc t the ez-usb core to retu r n a no re s ponse i f an invalid e ndpo i n t i s addressed, instea d o f a nak. the default value s of these r e g ist e rs a r e set to support a l l e ndpoint s t hat e xist in th e default usb device ( s e e t a b le 5- 1 ). in07 v al e n dpoi n ts 0-7 in va l id bits 7fde b7 b6 b5 b4 b3 b2 b1 b0 in 7 v al in 6 v al in 5 v al in 4 v al in 3 v al in 2 v al in 1 v al in 0 v al r/w r/w r/w r/w r/w r/w r/w r/w 0 1 0 1 0 1 1 1 o u t 07val endp o ints 0-7 out val i d b its 7fdf b7 b6 b5 b4 b3 b2 b1 b0 out7 v al out6 v al out5 v al out4 v al out3 v al out2 v al out1 v al out0 v al r/w r/w r/w r/w r/w r/w r/w r/w 0 1 0 1 0 1 0 1
ez-u s b s er i e s 2 1 0 0 t rm v 1.8 c h a p t er 1 2 . ez- u s b r e g i s ters p a g e 1 2 - 45 f i g u re 1 2 -37 . i s o c h r onous i n /o u t e n d p o i n t v a l id b i t s r e g ister the 8051 s e ts v a l =1 fo r active endpo i nts , a n d val= 0 fo r inactive endpoin t s. these bits instruct the e z - u s b core to return a no re s pons e if an invalid e ndpoint i s a ddressed. the de f a ult values o f these r e gis t er s a re se t t o suppor t a l l endpoints th a t exi s t i n the default usb device ( s e e t a b le 5- 1 ). in i s o v al i sochronous in endp o int v a lid bits 7 f e0 b7 b6 b5 b4 b3 b2 b1 b0 i n 1 5 v a l i n 1 4 v a l i n 1 3 v a l i n 1 2 v a l i n 1 1 v a l i n 1 0 v a l in 9 v al in 8 v al r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 1 1 1 outis o v a l isochronous ou t e n d p oint valid b i t s 7 f e1 b7 b6 b5 b4 b3 b2 b1 b0 o u t 1 5 val o u t 1 4 val o u t 1 3 val o u t 1 2 val out 1 1 v al out1 0 val out9 v al out8 v al r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 1 1 1
p a g e 1 2 - 4 6 c h a p t er 1 2 . ez- u s b r e g i s ters e z -usb s e r i e s 2 1 0 0 t r m v 1.8 f i g u r e 1 2 - 38 . f a s t t r a n sfer c o n t r ol r eg i ster the e z-usb co r e provid e s a fast t ransf e r mode t h a t impr o v es th e 8051 t r a n s f e r s peed between external logic and the isochronous and bulk endpoi n t buffers. t he f astxfr r eg i s ter enabl e s the modes for bulk and/or isochronous transfers, and s e lects the timing wavefo r ms for the f r d# and fwr# signals. bit 7: f i s o enable fa s t iso t ransfe r s the 8051 s ets fiso=1 to enable fa s t isochronous transfers fo r a l l 16 isochronous endpoint f i fos. when f i so=0, fa s t t r ansfers a r e disabled fo r all 16 isochronous endpoints. bit 6: f b lk enable fa s t bulk t ransfe r s the 8051 s ets fblk=1 to enable f a s t bulk t ran s f e r s u s ing the autopointer ( see s e ction 12.16, " s e t u p dat a " ) with bulk endpoin t s . when fblk=0 f a s t transfers are d i sabled for bu l k endpoints. bit 5: r p ol f rd# pulse pola r ity the 8051 s ets rpol=0 for active-low frd# p u lses, and r pol= 1 for active high frd# pulses. bit 4-3: rmod f rd# pulse mode the s e b i ts select the p h asing and width of the frd# p u lse. s e e fi g u re 8-12. 12.1 5 fast t ra n s f e r s f a s t x f r fast t ransfer co n trol 7 f e2 b7 b6 b5 b4 b3 b2 b1 b0 fi s o fblk rpol rmod1 rmod0 w p ol w m o d 1 w m o d 0 r/w r/w r/w r/w r/w r/w r/w r/w x x x x x x x x
ez-usb series 2100 trm v1.8 chapter 12. ez-usb registers page 12-47 bit 2: wpol fwr# pulse polarity the 8051 sets wpol=0 for active-low fwr# pulses, and wpol=1 for active high fwr# pulses. bit 1-0: wmod fwr# pulse mode these bits select the phasing and width of the fwr# pulse. see figure 8-11.
p a g e 1 2 - 4 8 c h a p t er 1 2 . ez- u s b r e g i s ters e z -usb s e r i e s 2 1 0 0 t r m v 1.8 f i g u r e 1 2 - 39. a u t o p o i n t e r r e g i s t ers the s e r egi s te r s implement the ez-us b autopointe r . a u t o ptrh/l the 8051 loads a 16-bi t address into the a u t o p t rh/ l r eg i s ters. sub s equent reads or w r it e s to the au t o data register increment the 16-bit value i n these r e g i sters. the loaded add r e s s must be in int e rnal e z - u s b r a m. the 8051 c a n read t h es e r e g i sters to determine the a d d r e s s must be in inter n a l ez-usb ram. the 8051 can read these regis- te r s to determi n e the a d d ress of the next byte to be accessed vi a t he autoda t a register. a u tod a t a 8051 data read o r written t o t h e a utodata reg i st e r accesses the me m ory addressed by the aut o ptrh/l registers, and increments the addre s s a f ter the read o r write. the s e r eg i s ters allo w fifo a c cess to the bulk endpoi n t buf f e rs, as w ell as bei n g usefu l for intern a l data movement. chapter 6, "e z -usb bul k transfer s " and chapter 8, " ez- u sb i sochronous t ran s f ers" exp l a in how to u s e the autopointer for f ast transfers t o and from the e z -usb endpoint bu f f e r s . au t o p t rh a u to poin t er ad d r e ss high 7 f e3 b7 b6 b5 b4 b3 b2 b1 b0 a15 a14 a13 a12 a 1 1 a10 a9 a8 r/w r/w r/w r/w r/w r/w r/w r/w x x x x x x x x au t o p t rl auto po i nter a d dr e ss low 7 f e4 b7 b6 b5 b4 b3 b2 b1 b0 a7 a6 a5 a4 a3 a2 a1 a0 r/w r/w r/w r/w r/w r/w r/w r/w x x x x x x x x au t o d a ta auto poi n ter data 7 f e5 b7 b6 b5 b4 b3 b2 b1 b0 d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w x x x x x x x x
ez-usb series 2100 trm v1.8 chapter 12. ez-usb registers page 12-49 figure 12-40. setup data buffer this buffer contains the 8 bytes of setup packet data from the most recently received control transfer. the data in setupbuf is valid when the sudavir (setup data available interrupt request) bit is set. the 8051 responds to the sudav interrupt by reading the setup bytes from this buffer. 12.16 setup data setupbuf setup data buffer (8 bytes) 7fe8-7fef b7 b6 b5 b4 b3 b2 b1 b0 d7 d6 d5 d4 d3 d2 d1 d0 r r r r r r r r x x x x x x x x
page 12-50 chapter 12. ez-usb registers ez-usb series 2100 trm v1.8 * see table 12-6 for individual start address register addresses. figure 12-41. setup data buffer 12.17 isochronous fifo sizes outnaddr iso out endpoint start address 7ff0-7ff7* b7 b6 b5 b4 b3 b2 b1 b0 a9 a8 a7 a6 a5 a4 0 0 r/w r/w r/w r/w r/w r/w r/w r/w x x x x x x x x innaddr iso in endpoint start address 7ff8-7fff* b7 b6 b5 b4 b3 b2 b1 b0 a9 a8 a7 a6 a5 a4 0 0 r/w r/w r/w r/w r/w r/w r/w r/w x x x x x x x x
ez-usb series 2100 trm v1.8 chapter 12. ez-usb registers page 12-51 ez-usb isochronous endpoints use a pool of 1,024 double-buffered fifo bytes. the 1,024 fifo bytes can be divided between any or all of the isochronous e ndpo ints. the 8051 sets isochronous endpoint fifo sizes by writing starting addresses to these registers, starting with address 0. address bits a3-a0 are internally set to zero, so the minimum fifo size is 16 bytes. see section 8.8, "fast transfer speed" for details about how to set these registers. table 12-6. isochronous fifo start address registers address endpoint start address 7ff0 endpoint 8 out start address 7ff1 endpoint 9 out start address 7ff2 endpoint 10 out start address 7ff3 endpoint 11 out start address 7ff4 endpoint 12 out start address 7ff5 endpoint 13 out start address 7ff6 endpoint 14 out start address 7ff7 endpoint 15 out start address 7ff8 endpoint 8 in start address 7ff9 endpoint 9 in start address 7ffa endpoint 10 in start address 7ffb endpoint 11 in start address 7ffc endpoint 12 in start address 7ffd endpoint 13 in start address 7ffe endpoint 14 in start address 7fff endpoint 15 in start address
page 12-52 chapter 12. ez-usb registers ez-usb series 2100 trm v1.8
ez-usb series 2100 trm v1.8 chapter 13. ez-usb ac/dc parameters page 13-1 13 ez-usb ac/dc parameters 13.1.1 absolute maximum ratings storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65 o c to +150 o c ambient temperature under bias . . . . . . . . . . . . . . . . . . . .-40 o c to +85 o c supply voltage to ground potential . . . . . . . . . . . . . . . . . . . -0.5v to +4.0v dc input voltage to any pin . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to +5.8v 13.1.2 operating conditions ta (ambient temperature under bias). . . . . . . . . . . . . . . . . . 0 o c to +70 o c supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.0v to +3.6v ground voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0v f osc (oscillator or crystal frequency) . . . . . . . . . . . . . . 12 mhz +/- 0.25% 13.1.3 dc characteristics 13.1 electrical characteristics table 13-1. dc characteristics symbol parameter condition min max unit notes v cc supply voltage 3.0 3.6 v v ih input high voltage 2 5.25 v v il input low voltage -.5 .8 v i i input leakage current 0 < v in < v cc + 10 m a v oh output voltage high i out = 1.6 ma 2.4 v v ol output low voltage i out = -1.6 ma .8 v c in input pin capacitance 10 pf i susp suspend current 275 m a i cc supply current 8051 running, connected to usb 50 ma
p a g e 1 3 -2 c h a p t e r 1 3 . ez - usb ac/dc p a r a m e ters e z -usb s e r i e s 2 1 0 0 t r m v 1.8 13.1.4 ac el e c trical characteristics spec i fied condition s : capacitive load on all pins = 30 pf 13.1.5 general memor y t i ming 13.1.6 p r ogram m emory read 13.1.7 data m emory read t ab l e 13- 2 . ge n e r al m e m o r y tim i ng sy m b o l p a r a m e t e r m i n typ m a x un i t notes t cl 1 / cl k 24 fr e quency 4 1 .66 ns t a v d e l ay f rom c l o c k t o v a lid add r ess 0 10 n s t c d d e l ay f rom c lk2 4 to c s# 2 15 ns t o e d d e l ay f rom c lk2 4 to oe# 2 15 ns t wd d e l ay f rom c lk2 4 to wr# 2 15 ns t r d d e l ay f rom c lk2 4 to rd# 2 15 ns t p d d e l ay f rom c lk2 4 to p s e n# 2 15 ns t ab l e 13-3 . p r o g r a m m e mor y r e ad s y m b o l p a r a m e t e r f o r m u l a m i n m a x un i t not e s t a a1 ad d ress a cc e s s time 3 t c l - t a v-td s u1 103 ns t a h1 ad d ress hold f r o m clk 2 4 t c l+1 42 ns t d s u1 da t a s e t up to c l k24 12 ns t d h1 da t a h o l d f rom cl k 24 0 n s t a b l e 1 3 -4 . d a t a m e m o r y read sy m b o l para m eter fo r m u l a m i n m a x un i t notes t a a2 a d dr e ss a c ce s s t i m e 3 t cl- t a v - t d su1 103 ns t ah2 a d dr e ss hold fr o m c l k24 t cl+1 4 2 ns t dsu2 d a t a se t up to clk24 1 2 ns t dh2 d a t a hold f rom c l k24 0 ns
ez-u s b s er i e s 2 1 0 0 t rm v 1.8 c h a p t e r 1 3 . ez - usb ac/dc p a r a m e t ers p a g e 1 3-3 13.1.8 data m emory w rite 13.1.9 fast data w ri t e 13.1.1 0 fast data read t a b l e 1 3 -5 . d a ta m e mo r y w rite s y m b o l p a r a m e t er fo r m u l a m i n max un i t n o t es t a h3 ad d ress ho l d f r o m clk24 t cl+2 43 ns t dzv clk 2 4 t o d a t a v a lid 15 ns t d v z clk 2 4 t o hig h i m p edance t c l + 1 6 57 ns t a b l e 1 3 -6 . fast d a t a w rite s y m b o l p a r a m e t er c o n d i t i on s m i n max un i t n o t es t cdo clock to d a t a o u t p ut d elay 3 15 ns t c wo clock to f i f o wr i te o u tput delay 2 1 0 n s t p f wd pro p a g ation dela y d i ffer- e n c e f r om f i f o w r i t e t o d a t a out 1 n s t a b l e 13 - 7 . f a s t d ata r e a d s y m b o l p a r a m e t er c o n d i t i on s m i n max un i t n o t es t cro clock to f i fo r e a d o u tput delay 2 1 0 n s t d s u4 da t a s e t u p t o risin g c lk24 12 ns t d h 4 da t a hold t o rising c l k24 0 n s
page 13-4 chapter 13. ez-usb ac/dc parameters ez-usb series 2100 trm v1.8 figure 13-1. external memory timing figure 13-2. program memory read timing clk24 a [15.0] tcl cs# tav tcd tcd oe# toed toed wr# twd twd rd# trd trd psen# tpd tpd clk24 a [15.0] tcl tah1 psen# d [7.0] tdh1 tdsu1 cs# oe# taa1
ez-usb series 2100 trm v1.8 chapter 13. ez-usb ac/dc parameters page 13-5 figure 13-3. data memory read timing figure 13-4. data memory write timing clk24 a [15.0] tcl tah2 rd# d [7.0] tdh2 tdsu2 cs# oe# taa2 clk24 a [15.0] tcl tah3 cs# d [7.0] tdv tdzv wr#
page 13-6 chapter 13. ez-usb ac/dc parameters ez-usb series 2100 trm v1.8 figure 13-5. fast transfer mode block diagram clk24 d [7:0] fwr# ez-usb an2131q asic 80 pqfp ez-usb fast transfer block diagram fifo clock d [7:0] fifo write stob frd# fifo read stob
ez-usb series 2100 trm v1.8 chapter 13. ez-usb ac/dc parameters page 13-7 figure 13-6. fast transfer read timing [mode 00] figure 13-7. fast transfer write timing [mode 00] clk24 d[7..0] frd#[00] tcl input tdsu4 tdh4 tcro clk24 d[7..0] fwr#[00] tcl output tcdo tcdo tcwo tcwo
page 13-8 chapter 13. ez-usb ac/dc parameters ez-usb series 2100 trm v1.8 figure 13-8. fast transfer read timing [mode 01] figure 13-9. fast transfer write timing [mode 01] clk24 d[7..0] frd#[01] tcl input tdsu4 tdh4 tcro clk24 d[7..0] fwr#[01] tcl output tcdo tcdo tcwo tcwo tpfwd
ez-usb series 2100 trm v1.8 chapter 13. ez-usb ac/dc parameters page 13-9 figure 13-10. fast transfer read timing [mode 10] figure 13-11. fast transfer write timing [mode 10] clk24 d[7..0] frd#[10] tcl input tdsu4 tdh4 tcro clk24 d[7..0] fwr#[10] tcl output tcdo tcdo tcwo tcwo
page 13-10 chapter 13. ez-usb ac/dc parameters ez-usb series 2100 trm v1.8 figure 13-12. fast transfer read timing [mode 11] figure 13-13. fast transfer write timing [mode 11] clk24 d[7..0] frd#[11] tcl input tdsu4 tdh4 tcro clk24 d[7..0] fwr#[11] tcl output tcdo tcdo tcwo tcwo tpfwd
ez-usb series 2100 trm v1.8 chapter 14. ez-usb packaging page 14-1 14 ez-usb packaging figure 14-1. 44-pin pqfp package (top view) figure 14-2. 44-pin pqfp package (side view) 14.1 44-pin pqfp package 1 10.10 9.90 13.45 12.95 8.00 ref 11 33 23 12 22 44 34 0.80 bsc. 2.35 max see lead d etail 0.45 0.30
page 14-2 chapter 14. ez-usb packaging ez-usb series 2100 trm v1.8 figure 14-3. 44-pin pqfp package (detail view) 0 o ~7 o 0.95 0.65 1.60 typ lead detail: a(s=n/s) 2.10 1.95 0.25 0.10 0.23 0.13
ez-usb series 2100 trm v1.8 chapter 14. ez-usb packaging page 14-3 figure 14-4. 80-pin pqfp package (top view) figure 14-5. 80-pin pqfp package (side view) 14.2 80-pin pqfp package 3.0 3.0 80 pqfp 0.80 1.00 ref 124 25 40 64 41 80 65 0.80 bsc. 24.10 23.70 20.05 19.95 14.05 13.95 18.10 17.70 3.04 max 0.42 0.32 see lead detail
page 14-4 chapter 14. ez-usb packaging ez-usb series 2100 trm v1.8 figure 14-6. 80-pin pqfp package (detail view) 0 o ~7 o 1.00 0.80 1.95 + 0.15 detail "a" 2.76 2.66 0.28 0.18 8 places 12 o ref. base plane seating plane 0 o ~10 o 0.25 gage plane
ez-usb series 2100 trm v1.8 chapter 14. ez-usb packaging page 14-5 figure 14-7. 48-pin pqfp package (side view) figure 14-8. 48-pin pqfp package (top view) 14.3 48-pin pqfp package 2.35 max see lead detail 0.27 0.17 1 12 36 25 13 24 48 37 0.50 bsc. 48 pqfp 9.00 bsc. 7.00 bsc.
page 14-6 chapter 14. ez-usb packaging ez-usb series 2100 trm v1.8 figure 14-9. 48-pin pqfp package (detail view) 0.05 0.15 1.35 1.45 0.08 0.20 0 o min. 0.08 r. min. 0.20 min. 0.25 gauge plan r. 0 - 7 o 1.00 ref. 0.45 0.75 seating plane base plane 48-pin lead detail
e z - u s b s e r i e s 2 1 00 t rm v 1 . 8 a p p e n d ix a : 8 0 5 1 i n t r o d u c t i o n a - 1 appen d ix a: 8051 i n tr o duction the e z - usb contains an 8051 co r e that is binary compatible with the i ndust r y standard 8051 instruction s et. this appendix provi d es an overview of the 805 1 c o re f e at u r e s. t he topi c s are: ? new 8051 features ? per f ormance overvi e w ? so f tware compatibility ? 803x/805x feature compa r ison ? 8051/ds80c320 diff e re n ces the 8051 core provides the following de s ign f e atu r e s and enhancemen t s to the standard 8051 micro-contro l l e r : ? compatible w i th industry s t andard 803x/805x: - s t andard 8051 in s truction set - t wo full-duplex s e rial p o rts - three t i m ers ? high - speed ar c hi t ec t ur e : - 4 clocks/instruction cycle - 2.5x average improvement in instruction executi o n t ime o v er the standard 8051 - runs dc t o 25-m h z clock - w a s t ed b u s cyc l es e l iminated - dual d a t a pointers ? 256 by t e s int e rnal data r am ? high-s p eed external memory inter f a ce w i th 16-bit address bus ? v ariable lengt h movx to a c ce s s fas t /slow ram p eripherals a .1 in t roduction a .2 8051 featur e s
a - 2 appendix a: 8051 introduction ez-usb series 2100 trm v1.8 ? fully static synchronous design ? supports industry standard compilers, assemblers, emulators, and rom monitors the 8051 core has been designed to offer increased performance by executing instructions in a 4-clock bus cycle, as oppo sed to the 12-clock bus cycle in the standard 8051 (see figure a- 1.). the shortened bus timing improves the instruction execution rate for most instructions by a factor of three over the standard 8051 architectures. some instructions require a different number of instruction cycles on the 8051 c ore than they do on the standard 8051. in the standard 8051, all instruct ions except for mul and div take one or two instruction cycles to complete. in the 8051 core, instructions can take between one and five instruction cycles to complete. the average speed improvement for the entire instruc- tion set is approximately 2.5x, calculated as follows: a.3 performance overview number of opcodes speed improvement 150 3.0x 51 1.5x 43 2.0x 2 2.4x total: 255 average: 2.5x note: comparison is for 8051 and standard 8051 running at the same clock frequency.
e z - u s b s e r i e s 2 1 00 t rm v 1 . 8 a p p e n d ix a : 8 0 5 1 i n t r o d u c t i o n a - 3 the 8051 co r e is object code compatible with the industry standard 8051 micro-cont r oller. that is, object code com p iled with an indust r y standard 8051 compiler o r assembler will exe- cute o n the 805 1 core and will b e functionally equivalent. how e ve r , bec a use the 8051 core uses a di f ferent ins t r uction timing t h a n the standard 8051, exi s t ing c o d e with timing loops may require modification. the instruct i o n set i n table b-2 on page b-5 li s ts the numb e r o f ins t ruction cycles r equired to per f orm each i n s truction on th e 8051 core. the 8051 instruction cycle timing and number o f instruction cycles requ i red fo r e ach i n str u c tion are compati b l e with the dallas semiconduc- to r ds80c320. f i g u r e a - 1. c o m p a r a t i v e t i m i n g o f 8 0 5 1 a nd i nd u s t r y s t andard 8051 a . 4 software compatibility p s e n # a l e x t a l 1 a d 0-ad7 p s e n # a l e p o r t2 8 0 51 t iming s t an d ard 8 0 5 1 t i m ing p o r t2 s i n g l e by t e si n gle cy c l e i ns t r uc t ion s i n g le b y t e s in g l e cy c l e i n s t ru c t i o n a d 0-ad7 4 12
a - 4 ap p e n d i x a: 8 0 51 i n tr o d u c t ion e z -usb se r i e s 2 1 00 t r m v1.8 t able a-1 provides a f e a t ure-by-f e a t ure comparison of the 8051 c o r e and se v e ral common 803x/805x configu r a t ion s . a . 5 803x/805x feature comparison t ab l e a-1. f e a t u r e s u m ma r y o f 8 0 5 1 c ore a n d c o m m o n 8 0 3 x / 8 0 5 x c o n f i gurations feature intel d allas ds80c3 20 anchor 8051 8031 8051 80c32 80c52 c locks per instruction cycle 12 12 12 12 4 4 prog r a m / data memor y - 4 kb r o m - 8 k b r o m - 8 k r a m internal r am 128 byt e s 128 byt e s 256 byt e s 256 byt e s 256 byt e s 256 bytes d ata pointers 1 1 1 1 2 2 s e r i a l p o r t s 1 1 1 122 16-bi t timers 2 2 3 3 3 3 interrupt sourc e s (total of int. and ext.) 5 5 6 6 1 3 1 3 stretch m e mory cycles n o n o n o n o y e s y e s
e z - u s b s e r i e s 2 1 00 t rm v 1 . 8 a p p e n d ix a : 8 0 5 1 i n t r o d u c t i o n a - 5 the 8051 core is s i m ilar to the ds80c320 i n t e rms of hardwar e f eat u r e s and instruction cycle t i ming. howev e r, t h e re are some importan t d i ff e rences between the 8051 core and the ds80c320. a.6. 1 serial ports the 8051 co r e does not imp l e ment s e rial p o rt f raming error d e t ectio n and does no t implement slave addre s s com p a rison f o r mu l tipro c essor communi c ations. th e r efore, t h e 8051 core also does not implement t he fol l owing s f r s: s a ddr0, saddr1, saden 0 , and saden1. a.6. 2 t imer 2 the 8051 co r e does not impleme n t timer 2 downcounting mode or the downcount enable bit ( tmod2, b i t 0 ) . also, the 8051 core does not im p l e men t timer 2 output ena b le ( t 2oe) bit ( tmod2, b i t 1 ) . therefo r e, the tm o d2 s fr is also not implemented in the 8051 core. also, the 8051 core t i mer 2 ove r flow output is active for one clock cycle. in the ds80c320, the t imer 2 o v erflow output is a square wave with a 50% duty cycle. a.6. 3 t imed acc e ss p rotection the 8051 core d o e s not implement t i m e d acce s s protection and ther e fore, does not implement the t a sfr. a.6. 4 w atchd o g t i mer the ez-usb/8051 does not im p l em e nt a watchdog t imer. a .6 8051 cor e /ds80c320 diff e rences
a - 6 appendix a: 8051 introduction ez-usb series 2100 trm v1.8
ez-usb series 2100 trm v1.8 appendix b: 8051 architectural overvie b - 1 appendix b: 8051 architectural overview this appendix provides a technical overview and description of the 8051 core archi tecture. b.1 introduction figure b-1. 8051 block diagram 8051_cpu 8051_intr_0 8051_ram_128 8051_timer (lower 128 byte ram) timers 0 and 1 8051_timer2 8051_serial serial port 0 timer 2 interrupt unit interrupts a15-a0 port_control 805 (0..7fh direct/indirect) pc4/to, pc5/t1 pa0/t0_out, pc1/txd0 pa6/rxd0out pc0/rxd0in pb0/t2 pb1/t2ex 8051_biu 8051_op_decoder 8051_ram_128 8051_alu 8051_control (80..ffh indirect) clk24 pb7/t2out 8051_ main_regs 8051_intr_1 or 8051_serial serial port 1 pb3/txd1 pa7/rxd1out pb2/rxd1in pa1/t0_out d7 - d0 reset#
b - 2 a p p e n d ix b : 8 0 51 a r c hi t e ct u ral o v e r vie e z - u s b s e r i e s 2 1 00 t r m v1 . 8 b.1. 1 memory organization memory organi z a tion in the 8051 core is s i m i lar to th a t of the industry standard 8051. there ar e three distinct memory a r eas: p r ogr a m memory (r o m ) , dat a memory (external ram), and r eg i s ters ( interna l r am). b.1.1.1 p rogra m memory the e z-usb provides 8k of data that is mapped as both program a n d d ata memory at addres s es 0x0000-0x1b 3f. i n addition, th e bul k endpoint buf f ers ma y be use d as external data memory if the y a r e not use d a s endpoint bu f fers. see c hapte r 3, "ez- u sb mem o ry" for m o re details. b.1.1.2 external ram the e z-usb chip has dedicated addr e ss and data pins, so port 2 and p o rt 0 are not used to a c cess t h e memory bus. as shown in chapter 3 , "ez-usb memory" , the e z - u sb is expand- able to over 100k o f external program and da t a mem o ry. b.1.1.3 internal ram the internal r a m (figu r e b-2) consi s ts of: ? 128 bytes of regi s t ers and scratch p a d memory accessib l e through dir e c t or indirect addres s ing (add r e s s es 00hC7fh). ? a 128 r egister space for special fun c ti o n r egis t ers ( s f rs) accessi b le through direct addres s ing (add r e s s es 80hC f fh). ? upper 128 b y t es o f scratch pad memo r y accessible through indir e c t addressing ( add r e s ses 80hCffh). although the s fr sp a ce and the upper 128 bytes of r a m share the s a m e address range, the actual addr e ss s pace is separate and i s d i ff e r e n tiat e d by the t ype of addre s s ing. d i rect a ddress- ing a c ce s ses the s f rs, and indirec t a ddres s i n g accesses the upper 128 b y tes of ram. the lower 128 bytes are organized as shown in fi g u re b-2. the lo w er 32 bytes (0x00-0xif) for m four bank s of eight registers (r0C r 7 ) . t w o b i t s o n t h e program st a t u s word (psw ) sele c t whic h bank is i n use. th e nex t 1 6 bytes ( 0x20 - 0x2f) f o r m a b lock of bit-addressab l e memory spa c e at bit add r e s s e s 0h-7f h . all o f the byt e s in t h e lower 128 bytes a r e a ccessible through di r e c t or indirect a d dr e ssing.
ez-u s b s er i e s 2 1 0 0 t rm v 1.8 a p p e n d ix b: 8 0 5 1 a r c hi t e c t u r al o v e r v i e b - 3 the sfrs occupy addr e sse s 80hCffh a n d are on l y a ccessible throug h direct a ddressing. most s f r s a r e res e rved fo r specific funct i ons as d escribed in t he spec i a l function register s on page b-13. s f r addre s ses ending in 0h or 8h are b i t-addre s sable. b.1. 2 instruction set all 8051 in s tru c t ions are binar y code compatible and p e rfo r m the same functions as they do with the industr y st a nd a rd 8051. th e effec t s of t h ese instructions on bit s , flags, a nd other sta- tus functi o n s is identical to the industry standard 8051. ho w ever, the timing of the instruc- tions is d i ff e re n t, both in terms of number of clock cycles per in s tru c t ion cycle and timing within the in s tru c t ion cycle. figure b-2 lists the 8051 in s tructi o n set and the number of instruction cyc l es required to com- plete e ach i n struct i o n . ta b le b-1 defines the symbols and mnemonics used i n t a ble b-2. f i g u r e b - 2. i n t e r nal r a m or g a nization 00h f f h 7fh 80h l o w e r 128 b y t e s upp e r 128 by t e s ( o p ti o n a l) s f r s p ace f f h 80h l o w er 1 2 8 bytes 00h b a nk 0 0 7 h 0 8 h b a nk 1 0fh 10h b a nk 2 b a nk 3 17h 18h 1 f h 2 0 h 2fh 30h 7 f h 0 0 07 7 8 7f . . . . . . . . . b i t - a dd r e s s a b l e r e g i s t ers dir e c t r a m d i re c t o r i n d i r e c t a d d r e ssing i n d i r e c t a dd r e s s i ng on ly d ire c t a d dr e ss i n g only 00 01 10 11 b a nk s e l e ct (p s w bi t s 4, 3 )
b - 4 appendix b: 8051 architectural overvie ez-usb series 2100 trm v1.8 table b-1. legend for instruction set table symbol function a accumulator rn register r7Cr0 direct internal register address @ri internal register pointed to by r0 or r1 (except movx) rel twos complement offset byte bit direct bit address #data 8-bit constant #data 16 16-bit constant addr 16 16-bit destination address addr 11 11-bit destination address
ez-usb series 2100 trm v1.8 appendix b: 8051 architectural overvie b - 5 table b-2. 8051 instruction set mnemonic description byte instr. cycles hex code arithmetic add a, rn add register to a 1 1 28-2f add a, direct add direct byte to a 2 2 25 add a, @ri add data memory to a 1 1 26-27 addc a, #data add immediate to a 2 2 24 addc a, rn add register to a with carry 1 1 38-3f addc a, direct add direct byte to a with carry 2 2 35 addc a, @ri add data memory to a with carry 1 1 36-37 addc a, #data add immediate to a with carry 2 2 34 subb a, rn subtract register from a with borrow 1 1 98-9f subb a, direct subtract direct byte from a with bor- row 22 95 subb a, @ri subtract data memory from a with borrow 1 1 96-97 subb a, #data subtract immediate from a with bor- row 22 94 inc a increment a 1 1 04 inc rn increment register 1 1 08-0f inc direct increment direct byte 2 2 05 inc @ ri increment data memory 1 1 06-07 dec a decrement a 1 1 14 dec rn decrement register 1 1 18-1f dec direct decrement direct byte 2 2 15 dec @ri decrement data memory 1 1 16-17
b - 6 appendix b: 8051 architectural overvie ez-usb series 2100 trm v1.8 inc dptr increment data pointer 1 3 a3 mul ab multiply a by b 1 5 a4 div ab divide a by b 1 5 84 da a decimal adjust a 1 1 d4 logical anl, rn and register to a 1 1 58-5f anl a, direct and direct byte to a 2 2 55 anl a, @ri and data memory to a 1 1 56-57 anl a, #data and immediate to a 2 2 54 anl direct, a and a to direct byte 2 2 52 anl direct, #data and immediate data to direct byte 3 3 53 orl a, rn or register to a 1 1 48-4f orl a, direct or direct byte to a 2 2 45 orl a, @ri or data memory to a 1 1 46-47 orl a, #data or immediate to a 2 2 44 orl direct, a or a to direct byte 2 2 42 orl direct, #data or immediate data to direct byte 3 3 43 xorl a, rn exclusive-or register to a 1 1 68-6f xorl a, direct exclusive-or direct byte to a 2 2 65 xorl a, @ri exclusive-or data memory to a 1 1 66-67 xorl a, #data exclusive-or immediate to a 2 2 64 xorl direct, a exclusive-or a to direct byte 2 2 62 xorl direct, #data exclusive-or immediate data to direct byte 33 63 table b-2. 8051 instruction set mnemonic description byte instr. cycles hex code
ez-usb series 2100 trm v1.8 appendix b: 8051 architectural overvie b - 7 clr a clear a 1 1 e4 cpl a complement a 1 1 f4 swap a swap nibbles of a 1 1 c4 rl a rotate a left 1 1 23 rlc a rotate a left through carry 1 1 33 rra rotate a right 1 1 03 rrc a rotate a right thr ough carry 1 1 13 data transfer mov a, rn move register to a 1 1 e8-ef mov a, direct move direct byte to a 2 2 e5 mov a, @ri move data memory to a 1 1 e6-e7 mov a, #data move immediate to a 2 2 74 mov rn, a move a to register 1 1 f8-ff mov rn, direct move direct byte to register 2 2 a8-af mov rn, #data move immediate to register 2 2 78-7f mov direct, a move a to direct byte 2 2 f5 mov direct, rn move register to direct byte 2 2 88-8f mov direct, direct move direct byte to direct byte 3 3 85 mov direct, @ri move data memory to direct byte 2 2 86-87 mov direct, #data move immediate to direct byte 3 3 75 mov @ri, a mov a to data memory 1 1 f6-f7 mov @ri, direct move direct byte to data memory 2 2 a6-a7 mov @ri, #data move immediate to data memory 2 2 76-77 mov dptr, #data move immediate to data pointer 3 3 90 table b-2. 8051 instruction set mnemonic description byte instr. cycles hex code
b - 8 appendix b: 8051 architectural overvie ez-usb series 2100 trm v1.8 movc a, @a+dptr move code byte relative dptr to a 1 3 93 movc a, @a+pc move code byte relative pc to a 1 3 83 movx a, @ri move external data (a8) to a 1 2-9* e2-e3 movx a, @dptr move external data (a16) to a 1 2-9* e0 movx @ri, a move a to external data (a8) 1 2-9* f2-f3 movx @dptr, a move a to external data (a16) 1 2-9* f0 push direct push direct byte onto stack 2 2 c0 pop direct pop direct byte from stack 2 2 d0 xch a, rn exchange a and register 1 1 c8-cf xch a, direct exchange a and direct byte 2 2 c5 xch a, @ri exchange a and data memory 1 1 c6-c7 xchd a, @ri exchange a and data memory nibble 1 1 d6-d7 * number of cycles is user-selectable. see stretch memory cycles (wait states) on page b-11 . boolean clr c clear carry 1 1 c3 clr bit clear direct bit 2 2 c2 setb c set carry 1 1 d3 setb bit set direct bit 2 2 d2 cpl c complement carry 1 1 b3 cpl bit complement direct bit 2 2 b2 anl c, bit and direct bit to carry 2 2 82 table b-2. 8051 instruction set mnemonic description byte instr. cycles hex code
ez-usb series 2100 trm v1.8 appendix b: 8051 architectural overvie b - 9 anl c, /bit and direct bit inverse to carry 2 2 b0 orl c, bit or direct bit to carry 2 2 72 orl c, /bit or direct bit inverse to carry 2 2 a0 mov c, bit move direct bit to carry 2 2 a2 mov bit, c move carry to direct bit 2 2 92 branching acall addr 11 absolute call to subroutine 2 3 11-f1 lcall addr 16 long call to subroutine 3 4 12 ret return from subroutine 1 4 22 reti return from interrupt 1 4 32 ajmp addr 11 absolute jump unconditional 2 3 01-e1 ljmp addr 16 long jump unconditional 3 4 02 sjmp rel short jump (relative address) 2 3 80 jc rel jump on carry = 1 2 3 40 jnc rel jump on carry = 0 2 3 50 jb bit, rel jump on direct bit = 1 3 4 20 jnb bit, rel jump on direct bit = 0 3 4 30 jbc bit, rel jump on direct bit = 1 and clear 3 4 10 jmp @ a+dptr jump indirect relative dptr 1 3 73 jz rel jump on accumulator = 0 2 3 60 jnz rel jump on accumulator /= 0 2 3 70 cjne a, direct, rel compare a, direct jne relative 3 4 b5 cjne a, #d, rel compare a, immediate jne relative 3 4 b4 cjne rn, #d, rel compare reg, immediate jne rela- tive 3 4 b8-bf table b-2. 8051 instruction set mnemonic description byte instr. cycles hex code
b - 10 a p p e n d ix b : 8 0 51 a r c hi t e ct u ral o v e r vie e z - u s b s e r i e s 2 1 00 t r m v1 . 8 b.1. 3 instruction t i ming in s tru c t ion cycles in the 8051 co r e are 4 clock cycles in l ength, a s opposed to the 12 clock cycles per instruction c y c l e in the standard 8051. t h is transla t es to a 3x improvement i n execu- tion time for most instructions. so m e instructions requ i r e a di f f e rent num b e r of instruction cyc l e s on th e 8051 c o r e than the y do on the standard 8051. in the standard 8051, all instruct i ons except fo r mul an d div t ake one or two inst r uct i o n cycles t o comple t e . i n the 8051 core, inst r uctions c a n t a ke between one a n d five instruction cycl e s to complete. fo r example, in the stand a rd 8051, the i n s truction s movx a, @dptr and mov direct, direct e a ch take 2 in s truction cycl e s (24 clock cycl e s ) to execute. in the 8051 core, movx a, @dptr takes two instruction cycles (8 clock cyc l es) an d mov direct, direct takes th r ee instruction cycl e s (1 2 clock c y c l es). both instruction s e xecut e faste r o n th e 805 1 cor e than they do on the standard 8051, bu t requi r e di f ferent num b e rs of clock cyc l es. fo r t i mi n g o f r e al-time ev e nts, use the num b ers of instruct i on cyc l es from tabl e b-1 t o calcu- late the timing o f software l oop s . the bytes column i ndicates the numbe r o f memory accesses (byte s ) needed to execute t he instruction. in mo s t cases, the number of bytes is equal to the number of instruction cycle s re q u ired to complete the i n struct i on. how e v e r, as ind i c ated, t h ere are some in s t ructions (for example , div and mul ) that require a greater number of i n str u c tion cycles than memory a c c e sses. cj n e @ ri, #d, re l compare ind, immedia t e jn e rela- tive 3 4 b6-b7 djnz rn, r el decrement reg i s t e r , jn z r elative 2 3 d8 - d f djnz direc t , rel decrement direct byte, jnz relative 3 4 d5 mis c ellaneous nop no operation 1 1 00 there is an additi o n a l r e served opcode ( a 5 ) that pe r f o rms the same func t i o n as nop. all mnemonics are c o p y righted. intel corporation 1980. t a b l e b - 2 . 8 05 1 i n st r u c t i on set mnemonic d escription byte inst r . cycles hex code
ez-u s b s er i e s 2 1 0 0 t rm v 1.8 a p p e n d ix b: 8 0 5 1 a r c hi t e c t u r al o v e r v i e b - 1 1 by d e fa u lt, the 8051 c o re t i mer/counters run at 12 clock cycles per i n c re m ent so that timer- based events have the same t i ming as with the sta n d ard 8051. the t i mers can also be config- u r ed to run at 4 clock cycles per increment to take advantag e of the higher sp e ed of the 8051 core. b.1. 4 cpu t iming as previously stated, an 8051 core instruction cycle con s i sts of 4 clk24 cycle s . eac h clk24 cycle forms a c pu cy c l e . therefo r e , an in s t ruction cycle consists of 4 cpu cycles: c 1 , c2, c3, and c4, as illustrated in f i gure b-3. v a r ious events occu r in each cpu cycle, depending on the type of in s tru c t ion being e x ecuted. t h e labe l s c 1, c2, c3, and c4 in tim i n g descrip- tions refer to the 4 cpu cycles within a p a rtic u l ar ins t r uction cycle. the exec u tion for i n str u c tion n is perf o rme d during the fet c h of instructio n n +1. d a t a writes occur during fetc h of instructio n n +2. the lev e l sensitive interr u p t s a r e s ampled with t h e ris- ing edge of clk24 at the end o f c3. b.1. 5 s t r e t c h m emor y cycles ( w a i t s tates) the stretch memory cycle f e atu r e enabl e s appl i cation software to adjust the speed of data memory a c cess. the 8051 core can execute th e movx in s tru c t ion in as few as 2 in s truction cycle s . howeve r , it is someti m e s de s i ra b l e t o stretch this value; f or e x am p le to access slow memory o r slow memory-mapped per i p h erals s u ch a s uarts or lcds. the thre e l s bs o f the cl o c k c o n trol reg i st e r (a t s f r lo c a tion 8 e h ) control t h e stretc h v a lue. y ou c an u se s t retch values be t w een z ero a n d seve n . a stretch v a lue of zero adds zero instruc- tion cycl e s, resultin g i n movx in s tructi o n s executing in tw o i n struction c ycles. a stret c h value o f seven adds seven i n str u c tion cycl e s , r esulting in movx instructions executing in nine instruction cycl e s. t h e s tretch value can be changed dynamic a lly under program control. f i g u r e b- 3 . c p u tim i ng f o r s i n g le - c y c le in s t r u ct i o n c lk 2 4 i n s t r u c t ion c y c l e c p u c y c l e n + 1 n + 2 c1 c2 c3 c4 c1 c 2 c3 c4 c 1
b - 12 a p p e n d ix b : 8 0 51 a r c hi t e ct u ral o v e r vie e z - u s b s e r i e s 2 1 00 t r m v1 . 8 by d e fa u l t , the stretch value r esets t o one (three cycl e movx ) . for fu l l-sp e ed data memory a c c e ss, the software m u s t set the stre t ch value to zero. the stretc h value af f e cts only data memory a c cess (not pr o g ram memory). the stretch value a ffe c ts the width of th e r ead/w r ite strobe and a ll r e lated timing. using a highe r stretch value resu l t s in a wider r e ad/wr i te strobe, which allows t h e memory or periph- eral more time to respond. t able b-3 lists t he data memory a c c e ss sp e eds for stretch values zero through s e ven. md2C0 are the th r e e lsbs o f the c lock control regist e r ( c kcon . 2C0 ) . b.1. 6 dual data poi n ters the 8051core e mploys dual data point e r s to a ccelerate data memo r y block m o v es. the stan- dard 8051 data pointe r ( d p t r ) is a 16-bit value used to add r ess external data r a m o r periph- erals. the 8051 maintains the s t andard data poi n t e r as d p tr0 a t s f r locati o n s 82h (dpl0) and 83h (d p h0). it is not n e ce s sary to modify ex i sting code t o u s e dptr0. the 8051 co r e adds a s e cond data po i n t e r (dptr1) a t sfr l o cati o n s 84h (d p l1) and 85h ( dph1) . t h e s e l b i t in the d p tr selec t regist e r, d p s (sf r 86h), sel e cts the activ e pointer. when s e l = 0, in s tru c tions that use the d p tr will use dpl0 and d p h0. when se l = 1, instructions t h at u s e the d ptr will use dpl1 and dph 1 . sel is the bit 0 of sfr location 86h. no other bits of sfr loca t ion 86h are used. t ab l e b - 3 . d at a memo r y s t r e t c h va lu e s md2 md1 md0 m emory cycles read / write strobe w idth ( c l ocks) strobe w idth @ 24mhz 0002 2 83.3 ns 001 3 ( d e f a u l t ) 4 166.7 ns 0104 8 333.3 ns 0115 1 2 500 ns 1006 1 6 666.7 ns 1017 2 0 833.3 ns 1108 2 4 1000 ns 1119 2 8 1 166.7 ns
ez-u s b s er i e s 2 1 0 0 t rm v 1.8 a p p e n d ix b: 8 0 5 1 a r c hi t e c t u r al o v e r v i e b - 1 3 all d p tr-r e lated i nstructions use the cu r rently selected data poi n ter. to switch t he active pointe r , toggle the s e l bit. the fas t est way to do so i s to use t he increment i nstruction ( inc dps ) . this r equ i res only one instruction to switc h from a s o u r c e addre s s to a d estination addres s , saving applicati o n code from having to save sou r ce and destin a ti o n addresses when doing a block move. using dual data pointers provid e s significant l y i n crea s ed efficiency whe n moving large blocks of data. the sfr lo c ati o n s related to the dual data pointers a r e: 82h dpl0 d p t r0 low byte 83h dph0 d p t r0 high byte 84h dpl1 d p t r1 low byte 85h dph1 d p t r1 high byte 86h dps d p t r select ( b i t 0) b.1. 7 s p e c ial f u n c tion regist e r s the special function register s (sfrs ) cont r o l severa l o f th e featur e s of the 8051. mo s t of the 8051 core s f r s a r e identical to the standar d 805 1 s f r s . h o w e v e r , t h e r e a r e a d d it ional sfrs that control features that a re not a v a i lable in t h e s tandard 8051. t able b-4 l i sts the 8051 c o re s f rs and indic a te s which sfrs ar e not included in t h e standard 8051 sfr sp a ce. in t able b-5, sfr bit p o sitions that contain a 0 or a 1 cannot be w ritten to and, when read, always r eturn th e value shown (0 o r 1). s fr bi t positions tha t contain - ar e availabl e but not used. t ab l e b-5 l i sts t he re s et values for t he s frs. the fo l lowing sfr s a re r e lated to cpu operation and program execution: 81h sp s t a ck pointer d0h psw program status w ord () e0h a c c accumulator register f0h b b regis t e r t able b-6 li s ts the f u n ctions of t he bits in the psw sf r . detailed d e scriptions o f the remain- ing sfrs app e a r wi t h the associat e d ha r d ware d e scriptions in append i x c.
b - 14 appendix b: 8051 architectural overvie ez-usb series 2100 trm v1.8 table b-4. special function registers register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 addr sp 81h dpl0 82h dph0 83h dpl1 (1) 84h dph1 (1) 85h dps (1) 0000 000sel86h pcon smod 0 - 1 1 gf1 gf0 stop idle 87h tcon tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 88h tmod gate c/t m1 m0 gate c/t m1 m0 89h tl0 8ah tl1 8bh th0 8ch th1 8dh ckcon (1) - - t2m t1m t0m md2 md1 md0 8eh spc_fnc (1 ) 0000 000wrs8fh exif (1) ie5 ie4 i2cin t usbin t 100091h mpage (1) 92h scon0 sm0_ 0 sm1_ 0 sm2_ 0 ren_0 tb8_0 rb8_0 ti_0 ri_0 98h sbuf0 99h ie ea es1 et2 es0 et1 ex1 et0 ex0 a8h ip 1 ps1 pt2 ps0 pt1 px1 pt0 px0 b8h scon1 (1) sm0_ 1 sm1_ 1 sm2_ 1 ren_1 tb8_1 rb8_1 ti_1 ri_1 c0h
ez-usb series 2100 trm v1.8 appendix b: 8051 architectural overvie b - 15 sbuf1 (1) c1h t2con tf2 exf2 rclk tclk exen 2 tr2 c/t2 cp/ rl2 c8h rcap2l cah rcap2h cbh tl cch th2 cdh psw cy ac f0 rs1 rs0 ov f1 p d0h eicon (1) smod 1 1eresiresiint6000d8h acc e0h eie (1) 111ewdiex5ex4ei2ceusbe8h b f0h eip (1) 111px6px5px4pi2cpusbf8h (1) not part of standard 8051 architecture. table b-4. special function registers register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 addr
b - 16 appendix b: 8051 architectural overvie ez-usb series 2100 trm v1.8 table b-5. special function register reset value register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 addr sp 0000011181h dpl00000000082h dph00000000083h dpl1 (1) 0000000084h dph1 (1) 0000000085h dps (1) 0000000086h pcon0011000087h tcon0000000088h tmod0000000089h tl0 000000008ah tl1 000000008bh th0 000000008ch th1 000000008dh ckcon (1) 000000018eh spc_fnc (1 ) 000000008fh exif (1) 0000100091h mpage (1) 0000000092h scon00000000098h sbuf00000000099h ie 00000000a8h ip 10000000b8h scon1 (1) 00000000c0h sbuf1 (1) 00000000c1h t2con00000000c8h rcap2l00000000cah
ez-usb series 2100 trm v1.8 appendix b: 8051 architectural overvie b - 17 rcap2h00000000cbh tl 00000000cch th2 00000000cdh psw 00000000d0h eicon (1) 01000000d8h acc 00000000e0h eie (1) 11100000e8h b 00000000f0h eip (1) 11100000f8h (1) not part of standard 8051 architecture. table b-5. special function register reset value register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 addr
b - 18 appendix b: 8051 architectural overvie ez-usb series 2100 trm v1.8 table b-6. psw register - sfr d0h bit function psw.7 cy - carry flag. this is the unsigned carry bit. the cy flag is set when an arithmetic operation results in a carry from bit 7 to bit 8, and cleared otherwise. in other words, it acts as a virtual bit 8. the cy flag is cleared on multiplication and division. psw.6 ac - auxiliary carry flag. set to 1 when the last arithmetic operation resulted in a carry into (during addition) or borrow from (during subtraction) the high order nibble, otherwise cleared to 0 by all arith- metic operations. psw.5 f0 - user flag 0. bit-addressable, general purpose flag for software control. psw.4 rs1 - register bank select bit 1. used with rs0 to select a register bank in internal ram. psw.3 rs0 - register bank select bit 0, decoded as: rs1 rs0 banks selected 0 0 register bank 0, addresses 00h-07h 0 1 register bank 1, addresses 08h-0fh 1 0 register bank 2, addresses 10h-17h 1 1 register bank 3, addresses 18h-1fh psw.2 ov - overflow flag. this is the signed carry bit. the ov flag is set when a positive sum exceeds 7fh, or a negative sum (in twos c ompliment notation) exceeds 80h. on a multiply, if ov = 1, the result of the multiply is greater than ffh. on a divide, ov = 1 on a divide by 0. psw.1 f1 - user flag 1. bit-addressable, general purpose flag for software control. psw.0 p - parity flag. set to 1 when the modulo-2 sum of the 8 bits in the accumulator is 1 (odd parity), cleared to 0 on even parity.
ez-usb series 2100 trm v1.8 appendix c: 8051 hardware description c - 1 appendix c: 8051 hardware description this chapter provides technical data about the 8051 core hardware operation and timing. the topics are: ? timers/counters ? serial interface ? interrupts ? reset ? power saving modes the 8051 core includes three timer/counters (timer 0, timer 1, and timer 2). each timer/ counter can operate as either a timer with a clock rate based on the clk24 pin, or as an event counter clocked by the t0 pin (timer 0), t1 pin (timer 1), or the t2 pin (timer 2). each timer/counter consists of a 16-bit register that is accessible to software as two sfrs: ? timer 0 - tl0 and th0 ? timer 1 - tl1 and th1 ? timer 2 - tl2 and th2 c.1 introduction c.2 timers/counters
c - 2 a p p e n d ix c : 8 0 5 1 h a r d w a r e d e scr i p t i on e z - u s b s e r i es 2 1 0 0 t rm v 1 . 8 c.2. 1 803x/805x compa t ibility t h e i m p l e m e n t a t i o n o f t h e t i m e r s / coun t e rs i s similar to that of t he dallas semiconductor ds80c320. t able c-1 summarizes the di f fe r ences in timer/ c ounter implemen t a t ion between the intel 8051, the dall a s semiconductor ds80c 320, and the 8051 core. c.2. 2 t imers 0 and 1 t i m e r s 0 and 1 each operate in four m ode s , as controlled th r ough t he tmo d sfr ( t able c- 2) and the tc o n sf r ( table c-3). t he four m odes are: ? 13-bi t t i m er/counter (mode 0) ? 16-bi t t i m er/counter (mode 1) ? 8-bit counter with auto-reload (mode 2) ? t wo 8-bit count e rs (mode 3 , timer 0 only) c.2.2.1 mode 0 mode 0 operation, i l lustrated in figur e c-1, is th e same fo r timer 0 a nd timer 1. in mode 0, the timer is conf i gured as a 13 - bit counter that uses bits 0-4 of tl0 ( or tl1) and all 8 bits of t a b le c- 1. t i m e r/ c o u n t er i m pl e men t at i on c o m pa r i s o n feature intel 8051 dallas ds80c320 8051 numb e r o f t i m e rs 2 3 3 t imer 0/1 o v erflow available a s output sig- n a ls not i m p le- men t ed not i m p le- men t ed t0o u t, t1out (one clk24 pulse) t imer 2 output enable n/a imple- men t ed not i m p lemented t imer 2 downcount enable n/a imple- men t ed not i m p lemented t imer 2 o v erflow av a il- able as output signal n/a imple- men t ed t2out (one clk24 pulse)
e z - u s b s e r i e s 2 1 00 t rm v 1 . 8 a p p e n d ix c : 8 0 5 1 h a r d w a r e d e scr i p t i on c - 3 t h0 (or t h1). th e timer enabl e bi t (tr0/tr1) in t h e tc o n sf r start s th e time r . th e c / t bit s e l e c t s t h e t i m e r / c oun t e r clock source, clk24 o r t h e t0/t 1 pins . the timer counts transitions from t h e select e d s ource as l on g a s t h e g a t e b i t i s 0 , o r the g a te bit is 1 and the c orresponding interrupt p i n (in t 0# or int1# ) is 1. when the 13-bit count i n c reme n t s from 1f f f h (all o n es), the counter r o lls over to all zeros, the tf0 (o r t f1) bi t i s set in the t c o n sfr, a nd th e t0out (or t1out) pin goes high for one c l o ck cy c l e . the upper 3 bits o f tl0 ( o r tl1) are i nde t erminate in mode 0 and must be masked when the software evaluates the register c.2.2.2 mode 1 mode 1 op e r a tion is the same fo r time r 0 a nd timer 1. i n mode 1, th e t i m er is configured as a 16-bit count e r. as il l u s t rated i n figure c-1, all 8 b i ts of the lsb r e g i ster (tl0 o r tl1) are used. the count e r r o lls over to a l l ze r os when the count increments f rom ffffh. otherwise, mode 1 operation is t h e same as mode 0. f i gu r e c- 1 . t i m e r 0 / 1 - m od e s 0 an d 1 t l0 ( o r t l 1) 0 7 4 d i v i de by 1 2 d i v i d e b y 4 c l k 2 4 t0 (o r t 1 ) p in t r 0 ( o r t r 1 ) g a t e int 0 # p in ( o r i n t 1 # ) 7 0 t f 0 ( o r t f 1 ) i n t th0 ( o r t h 1 ) t 0 m ( o r t 1 m ) m o de 0 m o d e 1 0 1 0 1 t o s e r i a l p o r t ( t i me r 1 o n l y ) c l k c / t
c - 4 a p p e n d ix c : 8 0 5 1 h a r d w a r e d e scr i p t i on e z - u s b s e r i es 2 1 0 0 t rm v 1 . 8 t a b l e c- 2 . t mod r e gi s t e r - s f r 8 9 h bit function tmod . 7 g a t e - t i m e r 1 gate cont r ol. whe n g ate = 1, t imer 1 will clock only when int1# = 1 and tr1 (tcon. 6 ) = 1. when g a te = 0 , timer 1 will c loc k only when tr1 = 1, r e gardle s s of the s t ate of int1#. tmod . 6 - counter / t imer sele c t. when = 0 , t imer 1 is clocked by clk24/4 o r clk24/12, depending on the s tat e o f t 1m (ckcon. 4 ). when = 1, t imer 1 i s clocked by t h e t1 pin. tmod . 5 m1 - t imer 1 mode select bit 1. tmod . 4 m0 - t imer 1 mode select bit 0, decoded as: m 1 m0 m o d e 0 0 mod e 0 : 13 - bit c ount e r 0 1 mod e 1 : 16 - bit c ount e r 1 0 mod e 2 : 8 - bit c o u n ter w i th a u to - re l o a d 1 1 mod e 3 : t i me r 1 st o p p e d tmod . 3 g a t e - t i m e r 0 gate cont r ol, whe n g ate = 1, t imer 0 will clock only when int0 = 1 and tr0 (tcon. 4 ) = 1. when g a te = 0 , timer 0 will c loc k only when tr0 = 1, r e gardle s s of the s t ate of int0. tmod . 2 - counter / t imer sele c t. when = 0, t imer 0 is clocked by clk24/4 o r clk24/12, depending on the s tat e o f t 0m (ckcon. 3 ). when = 1, t imer 0 i s clocked by t h e t0 pin. tmod . 1 m1 - t imer 0 mode select bit 1. tmod . 0 m0 - t imer 0 mode select bit 0, decoded as: m 1 m0 m o d e 0 0 mod e 0 : 13 - bit c ount e r 0 1 mod e 1 : 16 - bit c ount e r 1 0 mod e 2 : 8 - bit c o u n ter w i th a u to - re l o a d 1 1 mod e 3 : t w o 8-bi t co u n te r s c / t c / t c / t c / t c / t c / t
ez-usb series 2100 trm v1.8 appendix c: 8051 hardware description c - 5 table c-3. tcon register - srf 88h bit function tcon.7 tf1 - timer 1 overflow flag. set to 1 when the timer 1 count overflows and cleared when the processor vectors to the interrupt service routine. tcon.6 tr1 - timer 1 run control. set to 1 to enable counting on timer 1. tcon.5 tf0 - timer 0 overflow flag. set to 1 when the timer 0 count overflows and cleared when the processor vectors to the interrupt service routine. tcon.4 tr0 - timer 0 run control. set to 1 to enable counting on timer 0. tcon.3 ie1 - interrupt 1 edge detect. if external interrupt 1 is configured to be edge-sensitive (it1 = 1), ie1 is set by hardware when a negative edge is detected on the int1 pin and is automatically cleared when the cpu vectors to the correspond- ing interrupt service routine. in this case, ie1 can also be cleared by software. if external interrupt 1 is configured to be level-sensitive (it1 = 0), ie1 is set when the int1# pin is 0 and cleared when the int1# pin is 1. in level-sensitive mode, software cannot write to ie1. tcon.2 it1 - interrupt 1 type select. int1 is detected on falling edge when it1 = 1; int1 is detected as a low level when it1 = 0. tcon.1 ie0 - interrupt 0 edge detect. if external interrupt 0 is configured to be edge-sensitive (it0 = 1), ie0 is set by hardware when a negative edge is detected on the int0 pin and is automatically cleared when the cpu vectors to the correspond- ing interrupt service routine. in this case, ie0 can also be cleared by software. if external interrupt 0 is configured to be level-sensitive (it0 = 0), ie0 is set when the int0# pin is 0 and cleared when the int0# pin is 1. in level-sensitive mode, software cannot write to ie0.
c - 6 a p p e n d ix c : 8 0 5 1 h a r d w a r e d e scr i p t i on e z - u s b s e r i es 2 1 0 0 t rm v 1 . 8 c.2.2.3 mode 2 mode 2 operat i o n is the s a me f o r t i mer 0 a nd t i mer 1. in mode 2, the t imer is configured as an 8-bit cou n t er, with au t o m a t ic relo a d of t h e s t art value . t h e l sb regi s t er (tl0 or tl1) is the c ount e r and the msb register (th0 or t h 1) sto r es t h e reload value. as ill u s t r a ted i n figure c-2, mode 2 counter con t rol i s the sa m e a s f o r mode 0 and mode 1. howeve r , in mode 2, whe n t l n in c r ements f ro m f fh, t h e valu e store d i n t h n is reloaded into t l n . tcon.0 it0 - in t e r rupt 0 type s elect. int0 is detected on falling edge wh e n it0 = 1; int0 is det e c t e d as a low l evel when it0 = 0. f i g u re c - 2 . t i mer 0 / 1 - m o de 2 t a b l e c - 3 . t c on r e g i ster - s rf 88h b i t function t l 0 ( o r t l 1 ) 0 7 d i v i de by 1 2 d i v i d e b y 4 t 0 ( o r t 1 ) p i n tr0 ( o r tr 1 ) g a t e int0# p i n (o r int 1 # p i n ) 7 0 t f 0 (or t f 1) t h 0 ( o r th 1 ) t 0m ( o r t 1 m ) re l oad int 0 1 0 1 t o s e r i a l p o rt ( t i m e r 1 o n l y ) c l k 2 4 c l k c / t
e z - u s b s e r i e s 2 1 00 t rm v 1 . 8 a p p e n d ix c : 8 0 5 1 h a r d w a r e d e scr i p t i on c - 7 c.2.2.4 mode 3 in mode 3, t imer 0 operates as two 8-bit count e rs a nd tim e r 1 s t ops counting a nd holds its value. as shown in fi g u r e c-3, tl 0 is configure d as an 8-bit counte r control l ed by the normal t i m e r 0 control bits. tl0 can either count clk2 4 cycles (divided by 4 or by 12) or high-to- low transitions on t 0 , as det e r mined by the c/t bit. th e g ate funct i on can be used to give counter en a b le control to t h e int0# pin. t h0 fun c tions a s an independent 8-b i t counte r . howeve r , th0 can only coun t clk24 cycles (divided by 4 or by 12) . t h e timer 1 control and fl a g b its ( t r1 and tf1) are u sed as the con- trol and flag b i t s for th0. when t imer 0 is in mode 3 , timer 1 has l imited u s a ge beca u se t i mer 0 uses the timer 1 con- trol bi t ( t r1) and interrupt f lag ( t f1). t ime r 1 can still be used f o r baud rate generation and the t imer 1 count valu e s a re still available in the tl1 a nd th1 re g i sters. control of t imer 1 whe n time r 0 is in mode 3 i s through t h e timer 1 mode bits. t o turn t i m e r 1 on, se t timer 1 to mode 0, 1, or 2. t o turn t imer 1 off, s e t it to mode 3. t he t imer 1 c/t bi t an d t1 m b it are still availa b le to time r 1 . there f ore , t imer 1 c a n coun t clk24/4, clk24/12, or high- t o-low transitions on the t1 pin. the t imer 1 g ate funct i o n i s also available whe n timer 0 is in m o d e 3. f i g u r e c-3. ti m e r 0 - m o d e 3 t l 0 0 7 d i v i d e by 1 2 d i v i d e b y 4 t0 pin tr0 g a t e int 0 # p in 7 0 t f 0 th0 t 0 m int tr1 tf1 int 0 1 0 1 c l k 2 4 c l k c / t
c - 8 a p p e n d ix c : 8 0 5 1 h a r d w a r e d e scr i p t i on e z - u s b s e r i es 2 1 0 0 t rm v 1 . 8 c.2. 3 t imer r a te co n trol the default timer clock scheme for the 8051 t ime r s is 12 clk24 cy c les pe r increment, the same a s in t h e standard 8051. howe v er, in the 8051, the i nstruction cy c le is 4 clk24 cy c les. using the default rate ( 1 2 clocks per timer i ncreme n t) al l ows existing a p p lication code with r e al - time dependenc i es, such as b a u d r a te, to operate prop e rly. how e ver, applications that r equ i re fa s t timi n g can s e t t he t i mers to increment every 4 clk2 4 cycles by setting bits in the clock control r egister (ck c o n ) at sfr location 8 e h (s e e tabl e c-4.). the ck c on b i ts that control t he timer clock rates are: ckcon bi t coun t e r / t imer 5 t i m e r 2 4 t i m e r 1 3 t i m e r 0 when a c kco n r e g i ster b i t is set t o 1 , the associated counter inc r eme n t s at 4-c l k 2 4 inter- vals. when a c kcon bi t is clear e d , th e associated counter i ncreme n ts at 12-clk2 4 intervals. the ti m er contro l s are independen t of eac h other. the d e fault s etting f o r a l l three timers is 0 (12-clk24 intervals ) . t hese bits have no e f fect in counter mode. t ab l e c - 4 . c k c o n re g i st e r - s rf 8 eh bit function c kcon.7,6 r es e rved c kcon.5 t2m - t imer 2 clock select. when t 2m = 0, t imer 2 u s e s clk24 / 12 (for compatibility with 80c32 ) ; when t2m = 1, t imer 2 u se s clk24/4. this bit has no e f f e ct wh e n timer 2 is conf i gured for baud rate gen e r ation. c kcon.4 t1m - t imer 1 clock select. when t 1m = 0, t imer 1 u s e s clk24 / 12 (for compatibility with 80c32 ) ; when t1m = 1, t imer 1 u se s clk24/4. c kcon.3 t0m - t imer 0 clock select. when t 0m = 0, t imer 0 u s e s clk24 / 12 (for compatibility with 80c32 ) ; when t0m = 1, t imer 0 u se s clk24/4. c kcon.2-0 m d2, md1, m d0 - control the number of cycles to be u sed for e x t ernal movx instructions.
ez-usb series 2100 trm v1.8 appendix c: 8051 hardware description c - 9 c.2.4 timer 2 timer 2 runs only in 16-bit mode and offers several capabilities not available with timers 0 and 1. the modes available with timer 2 are: ? 16-bit timer/counter ? 16-bit timer with capture ? 16-bit auto-reload timer/counter ? baud rate generator the sfrs associated with timer 2 are: ? t2con - sfr c8h (table c-6.) ? rcap2l - sfr cah - used to capture the tl2 value when timer 2 is configured for capture mode, or as the lsb of the 16-bit reload value when timer 2 is configured for auto-reload mode. ? rcap2h - sfr cbh - used to capture the th2 value when timer 2 is configured for capture mode, or as the msb of the 16-bit reload value when timer 2 is configured for auto-reload mode. ? tl2 - sfr cch - lower 8 bits of the 16-bit count. ? th2 - sfr cdh - upper 8 bits of the 16-bit count.
c - 10 appendix c: 8051 hardware description ez-usb series 2100 trm v1.8 c.2.4.1 timer 2 mode control table c-5. summarizes how the sfr bits determine the timer 2 mode. c.2.5 16-bit timer/counter mode figure c-4. illustrates how timer 2 operates in timer/counter mode with the optional capture feature. the c/t2 bit determines whether the 16-bit counter counts clk24 cycles (divided by 4 or 12), or high-to-low transitions on the t2 pin. the tr2 bit enables the counter. when the count increments from ffffh, the tf2 flag is set, and the t2out pin goes high for one clk24 cycle. table c-5. timer 2 mode control summary rclk tclk cp/ rl 2 tr2 mode 0 0 1 1 16-bit timer/counter with cap- ture 0 0 0 1 16-bit timer/counter with auto- reload 1 x x 1 baud rate generator x 1 x 1 baud rate generator xxx 0 off x = dont care. table c-6. t2con register - sfr c8h bit function t2con.7 tf2 - timer 2 overflow flag. hardware will set tf2 when the timer 2 overflows from ffffh. tf2 must be cleared to 0 by the software. tf2 will only be set to a 1 if rclk and tclk are both cleared to 0. writing a 1 to tf2 forces a timer 2 interrupt if enabled. t2con.6 exf2 - timer 2 external flag. hardware will set exf2 when a reload or capture is caused by a high-to-low transition on the t2ex pin, and exen2 is set. exf2 must be cleared to 0 by the software. writing a 1 to exf2 forces a timer 2 interrupt if enabled.
ez-usb series 2100 trm v1.8 appendix c: 8051 hardware description c - 11 t2con.5 rclk - receive clock flag. determines whether timer 1 or timer 2 is used for serial port 0 timing of received data in serial mode 1 or 3. rclk =1 selects timer 2 overflow as the receive clock. rclk =0 selects timer 1 overflow as the receive clock. t2con.4 tclk - transmit clock flag. determines whether timer 1 or timer 2 is used for serial port 0 timing of transmit data in serial mode 1 or 3. rclk =1 selects timer 2 overflow as the transmit clock. rclk =0 selects timer 1 overflow as the transmit clock. t2con.3 exen2 - timer 2 external enable. exen2 = 1 enables capture or reload to occur as a result of a high-to-low transition on the t2ex pin, if timer 2 is not generating baud rates for the serial port. exen2 = 0 causes timer 2 to ignore all exter nal events on the t2ex pin. t2con.2 tr2 - timer 2 run control flag. tr2 = 1 starts timer 2. tr2 = 0 stops timer 2. t2con.1 c/t2 - counter/timer select. c/t2 = 0 selects a timer function for timer 2. c/t2 = 1 selects a counter of falling transitions on the t2 pin. when used as a timer, timer 2 runs at 4 clocks per tick or 12 clocks per tick as programmed by ckcon.5, in all modes except baud rate generator mode. when used in baud rate generator mode, timer 2 runs at 2 clocks per tick, independent of the state of ckcon.5. t2con.0 cp/rl2 - capture/reload flag. when cp/rl2 = 1, timer 2 captures occur on high-to-low transitions of the t2ex pin, if exen2 = 1. when cp/rl 2 = 0, auto-reloads occur when timer 2 overflows or when high-to-low transitions occur on the t2ex pin, if exen2 = 1. if either rclk or tclk is set to 1, cp/rl2 will not function and timer 2 will operate in auto-reload mode following each over- flow. table c-6. t2con register - sfr c8h bit function
c - 1 2 a p p e n d ix c : 8 0 5 1 h a r d w a r e d e scr i p t i on e z - u s b s e r i es 2 1 0 0 t rm v 1 . 8 c.2.5.1 6 - b i t ti mer/count e r m ode with c a pture the t imer 2 capt u re mode (fi g u r e c-4.) i s the s a m e as the 16-b i t t i m er/counter m ode, with the a ddit i on of t he ca p ture registers a n d cont r ol signals. the c p / r l2 bit i n the t2con sfr e n ables t h e capture feature. when cp / rl2 = 1, a high - to- low transition on the t2ex pin when e x e n2 = 1 cau s es t h e timer 2 value to be loaded into the c aptu r e registers rcap2l and r cap 2 h. c.2. 6 16 - b i t ti mer/count e r m ode with a u to-reload when cp/rl2 = 0, t imer 2 is configured for t h e auto - r eload mode il l u s t r ated in figu r e c-5. control of counter input is t h e same as for the other 16 - bit counter m o d es. when t he count inc r e ments f r o m fff f h, ti m er 2 sets the t f2 flag a n d the s ta r t ing value is re l o aded i nto tl2 and th2. the so f tware must preload the s t art i ng value into the r cap2l and rcap2 h reg i s- te r s. f i g u r e c- 4 . t i mer 2 - t i mer / c ou n t e r w i th c a p t u r e 0 7 d i v i d e b y 1 2 d i v i d e b y 4 c l k 2 4 t 2 p i n t r 2 c l k 7 0 e x f2 t 2 m i n t rc a p 2l t l 2 t h 2 rc a p 2h 8 15 8 15 e x e n 2 t 2 ex pin capture t f 2 0 1 0 1 c / t2
ez-usb series 2100 trm v1.8 appendix c: 8051 hardware description c - 13 when timer 2 is in auto-reload mode, a reload can be forced by a high-to-low transition on the t2ex pin, if enabled by exen2 = 1. c.2.7 baud rate generator mode setting either rclk or tclk to 1 configures timer 2 to generate baud rates for serial port 0 in serial mode 1 or 3. in baud rate generator mode, timer 2 functions in auto-reload mode. however, instead of setting the tf2 flag, the counter overflow is used to generate a shift clock for the serial port function. as in normal auto-reload mode, the overflow also causes the pre- loaded start value in the rcap2l and rcap2h registers to be reloaded into the tl2 and th2 registers. when either tclk = 1 or rclk = 1, timer 2 is forced into auto-reload operation, regardless of the state of the cp/rl2 bit. when operating as a baud rate generator, timer 2 does not set the tf2 bit. in this mode, a timer 2 interrupt can only be generated by a high-to-low transition on the t2ex pin setting the exf2 bit, and only if enabled by exen2 = 1. figure c-5. timer 2 - timer/counter with auto reload 0 7 divide by 12 divide by 4 clk24 t2 pin tr2 clk 7 0 exf2 t2m int rcap2l tl2 th2 rcap2h 8 15 8 15 exen2 t2ex pin tf2 0 10 1 c/ t2
c - 1 4 a p p e n d ix c : 8 0 5 1 h a r d w a r e d e scr i p t i on e z - u s b s e r i es 2 1 0 0 t rm v 1 . 8 the counter time base in baud rate g e nerat o r mode is clk24/ 2 . t o use an external clock sourc e , set c / t2 to 1 and apply the de s i r ed clock source to the t 2 pin. the 8051 co r e provid e s t wo s e r ial po r t s . s e r i al po r t 0 is identical in operation t o the s t andard 8051 s e r i a l por t . serial port 1 is identi c a l to s e r i al port 0, except tha t t i m er 2 cannot be used as the baud rate gene r a tor for serial port 1. e ach s e r i a l por t can operate in synchronou s or asynch r onous mode. in synchronous m ode, 8051 ge n e rat e s the s e rial clock and the serial port o p e rat e s in h a lf-duplex mode. in asynchro- nous mode, the s er i a l port operates in full-duplex mode. in all m odes , 8051 bu f fers r eceived data i n a holdin g registe r , en a b ling the u ar t t o r eceiv e a n incoming byt e before th e software has read the previous value. each s e r i a l por t can operate in one of four modes, as outli n ed in t ab l e c-7. f i g u re c- 6. t i m e r 2 - b aud r a te ge n e ra t o r m o d e c . 3 ser i al i nter f ace 0 7 d i v i d e by 2 t 2 p i n t r 2 7 0 e x f 2 ti m er 2 i nterrupt rc a p2l t l 2 th2 rc a p2h 8 15 8 15 e x en2 t 2 ex p i n d i v i d e by 2 ti m er 1 o v erf l o w d i v i d e b y 1 6 d i v i d e by 1 6 r x c l ock t x c l ock s m od1 r c lk tc l k 0 0 0 0 1 1 1 1 c l k c l k 2 4 c / t 2
e z - u s b s e r i e s 2 1 00 t rm v 1 . 8 a p p e n d ix c : 8 0 5 1 h a r d w a r e d e scr i p t i on c - 1 5 the sfrs associated with the serial ports are: ? s c o n 0 - s f r 98h - s e r i al p o rt 0 control ( t able c-8). ? s b uf0 - sfr 99h - serial port 0 b u ff e r. ? scon 1 - s f r c0h - serial port 1 con t rol ( t able c-9). ? sbuf1 - sfr c 1 h - s e rial p o rt 1 b u f fer. c.3. 1 803x/805x compa t ibility the implementation of t h e seri a l i nterface is s i milar to that of the intel 8052. c.3. 2 mode 0 ser i al mode 0 provi d es synchronous, half-duplex s e r ial communication. f o r serial port 0, serial d a ta output o c cu r s on the r xd0out pin, s erial data is received on the rxd0 pin, and the t xd0 pin provides t he sh i f t clock for bot h t r a nsm i t and receive. f o r serial port 1, t h e cor- r e sponding pi n s are rxd 1 ou t , rxd1, and txd1. the s e r ial mode 0 baud rate is ei t her clk24 / 12 or clk24/4, depending on the state of the sm2_0 bit (or sm2_1 f or s e rial p o rt 1 ). when sm2_0 = 0, the baud rate is c lk24/12, when sm2_0 = 1, the baud rate is c l k24/4. t a b l e c - 7 . se r i a l port m odes mode sync/ async baud clock data bits sta r t/stop 9th b it function 0 sync c l k24/4 or c l k24/12 8 none none 1 a sync t imer 1 or t imer 2 1 8 1 s t a r t, 1 sto p none 2 a sync c l k24/32 or c l k24/64 9 1 s t a r t, 1 sto p 0, 1, par- ity 3 a sync t imer 1 or t imer 2 1 9 1 s t a r t, 1 sto p 0, 1, par- ity (1) t imer 2 available for serial port 0 o n ly.
c - 1 6 a p p e n d ix c : 8 0 5 1 h a r d w a r e d e scr i p t i on e z - u s b s e r i es 2 1 0 0 t rm v 1 . 8 mode 0 operation is ide n t ical to t he standard 8051. data t r a n smission b egins when an instruc- tion writes to t h e sbuf0 ( or sbu f 1 ) s fr. t h e u art s h i fts the dat a , ls b f irst, at the sele c ted baud rate, unt i l the 8-bit value has be e n shift e d out. mode 0 d a t a reception begins when the r e n_0 (or re n _1) bit is s et and the ri_0 (or ri_1) bit is cleared in t h e corresponding s c on sfr. the shift clock is activate d and the uart shifts data in on e a ch rising edge of the shift c lock until 8 bits have been re c e ived. one machine cyc l e after the 8th bi t is shifted in, t h e ri_0 (or ri_1 ) b i t i s set and reception stops unt i l the so f t w a r e clea r s the ri bit. figure c-7 through figure c-10 i l l u s t r a t e se r i a l p o r t mod e 0 transmit a n d recei v e t i ming for both low-speed (clk24/12) and high-speed (clk24/4) oper a t i on. t a b l e c - 8 . s c o n 0 r e gi s t e r - s fr 98h bit function s c on0.7 sm0_0 - serial port 0 mode bit 0. s c on0.6 sm1_0 - serial port 0 mode bit 1, de c oded a s : sm0_0 sm1_0 mode 0 0 0 0 1 1 1 0 2 1 1 3 s c on0.5 sm2_0 - mul t iproc e ssor c o mmuni c a tion enable. in mod e s 2 and 3, t h is bit enab l es the multi p roces- sor communication f e a ture. if sm2_0 = 1 in mode 2 or 3, then ri_0 will not be a cti v ated if the re c eived 9 t h bit is 0. if sm2_0=1 in mode 1, then ri_0 will only be a ctivated if a valid st o p is received. in mode 0, sm2_0 establishes the baud rate: when sm2_0=0, the baud r ate is clk24/12; when sm2_0=1, the baud rate i s c l k24/4. s c on0.4 r e n_0 - r e ceive enable. when ren_0=1 , r ecep- tion is enabled. s c on0.3 tb8_0 - defines the s tate of the 9th data b i t tr a ns- mitted in modes 2 and 3.
ez-usb series 2100 trm v1.8 appendix c: 8051 hardware description c - 17 scon0.2 rb8_0 - in modes 2 and 3, rb8_0 indicates the state of the 9th bit received. in mode 1, rb8_0 indicates the state of the received stop bit. in mode 0, rb8_0 is not used. scon0.1 ti_0 - transmit interrupt flag. indicates that the transmit data word has been shifted out. in mode 0, ti_0 is set at the end of the 8th data bit. in all other modes, ti_0 is set when the stop bit is placed on the txd0 pin. ti_0 must be cleared by firm- ware. scon0.0 ri_0 - receive inter rupt flag. indicates that serial data word has been received. in mode 0, ri_0 is set at the end of the 8th data bit. in mode 1, ri_0 is set after the last sample of the incoming stop bit, subject to the state of sm2_0. in modes 2 and 3, ri_0 is set at the end of the last sample of rb8_0. ri_0 must be cleared by firmw are. table c-8. scon0 register - sfr 98h bit function
c - 18 appendix c: 8051 hardware description ez-usb series 2100 trm v1.8 table c-9. scon1 register - sfr c0h bit function scon1.7 sm0_1 - serial port 1 mode bit 0. scon1.6 sm1_1 - serial port 1 mode bit 1, decoded as: sm0_1 sm1_1 mode 0 0 0 0 1 1 1 0 2 1 1 3 scon1.5 sm2_1 - multiprocessor communication enable. in modes 2 and 3, this bit enables the multiproces- sor communication feature. if sm2_1 = 1 in mode 2 or 3, then ri_1 will not be activated if the received 9th bit is 0. if sm2_1=1 in mode 1, then ri_1 will only be activated if a valid stop is received. in mode 0, sm2_1 establishes the baud rate: when sm2_1=0, the baud rate is clk24/12; when sm2_1=1, the baud rate is clk24/4. scon1.4 ren_1 - receive enable. when ren_1=1, recep- tion is enabled. scon1.3 tb8_1 - defines the state of the 9th data bit trans- mitted in modes 2 and 3. scon1.2 rb8_1 - in modes 2 and 3, rb8_0 indicates the state of the 9th bit received. in mode 1, rb8_1 indicates the state of the received stop bit. in mode 0, rb8_1 is not used. scon1.1 ti_1 - transmit interrupt flag. indicates that the transmit data word has been shifted out. in mode 0, ti_1 is set at the end of the 8th data bit. in all other modes, ti_1 is set when the stop bit is placed on the txd0 pin. ti_1 must be cleared by the soft- ware.
e z - u s b s e r i e s 2 1 00 t rm v 1 . 8 a p p e n d ix c : 8 0 5 1 h a r d w a r e d e scr i p t i on c - 1 9 s c on1.0 ri_ 1 - r e c e i v e i n t e r rupt flag. indi c ates that s e r i a l d a ta word h a s b een r e ceived. in mode 0 , ri_1 is s e t at th e en d o f the 8t h dat a bit. in mode 1, ri_1 is s et a f ter the la s t s a m p le of the incoming stop bit, subject to the state o f sm2_1. in modes 2 and 3, ri_1 i s s e t a t the end of the last sampl e of rb8_1. ri_1 must be cle a r e d by the s o f tware. f i g u r e c- 7 . s e r i al p o r t mode 0 r e c e i v e t i ming - l o w sp e e d o p e r a t i o n t ab l e c-9 . s c on1 r e gi s t e r - s f r c 0 h bit function clk24 d0 d1 d2 d3 d4 d5 d6 d7 ri txd0 rxd0 rxd 0 o u t psen ti
c - 20 appendix c: 8051 hardware description ez-usb series 2100 trm v1.8 figure c-8. serial port mode 0 receive timing - high speed operation figure c-9. serial port mode 0 transmit timing - low speed operation d0 d1 d2 d3 d4 d5 d6 d7 clk24 ri txd0 rxd0 rxd0out psen ti clk24 ri txd0 rxd0 rxd0out psen ti d0 d1 d2 d3 d4 d5 d6 d7
e z - u s b s e r i e s 2 1 00 t rm v 1 . 8 a p p e n d ix c : 8 0 5 1 h a r d w a r e d e scr i p t i on c - 2 1 c.3. 3 mode 1 mode 1 provides st a ndard asynchronous, full-duplex communication, using a total of 10 bits: 1 star t bit, 8 dat a bits, and 1 s top bit. for rece i v e oper a tions, the s t o p bi t is store d in rb8_0 (or rb8_1). data b i t s a re receiv e d and tr a n sm i t t ed l sb first. c.3.3.1 mode 1 baud rate the mode 1 baud r ate is a functi o n o f t imer o v er f low . se r i al p ort 0 c a n use e i ther t imer 1 or t i m e r 2 to g ene r a te baud rates. serial port 1 can only u s e t i mer 1. the two s erial ports can run at the same baud rate i f they both u se timer 1, o r di f ferent baud r a tes if serial port 0 uses t i m e r 2 and ser i al por t 1 u s es t imer 1. e ac h t ime th e time r i n c re m e n ts from it s maximu m count ( f f h for timer 1 o r ffffh for timer 2 ) , a clock is se n t to the ba u d r at e circuit. the cloc k is then divided by 1 6 to generate the baud r a t e . f i g u re c - 10 . s e r i a l p o r t m o d e 0 tran s m i t tim i n g - h i g h s p e e d o p e r a tion clk24 ri txd0 rxd0 rx d 0 o u t psen ti d0 d1 d2 d3 d4 d5 d6 d7
c - 2 2 a p p e n d ix c : 8 0 5 1 h a r d w a r e d e scr i p t i on e z - u s b s e r i es 2 1 0 0 t rm v 1 . 8 when usi n g timer 1, the smod0 ( o r smod 1 ) bit selects whether or not to d i vide the timer 1 rollov e r rate by 2. t h erefore, when u s ing ti m er 1, the baud rate is d e termined by the equa- tion: smod0 is sfr bit pcon. 7 ; smod1 is s fr bit eicon.7. when usi n g timer 2, the baud rate is det e rmined b y the equation: t o u s e timer 1 as the baud rate genera t or , it is best t o use timer 1 mode 2 (8 - b i t counter with auto - reload), although any counter mode can b e used. t h e t ime r 1 rel o a d i s stored i n the th1 r eg i s te r , which makes the complete formula for t imer 1: the 12 i n the d enomin a tor i n the a bov e e q u ation can be changed to 4 by settin g the t1m bit in the ck c on s f r . to d e riv e the require d th1 value from a known baud r ate ( when tm 1 = 0), use the equation: y ou c an also ach i eve very low s e r ial po r t baud rates fr o m t i m er 1 by enabling t h e t i mer 1 inte r rupt, configu r ing t imer 1 to mode 1, a n d using t h e t i mer 1 interrupt to initiate a 16-bit software reload. ta ble c-10 lists sa m ple r eload v a lu e s for a variety of c o mmon serial p o rt baud rate s . x t i me r 1 o v e r f l o w b a u d r a t e = 32 2 s m o d x t i m e r 2 ov e r f l ow b a u d r a te = 16 x b a ud r a t e = 32 2 s m o dx 12 x ( 2 56 - t h 1) c l k 2 4 x th1 = 2 s m odx c l k 2 4 3 8 4 x b a u d r a t e 2 5 6 -
e z - u s b s e r i e s 2 1 00 t rm v 1 . 8 a p p e n d ix c : 8 0 5 1 h a r d w a r e d e scr i p t i on c - 2 3 note that m o r e ac c urate b a ud r a te s a re achieved by u sing timer 2 as the baud rat e g enerator (nex t s e cti o n ). t o u s e timer 2 as the baud rate ge n e ra t or, conf i g u r e timer 2 in au t o-reload m o d e and set the t c lk and/o r r c lk bi t s in the t2con s f r. t clk sel e ct s timer 2 as the baud rate genera- tor for t h e transmitt e r ; rclk sel e cts ti m er 2 as the baud rate generator for th e receiver. the 16-bit reload value f o r t i mer 2 is stored in the rcap2l and r c a 2h sfrs, whi c h makes the equation for th e timer 2 b a u d r ate: where r c ap2h, r cap2 l i s the conten t of r c ap2h an d r cap2 l t ake n as a 16-bit uns i gned numbe r . the 32 in the deno m inator is the result of c lk24 being divided by 2 and t h e timer 2 over- f low being divided by 16. setting tclk or rclk to 1 automatica l ly c auses clk2 4 to be divided by 2 , as shown i n figure c-6, i n s t ead of the 4 o r 12 determined by the t2m bit in the ck c on sfr. t ab l e c-1 0 . tim e r 1 r el o a d v al u e s f o r com m on s e ri a l p o rt m o d e 1 b a u d r at e s nominal r a t e 24 m hz divisor r e load v a lue actu a l r a t e e r ror 57600 6 f a 62500 8.5% 38400 10 f6 37500 -2.3% 28800 13 f3 28846 +0.16% 19200 20 ec 18750 -2.3% 9600 39 d9 9615 +0.16% 4800 78 b2 4807 +0.15% 2400 156 64 2403 + .13% setting s : smod = 1, c/t =0, t i m e r1 mode=2 , t i m=1 no t e : u s ing rates that are o f f by 2.3% o r m o re will not work in all syste m s. b a u d r a t e = 3 2 x ( 6 5 5 3 6 - r c a p 2 h , r c a p 2 l ) c l k 2 4
c - 2 4 a p p e n d ix c : 8 0 5 1 h a r d w a r e d e scr i p t i on e z - u s b s e r i es 2 1 0 0 t rm v 1 . 8 t o derive the required rcap2h a n d r cap2l value s from a known baud rate, u se the equa- tion: whe n e ith e r rcl k or tclk is set, the tf2 fla g wil l no t be se t o n a t ime r 2 rol l ov e r, and the t2e x reload t r igger is di s abled. c.3.3.2 mode 1 t r an s mit figure c- 11 illu s t r a t e s the mode 1 transm i t timing. in mode 1, t he uart begins transmitting af t e r the first roll over o f the divide-by-16 counter after the software w r it e s to t h e sbuf0 (or sbuf1 ) registe r . the u a r t t ra n smi t s data on the txd0 (or txd1) pin in the following ord e r : start bit, 8 d ata b i ts ( l sb first), s top bit . the t i _ 0 (or ti _ 1 ) bit is set 2 clk24 cy c l e s af t e r the s top b i t is transmitted. c.3. 4 mode 1 rec e ive figure c-12. ill u st r a t e s t he m o d e 1 receive tim i n g . reception begi n s at the falling edge of a start bi t r e ceived on the rxd0 (or rxd1) pin, wh e n enabled by t h e ren_0 ( o r ren _ 1 ) bit. fo r th i s purpos e , the r x d0 (o r rxd1 ) pin is sampled 16 times per bit fo r any b aud rate. t a b l e c - 1 1 . t i me r 2 r e l o a d v a l u e s f o r c o mm o n s e r ial p o rt m o de 1 baud rates nominal r a t e c / t 2 divis or r eload v al actual rate e rror 57600 0 1 3 f 3 57692.3 1 0.16% 38400 0 2 0 ec 37500 -2.34% 28800 0 2 6 e 6 28846.1 5 0.16% 19200 0 3 9 d 9 19230.7 7 0.16% 9600 0 7 8 b 2 9615.38 5 0.16% 4800 0 156 64 4807.69 2 0.16% 2400 0 312 fec8 2403.84 6 0.16% no t e : us i ng r a tes t ha t ar e o f f b y 2 .3 % o r mo r e wil l no t w o r k in all systems. rc a p2h,r c a p 2l = c l k 2 4 32 x b a ud r a t e 6 5 5 3 6 -
ez-usb series 2100 trm v1.8 appendix c: 8051 hardware description c - 25 when a falling edge of a start bit is detected, the divide-by-16 counter used to generate the receive clock is reset to align the counter roll over to the bit boundaries. for noise rejection, the serial port establishes the content of each received bit by a majority decision of 3 consecutive samples in the middle of each bit time. this is especially true for the start bit. if the falling edge on the rxd0 (or rxd1) pin is not verified by a majority decision of 3 consecutive samples (low), then the serial port stops reception and waits for another fall- ing edge on the rxd0 (or rxd1) pin. at the middle of the stop bit time, the serial port checks for the following c onditions: ? ri_0 (or ri_1) = 0, and ? if sm2_0 (or sm2_1) = 1, the state of the stop bit is 1. (if sm2_0 (or sm 2_1) = 0, the state of the stop bit doesnt matter.) if the above conditions are met, the serial port then writes the received byte to the sbuf0 (or sbuf1) register, loads the stop bit into rb8_0 (or rb8_1), and sets the ri_0 (or ri_1) bit. if the above conditions are not met, the received data is lost, the sbuf register and rb8 bit are not loaded, and the ri bit is not set. after the middle of the stop bit time, the serial port waits for another high-to-low transition on the (rxd0 or rxd1) pin. mode 1 operation is identical to that of the standard 8051 when timers 1 and 2 use clk24/12 (the default). figure c-11. serial port 0 mode 1 transmit timing write to sbuf0 ri_0 txd0 rxd0 rxd0out shif tx clk ti_0 d0 d1 d2 d3 d4 d5 d6 d7 stop start
c - 26 appendix c: 8051 hardware description ez-usb series 2100 trm v1.8 c.3.5 mode 2 mode 2 provides asynchr onous, full- duplex communication, using a total of 11 bits: 1 start bit, 8 data bits, a programmable 9th bit, and 1 stop bit. the data bits are transmitted and received lsb first. for transmission, the 9th bit is determined by the value in tb8_0 (or tb8_1). to use the 9th bit as a parity bit, move the value of the p bit (sfr psw.0) to tb8_0 (or tb8_1). the mode 2 baud rate is either clk24/32 or clk24/64, as determined by the smod0 (or smod1) bit. the formula for the mode 2 baud rate is: mode 2 operation is identical to the standard 8051. figure c-12. serial port 0 mode 1 receive timing ri_0 txd0 rxd0 rxd0out shift rx clk ti_0 d0 d1 d2 d3 d4 d5 d6 d7 stop start bit detector sampling x baud rate = 2 smodx clk24 64
e z - u s b s e r i e s 2 1 00 t rm v 1 . 8 a p p e n d ix c : 8 0 5 1 h a r d w a r e d e scr i p t i on c - 2 7 c.3.5.1 mode 2 t r an s mit figure c-13 ill u st r a t e s t he m o d e 2 transmit ti m i ng. tra n smission begins af t er the first roll over of the divi d e -by-16 coun t e r following a so f twa r e wri t e t o sb u f0 (or s b u f1) . the u a rt sh i fts data out on the txd0 (or txd1) pin in the following or d er: sta r t bit, data bits ( lsb f irst), 9th bit, st o p bit. t h e ti_0 ( or ti_1) b i t is set when the st o p b it is placed on the t xd0 ( o r txd1) pin. c.3.5.2 mode 2 rec e ive figure c-14 ill u st r a t e s t he m o d e 2 receive tim i n g . reception begi n s at the falling edge of a start bi t r e ceived on the rxd0 (or rxd1) pin, when enabled by t h e ren_0 ( o r ren _ 1 ) bit. fo r th i s purpos e , the r x d0 (o r rxd1) pin is sampled 16 times per bit fo r any b aud rate. when a falling edge of a start bit is det e cted, the d ivide-by - 16 counter used to generate the r e ceive clock is r e s et t o align the cou n ter ro l l over to the bit boundaries. for noise r ej e ction, t h e s e rial p o rt esta b lishes the c o n tent of e ach received bit by a majority decisio n o f 3 c o n secut i ve samples i n t he middl e of eac h b i t time. thi s is e s pecially tru e fo r the start bit . if th e falling edge on t he rx d 0 (or rxd1) pin is no t verified by a majo r ity decision of 3 consecutive samp l es (low), then the serial po r t st o p s r eception and waits for a n o the r fall- ing edge on the rx d 0 (o r rxd1) pin. at the mi d d le of the st o p bit tim e , t h e serial port checks for the following c o n d itions: ? ri_0 (or ri_1) = 0, and ? i f s m2_0 (o r sm2_1) = 1, the state o f the s top bit is 1. ( if sm2_0 ( o r sm 2_1) = 0, t h e s t a t e o f t he stop bit do e snt m atter.) i f the above cond i ti o n s are met, the serial port th e n wr i tes the received byte to the sbuf0 (or sbuf1 ) regi s t e r , loads the s to p bit into rb8_0 (or rb8_1), and s ets the ri_0 (or ri_1 ) bit. if the above conditions are not met, the received data is los t , the sbuf register and rb8 bit are not loaded, and the ri bit is n o t set. af t er t h e middl e of the st o p bit time, t he se r ial port waits for another high - to-low tran s i tion on the rxd 0 ( or r xd1) pin.
c - 28 appendix c: 8051 hardware description ez-usb series 2100 trm v1.8 figure c-13. serial port 0 mode 2 transmit timing figure c-14. serial port 0 mode 2 receive timing ri_0 txd0 rxd0 rxd0out shift tx clk ti_0 d0 d1 d2 d3 d4 d5 d6 d7 stop start write to sbuf0 tb8 ri_0 txd0 rxd0 rxd0out shif rx clk ti_0 d0 d1 d2 d3 d4 d5 d6 d7 stop start rb8 bit detector sampling
e z - u s b s e r i e s 2 1 00 t rm v 1 . 8 a p p e n d ix c : 8 0 5 1 h a r d w a r e d e scr i p t i on c - 2 9 c.3. 6 mode 3 mode 3 provides asynchr onou s , f u l l - dupl e x communica t ion, usi n g a total of 11 bits: 1 start bit, 8 data bits, a programmable 9th bit, a n d 1 stop bit. the dat a bits a r e transmitted and r e ceive d ls b first. the mode 3 t r a n s mi t and operations are identical t o mode 2. the mode 3 bau d rate generation is ident i c al to mode 1. that is, mod e 3 i s a combination of mode 2 protocol and mode 1 baud r a t e . f igure c-15 illustrates the mode 3 t ran s m i t t im i ng. figu r e c-16 ill u s t r a t es t h e mode 3 r e ceiv e timing. mod e 3 operatio n is ide n t i ca l t o that of the standard 8051 whe n t i m e rs 1 and 2 u s e clk24/12 ( the defaul t ) . f ig u re c- 1 5 . s e r ia l p o r t 0 mo d e 3 t r a n s mi t t i ming f i g u r e c-1 6. s e r i a l p o rt 0 m o de 3 r e c e i v e t i m in g ri _ 0 txd0 rxd0 rxd0out shi f t tx c l k t i _ 0 d0 d1 d2 d3 d4 d5 d6 d7 st o p s t art w r i te t o sbuf0 t b 8 ri _ 0 txd0 rxd0 rxd0out shif rx clk t i _ 0 d0 d1 d2 d3 d4 d5 d6 d7 st o p s t art rb8 b i t d e te c tor s ampling
c - 3 0 a p p e n d ix c : 8 0 5 1 h a r d w a r e d e scr i p t i on e z - u s b s e r i es 2 1 0 0 t rm v 1 . 8 c.3. 7 mult i proce s sor com m unicati o ns the mul t ipr o cessor comm u n ication f e a ture is enabled in modes 2 and 3 w h e n the sm2 bit is s et in th e s con sf r for a s e rial port (sm2_0 for serial port 0, sm2_1 for serial port 1 ) . in mul t iproc e ssor communicat i on mode , the 9th b i t received is s t ore d in rb 8_ 0 (or rb8_1) and, af t e r the s top b i t is receiv e d , t he se r ial po r t in t e r rupt i s acti v ated only if rb8_0 (or rb8_1) = 1. a typical use f o r the multi p roce s sor communication f e ature is when a master wants to send a bloc k of dat a to on e o f sever a l s laves. the maste r fi r s t t ransmits an address byt e that id e ntifies the target slave. when transmitting an address byte, the m a ster sets the 9th bit to 1; for data bytes, the 9th bit is 0. w ith sm2_ 0 ( o r sm 2_1) = 1 , n o s l a v e w i ll b e i n t e r r upted by a dat a byte. however , a n address byte interr u p t s a ll sla v es so that each s l ave can examine t he received address b y t e to deter- mine whet h e r that s lave is being a d d r e s sed. a d d r ess decoding must be done b y softwar e dur- ing the in t e r rupt serv i c e routin e . t h e addressed slave clear s its sm2_0 (or sm2_1) bit and p r epa r e s to receiv e the dat a by t e s. the slaves tha t are not being addressed leave th e s m 2_ 0 (or sm2_1) bit set and ignore the incoming data bytes. c.3. 8 inter ru p t sfrs the fo l lowing sfr s a re a s s o ciated with interrupt control: ? ie - s f r a8h ( t abl e c-12 ) ? i p - s f r b8h ( table c-13 ) ? e xif - sfr 91h ( table c-14 ) ? e icon - sfr d8h ( table c-15 ) ? e i e - sfr e 8 h ( table c-16) ? e ip - sfr f8h ( table c-17 ) the i e and ip sfrs provide interrupt enable and p r iority c o n tr o l for the standard interrupt uni t , as with the standard 8051. additi o n a lly, th e s e sfrs provide control bits for the serial po r t 1 interrupt. the s e bits ( es1 and p s 1) are a vai l able only when the extended interrupt unit is i mplemented (ext_int r =1). otherwise, th e y are read as 0. bit s es0, es1, et2, ps0, ps1 , and pt2 a re p resent, but not used, when the c orresponding modu l e is not implemented.
ez-usb series 2100 trm v1.8 appendix c: 8051 hardware description c - 31 the exif, eicon, eie and eip registers provide flags, enable control, and priority control for the optional extended interrupt unit. table c-12. ie register - sfr a8h bit function ie.7 ea - global interrupt enable. controls masking of all interrupts except usb wakeup (resume). ea = 0 disables all interrupts except usb wakeup. when ea = 1, interrupts are enabled or masked by their individual enable bits. ie.6 es1 - enable serial port 1 interrupt. es1 = 0 dis- ables serial port 1 interrupts (ti_1 and ri_1). es1 = 1 enables interrupts generated by the ti_1 or ti_1 flag. ie.5 et2 - enable timer 2 interrupt. et2 = 0 disables timer 2 interrupt (tf2). et2=1 enables interrupts generated by the tf2 or exf2 flag. ie.4 es0 - enable serial port 0 interrupt. es0 = 0 dis- ables serial port 0 interrupts (ti_0 and ri_0). es0=1 enables interrupts generated by the ti_0 or ri_0 flag. ie.3 et1 - enable timer 1 interrupt. et1 = 0 disables timer 1 interrupt (tf1). et1=1 enables interrupts generated by the tf1 flag. ie.2 ex1 - enable external interrupt 1. ex1 = 0 dis- ables external interrupt 1 (int1). ex1=1 enables interrupts generated by the int1# pin. ie.1 et0 - enable timer 0 interrupt. et0 = 0 disables timer 0 interrupt (tf0). et0=1 enables interrupts generated by the tf0 flag. ie.0 ex0 - enable external interrupt 0. ex0 = 0 dis- ables external interrupt 0 (int0). ex0=1 enables interrupts generated by the int0# pin.
c - 32 appendix c: 8051 hardware description ez-usb series 2100 trm v1.8 table c-13. ip register - sfr b8h bit function ip.7 reserved. read as 1. ip.6 ps1 - serial port 1 interrupt priority control. ps1=0 sets serial port 1 interrupt (ti_1 or ri_1) to low priority. ps1=1 sets serial port 1 interrupt to high priority. ip.5 pt2 - timer 2 interrupt priority control. pt2=0 sets timer 2 interrupt (tf2) to low priority. pt2=1 sets timer 2 interrupt to high priority. ip.4 ps0 - serial port 0 interrupt priority control. ps0=0 sets serial port 0 interrupt (ti_0 or ri_0) to low priority. ps0=1 sets serial port 0 interrupt to high priority. ip.3 pt2 - timer 1 interrupt priority control. pt1 = 0 sets timer 1 interrupt (tf1) to low priority. pt1=1 sets timer 1 interrupt to high priority. ip.2 px1 - external interrupt 1 priority control. px 1= 0 sets external interrupt 1 (int1) to low priority. pt1 = 1 sets external interrupt 1 to high priority. ip.1 pt0 - timer 0 interrupt priority control. pt0 = 0 sets timer 0 interrupt (tf0) to low priority. pt0=1 sets timer 0 interrupt to high priority. ip.0 px0 - external interrupt 0 priority control. px0 = 0 sets external interrupt 0 (int0) to low priority. px0=1 sets external interrupt 0 to high priority.
ez-usb series 2100 trm v1.8 appendix c: 8051 hardware description c - 33 table c-14. exif register - sfr 91h bit function exif.7 ie5 - external interrupt 5 flag. ie 5= 1 indicates a falling edge was detected at the int5# pin. ie5 must be cleared by software. setting ie5 in soft- ware generates an interrupt, if enabled. exif.6 ie4 - external interrupt 4 flag. ie4 indicates a ris- ing edge was detected at the int4 pin. ie4 must be cleared by software. setting ie4 in software gener- ates an interrupt, if enabled. exif.5 i2cint - external interrupt 3 flag. the int3 interrupt is internally c onnected to the ez-usb i 2 c controller and renamed i2cint. i2cint = 1 indicates an i 2 c interrupt. i2cint must be cleared by software. setting i2cint in software generates an interrupt, if enabled. exif.4 usbint - external interrupt 2 flag. the int2 interrupt is internally connected to the ez-usb interrupt and renamed usbint. usbint = 1 indicates an usb interrupt. usbint must be cleared by software. setting usbint in software generates an interrupt, if enabled. exif.3 reserved. read as 1. exif.2-0 reserved. read as 0.
c - 34 appendix c: 8051 hardware description ez-usb series 2100 trm v1.8 table c-15. eicon register - sfr d8h bit function eicon.7 smod1 - serial port 1 baud rate doubler enable. when smod1 = 1 the baud rate for serial port is doubled. eicon.6 reserved. read as 1. eicon.5 eresi - enable resume interrupt. eresi = 0 dis- ables resume interrupt (resi). eresi = 1 enables interrupts generated by the resume event. eicon.4 resi - wakeup interrupt flag. eicon.4 = 1 indi- cates a negative transition was detected at the wakeup# pin, or that usb has activity resumed from the suspended state. eicon.4 = 1 must be cleared by software before exiting the interrupt service routine, otherwise the interrupt occurs again. setting eicon.4=1 in software generates a wakeup interrupt, if enabled. eicon.3 int6 - external interrupt 6. when int6 = 1, the int6 pin has detected a low to high transition. int6 will remain active until cleared by writing a 0 to this bit. setting this bit in software generates an int6 interrupt in enabled. eicon.2-0 reserved. read as 0.
ez-usb series 2100 trm v1.8 appendix c: 8051 hardware description c - 35 table c-16. eie register - sfr e8h bit function eie.7-5 reserved. read as 1. eie.4 ex6 - enable external interrupt 6. ex6 = 0 dis- ables external interrupt 6 (int6). ex6 = 1 enables interrupts generated by the int6 pin. eie.3 ex5 - enable external interrupt 5. ex5 = 0 dis- ables external interrupt 5 (int5). ex5 = 1 enables interrupts generated by the int5# pin. eie.2 ex4 - enable external interrupt 4. ex4 = 0 dis- ables external interrupt 4 (int4). ex4 = 1 enables interrupts generated by the int4 pin. eie.1 ei2c - enable external interrupt 3. ei2c = 0 dis- ables external interrupt 3 (int3). ei2c = 1 enables interrupts generated by the i 2 c interface. eie.0 eusb - enable usb interrupt. eusb = 0 disables usb interrupts. eusb = 1 enables interrupts gen- erated by the usb interface.
c - 3 6 a p p e n d ix c : 8 0 5 1 h a r d w a r e d e scr i p t i on e z - u s b s e r i es 2 1 0 0 t rm v 1 . 8 c.4 inte r rupt proces s ing whe n a n enabled int e r rupt occurs, the 8051 core vectors t o the addr e s s of the in t e r rup t s e rvice routin e (isr) a ss o ciated with t h at interrupt, as l iste d in ta b le c-18 . the 8051 core executes th e isr to completio n unl e ss anoth e r int e rrup t of higher pr i ority occurs. eac h isr ends with a reti ( r e turn f rom inter r upt) i nst r u ction. after e xecuting th e reti , the cpu r e turns to the next i n struction t hat would ha v e been executed if the i n terrupt had not o ccurred. an isr can only be interrupted by a hi g h er priority interrupt. t hat is, an isr fo r a low-level inte r rupt can only b e i n terrupted by high-level interrupt. a n isr fo r a high- l e v el interrupt can only be int e rrupted by th e resume interrupt. the 8051 co r e always completes the instruction in progress befo r e servicing an in t errupt. if the in s truction in p r og r ess i s reti , or a write a ccess t o any o f t he i p, i e, e ip, or eie sfrs, the 8051 core completes o n e addition a l instruct i on before serv i cing the interrupt. t a b le c- 1 7. eip r e g i s t er - s f r f8h bit function ei p .7-5 r es e rved. r ea d as 1. ei p . 4 px6 - ext e rnal int e rrupt 6 priority control. px6 = 0 s e t s ex t e rnal int e rrupt 6 ( int 6 ) to low p rior i ty. px6 = 1 s e t s ex t e rnal int e rrupt 6 to h i gh pri o rity. ei p . 3 px5 - ext e rnal int e rrupt 5 priority control. px5 = 0 s e t s ex t e rnal int e rrupt 5 ( int 5 # ) to low p rior i ty. px5=1 s e t s ex t e rn a l inte r rupt 5 to hi g h prio r ity. ei p . 2 px4 - ext e rnal int e rrupt 4 priority control. px4 = 0 s e t s ex t e rnal int e rrupt 4 ( int 4 ) to low p rior i ty. px4=1 s e t s ex t e rn a l inte r rupt 4 to hi g h prio r ity. ei p . 1 pi2c - extern a l interrupt 3 p r iori t y control. pi 2 c = 0 sets i 2 c interrupt to lo w prio r i t y. pi2c=1 sets i 2 c interrupt to h igh pr i ority. ei p . 0 pusb - ex t e rnal inter r upt 2 pr i orit y control . pusb = 0 sets usb inte r rupt to low pri o r i ty. pusb=1 s ets usb int e r rupt to high pri o rity.
e z - u s b s e r i e s 2 1 00 t rm v 1 . 8 a p p e n d ix c : 8 0 5 1 h a r d w a r e d e scr i p t i on c - 3 7 c.4. 1 inter ru pt m a sking the ea bit in th e ie s f r ( i e.7) is a global enable f or al l interrupts ex c e p t the usb wakeup ( resume ) inte r rupt. when e a = 1, each in t err u p t is e n able d or masked by its individual enable bit. when ea = 0, all i n t errupt s a re masked, except t h e usb wakeup interrupt. t able c-19 provides a s ummary of interrupt sour c es , fla g s, enab l es, a nd pri o r i ties. t a b l e c - 18 . i nt e r r u pt n a t u r a l v e c t o r s a nd p r i oritie int e r rupt des c r iption natural prio r ity interrupt v e c tor resume usb w akeup ( resu m e ) interrupt 0 33h int0 ext e rnal int e rrupt 0 1 03h t f 0 t imer 0 interrupt 2 0bh int1 ext e rnal int e rrupt 1 3 13h t f 1 t imer 1 interrupt 4 1bh t i_0 o r ri_0 seri a l port 0 interrupt 5 23h t f2 o r exf2 t imer 2 interrupt 6 2bh t i_1 o r ri_1 seri a l port 1 interrupt 7 3bh int2 usb in t e r rupt 8 43h int3 i 2 c inte r rupt 9 4bh int4 ext e rnal int e rrupt 4 4 53h int5 ext e rnal int e rrupt 5 1 1 5bh int6 ext e rnal int e rrupt 6 1 2 63h
c - 3 8 a p p e n d ix c : 8 0 5 1 h a r d w a r e d e scr i p t i on e z - u s b s e r i es 2 1 0 0 t rm v 1 . 8 c.4. 2 inter ru p t prio r ities there are two stages of interrupt prio r ity a s signme n t, interrupt level and natu r al pr i ority. the inte r rup t level (hi g h est , high, o r low) takes precedenc e over natura l pri o rity . t he us b w a k eup inte r rupt, i f enabled, always has highest pr i orit y and i s the onl y inte r rupt that ca n have high e st p r iori t y. a l l othe r interrupts can be assigned eithe r high or low p r i ority. in addition to an assign e d priority l evel (high or low) , e a ch interr u p t also has a nat u ral prior- i t y, a s liste d i n tab l e c-18. simultane o u s int e rrupts with th e s a me prio r it y level ( for example, both hi g h ) are resolved according to their n a t ural prio r i ty. f o r e x a m p le, i f int0 and int2 are both pr o g r a mmed as high pri o r i ty, int0 takes prec e dence due to its higher natural p r i ority. once an inte r rupt is b e ing s e r viced, only an in t errupt of h i ghe r priority level c a n i nterrupt the service routin e of the interrupt currently being serviced. t a b l e c - 1 9 . i n t e r r u pt f lag s , e na b l e s, a n d p r i o r i t y c ontrol int e r rupt de s cription flag enable p r iority control r esume r esume inter- rupt eic o n.4 eic o n. 5 n/a int0 external inter- rupt 0 tcon.1 ie.0 i p .0 tf0 t imer 0 int e r- rupt tcon.5 ie.1 i p .1 int1 external inter- rupt 1 tcon.3 ie.2 i p .2 tf1 t imer 1 int e r- rupt tcon.7 ie.3 i p .3 ti_0 or ri_0 serial por t 0 tran s m it or re c eive s c on0.0 (ri.0), s c on0.1 ( t i_0) ie.4 i p .4 tf2 or e x f2 t imer 2 int e r- rupt t2con.7 (tf2), t2con.6 (exf 2 ) ie.5 i p .5
e z - u s b s e r i e s 2 1 00 t rm v 1 . 8 a p p e n d ix c : 8 0 5 1 h a r d w a r e d e scr i p t i on c - 3 9 c.4. 3 inter ru pt s ampling the internal timers a n d s e ria l ports g e n e r ate interrupts by set t i ng t heir res p e c tive sfr inter- rupt f lag bits. exte r n al interr u p ts are sampled o n c e per instruction cycle. i nt0 and int1 are both active l ow and can b e p r o g ramm e d to be eit h e r edge-sensitive or level-sen s i t ive, through the it0 and it1 bits in t h e t con sfr . for example, when it0 = 0, i nt0 i s lev e l -sensitive and the 8051 core sets t he ie0 flag when the int0# pin is sampled lo w . when it0 = 1, i n t0 is e dge - s e nsitive and the 8051 sets the ie 0 flag when the int0# pin is s ampled high then low on c o n secut i ve samples. the remaining five interr u p t s (int 4-6, u sb & i 2 c interrupts) are edge-s e nsitiv e on l y. int6 and int4 are act i ve hi g h and int5 is active l ow. t o ensure that edge-sensiti v e interrupts are detected, the c orresponding ports s hould be held high for 4 c l k2 4 cycles and then low for 4 clk2 4 cycles. level-sen s itive interr u p ts are not latched and mu s t remain a c t ive unt i l ser v iced. ti_1 or ri_1 serial por t 1 tran s m it or re c eive s c on1.0 (ri_1), s c on1.1 (ti_1) ie.6 i p .6 u s b u s b interrupt exi f .4 ei e . 0 ei p .0 i 2 c i 2 c inte r rupt exi t .5 ei e . 1 ei p .1 int4 external inter- rupt 4 exi f .6 ei e .2 ei p .2 int5 external inter- rupt 5 exi f .7 ei e .3 ei p .3 int6 external int 6 eicon.3 ei e .4 ei p . 4 t a b l e c - 1 9 . i n t e r r u pt f lag s , e na b l es, a n d pr i o r i t y c on trol int e r rupt de s cription flag enable p r iority control
c - 40 appendix c: 8051 hardware description ez-usb series 2100 trm v1.8 c.4.4 interrupt latency interrupt response time depends on the current state of the 8051. the fastest response time is 5 instruction cycles: 1 to detect the interrupt, and 4 to perform the lcall to the isr. the maximum latency (13 instruction cycles) occurs when the 8051 is currently executing a reti instruction followed by a mul or div instruction. the 13 instruction cycles in this case are: 1 to detect the interrupt, 3 to complete the reti , 5 to execute the div or mul , and 4 to execute the lcall to the isr. for the maximum latency case, the response time is 13 x 4 = 52 clk24 cycles. c.4.5 single-step operation the 8051 interrupt structure provides a way to perform single-step program execution. when exiting an isr with an reti instruction, the 8051 will always execute at least one instruction of the task program. therefore, once an isr is entered, it cannot be re-entered until at least one program instruction is executed. to perform single-step execution, program one of the external interrupts (for example,int0) to be level-sensitive and write an isr for that interrupt the terminates as follows: jnb tcon.1,$ ; wait for high on int0# pin jb tcon.1,$ ; wait for low on int0# pin reti ; return for isr the cpu enters the isr when the int0# pin goes low, then waits for a pulse on int0#. each time int0# is pulsed, the cpu exits the isr, executes one program instruction, then re-enters the isr. the 8051 reset pin is internally connected to an ez-usb register bit that is controllable through the usb host. see chapter 10, "ez-usb resets" for details. c.5 reset
ez-usb series 2100 trm v1.8 appendix c: 8051 hardware description c - 41 c.6.1 idle mode an instruction that sets the idle bit (pcon.0) causes the 8051 to enter idle mode when that instruction completes. in idle mode, cpu processing is suspended, and internal registers maintain their current data. when the 8051 core is in idle, the ez-usb core enters suspend mode and shuts down the 24 mhz oscillator. see chapter 11, "ez-usb power management" for a full description of the suspend/resume process. c.6 power saving modes table c-20. pcon register - sfr 87h bit function pcon.7 smod0 - serial port 0 baud rate double enable. when smod0 = 1, the baud rate for serial port 0 is doubled. pcon.6-4 reserved. pcon.3 gf1 - general purpose flag 1. bit-addressable, general purpose flag for software control. pcon.2 gf0 - general purpose flag 0. bit-addressable, general purpose flag for software control. pcon.1 this bit should always be set to 0. pcon.0 idle - idle mode select. setting the idle bit places the 8051 in idle mode.
c - 42 appendix c: 8051 hardware description ez-usb series 2100 trm v1.8
cypress: ez-usb series 2100 family page 1 of 2 file://f:\export\projects\bitting2\imaging\bitting\mail_pdf\recode\ezusb1pg.htm 1/23/01 cypress parametric product families > usb > full-speed microcontrollers > ez-usb family ez-usb ? series 2100 family to download full device information in adobe acrobat format: [ adobe acrobat(pdf)(3.41mb) ] the anchor chips ez-usb ? family (an21xx) provides significant improvements over other usb architectures including an enhanced 8051 core, 4 or 8 kbytes of ram, an intelligent usb core, and high-performance i/o ports. the family includes 16 different products to accommodate the needs of different systems. the enhanced 8051 core provides five times the performance of the standard 8051, while maintaining complete 8051 software compatibility. with on - chip ram, firmware code can be downloaded from the host pc. this allows the peripheral manufacturer to easily modify and transfer new code to current and new users. this on - chip memory eliminates the need for external memory. the ez - usb family supports high - bandwidth transfers by providing an efficient mechanism to move data between external memory and the usb fifos. using this ? turbo mode, ? the 8051 core can transfer 1024 bytes of data in or out of an isochronous fifo in 338 microseconds. this leaves a high percentage of the bandwidth for the processor to service the application. the ez - usb family also supports an equiva - lent data transfer rate for bulk packets of over 2 mbytes per second, which is more than the usb bandwidth. the ez - usb family conforms to the high - speed (12 mbps) requirements of usb specification version 1.0, including support for remote wake - up. the internal sram replaces flash memory, eeprom, eprom, or masked rom that is conventionally used in other usb solutions. the ez - usb family offers two packages, a 44 pqfp and an 80 pqfp. all ez - usb ???features l single - chip, low power solution for high - speed usb peripherals l firmware downloadable l high - performance i/o port l small board space (less than 1 square inch) l 44 pqfp or 80 pqfp l usb specification 1.1 compliant l uses commercially available 8051 software tools l thirty - one flexible endpoints l all endpoints can be double buffered l 4 or 8 kbytes of memory l five times the speed of a standard 8051 l supports composite devices l i 2 c controller l supports isochronous, bulk, control, and interrupt data l on - chip pll ???ez - usb series 2100 an2121sc an2122tc an2125sc an2126sc an2126tc
cypress: ez-usb series 2100 family page 2 of 2 file://f:\export\projects\bitting2\imaging\bitting\mail_pdf\recode\ezusb1pg.htm 1/23/01 february 23, 2000 the ez - usb family offers two packages, a 44 pqfp and an 80 pqfp. all ez - usb devices are pin - and software - compatible. and, all ram versions have rom equivalents to allow easy migration for high - volume applications. an2126tc an2131sc AN2135Sc an2136sc an2131qc home | corporate info | site map | contact us | search design resources | press room | investor relations | employment please email your comments on this site to webmaster@cypress.com . ? copyright 1995 - 1998. cypress semiconductor corporation. all rights reserved. terms & conditions.

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