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| document no. u15836ej5v0ud00 (5th edition) date published february 2005 n cp(k) printed in japan pd780101 pd780101(a) pd780101(a1) pd780101(a2) pd780102 pd780102(a) pd780102(a1) pd780102(a2) pd780103 pd780103(a) pd780103(a1) pd780103(a2) pd78f0103 pd78f0103(a) pd78f0103(a1) 78k0/kb1 8-bit single-chip microcontrollers user?s manual c
user?s manual u15836ej5v0ud 2 [memo] user?s manual u15836ej5v0ud 3 1 2 3 4 voltage application waveform at input pin waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between v il (max) and v ih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between v il (max) and v ih (min). handling of unused input pins unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. precaution against esd a strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. status before initialization power-on does not necessarily define the initial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the reset signal is received. a reset operation must be executed immediately after power-on for devices with reset functions. power on/off sequence in the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. when switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. the correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. input of signal during power off state do not input signals or an i/o pull-up power supply while the device is not powered. the current injection that results from input of such a signal or i/o pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. notes for cmos devices 5 6 user?s manual u15836ej5v0ud 4 windows and windows nt are either registered trademarks or trademar ks of microsoft corporation in the united states and/or other countries. pc/at is a trademark of internati onal business machines corporation. hp9000 series 700 and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. solaris and sunos are trademar ks of sun microsystems, inc. user?s manual u15836ej5v0ud 5 these commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. diversion contrary to the law of that country is prohibited. the information in this document is current as of september, 2004. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) ? ? ? ? ? ? user?s manual u15836ej5v0ud 6 regional information ? ? ? ? ? ? ? ? ? ? ? ? user?s manual u15836ej5v0ud 7 introduction readers this manual is intended for user engineers who wish to understand the functions of the 78k0/kb1 and design and develop appl ication systems and programs for these devices. the target products are as follows. 78k0/kb1: ? ? ? ? ? ? ? ? user?s manual u15836ej5v0ud 8 how to read this manual it is assumed that the readers of this ma nual have general knowledge of electrical engineering, logic circuits, and microcontrollers. ? ? ? ? ? ? ? ? ? user?s manual u15836ej5v0ud 9 differences between 78k0/kb1 and 78k0/kb1+ series name item 78k0/kb1 78k0/kb1+ mask rom version available none power supply two power supplies single power supply self-programming function none available flash memory version option byte none ring-osc can be stopped/cannot be stopped selectable power-on clear function 2.85 v 0.15 v or 3.5 v 0.2 v selectable 2.1 v 0.1 v (fixed) note minimum instruction execution time 0.166 s (at 12 mhz operation) 0.125 s (at 16 mhz operation) note this value may change after evaluation. related documents the related documents indicated in this pub lication may include preliminary versions. however, preliminary versions are not marked as such. documents related to devices document name document no. 78k0/kb1 user?s manual this manual 78k0/kb1+ user?s manual u16846e 78k/0 series instructions user?s manual u12326e documents related to development tools (software) (user?s manuals) document name document no. operation u16629e language u14446e ra78k0 assembler package structured assembly language u11789e operation u16613e cc78k0 c compiler language u14298e operation u16768e sm78k series ver. 2.52 system simulator external part user open interface specifications u15802e id78k0-ns ver. 2.52 integrat ed debugger operation u16488e id78k0-qb ver. 2.81 integrat ed debugger operation u16996e pm plus ver. 5.10 u16569e caution the related docum ents listed above are subject to change with out notice. be sure to use the latest version of each document when designing. user?s manual u15836ej5v0ud 10 documents related to development tools (hardware) (user?s manuals) document name document no. ie-78k0-ns in-circuit emulator u13731e ie-78k0-ns-a in-circuit emulator u14889e ie-78k0k1-et in-circuit emulator u16604e qb-78k0kx1h in-circuit emulator u17081e ie-780148-ns-em1 emulation board to be prepared documents related to fl ash memory programming document name document no. pg-fp3 flash memory programmer user?s manual u13502e pg-fp4 flash memory programmer user?s manual u15260e other documents document name document no. semiconductor selection guide ? ? user?s manual u15836ej5v0ud 11 contents chapter 1 outline ........................................................................................................... ................. 17 1.1 expanded-specification products and conventional products (standard products, (a) grade products only) ........... ........................................................... 17 1.2 features ................................................................................................................... ................... 18 1.3 applications............................................................................................................... ................. 19 1.4 ordering information ....................................................................................................... .......... 20 1.5 pin configuration (top view).................................... ........................................................... ..... 22 1.6 kx1 series lineup .......................................................................................................... ............ 23 1.6.1 78k0/kx1, 78k0 /kx1+ produc t lineup ....................................................................................... ......23 1.6.2 v850es/kx1, v850es/ kx1+ produc t lineup ................................................................................... 26 1.7 block diagram .............................................................................................................. .............. 29 1.8 outline of functions ....................................................................................................... ........... 30 chapter 2 pin functions .................................................................................................... ........... 32 2.1 pin function list .......................................................................................................... .............. 32 2.2 description of pin functions .................................... ........................................................... ..... 34 2.2.1 p00 to p03 (por t 0) ...................................................................................................... ...................34 2.2.2 p10 to p17 (por t 1) ...................................................................................................... ...................34 2.2.3 p20 to p23 (por t 2) ...................................................................................................... ...................35 2.2.4 p30 to p33 (por t 3) ...................................................................................................... ...................35 2.2.5 p120 (port 12)........................................................................................................... ......................35 2.2.6 p130 (port 13)........................................................................................................... ......................36 2.2.7 av ref ............................................................................................................................... ...............36 2.2.8 av ss ............................................................................................................................... ................36 2.2.9 reset .................................................................................................................... .......................36 2.2.10 x1 and x2............................................................................................................... ........................36 2.2.11 v dd ............................................................................................................................... ...................36 2.2.12 v ss ............................................................................................................................... ...................36 2.2.13 v pp (flash memory versions only) .................................................................................................. .36 2.2.14 ic (mask rom versions only)............................................................................................. ............36 2.3 pin i/o circuits and recommende d connection of unused pins......................................... 37 chapter 3 cpu architecture ................................................................................................. ..... 39 3.1 memory space............................................................................................................... ............. 39 3.1.1 internal progr am memory space............................................................................................ .........44 3.1.2 internal data memory space ............................................................................................... ............45 3.1.3 special function register (s fr) area..................................................................................... ..........45 3.1.4 data memo ry addre ssing ................................................................................................... ............46 3.2 processor registers ........................................................................................................ .......... 50 3.2.1 control registers ........................................................................................................ .....................50 3.2.2 general-purpo se regi sters ................................................................................................ ..............54 3.2.3 special function register s (sfrs) ........................................................................................ ...........55 3.3 instruction address addressing ................................... .......................................................... .59 3.3.1 relative addre ssing ...................................................................................................... ..................59 3.3.2 immediat e addre ssing ..................................................................................................... ...............60 user?s manual u15836ej5v0ud 12 3.3.3 table indi rect addr essing................................................................................................ ............... 61 3.3.4 register addre ssing ...................................................................................................... ................. 61 3.4 operand address addre ssing ................................................................................................. .62 3.4.1 impli ed addres sing....................................................................................................... .................. 62 3.4.2 register addre ssing ...................................................................................................... ................. 63 3.4.3 direct addre ssing........................................................................................................ ................... 64 3.4.4 short dire ct addressing .................................................................................................. ................ 65 3.4.5 special function r egister (sfr ) addre ssing............................................................................... ..... 66 3.4.6 register i ndirect addr essing ............................................................................................. ............. 67 3.4.7 based addres sing ......................................................................................................... ................. 68 3.4.8 based index ed addres sing................................................................................................. ............ 69 3.4.9 stack addressi ng ......................................................................................................... .................. 70 chapter 4 port functions ................................................................................................... ........ 71 4.1 port functions ............................................................................................................. ............... 71 4.2 port configurat ion......................................................................................................... ............. 72 4.2.1 port 0 ................................................................................................................... .......................... 73 4.2.2 port 1 ................................................................................................................... .......................... 76 4.2.3 port 2 ................................................................................................................... .......................... 81 4.2.4 port 3 ................................................................................................................... .......................... 82 4.2.5 po rt 12 .................................................................................................................. ......................... 83 4.2.6 po rt 13 .................................................................................................................. ......................... 84 4.3 registers controlling port func tion ........................................................................................ 84 4.4 port function operations ................................................... ................................................ ....... 88 4.4.1 writing to i/o port...................................................................................................... ..................... 88 4.4.2 reading from i/o port .................................................................................................... ................ 88 4.4.3 operatio ns on i/o port ................................................................................................... ................ 88 chapter 5 clock generator .................................................................................................. .... 89 5.1 functions of clock generator......................................... ...................................................... .... 89 5.2 configuration of clock genera tor ........................................................................................... .89 5.3 registers controlling clock generator........................ ............................................................ 91 5.4 system clock oscillator .................................................................................................... ........ 97 5.4.1 x1 o scillat or ............................................................................................................ ....................... 97 5.4.2 ring-osc oscilla tor ...................................................................................................... ................. 99 5.4.3 pre scaler................................................................................................................ ........................ 99 5.5 clock generator operation ............................................. ..................................................... ... 100 5.6 time required to switch between ring-osc clo ck and x1 input clock........................... 105 5.7 time required for cpu clock switchover................... .......................................................... 106 5.8 clock switching flowchart and re gister setting ................................................................. 107 5.8.1 switching from ring-osc clock to x1 i nput cloc k........................................................................ 10 7 5.8.2 switching from x1 input clock to ring- osc cloc k........................................................................ 10 8 5.8.3 register settings ........................................................................................................ .................. 109 chapter 6 16-bit timer/event counter 00 ........................................................................... 110 6.1 functions of 16-bit time r/event counter 00 .............................. ........................................... 110 6.2 configuration of 16-bit timer/e vent counter 00................................................................... 111 6.3 registers controlling 16 -bit timer/event counter 00 .......................................................... 115 user?s manual u15836ej5v0ud 13 6.4 operation of 16-bit timer/event co unter 00 ......................................................................... 121 6.4.1 interval ti mer operation................................................................................................. ................121 6.4.2 ppg output operations .................................................................................................... .............124 6.4.3 pulse width me asurement operati ons....................................................................................... ....127 6.4.4 external event counter o peration......................................................................................... .........135 6.4.5 square-wave output oper ation............................................................................................. .........138 6.4.6 one-shot puls e output op eration .......................................................................................... ........140 6.5 cautions for 16-bit timer/event co unter 00 ......................................................................... 145 chapter 7 8-bit timer/event counter 50............................................................................. 148 7.1 functions of 8-bit timer/ event counter 50.............................. ............................................. 148 7.2 configuration of 8-bit timer/even t counter 50 .................................................................... 149 7.3 registers controlling 8- bit timer/event counter 50................... ......................................... 151 7.4 operations of 8-bit timer/event counter 50 .......... ............................................................... 154 7.4.1 operation as interval timer .............................................................................................. .............154 7.4.2 operation as ex ternal event count er...................................................................................... .......156 7.4.3 operation as square-wave output.......................................................................................... .......157 7.4.4 operation as pwm output .................................................................................................. ..........158 7.5 cautions for 8-bit timer/event c ounter 50 ........................................................................... 160 chapter 8 8-bit timers h0 and h1 ........................................................................................ .. 161 8.1 functions of 8-bit timers h0 and h1 ..................................................................................... 161 8.2 configuration of 8-bit timers h0 and h1 ............... ............................................................... 161 8.3 registers controlling 8-bit timers h0 and h1...................................................................... 165 8.4 operation of 8-bit timers h0 and h1 ....................... .............................................................. 169 8.4.1 operation as interval timer/square- wave ou tput ........................................................................... 169 8.4.2 operation as pwm output mode ............................................................................................. .....172 chapter 9 watchdog timer ................................................................................................... .... 178 9.1 functions of watchdog timer ....................................... ......................................................... 178 9.2 configuration of watchdog timer.............................. ............................................................ 18 0 9.3 registers controlling wa tchdog timer ................................................................................. 181 9.4 operation of watchdog timer ................................................................................................ 184 9.4.1 watchdog timer operation when ?ring-osc cannot be stopped? is selected by mask option ......184 9.4.2 watchdog timer operation when ?ring-osc can be stopped by software? is selected by mask option......................................................................................................................... ...................185 9.4.3 watchdog timer operation in stop mode (when ? ring-osc can be stopped by software? is selected by mask opt ion) ....................................................................................................... .......186 9.4.4 watchdog timer operation in halt mode (when ?r ing-osc can be stopped by software? is selected by mask opt ion) ....................................................................................................... .......188 chapter 10 a/d converter ................................................................................................... ...... 189 10.1 function of a/d converter ................................................................................................. ..... 189 10.2 configuration of a/d converter................................ ............................................................ .. 190 10.3 registers used in a/d converter ........................................................................................... 192 10.4 a/d converter operations.................................................................................................. ..... 196 10.4.1 basic operations of a/d c onverter ....................................................................................... .........196 10.4.2 input volt age and conversi on results .................................................................................... ........198 user?s manual u15836ej5v0ud 14 10.4.3 a/d converte r operati on mode ............................................................................................ ......... 199 10.5 how to read a/d converter char acteristics table............................................................... 202 10.6 cautions for a/d converter ................................................................................................ ..... 204 chapter 11 serial interface uart0 ( 11.1 functions of serial interface uart0.............................. ........................................................ 2 09 11.2 configuration of serial interf ace uart0 ............................................................................... 210 11.3 registers controlling serial in terface uart0....................................................................... 213 11.4 operation of serial interface uart0 ............................ .......................................................... 2 18 11.4.1 operatio n stop mode ..................................................................................................... .............. 218 11.4.2 asynchronous serial interface (u art) mode............................................................................... 219 11.4.3 dedicated baud rate generator ........................................................................................... ......... 225 chapter 12 serial interface uart6 ...................................................................................... 230 12.1 functions of serial interface uart6.............................. ........................................................ 2 30 12.2 configuration of serial interf ace uart6 ............................................................................... 234 12.3 registers controlling serial in terface uart6....................................................................... 237 12.4 operation of serial interface uart6 ............................ .......................................................... 2 45 12.4.1 operatio n stop mode ..................................................................................................... .............. 245 12.4.2 asynchronous serial interface (u art) mode............................................................................... 246 12.4.3 dedicated baud rate generator ........................................................................................... ......... 260 chapter 13 serial interface csi10 ........................................................................................ 2 67 13.1 functions of serial interface csi10.............................. ......................................................... . 267 13.2 configuration of serial interf ace csi10 ................................................................................. 26 7 13.3 registers controlling serial in terface csi10......................................................................... 269 13.4 operation of serial interface csi10 .......................... ............................................................. . 272 13.4.1 operatio n stop mode ..................................................................................................... .............. 272 13.4.2 3-wire se rial i/o mode.................................................................................................. ................ 273 chapter 14 interrupt functions............................................................................................. 280 14.1 interrupt function types .................................................................................................. ....... 280 14.2 interrupt sources and configuration ........................... .......................................................... 28 0 14.3 registers controlling interrupt function............................................................................... 283 14.4 interrupt servicing operati ons ............................................................................................ ... 289 14.4.1 maskable interrupt request ack nowledg ment............................................................................... 289 14.4.2 software interrupt request ack nowledg ment............................................................................... . 291 14.4.3 multiple inte rrupt servicing ............................................................................................ ............... 292 14.4.4 interrupt request hold.................................................................................................. ................. 295 chapter 15 standby function ................................................................................................ .. 296 15.1 standby function and configurat ion..................................................................................... 296 15.1.1 standby functi on ........................................................................................................ .................. 296 15.1.2 registers contro lling standby function .................................................................................. ....... 298 15.2 standby function operation................................................................................................ ... 301 15.2.1 halt mode............................................................................................................... ................... 301 15.2.2 stop mode ............................................................................................................... .................. 304 user?s manual u15836ej5v0ud 15 chapter 16 reset function .................................................................................................. ..... 308 16.1 register for confirming reset source .................................................................................. 314 chapter 17 clock monitor ................................................................................................... ..... 315 17.1 functions of clock monitor ................................................................................................ .... 315 17.2 configuration of clock monitor ............................................................................................ .. 315 17.3 register controlling clock monitor ......................... .............................................................. 3 16 17.4 operation of clock monitor................................................................................................ ..... 317 chapter 18 power-on-clear circuit ..................................................................................... 322 18.1 functions of power-on-cl ear circuit ..................................................................................... 32 2 18.2 configuration of power-on-clear circuit............................................................................... 323 18.3 operation of power-on-clear circuit ....................... .............................................................. 32 3 18.4 cautions for power-on-clear circ uit...................................................................................... 3 24 chapter 19 low-voltage detector ....................................................................................... 326 19.1 functions of low-voltage detector ....................................................................................... 32 6 19.2 configuration of low-voltage de tector................................................................................. 327 19.3 registers controlling low-voltage detector ........................................................................ 327 19.4 operation of low-voltage detector............................ ............................................................ 3 30 19.5 cautions for low-voltage detector............................ ............................................................ 3 34 chapter 20 mask options .................................................................................................... ....... 337 chapter 21 21.1 internal memory size switching register .............. ............................................................... 339 21.2 writing with flash programmer............................................................................................. . 340 21.3 programming environment................................................................................................... .. 347 21.4 communication mode ........................................................................................................ ..... 347 21.5 handling of pins on board................................................................................................. ..... 351 21.5.1 v pp pin ........................................................................................................................... ...............351 21.5.2 serial in terface pins ................................................................................................... ...................351 21.5.3 reset pin............................................................................................................... .....................353 21.5.4 port pi ns ............................................................................................................... ........................353 21.5.5 other signal pins....................................................................................................... ....................353 21.5.6 powe r supply ............................................................................................................ ....................353 21.6 programming method........................................................................................................ ...... 354 21.6.1 controllin g flash memory ................................................................................................ ..............354 21.6.2 flash memory programmi ng m ode........................................................................................... ....354 21.6.3 selecting co mmunicati on mode............................................................................................ ........355 21.6.4 communicati on commands .................................................................................................. ........356 chapter 22 instruction set ................................................................................................. ..... 357 22.1 conventions used in operation list........................ .............................................................. 35 7 22.1.1 operand identifiers and specificati on met hods ........................................................................... ..357 22.1.2 description of operation column ......................................................................................... ..........358 22.1.3 description of fl ag operati on colu mn .................................................................................... ........358 22.2 operation list............................................................................................................ ............... 359 user?s manual u15836ej5v0ud 16 22.3 instructions listed by addressing type...................... .......................................................... 367 chapter 23 electrical specifications (standard products, (a) grade products) (expanded-specification prod ucts) ...................................... 370 chapter 24 electrical specifications (standard products, (a) grade products) (conventional products)........................................................... 388 chapter 25 electrical specifications ((a1) grade products) ................................ 405 chapter 26 electrical specifications ((a2 ) grade products) ................................ 420 chapter 27 package drawing................................................................................................. .. 430 chapter 28 recommended soldering conditions........................................................... 431 chapter 29 cautions for wait.............................................................................................. ... 433 29.1 cautions for wait......................................................................................................... ............. 433 29.2 peripheral hardware that generates wait .................. .......................................................... 434 29.3 example of wait occurrence .......................................... ...................................................... .. 435 appendix a development tools............................................................................................... 436 a.1 software package........................................................................................................... .......... 440 a.2 language processing software...................................... ........................................................ 4 40 a.3 control software ........................................................................................................... ........... 441 a.4 flash memory writing tools ................................................................................................. .. 441 a.5 debugging tools (hardware) ................................................................................................. . 442 a.5.1 when using in-circuit emulat ors ie-78k0-ns and ie-78k0- ns-a ................................................ 442 a.5.2 when using in-circuit emulator ie- 78k0k1- et............................................................................. 4 43 a.5.3 when using in-circuit emulator qb- 78k0kx1 h............................................................................ 444 a.6 debugging tools (software) ................................................................................................. .. 445 appendix b notes on target system design ................................................................... 446 b.1 when using ie-78k0-ns, ie-78k0-ns-a, or ie- 78k0k1-et .................................................. 446 b.2 when using qb-78k0kx1h..................................................................................................... 448 appendix c register index .................................................................................................. ....... 449 c.1 register index (in alphabetical order with resp ect to register names) .......................... 449 c.2 register index (in alphabetical order with resp ect to register symbol) ......................... 452 appendix d list of cautions ............................................................................................... ...... 455 appendix e revision history................................................................................................ ...... 475 e.1 major revisions in this edition............................................................................................ .. 475 e.2 revision history of previous editions ......................... .......................................................... 477 user?s manual u15836ej5v0ud 17 chapter 1 outline 1.1 expanded-specification products and conventional products (standard products, (a) grade products only) the expanded-specification products and conventional products refer to the following products. expanded-specification pro ducts: products with a rank note e or after ? mask rom version for which order was received on or after mid-march, 2004 ? flash memory version for which order was received on or after mid-july, 2004 conventional products: products with rank note i or k ? products other than the above expanded-specification products note the rank is indicated by the 5th digit from the le ft in the 3rd column (lot number) marked on the package. lot number year code week code rank expanded-specification products and conventional products of standard products and (a) grade products differ in the operating frequency ratings. table 1-1 show s the differences between these products. table 1-1. differences between expanded-specification products and c onventional products of standard products and (a) grade products power supply voltage (v dd ) guaranteed operating speed (minimum instruction execution time) conventional products (rank: i, k) expanded-specification products (rank: e or after) 12 mhz (0.166 s) not used 4.0 to 5.5 v 10 mhz (0.2 s) 4.0 to 5.5 v 3.5 to 4.0 v 8.38 mhz (0.238 s) 3.3 to 4.0 v 3.0 to 3.5 v 5 mhz (0.4 s) 2.7 to 3.3 v 2.5 to 3.0 v cautions 1. the specifications of the peripheral f unctions (such as the timer, serial interface, and a/d converter) at v dd = 2.7 to 5.5 v remain unchanged. consequently when selecting the count clock or base clock of a peri pheral function, set to satisfy the followin g conditions. ? v dd = 4.0 to 5.5 v: count clock or base clock 10 mhz ? v dd = 3.3 to 4.0 v: count clock or base clock 8.38 mhz ? v dd = 2.7 to 3.3 v: count clock or base clock 5 mhz ? v dd = 2.5 to 2.7 v: count clock or base clock 2.5 mhz 2. rewrite the flash me mory within the ranges of f x = 2 to 10 mhz and v dd = 2.7 to 5.5 v as before. chapter 1 outline user?s manual u15836ej5v0ud 18 1.2 features { minimum instruction execution time can be changed from high speed (0.166 s: @ 12 mhz operation with x1 input clock) to low-speed (2.666 s: @ 12 mhz operation with x1 input clock) { general-purpose register: 8 bits 32 registers (8 bits 8 registers 4 banks) { rom, ram capacities part number item program memory (rom) data memory (internal high-speed ram) pd780101 8 kb 512 bytes pd780102 16 kb pd780103 mask rom 24 kb pd78f0103 flash memory 24 kb note 768 bytes note the internal flash memory and internal high-speed ram capacities can be changed using the internal memory size switching register (ims). { on-chip power-on-clear (poc) circuit and low-voltage detector (lvi) { short startup is possible via the cpu default start using the on-chip ring-osc { on-chip clock monitor function using on-chip ring-osc { on-chip watchdog timer (operable with ring-osc clock) { i/o ports: 22 { timer: 5 channels { serial interface: 2 channels uart (lin (local interconnect network)-bus supported): 1 channel csi1/uart note 1 : 1 channel ( pd780101 only, csi1: 1 channel) { 10-bit resolution a/d converter: 4 channels { supply voltage: v dd = 2.5 to 5.5 v notes 2, 3 (expanded-specification products of standard and (a) grade products) v dd = 2.7 to 5.5 v notes 2, 3 (conventional products of st andard and (a) grade products) v dd = 3.3 to 5.5 v note 3 ((a1) grade and (a2) grade products) { operating ambient temperature: t a = ? 40 to +85 c (standard and (a) grade products) t a = ? 40 to +105 c (flash memory version of (a1) grade product) t a = ? 40 to +110 c (mask rom version of (a1) grade product) t a = ? 40 to +125 c (mask rom version of (a2) grade product) notes 1. select either of the functions of these alternate-function pins. 2. if the poc circuit detection voltage (v poc ) is used with 2.85 v 0.15 v, then use t he products in the voltage range of 3.0 to 5.5 v. 3. if the poc circuit detection voltage (v poc ) is used with 3.5 v 0.2 v, then use the products in the voltage range of 3.7 to 5.5 v. chapter 1 outline user?s manual u15836ej5v0ud 19 1.3 applications { automotive equipment ? ? { home audio, car audio { av equipment { pc peripheral equipment (keyboards, etc.) { household electrical appliances ? ? { industrial equipment ? ? ? chapter 1 outline user?s manual u15836ej5v0ud 20 1.4 ordering information (1) mask rom version part number package quality grade flash memory version part number package quality grade chapter 1 outline user?s manual u15836ej5v0ud 21 mask rom versions ( chapter 1 outline user?s manual u15836ej5v0ud 22 1.5 pin configuration (top view) ? chapter 1 outline user?s manual u15836ej5v0ud 23 1.6 kx1 series lineup 1.6.1 78k0/kx1, 78k0/ kx1+ product lineup mask rom: 24 kb, ram: 768 b mask rom: 16 kb, ram: 768 b mask rom: 8 kb, ram: 512 b pd780101 78k0/kb1 ? ? ? ? ? ? ? chapter 1 outline user?s manual u15836ej5v0ud 24 the list of functions in the 78k0/kx1 is shown below. part number item 78k0/kb1 78k0/kc1 78k0/kd1 78k0/ke1 78k0/kf1 number of pins 30 pins 44 pi ns 52 pins 64 pins 80 pins mask rom 8 16/ 24 ? 8/ 16 24/ 32 ? 8/ 16 24/ 32 ? 8/ 16 24/ 32 ? 48/ 60 ? 24/ 32 48/ 60 ? flash memory ? 24 ? 32 ? 32 ? 32 ? 60 ? 60 internal memory (kb) ram 0.5 0.75 0.5 1 0.5 1 0.5 1 2 1 2 power supply voltage v dd = 2.5 to 5.5 v notes 1, 2 minimum instruction execution time 0.166 s (when 12 mhz, v dd = 4.0 to 5.5 v) 0.2 s (when 10 mhz, v dd = 3.5 to 5.5 v) 0.238 s (when 8.38 mhz, v dd = 3.0 to 5.5 v) 0.4 s (when 5 mhz, v dd = 2.5 to 5.5 v) chapter 1 outline user?s manual u15836ej5v0ud 25 the list of functions in the 78k0/kx1+ is shown below. part number item 78k0/kb1+ 78k0/kc1+ 78k0/kd1+ 78k0/ke1+ 78k0/kf1+ number of pins 30 pins 44 pi ns 52 pins 64 pins 80 pins flash memory 8 16/24 16 24/32 16 24/32 16 24/32 48/60 60 internal memory (kb) ram 0.5 0.75 0.5 1 0.5 1 0.5 1 2 2 power supply voltage v dd = 2.5 to 5.5 v (with ring-osc clock or subclock: v dd = 2.0 to 5.5 v note 1 ) minimum instruction execution time 0.125 s (when 16 mhz, v dd = 4.0 to 5.5 v), 0.2 s (when 10 mhz, v dd = 3.5 to 5.5 v), 0.238 s (when 8.38 mhz, v dd = 3.0 to 5.5 v), 0.4 s (when 5 mhz, v dd = 2.5 to 5.5 v) crystal/ceramic 2 to 16 mhz rc 3 to 4 mhz ? subclock ? 32.768 khz clock ring-osc 240 khz (typ.) cmos i/o 17 19 26 38 54 cmos input 4 8 cmos output 1 ports n-ch open-drain i/o ? 4 16 bits (tm0) 1 ch 2 ch 8 bits (tm5) 1 ch 2 ch 8 bits (tmh) 2 ch for watch ? 1 ch timer wdt 1 ch 3-wire csi note 2 1 ch 2 ch automatic transmit/ receive 3-wire csi ? 1 ch uart note 2 ? 1 ch serial interface uart supporting lin-bus 1 ch 10-bit a/d converter 4 ch 8 ch external 6 7 8 9 9 interrupts internal 11 12 15 16 19 20 key return input ? 4 ch 8 ch reset pin provided poc 2.1 v 0.1 v (detection voltage is fixed) lvi 2.35 v/2.6 v/2.85 v/3.1 v/3.3 v 0.15 v/3.5 v/3.7 v/3.9 v/4.1 v/4.3 v 0.2 v (selectable by software) clock monitor provided reset wdt provided clock output/buzzer output ? clock output only provided external bus interface ? provided multiplier/divider ? 16 bits 16 bits, 32 bits 16 bits rom correction ? provided ? self-programming function provided product with on-chip debug function pd78f0114hd, 78f0124hd, 78f0138hd, 78f0148hd standby function halt/stop mode operating ambient temperature t a = ? 40 to +85 c notes 1. because the poc circuit detection voltage (v poc ) is 2.1 v 0.1 v, use the products in the voltage range of 2.2 to 5.5 v. 2. select either of the functions of these alternate-function pins. chapter 1 outline user?s manual u15836ej5v0ud 26 1.6.2 v850es/kx1, v850es/kx1+ product lineup v850es/ke1 ? ? ? ? ? ? ? ? chapter 1 outline user?s manual u15836ej5v0ud 27 the list of functions in the v850es/kx1 is shown below. part number item v850es/ke1 v850es/kf1 v850es/kg1 v850es/kj1 number of pins 64 pins 80 pins 100 pins 144 pins mask rom 96/128 ? 64/ 96 128 ? 256 ? 64/ 96 128 ? 256 ? 96/ 128 ? 256 ? flash memory ? 128 ? ? 128 ? 256 ? ? 128 ? 256 ? 128 ? 256 internal memory (kb) ram 4 4 6 12 4 6 16 6 16 power supply voltage v dd = 2.7 to 5.5 v minimum instruction execution time 50 ns @ 20 mhz x1 input 2 to 10 mhz subclock 32.768 khz clock ring-osc ? cmos input 8 8 8 16 cmos i/o 43 59 76 112 ports n-ch open-drain i/o 1 2 4 6 16 bits (tmp) 1 ch ? 1 ch ? 1 ch ? 1 ch 16 bits (tm0) 1 ch 2 ch 4 ch 6 ch 8 bits (tm5) 2 ch 2 ch 2 ch 2 ch 8 bits (tmh) 2 ch 2 ch 2 ch 2 ch interval timer 1 ch 1 ch 1 ch 1 ch for watch 1 ch 1 ch 1 ch 1 ch wdt1 1 ch 1 ch 1 ch 1 ch timer wdt2 1 ch 1 ch 1 ch 1 ch rto 6 bits 1 ch 6 bits 1 ch 6 bits 1 ch 6 bits 2 ch csi 2 ch 2 ch 2 ch 3 ch automatic transmit/ receive 3-wire csi ? 1 ch 2 ch 2 ch uart 2 ch 2 ch 2 ch 3 ch uart supporting lin-bus ? ? ? ? serial interface i 2 c note 1 ch 1 ch 1 ch 2 ch address space ? 128 kb 3 mb 15 mb address bus ? 16 bits 22 bits 24 bits external bus mode ? multiplexed mode only multiplexed/separate mode dma controller ? ? ? ? 10-bit a/d converter 8 ch 8 ch 8 ch 16 ch 8-bit d/a converter ? ? 2 ch 2 ch external 8 8 8 8 interrupts internal 26 26 29 31 34 40 43 key return input 8 ch 8 ch 8 ch 8 ch reset pin provided poc not provided lvi not provided clock monitor not provided wdt1 provided reset wdt2 provided rom correction 4 points regulator not provided provided standby function halt/idle/stop/sub-idle mode operating ambient temperature t a = ? 40 to +85 c note provided in the y version only. chapter 1 outline user?s manual u15836ej5v0ud 28 the list of functions in the v850es/kx1+ is shown below. part number item v850es/ke1+ v850es/kf1+ v850es/kg1+ v850es/kj1+ number of pins 64 pins 80 pins 100 pins 144 pins mask rom 96/128 ? 128 256 ? 128/256 ? 128/256 ? flash memory ? 128 ? ? 256 ? 256 ? 256 internal memory (kb) ram 4 6 12 6 16 6 16 power supply voltage v dd = 2.7 to 5.5 v minimum instruction execution time 50 ns @ 20 mhz x1 input 2 to 10 mhz subclock 32.768 khz clock ring-osc 240 khz (typ.) cmos input 8 8 8 16 cmos i/o 43 59 76 112 ports n-ch open-drain i/o 1 2 4 6 16 bits (tmp) 1 ch 1 ch 1 ch 1 ch 16 bits (tm0) 1 ch 2 ch 4 ch 6 ch 8 bits (tm5) 2 ch 2 ch 2 ch 2 ch 8 bits (tmh) 2 ch 2 ch 2 ch 2 ch interval timer 1 ch 1 ch 1 ch 1 ch for watch 1 ch 1 ch 1 ch 1 ch wdt1 1 ch 1 ch 1 ch 1 ch timer wdt2 1 ch 1 ch 1 ch 1 ch rto 6 bits 1 ch 6 bits 1 ch 6 bits 1 ch 6 bits 2 ch csi 2 ch 2 ch 2 ch 3 ch automatic transmit/ receive 3-wire csi ? 1 ch 2 ch 2 ch uart 1 ch 1 ch 1 ch 2 ch uart supporting lin-bus 1 ch 1 ch 1 ch 1 ch serial interface i 2 c note 1 ch 1 ch 1 ch 2 ch address space ? 128 kb 3 mb 15 mb address bus ? 16 bits 22 bits 24 bits external bus mode ? multiplexed mode only multiplexed/separate mode dma controller ? ? 4 ch 4 ch 10-bit a/d converter 8 ch 8 ch 8 ch 16 ch 8-bit d/a converter ? ? 2 ch 2 ch external 9 9 9 9 interrupts internal 27 30 42 48 key return input 8 ch 8 ch 8 ch 8 ch reset pin provided poc fixed to 2.7 v or lower lvi 3.1 v/3.3 v 0.15 v or 3.5 v/3.7 v/3.9 v/4.1 v/4.3 v 0.2 v (selectable by software) clock monitor provided (m onitoring by ring-osc) wdt1 provided reset wdt2 provided rom correction 4 points regulator not provided provided standby function halt/idle/stop/sub-idle mode operating ambient temperature t a = ? 40 to +85 c note provided in the y version only. chapter 1 outline user?s manual u15836ej5v0ud 29 1.7 block diagram 16-bit timer/ event counter 00 to00/ti010/p01 ti000/p00 serial interface csi10 si1/p11 so10/p12 sck10/p10 ani0/p20 to ani3/p23 interrupt control 8-bit timer h0 toh0/p15 8-bit timer h1 toh1/p16 ti50/to50/p17 8-bit timer/ event counter 50 4 a/d converter 78k/0 cpu core internal high-speed ram rom (flash memory) port 0 p00 to p03 4 port 1 p10 to p17 port 2 p20 to p23 4 port 3 p30 to p33 4 port 12 p120 port 13 p130 system control reset x1 x2 rxd0 note /p11 txd0 note /p10 serial interface uart0 note watchdog timer rxd6/p14 txd6/p13 serial interface uart6 v ss ic (v pp ) v dd av ref av ss intp1/p30 to intp4/p33 4 intp0/p120 clock monitor power-on-clear/ low voltage indicator poc/lvi control reset control ring-osc 8 note chapter 1 outline user?s manual u15836ej5v0ud 30 1.8 outline of functions (1/2) item pd780101 pd780102 pd780103 pd78f0103 rom 8 kb 16 kb 24 kb 24 kb (flash memory) internal memory high-speed ram 512 bytes 768 bytes memory space 64 kb x1 input clock (oscillation frequency) ceramic/crystal/external clock oscillation expanded- specification products of standard and (a) grade products 2 to 12 mhz: v dd = 4.0 to 5.5 v, 2 to 10 mhz: v dd = 3.5 to 5.5 v, 2 to 8.38 mhz: v dd = 3.0 to 5.5 v, 2 to 5 mhz: v dd = 2.5 to 5.5 v conventional products of standard and (a) grade products 2 to 10 mhz: v dd = 4.0 to 5.5 v, 2 to 8.38 mhz: v dd = 3.3 to 5.5 v, 2 to 5 mhz: v dd = 2.7 to 5.5 v (a1) grade products 2 to 10 mhz: v dd = 4.5 to 5.5 v, 2 to 8.38 mhz: v dd = 4.0 to 5.5 v, 2 to 5 mhz: v dd = 3.3 to 5.5 v (a2) grade products 2 to 8.38 mhz: v dd = 4.0 to 5.5 v, 2 to 5 mhz: v dd = 3.3 to 5.5 v ring-osc clock (oscillation frequency) on-chip ring oscillation (240 khz (typ.): v dd = 2.5 to 5.5 v) general-purpose registers 8 bits 32 registers (8 bits 8 registers 4 banks) minimum instruction execution time 0.166 s/0.333 s/0.666 s/1.333 s/2.666 s (x1 input clock: @ f xp = 12 mhz operation) 8.3 s/16.6 s/33.2 s/66.4 s/132.8 s (typ.) (ring-osc clock: @ f r = 240 khz (typ.) operation) instruction set 16-bit operation multiply/divide (8 bits 8 bits, 16 bits 8 bits) bit manipulate (set, reset, test, and boolean operation) bcd adjust, etc. i/o ports total: 22 cmos i/o 17 cmos input 4 cmos output 1 timers 16-bit timer/event counter: 1 channel 8-bit timer/event counter: 1 channel 8-bit timer: 2 channels watchdog timer: 1 channel timer outputs 4 (pwm: 3) a/d converter 10-bit resolution 4 channels serial interface uart mode supporting lin-bus: 1 channel 3-wire serial i/o mode/uart mode note : 1 channel ( pd780101 only, 3-wire serial i/o mode: 1 channel) internal 10 12 vectored interrupt sources external 6 reset reset using reset pin internal reset by watchdog timer internal reset by clock monitor internal reset by power-on-clear internal reset by low-voltage detector note select either of the functions of these alternate-function pins. chapter 1 outline user?s manual u15836ej5v0ud 31 (2/2) item pd780101 pd780102 pd780103 pd78f0103 supply voltage expanded-specification products of standard and (a) grade products: v dd = 2.5 to 5.5 v notes 1, 2 conventional products of standard and (a) grade products: v dd = 2.7 to 5.5 v notes 1, 2 (a1) grade and (a2) grade products: v dd = 3.3 to 5.5 v note 2 operating ambient temperature standard and (a) grade products: t a = ? 40 to +85 c (a1) grade products: t a = ? 40 to +110 c (mask rom version), ? 40 to +105 c (flash memory version) ? (a2) grade products: t a = ? 40 to +125 c (mask rom version) package 30-pin plastic ssop (7.62 mm (300)) notes 1. if the poc circuit detection voltage (v poc ) is used with 2.85 v 0.15 v, then use the pr oducts in the voltage range of 3.0 to 5.5 v. 2. if the poc circuit detection voltage (v poc ) is used with 3.5 v 0.2 v, then use the products in the voltage range of 3.7 to 5.5 v. an outline of the timer is shown below. 8-bit timers h0 and h1 16-bit timer/event counter 00 8-bit timer/event counter 50 tmh0 tmh1 watchdog timer interval timer 1 channel 1 channel 1 channel 1 channel ? external event counter 1 channel 1 channel ? ? ? operation mode watchdog timer ? ? ? ? 1 channel timer output 1 output 1 output 1 output 1 output ? ppg output 1 output ? ? ? ? pwm output ? 1 output 1 output 1 output ? pulse width measurement 2 inputs ? ? ? ? square-wave output 1 output 1 output 1 output 1 output ? function interrupt source 2 1 1 1 ? user?s manual u15836ej5v0ud 32 chapter 2 pin functions 2.1 pin function list there are two types of pin i/o buffer power supplies: av ref and v dd . the relationship between these power supplies and the pins is shown below. table 2-1. pin i/o buffer power supplies power supply corresponding pins av ref p20 to p23 v dd pins other than p20 to p23 (1) port pins pin name i/o function after reset alternate function p00 ti000 p01 ti010/to00 p02 p03 i/o port 0. 4-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input ? p10 sck10/txd0 note p11 si10/rxd0 note p12 so10 p13 txd6 p14 rxd6 p15 toh0 p16 toh1/intp5 p17 i/o port 1. 8-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input ti50/to50 p20 to p23 input port 2. 4-bit input-only port. input ani0 to ani3 p30 to p33 i/o port 3. 4-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input intp1 to intp4 p120 i/o port 12. 1-bit i/o port. use of an on-chip pull-up resistor can be specified by a software setting. input intp0 p130 output port 13. 1-bit output-only port. output ? note txd0 and rxd0 are available only in the pd780102, 780103, and 78f0103. chapter 2 pin functions user?s manual u15836ej5v0ud 33 (2) non-port pins pin name i/o function after reset alternate function intp0 p120 intp1 to intp4 p30 to p33 intp5 input external interrupt request input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified input p16/toh1 si10 input serial data input to serial interface input p11/rxd0 note so10 output serial data output from serial interface input p12 sck10 i/o clock input/output for serial interface input p10/txd0 note rxd0 note p11/si10 rxd6 input serial data input to asynch ronous serial interface input p14 txd0 note p10/sck10 txd6 output serial data output from asyn chronous serial interface input p13 ti000 external count clock input to 16-bit timer/event counter 00 capture trigger input to captur e registers (cr000, cr010) of 16-bit timer/event counter 00 p00 ti010 input capture trigger input to capture register (cr000) of 16-bit timer/event counter 00 input p01/to00 to00 output 16-bit timer/event counter 00 output input p01/ti010 ti50 input external count clock input to 8-bit timer/event counter 50 input p17/to50 to50 output 8-bit timer/event counter 50 output input p17/ti50 toh0 8-bit timer h0 output p15 toh1 output 8-bit timer h1 output input p16/intp5 ani0 to ani3 input a/d converter analog input input p20 to p23 av ref input a/d converter reference voltage input and positive power supply for port 2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? chapter 2 pin functions user?s manual u15836ej5v0ud 34 2.2 description of pin functions 2.2.1 p00 to p03 (port 0) p00 to p03 function as a 4-bit i/o port. these pins also function as timer i/o. the following operation modes can be specified in 1-bit units. (1) port mode p00 to p03 function as a 4-bit i/o port. p00 to p03 can be set to input or output in 1-bit units using port mode register 0 (pm0). use of an on-chip pull-up resistor can be specified by pull-up resistor option register 0 (pu0). (2) control mode p00 to p03 function as timer i/o. (a) ti000 this is the pins for inputting an external count clock to 16-bit timer/event counter 00 and is also for inputting a capture trigger signal to the ca pture registers (cr000, cr010) of 16-bit timer/event counter 00. (b) ti010 this is the pin for inputting a capture trigger signal to the capture register (cr000) of 16-bit timer/event counter 00. (c) to00 this is a timer output pin. 2.2.2 p10 to p17 (port 1) p10 to p17 function as an 8-bit i/o port. these pins also function as pins for ex ternal interrupt re quest input, serial interface data i/o, cl ock i/o, and timer i/o. the following operation modes can be specified in 1-bit units. (1) port mode p10 to p17 function as an 8-bit i/o port. p10 to p17 can be set to input or output in 1-bit units using port mode register 1 (pm1). use of an on-chip pull-up resistor can be specified by pull-up resistor option register 1 (pu1). (2) control mode p10 to p17 function as external interrupt request in put, serial interface data i/o, clock i/o, and timer i/o. (a) si10 this is a serial data input pi n of the serial interface. (b) so10 this is a serial data output pi n of the serial interface. (c) sck10 this is a serial clock i/o pi n of the serial interface. (d) rxd0 note , rxd6 these are the serial data input pins of the asynchronous serial interface. chapter 2 pin functions user?s manual u15836ej5v0ud 35 (e) txd0 note , txd6 these are serial data output pins of the asynchronous serial interface. note txd0 and rxd0 are available only in the pd780102, 780103, and 78f0103. (f) ti50 this is the pin for inputting an external c ount clock to 8-bit timer/event counter 50. (g) to50, toh0, and toh1 these are timer output pins. (h) intp5 this is an external interrupt request input pin for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. 2.2.3 p20 to p23 (port 2) p20 to p23 function as a 4-bit input-only port. these pins also function as pins for a/d converter analog input. the following operation modes can be specified in 1-bit units. (1) port mode p20 to p23 function as a 4-bit input-only port. (2) control mode p20 to p23 function as a/d converter analog input pins (ani0 to ani3). when using these pins as analog input pins, see (5) ani0/p20 to ani3/p23 in 10.6 cautions for a/d converter . 2.2.4 p30 to p33 (port 3) p30 to p33 function as a 4-bit i/o port. these pins also function as pins for exter nal interrupt request input. the following operation modes can be specified in 1-bit units. (1) port mode p30 to p33 function as a 4-bit i/o port. p30 to p33 can be set to input or output in 1-bit units using port mode register 3 (pm3). use of an on-chip pull-up resistor can be specified by pull-up resistor option register 3 (pu3). (2) control mode p30 to p33 function as external interrupt request input pins (intp1 to intp4) for which the valid edge (rising edge, falling edge, or both rising an d falling edges) can be specified. 2.2.5 p120 (port 12) p120 functions as a 1-bit i/o port. this pin also func tions as a pin for external interrupt request input. the following operation modes can be specified. (1) port mode p120 functions as a 1-bit i/o port. p120 can be set to input or output using port mode register 12 (pm12). use of an on-chip pull-up resistor can be specified by pull-up resistor option register 12 (pu12). chapter 2 pin functions user?s manual u15836ej5v0ud 36 (2) control mode p120 functions as an external interrupt request input pin (intp0) for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. 2.2.6 p130 (port 13) p130 functions as a 1-bit output-only port. 2.2.7 av ref this is the a/d converter reference voltage input pin. when a/d converter is not used, connect this pin directly to v dd . 2.2.8 av ss this is the a/d converter ground potenti al pin. even when the a/d converter is not used, always use this pin with the same potential as the v ss pin. 2.2.9 reset this is the active-low system reset input pin. 2.2.10 x1 and x2 these are the pins for connecting a reso nator for x1 input clock oscillation. when supplying an external clock, input a signal to t he x1 pin and input the inverse signal to the x2 pin. 2.2.11 v dd this is the positive power supply pin. 2.2.12 v ss this is the ground potential pin. 2.2.13 v pp (flash memory versions only) this is a pin for flash memory programming mode setting and high-voltage application for program write/verify. connect to v ss in the normal operation mode. 2.2.14 ic (mask rom versions only) the ic (internally connected) pin is provided to set the test mode to check the 78k0/kb1 at shipment. connect it directly to v ss with the shortest possible wir e in the normal operation mode. when a potential difference is produced between the ic pin and the v ss pin because the wiring between these two pins is too long or external noise is input to t he ic pin, the user?s progr am may not operate normally. ? connect the ic pin directly to v ss . as short as possible ic v ss chapter 2 pin functions user?s manual u15836ej5v0ud 37 2.3 pin i/o circuits and recommended connection of unused pins table 2-2 shows the types of pin i/o circuit and the recommended connections of unused pins. see figure 2-1 for the configuration of the i/o circuits of each type. table 2-2. pin i/o circuit types pin name i/o circuit type i/o recommended connection of unused pins p00/ti000 p01/ti010/to00 p02 p03 p10/sck10/txd0 note p11/si10/rxd0 note 8-a p12/so10 p13/txd6 5-a p14/rxd6 8-a p15/toh0 5-a p16/toh1/intp5 p17/ti50/to50 8-a i/o input: independently connect to v dd or v ss via a resistor. output: leave open. p20/ani0 to p23/ani3 9-c input connect to v dd or v ss . p30/intp1 to p33/intp4 input: independently connect to v ss via a resistor. output: leave open. p120/intp0 8-a i/o input: independently connect to v dd or v ss via a resistor. output: leave open. p130 3-c output leave open. reset 2 input connect to v dd . av ref input connect directly to v dd . av ss ic connect directly to v ss . v pp ? ? chapter 2 pin functions user?s manual u15836ej5v0ud 38 figure 2-1. pin i/o circuit list type 3-c type 2 type 8-a type 5-a type 9-c schmitt-triggered input with hysteresis characteristics in pull-up enable data output disable v dd p-ch v dd p-ch in/out n-ch v dd p-ch n-ch data out in comparator v ref (threshold voltage) av ss p-ch n-ch input enable + ? pull-up enable data output disable input enable v dd p-ch v dd p-ch in/out n-ch user?s manual u15836ej5v0ud 39 chapter 3 cpu architecture 3.1 memory space products in the 78k0/kb1 can each access a 64 kb memory s pace. figures 3-1 to 3-4 show the memory maps. caution regardless of the internal memory capacity, the initial values of internal memory size switching register (ims) of all pr oducts in the 78k0/kb1 are fixed (ims = cfh). therefore, set the value corresponding to each pro duct as indicated below. table 3-1. internal memory size switching register (ims) set value internal memory size switching register (ims) chapter 3 cpu architecture user?s manual u15836ej5v0ud 40 figure 3-1. memory map ( chapter 3 cpu architecture user?s manual u15836ej5v0ud 41 figure 3-2. memory map ( chapter 3 cpu architecture user?s manual u15836ej5v0ud 42 figure 3-3. memory map ( chapter 3 cpu architecture user?s manual u15836ej5v0ud 43 figure 3-4. memory map ( chapter 3 cpu architecture user?s manual u15836ej5v0ud 44 3.1.1 internal program memory space the internal program memory space stores the program and table data. normally, it is addressed with the program counter (pc). 78k0/kb1 products incorporate internal rom (ma sk rom or flash memory), as shown below. table 3-2. intern al rom capacity internal rom part number structure capacity chapter 3 cpu architecture user?s manual u15836ej5v0ud 45 3.1.2 internal data memory space 78k0/kb1 products incorporate the following internal high-speed ram. table 3-4. internal high-speed ram capacity part number internal high-speed ram pd780101 512 8 bits (fd00h to feffh) pd780102 pd780103 pd78f0103 768 8 bits (fc00h to feffh) the 32-byte area fee0h to feffh is assigned to four g eneral-purpose register banks consisting of eight 8-bit registers per bank. this area cannot be used as a program area in which instructions are written and executed. the internal high-speed ram can also be used as a stack memory. 3.1.3 special function register (sfr) area on-chip peripheral hard ware special function registers (sfrs) ar e allocated in the area ff00h to ffffh (see table 3-5 special function register list in 3.2.3 special func tion registers (sfrs) ). caution do not access addresses to which sfrs are not assigned. chapter 3 cpu architecture user?s manual u15836ej5v0ud 46 3.1.4 data memory addressing addressing refers to the method of specifying the addre ss of the instruction to be ex ecuted next or the address of the register or memory relevant to the execution of instructions. several addressing modes are provided for addressing the memo ry relevant to the executi on of instructions for the 78k0/kb1, based on operability and other considerations. for areas containing data memory in particular, special addressing methods designed for the functions of special function registers (sfr) and general-purpose registers are available for use. figures 3-5 to 3-8 show the correspon dence between data memory and addressing. for details of each addressing mode, see 3.4 operand address addressing . figure 3-5. correspondence between data memory and addressing ( chapter 3 cpu architecture user?s manual u15836ej5v0ud 47 figure 3-6. correspondence between data memory and addressing ( chapter 3 cpu architecture user?s manual u15836ej5v0ud 48 figure 3-7. correspondence between data memory and addressing ( chapter 3 cpu architecture user?s manual u15836ej5v0ud 49 figure 3-8. correspondence between data memory and addressing ( chapter 3 cpu architecture user?s manual u15836ej5v0ud 50 3.2 processor registers 78k0/kb1 products incorporate t he following processor registers. 3.2.1 control registers the control registers control the program sequence, statuses and stack memory. the control registers consist of a program counter (pc), a program status word (psw) and a stack pointer (sp). (1) program counter (pc) the program counter is a 16-bit regist er that holds the address information of the next program to be executed. in normal operation, the pc is automatically incremented ac cording to the number of bytes of the instruction to be fetched. when a branch instruction is execut ed, immediate data and regi ster contents are set. reset input sets the reset vector table values at addresses 0000h and 0001h to the program counter. figure 3-9. format of program counter 15 0 pc pc15 pc14 pc13 pc12 pc11 pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 (2) program status word (psw) the program status word is an 8-bit regi ster consisting of various flags to be set/reset by instruction execution. program status word contents are automatically stacked upon interrupt request generation or push psw instruction execution and are reset upon executi on of the retb, reti and pop psw instructions. reset input sets the psw to 02h. figure 3-10. format of program status word 7 0 psw ie z rbs1 ac rbs0 0 isp cy (a) interrupt enable flag (ie) this flag controls the interrupt request acknowledgment operations of the cpu. when 0, the ie flag is set to the interrupt disabl ed (di) state, and maskable interrupt requests are all disabled. when 1, the ie flag is set to the interrupt enabled (ei) state and interrupt request acknowledgment enable is controlled with an in-service priority flag (isp), an interrupt mask flag for various interrupt sources and a priority specification flag. the ie flag is reset (0) upon di instruction executi on or interrupt acknowledgment and is set (1) upon ei instruction execution. (b) zero flag (z) when the operation result is zero, this flag is se t (1). it is reset (0 ) in all other cases. chapter 3 cpu architecture user?s manual u15836ej5v0ud 51 (c) register bank select flags (rbs0 and rbs1) these are 2-bit flags to select one of the four register banks. in these flags, the 2-bit information that indicates th e register bank selected by sel rbn instruction execution is stored. (d) auxiliary carry flag (ac) if the operation result has a carry from bit 3 or a borrow at bi t 3, this flag is set (1). it is reset (0) in all other cases. (e) in-service priority flag (isp) this flag manages the priority of acknowledgeable ma skable vectored interrupts. when this flag is 0, low- level vectored interrupt requests specified by a priori ty specification flag register (pr0l, pr0h, pr1l) (see 14.3 (3) priority specification fl ag registers (pr0l, pr0h, pr1l) ) can not be acknowledged. actual request acknowledgment is controlled by the interrupt enable flag (ie). (f) carry flag (cy) this flag stores on overflow or underflow upon add/subt ract instruction execution. it stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit operation instruction execution. (3) stack pointer (sp) this is a 16-bit register to hold the start address of t he memory stack area. only the internal high-speed ram area can be set as the stack area. figure 3-11. format of stack pointer 15 0 sp sp15 sp14 sp13 sp12 sp11 sp10 sp9 sp8 sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 the sp is decremented ahead of write (save) to the stack memory and is in cremented after read (restore) from the stack memory. each stack operation saves/restores dat a as shown in figures 3-12 and 3-13. caution since reset input makes the sp contents undefi ned, be sure to initialize the sp before use. chapter 3 cpu architecture user?s manual u15836ej5v0ud 52 figure 3-12. data to be saved to stack memory (a) push rp instruction (when sp = fee0h) register pair lower fee0h sp sp fee0h fedfh fedeh register pair upper fedeh (b) call, callf, callt instructions (when sp = fee0h) pc15-pc8 fee0h sp sp fee0h fedfh fedeh pc7-pc0 fedeh (c) interrupt, brk instruct ions (when sp = fee0h) pc15-pc8 psw fedfh fee0h sp sp fee0h fedeh feddh pc7-pc0 feddh chapter 3 cpu architecture user?s manual u15836ej5v0ud 53 figure 3-13. data to be restored from stack memory (a) pop rp instruction (when sp = fedeh) register pair lower fee0h sp sp fee0h fedfh fedeh register pair upper fedeh (b) ret instruction (when sp = fedeh) pc15-pc8 fee0h sp sp fee0h fedfh fedeh pc7-pc0 fedeh (c) reti, retb instructions (when sp = feddh) pc15-pc8 psw fedfh fee0h sp sp fee0h fedeh feddh pc7-pc0 feddh chapter 3 cpu architecture user?s manual u15836ej5v0ud 54 3.2.2 general-purpose registers general-purpose registers are mapped at particular a ddresses (fee0h to feffh) of the data memory. the general-purpose registers consists of 4 bank s, each bank consisting of eight 8-bit r egisters (x, a, c, b, e, d, l, and h). each register can be used as an 8-bit register, and two 8-bit r egisters can also be used in a pair as a 16-bit register (ax, bc, de, and hl). these registers can be described in terms of function names (x, a, c, b, e, d, l, h, ax, bc, de, and hl) and absolute names (r0 to r7 and rp0 to rp3). register banks to be used for instruction execution are se t by the cpu control instruction (sel rbn). because of the 4-register bank configuration, an efficient program ca n be created by switching between a register for normal processing and a register for interrupts for each bank. figure 3-14. configuration of general-purpose registers (a) absolute name bank0 bank1 bank2 bank3 feffh fef8h fee0h rp3 rp2 rp1 rp0 r7 15 0 7 0 r6 r5 r4 r3 r2 r1 r0 16-bit processing 8-bit processing fef0h fee8h (b) function name bank0 bank1 bank2 bank3 feffh fef8h fee0h hl de bc ax h 15 0 7 0 l d e b c a x 16-bit processing 8-bit processing fef0h fee8h chapter 3 cpu architecture user?s manual u15836ej5v0ud 55 3.2.3 special function registers (sfrs) unlike a general-purpose register, each special f unction register has a special function. sfrs are allocated to the ff00h to ffffh area. special function registers can be manipulated like gener al-purpose registers, using operation, transfer and bit manipulation instructions. the manipulatable bit units, 1, 8, and 16, depend on the spec ial function register type. each manipulation bit unit can be specified as follows. ? 1-bit manipulation describe the symbol reserved by the assembler for the 1-bit manipulation instruction operand (sfr.bit). this manipulation can also be specified with an address. ? 8-bit manipulation describe the symbol reserved by the assembler fo r the 8-bit manipulation instruction operand (sfr). this manipulation can also be specified with an address. ? 16-bit manipulation describe the symbol reserved by the assembler fo r the 16-bit manipulation instruction operand (sfrp). when specifying an address, describe an even address. table 3-5 gives a list of the special f unction registers. the meanings of items in the table are as follows. ? symbol symbol indicating the address of a special function regist er. it is a reserved word in the ra78k0, and is defined as an sfr variable using the #pragma sfr directive in the cc78k0. when using the ra78k0, id78k0-ns, id78k0, and sm78k0, symbols can be wr itten as an instruction operand. ? r/w indicates whether the corresponding special f unction register can be read or written. r/w: read/write enable r: read only w: write only ? manipulatable bit units indicates the manipulatable bit unit (1, 8, or 16). ? ? ? indicates a bit unit for which manipulation is not possible. ? after reset indicates each register status upon reset input. chapter 3 cpu architecture user?s manual u15836ej5v0ud 56 table 3-5. special function register list (1/3) manipulatable bit unit address special function regist er (sfr) name symbol r/w 1 bit 8 bits 16 bits after reset ff00h port register 0 p0 r/w ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? chapter 3 cpu architecture user?s manual u15836ej5v0ud 57 table 3-5. special function register list (2/3) manipulatable bit unit address special function regist er (sfr) name symbol r/w 1 bit 8 bits 16 bits after reset ff50h asynchronous serial interface operation mode register 6 asim6 r/w ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? chapter 3 cpu architecture user?s manual u15836ej5v0ud 58 table 3-5. special function register list (3/3) manipulatable bit unit address special function regist er (sfr) name symbol r/w 1 bit 8 bits 16 bits after reset ffbch capture/compare control register 00 crc00 r/w ? ? ? ? ? ? ? ? ? ? ? chapter 3 cpu architecture user?s manual u15836ej5v0ud 59 3.3 instruction address addressing an instruction address is determined by program counter (pc) contents and is normally incremented (+1 for each byte) automatically according to the num ber of bytes of an instruction to be fetched each time another instruction is executed. when a branch instruction is executed, the branch destination information is set to the pc and branched by the following addressing (for deta ils of instructions, refer to 78k/0 series instructions user?s manual (u12326e) ). 3.3.1 relative addressing [function] the value obtained by adding 8-bit immediate data (displ acement value: jdisp8) of an instruction code to the start address of the following instruction is transferre d to the program counter (pc) and branched. the displacement value is treated as signed two?s complement data ( ? + ? + + chapter 3 cpu architecture user?s manual u15836ej5v0ud 60 3.3.2 immediate addressing [function] immediate data in the instruction word is tran sferred to the program counter (pc) and branched. this function is carried out when the call !addr16 or br !addr16 or callf !addr11 instruction is executed. call !addr16 and br !addr16 instructions can be branched to the entire memory space. the callf !addr11 instruction is branc hed to the 0800h to 0fffh area. [illustration] in the case of call !addr16 and br !addr16 instructions 15 0 pc 87 70 call or br low addr. high addr. in the case of callf !addr11 instruction 15 0 pc 87 70 fa 10?8 11 10 00001 643 callf fa 7?0 chapter 3 cpu architecture user?s manual u15836ej5v0ud 61 3.3.3 table indirect addressing [function] table contents (branch destinat ion address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation co de are transferred to the progr am counter (pc) and branched. this function is carried out when the ca llt [addr5] instruction is executed. this instruction references the address stored in the me mory table from 40h to 7fh, and allows branching to the entire memory space. [illustration] 15 1 15 0 pc 70 low addr. high addr. memory (table) effective address+1 effective address 01 00000000 87 87 65 0 0 1 11 765 10 ta 4?0 operation code 3.3.4 register addressing [function] register pair (ax) contents to be spec ified with an instruction word are trans ferred to the program counter (pc) and branched. this function is carried out when t he br ax instruction is executed. [illustration] 70 rp 07 ax 15 0 pc 87 chapter 3 cpu architecture user?s manual u15836ej5v0ud 62 3.4 operand address addressing the following methods are available to specify the regi ster and memory (addressing) to undergo manipulation during instruction execution. 3.4.1 implied addressing [function] the register that functions as an accumulator (a and ax) among the general-purpose registers is automatically (implicitly) addressed. of the 78k0/kb1 instruction words, the followi ng instructions employ implied addressing. instruction register to be s pecified by implied addressing mulu a register for multiplicand and ax register for product storage divuw ax register for dividend and quotient storage adjba/adjbs a register for storage of numeric va lues that become decimal correction targets ror4/rol4 a register for storage of di git data that undergoes digit rotation [operand format] because implied addressing can be automatically employ ed with an instruction, no particular operand format is necessary. [description example] in the case of mulu x with an 8-bit chapter 3 cpu architecture user?s manual u15836ej5v0ud 63 3.4.2 register addressing [function] the general-purpose register to be specified is accesse d as an operand with the register bank select flags (rbs0 to rbs1) and the register specify co des (rn and rpn) of an operation code. register addressing is carried out when an instruction wi th the following operand format is executed. when an 8-bit register is specified, one of the eight registers is specified with 3 bits in the operation code. [operand format] identifier description r x, a, c, b, e, d, l, h rp ax, bc, de, hl ?r? and ?rp? can be described by absolute names (r0 to r7 and rp0 to rp3) as well as function names (x, a, c, b, e, d, l, h, ax, bc, de, and hl). [description example] mov a, c; when selecting c register as r operation code 0 1 1 0 0 0 1 0 register specify code incw de; when selecting de register pair as rp operation code 1 0 0 0 0 1 0 0 register specify code chapter 3 cpu architecture user?s manual u15836ej5v0ud 64 3.4.3 direct addressing [function] the memory to be manipulated is directly addressed with immediate data in an instruction word becoming an operand address. [operand format] identifier description addr16 label or 16-bit immediate data [description example] mov a, !0fe00h; when setting !addr16 to fe00h operation code 10001110 op c ode 00000000 00h 11111110 feh [illustration] memory 0 7 addr16 (lower) addr16 (upper) op code chapter 3 cpu architecture user?s manual u15836ej5v0ud 65 3.4.4 short direct addressing [function] the memory to be manipulated in the fixed space is di rectly addressed with 8-bit data in an instruction word. this addressing is applied to the 256-byte space fe20h to ff1fh. internal ram and special function registers (sfrs) are mapped at fe20h to feffh and ff00h to ff1fh, respectively. the sfr area (ff00h to ff1fh) where short direct addre ssing is applied is a part of the overall sfr area. ports that are frequently accessed in a program and comp are and capture registers of the timer/event counter are mapped in this area, allowing sfrs to be mani pulated with a small number of bytes and clocks. when 8-bit immediate data is at 20h to ffh, bit 8 of an effe ctive address is cleared to 0. when it is at 00h to 1fh, bit 8 is set to 1. see the [illustration] . [operand format] identifier description saddr immediate data that indicate label or fe20h to ff1fh saddrp immediate data that indicate label or fe20h to ff1fh (even address only) [description example] mov 0fe30h, a; when transferring valu e of a register to saddr (fe30h) operation code 1 1 1 1 0 0 1 0 op code 0 0 1 1 0 0 0 0 30h (saddr-offset) [illustration] 15 0 short direct memory effective address 1 111111 87 0 7 op code saddr-offset chapter 3 cpu architecture user?s manual u15836ej5v0ud 66 3.4.5 special function register (sfr) addressing [function] a memory-mapped special function register (sfr) is addre ssed with 8-bit immediate data in an instruction word. this addressing is applied to the 240-byte spaces ff 00h to ffcfh and ffe0h to ffffh. however, the sfrs mapped at ff00h to ff1fh can be ac cessed with short direct addressing. [operand format] identifier description sfr special function register name sfrp 16-bit manipulatable special function register name (even address only) [description example] mov pm0, a; when selecting pm0 (ff20h) as sfr operation code 1 1110110 op c ode 0 0100000 20h (sfr-offset) [illustration] 15 0 sfr effective address 1 111111 87 0 7 op code sfr-offset 1 chapter 3 cpu architecture user?s manual u15836ej5v0ud 67 3.4.6 register indirect addressing [function] register pair contents specified by a register pair spec ify code in an instruction word and by a register bank select flag (rbs0 and rbs1) serve as an operand address for addressing the memory. this addressing can be carried out for all the memory spaces. [operand format] identifier description ? chapter 3 cpu architecture user?s manual u15836ej5v0ud 68 3.4.7 based addressing [function] 8-bit immediate data is added as offset data to the content s of the base register, that is , the hl register pair in the register bank specified by the register bank select flag (rbs0 and rbs1), and the sum is used to address the memory. addition is performed by expanding the offset data as a positive number to 16 bits. a carry from the 16th bit is ignored. this addressing can be carried out for all the memory spaces. [operand format] identifier description ? + + + chapter 3 cpu architecture user?s manual u15836ej5v0ud 69 3.4.8 based indexed addressing [function] the b or c register contents specified in an instruction word are added to the contents of the base register, that is, the hl register pair in the register bank specified by the register bank select flag (rbs0 and rbs1), and the sum is used to address the memory. addition is perf ormed by expanding the b or c register contents as a positive number to 16 bits. a carry from the 16th bit is ignored. this addressing can be carried out for all the memory spaces. [operand format] identifier description ? ++ + + chapter 3 cpu architecture user?s manual u15836ej5v0ud 70 3.4.9 stack addressing [function] the stack area is indirectly addressed with the stack pointer (sp) contents. this addressing method is automatically employed when the push, pop, subroutine call and return instructions are executed or the register is sa ved/reset upon generation of an interrupt request. with stack addressing, only the internal high-speed ram area can be accessed. [description example] in the case of push de (saving de register) operation code 10110101 [illustration] e fee0h sp sp fee0h fedfh fedeh d memory 0 7 fedeh user?s manual u15836ej5v0ud 71 chapter 4 port functions 4.1 port functions there are two types of pin i/o buffer power supplies: av ref and v dd . the relationship between these power supplies and the pins is shown below. table 4-1. pin i/o buffer power supplies power supply corresponding pins av ref p20 to p23 v dd pins other than p20 to p23 78k0/kb1 products are provided with the ports shown in fi gure 4-1, which enable vari ety of control operations. the functions of each port are shown in table 4-2. in addition to the func tion as digital i/o ports, these ports have several alternate f unctions. for details of the alternate functions, see chapter 2 pin functions . figure 4-1. port types p30 port 3 p33 p23 port 12 p120 port 2 p00 port 0 p03 p10 port 1 p17 p20 port 13 p130 chapter 4 port functions user?s manual u15836ej5v0ud 72 table 4-2. port functions pin name i/o function after reset alternate function p00 ti000 p01 ti010/to00 p02 p03 i/o port 0. 4-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input ? p10 sck10/txd0 note p11 si10/rxd0 note p12 so10 p13 txd6 p14 rxd6 p15 toh0 p16 toh1/intp5 p17 i/o port 1. 8-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input ti50/to50 p20 to p23 input port 2. 4-bit input-only port. input ani0 to ani3 p30 to p33 i/o port 3. 4-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input intp1 to intp4 p120 i/o port 12. 1-bit i/o port. use of an on-chip pull-up resistor can be specified by a software setting. input intp0 p130 output port 13. 1-bit output-only port. output ? note txd0 and rxd0 are available only in the pd780102, 780103, and 78f0103. 4.2 port configuration a port includes the following hardware. table 4-3. port configuration item configuration control registers port mode register (pm0, pm1, pm3, pm12) port register (p0 to p3, p12, p13) pull-up resistor option register (pu0, pu1, pu3, pu12) port total: 22 (cmos i/o: 17, cmos input: 4, cmos output: 1) pull-up resistors total: 17 (software control only) chapter 4 port functions user?s manual u15836ej5v0ud 73 4.2.1 port 0 port 0 is a 4-bit i/o port with an output latch. port 0 can be set to the input mode or output mode in 1-bit units using port mode register 0 (pm0). when the p00 to p03 pi ns are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 0 (pu0). this port can also be used for timer i/o. reset input sets port 0 to input mode. figures 4-2 to 4-4 show block diagrams of port 0. figure 4-2. block diagram of p00 p00/ti000 wr pu rd wr port wr pm pu00 pu0 alternate function output latch (p00) pm00 pm0 v dd p-ch selector internal bus pu0: pull-up resistor option register 0 pm0: port mode register 0 rd: read signal wr chapter 4 port functions user?s manual u15836ej5v0ud 74 figure 4-3. block diagram of p01 p01/ti010/to00 wr pu rd wr port wr pm pu01 alternate function output latch (p01) pm01 pu0 pm0 alternate function v dd p-ch selector internal bus pu0: pull-up resistor option register 0 pm0: port mode register 0 rd: read signal wr chapter 4 port functions user?s manual u15836ej5v0ud 75 figure 4-4. block diagram of p02 and p03 wr pu rd wr port wr pm pu02, pu03 output latch (p02, p03) pm02, pm03 pu0 pm0 v dd p-ch p02, p03 selector internal bus pu0: pull-up resistor option register 0 pm0: port mode register 0 rd: read signal wr chapter 4 port functions user?s manual u15836ej5v0ud 76 4.2.2 port 1 port 1 is an 8-bit i/o port with an output latch. port 1 can be set to the input mode or output mode in 1-bit units using port mode register 1 (pm1). when the p10 to p17 pi ns are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 1 (pu1). this port can also be used for external interrupt requ est input, serial interfac e data i/o, clock i/o, and timer i/o. reset input sets port 1 to input mode. figures 4-5 to 4-9 show block diagrams of port 1. caution when using p10/sck10 (/txd0 note ), p11/si10 (/rxd0 note ), and p12/so10 as general-purpose ports, do not write to serial clock sel ection register 10 (csic10). figure 4-5. block diagram of p10 p10/sck10 (/txd0 note ) wr pu rd wr port wr pm pu10 alternate function output latch (p10) pm10 pu1 pm1 alternate function v dd p-ch selector internal bus note available only in the chapter 4 port functions user?s manual u15836ej5v0ud 77 figure 4-6. block diagram of p11 and p14 p11/si10 (/rxd0 note ), p14/rxd6 wr pu rd wr port wr pm pu11, pu14 alternate function output latch (p11, p14) pm11, pm14 pu1 pm1 v dd p-ch selector internal bus note available only in the chapter 4 port functions user?s manual u15836ej5v0ud 78 figure 4-7. block diagram of p12 and p15 p12/so10, p15/toh0 wr pu rd wr port wr pm pu12, pu15 output latch (p12, p15) pm12, pm15 pu1 pm1 alternate function v dd p-ch selector internal bus pu1: pull-up resistor option register 1 pm1: port mode register 1 rd: read signal wr chapter 4 port functions user?s manual u15836ej5v0ud 79 figure 4-8. block diagram of p13 p13/txd6 wr pu rd wr port wr pm pu13 output latch (p13) pm13 pu1 pm1 alternate function v dd p-ch internal bus selector pu1: pull-up resistor option register 1 pm1: port mode register 1 rd: read signal wr chapter 4 port functions user?s manual u15836ej5v0ud 80 figure 4-9. block diagram of p16 and p17 p16/toh1/intp5, p17/ti50/to50 wr pu rd wr port wr pm pu16, pu17 alternate function output latch (p16, p17) pm16, pm17 pu1 pm1 alternate function v dd p-ch selector internal bus pu1: pull-up resistor option register 1 pm1: port mode register 1 rd: read signal wr chapter 4 port functions user?s manual u15836ej5v0ud 81 4.2.3 port 2 port 2 is a 4-bit input-only port. this port can also be used for a/d converter analog input. figure 4-10 shows a block diagram of port 2. figure 4-10. block di agram of p20 to p23 rd a/d converter p20/ani0 to p23/ani3 internal bus rd: read signal chapter 4 port functions user?s manual u15836ej5v0ud 82 4.2.4 port 3 port 3 is a 4-bit i/o port with an output latch. port 3 can be set to the input mode or output mode in 1-bit units using port mode register 3 (pm3). when the p30 to p33 pi ns are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 3 (pu3). this port can also be used for external interrupt request input. reset input sets port 3 to input mode. figure 4-11 shows a block diagram of port 3. figure 4-11. block di agram of p30 to p33 p30/intp1 to p33/intp4 wr pu rd wr port wr pm pu30 to pu33 alternate function output latch (p30 to p33) pm30 to pm33 pu3 pm3 v dd p-ch selector internal bus pu3: pull-up resistor option register 3 pm3: port mode register 3 rd: read signal wr chapter 4 port functions user?s manual u15836ej5v0ud 83 4.2.5 port 12 port 12 is a 1-bit i/o port with an out put latch. port 12 can be set to the input mode or output mo de in 1-bit units using port mode register 12 (pm12). when the p120 pin is used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resist or option register 12 (pu12). this port can also be used for external interrupt request input. reset input sets port 12 to input mode. figure 4-12 shows a block diagram of port 12. figure 4-12. blo ck diagram of p120 p120/intp0 wr pu rd wr port wr pm pu120 alternate function output latch (p120) pm120 pu12 pm12 v dd p-ch selector internal bus pu12: pull-up resistor option register 12 pm12: port mode register 12 rd: read signal wr chapter 4 port functions user?s manual u15836ej5v0ud 84 4.2.6 port 13 port 13 is a 1-bit output-only port. figure 4-13 shows a block diagram of port 13. figure 4-13. blo ck diagram of p130 rd output latch (p130) wr port p130 internal bus rd: read signal wr ? ? ? chapter 4 port functions user?s manual u15836ej5v0ud 85 figure 4-14. format of port mode register symbol 7 6 5 4 3 2 1 0 address after reset r/w pm0 1 1 1 1 pm03 pm02 pm01 pm00 ff20h ffh r/w pm1 pm17 pm16 pm15 pm14 pm13 pm12 pm11 pm10 ff21h ffh r/w pm3 1 1 1 1 pm33 pm32 pm31 pm30 ff23h ffh r/w pm12 1 1 1 1 1 1 1 pm120 ff2ch ffh r/w pmmn pmn pin i/o mode selection (m = 0, 1, 3, 12; n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) table 4-4. settings of port mode register a nd output latch when alternate function is used alternate function pin name name i/o pm chapter 4 port functions user?s manual u15836ej5v0ud 86 (2) port registers (p0 to p3, p12, p13) these registers write the data t hat is output from the chip when data is output from a port. if the data is read in the input mode, the pin level is read. if it is read in the output mode, the value of the output latch is read. these registers can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears these registers to 00h (but p2 is undefined). figure 4-15. format of port register 7 0 symbol p0 6 0 5 0 4 0 3 p03 2 p02 1 p01 0 p00 address ff00h after reset 00h (output latch) r/w r/w 7 p17 p1 6 p16 5 p15 4 p14 3 p13 2 p12 1 p11 0 p10 ff01h 00h (output latch) r/w r 7 0 p2 6 0 5 0 4 0 3 p23 2 p22 1 p21 0 p20 ff02h undefined 7 0 p3 6 0 5 0 4 0 3 p33 2 p32 1 p31 0 p30 ff03h 00h (output latch) r/w 7 0 p12 6 0 5 0 4 0 3 0 2 0 1 0 0 p120 ff0ch 00h (output latch) r/w 7 0 p13 6 0 5 0 4 0 3 0 2 0 1 0 0 p130 ff0dh 00h (output latch) r/w m = 0 to 3, 12, 13; n = 0 to 7 pmn output data control (in output mode) input data read (in input mode) 0 output 0 input low level 1 output 1 input high level chapter 4 port functions user?s manual u15836ej5v0ud 87 (3) pull-up resistor option regist ers (pu0, pu1, pu3, and pu12) these registers specify whether the on-chip pull-up resistors of p00 to p03, p10 to p17, p30 to p33, or p120 is to be used or not. an on-chip pull-up resistors can be used in 1-bit units only for the bits set to input mode of the pins to which the use of an on-chip pull-up resistor has been specified. on-chip pull-up resistor cannot be connected for bits set to output mode and bits used as alte rnate-function output pins, re gardless of the settings of pu0, pu1, pu3 and pu12. these registers can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears these registers to 00h. figure 4-16. format of pull-up resistor option register symbol 7 6 5 4 3 2 1 0 address after reset r/w pu0 0 0 0 0 pu03 pu02 pu01 pu00 ff30h 00h r/w 7 6 5 4 3 2 1 0 pu1 pu17 pu16 pu15 pu14 pu13 pu12 pu11 pu10 ff31h 00h r/w 7 6 5 4 3 2 1 0 pu3 0 0 0 0 pu33 pu32 pu31 pu30 ff33h 00h r/w 7 6 5 4 3 2 1 0 pu12 0 0 0 0 0 0 0 pu120 ff3ch 00h r/w pumn pmn pin on-chip pull-up resistor selection (m = 0, 1, 3, 12; n = 0 to 7) 0 on-chip pull-up resistor not connected 1 on-chip pull-up resistor connected chapter 4 port functions user?s manual u15836ej5v0ud 88 4.4 port function operations port operations differ depending on whether the inpu t or output mode is set, as shown below. caution in the case of a 1-bit memory manipulation in struction, although a singl e bit is manipulated, the port is accessed as an 8-bit unit. therefore, on a port with a mixture of input and output pins, the output latch contents for pins specified as input are undefined, even for bits other than the manipulated bit. 4.4.1 writing to i/o port (1) output mode a value is written to the output latch by a transfer inst ruction, and the output latch contents are output from the pin. once data is written to the output latch, it is reta ined until data is written to the output latch again. the data of the output latch is cleared by reset. (2) input mode a value is written to the output latch by a transfer instruction, but since the output buffer is off, the pin status does not change. once data is written to the output latch, it is reta ined until data is written to the output latch again. 4.4.2 reading from i/o port (1) output mode the output latch contents ar e read by a transfer instruction. t he output latch content s do not change. (2) input mode the pin status is read by a transfer instruct ion. the output latch c ontents do not change. 4.4.3 operations on i/o port (1) output mode an operation is performed on the output latch contents, and the result is wr itten to the output latch. the output latch contents are output from the pins. once data is written to the output latch, it is reta ined until data is written to the output latch again. the data of the output latch is cleared by reset. (2) input mode the pin level is read and an operation is performed on its cont ents. the result of the op eration is written to the output latch, but since the output buffer is off, the pin status does not change. user?s manual u15836ej5v0ud 89 chapter 5 clock generator 5.1 functions of clock generator the clock generator generates the clock to be supplied to the cpu and peripheral hardware. the following two system clock oscillators are available. ? ? chapter 5 clock generator user?s manual u15836ej5v0ud 90 figure 5-1. block diagra m of clock generator x1 x2 x1 oscillator f xp f x 2 2 internal bus ring-osc mode register (rcm) stop mstop main osc control register (moc) f x 2 3 f x 2 4 f x 2 3 internal bus ring-osc oscillator mask option 1: cannot be stopped 0. can be stopped rstop controller pcc1 pcc0 control signal cpu clock (f cpu ) f cpu processor clock control register (pcc) pcc2 mcm0 mcs main clock mode register (mcm) osts1 osts0 osts2 x1 oscillation stabilization time counter oscillation stabilization time select register (osts) 3 most 16 most 15 most 14 most 13 most 11 oscillation stabilization time counter status register (ostc) f r clock to peripheral hardware prescaler operation clock switch f x 8-bit timer h1, watchdog timer prescaler prescaler selector c p u chapter 5 clock generator user?s manual u15836ej5v0ud 91 5.3 registers controlling clock generator the following six registers are used to control the clock generator. ? processor clock control register (pcc) ? ring-osc mode register (rcm) ? main clock mode register (mcm) ? main osc control register (moc) ? oscillation stabilization time c ounter status register (ostc) ? oscillation stabilization time select register (osts) (1) processor clock control register (pcc) this register sets the division ratio of the cpu clock. pcc can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 5-2. format of processor clock control register (pcc) address: fffbh after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 pcc 0 0 0 0 0 pcc2 pcc1 pcc0 cpu clock selection (f cpu ) pcc2 pcc1 pcc0 mcm0 = 0 mcm0 = 1 0 0 0 f x f r f xp 0 0 1 f x /2 f r /2 note f xp /2 0 1 0 f x /2 2 setting prohibited f xp /2 2 0 1 1 f x /2 3 setting prohibited f xp /2 3 1 0 0 f x /2 4 setting prohibited f xp /2 4 other than above setting prohibited note the setting of (a1) grade products and (a2) grade products is prohibited. remarks 1. mcm0: bit 0 of the main clock mode register (mcm) 2. f x : main system clock oscillation frequency (x1 input clock oscillation frequency or ring-osc clock oscillation frequency) 3. f r : ring-osc clock oscillation frequency 4. f xp : x1 input clock oscillation frequency chapter 5 clock generator user?s manual u15836ej5v0ud 92 the fastest instruction can be executed in 2 clocks of the cpu clock in the 78k0/kb1. therefore, the relationship between the cpu clock (f cpu ) and minimum instruction execution time is as shown in the table 5-2. table 5-2. relationship between cpu clo ck and minimum instruction execution time minimum instruction execution time: 2/f cpu x1 input clock cpu clock (f cpu ) note 1 at 10 mhz operation at 12 mhz operation note 2 ring-osc clock (at 240 khz (typ.) operation) f x 0.2 s 0.166 s 8.3 s (typ.) f x /2 0.4 s 0.333 s 16.6 s (typ.) note 3 f x /2 2 0.8 s 0.666 s setting prohibited f x /2 3 1.6 s 1.333 s setting prohibited f x /2 4 3.2 s 2.666 s setting prohibited notes 1. the main clock mode register (mcm) is used to set the cpu clock (x1 input clock/ring-osc clock) (see figure 5-4 ). 2. expanded-specification products of st andard products and (a) grade products only 3. the setting of (a1) grade products and (a2) grade products is prohibited. (2) ring-osc mode register (rcm) this register sets the operation mode of ring-osc. this register is valid when ?can be stopped by software? is set for ring-osc by a mask option, and the x1 input clock is input to the cpu clock. if ?cannot be stopped? is selected for ring-osc by a mask option, settings for this register are invalid. rcm can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 5-3. format of ring-osc mode register (rcm) address: ffa0h after reset: 00h r/w symbol 7 6 5 4 3 2 1 <0> rcm 0 0 0 0 0 0 0 rstop rstop ring-osc oscillating/stopped 0 ring-osc oscillating 1 ring-osc stopped caution make sure that bit 1 (mcs) of the main clock mode register (mcm) is 1 before setting rstop. chapter 5 clock generator user?s manual u15836ej5v0ud 93 (3) main clock mode register (mcm) this register sets the cpu clo ck (x1 input clock/ring-osc clock). mcm can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 5-4. format of main clock mode register (mcm) address: ffa1h after reset: 00h r/w note symbol 7 6 5 4 3 2 <1> <0> mcm 0 0 0 0 0 0 mcs mcm0 mcs cpu clock status 0 operates with ring-osc clock 1 operates with x1 input clock mcm0 selection of clock supplied to cpu 0 ring-osc clock 1 x1 input clock note bit 1 is read-only. caution when the ring-osc clo ck is selected as the clock to be supplied to the cpu, the divided clock of the ring-osc oscillator output (f x ) is supplied to the peripheral hardware (f x = 240 khz (typ.)). operation of the peripheral hardwa re with the ring-osc clock cannot be guaranteed. therefore, when the ring-osc clock is selected as the clock supplied to the cpu, do not use peripheral hardwa re. in addition, stop the peripheral hardware before switching the clock supplie d to the cpu from the x1 input clock to the ring-osc clock. note, however, that th e following periphera l hardware can be used when the cpu operat es on the ring-osc clock. ? ? ? ? chapter 5 clock generator user?s manual u15836ej5v0ud 94 (4) main osc control register (moc) this register selects the operat ion mode of the x1 input clock. this register is used to stop the x1 oscillator operation when the cpu is operating with the ring-osc clock. therefore, this register is valid only when t he cpu is operating with the ring-osc clock. moc can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 5-5. format of main osc control register (moc) address: ffa2h after reset: 00h r/w symbol <7> 6 5 4 3 2 1 0 moc mstop 0 0 0 0 0 0 0 mstop control of x1 oscillator operation 0 x1 oscillator operating 1 x1 oscillator stopped caution make sure that bit 1 (mcs) of the main clock mode register (mcm) is 0 before setting mstop. chapter 5 clock generator user?s manual u15836ej5v0ud 95 (5) oscillation stabilization time c ounter status register (ostc) this is the status register of the x1 input clock oscillation stabilization time counter. if the ring-osc clock is used as the cpu clock, the x1 input clock o scillation stabilization time can be checked. ostc can be read by a 1-bit or 8-bit memory manipulation instruction. when reset is released (reset by reset input, poc, lv i, clock monitor, and wdt), the stop instruction, mstop = 1 clear ostc to 00h. figure 5-6. format of oscillation stabilizati on time counter status register (ostc) address: ffa3h after reset: 00h r symbol 7 6 5 4 3 2 1 0 ostc 0 0 0 most11 most 13 most14 most15 most16 oscillation stabilization time status most11 most13 mo st14 most15 most16 f xp = 10 mhz f xp = 12 mhz note 1 0 0 0 0 2 11 /f xp min. 204.8 ? chapter 5 clock generator user?s manual u15836ej5v0ud 96 (6) oscillation stabilization time select register (osts) this register is used to select the x1 oscillation stabilization wait time when stop mode is released. the wait time set by osts is valid only after stop m ode is released with the x1 input clock selected as the cpu clock. after stop mode is released with ring-osc select ed as the cpu clock, the oscillation stabilization time must be confirmed by ostc. osts can be set by an 8-bit memory manipulation instruction. reset input sets osts to 05h. figure 5-7. format of oscillation stabiliz ation time select register (osts) address: ffa4h after reset: 05h r/w symbol 7 6 5 4 3 2 1 0 osts 0 0 0 0 0 osts2 osts1 osts0 oscillation stabilization time selection osts2 osts1 osts0 f xp = 10 mhz f xp = 12 mhz note 0 0 1 2 11 /f xp 204.8 s 170.7 s 0 1 0 2 13 /f xp 819.2 s 682.7 s 0 1 1 2 14 /f xp 1.64 ms 1.37 ms 1 0 0 2 15 /f xp 3.27 ms 2.73 ms 1 0 1 2 16 /f xp 6.55 ms 5.46 ms other than above setting prohibited note expanded-specification products of st andard products and (a) grade products only cautions 1. to set the stop mode when the x1 input clock is used as the cpu clock, set osts before executing the stop instruction. 2. execute the osts setting after confirmi ng that the oscillation stabilization time has elapsed as expect ed in the ostc. 3. if the stop mode is entered and th en released while th e ring-osc clock is being used as the cpu clo ck, set the oscillation stabilization time as follows. ? desired ostc oscillation stabilization time oscillation stabilization time set by osts the x1 oscillation stabilization time counter counts up to the oscillation stabilization time set by osts. note, ther efore, that only the status up to the oscillation stabilization time set by osts is set to ostc after stop mode is released. 4. the wait time when stop mode is re leased does not include the time after stop mode release until clock oscillation star ts (?a? below) regardless of whether stop mode is released by reset input or interr upt generation. stop mode release x1 pin voltage waveform a remark f xp : x1 input clock oscillation frequency chapter 5 clock generator user?s manual u15836ej5v0ud 97 5.4 system clock oscillator 5.4.1 x1 oscillator the x1 oscillator oscillates with a crystal resonator or ceramic resonator connected to the x1 and x2 pins. an external clock can be input to the x1 oscillator. in th is case, input the clock signal to the x1 pin and input the inverse signal to the x2 pin. figure 5-8 shows the external circuit of the x1 oscillator. figure 5-8. external circuit of x1 oscillator (a) crystal, ceramic osc illation (b) external clock v ss x1 x2 crystal resonator or ceramic resonator external clock x1 x2 caution when using the x1 oscillator, wire as follows in the area enclosed by the broken lines in the figure 5-8 to avoid an adverse ef fect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line th rough which a high fluctuating current flows. always make the ground point of the o scillator capacitor the same potential as v ss . do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. figure 5-9 shows examples of incorrect resonator connection. chapter 5 clock generator user?s manual u15836ej5v0ud 98 figure 5-9. examples of in correct resonator connection (a) too long wiring (b) crossed signal line x2 v ss x1 x1 v ss x2 port (c) wiring near high alternating current (d) current flowing through ground line of oscillator (potential at points a, b, and c fluctuates) v ss x1 x2 v ss x1 x2 ab c pmn v dd high current high current (e) signals are fetched v ss x1 x2 chapter 5 clock generator user?s manual u15836ej5v0ud 99 5.4.2 ring-osc oscillator a ring-osc oscillator is incorporated in the 78k0/kb1. ?can be stopped by software? or ?cannot be stopped? can be selected by a mask option. the ring-osc clock always oscillates after reset release (240 khz (typ.)). 5.4.3 prescaler the prescaler generates various clocks by dividing the x1 o scillator output when the x1 input clock is selected as the clock to be supplied to the cpu. caution when the ring-osc clock is selected as the clock supplied to the cpu, the prescaler generates various clocks by dividing th e ring-osc oscillator output (f x = 240 khz (typ.)). chapter 5 clock generator user?s manual u15836ej5v0ud 100 5.5 clock generator operation the clock generator generates the following clocks and cont rols the operation modes of the cpu, such as standby mode. ? ? ? ? chapter 5 clock generator user?s manual u15836ej5v0ud 101 (2) improvement of performance because the cpu can be started without waiting for the x1 input clock oscillation stabilization time, the total performance can be improved. a timing diagram of the cpu default start using ring-osc is shown in figure 5-10. figure 5-10. timing diagram of cpu default start using ring-osc ring-osc clock (f r ) cpu clock x1 input clock (f xp ) operation stopped: 17/f r x1 oscillation stabilization time: 2 11 /f xp to 2 16 /f xp note reset ring-osc clock x1 input clock switched by software note check using the oscillation stabilization time counter status register (ostc). (a) when the reset signal is generated, bit 0 of the main clock mode register (mcm) is set to 0 and the ring- osc clock is set as the cpu clock. however, a clock is supplied to t he cpu after 17 clocks of the ring-osc clock have elapsed after reset release (or clock supp ly to the cpu stops for 17 clocks). during the reset period, oscillation of the x1 in put clock and ring-osc clock is stopped. (b) after reset release, the cpu clock can be switched fr om the ring-osc clock to the x1 input clock using bit 0 (mcm0) of the main clock mode register (mcm) after the x1 input clock oscillation stabilization time has elapsed. at this time, check the oscillation stabilizatio n time using the oscillati on stabilization time counter status register (ostc) bef ore switching the cpu clock. the cpu clock status can be checked using bit 1 (mcs) of mcm. (c) ring-osc can be set to stopped/oscillating using th e ring-osc mode register (rcm) when ?can be stopped by software? is selected for the ring-osc by a mask opti on, if the x1 input is used as the cpu clock. make sure that mcs is 1 at this time. (d) when ring-osc is used as the cpu clock, the x1 i nput clock can be set to stopped/oscillating using the main osc control register (moc). make sure that mcs is 0 at this time. (e) select the x1 input clock oscillation stabilization time (2 11 /f xp , 2 13 /f xp , 2 14 /f xp , 2 15 /f xp , 2 16 /f xp ) using the oscillation stabilization time select register (o sts) when releasing stop mode while the x1 input clock is being used as the cpu clock. in addition, when releasing stop mode while reset is released and the ring-osc clock is being used as the cpu clock, check the x1 input clock oscillation stabilization time using the oscillation stabilization time co unter status register (ostc). chapter 5 clock generator user?s manual u15836ej5v0ud 102 a status transition diagram of this product is shown in figure 5-11, and the relationship between the operation clocks in each operation status and between the oscillation control flag and oscill ation status of each clock are shown in tables 5-3 and 5-4, respectively. figure 5-11. status transition diagram (1/2) (1) when ?ring-osc can be stopped by software? is selected by mask option status 4 cpu clock: f xp f xp : oscillating f r : oscillation stopped status 3 cpu clock: f xp f xp : oscillating f r : oscillating status 1 cpu clock: f r f xp : oscillation stopped f r : oscillating status 2 cpu clock: f r f xp : oscillating f r : oscillating halt note 4 interrupt interrupt interrupt interrupt interrupt interrupt reset release interrupt interrupt halt instruction stop instruction stop instruction stop instruction stop instruction rstop = 0 rstop = 1 note 1 mcm0 = 0 mcm0 = 1 note 2 mstop = 1 note 3 mstop = 0 halt instruction halt instruction halt instruction stop note 4 reset note 5 notes 1. when shifting from status 3 to status 4, make sure that bit 1 (mcs) of the main clock mode register (mcm) is 1. 2. before shifting from status 2 to status 3 after reset and stop are released, check the x1 input clock oscillation stabilization time status using the oscillation stabilizati on time counter status register (ostc). 3. when shifting from status 2 to stat us 1, make sure that mcs is 0. 4. when ?ring-osc can be stopped by software? is selected by a mask option, the watchdog timer stops operating in the halt and stop modes, regardle ss of the source clock of the watchdog timer. however, oscillation of ring-osc does not stop ev en in the halt and stop modes if rstop = 0. 5. all reset sources (reset input, poc, lvi, clock monitor, and wdt) chapter 5 clock generator user?s manual u15836ej5v0ud 103 figure 5-11. status transition diagram (2/2) (2) when ?ring-osc cannot be stop ped? is selected by mask option status 3 cpu clock: f xp f xp : oscillating f r : oscillating halt interrupt interrupt interrupt stop instruction mcm0 = 0 mcm0 = 1 note 1 halt instruction halt instruction stop note 3 reset note 4 status 2 cpu clock: f r f xp : oscillating f r : oscillating status 1 cpu clock: f r f xp : oscillation stopped f r : oscillating interrupt stop instruction interrupt interrupt stop instruction mstop = 1 note 2 mstop = 0 halt instruction reset release notes 1. before shifting from status 2 to status 3 after reset and stop are released, check the x1 input clock oscillation stabilization time status using the oscillation stabilizati on time counter status register (ostc). 2. when shifting from status 2 to stat us 1, make sure that mcs is 0. 3. the watchdog timer operates using ring-osc even in stop mode if ?ring- osc cannot be stopped? is selected by a mask option. ring-osc division can be selected as the count source of 8-bit timer h1 (tmh1), so clear the watchdog timer using t he tmh1 interrupt request before watchdog timer overflow. if this processing is not performed, an in ternal reset signal is generated at watchdog timer overflow after stop instruction execution. 4. all reset sources (reset input, poc, lvi, clock monitor, and wdt) chapter 5 clock generator user?s manual u15836ej5v0ud 104 table 5-3. relationship between operat ion clocks in each operation status ring-osc oscillator prescaler clock supplied to peripherals note 2 status operation mode x1 oscillator note 1 rstop = 0 rstop = 1 cpu clock after release mcm0 = 0 mcm0 = 1 reset stopped ring-osc stopped stop stopped note 3 stopped halt oscillating oscillating oscillating stopped note 4 ring-osc x1 notes 1. when ?cannot be stopped? is select ed for ring-osc by a mask option. 2. when ?can be stopped by software? is selected for ring-osc by a mask option. 3. operates using the cpu clock at stop instruction execution. 4. operates using the cpu clock at halt instruction execution. caution the rstop setting is valid only when ?can be stopped by software? is set for ring-osc by a mask option. remark rstop: bit 0 of the ring-osc mode register (rcm) mcm0: bit 0 of the main clock mode register (mcm) table 5-4. oscillation control fl ags and clock oscillation status x1 oscillator ring-osc oscillator rstop = 0 stopped oscillating mstop = 1 rstop = 1 setting prohibited rstop = 0 oscillating mstop = 0 rstop = 1 oscillating stopped caution the rstop setting is valid only when ?can be stopped by software? is set for ring-osc by a mask option. remark mstop: bit 7 of the main osc control register (moc) rstop: bit 0 of the ring-osc mode register (rcm) chapter 5 clock generator user?s manual u15836ej5v0ud 105 5.6 time required to switch betwee n ring-osc clock and x1 input clock bit 0 (mcm0) of the main clock mode register (mcm) is us ed to switch between the ring-osc clock and x1 input clock. in the actual switching operation, s witching does not occur immediately after mcm0 rewrite; several instructions are executed using the pre-switch ov er clock after switching mcm0 (see table 5-5 ). bit 1 (mcs) of mcm is used to judge that operation is per formed using either the ring-osc clock or x1 input clock. to stop the original clock after changing the clock, wait for the number of clocks shown in table 5-5. table 5-5. maximum time required to switch between ring-osc clock and x1 input clock pcc maximum time required for switching pcc2 pcc1 pcc0 x1 ring-osc ring-osc x1 0 0 0 f xp /f r + 1 clock 2 clocks 0 0 1 f xp /2f r + 1 clock note 2 clocks note note the setting of (a1) grade products and (a2) grade products is prohibited. caution to calculate the maximum time, set f r = 120 khz. remarks 1. pcc: processor clock control register 2. f xp : x1 input clock oscillation frequency 3. f r : ring-osc clock oscillation frequency 4. the maximum time is the number of cl ocks of the cpu cloc k before switching. chapter 5 clock generator user?s manual u15836ej5v0ud 106 5.7 time required for cpu clock switchover the cpu clock can be switched using bits 0 to 2 (pcc0 to pcc2) of the processor clock control register (pcc). the actual switchover operation is not performed immedi ately after rewriting to the pcc; operation continues on the pre-switchover clock for several instructions (see table 5-6 ). table 5-6. maximum time requi red for cpu clock switchover set value before switchover set value after switchover pcc2 pcc1 pcc0 pcc2 pcc1 pcc0 pcc2 p cc1 pcc0 pcc2 pcc1 pcc0 pcc2 pcc1 pcc0 pcc2 pcc1 pcc0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 0 0 0 16 clocks 16 clocks 16 clocks 16 clocks 0 0 1 8 clocks 8 clocks 8 clocks 8 clocks 0 1 0 4 clocks 4 clocks 4 clocks 4 clocks 0 1 1 2 clocks 2 clocks 2 clocks 2 clocks 1 0 0 1 clock 1 cloc k 1 clock 1 clock remark the maximum time is the number of clo cks of the cpu clock before switching. caution setting the following values is prohibit ed when the cpu operat es on the ring-osc clock. ? ? ? ? chapter 5 clock generator user?s manual u15836ej5v0ud 107 5.8 clock switching flowchart and register setting 5.8.1 switching from ring-o sc clock to x1 input clock figure 5-12. switching from ring-osc clock to x1 input clock (flowchart) ; f cpu = f r ; ring-osc oscillation ; ring-osc clock operation ; x1 oscillation ; oscillation stabilization time status register ; oscillation stabilization time f xp /2 16 mcm.1 (mcs) is changed from 0 to 1 ; x1 oscillation stabilization time status check x1 oscillation stabilization time has elapsed x1 oscillation stabilization time has not elapsed pcc = 00h rcm = 00h mcm = 00h moc = 00h ostc = 00h osts = 05h note ostc check note each processing after reset release pcc setting mcm.0 chapter 5 clock generator user?s manual u15836ej5v0ud 108 5.8.2 switching from x1 in put clock to ring-osc clock figure 5-13. switching from x1 input clock to ring-osc clock (flowchart) mcm.1 (mcs) is changed from 1 to 0 ; ring-osc clock operation ; ring-osc oscillating? ring-osc clock operation ; x1 input clock operation no: rstop = 0 yes: rstop = 1 mcm = 03h rcm.0 note (rstop) = 1? rstop = 0 mcm0 0 register setting in x1 input clock operation x1 input clock operation ring-osc clock operation note required only when ?can be stopped by software? is selected for ring-osc by a mask option. chapter 5 clock generator user?s manual u15836ej5v0ud 109 5.8.3 register settings the table below shows the statuses of the setting flags and status flags when each mode is set. table 5-7. clock and register settings setting flag status flag mcm register moc register rcm register mcm register f cpu mode mcm0 mstop rstop note 1 mcs ring-osc oscillating 1 0 0 1 x1 input clock note 2 ring-osc stopped 1 0 1 1 x1 oscillating 0 0 0 0 ring-osc clock x1 stopped 0 1 0 0 notes 1. this is valid only when ?can be stopped by software? is selected for ring-osc by mask option. 2. do not set mstop to 1 during x1 input clock oper ation (oscillation of x1 is not stopped even when mstop = 1). user?s manual u15836ej5v0ud 110 chapter 6 16-bit timer/event counter 00 6.1 functions of 16-bit timer/event counter 00 16-bit timer/event counter 00 has the following functions. ? ? ? ? ? ? chapter 6 16-bit timer/event counter 00 user?s manual u15836ej5v0ud 111 6.2 configuration of 16-b it timer/event counter 00 16-bit timer/event counter 00 includes the following hardware. table 6-1. configuration of 16-bit timer/event counter 00 item configuration timer counter 16 bits (tm00) register 16-bit timer capture/compar e register: 16 bits (cr000, cr010) timer input ti000, ti010 timer output to00, output controller control registers 16-bit timer mode control register 00 (tmc00) capture/compare control register 00 (crc00) 16-bit timer output control register 00 (toc00) prescaler mode register 00 (prm00) port mode register 0 (pm0) port register 0 (p0) figure 6-1 shows the block diagram. figure 6-1. block diagram of 16-bit timer/event counter 00 internal bus capture/compare control register 00 (crc00) ti010/to00/p01 f x f x /2 2 f x /2 8 f x ti000/p00 prescaler mode register 00 (prm00) 2 prm001 prm000 crc002 16-bit timer capture/compare register 010 (cr010) match match 16-bit timer counter 00 (tm00) clear noise elimi- nator crc002 crc001 crc000 inttm000 to00/ti010/ p01 inttm010 16-bit timer output control register 00 (toc00) 16-bit timer mode control register 00 (tmc00) internal bus tmc003 tmc002 tmc001 ovf00 toc004 lvs00 lvr00 toc001 toe00 selector 16-bit timer capture/compare register 000 (cr000) selector selector selector noise elimi- nator noise elimi- nator output controller ospe00 ospt00 output latch (p01) pm01 to cr010 chapter 6 16-bit timer/event counter 00 user?s manual u15836ej5v0ud 112 (1) 16-bit timer counter 00 (tm00) tm00 is a 16-bit read-only regist er that counts count pulses. the counter is incremented in synchronization with the rising edge of the input clock. figure 6-2. format of 16-bit timer counter 00 (tm00) tm00 symbol ff11h ff10h address: ff10h, ff11h after reset: 0000h r the count value is reset to 0000h in the following cases. <1> at reset input <2> if tmc003 and tmc002 are cleared <3> if the valid edge of ti000 is input in the mode in wh ich clear & start occurs when inputting the valid edge of ti000 <4> if tm00 and cr000 match in the mode in which cl ear & start occurs on a match of tm00 and cr000 <5> ospt00 is set to 1 in one-shot pulse output mode (2) 16-bit timer capture/comp are register 000 (cr000) cr000 is a 16-bit register that has the functions of both a capture register and a compar e register. whether it is used as a capture register or as a comp are register is set by bit 0 (crc000) of capture/compar e control register 00 (crc00). cr000 can be set by a 16-bit memory manipulation instruction. reset input clears cr000 to 0000h. figure 6-3. format of 16-bit timer ca pture/compare register 000 (cr000) cr000 symbol ff13h ff12h address: ff12h, ff13h after reset: 0000h r/w ? ? chapter 6 16-bit timer/event counter 00 user?s manual u15836ej5v0ud 113 table 6-2. cr000 capture trigger and valid edges of ti000 and ti010 pins (1) ti000 pin valid edge selected as captu re trigger (crc001 = 1, crc000 = 1) ti000 pin valid edge cr000 capture trigger es001 es000 falling edge rising edge 0 1 rising edge falling edge 0 0 no capture operation both rising and falling edges 1 1 (2) ti010 pin valid edge selected as captu re trigger (crc001 = 0, crc000 = 1) ti010 pin valid edge cr000 capture trigger es101 es100 falling edge falling edge 0 0 rising edge rising edge 0 1 both rising and falling edges both rising and falling edges 1 1 remarks 1. setting es001, es000 = 1, 0 and es101, es100 = 1, 0 is prohibited. 2. es001, es000: bits 5 and 4 of prescaler mode register 00 (prm00) es101, es100: bits 7 and 6 of prescaler mode register 00 (prm00) crc001, crc000: bits 1 and 0 of capture/ compare control register 00 (crc00) cautions 1. set a value other than 0000h in cr000 in the mode in which clear & start occurs on a match of tm00 and cr000. 2. if cr000 is set to 0000h in the free-running mode and in the clear mode using the valid edge of the ti000 pin, an interrupt request (inttm 000) is generated when the value of cr000 changes from 0000h to 0001h following tm00 overflow (ffffh ). moreover, inttm000 is generated after a match of tm00 and cr000 is detected, a valid edge of the ti010 pin is detected, and the timer is cl eared by a one-shot trigger. 3. when p01 is used as the valid edge input pi n of ti010, it cannot be used as the timer output (to00). moreover, when p01 is used as to00, it cannot be used as the valid edge input pin of ti010. 4. when cr000 is used as a cap ture register, read data is undefi ned if the regist er read time and capture trigger input conflict (the captu re data itself is the correct value). if timer count stop and capture trigger in put conflict, the capture d data is undefined. 5. do not rewrite cr000 during tm00 operation. chapter 6 16-bit timer/event counter 00 user?s manual u15836ej5v0ud 114 (3) 16-bit timer capture/comp are register 010 (cr010) cr010 is a 16-bit register that has the functions of both a capture register and a compar e register. whether it is used as a capture register or a compare register is set by bit 2 (crc002) of capture/ compare control register 00 (crc00). cr010 can be set by a 16-bit memory manipulation instruction. reset input clears cr010 to 0000h. figure 6-4. format of 16-bit timer ca pture/compare register 010 (cr010) cr010 symbol ff15h ff14h address: ff14h, ff15h after reset: 0000h r/w ? ? chapter 6 16-bit timer/event counter 00 user?s manual u15836ej5v0ud 115 6.3 registers controlling 16-bi t timer/event counter 00 the following six registers are used to control 16-bit timer/event counter 00. ? ? ? ? ? ? chapter 6 16-bit timer/event counter 00 user?s manual u15836ej5v0ud 116 figure 6-5. format of 16-bit timer mode control register 00 (tmc00) address ffbah after reset: 00h r/w symbol 7 6 5 4 3 2 1 <0> tmc00 0 0 0 0 tmc003 tmc002 tmc001 ovf00 tmc003 tmc002 tmc001 operating mode and clear mode selection to00 inversion timing selection interrupt request generation 0 0 0 0 0 1 operation stop (tm00 cleared to 0) no change not generated 0 1 0 free-running mode match between tm00 and cr000 or match between tm00 and cr010 0 1 1 match between tm00 and cr000, match between tm00 and cr010 or ti000 valid edge 1 0 0 1 0 1 clear & start occurs on ti000 valid edge ? chapter 6 16-bit timer/event counter 00 user?s manual u15836ej5v0ud 117 (2) capture/compare control register 00 (crc00) this register controls the oper ation of the 16-bit timer capture/ compare registers (cr000, cr010). crc00 can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears crc00 to 00h. figure 6-6. format of capture/comp are control register 00 (crc00) address: ffbch after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 crc00 0 0 0 0 0 crc002 crc001 crc000 crc002 cr010 operating mode selection 0 operates as compare register 1 operates as capture register crc001 cr000 capture trigger selection 0 captures on valid edge of ti010 1 captures on valid edge of ti000 by reverse phase note crc000 cr000 operating mode selection 0 operates as compare register 1 operates as capture register note the capture operation is not perform ed if both the rising and falling edges are specified as the valid edge of ti000. cautions 1. timer operation must be stopped before setting crc00. 2. when the mode in which clear & start occurs on a match betw een tm00 and cr000 is selected with 16-bit timer mode control register 00 (tmc00), cr0 00 should not be specified as a capture register. 3. to ensure that the capture operation is pe rformed properly, the cap ture trigger requires a pulse two cycles longer than th e count clock selected by pr escaler mode register 00 (prm00). (3) 16-bit timer output control register 00 (toc00) this register controls the operation of the 16-bit timer/ event counter 00 output controller. it sets/resets the timer output f/f (lv00), enables/disables output inversio n and 16-bit timer/event counter 00 timer output, enables/disables the one-shot pulse output operation, and sets the one-shot pulse output trigger via software. toc00 can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears toc00 to 00h. chapter 6 16-bit timer/event counter 00 user?s manual u15836ej5v0ud 118 figure 6-7. format of 16-bit timer ou tput control register 00 (toc00) address: ffbdh after reset: 00h r/w symbol 7 <6> <5> 4 <3> <2> 1 <0> toc00 0 ospt00 ospe00 toc004 lvs00 lvr00 toc001 toe00 ospt00 one-shot pulse output trigger control via software 0 no one-shot pulse output trigger 1 one-shot pulse output trigger ospe00 one-shot pulse output operation control 0 successive pulse output mode 1 one-shot pulse output mode note toc004 timer output f/f control using match of cr010 and tm00 0 disables inversion operation 1 enables inversion operation lvs00 lvr00 timer output f/f status setting 0 0 no change 0 1 timer output f/f reset (0) 1 0 timer output f/f set (1) 1 1 setting prohibited toc001 timer output f/f control using match of cr000 and tm00 0 disables inversion operation 1 enables inversion operation toe00 timer output control 0 disables output (output fixed to level 0) 1 enables output note the one-shot pulse output mode op erates correctly only in the free-running mode and the mode in which clear & start occurs at the ti000 vali d edge. in the mode in which clear & start occurs on a match between the tm00 register and cr000 register, one-shot pulse output is not possi ble because an overflow does not occur. cautions 1. timer operation must be st opped before setting other than toc004. 2. lvs00 and lvr00 are 0 when they are read. 3. ospt00 is automatically cleared after data is set, so 0 is read. 4. do not set ospt00 to 1 other than in one-shot pulse output mode. 5. a write interval of two cycles or more of th e count clock selected by prescaler mode register 00 (prm00) is required to write to ospt00 successively. 6. do not set lvs00 to 1 before toe00, and do not set lvs00 and toe00 to 1 simultaneously. 7. do not make settings <1> and <2> below simultan eously. in addition, follow the setting procedure shown below. <1> setting of toc001, to c004, toe00, and ospe00: setting of timer output operation <2> setting of lvs00 and lvr00: setting of timer output f/f chapter 6 16-bit timer/event counter 00 user?s manual u15836ej5v0ud 119 (4) prescaler mode register 00 (prm00) this register is used to set the 16-bit timer counter 00 (tm00) count clock and ti000 and ti010 input valid edges. prm00 can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears prm00 to 00h. figure 6-8. format of prescaler mode register 00 (prm00) address: ffbbh after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 prm00 es101 es100 es001 es000 0 0 prm001 prm000 es101 es100 ti010 valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both falling and rising edges es001 es000 ti000 valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both falling and rising edges prm001 prm000 count clock selection note 1 0 0 f x (10 mhz) 0 1 f x /2 2 (2.5 mhz) 1 0 f x /2 8 (39.06 khz) 1 1 ti000 valid edge note 2 notes 1. be sure to set the coun t clock so that the following condition is satisfied. ? v dd = 4.0 to 5.5 v: count clock 10 mhz ? v dd = 3.3 to 4.0 v: count clock 8.38 mhz ? v dd = 2.7 to 3.3 v: count clock 5 mhz ? v dd = 2.5 to 2.7 v: count clock 2.5 mhz 2. the external clock requires a pulse two cycles longer than the internal clock (f x ). cautions 1. when the ring-osc clo ck is selected as the clock to be supplied to the cpu, the clock of the ring-osc oscillator is divided and supplied as th e count clock. if the count clock is the ring-osc clock, the operation of 16-bit timer/ev ent counter 00 is not guaranteed. when an external clock is used and when the ring-osc clock is selected and supplied to the cpu, the operation of 16-bit timer/event counter 00 is not guaranteed, either, because the ring-osc clock is supplied as the samplin g clock to eliminate noise. 2. always set data to prm00 a fter stopping the timer operation. 3. if the valid edge of ti000 is to be set for the count clock, do not set the clear & start mode using the valid edge of ti 000 and the capture trigger. chapter 6 16-bit timer/event counter 00 user?s manual u15836ej5v0ud 120 cautions 4. if the ti000 or ti010 pi n is high level immediately after system reset, the rising edge is immediately detected after the rising edge or both the rising and falling edges are set as the valid edge(s) of the ti000 pin or ti010 pin to en able the operation of 16-bit timer counter 00 (tm00). care is therefore required when pul ling up the ti000 or ti010 pin. however, when the ti000 or ti010 pin is high level and re-ena bling operation after the operation has been stopped, the rising edge is not detected. 5. when p01 is used as the ti 010 valid edge input pin, it cannot be used as the timer output (to00), and when used as to00, it cannot be used as the ti010 valid edge input pin. remarks 1 . f x : x1 input clock oscillation frequency 2. ti000, ti010: 16-bit timer/ event counter 00 input pin 3. figures in parentheses are for operation with f x = 10 mhz. (5) port mode register 0 (pm0) this register sets port 0 input/output in 1-bit units. when using the p01/to00/ti010 pin for timer output, set pm01 and the output latch of p01 to 0. when using the p01/to00/ti010 pin for timer input, set pm01 to 1. the output latch of p01 at this time may be 0 or 1. pm0 can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets pm0 to ffh. figure 6-9. format of port mode register 0 (pm0) 7 1 6 1 5 1 4 1 3 pm03 2 pm02 1 pm01 0 pm00 symbol pm0 address: ff20h after reset: ffh r/w pm0n 0 1 p0n pin i/o mode selection (n = 0 to 3) output mode (output buffer on) input mode (output buffer off) chapter 6 16-bit timer/event counter 00 user?s manual u15836ej5v0ud 121 6.4 operation of 16-bit timer/event counter 00 6.4.1 interval timer operation setting 16-bit timer mode control register 00 (tmc00) and capture/compare control register 00 (crc00) as shown in figure 6-10 allows operation as an interval timer. setting the basic operation setting procedure is as follows. <1> set the crc00 register (see figure 6-10 for the set value). <2> set any value to the cr000 register. <3> set the count clock by using the prm000 register. <4> set the tmc00 register to start the operation (see figure 6-10 for the set value). caution do not rewrite cr000 during tm00 operation. remark for how to enable the inttm000 interrupt, see chapter 14 interrupt functions . interrupt requests are generated repeatedly using the count value preset in 16-bit timer capture/compare register 000 (cr000) as the interval. when the count value of 16-bit timer counter 00 (tm00) matches the value set in cr000, counting continues with the tm00 value cleared to 0 and the interrupt request signal (inttm000) is generated. the count clock of 16-bit timer/event counter 00 can be selected with bits 0 and 1 (prm000, prm001) of prescaler mode register 00 (prm00). chapter 6 16-bit timer/event counter 00 user?s manual u15836ej5v0ud 122 figure 6-10. control register setti ngs for interval timer operation (a) 16-bit timer mode control register 00 (tmc00) 7 0 6 0 5 0 4 0 tmc003 1 tmc002 1 tmc001 0/1 ovf0 0 0 tmc00 clears and starts on match between tm00 and cr000. (b) capture/compare cont rol register 00 (crc00) 7 0 6 0 5 0 4 0 3 0 crc002 0/1 crc001 0/1 crc000 0 crc00 cr000 used as compare register (c) prescaler mode register 00 (prm00) es101 0/1 es100 0/1 es001 0/1 es000 0/1 3 0 2 0 prm001 0/1 prm000 0/1 prm00 selects count clock. setting invalid (setting ?10? is prohibited.) setting invalid (setting ?10? is prohibited.) remark 0/1: setting 0 or 1 allows another function to be used simultaneously with the interval timer. see the description of the respective control registers for details. chapter 6 16-bit timer/event counter 00 user?s manual u15836ej5v0ud 123 figure 6-11. interval ti mer configuration diagram 16-bit timer capture/compare register 000 (cr000) 16-bit timer counter 00 (tm00) ovf00 clear circuit inttm000 f x f x /2 2 f x /2 8 ti000/p00 selector noise eliminator f x note note ovf00 is set to 1 only when cr000 is set to ffffh. figure 6-12. timing of interval timer operation count clock t tm00 count value cr000 inttm000 0000h 0001h n 0000h 0001h n 0000h 0001h n n n n n timer operation enabled clear clear interrupt acknowledged interrupt acknowledged remark interval time = (n + 1) chapter 6 16-bit timer/event counter 00 user?s manual u15836ej5v0ud 124 6.4.2 ppg output operations setting 16-bit timer mode control register 00 (tmc00) and capture/compare control register 00 (crc00) as shown in figure 6-13 allows operation as ppg (programmable pulse generator) output. setting the basic operation setting procedure is as follows. <1> set the crc00 register (see figure 6-13 for the set value). <2> set any value to the cr000 register as the cycle. <3> set any value to the cr010 register as the duty factor. <4> set the toc00 register (see figure 6-13 for the set value). <5> set the count clock by using the prm00 register. <6> set the tmc00 register to start the operation (see figure 6-13 for the set value). caution to change the value of the duty factor (the value of the cr010 register) during operation, see caution 2 in figure 6-15 ppg output operation timing. remarks 1. for the setting of the to00 pin, see 6.3 (5) port mode register 0 (pm0) . 2. for how to enable the inttm000 interrupt, see chapter 14 interrupt functions . in the ppg output oper ation, rectangular wa ves are output from the to00 pin with the pulse wi dth and the cycle that correspond to the count values preset in 16-bit time r capture/compare register 010 (cr010) and in 16-bit timer capture/compare register 000 (cr000), respectively. chapter 6 16-bit timer/event counter 00 user?s manual u15836ej5v0ud 125 figure 6-13. control register settings for ppg output operation (a) 16-bit timer mode control register 00 (tmc00) 7 0 6 0 5 0 4 0 tmc003 1 tmc002 1 tmc001 0 ovf00 0 tmc00 clears and starts on match between tm00 and cr000. (b) capture/compare cont rol register 00 (crc00) 7 0 6 0 5 0 4 0 3 0 crc002 0 crc001 chapter 6 16-bit timer/event counter 00 user?s manual u15836ej5v0ud 126 figure 6-14. configuration of ppg output 16-bit timer capture/compare register 000 (cr000) 16-bit timer counter 00 (tm00) clear circuit noise eliminator f x f x f x /2 2 f x /2 8 ti000/p00 16-bit timer capture/compare register 010 (cr010) to00/ti010/p01 selector output controller figure 6-15. ppg output operation timing t 0000h 0000h 0001h 0001h m ? 1 count clock tm00 count value to00 pulse width: (m + 1) t 1 cycle: (n + 1) t n cr000 capture value cr010 capture value m m n ? 1 n n clear clear cautions 1. do not rewrit e cr000 during tm00 operation. 2. in the ppg output operation, change th e pulse width (rewrite cr010) during tm00 operation using the following procedure. <1> disable the timer output inversion operati on by match of tm00 and cr010 (toc004 = 0) <2> disable the inttm010 interrupt (tmmk010 = 1) <3> rewrite cr010 <4> wait for 1 cycle of the tm00 count clock <5> enable the timer output inversion operati on by match of tm00 and cr010 (toc004 = 1) <6> clear the interrupt request flag of inttm010 (tmif010 = 0) <7> enable the inttm010 interrupt (tmmk010 = 0) remark 0000h m < n ffffh chapter 6 16-bit timer/event counter 00 user?s manual u15836ej5v0ud 127 6.4.3 pulse width measurement operations it is possible to measure the pulse width of the signals input to the ti000 pin and ti010 pin using 16-bit timer counter 00 (tm00). there are two measurement methods: measuring with tm00 used in free-running mode, and measuring by restarting the timer in synchronization with th e edge of the signal in put to the ti000 pin. when an interrupt occurs, read the valid value of the capt ure register, check the overflow flag, and then calculate the necessary pulse width. clear the overflow flag after checking it. the capture operation is not performed unt il the signal pulse width is sampl ed in the count clock cycle selected by prescaler mode register 00 (prm00) and the valid level of the ti000 or ti010 pin is dete cted twice, thus eliminating noise with a short pulse width. figure 6-16. cr010 capture operat ion with rising edge specified count clock tm00 ti000 rising edge detection cr010 inttm010 n ? ? ? chapter 6 16-bit timer/event counter 00 user?s manual u15836ej5v0ud 128 (1) pulse width measurement with free-runni ng counter and one capture register when 16-bit timer counter 00 (tm00) is operated in free-ru nning mode, and the edge specified by prescaler mode register 00 (prm00) is input to the ti000 pin, the value of tm00 is taken into 16-bit timer capture/compare register 010 (cr010) and an external interrupt request signal (inttm010) is set. specify both the rising and falling edges of the ti000 pin by using bits 4 and 5 (es000 and es001) of prm00. sampling is performed using the count clock selected by prm00, and a capture operation is only performed when the valid level of the ti000 pin is detected twic e, thus eliminating noise with a short pulse width. figure 6-17. control register settings for pul se width measurement with free-running counter and one capture register (when ti000 and cr010 are used) (a) 16-bit timer mode control register 00 (tmc00) 7 0 6 0 5 0 4 0 tmc003 0 tmc002 1 tmc001 0/1 ovf00 0 tmc00 free-running mode (b) capture/compare cont rol register 00 (crc00) 7 0 6 0 5 0 4 0 3 0 crc002 1 crc001 0/1 crc000 0 crc00 cr000 used as compare register cr010 used as capture register (c) prescaler mode register 00 (prm00) es101 0/1 es100 0/1 es001 1 es000 1 3 0 2 0 prm001 0/1 prm000 0/1 prm00 selects count clock (setting ?11? is prohibited). specifies both edges for pulse width detection. setting invalid (setting ?10? is prohibited.) remark 0/1: setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. see the description of the respecti ve control registers for details. chapter 6 16-bit timer/event counter 00 user?s manual u15836ej5v0ud 129 figure 6-18. configuration di agram for pulse width measureme nt with free-running counter f x f x /2 2 f x /2 8 ti000 16-bit timer counter 00 (tm00) ovf00 16-bit timer capture/compare register 010 (cr010) internal bus inttm010 selector figure 6-19. timing of pulse width measureme nt operation with free-running counter and one capture register ( with both edges specified) t 0000h 0000h ffffh 0001h d0 d0 count clock tm00 count value ti000 pin input cr010 capture value inttm010 ovf00 (d1 ? d0) chapter 6 16-bit timer/event counter 00 user?s manual u15836ej5v0ud 130 (2) measurement of two pulse widths with free-running counter when 16-bit timer counter 00 (tm00) is operated in free- running mode, it is possible to simultaneously measure the pulse widths of the two signals input to the ti000 pin and the ti010 pin. when the edge specified by bits 4 and 5 (es000 and es001) of prescaler mode register 00 (prm00) is input to the ti000 pin, the value of tm00 is taken into 16-bit time r capture/compare register 010 (cr010) and an interrupt request signal (inttm010) is set. also, when the edge specified by bits 6 and 7 (es100 and es101) of prm00 is input to the ti010 pin, the value of tm00 is taken into 16-bit timer capture/compare register 000 (cr000) and an interrupt request signal (inttm000) is set. specify both the rising and falling edges as the edges of the ti000 and ti010 pins, by using bits 4 and 5 (es000 and es001) and bits 6 and 7 (es100 and es101) of prm00. sampling is performed at the interval selected by pres caler mode register 00 (prm00), and a capture operation is only performed when the valid level of the ti000 pin or ti010 pin is detected twice, t hus eliminating noise with a short pulse width. figure 6-20. control register settings for measure ment of two pulse widths with free-running counter (a) 16-bit timer mode control register 00 (tmc00) 7 0 6 0 5 0 4 0 tmc003 0 tmc002 1 tmc001 0/1 ovf00 0 tmc00 free-running mode (b) capture/compare control register 00 (crc00) 7 0 6 0 5 0 4 0 3 0 crc002 1 crc001 0 crc000 1 crc00 cr000 used as capture register captures valid edge of ti010 pin to cr000 cr010 used as capture register (c) prescaler mode register 00 (prm00) es101 1 es100 1 es001 1 es000 1 3 0 2 0 prm001 0/1 prm000 0/1 prm00 selects count clock (setting ?11? is prohibited). specifies both edges for pulse width detection. specifies both edges for pulse width detection. remark 0/1: setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. see the description of the respecti ve control registers for details. chapter 6 16-bit timer/event counter 00 user?s manual u15836ej5v0ud 131 figure 6-21. timing of pulse width measure ment operation with free-running counter (with both edges specified) t 0000h 0000h ffffh 0001h d0 d0 ti010 pin input cr000 capture value inttm010 inttm000 ovf00 (d1 ? d0) chapter 6 16-bit timer/event counter 00 user?s manual u15836ej5v0ud 132 (3) pulse width measurement with free-runni ng counter and two capture registers when 16-bit timer counter 00 (tm00) is operated in free -running mode, it is possible to measure the pulse width of the signal input to the ti000 pin. when the rising or falling edge specified by bits 4 and 5 (es000 and es001) of prescaler mode register 00 (prm00) is input to the ti000 pin, the value of tm00 is taken into 16-bi t timer capture/compare register 010 (cr010) and an interrupt request signal (inttm010) is set. also, when the inverse edge to that of the capture operation is input into cr 010, the value of tm00 is taken into 16-bit timer capture/compare register 000 (cr000). sampling is performed at the interval selected by pres caler mode register 00 (prm00), and a capture operation is only performed when the valid level of the ti000 pin is dete cted twice, thus eliminating noise with a short pulse width. figure 6-22. control register settings for pulse width measurement with fr ee-running counter and two capture registers (with rising edge specified) (a) 16-bit timer mode control register 00 (tmc00) 7 0 6 0 5 0 4 0 tmc003 0 tmc002 1 tmc001 0/1 ovf00 0 tmc00 free-running mode (b) capture/compare cont rol register 00 (crc00) 7 0 6 0 5 0 4 0 3 0 crc002 1 crc001 1 crc000 1 crc00 cr000 used as capture register captures to cr000 at inverse edge to valid edge of ti000. cr010 used as capture register (c) prescaler mode register 00 (prm00) es101 0/1 es100 0/1 es001 0 es000 1 3 0 2 0 prm001 0/1 prm000 0/1 prm00 selects count clock (setting ?11? is prohibited). specifies rising edge for pulse width detection. setting invalid (setting ?10? is prohibited.) remark 0/1: setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. see the description of the respecti ve control registers for details. chapter 6 16-bit timer/event counter 00 user?s manual u15836ej5v0ud 133 figure 6-23. timing of pulse width measureme nt operation with free-running counter and two capture registers (with rising edge specified) t 0000h 0000h ffffh 0001h d0 d0 inttm010 ovf00 d2 d1 d3 d2 d3 d0 + 1 d2 + 1 d1 d1 + 1 cr000 capture value count clock tm00 count value ti000 pin input cr010 capture value (d1 ? d0) ? ? chapter 6 16-bit timer/event counter 00 user?s manual u15836ej5v0ud 134 figure 6-24. control register settings for pul se width measurement by means of restart (with rising edge specified) (a) 16-bit timer mode control register 00 (tmc00) 7 0 6 0 5 0 4 0 tmc003 1 tmc002 0 tmc001 0/1 ovf00 0 tmc00 clears and starts at valid edge of ti000 pin. (b) capture/compare cont rol register 00 (crc00) 7 0 6 0 5 0 4 0 3 0 crc002 1 crc001 1 crc000 1 crc00 cr000 used as capture register captures to cr000 at inverse edge to valid edge of ti000. cr010 used as capture register (c) prescaler mode register 00 (prm00) es101 0/1 es100 0/1 es001 0 es000 1 3 0 2 0 prm001 0/1 prm000 0/1 prm00 selects count clock (setting ?11? is prohibited). specifies rising edge for pulse width detection. setting invalid (setting ?10? is prohibited.) figure 6-25. timing of pulse width measure ment operation by means of restart (with rising edge specified) t 0000h 0001h 0000h 0001h 0000h 0001h d0 d0 inttm010 d1 chapter 6 16-bit timer/event counter 00 user?s manual u15836ej5v0ud 135 6.4.4 external event counter operation setting the basic operation setting procedure is as follows. <1> set the crc00 register (see figure 6-26 for the set value). <2> set the count clock by using the prm00 register. <3> set any value to the cr000 register (0000h cannot be set). <4> set the tmc00 register to start the operation (see figure 6-26 for the set value). remarks 1. for the setting of the ti000 pin, see 6.3 (5) port mode register 0 (pm0) . 2. for how to enable the inttm000 interrupt, see chapter 14 interrupt functions . the external event counter counts the num ber of external clock pulses input to the ti000 pin using 16-bit timer counter 00 (tm00). tm00 is incremented each time the valid edge specified by prescaler mode register 00 (prm00) is input. when the tm00 count value matches the 16-bit timer capt ure/compare register 000 (cr000) value, tm00 is cleared to 0 and the interrupt requ est signal (inttm000) is generated. input a value other than 0000h to cr000 (a count operation with 1-bit pulse cannot be carried out). any of three edges ? ? chapter 6 16-bit timer/event counter 00 user?s manual u15836ej5v0ud 136 figure 6-26. control register setti ngs in external event counter mode (with rising edge specified) (a) 16-bit timer mode control register 00 (tmc00) 7 0 6 0 5 0 4 0 tmc003 1 tmc002 1 tmc001 0/1 ovf00 0 tmc00 clears and starts on match between tm00 and cr000. (b) capture/compare cont rol register 00 (crc00) 7 0 6 0 5 0 4 0 3 0 crc002 0/1 crc001 0/1 crc000 0 crc00 cr000 used as compare register (c) prescaler mode register 00 (prm00) es101 0/1 es100 0/1 es001 0 es000 1 3 0 2 0 prm001 1 prm000 1 prm00 selects external clock. specifies rising edge for pulse width detection. setting invalid (setting ?10? is prohibited.) remark 0/1: setting 0 or 1 allows another function to be used simultaneously with the external event counter. see the description of the respecti ve control registers for details. chapter 6 16-bit timer/event counter 00 user?s manual u15836ej5v0ud 137 figure 6-27. configuration diagra m of external event counter f x internal bus 16-bit timer capture/compare register 000 (cr000) match clear ovf00 note noise eliminator 16-bit timer counter 00 (tm00) valid edge of ti000 inttm000 note ovf00 is set to 1 only when cr000 is set to ffffh. figure 6-28. external event counter oper ation timing (with rising edge specified) ti000 pin input tm00 count value cr000 inttm000 0000h 0001h 0002h 0003h 0004h 0005h n ? chapter 6 16-bit timer/event counter 00 user?s manual u15836ej5v0ud 138 6.4.5 square-wave output operation setting the basic operation setting procedure is as follows. <1> set the count clock by using the prm00 register. <2> set the crc00 register (see figure 6-29 for the set value). <3> set the toc00 register (see figure 6-29 for the set value). <4> set any value to the cr000 register (0000h cannot be set). <5> set the tmc00 register to start the operation (see figure 6-29 for the set value). caution do not rewrite cr000 during tm00 operation. remarks 1. for the setting of the to00 pin, see 6.3 (5) port mode register 0 (pm0) . 2. for how to enable the inttm000 interrupt, see chapter 14 interrupt functions . a square wave with any selected frequency can be output at intervals determined by the count value preset to 16- bit timer capture/compare register 000 (cr000). the to00 pin output status is reversed at intervals determined by the count value preset to cr000 +1 by setting bit 0 (toe00) and bit 1 (toc001) of 16-bit timer output control register 00 (toc00) to 1. this enables a square wave with any selected frequency to be output. figure 6-29. control register settings in square-wave output mode (1/2) (a) 16-bit timer mode control register 00 (tmc00) 7 0 6 0 5 0 4 0 tmc003 1 tmc002 1 tmc001 0 ovf00 0 tmc00 clears and starts on match between tm00 and cr000. (b) capture/compare cont rol register 00 (crc00) 7 0 6 0 5 0 4 0 3 0 crc002 0/1 crc001 0/1 crc000 0 crc00 cr000 used as compare register chapter 6 16-bit timer/event counter 00 user?s manual u15836ej5v0ud 139 figure 6-29. control register settings in square-wave output mode (2/2) (c) 16-bit timer output control register 00 (toc00) 7 0 ospt00 0 ospe00 0 toc004 0 lvs00 0/1 lvr00 0/1 toc001 1 toe00 1 toc00 enables to00 output. inverts output on match between tm00 and cr000. specifies initial value of to00 output f/f (setting ?11? is prohibited). does not invert output on match between tm00 and cr010. disables one-shot pulse output. (d) prescaler mode register 00 (prm00) es101 0/1 es100 0/1 es001 0/1 es000 0/1 3 0 2 0 prm001 0/1 prm000 0/1 prm00 selects count clock. setting invalid (setting ?10? is prohibited.) setting invalid (setting ?10? is prohibited.) remark 0/1: setting 0 or 1 allows another function to be used simultaneously with square-wave output. see the description of the respective control registers for details. figure 6-30. square-wave output operation timing count clock tm00 count value cr000 inttm000 to00 pin output 0000h 0001h 0002h n ? ? chapter 6 16-bit timer/event counter 00 user?s manual u15836ej5v0ud 140 6.4.6 one-shot pulse output operation 16-bit timer/event counter 00 can output a one-shot pulse in synchronization with a software trigger or an external trigger (ti000 pin input). setting the basic operation setting procedure is as follows. <1> set the count clock by using the prm00 register. <2> set the crc00 register (see figures 6-31 and 6-33 for the set value). <3> set the toc00 register (see figures 6-31 and 6-33 for the set value). <4> set any value to the cr000 and cr010 registers (0000h cannot be set). <5> set the tmc00 register to start the operation (see figures 6-31 and 6-33 for the set value). remarks 1. for the setting of the to00 pin, see 6.3 (5) port mode register 0 (pm0) . 2. for how to enable the inttm000 (if necessary, inttm010) interrupt, see chapter 14 interrupt functions . (1) one-shot pulse output with software trigger a one-shot pulse can be output from t he to00 pin by setting 16-bit timer mode control register 00 (tmc00), capture/compare control register 00 (crc00), and 16-bit timer output control register 00 (toc00) as shown in figure 6-31, and by setting bit 6 (ospt00) of the toc00 register to 1 by software. by setting the ospt00 bit to 1, 16-bit timer/event co unter 00 is cleared and starte d, and its output becomes active at the count value (n) set in advance to 16-bit time r capture/compare register 010 (cr010). after that, the output becomes inactive at the count value (m) set in advance to 16-bit timer capture/compare register 000 (cr000) note . even after the one-shot pulse has been output, the tm00 regi ster continues its operat ion. to stop the tm00 register, the tmc003 and tmc002 bits of t he tmc00 register must be set to 00. note the case where n < m is described here. w hen n > m, the output becom es active with the cr000 register and inactive with the cr010 register. do not set n to m. cautions 1. do not set the ospt00 bit to 1 while the one-shot pulse is being output. to output the one- shot pulse again, wait until the current one-shot pulse output is completed. 2. when using the one-shot pulse output of 16-bit timer/event counter 00 with a software trigger, do not change the level of the ti000 pin or its alternate-function port pin. because the external trigger is valid even in this case, the ti mer is cleared and started even at the level of the ti000 pin or its alternate -function port pin, resulting in the output of a pulse at an undesired timing. chapter 6 16-bit timer/event counter 00 user?s manual u15836ej5v0ud 141 figure 6-31. control register settings for on e-shot pulse output with software trigger (a) 16-bit timer mode control register 00 (tmc00) 0000 7654 0 tmc003 tmc00 tmc002 tmc001 ovf00 free-running mode 100 (b) capture/compare cont rol register 00 (crc00) 00000 76543 crc00 crc002 crc001 crc000 cr000 as compare register cr010 as compare register 0 0/1 0 (c) 16-bit timer output control register 00 (toc00) 0 7 0 1 1 0/1 toc00 lvr00 lvs00 toc004 ospe00 ospt00 toc001 toe00 enables to00 output inverts output upon match between tm00 and cr000 specifies initial value of to00 output f/f (setting ?11? is prohibited.) inverts output upon match between tm00 and cr010 sets one-shot pulse output mode set to 1 for output 0/1 1 1 (d) prescaler mode register 00 (prm00) 0/1 0/1 0/1 0/1 0 prm00 prm001 prm000 selects count clock. setting invalid (setting ?10? is prohibited.) 0 0/1 0/1 es101 es100 es001 es000 setting invalid (setting ?10? is prohibited.) 32 caution do not set the cr000 and cr010 registers to 0000h. chapter 6 16-bit timer/event counter 00 user?s manual u15836ej5v0ud 142 figure 6-32. timing of one-shot pulse output operation with software trigger 0000h n nn n n mm m m nm n + 1 n ? 1m ? 1 0001h m + 1 m + 2 0000h count clock tm00 count cr010 set value cr000 set value ospt00 inttm010 inttm000 to00 pin output set tmc00 to 04h (tm00 count starts) caution 16-bit timer counter 00 starts operating as soon as the tmc003 and tmc002 bits are set to a value other than 00 (operation stop mode). remark n < m (2) one-shot pulse output with external trigger a one-shot pulse can be output from t he to00 pin by setting 16-bit timer mode control register 00 (tmc00), capture/compare control register 00 (crc00), and 16-bit timer output control register 00 (toc00) as shown in figure 6-33, and by using the valid edge of the ti000 pin as an external trigger. the valid edge of the ti000 pin is specified by bits 4 and 5 (es000, es001) of prescaler mode register 00 (prm00). the rising, falling, or both the rising and falling edges can be specified. when the valid edge of the ti000 pin is detected, the 16-bit time r/event counter is clear ed and started, and the output becomes active at the count value set in advance to 16-bit timer capture/compare register 010 (cr010). after that, the output becomes inactive at the count value set in advance to 16-bit timer capture/compare register 000 (cr000) note . note the case where n < m is described here. w hen n > m, the output becom es active with the cr000 register and inactive with the cr010 register. do not set n to m. caution even if the external trigge r is generated again while the one -shot pulse is being output, it is ignored. chapter 6 16-bit timer/event counter 00 user?s manual u15836ej5v0ud 143 figure 6-33. control register settings for one- shot pulse output with external trigger (with rising edge specified) (a) 16-bit timer mode control register 00 (tmc00) 0000 7654 1 tmc003 tmc00 tmc002 tmc001 ovf00 clears and starts at valid edge of ti000 pin 000 (b) capture/compare cont rol register 00 (crc00) 00000 76543 crc00 crc002 crc001 crc000 cr000 used as compare register cr010 used as compare register 0 0/1 0 (c) 16-bit timer output control register 00 (toc00) 0 7 01 1 0/1 toc00 lvr00 toc001 toe00 ospe00 ospt00 toc004 lvs00 enables to00 output inverts output upon match between tm00 and cr000 specifies initial value of to00 output f/f (setting ?11? is prohibited.) inverts output upon match between tm00 and cr010 sets one-shot pulse output mode 0/1 1 1 (d) prescaler mode register 00 (prm00) 0/1 0/1 0 1 prm00 prm001 prm000 selects count clock (setting ?11? is prohibited). specifies the rising edge for pulse width detection. 0/1 0/1 es101 es100 es001 es000 setting invalid (setting ?10? is prohibited.) 00 32 caution do not set the cr000 and cr010 registers to 0000h. chapter 6 16-bit timer/event counter 00 user?s manual u15836ej5v0ud 144 figure 6-34. timing of one-shot pulse output operation with external trigger (wit h rising edge specified) 0000h n nn n n mm m m m n + 1 n + 2 m + 1 m + 2 m ? ? chapter 6 16-bit timer/event counter 00 user?s manual u15836ej5v0ud 145 6.5 cautions for 16-bit timer/event counter 00 (1) timer start errors an error of up to one clock may occur in the time requir ed for a match signal to be generated after timer start. this is because 16-bit timer counter 00 (tm00) is started asynchronously to the count clock. figure 6-35. start timing of 16-bit timer counter 00 (tm00) tm00 count value 0000h 0001h 0002h 0004h count clock timer start 0003h (2) 16-bit timer capture/comp are registers 000, 010 setting in the mode in which clear & start occurs on match bet ween tm00 and cr000, set 16-bit timer capture/compare registers 000, 010 (cr000, cr010) to other than 0000h. this means a 1-pulse count operation cannot be performed when 16-bit timer/event counter 00 is used as an external event counter. (3) capture register data retention timing the values of 16-bit timer capture/ compare registers 000 and 010 (cr000 and cr010) are not guaranteed after 16-bit timer/event counter 00 has been stopped. (4) valid edge setting set the valid edge of the ti000 pin after setting bits 2 and 3 (tmc002 and tmc003) of 16-bit timer mode control register 00 (tmc00) to 0, 0, respectively, and then sto pping timer operation. the valid edge is set using bits 4 and 5 (es000 and es001) of prescaler mode register 00 (prm00). (5) re-triggering one-shot pulse (a) one-shot pulse output by software when a one-shot pulse is output, do not set the ospt00 bit to 1. do not output the one-shot pulse again until inttm000, which occurs upon a match with the cr000 register, or inttm010, which occurs upon a match with the cr010 register, occurs. (b) one-shot pulse output with external trigger if the external trigger occurs again while a one-shot pulse is output, it is ignored. (c) one-shot pulse output function when using the one-shot pulse output of 16-bit timer/ev ent counter 00 with a software trigger, do not change the level of the ti000 pin or its alternate function port pin. because the external trigger is valid even in this case, the timer is cleared and started even at the level of the ti000 pin or its alternate function port pin, resulting in the output of a pulse at an undesired timing. chapter 6 16-bit timer/event counter 00 user?s manual u15836ej5v0ud 146 (6) operation of ovf00 flag <1> the ovf00 flag is also set to 1 in the following case. if any of the following modes: t he mode in which clear & start occurs on a match between tm00 and cr000, the mode in which clear & start occurs on a ti 000 valid edge, or the free-running mode, is selected cr000 is set to ffffh. tm00 is counted up from ffffh to 0000h. figure 6-36. operation timing of ovf00 flag count clock cr000 tm00 ovf00 inttm000 ffffh fffeh ffffh 0000h 0001h <2> even if the ovf00 flag is clear ed before the next count clock (bef ore tm00 becomes 0001h) after the occurrence of tm00 overflow, the ovf00 flag is re-set newly and clear is disabled. (7) conflicting operations when the read period of the 16-bit timer capture/comp are register (cr000/cr010) and capture trigger input (cr000/cr010 used as capture register) conflict, capt ure trigger input has priority. the data read from cr000/cr010 is undefined. figure 6-37. capture regist er data retention timing count clock tm00 count value edge input inttm010 capture read signal cr010 capture value n n + 1 n + 2 m m + 1 m + 2 x n + 2 capture, but read value is not guaranteed capture m + 1 chapter 6 16-bit timer/event counter 00 user?s manual u15836ej5v0ud 147 (8) timer operation <1> even if 16-bit timer counter 00 (tm00) is read, t he value is not captured by 16-bit timer capture/compare register 010 (cr010). <2> regardless of the cpu?s operation mode, when the timer stops, the input signals to the ti000/ti010 pins are not acknowledged. <3> the one-shot pulse output mode oper ates correctly only in the free-ru nning mode and the mode in which clear & start occurs at the ti000 vali d edge. in the mode in which clear & start occurs on a match between the tm00 register and cr000 register, one-shot pulse output is not possi ble because an overflow does not occur. (9) capture operation <1> if ti000 valid edge is specified as the count clock, a capture operation by the capt ure register specified as the trigger for ti000 is not possible. <2> to ensure the reliability of the capture operation, the capture trigger requires a pulse two cycles longer than the count clock selected by prescaler mode register 00 (prm00). <3> the capture operation is performed at the falling edge of the count clock. an interrupt request input (inttm000/inttm010), however, is generated at the rise of the next count clock. (10) compare operation a capture operation may not be performed for cr000/cr010 se t in compare mode even if a capture trigger has been input. (11) edge detection <1> if the ti000 or ti010 pin is high level immediately a fter system reset and the rising edge or both the rising and falling edges are specified as the valid edge of the ti 000 or ti010 pin to enable the 16-bit timer counter 00 (tm00) operation, a rising edge is detected immediately after the operation is enabled. be careful therefore when pulling up the ti000 or ti 010 pin. however, when the ti000 or ti010 pin is high level, the rising edge is not detected at restar t after the operation has been stopped. <2> the sampling clock used to eliminate noise diffe rs when the ti000 valid edge is used as the count clock and when it is used as a capture trigger. in the former case, the count clock is f x , and in the latter case the count clock is selected by prescaler mode register 00 (prm00). the capture operation is started only after a valid level is detected twice by sampling the valid edg e, thus eliminating noise with a short pulse width. user?s manual u15836ej5v0ud 148 chapter 7 8-bit ti mer/event counter 50 7.1 functions of 8-bit timer/event counter 50 8-bit timer/event counter 50 has the following functions. ? ? ? ? chapter 7 8-bit timer/event counter 50 user?s manual u15836ej5v0ud 149 7.2 configuration of 8-bit timer/event counter 50 8-bit timer/event counter 50 includes the following hardware. table 7-1. configuration of 8-bit timer/event counter 50 item configuration timer register 8-bit timer counter 50 (tm50) register 8-bit timer compare register 50 (cr50) timer input ti50 timer output to50 control registers timer clock selection register 50 (tcl50) 8-bit timer mode control register 50 (tmc50) port mode register 1 (pm1) port register 1 (p1) (1) 8-bit timer counter 50 (tm50) tm50 is an 8-bit register that count s the count pulses and is read-only. the counter is incremented is synchronization with the rising edge of the count clock. figure 7-2. format of 8-bit timer counter 50 (tm50) symbol tm50 address: ff16h after reset: 00h r in the following situations, the count value is cleared to 00h. <1> reset input <2> when tce50 is cleared <3> when tm50 and cr50 match in clear & start mode if this mode was entered upon a match of tm50 and cr50 values. chapter 7 8-bit timer/event counter 50 user?s manual u15836ej5v0ud 150 (2) 8-bit timer compare register 50 (cr50) cr50 can be read and written by an 8-bi t memory manipulation instruction. except in pwm mode, the value set in cr50 is constantly compared with the 8-bit timer counter 50 (tm50) count value, and an interrupt request (in ttm50) is generated if they match. in pwm mode, when the to50 pin becomes high level due to a tm50 overflow and the values of tm50 and cr50 match, the to50 pin becomes inactive. the value of cr50 can be set within 00h to ffh. reset input clears this register to 00h. figure 7-3. format of 8-bit time r compare register 50 (cr50) symbol cr50 address: ff17h after reset: 00h r/w cautions 1. in the clear & start mode entered on a match of tm50 and cr50 (tmc506 = 0), do not write other values to cr50 during operation. 2. in pwm mode, make the cr50 rewrite peri od 3 count clocks of th e count clock (clock selected by tcl50) or more. chapter 7 8-bit timer/event counter 50 user?s manual u15836ej5v0ud 151 7.3 registers controlling 8- bit timer/event counter 50 the following four registers are used to control 8-bit timer/event counter 50. ? timer clock selection register 50 (tcl50) ? 8-bit timer mode control register 50 (tmc50) ? port mode register 1 (pm1) ? port register 1 (p1) (1) timer clock selecti on register 50 (tcl50) this register sets the count clock of 8-bit time r/event counter 50 and the valid edge of ti50 input. tcl50 can be set by an 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 7-4. format of timer clo ck selection register 50 (tcl50) address: ff6ah after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 tcl50 0 0 0 0 0 tcl502 tcl501 tcl500 tcl502 tcl501 tcl500 count clock selection note 0 0 0 ti50 falling edge 0 0 1 ti50 rising edge 0 1 0 f x (10 mhz) 0 1 1 f x /2 (5 mhz) 1 0 0 f x /2 2 (2.5 mhz) 1 0 1 f x /2 6 (156.25 khz) 1 1 0 f x /2 8 (39.06 khz) 1 1 1 f x /2 13 (1.22 khz) note be sure to set the coun t clock so that the following condition is satisfied. ? v dd = 4.0 to 5.5 v: count clock 10 mhz ? v dd = 3.3 to 4.0 v: count clock 8.38 mhz ? v dd = 2.7 to 3.3 v: count clock 5 mhz ? v dd = 2.5 to 2.7 v: count clock 2.5 mhz cautions 1. when the ring-osc clo ck is selected as the clock to be supplied to the cpu, the clock of the ring-osc oscillator is divided and supplied as th e count clock. if the count clock is the ring-osc clock, the operation of 8-bit ti mer/event counter 50 is not guaranteed. 2. when rewriting tcl50 to other than the sa me data, stop the time r operation beforehand. 3. be sure to clea r bits 3 to 7 to 0. remarks 1. f x : x1 input clock oscillation frequency 2. figures in parentheses apply to operation at f x = 10 mhz. chapter 7 8-bit timer/event counter 50 user?s manual u15836ej5v0ud 152 (2) 8-bit timer mode control register 50 (tmc50) tmc50 is a register that performs the following five types of settings. <1> 8-bit timer counter 50 (tm50) count operation control <2> 8-bit timer counter 50 (tm50) operating mode selection <3> timer output f/f (flip-flop) status setting <4> active level selection in timer f/f control or pwm (free-running) mode <5> timer output control tmc50 can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 7-5 shows the tmc50 format. figure 7-5. format of 8-bit timer mode control register 50 (tmc50) address: ff6bh after reset: 00h r/w note symbol <7> 6 5 4 <3> <2> 1 <0> tmc50 tce50 tmc506 0 0 lvs50 lvr50 tmc501 toe50 tce50 tm50 count operation control 0 after clearing to 0, count operation disabled (counter stopped) 1 count operation start tmc506 tm50 operating mode selection 0 clear & start mode by match between tm50 and cr50 1 pwm (free-running) mode lvs50 lvr50 timer output f/f status setting 0 0 no change 0 1 timer output f/f reset (0) 1 0 timer output f/f set (1) 1 1 setting prohibited in other modes (tmc506 = 0) in pwm mode (tmc506 = 1) tmc501 timer f/f control active level selection 0 inversion operation disabled active high 1 inversion operation enabled active low toe50 timer output control 0 output disabled (tm50 outputs the low level) 1 output enabled note bits 2 and 3 are write-only. chapter 7 8-bit timer/event counter 50 user?s manual u15836ej5v0ud 153 cautions 1. the settings of lvs50 and lv r50 are valid in other than pwm mode. 2. do not make settings <1> to <4> below simultaneously. in addition, follow the setting procedure shown below. <1> setting of tmc501 and tm c506: setting of operation mode <2> setting of toe50 if enabling output: enabling timer output <3> setting of lvs50 and lvr50 (see caution 1): setting of timer f/f <4> setting of tce50 3. stop operation before rewriting tmc506. remarks 1. in pwm mode, pwm output is made inactive by setting tce50 to 0. 2. if lvs50 and lvr50 are read, 0 is read. 3. the values of the tmc506, lvs50, lvr50, tmc 501, and toe50 bits are re flected at the to50 pin regardless of the value of tce50. (3) port mode register 1 (pm1) this register sets port 1 input/output in 1-bit units. when using the p17/to50/ti50 pin for timer output, cl ear pm17 and the output latch of p17 to 0. when using the p17/to50/ti50 pin for timer input, set pm17 to 1. the output latch of p17 at this time may be 0 or 1. pm1 can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to ffh. figure 7-6. format of port mode register 1 (pm1) address: ff21h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm1 pm17 pm16 pm15 pm14 pm13 pm12 pm11 pm10 pm1n p1n pin i/o mode selection (n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) chapter 7 8-bit timer/event counter 50 user?s manual u15836ej5v0ud 154 7.4 operations of 8-bit timer/event counter 50 7.4.1 operation as interval timer 8-bit timer/event counter 50 operates as an interval timer t hat generates interrupt reques ts repeatedly at intervals of the count value preset to 8-bi t timer compare register 50 (cr50). when the count value of 8-bit timer counter 50 (tm50) ma tches the value set to cr50, counting continues with the tm50 value cleared to 0 and an interrupt request signal (inttm50) is generated. the count clock of tm50 can be selected with bits 0 to 2 (tcl500 to tcl502) of timer clock selection register 50 (tcl50). setting <1> set the registers. ? ? ? chapter 7 8-bit timer/event counter 50 user?s manual u15836ej5v0ud 155 figure 7-7. interval timer operation timing (2/2) (b) when cr50 = 00h t interval time count clock tm50 cr50 tce50 inttm50 00h 00h 00h 00h 00h (c) when cr50 = ffh t count clock tm50 cr50 tce50 inttm50 01h feh ffh 00h feh ffh 00h ffh ffh ffh interval time interrupt acknowledged interrupt acknowledged chapter 7 8-bit timer/event counter 50 user?s manual u15836ej5v0ud 156 7.4.2 operation as external event counter the external event counter c ounts the number of external clock pulses to be input to ti50 by 8-bit timer counter 50 (tm50). tm50 is incremented each time the valid edge specified by timer clock selection regist er 50 (tcl50) is input. either the rising or falling edge can be selected. when the tm50 count value matches the value of 8-bit ti mer compare register 50 (cr50), tm50 is cleared to 0 and an interrupt request signal (inttm50) is generated. whenever the tm50 count value matches t he value of cr50, inttm50 is generated. setting <1> set each register. ? ? ? ? chapter 7 8-bit timer/event counter 50 user?s manual u15836ej5v0ud 157 7.4.3 operation as square-wave output a square wave with any selected frequency is output at in tervals determined by the value preset to 8-bit timer compare register 50 (cr50). the to50 pin output status is inverted at intervals determined by the count value preset to cr50 by setting bit 0 (toe50) of 8-bit timer mode control register 50 (tmc50 ) to 1. this enables a square wave with any selected frequency to be output (duty = 50%). setting <1> set each register. ? ? ? ? ? ? chapter 7 8-bit timer/event counter 50 user?s manual u15836ej5v0ud 158 7.4.4 operation as pwm output 8-bit timer/event counter 50 operates as a pwm output when bit 6 (tmc506) of 8-bit timer mode control register 50 (tmc50) is set to 1. the duty pulse is determined by the value set to 8-bit timer compare register 50 (cr50). set the active level width of the pwm pulse to cr50; the active level can be selected with bit 1 of tmc50 (tmc501). the count clock can be selected with bits 0 to 2 (tcl500 to tcl502) of timer clock selection register 50 (tcl50). pwm output can be enabled/disabled with bit 0 of tmc50 (toe50). caution in pwm mode, make the cr50 rewrite period 3 count clocks of the count clock (clock selected by tcl50) or more. (1) pwm output basic operation setting <1> set each register. ? ? ? ? ? ? ? chapter 7 8-bit timer/event counter 50 user?s manual u15836ej5v0ud 159 figure 7-10. pwm output operation timing (a) basic operation (active level = h) count clock tm50 cr50 tce50 inttm50 to50 00h 01h ffh 00h 01h 02h n n+1 ffh 00h 01h 02h m 00h n <2> active level active level <3> inactive level <1> <5> t (b) cr50 = 00h count clock tm50 cr50 tce50 inttm50 to50 l inactive level inactive level 01h 00h ffh 00h 01h 02h n n+1 ffh 00h 01h 02h m 00h 00h n+2 t (c) cr50 = ffh tm50 count clock cr50 tce50 inttm50 to50 01h 00h ffh 00h 01h 02h n n+1 ffh 00h 01h 02h m 00h ffh n+2 inactive level active level inactive level active level inactive level t remark <1> to <3> and <5> in figure 7-10 (a) correspond to <1> to <3> and <5> in pwm output operation in 7.4.4 (1) pwm output basic operation . chapter 7 8-bit timer/event counter 50 user?s manual u15836ej5v0ud 160 (2) operation with cr50 changed figure 7-11. timing of operation with cr50 changed (a) cr50 value is changed from n to m before clock rising edge of ffh user?s manual u15836ej5v0ud 161 chapter 8 8-bit timers h0 and h1 8.1 functions of 8-bit timers h0 and h1 8-bit timers h0 and h1 have the following functions. ? ? ? chapter 8 8-bit timers h0 and h1 user?s manual u15836ej5v0ud 162 match internal bus tmhe0 cks02 cks01 cks00 tmmd01tmmd00 tolev0 toen0 8-bit timer h mode control register 0 (tmhmd0) 8-bit timer h compare register 10 (cmp10) decoder toh0/p15 inttmh0 selector f x f x /2 f x /2 2 f x /2 6 f x /2 10 interrupt generator output controller level inversion 1 0 f/f r 8-bit timer counter h0 pwm mode signal timer h enable signal clear 3 2 8-bit timer h compare register 00 (cmp00) selector output latch (p15) pm15 8-bit timer/ event counter 50 output figure 8-1. block diag ram of 8-bit timer h0 chapter 8 8-bit timers h0 and h1 user?s manual u15836ej5v0ud 163 match internal bus tmhe1 cks12 cks11 cks10 tmmd11tmmd10 tolev1 toen1 8-bit timer h mode control register 1 (tmhmd1) 8-bit timer h compare register 11 (cmp11) decoder toh1/ intp5/ p16 inttmh1 selector f x f x /2 2 f x /2 4 f x /2 6 f x /2 12 f r /2 7 interrupt generator output controller level inversion 1 0 f/f r pwm mode signal timer h enable signal 3 2 8-bit timer h compare register 01 (cmp01) 8-bit timer counter h1 clear selector output latch (p16) pm16 figure 8-2. block diag ram of 8-bit timer h1 chapter 8 8-bit timers h0 and h1 user?s manual u15836ej5v0ud 164 (1) 8-bit timer h compare register 0n (cmp0n) this register can be read/written by an 8- bit memory manipula tion instruction. reset input clears this register to 00h. figure 8-3. format of 8-bit time r h compare register 0n (cmp0n) symbol cmp0n (n = 0, 1) address: ff18h (cmp00), ff1ah (cmp01) after reset: 00h r/w 7 6 5 4 32 1 0 caution cmp0n cannot be rewritte n during timer count operation. (2) 8-bit timer h compare register 1n (cmp1n) this register can be read/written by an 8- bit memory manipula tion instruction. reset input clears this register to 00h. figure 8-4. format of 8-bit time r h compare register 1n (cmp1n) symbol cmp1n (n = 0, 1) address: ff19h (cmp10), ff1bh (cmp11) after reset: 00h r/w 7 6 5 4 32 1 0 cmp1n can be rewritten during timer count operation. if the cmp1n value is rewritten during timer operation, transf er is performed at the timing at which the count value and cmp1n value match. if the transfer timing and writing from cpu to cmp1n conflict, transfer is not performed. caution in the pwm output mode be sure to set cm p1n when starting the timer count operation (tmhen = 1) after the timer count operation was stopped (tmhen = 0) (be sure to set again even if setting the same value to cmp1n). remark n = 0, 1 chapter 8 8-bit timers h0 and h1 user?s manual u15836ej5v0ud 165 8.3 registers controlling 8-bit timers h0 and h1 the following three registers are used to control 8-bit timers h0 and h1. ? ? ? chapter 8 8-bit timers h0 and h1 user?s manual u15836ej5v0ud 166 figure 8-5. format of 8-bit time r h mode register 0 (tmhmd0) tmhe0 stops timer count operation (counter is cleared to 0) enables timer count operation (count operation started by inputting clock) tmhe0 0 1 timer operation enable tmhmd0 symbol cks02 cks01 cks00 tmmd01 tmmd00 tolev0 toen0 address: ff69h after reset: 00h r/w f x f x /2 f x /2 2 f x /2 6 f x /2 10 tm50 output note 2 cks02 0 0 0 0 1 1 cks01 0 0 1 1 0 0 cks00 0 1 0 1 0 1 (10 mhz) (5 mhz) (2.5 mhz) (156.25 khz) (9.77 khz) count clock (f cnt ) selection note 1 setting prohibited other than above interval timer mode pwm output mode setting prohibited tmmd01 0 1 tmmd00 0 0 timer operation mode low level high level tolev0 0 1 timer output level control (in default mode) disables output enables output toen0 0 1 timer output control other than above <7> 6 5 4 3 2 <1> <0> notes 1. be sure to set the coun t clock so that the following condition is satisfied. ? ? ? ? ? ? chapter 8 8-bit timers h0 and h1 user?s manual u15836ej5v0ud 167 cautions 1. when the ring-osc clo ck is selected as the clock to be supplied to the cpu, the clock of the ring-osc oscillator is divided and supplied as th e count clock. if the count clock is the ring-osc clock, the operation of 8-bit timer h0 is not guaranteed. 2. when tmhe0 = 1, setting the other bits of tmhmd0 is prohibited. 3. in the pwm output mode, be sure to set 8- bit timer h compare register 10 (cmp10) when starting the timer count operation (tmhe0 = 1) after the timer count operation was stopped (tmhe0 = 0) (be sure to set again even if setting the same value to cmp10). remarks 1. f x : x1 input clock oscillation frequency 2. figures in parentheses apply to operation at f x = 10 mhz figure 8-6. format of 8-bit time r h mode register 1 (tmhmd1) tmhe1 stops timer count operation (counter is cleared to 0) enables timer count operation (count operation started by inputting clock) tmhe1 0 1 timer operation enable tmhmd1 symbol cks12 cks11 cks10 tmmd11 tmmd10 tolev1 toen1 address: ff6ch after reset: 00h r/w f x f x /2 2 f x /2 4 f x /2 6 f x /2 12 f r /2 7 cks12 0 0 0 0 1 1 cks11 0 0 1 1 0 0 cks10 0 1 0 1 0 1 (10 mhz) (2.5 mhz) (625 khz) (156.25 khz) (2.44 khz) (1.88 khz (typ.)) count clock selection note setting prohibited other than above interval timer mode pwm output mode setting prohibited tmmd11 0 1 tmmd10 0 0 timer operation mode low level high level tolev1 0 1 timer output level control (in default mode) disables output enables output toen1 0 1 timer output control other than above <7> 6 5 4 3 2 <1> <0> chapter 8 8-bit timers h0 and h1 user?s manual u15836ej5v0ud 168 note be sure to set the coun t clock so that the following condition is satisfied. ? ? ? ? chapter 8 8-bit timers h0 and h1 user?s manual u15836ej5v0ud 169 8.4 operation of 8-bit timers h0 and h1 8.4.1 operation as inter val timer/square-wave output when 8-bit timer counter hn and compare register 0n (cmp0n) match, an interrupt request signal (inttmhn) is generated and 8-bit timer counter hn is cleared to 00h. compare register 1n (cmp1n) is not used in interval timer mode. since a match of 8-bit timer counter hn and the cmp1n register is not detected even if the cmp1n register is set, timer output is not affected. by setting bit 0 (toenn) of timer h mode register n (tmh mdn) to 1, a square wave of any frequency (duty = 50%) is output from tohn. (1) usage generates the inttmhn signal repeatedly at the same interval. <1> set each register. figure 8-8. register setting during inte rval timer/square-wave output operation (i) setting timer h mode register n (tmhmdn) 0 0/1 0/1 0/1 0 0 0/1 0/1 tmmdn0 tolevn toenn cksn1 cksn2 tmhen tmhmdn cksn0 tmmdn1 timer output setting timer output level inversion setting interval timer mode setting count clock (f cnt ) selection count operation stopped (ii) cmp0n register setting ? chapter 8 8-bit timers h0 and h1 user?s manual u15836ej5v0ud 170 (2) timing chart the timing of the interval timer/square- wave output operation is shown below. figure 8-9. timing of interval time r/square-wave output operation (1/2) (a) basic operation 00h count clock count start 8-bit timer counter hn cmp0n tmhen inttmhn tohn 01h n clear interval time clear n 00h 01h n 00h 01h 00h <2> level inversion, match interrupt occurrence, 8-bit timer counter hn clear <2> level inversion, match interrupt occurrence, 8-bit timer counter hn clear <3> <1> <1> the count operation is enabled by setting the tmhen bi t to 1. the count clock starts counting no more than 1 clock after the operation is enabled. <2> when the values of 8-bit timer counter hn and the cmp0n register match, the value of 8-bit timer counter hn is cleared, the tohn output level is in verted, and the inttmhn signal is output. <3> the inttmhn signal and tohn output become inactive by setting the tmhen bit to 0 during timer hn operation. if these are inactive from the first, the level is retained. remark n = 0, 1 n = 01h to feh chapter 8 8-bit timers h0 and h1 user?s manual u15836ej5v0ud 171 figure 8-9. timing of interval time r/square-wave output operation (2/2) (b) operation when cmp0n = ffh 00h count clock count start 8-bit timer counter hn cmp0n tmhen inttmhn tohn 01h feh clear clear ffh 00h feh ffh 00h ffh interval time (c) operation when cmp0n = 00h count clock count start 8-bit timer counter hn cmp0n tmhen inttmhn tohn 00h 00h interval time remark n = 0, 1 chapter 8 8-bit timers h0 and h1 user?s manual u15836ej5v0ud 172 8.4.2 operation as pwm output mode in pwm output mode, a pulse with an arbi trary duty and arbitrary cycle can be output. 8-bit timer compare register 0n (cmp0n ) controls the cycle of timer output (t ohn). rewriting the cmp0n register during timer operation is prohibited. 8-bit timer compare register 1n (cmp1n) controls the dut y of timer output (tohn). re writing the cmp1n register during timer operation is possible. the operation in pwm output mode is as follows. tohn output becomes active and 8-bit timer counter hn is cleared to 0 when 8-bit timer counter hn and the cmp0n register match after the timer count is started. tohn output becomes inactive when 8-bit timer counter hn and the cmp1n register match. (1) usage in pwm output mode, a pulse for which an arbitr ary duty and arbitrary cycle can be set is output. <1> set each register. figure 8-10. register setting in pwm output mode (i) setting timer h mode register n (tmhmdn) 0 0/1 0/1 0/1 1 0 0/1 1 tmmdn0 tolevn toenn cksn1 cksn2 tmhen tmhmdn cksn0 tmmdn1 timer output enabled timer output level inversion setting pwm output mode selection count clock (f cnt ) selection count operation stopped (ii) setting cmp0n register ? ? chapter 8 8-bit timers h0 and h1 user?s manual u15836ej5v0ud 173 <4> when 8-bit timer counter hn and the cmp1n regist er match, tohn output bec omes inactive and the compare register to be compared with 8-bit timer coun ter hn is changed from the cmp1n register to the cmp0n register. at this time, 8-bit timer counter hn is not cleared and the inttmhn signal is not generated. <5> by performing procedures <3> and <4> repeatedl y, a pulse with an arbitrary duty can be obtained. <6> to stop the count operation, set tmhen = 0. if the setting value of the cmp0n register is n, the setting value of the cmp1n register is m, and the count clock frequency is f cnt , the pwm pulse output cycle and duty are as follows. pwm pulse output cycle = (n+1)/f cnt duty = active width : total widt h of pwm = (m + 1) : (n + 1) cautions 1. in pwm output mode , three operation clocks (signal sel ected using the cksn2 to cksn0 bits of the tmhmdn register) are required to transfer the cmp1n register value after rewriting the register. 2. be sure to set the cmp1n register when starting the timer count operation (tmhen = 1) after the timer count operation was stopped (tmhen = 0) (be sure to set again even if setting the same value to the cmp1n register). chapter 8 8-bit timers h0 and h1 user?s manual u15836ej5v0ud 174 (2) timing chart the operation timing in pwm output mode is shown below. caution make sure that the cmp1n register setting value (m) and cmp0 n register setting value (n) are within the following range. 00h chapter 8 8-bit timers h0 and h1 user?s manual u15836ej5v0ud 175 figure 8-11. operation timing in pwm output mode (2/4) (b) operation when cmp0n = ffh, cmp1n = 00h count clock 8-bit timer counter hn cmp0n tmhen inttmhn tohn (tolevn = 0) 00h 01h ffh 00h 01h 02h ffh 00h ffh 00h 01h 02h cmp1n ffh 00h (c) operation when cmp0n = ffh, cmp1n = feh count clock 8-bit timer counter hn cmp0n tmhen inttmhn tohn (tolevn = 0) 00h 01h feh ffh 00h 01h feh ffh 00h 01h feh ffh 00h cmp1n ffh feh remark n = 0, 1 chapter 8 8-bit timers h0 and h1 user?s manual u15836ej5v0ud 176 figure 8-11. operation timing in pwm output mode (3/4) (d) operation when cmp0n = 01h, cmp1n = 00h count clock 8-bit timer counter hn cmp0n tmhen inttmhn tohn (tolevn = 0) 01h 00h 01h 00h 01h 00h 00h 01h 00h 01h cmp1n 00h remark n = 0, 1 chapter 8 8-bit timers h0 and h1 user?s manual u15836ej5v0ud 177 figure 8-11. operation timing in pwm output mode (4/4) (e) operation by changi ng cmp1n (cmp1n = 01h user?s manual u15836ej5v0ud 178 chapter 9 watchdog timer 9.1 functions of watchdog timer the watchdog timer is used to detect an inadvertent program loop. if a program loop is detected, an internal reset signal is generated. when a reset occurs due to the watchdog timer, bit 4 (wdtrf) of the reset control flag register (resf) is set to 1. for details of resf, see chapter 16 reset function . table 9-1. loop detection time of watchdog timer loop detection time during ring-osc clock o peration during x1 input clock operation 2 11 /f r (4.27 ms) 2 13 /f xp (819.2 chapter 9 watchdog timer user?s manual u15836ej5v0ud 179 table 9-2. mask option setting an d watchdog timer operation mode mask option ring-osc cannot be stopped ring-osc can be stopped by software watchdog timer clock source fixed to f r note 1 . ? ? ? ? ? ? ? chapter 9 watchdog timer user?s manual u15836ej5v0ud 180 9.2 configuration of watchdog timer the watchdog timer includes the following hardware. table 9-3. configuration of watchdog timer item configuration control registers watchdog timer mode register (wdtm) watchdog timer enable register (wdte) figure 9-1. block diagram of watchdog timer f r /2 2 clock input controller output controller internal reset signal wdcs2 internal bus wdcs1 wdcs0 f xp /2 4 wdcs3 wdcs4 01 1 selector 16-bit counter or 2 13 /f xp to 2 20 /f xp 2 11 /f r to 2 18 /f r watchdog timer enable register (wdte) watchdog timer mode register (wdtm) 3 2 clear mask option (to set ? ring-osc cannot be stopped ? or ? ring-osc can be stopped by software ? ) chapter 9 watchdog timer user?s manual u15836ej5v0ud 181 9.3 registers controlling watchdog timer the watchdog timer is controlled by the following two registers. ? watchdog timer mode register (wdtm) ? watchdog timer enable register (wdte) (1) watchdog timer mode register (wdtm) this register sets the overflow time and operation clock of the watchdog timer. this register can be set by an 8-bit memory manipula tion instruction and can be read many times, but can be written only once after reset is released. reset input sets this register to 67h. figure 9-2. format of watchdog timer mode register (wdtm) 0 wdcs0 1 wdcs1 2 wdcs2 3 wdcs3 4 wdcs4 5 1 6 1 7 0 symbol wdtm address: ff98h after reset: 67h r/w wdcs4 note 1 wdcs3 note 1 operation clock selection 0 0 ring-osc clock (f r ) 0 1 x1 input clock (f xp ) 1 watchdog timer operation stopped overflow time setting wdcs2 note 2 wdcs1 note 2 wdcs0 note 2 during ring-osc clock operation during x1 input clock operation 0 0 0 2 11 /f r (4.27 ms) 2 13 /f xp (819.2 s) 0 0 1 2 12 /f r (8.53 ms) 2 14 /f xp (1.64 ms) 0 1 0 2 13 /f r (17.07 ms) 2 15 /f xp (3.28 ms) 0 1 1 2 14 /f r (34.13 ms) 2 16 /f xp (6.55 ms) 1 0 0 2 15 /f r (68.27 ms) 2 17 /f xp (13.11 ms) 1 0 1 2 16 /f r (136.53 ms) 2 18 /f xp (26.21 ms) 1 1 0 2 17 /f r (273.07 ms) 2 19 /f xp (52.43 ms) 1 1 1 2 18 /f r (546.13 ms) 2 20 /f xp (104.86 ms) notes 1. if ?ring-osc cannot be stopped? is specified by a mask option, this cannot be set. the ring- osc clock will be selected no matter what value is written. 2. reset is released at the maximu m cycle (wdcs2, 1, 0 = 1, 1, 1). cautions 1. if data is written to wdtm, a wait cycle is generated. for details, see chapter 29 cautions for wait. 2. set bits 7, 6, and 5 to 0, 1, and 1, respectively (when ?ring-osc cannot be stopped? is selected by a mask option, other values are ignored). chapter 9 watchdog timer user?s manual u15836ej5v0ud 182 cautions 3. after reset is released, wdtm can be written only once by an 8-bit memory manipulation instruction. if writing is attempted a second time , an internal reset signal is generated. if the source clock to the watchdog timer is stopped, however, an internal reset signal is generated wh en the source clock to the watchdog timer resumes operation. 4. wdtm cannot be set by a 1-bi t memory manipulation instruction. 5. if ?ring-osc can be stopped by softw are? is selected by the mask option and the watchdog timer is stopped by setting wdcs 4 to 1, the watchdog timer does not resume operation even if wdcs4 is cleared to 0. in additi on, the internal reset signal is not generated. remarks 1. f r : ring-osc clock oscillation frequency 2. f xp : x1 input clock oscillation frequency 3. : don?t care 4. figures in parentheses apply to operation at f r = 480 khz (max.) (for standard products and (a) grade products), f xp = 10 mhz (2) watchdog timer enable register (wdte) writing ach to wdte clears the watchdog timer counter and starts counting again. this register can be set by an 8-bit memory manipulation instruction. reset input sets this register to 9ah. figure 9-3. format of watchdog timer enable register (wdte) 0 1 2 3 4 5 6 7 symbol wdte address: ff99h after reset: 9ah r/w cautions 1. if a value other than ach is written to wdte, an internal reset si gnal is genera ted. if the source clock to the watchdog timer is st opped, however, an internal reset signal is generated when the source clock to the watchdog timer resumes operation. 2. if a 1-bit memory manipulation instruct ion is executed for wdte, an internal reset signal is generated. if the source clock to the watchdog timer is stopped, however, an internal reset signal is generated wh en the source clock to the watchdog timer resumes operation. 3. the value read from wd te is 9ah (this differs from the written value (ach)). chapter 9 watchdog timer user?s manual u15836ej5v0ud 183 the relationship between the watchdog timer operation and the internal reset signal generated by the watchdog timer is shown below. table 9-4. relationship between watchdog timer operation and internal reset signal ge nerated by watchdog timer ?ring-osc can be stopped by software? is selected by mask option watchdog timer stopped watchdog timer operation internal reset signal generation cause ?ring-osc cannot be stopped? is selected by mask option (watchdog timer is always operating) watchdog timer is operating wdcs4 is set to 1 source clock to watchdog timer is stopped watchdog timer overflows internal reset signal is generated. internal reset signal is generated. ? ? write to wdtm for the second time internal reset signal is generated. internal reset signal is generated. internal reset signal is not generated and the watchdog timer does not resume operation. internal reset signal is generated when the source clock to the watchdog timer resumes operation. write other than ?ach? to wdte access wdte by 1-bit memory manipulation instruction internal reset signal is generated. internal reset signal is generated. internal reset signal is not generated. internal reset signal is generated when the source clock to the watchdog timer resumes operation. chapter 9 watchdog timer user?s manual u15836ej5v0ud 184 9.4 operation of watchdog timer 9.4.1 watchdog timer operation when ?ring-osc can not be stopped? is selected by mask option the operation clock of watchdog timer is fixed to ring-osc. after reset is released, operation is started at the maximum cycle (bits 2, 1, and 0 (wdcs2, w dcs1, wdcs0) of the watchdog timer mode register (wdtm) = 1, 1, 1) . the watchdog timer operation cannot be stopped. the following shows the watchdog timer operation after reset release. 1. the status after reset release is as follows. ? ? ? ? chapter 9 watchdog timer user?s manual u15836ej5v0ud 185 9.4.2 watchdog timer operation when ?ring-osc can be stopped by software? is selected by mask option the operation clock of the watchdog timer can be selected as either the ring-osc clock or the x1 input clock. after reset is released, operation is started at the maximum cycle (bits 2, 1, and 0 (wdcs2, w dcs1, wdcs0) of the watchdog timer mode register (wdtm) = 1, 1, 1) of the ring-osc clock. the following shows the watchdog timer operation after reset release. 1. the status after reset release is as follows. ? ? ? ? ? ? ? ? chapter 9 watchdog timer user?s manual u15836ej5v0ud 186 9.4.3 watchdog timer operation in stop mode (when ?ring-osc can be stopped by software? is selected by mask option) the watchdog timer stops counting during stop instruction execution regardless of whether the x1 input clock or ring-osc clock is being used. (1) when the cpu clock and the watchdog time r operation clock are the x1 input clock (f xp ) when the stop instruction is executed when stop instruction is executed, o peration of the watchdog timer is stopp ed. after stop mode is released, counting stops for the oscillation stabiliz ation time set by the oscillation stab ilization time select register (osts) and then counting is started again using the operation clock before the operation was stopped. at this time, the counter is not cleared to 0 but holds its value. figure 9-4. operation in stop mode (cpu cl ock and wdt operation clock: x1 input clock) watchdog timer operating operation stopped operating f r f xp cpu operation normal operation stop oscillation stabilization time normal operation oscillation stopped oscillation stabilization time (set by osts register) (2) when the cpu clock is the x1 input clock (f xp ) and the watchdog timer operati on clock is the ring-osc clock (f r ) when the stop instruction is executed when the stop instruction is execut ed, operation of the watchdog timer is stopped. after stop mode is released, counting is started again usi ng the operation clock before the operati on was stopped. at this time, the counter is not cleared to 0 but holds its value. figure 9-5. operation in stop mode (cpu clock: x1 input clock, wdt operation clock: ring-osc clock) watchdog timer operating f r f xp cpu operation normal operation stop oscillation stabilization time normal operation oscillation stopped oscillation stabilization time (set by osts register) operating operation stopped chapter 9 watchdog timer user?s manual u15836ej5v0ud 187 (3) when the cpu clock is the ring-osc clock (f r ) and the watchdog timer operati on clock is the x1 input clock (f xp ) when the stop inst ruction is executed when the stop instruction is execut ed, operation of the watchdog timer is stopped. after stop mode is released, counting is stopped until the timing of <1> or <2>, whichever is earlier , and then counting is started using the operation clock before the operation was stopped. at this time, the counter is not cleared to 0 but holds its value. <1> the oscillation stabilization time set by the oscillat ion stabilization time select register (osts) elapses. <2> the cpu clock is switched to the x1 input clock (f xp ). figure 9-6. operation in stop mode (cpu clock: ring-osc clock, wdt op eration clock: x1 input clock) <1> timing when counting is started afte r the oscillation stabilization time set by the oscillation stabilization time select register (osts) has elapsed watchdog timer operating operation stopped operating f r f xp cpu operation 17 clocks normal operation (ring-osc clock) clock supply stopped normal operation (ring-osc clock) oscillation stopped stop oscillation stabilization time (set by osts register) <2> timing when counting is started after the cp u clock is switched to the x1 input clock (f xp ) operating operation stopped operating f r f xp f r chapter 9 watchdog timer user?s manual u15836ej5v0ud 188 (4) when cpu clock and watchdog timer ope ration clock are the ring-osc clocks (f r ) during stop instruction execution when the stop instruction is execut ed, operation of the watchdog timer is stopped. after stop mode is released, counting is started again usi ng the operation clock before the operati on was stopped. at this time, the counter is not cleared to 0 but holds its value. figure 9-7. operation in stop mode (cpu cl ock and wdt operation clock: ring-osc clock) watchdog timer operating f r f xp cpu operation 17 clocks normal operation (ring-osc clock) clock supply stopped normal operation (ring-osc clock) oscillation stopped stop oscillation stabilization time (set by osts register) operating operation stopped 9.4.4 watchdog timer operation in halt mode (when ?ring-osc can be stoppe d by software? is selected by mask option) the watchdog timer stops counting during halt instruction execution regardle ss of whether the cpu clock is the x1 input clock (f xp ) or ring-osc clock (f r ), or whether the operation clock of t he watchdog timer is the x1 input clock (f xp ) or ring-osc clock (f r ). after halt mode is released, counting is started again using the operation clock before the operation was stopped. at this time, the c ounter is not cleared to 0 but holds its value. figure 9-8. operation in halt mode watchdog timer operating f r f xp cpu operation normal operation operating halt operation stopped normal operation user?s manual u15836ej5v0ud 189 chapter 10 a/d converter 10.1 function of a/d converter the a/d converter converts an analog input signal into a digital value, and consis ts of up to four channels (ani0 to ani3) with a resolution of 10 bits. the a/d converter has the following two functions. (1) 10-bit resolution a/d conversion 10-bit resolution a/d conversion is carried out repeatedly for one channel selected from analog inputs ani0 to ani3. each time an a/d conversion operation en ds, an interrupt request (intad) is generated. (2) power-fail de tection function this function is to detect a voltage drop in a battery. the values of the a/d conver sion result (adcr register value) and power-fail comparison threshold register (pft) are compared. intad is generated only when a comparative condition has been matched. figure 10-1. block diag ram of a/d converter av ref av ss intad adcs bit 2 ads1 ads0 adcs fr2 fr1 adce fr0 sample & hold circuit av ss voltage comparator controller a/d conversion result register (adcr) power-fail comparison threshold register (pft) analog input channel specification register (ads) a/d converter mode register (adm) pfen pfcm power-fail comparison mode register (pfm) internal bus comparator ani0/p20 ani1/p21 ani2/p22 ani3/p23 successive approximation register (sar) selector tap selector chapter 10 a/d converter user?s manual u15836ej5v0ud 190 10.2 configuration of a/d converter the a/d converter includes the following hardware. table 10-1. registers of a/ d converter used on software item configuration registers a/d conversion result register (adcr) a/d converter mode register (adm) analog input channel specification register (ads) power-fail comparison mode register (pfm) power-fail comparison threshold register (pft) (1) ani0 to ani3 pins these are the analog input pins of the 4- channel a/d converter. they input analog signals to be converted into digital signals. pins other than the one selected as the analog input pin by the analog input channel specification register (ads) can be used as input port pins. (2) sample & hold circuit the sample & hold circuit samples the input signal of the analog input pin selected by the selector when a/d conversion is started, and holds the sampled anal og input voltage value during a/d conversion. (3) series resistor string the series resistor stri ng is connected between av ref and av ss , and generates a voltage to be compared with the analog input signal. figure 10-2. circuit configuration of series resistor string av ref av ss p-ch series resistor string adcs (4) voltage comparator the voltage comparator compar es the sampled analog input voltage and t he output voltage of the series resistor string. (5) successive approximation register (sar) this register compares the sampled analog voltage and the voltage of the series resistor string, and converts the result, starting from the most significant bit (msb). when the voltage value is converted into a digital valu e down to the least significant bit (lsb) (end of a/d conversion), the contents of the sar register are transfe rred to the a/d conversion result register (adcr). chapter 10 a/d converter user?s manual u15836ej5v0ud 191 (6) a/d conversion result register (adcr) the result of a/d conversion is loa ded from the successive approximation register (sar) to this register each time a/d conversion is completed, and the adcr register hol ds the result of a/d conversion in its higher 10 bits (the lower 6 bits are fixed to 0). (7) controller when a/d conversion has been completed or when the powe r-fail detection function is used, this controller compares the result of a/d conversi on (value of the adcr register) and t he value of the power-fail comparison threshold register (pft). it generates the interrupt intad onl y if a specified comparison condition is satisfied as a result. (8) av ref pin this pin inputs an analog power/reference voltage to the a/ d converter. always use this pin at the same potential as that of the v dd pin even when the a/d converter is not used. the signal input to ani0 to ani3 is converted into a digital signal, based on the voltage applied across av ref and av ss . (9) av ss pin this is the ground potential pin of the a/d converter. al ways use this pin at the same potential as that of the v ss pin even when the a/d converter is not used. (10) a/d converter mode register (adm) this register is used to set the conversion time of the analog input signal to be conver ted, and to start or stop the conversion operation. (11) analog input channel sp ecification register (ads) this register is used to specify the port that inputs the analog voltage to be converted into a digital signal. (12) power-fail comparis on mode register (pfm) this register is used to set the power-fail monitor mode. (13) power-fail comparison threshold register (pft) this register is used to set the threshold value that is to be compared with the value of the a/d conversion result register (adcr). chapter 10 a/d converter user?s manual u15836ej5v0ud 192 10.3 registers used in a/d converter the a/d converter uses the following five registers. ? ? ? ? ? ? ? ? chapter 10 a/d converter user?s manual u15836ej5v0ud 193 notes 2. a booster circuit is incorporated to realize low-vo ltage operation. the operation of the circuit that generates the reference voltage for boosting is controlled by adce, and it takes 14 s from operation start to operation stabilization. theref ore, when adcs is set to 1 after 14 s or more has elapsed from the time adce is set to 1, the conversion result at that time has priority over the first conversion result. table 10-2. settings of adcs and adce adcs adce a/d co nversion operation 0 0 stop status (dc power consumption path does not exist) 0 1 conversion waiting mode (only reference voltage generator consumes power) 1 0 conversion mode (reference voltage generator operation stopped note ) 1 1 conversion mode (reference voltage generator operates) note data of first conversion cannot be used. figure 10-4. timing chart when boost reference voltage generator is used adce boost reference voltage adcs conversion operation conversion operation conversion stopped conversion waiting boost reference voltage generator: operating note note the time from the rising of the adce bit to the rising of the adcs bit must be 14 s or longer to stabilize the reference voltage. cautions 1. a/d conversion must be stopped before re writing bits fr0 to fr2 to values other than the identical data. 2. for the sampling time of th e a/d converter and the a/d con version start delay time, see (11) in 10.6 cautions for a/d converter. 3. if data is written to adm, a wait cycle is generated. for details, see chapter 29 cautions for wait. remark f x : x1 input clock oscillation frequency chapter 10 a/d converter user?s manual u15836ej5v0ud 194 (2) analog input channel specification register (ads) this register specifies the analog volt age input port to be a/d converted. ads can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 10-5. format of analog input channel specification register (ads) ads0 ads1 0 0 0 0 0 0 analog input channel specification ani0 ani1 ani2 ani3 ads0 0 1 0 1 ads1 0 0 1 1 0 1 2 3 4 5 6 7 ads address: ff29h after reset: 00h r/w symbol cautions 1. be sure to clea r bits 2 to 7 of ads to 0. 2. if data is written to ads , a wait cycle is generated. for details, see chapter 29 cautions for wait. (3) a/d conversion result register (adcr) this register is a 16-bit register that stores the a/d conversion result. the lower six bits are fixed to 0. each time a/d conversion ends, the conversion resu lt is loaded from the successive appr oximation register, and is stored in adcr in order starting from the most significant bit (msb) . ff09h indicates the higher 8 bits of the conversion result, and ff08h indicates the lower 2 bits of the conversion result. adcr can be read by a 16-bit memory manipulation instruction. reset input makes adcr undefined. figure 10-6. format of a/d con version result register (adcr) symbol address: ff08h, ff09h after reset: undefined r ff09h ff08h 0 0 0 0 0 0 adcr cautions 1. when writing to the a/d converter mode register (adm) and analog input channel specification register (ads), the contents of adcr may b ecome undefined. read the conversion result following con version completion before writing to adm and ads. using timing other than the above may cause an incorrect conversion result to be read. 2. if data is read from adcr, a wait cycl e is generated. for details, see chapter 29 cautions for wait. chapter 10 a/d converter user?s manual u15836ej5v0ud 195 (4) power-fail comparison mode register (pfm) the power-fail comparison mode regist er (pfm) is used to compare the a/ d conversion result (value of the adcr register) and the value of the power-fail comparison threshold value register (pft). pfm can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 10-7. format of power-fail comparison mode register (pfm) 0 0 0 0 0 0 pfcm pfen power-fail comparison enable stops power-fail comparison (used as a normal a/d converter) enables power-fail comparison (used for power-fail detection) pfen 0 1 power-fail comparison mode selection interrupt request signal (intad) generation no intad generation intad generation no intad generation higher 8 bits of adcr chapter 10 a/d converter user?s manual u15836ej5v0ud 196 10.4 a/d converter operations 10.4.1 basic operations of a/d converter <1> select one channel for a/d conversion using the analog input channel specification register (ads). <2> set adce to 1 and wait for 14 ? ? ? ? chapter 10 a/d converter user?s manual u15836ej5v0ud 197 figure 10-9. basic operation of a/d converter conversion time sampling time sampling a/d conversion undefined conversion result a/d converter operation sar adcr intad conversion result a/d conversion operations are performed continuously until bit 7 (adcs) of the a/d converter mode register (adm) is reset (0) by software. if any of adm, the analog input channel specification regi ster (ads), power-fail compar ison mode register (pfm), or power-fail comparison threshold register (pft) is wr itten during an a/d conversion operation, the conversion operation is initialized, and if the adcs bit is se t (1), conversion starts again from the beginning. reset input makes the a/d conversion re sult register (adcr) undefined. chapter 10 a/d converter user?s manual u15836ej5v0ud 198 10.4.2 input voltage and conversion results the relationship between the analog input voltage input to the analog input pins (ani0 to ani3) and the theoretical a/d conversion result (stored in the a/d conversion result register (adcr)) is shown by the following expression. sar = int ( ? chapter 10 a/d converter user?s manual u15836ej5v0ud 199 10.4.3 a/d converter operation mode the operation mode of the a/d c onverter is the select mode. one analog i nput channel is selected from ani0 to ani3 by the analog input channel specification register (ads) and a/d co nversion is executed. in addition, the following two functions can be selected by setting bit 7 (pfen) of the power-fail comparison mode register (pfm). ? ? chapter 10 a/d converter user?s manual u15836ej5v0ud 200 (2) power-fail detection f unction (when pfen = 1) by setting bit 7 (adcs) of the a/d converter mode regist er (adm) to 1 and bit 7 (pfen) of the power-fail comparison mode register (pfm) to 1, the a/d conversion operation of the vo ltage applied to the analog input pin specified by the analog input channel spec ification register (ads) is started. when the a/d conversion has been completed, the result of the a/d conversion is st ored in the a/d conversion result register (adcr), the values are compared with power-fail comparison threshold register (pft), and an interrupt request signal (intad) is generated under the condition specified by bit 6 (pfcm) of pfm. <1> when pfen = 1 and pfcm = 0 the higher 8 bits of adcr and pft values are co mpared when a/d conversion ends and intad is only generated when the higher 8 bits of adcr chapter 10 a/d converter user?s manual u15836ej5v0ud 201 the setting methods are described below. ? ? chapter 10 a/d converter user?s manual u15836ej5v0ud 202 10.5 how to read a/d converter characteristics table here, special terms unique to the a/d converter are explained. (1) resolution this is the minimum analog input vo ltage that can be identif ied. that is, the perce ntage of the analog input voltage per bit of digital output is called 1lsb (least si gnificant bit). the percentage of 1lsb with respect to the full scale is expressed by %fsr (full scale range). 1lsb is as follows when the resolution is 10 bits. 1lsb = 1/2 10 = 1/1024 = 0.098%fsr accuracy has no relation to resolution, but is determined by overall error. (2) overall error this shows the maximum error value between the actual measured value and the theoretical value. zero-scale error, full-scale error, integral linearity error, and differential linearity errors that are combinations of these express the overall error. note that the quantization error is not included in the overall erro r in the characteristics table. (3) quantization error when analog values are converted to digital values, a chapter 10 a/d converter user?s manual u15836ej5v0ud 203 (4) zero-scale error this shows the difference between the actual measuremen t value of the analog input vo ltage and the theoretical value (1/2lsb) when the digital output changes from 0......000 to 0......001. if the actual measurement value is greater than the theore tical value, it shows the difference between the actual measurement value of the analog in put voltage and the theoretical val ue (3/2lsb) when the digital output changes from 0??001 to 0??010. (5) full-scale error this shows the difference between the actual measuremen t value of the analog input vo ltage and the theoretical value (full-scale ? chapter 10 a/d converter user?s manual u15836ej5v0ud 204 (8) conversion time this expresses the time since sampling has b een started until digita l output is obtained. the sampling time is included in the conv ersion time in the characteristics table. (9) sampling time this is the time the analog switch is turned on for the anal og voltage to be sampled by the sample & hold circuit. sampling time conversion time 10.6 cautions for a/d converter (1) operating current in standby mode the a/d converter stops operating in the standby mode. at this time, th e operating current can be reduced by clearing bit 7 (adcs) of the a/d conver ter mode register (adm) to 0 (see figure 10-2 ). (2) input range of ani0 to ani3 observe the rated range of the ani0 to ani3 input voltage. if a voltage of av ref or higher and av ss or lower (even in the range of absolute maximum ratings) is input to an analog input channel, the converted value of that channel becomes undefined. in addition, the converted values of the other channels may also be affected. (3) conflicting operations <1> conflict between a/d conversion result register (adcr) write and adcr read by instruction upon the end of conversion adcr read has priority. after the read operation, the new conversion result is written to adcr. <2> conflict between adcr write and a/d converter mo de register (adm) write or analog input channel specification register (ads) wr ite upon the end of conversion adm or ads write has priority. adcr write is not pe rformed, nor is the conversion end interrupt signal (intad) generated. chapter 10 a/d converter user?s manual u15836ej5v0ud 205 (4) noise countermeasures to maintain the 10-bit resolution, attention must be paid to noise input to the av ref and ani0 to ani3 pins. because the effect increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be connected externally, as shown in figure 10-19, to reduce noise. figure 10-19. analog input pin connection reference voltage input c = 100 to 1,000 pf if there is a possibility that noise equal to or higher than av ref or equal to or lower than av ss may enter, clamp with a diode with a small v f value (0.3 v or lower). av ref av ss v ss ani0 to ani3 (5) ani0/p20 to ani3/p23 <1> the analog input pins (ani0 to ani3) are also used as input port pins (p20 to p23). when a/d conversion is performed with any of ani0 to ani3 selected, do not access port 2 while conversion is in progress; otherwise th e conversion resolution may be degraded. <2> if a digital pulse is applied to the pins adjacent to the pins currently being used for a/d conversion, the expected value of the a/d conversion may not be obtain ed due to coupling noise. therefore, do not apply a pulse to the pins adjacent to the pin undergoing a/d conversion. (6) input impedance of ani0 to ani3 pins in this a/d converter, the internal sampling capacitor is charged and sampling is performed for approx. one sixth of the conversion time. since only the leakage current flows other than during sa mpling and the current for charging the capacitor also flows during sampling, the input impedance fluctuates and has no meaning. to perform sufficient sampling, howeve r, it is recommended to make the output impedance of the analog input source 10 k ? or lower, or attach a capacitor of around 100 pf to the ani0 to ani3 pins (see figure 10-19 ). (7) av ref pin input impedance a series resistor string of several tens of k ? is connected between the av ref and av ss pins. therefore, if the output impedance of t he reference voltage source is high, this will result in a series connection to the series resistor string between the av ref and av ss pins, resulting in a large reference voltage error. chapter 10 a/d converter user?s manual u15836ej5v0ud 206 (8) interrupt request flag (adif) the interrupt request flag (adif) is not cleared even if th e analog input channel specification register (ads) is changed. therefore, if an analog input pin is changed during a/d conversion, the a/d conversion result and adif for the pre-change analog input may be set just before the ads rewrit e. caution is therefore re quired since, at this time, when adif is read immediately after the ads rewrite, ad if is set despite the fact a/d conversion for the post- change analog input has not finished. when a/d conversion is stopped and then resumed, clear ad if before the a/d conversion operation is resumed. figure 10-20. timing of a/d conver sion end interrupt request generation ads rewrite (start of anin conversion) a/d conversion adcr intad anin anin anim anim anin anin anim anim ads rewrite (start of anim conversion) adif is set but anim conversion has not finished. remarks 1. n = 0 to 3 2. m = 0 to 3 (9) conversion results just after a/d conversion start the first a/d conversion value immediately after a/d conv ersion starts may not fall wit hin the rating range if the adcs bit is set to 1 within 14 chapter 10 a/d converter user?s manual u15836ej5v0ud 207 (11) a/d converter sampling time a nd a/d conversion start delay time the a/d converter sampling time differs depending on the se t value of the a/d converter mode register (adm). a delay time exists until actual sampling is star ted after a/d converter operation is enabled. when using a set in which the a/d conversion time must be strictly observed, care is required regarding the contents shown in figure 10-21 and table 10-3. figure 10-21. timing of a/d converter sampling and a/d conversion start delay adcs wait period conversion time conversion time a/d conversion start delay time sampling time sampling timing intad adcs ? ? ? chapter 10 a/d converter user?s manual u15836ej5v0ud 208 (12) internal equivalent circuit the equivalent circuit of the analog input block is shown below. figure 10-22. internal equi valent circuit of anin pin anin c1 c2 c3 r1 r2 table 10-4. resistance and capacitance valu es of equivalent circui t (reference values) av ref r1 r2 c1 c2 c3 2.7 v 12 k ? ? ? ? user?s manual u15836ej5v0ud 209 chapter 11 serial interface uart0 ( ? ? ? ? ? ? chapter 11 serial interface uart0 ( chapter 11 serial interface uart0 ( chapter 11 serial interface uart0 ( chapter 11 serial interface uart0 ( ? ? ? ? ? chapter 11 serial interface uart0 ( chapter 11 serial interface uart0 ( chapter 11 serial interface uart0 ( pd780102, 780103, 78f0103 only) user?s manual u15836ej5v0ud 216 (3) baud rate generator cont rol register 0 (brgc0) this register selects the base clock of serial interf ace uart0 and the division value of the 5-bit counter. brgc0 can be set by an 8-bit memory manipulation instruction. reset input sets this register to 1fh. figure 11-4. format of baud rate ge nerator control register 0 (brgc0) address: ff71h after reset: 1fh r/w symbol 7 6 5 4 3 2 1 0 brgc0 tps01 tps00 0 mdl04 mdl03 mdl02 mdl01 mdl00 tps01 tps00 base clock (f xclk0 ) selection note 1 0 0 tm50 output note 2 0 1 f x /2 (5 mhz) 1 0 f x /2 3 (1.25 mhz) 1 1 f x /2 5 (312.5 khz) mdl04 mdl03 mdl02 mdl01 mdl00 k selection of 5-bit counter output clock 0 0 setting prohibited 0 1 0 0 0 8 f xclk0 /8 0 1 0 0 1 9 f xclk0 /9 0 1 0 1 0 10 f xclk0 /10 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 1 0 1 0 26 f xclk0 /26 1 1 0 1 1 27 f xclk0 /27 1 1 1 0 0 28 f xclk0 /28 1 1 1 0 1 29 f xclk0 /29 1 1 1 1 0 30 f xclk0 /30 1 1 1 1 1 31 f xclk0 /31 notes 1. be sure to set the base clock so that the following condition is satisfied. ? v dd = 4.0 to 5.5 v: base clock 10 mhz ? v dd = 3.3 to 4.0 v: base clock 8.38 mhz ? v dd = 2.7 to 3.3 v: base clock 5 mhz ? v dd = 2.5 to 2.7 v: base clock 2.5 mhz 2. note the following points when sele cting the tm50 output as the base clock. ? pwm mode (tmc506 = 1) start the operation of 8-bit timer/event counter 50 first and then set the base clock to make the duty = 50%. ? mode in which the base clock is cleared and started upon a match of tm50 and cr50 (tmc506 = 0) start the operation of 8-bit timer/event counte r 50 first and then enable the timer f/f inversion operation (tmc501 = 1). it is not necessary to enable the to50 pin as a timer output pin in any mode. chapter 11 serial interface uart0 ( pd780102, 780103, 78f0103 only) user?s manual u15836ej5v0ud 217 cautions 1. when the ring-osc clo ck is selected as the clock to be supplied to the cpu, the clock of the ring-osc oscillator is divided and supplied as the count clock. if the base clock is the ring- osc clock, the operation of serial interface uart0 is not guaranteed. 2. make sure that bit 6 (txe0) and bit 5 (rxe0) of the asim0 register = 0 when rewriting the mdl04 to mdl00 bits. 3. the baud rate value is the output clock of the 5-bit c ounter divided by 2. remarks 1. f xclk0 : frequency of base clock selected by the tps01 and tps00 bits 2. f x : x1 input clock oscillation frequency 3. k: value set by the mdl04 to md l00 bits (k = 8, 9, 10, ..., 31) 4. : don?t care 5. figures in parentheses apply to operation at f x = 10 mhz 6. tmc506: bit 6 of 8-bit timer mode control register 50 (tmc50) 7. tmc501: bit 1 of tmc50 (4) port mode register 1 (pm1) this register sets port 1 input/output in 1-bit units. when using the p10/txd0/sck10 pin for serial interface dat a output, clear pm10 to 0 and set the output latch of p10 to 1. when using the p11/rxd0/si10 pin for serial interface data in put, set pm11 to 1. the output latch of p11 at this time may be 0 or 1. pm1 can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to ffh. figure 11-5. format of port mode register 1 (pm1) address: ff21h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm1 pm17 pm16 pm15 pm14 pm13 pm12 pm11 pm10 pm1n p1n pin i/o mode selection (n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) chapter 11 serial interface uart0 ( ? ? chapter 11 serial interface uart0 ( ? ? ? ? ? chapter 11 serial interface uart0 ( ? ? ? ? chapter 11 serial interface uart0 ( ? ? ? ? chapter 11 serial interface uart0 ( chapter 11 serial interface uart0 ( chapter 11 serial interface uart0 ( chapter 11 serial interface uart0 ( ? ? ? chapter 11 serial interface uart0 ( ? ? ? ? chapter 11 serial interface uart0 ( ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? chapter 11 serial interface uart0 ( ? chapter 11 serial interface uart0 ( ? ? ? ? ? ? ? ? ? ? ? ? user?s manual u15836ej5v0ud 230 chapter 12 serial interface uart6 12.1 functions of serial interface uart6 serial interface uart6 has the following two modes. (1) operation stop mode this mode is used when serial communication is not executed and can enable a reduction in the power consumption. for details, see 12.4.1 operation stop mode . (2) asynchronous serial interface (uart) mode this mode supports the lin (local interconnect network) -bus. the functions of this mode are outlined below. for details, see 12.4.2 asynchronous seri al interface (uart) mode and 12.4.3 dedicated baud rate generator . ? ? ? ? ? ? ? ? ? chapter 12 serial interface uart6 user?s manual u15836ej5v0ud 231 remark lin stands for local interconnect network and is a low-speed (1 to 20 kbps) serial communication protocol intended to aid the cost reduction of an automotive network. lin communication is single-master communication, and up to 15 slaves can be connected to one master. the lin slaves are used to contro l the switches, actuator s, and sensors, and thes e are connected to the lin master via the lin network. normally, the lin master is connected to a network such as can (controller area network). in addition, the lin bus uses a single-wire method and is connected to the nodes via a transceiver that complies with iso9141. in the lin protocol, the master transmits a frame with baud rate information and the slave receives it and corrects the baud rate error. therefore, communication is possible when the baud rate error in the slave is chapter 12 serial interface uart6 user?s manual u15836ej5v0ud 232 figure 12-2. lin reception operation sleep bus 13 bits note 2 sf reception id reception data reception data reception data reception note 5 note 3 note 1 note 4 wakeup signal frame synchronous break field synchronous field ident field data field data field checksum field rx6 sbf reception reception interrupt (intsr6) edge detection (intp0) capture timer disable enable disable enable notes 1. the wakeup signal is detected at the edge of the pin, and enables uart6 and sets the sbf reception mode. 2. reception continues until the stop bit is detected. when an sbf wit h low-level data of 11 bits or more has been detected, it is assumed that sbf reception has been completed correctly, and an interrupt signal is output. if an sbf with low-level da ta of less than 11 bits has been detected, it is assumed that an sbf reception error has occurred. the interrupt signal is not output and the sbf reception mode is restored. 3. if sbf reception has been completed correctly, an interrupt signal is output. this sbf reception completion interrupt enables the capture timer. detection of errors ove6, pe6, and fe6 is suppressed, and error detection processing of ua rt communication and data transfer of the shift register and rxb6 is not performed. the shift register holds the reset value ffh. 4. calculate the baud rate error from the bit length of the synchronous field, disable uart6 after sf reception, and then re-set baud rate gen erator control register 6 (brgc6). 5. distinguish the checksum field by software. also perform processi ng by software to initialize uart6 after reception of the checksum field an d to set the sbf reception mode again. to perform a lin receive operation, use a conf iguration like the one shown in figure 12-3. the wakeup signal transmitted from the lin master is re ceived by detecting the edge of the external interrupt (intp0). the length of the synchronous field transmitted from the lin master can be measured using the external event capture operation of 16-bit ti mer/event counter 00, and the bau d rate error can be calculated. the input signal of the reception port input (rxd6) ca n be input to the external interrupt (intp0) and 16-bit timer/event counter 00 by port input switch control (isc0/isc1), without co nnecting rxd6 and intp0/ti000 externally. chapter 12 serial interface uart6 user?s manual u15836ej5v0ud 233 figure 12-3. port configurati on for lin reception operation rxd6 input intp0 input ti000 input p14/rxd6 p120/intp0 p00/ti000 port input switch control (isc0) chapter 12 serial interface uart6 user?s manual u15836ej5v0ud 234 12.2 configuration of serial interface uart6 serial interface uart6 includes the following hardware. table 12-1. configurati on of serial interface uart6 item configuration registers receive buffer register 6 (rxb6) receive shift register 6 (rxs6) transmit buffer register 6 (txb6) transmit shift register 6 (txs6) control registers asynchronous serial interface o peration mode register 6 (asim6) asynchronous serial interface recepti on error status register 6 (asis6) asynchronous serial interface transm ission status register 6 (asif6) clock selection register 6 (cksr6) baud rate generator control register 6 (brgc6) asynchronous serial interface control register 6 (asicl6) input switch control register (isc) port mode register 1 (pm1) port register 1 (p1) chapter 12 serial interface uart6 user?s manual u15836ej5v0ud 235 figure 12-4. block diagram of serial interface uart6 internal bus asynchronous serial interface control register 6 (asicl6) transmit buffer register 6 (txb6) transmit shift register 6 (txs6) t x d6/ p13 intst6 baud rate generator asynchronous serial interface control register 6 (asicl6) reception control receive shift register 6 (rxs6) receive buffer register 6 (rxb6) r x d6/ p14 ti000, intp0 note intsr6 baud rate generator filter intsre6 asynchronous serial interface reception error status register 6 (asis6) asynchronous serial interface operation mode register 6 (asim6) asynchronous serial interface transmission status register 6 (asif6) transmission control registers f x f x /2 f x /2 2 f x /2 3 f x /2 4 f x /2 5 f x /2 6 f x /2 7 f x /2 8 f x /2 9 f x /2 10 8-bit timer/ event counter 50 output 8 reception unit transmission unit clock selection register 6 (cksr6) baud rate generator control register 6 (brgc6) output latch (p13) pm13 8 selector note selectable with input switch control register (isc). chapter 12 serial interface uart6 user?s manual u15836ej5v0ud 236 (1) receive buffer register 6 (rxb6) this 8-bit register stores parallel data conv erted by receive shift register 6 (rxs6). each time 1 byte of data has been received, new receive data is transferred to this register from receive shift register 6 (rxs6). if the data length is set to 7 bits, data is transferred as follows. ? ? chapter 12 serial interface uart6 user?s manual u15836ej5v0ud 237 12.3 registers controlling serial interface uart6 serial interface uart6 is controlle d by the following nine registers. ? ? ? ? ? ? ? ? ? chapter 12 serial interface uart6 user?s manual u15836ej5v0ud 238 figure 12-5. format of asynchronous serial inte rface operation mode register 6 (asim6) (2/2) rxe6 enables/disables reception 0 disables reception (synchronous ly resets the reception circuit). 1 enables reception ps61 ps60 transmission oper ation reception operation 0 0 does not output parity bit. reception without parity 0 1 outputs 0 parity. reception as 0 parity note 1 0 outputs odd parity. judges as odd parity. 1 1 outputs even parity. judges as even parity. cl6 specifies character length of transmit/receive data 0 character length of data = 7 bits 1 character length of data = 8 bits sl6 specifies number of stop bits of transmit data 0 number of stop bits = 1 1 number of stop bits = 2 isrm6 enables/disables occurr ence of reception completion interrupt in case of error 0 ?intsre6? occurs in case of error (at this time, intsr6 does not occur). 1 ?intsr6? occurs in case of error (at this time, intsre6 does not occur). note if ?reception as 0 parity? is selected, the parity is not judged. therefore, bit 2 (pe6) of asynchronous serial interface reception error status register 6 (asis6) is not set and the error interrupt does not occur. cautions 1. at startup, set power6 to 1 and then set txe6 to 1. to stop the op eration, clear txe6 to 0 and then clear power6 to 0. 2. at startup, set power6 to 1 and then set r xe6 to 1. to stop the operation, clear rxe6 to 0 and then clear power6 to 0. 3. set power6 to 1 and then set rxe6 to 1 wh ile a high level is input to the rxd6 pin. if power6 is set to 1 and rxe6 is set to 1 wh ile a low level is input, reception is started. 4. clear the txe6 and rxe6 bits to 0 be fore rewriting the ps61, ps60, and cl6 bits. 5. fix the ps61 and ps60 bits to 0 when mounting the device on lin. 6. make sure that txe6 = 0 wh en rewriting the sl6 bit. recep tion is always performed with ?the number of stop bits = 1?, and therefore, is not affected by the set value of the sl6 bit. 7. make sure that rxe6 = 0 when rewriting the isrm6 bit. chapter 12 serial interface uart6 user?s manual u15836ej5v0ud 239 (2) asynchronous serial interface recepti on error status register 6 (asis6) this register indicates an error status on completion of reception by serial interface uart6. it includes three error flag bits (pe6, fe6, ove6). this register is read-only by an 8-bit memory manipulation instruction. reset input clears this re gister to 00h if bit 7 (power6) and bit 5 (rxe 6) of asim6 = 0. 00 h is read when this register is read. figure 12-6. format of asynchronous serial inte rface reception error status register 6 (asis6) address: ff53h after reset: 00h r symbol 7 6 5 4 3 2 1 0 asis6 0 0 0 0 0 pe6 fe6 ove6 pe6 status flag indicating parity error 0 if power6 = 0 and rxe6 = 0, or if asis6 register is read 1 if the parity of transmit data does not match the parity bit on completion of reception fe6 status flag indicating framing error 0 if power6 = 0 and rxe6 = 0, or if asis6 register is read 1 if the stop bit is not detected on completion of reception ove6 status flag indicating overrun error 0 if power6 = 0 and rxe6 = 0, or if asis6 register is read 1 if receive data is set to the rxb6 register and the next reception operation is completed before the data is read. cautions 1. the operation of the pe6 bit differs depending on the set values of the ps61 and ps60 bits of asynchronous serial interface operati on mode register 6 (asim6). 2. the first bit of the receive data is checked as the stop bit, regardless of the number of stop bits. 3. if an overrun error occurs, the next receive data is not wri tten to receive buffer register 6 (rxb6) but discarded. 4. if data is read from asis6, a wait c ycle is generated. for details, see chapter 29 cautions for wait. chapter 12 serial interface uart6 user?s manual u15836ej5v0ud 240 (3) asynchronous serial interface transm ission status register 6 (asif6) this register indicates the status of transmission by se rial interface uart6. it includes two status flag bits (txbf6 and txsf6). transmission can be continued without disruption even during an interrupt period, by writing the next data to the txb6 register after data has been transferred from the txb6 register to the txs6 register. this register is read-only by an 8-bit memory manipulation instruction. reset input clears this register to 00h if bi t 7 (power6) and bit 6 (txe6) of asim6 = 0. figure 12-7. format of asynchronous serial in terface transmission status register 6 (asif6) address: ff55h after reset: 00h r symbol 7 6 5 4 3 2 1 0 asif6 0 0 0 0 0 0 txbf6 txsf6 txbf6 transmit buffer data flag 0 if power6 = 0 or txe6 = 0, or if data is tr ansferred to transmit shift register 6 (txs6) 1 if data is written to transmit buffer register 6 (txb6) (if data exists in txb6) txsf6 transmit shift register data flag 0 if power6 = 0 or txe6 = 0, or if the next data is not transferred from transmit buffer register 6 (txb6) after completion of transfer 1 if data is transferred from transmit buffer regist er 6 (txb6) (if data transmi ssion is in progress) cautions 1. to transmit data continuously, write the first transmit da ta (first byte) to the txb6 register. be sure to check that the txbf6 fl ag is ?0?. if so, write the next transmit data (second byte) to the txb6 register. if data is written to th e txb6 register while the txbf6 flag is ?1?, the transmit data cannot be guaranteed. 2. to initialize the transmission unit upon comple tion of continuous transmission, be sure to check that the txsf6 flag is ?0? after genera tion of the transmission completion interrupt, and then execute initialization. if initializati on is executed while the txsf6 flag is ?1?, the transmit data cannot be guaranteed. chapter 12 serial interface uart6 user?s manual u15836ej5v0ud 241 (4) clock selection register 6 (cksr6) this register selects the base cl ock of serial interface uart6. cksr6 can be set by an 8-bit memory manipulation instruction. reset input clears this register to 00h. remark cksr6 can be refreshed (the same value is wri tten) by software during a communication operation (when bit 7 (power6) and bit 6 (txe6) of asim6 = 1 or bit 7 (power6) and bit 5 (rxe6) of asim6 = 1). figure 12-8. format of clock selection register 6 (cksr6) address: ff56h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 cksr6 0 0 0 0 tps63 tps62 tps61 tps60 tps63 tps62 tps61 tps60 base clock (f xclk6 ) selection note 1 0 0 0 0 f x (10 mhz) 0 0 0 1 f x /2 (5 mhz) 0 0 1 0 f x /2 2 (2.5 mhz) 0 0 1 1 f x /2 3 (1.25 mhz) 0 1 0 0 f x /2 4 (625 khz) 0 1 0 1 f x /2 5 (312.5 khz) 0 1 1 0 f x /2 6 (156.25 khz) 0 1 1 1 f x /2 7 (78.13 khz) 1 0 0 0 f x /2 8 (39.06 khz) 1 0 0 1 f x /2 9 (19.53 khz) 1 0 1 0 f x /2 10 (9.77 khz) 1 0 1 1 tm50 output note 2 other setting prohibited notes 1. be sure to set the base clock so that the following condition is satisfied. ? ? ? ? ? ? chapter 12 serial interface uart6 user?s manual u15836ej5v0ud 242 (5) baud rate generator cont rol register 6 (brgc6) this register sets the division value of t he 8-bit counter of serial interface uart6. brgc6 can be set by an 8-bit memory manipulation instruction. reset input sets this register to ffh. remark brgc6 can be refreshed (the same value is wr itten) by software during a communication operation (when bit 7 (power6) and bit 6 (txe6) of asim6 = 1 or bit 7 (power6) and bit 5 (rxe6) of asim6 = 1). figure 12-9. format of baud rate ge nerator control register 6 (brgc6) address: ff57h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 brgc6 mdl67 mdl66 mdl65 mdl64 mdl63 mdl62 mdl61 mdl60 mdl67 mdl66 mdl65 mdl64 mdl63 mdl62 mdl61 mdl60 k output clock selection of 8-bit counter 0 0 0 0 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? chapter 12 serial interface uart6 user?s manual u15836ej5v0ud 243 (6) asynchronous serial interface control register 6 (asicl6) this register controls the serial communicati on operations of serial interface uart6. asicl6 can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 16h. caution asicl6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (power6) and bit 6 (txe6) of asim6 = 1 or bit 7 (power6) and bit 5 (rxe6) of asim6 = 1). note, however, that comm unication is started by the refresh operation because bit 6 (sbrt6) of asicl6 is cleared to 0 when communication is completed (when an interrupt signal is generated). figure 12-10. format of asynchronous serial interface control register 6 (asicl6) address: ff58h after reset: 16h r/w note symbol <7> <6> 5 4 3 2 1 0 asicl6 sbrf6 sbrt6 0 1 0 1 dir6 txdlv6 sbrf6 sbf reception status flag 0 if power6 = 0 and rxe6 = 0 or if sbf reception has been completed correctly 1 sbf reception in progress sbrt6 sbf reception trigger 0 ? chapter 12 serial interface uart6 user?s manual u15836ej5v0ud 244 (7) input switch control register (isc) the input switch control register (isc) is used to receiv e a status signal transmitted from the master during lin (local interconnect network) reception. the input signal is switched by setting isc. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 12-11. format of input s witch control register (isc) address: ff4fh after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 isc 0 0 0 0 0 0 isc1 isc0 isc1 ti000 input source selection 0 ti000 (p00) 1 rxd6 (p14) isc0 intp0 input source selection 0 intp0 (p120) 1 rxd6 (p14) (8) port mode register 1 (pm1) this register sets port 1 input/output in 1-bit units. when using the p13/txd6 pin for serial interface data out put, clear pm13 to 0 and set the output latch of p13 to 1. when using the p14/rxd6 pin for serial interface data input, set pm14 to 1. the output latch of p14 at this time may be 0 or 1. pm1 can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to ffh. figure 12-12. format of port mode register 1 (pm1) address: ff21h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm1 pm17 pm16 pm15 pm14 pm13 pm12 pm11 pm10 pm1n p1n pin i/o mode selection (n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) chapter 12 serial interface uart6 user?s manual u15836ej5v0ud 245 12.4 operation of serial interface uart6 serial interface uart6 has the following two modes. ? ? chapter 12 serial interface uart6 user?s manual u15836ej5v0ud 246 12.4.2 asynchronous serial interface (uart) mode in this mode, data of 1 byte is transmitted/received following a start bit, and a full-duplex operation can be performed. a dedicated uart baud rate generator is incorporated, so that communication can be executed at a wide range of baud rates. (1) registers used ? ? ? ? ? ? ? ? ? chapter 12 serial interface uart6 user?s manual u15836ej5v0ud 247 (2) communication operation (a) format and waveform example of normal transmit/receive data figures 12-13 and 12-14 show the format and waveform example of the normal transmit/receive data. figure 12-13. format of normal uart transmit/receive data 1. lsb-first transmission/reception start bit parity bit d0 d1 d2 d3 d4 1 data frame character bits d5 d6 d7 stop bit 2. msb-first transmission/reception start bit parity bit d7 d6 d5 d4 d3 1 data frame character bits d2 d1 d0 stop bit one data frame consists of the following bits. ? ? ? ? chapter 12 serial interface uart6 user?s manual u15836ej5v0ud 248 figure 12-14. example of normal uart transmit/receive data waveform 1. data length: 8 bits, lsb first, parity: even parity, stop bit: 1 bit, communication data: 55h 1 data frame start d0 d1 d2 d3 d4 d5 d6 d7 parity stop 2. data length: 8 bits, msb first, parity: even parity, stop bit: 1 bit, communication data: 55h 1 data frame start d7 d6 d5 d4 d3 d2 d1 d0 parity stop 3. data length: 8 bits, msb first, parity: even parity, stop bit: 1 bit, communication data: 55h, t x d6 pin inverted output 1 data frame start d7 d6 d5 d4 d3 d2 d1 d0 parity stop 4. data length: 7 bits, lsb first, parity: o dd parity, stop bit: 2 bits, communication data: 36h 1 data frame start d0 d1 d2 d3 d4 d5 d6 parity stop stop 5. data length: 8 bits, lsb first, parity: none, stop bit: 1 bit, communication data: 87h 1 data frame start d0 d1 d2 d3 d4 d5 d6 d7 stop chapter 12 serial interface uart6 user?s manual u15836ej5v0ud 249 (b) parity types and operation the parity bit is used to detect a bit error in communica tion data. usually, the same type of parity bit is used on both the transmission and reception sides. with even parity and odd parity, a 1-bit (odd number) error can be detected. with zero parity and no parity, an error cannot be detected. caution fix the ps61 and ps60 bits to 0 wh en the device is inco rporated in lin. (i) even parity ? ? ? ? chapter 12 serial interface uart6 user?s manual u15836ej5v0ud 250 (c) normal transmission the t x d6 pin outputs a high level when bit 7 (power6) of asynchronous serial interface operation mode register 6 (asim6) is set to 1. if bit 6 (txe6) of asim6 is then set to 1, transmission is enabled. transmission can be started by writing transmit data to tr ansmit buffer register 6 (txb6). the start bit, parity bit, and stop bit are automatica lly appended to the data. when transmission is started, the data in txb6 is transferred to transmit sh ift register 6 (txs6). after that, the data is sequentially output from txs6 to the t x d6 pin. when transmission is completed, the parity bit and stop bit set by asim6 are added and a transmission co mpletion interrupt reques t (intst6) is generated. transmission is stopped until the data to be transmitted next is written to txb6. figure 12-15 shows the timing of the transmission comp letion interrupt request (intst6). this interrupt occurs as soon as the last stop bit has been output. figure 12-15. normal transmission comp letion interrupt request timing 1. stop bit length: 1 intst6 d0 start d1 d2 d6 d7 stop t x d6 (output) parity 2. stop bit length: 2 t x d6 (output) intst6 d0 start d1 d2 d6 d7 parity stop chapter 12 serial interface uart6 user?s manual u15836ej5v0ud 251 (d) continuous transmission the next transmit data can be written to transmit buffer re gister 6 (txb6) as soon as transmit shift register 6 (txs6) has started its shift operation. consequently, even while the intst6 interrupt is being serviced after transmission of one data frame, data can be continuously transmitted and an efficient communication rate can be realized. in addition, the txb6 register can be e fficiently written twice (2 bytes) without having to wait for the transmission time of one data frame, by readi ng bit 0 (txsf6) of asynchronous serial interface transmission status register 6 (asif6) when the transmission completion interrupt has occurred. to transmit data continuously, be sure to reference the asif6 register to check the transmission status and whether the txb6 register can be written, and then write the data. cautions 1. the txbf6 and txsf6 flags of the asif6 register change from ?10? to ?11?, and to ?01? during continuous transmission. to check the status, therefore, do not use a combination of the txbf6 a nd txsf6 flags for judgment. read only the txbf6 flag when executing continuous transmission. 2. when the device is incorp orated in a lin, the continuous transmission function cannot be used. make sure that a synchronous serial interface tran smission status register 6 (asif6) is 00h before writin g transmit data to transmit buffer register 6 (txb6). txbf6 writing to txb6 register 0 writing enabled 1 writing disabled caution to transmit data continuously, write the first transmit data (fi rst byte) to the txb6 register. be sure to check that the txbf6 fl ag is ?0?. if so, write the next transmit da ta (second byte) to the txb6 register. if data is written to the txb6 register while the txbf6 flag is ?1?, the transmit data cannot be guaranteed. the communication status can be checked using the txsf6 flag. txsf6 transmission status 0 transmission is completed. 1 transmission is in progress. cautions 1. to initialize the transmission unit upon completion of continuous transmission, be sure to check that the txsf6 flag is ?0? afte r generation of the transmission completion interrupt, and then execute initialization. if initialization is executed while the txsf6 flag is ?1?, the transmit data cannot be guaranteed. 2. during continuous transmission, an ove rrun error may occur, which means that the next transmission was completed before exe cution of intst6 interrupt servicing after transmission of one data frame. an ove rrun error can be detected by developing a program that can count the number of transmit data and by refere ncing the txsf6 flag. chapter 12 serial interface uart6 user?s manual u15836ej5v0ud 252 figure 12-16 shows an example of the continuous transmission processing flow. figure 12-16. example of contin uous transmission processing flow write txb6. set registers. write txb6. transfer executed necessary number of times? yes read asif6 txbf6 = 0? no no yes transmission completion interrupt occurs? read asif6 txsf6 = 0? no no no yes yes yes yes completion of transmission processing transfer executed necessary number of times? remark txb6: transmit buffer register 6 asif6: asynchronous serial interface transmission status register 6 txbf6: bit 1 of asif6 (transmit buffer data flag) txsf6: bit 0 of asif6 (trans mit shift register data flag) chapter 12 serial interface uart6 user?s manual u15836ej5v0ud 253 figure 12-17 shows the timing of starting continuous transmission, and figure 12-18 shows the timing of ending continuous transmission. figure 12-17. timing of starting continuous transmission t x d6 start intst6 data (1) data (1) data (2) data (3) data (2) data (1) data (3) ff ff parity stop data (2) parity stop txb6 txs6 txbf6 txsf6 start start note note when asif6 is read, there is a period in which t xbf6 and txsf6 = 1, 1. therefore, judge whether writing is enabled using only the txbf6 bit. remark t x d6: t x d6 pin (output) intst6: interrupt request signal txb6: transmit buffer register 6 txs6: transmit shift register 6 asif6: asynchronous serial interface transmission status register 6 txbf6: bit 1 of asif6 txsf6: bit 0 of asif6 chapter 12 serial interface uart6 user?s manual u15836ej5v0ud 254 figure 12-18. timing of ending continuous transmission t x d6 start intst6 data (n ? ? ? chapter 12 serial interface uart6 user?s manual u15836ej5v0ud 255 (e) normal reception reception is enabled and the r x d6 pin input is sampled when bit 7 (power6) of asynchronous serial interface operation mode register 6 (asim6) is set to 1 and then bit 5 (rxe6) of asim6 is set to 1. the 8-bit counter of the baud rate generator st arts counting when the falling edge of the r x d6 pin input is detected. when the set value of baud rate generator control register 6 (brgc6) has been counted, the r x d6 pin input is sampled again ( in figure 12-19). if the r x d6 pin is low level at this time, it is recognized as a start bit. when the start bit is detected, receptio n is started, and serial data is sequ entially stored in the receive shift register (rxs6) at the set baud rate. when the stop bi t has been received, the reception completion interrupt (intsr6) is generated and the data of rxs6 is written to receive buffer register 6 (rxb6). if an overrun error (ove6) occurs, however, the receiv e data is not written to rxb6. even if a parity error (pe6) occurs while reception is in progress, reception continues to the reception position of the stop bit, and an error interrupt (intsr6 /intsre6) is generated on completion of reception. figure 12-19. reception completi on interrupt request timing r x d6 (input) intsr6 start d0 d1 d2 d3 d4 d5 d6 d7 parity rxb6 stop cautions 1. be sure to read receive buffer register 6 (rxb6) e ven if a reception error occurs. otherwise, an overrun error wil l occur when the next data is received, and the reception error status will persist. 2. reception is always performed with the ? number of stop bits = 1?. the second stop bit is ignored. 3. be sure to read asynchro nous serial interface reception e rror status register 6 (asis6) before reading rxb6. chapter 12 serial interface uart6 user?s manual u15836ej5v0ud 256 (f) reception error three types of errors may occur during reception: a parity error, framing error, or ov errun error. if the error flag of asynchronous serial interface reception error st atus register 6 (asis6) is set as a result of data reception, a reception error interrupt r equest (intsr6/intsre6) is generated. which error has occurred during reception can be identifi ed by reading the contents of asis6 in the reception error interrupt servicing (intsr6/intsre6) (see figure 12-6 ). the contents of asis6 are reset to 0 when asis6 is read. table 12-3. cause of reception error reception error cause parity error the parity specified for transmission does not match the parity of the receive data. framing error stop bit is not detected. overrun error reception of the next data is comp leted before data is read from receive buffer register 6 (rxb6). the error interrupt can be separated into reception completion interrupt (intsr6) and error interrupt (intsre6) by clearing bit 0 (isrm6) of asynchronous se rial interface operation mode register 6 (asim6) to 0. figure 12-20. reception error interrupt 1. if isrm6 is cleared to 0 (reception completion in terrupt (intsr6) and erro r interrupt (intsre6) are separated) (a) no error during recepti on (b) error during reception intsr6 intsre6 intsr6 intsre6 2. if isrm6 is set to 1 (error interrupt is included in intsr6) (a) no error during recepti on (b) error during reception intsre6 intsr6 intsre6 intsr6 chapter 12 serial interface uart6 user?s manual u15836ej5v0ud 257 (g) noise filter of receive data the rxd6 signal is sampled with the base clock output by the prescaler block. if two sampled values are the same, the output of t he match detector changes, and the data is sampled as input data. because the circuit is configured as shown in figure 12- 21, the internal processing of the reception operation is delayed by two clocks from the external signal status. figure 12-21. noise filter circuit internal signal b internal signal a match detector in base clock r x d6/p14 q in ld_en q (h) sbf transmission when the device is incorporated in lin, the sbf (syn chronous break field) transmission control function is used for transmission. for the tr ansmission operation of lin, see figure 12-1 lin transmission operation . sbf transmission is used to transmit an sbf length that is a low-level widt h of 13 bits or more by adjusting the baud rate value of the ordi nary uart transmission function. [setting method] transmit 00h by setting the number of character bits of the data to 8 bits and the parity bit to 0 parity or even parity. this enables a low-level transmi ssion of a data frame consisting of 10 bits (1 bit (start bit) + 8 bits (character bits) + 1 bit (parity bit)). adjust the baud rate value to adjust this 10 -bit low level to the targeted sbf length. example if lin is to be transmitted under the following conditions ? ? ? ? chapter 12 serial interface uart6 user?s manual u15836ej5v0ud 258 if the number of bits set by brgc6 runs short, adjus t the number of bits by setting the base clock of uart6. figure 12-22. example of setting proced ure of sbf transmission (flowchart) start read brgc6 register and save current set value of brgc6 register to general- purpose register. clear txe6 and rxe6 bits of asim6 register to 0 (to disable transmission/ reception). set value to brgc6 register to realize desired sbf length. set character length of data to 8 bits and parity to 0 or even using asim6 register. set txe6 bit of asim6 register to 1 to enable transmission. set txb6 register to "00h" and start transmission. intst6 occurred? no yes clear txe6 and rxe6 bits of asim6 register to 0. rewrite saved brgc6 value to brgc6 register. re-set ps61 bit, ps60 bit, and cl6 bit of asim6 register to desired value. set txe6 bit of asim6 register to 1 to enable transmission. end figure 12-23. sbf transmission t x d6 intst6 1 2 3 4 5 6 7 8 9 10 11 12 13 stop remark t x d6: t x d6 pin (output) intst6: transmission completion interrupt request chapter 12 serial interface uart6 user?s manual u15836ej5v0ud 259 (i) sbf reception when the device is incorporated in lin, the sbf (syn chronous break field) reception control function is used for reception. for the re ception operation of lin, see figure 12-2 lin reception operation . reception is enabled when bit 7 (power6) of asynch ronous serial interface operation mode register 6 (asim6) is set to 1 and then bit 5 (rxe6) of asim6 is se t to 1. sbf reception is enabled when bit 6 (sbrt6) of asynchronous serial interface contro l register 6 (asicl6) is set to 1. in the sbf reception enabled status, the r x d6 pin is sampled and the start bit is detected in the same manner as the normal reception enable status. when the start bit has been det ected, reception is started, and serial data is sequentially stored in receive shift register 6 (rxs6) at the set baud rate. when the stop bit is received and if the width of sbf is 11 bits or more, a reception completion interrupt request (intsr6) is generated as normal processing. at this time, the sbrf6 and sbrt6 bits are automatically cleared, and sbf reception ends. detection of errors, such as ove6, pe6, and fe6 (bits 0 to 2 of asynchronous serial in terface reception error status register 6 (asis6)) is suppressed, and error detection processing of uart communication is not performed. in addition, data transfer between receive shift register 6 (rxs6) and rece ive buffer register 6 (rxb6) is not performed, and the reset value of ffh is retained. if the width of sbf is 10 bits or less, an interrupt does not occur as error processing after the stop bit has been received, and th e sbf reception mode is restored. in this case, the sbrf6 and sbrt6 bits are not cleared. figure 12-24. sbf reception 1. normal sbf reception (stop bit is detect ed with a width of more than 10.5 bits) r x d6 sbrt6 /sbrf6 intsr6 1234567891011 2. sbf reception error (stop bit is detect ed with a width of 10.5 bits or less) r x d6 sbrt6 /sbrf6 intsr6 12345678910 ?0? remark r x d6: r x d6 pin (input) sbrt6: bit 6 of asynchronous serial interface control register 6 (asicl6) sbrf6: bit 7 of asicl6 intsr6: reception completion interrupt request chapter 12 serial interface uart6 user?s manual u15836ej5v0ud 260 12.4.3 dedicated baud rate generator the dedicated baud rate generator consists of a source clock selector and an 8-bit programmable counter, and generates a serial clock for transmission/reception of uart6. separate 8-bit counters are provided for transmission and reception. (1) configuration of ba ud rate generator ? ? ? chapter 12 serial interface uart6 user?s manual u15836ej5v0ud 261 figure 12-25. configuration of baud rate generator selector power6 8-bit counter match detector baud rate baud rate generator brgc6: mdl67 to mdl60 1/2 power6, txe6 (or rxe6) cksr6: tps63 to tps60 f x f x /2 f x /2 2 f x /2 3 f x /2 4 f x /2 5 f x /2 6 f x /2 7 f x /2 8 f x /2 9 f x /2 10 8-bit timer/ event counter 50 output f xclk6 remark power6: bit 7 of asynchronous serial interface operation mode register 6 (asim6) txe6: bit 6 of asim6 rxe6: bit 5 of asim6 cksr6: clock selection register 6 brgc6: baud rate generator control register 6 chapter 12 serial interface uart6 user?s manual u15836ej5v0ud 262 (2) generation of serial clock a serial clock can be generated by using clock selecti on register 6 (cksr6) and baud rate generator control register 6 (brgc6). select the clock to be input to the 8-bit counter by using bits 3 to 0 (tps63 to tps60) of cksr6. bits 7 to 0 (mdl67 to mdl60) of brgc6 can be used to select the division value of the 8-bit counter. (a) baud rate the baud rate can be calculated by the following expression. ? ? ? ? ? chapter 12 serial interface uart6 user?s manual u15836ej5v0ud 263 (3) example of setting baud rate table 12-4. set data of baud rate generator f x = 10.0 mhz f x = 8.38 mhz f x = 4.19 mhz baud rate [bps] tps63 to tps60 k calculated value err[%] tps63 to tps60 k calculated value err[%] tps63 to tps60 k calculated value err[%] 600 6h 130 601 0.16 6h 109 601 0.11 5h 109 601 0.11 1200 5h 130 1202 0.16 5h 109 1201 0.11 4h 109 1201 0.11 2400 4h 130 2404 0.16 4h 109 2403 0.11 3h 109 2403 0.11 4800 3h 130 4808 0.16 3h 109 4805 0.11 2h 109 4805 0.11 9600 2h 130 9615 0.16 2h 109 9610 0.11 1h 109 9610 0.11 10400 2h 120 10417 0.16 2h 101 10371 0.28 1h 101 10475 ? ? ? ? ? ? chapter 12 serial interface uart6 user?s manual u15836ej5v0ud 264 (4) permissible baud rate range during reception the permissible error from the baud rate at the trans mission destination during reception is shown below. caution make sure that the baud rate error during reception is within the permissible error range, by using the calculation expression shown below. figure 12-26. permissible baud rate range during reception fl 1 data frame (11 ? ? ? chapter 12 serial interface uart6 user?s manual u15836ej5v0ud 265 therefore, the maximum receivable baud rate at the transmission destination is as follows. brmax = (flmin/11) ? ? ? ? ? ? ? ? ? ? ? chapter 12 serial interface uart6 user?s manual u15836ej5v0ud 266 (5) data frame length during continuous transmission when data is continuously transmitted, th e data frame length from a stop bit to the next start bit is extended by two clocks of base clock from the normal value. howeve r, the result of communica tion is not affected because the timing is initialized on the recepti on side when the start bit is detected. figure 12-27. data frame length during continuous transmission start bit bit 0 bit 1 bit 7 parity bit stop bit fl 1 data frame fl fl fl fl fl fl flstp start bit of second byte start bit bit 0 where the 1-bit data length is fl, the stop bit length is flstp, and base clock frequency is f xclk6 , the following expression is satisfied. flstp = fl + 2/f xclk6 therefore, the data frame length during continuous transmission is: data frame length = 11 user?s manual u15836ej5v0ud 267 chapter 13 serial interface csi10 13.1 functions of serial interface csi10 serial interface csi10 has the following two modes. ? ? chapter 13 serial interface csi10 user?s manual u15836ej5v0ud 268 figure 13-1. block diagram of serial interface csi10 internal bus si10/p11(/rxd0 note ) intcsi10 f x /2 f x /2 2 f x /2 3 f x /2 4 f x /2 5 f x /2 6 f x /2 7 sck10/p10 (/txd0 note ) transmit buffer register 10 (sotb10) transmit controller clock start/stop controller & clock phase controller serial i/o shift register 10 (sio10) output selector so10/p12 output latch 8 transmit data controller 8 output latch (p12) pm12 selector note chapter 13 serial interface csi10 user?s manual u15836ej5v0ud 269 13.3 registers controlling serial interface csi10 serial interface csi10 is controlled by the following four registers. ? ? ? ? chapter 13 serial interface csi10 user?s manual u15836ej5v0ud 270 (2) serial clock selecti on register 10 (csic10) this register specifies the timing of the data transmission/reception and sets the serial clock. csic10 can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 13-3. format of serial clo ck selection register 10 (csic10) address: ff81h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 csic10 0 0 0 ckp10 dap10 cks102 cks101 cks100 ckp10 dap10 specification of data transmission/reception timing type 0 0 d7 d6 d5 d4 d3 d2 d1 d0 sck10 so10 si10 input timing 1 0 1 d7 d6 d5 d4 d3 d2 d1 d0 sck10 so10 si10 input timing 2 1 0 d7 d6 d5 d4 d3 d2 d1 d0 sck10 so10 si10 input timing 3 1 1 d7 d6 d5 d4 d3 d2 d1 d0 sck10 so10 si10 input timing 4 cks102 cks101 cks100 csi10 serial clock selection note mode 0 0 0 f x /2 (5 mhz) master mode 0 0 1 f x /2 2 (2.5 mhz) master mode 0 1 0 f x /2 3 (1.25 mhz) master mode 0 1 1 f x /2 4 (625 khz) master mode 1 0 0 f x /2 5 (312.5 khz) master mode 1 0 1 f x /2 6 (156.25 khz) master mode 1 1 0 f x /2 7 (78.13 khz) master mode 1 1 1 external clock input to sck10 slave mode note be sure to set the serial clock so that the following condition is satisfied. ? ? ? ? chapter 13 serial interface csi10 user?s manual u15836ej5v0ud 271 cautions 1. when the ring-osc clo ck is selected as the clock supplied to the cpu, the clock of the ring- osc oscillator is divided and supp lied as the serial clock. at th is time, the operation of serial interface csi10 is not guaranteed. 2. do not write to csic10 while csie10 = 1 (operation enabled). 3. clear ckp10 to 0 to use p10/sck10 (/txd0 note ), p11/si10 (/rxd0 note ), and p12/so10 as general- purpose port pins. 4. the phase type of the data clock is type 1 after reset. note pd780102, 780103, 78f0103 only. remarks 1. figures in parentheses are for operation with f x = 10 mhz 2. f x : x1 input clock oscillation frequency (3) port mode register 1 (pm1) this register sets port 1 input/output in 1-bit units. when using p10/sck10(/txd0 note ) as the clock output pin of the serial interface, clear pm10 to 0 and set the output latch of p10 to 1. when using p12/so10 as the data output pin of the serial interface, clear pm12 and the output latch of p12 to 0. when using p10/sck10(/txd0 note ) as the clock input pin of the se rial interface, and p11/si10(/rxd0 note ) as the data input pin, set pm10 and pm11 to 1. at this ti me, the output latches of p10 and p11 may be 0 or 1. pm1 can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to ffh. note pd780102, 780103, 78f0103 only. figure 13-4. format of port mode register 1 (pm1) address: ff21h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm1 pm17 pm16 pm15 pm14 pm13 pm12 pm11 pm10 pm1n p1n pin i/o mode selection (n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) chapter 13 serial interface csi10 user?s manual u15836ej5v0ud 272 13.4 operation of serial interface csi10 serial interface csi10 can be used in the following two modes. ? ? chapter 13 serial interface csi10 user?s manual u15836ej5v0ud 273 13.4.2 3-wire serial i/o mode the 3-wire serial i/o mode can be used fo r connecting peripheral ics and displa y controllers that have a clocked serial interface. in this mode, communication is executed by using three li nes: the serial clock (sck10), serial output (so10), and serial input (si10) lines. (1) registers used ? ? ? ? chapter 13 serial interface csi10 user?s manual u15836ej5v0ud 274 the relationship between the register settings and pins is shown below. table 13-2. relationship between register settings and pins pin function csie10 trmd10 pm11 p11 pm12 p12 pm10 p10 csi10 operation p11/si10 (/rxd0 note 4 ) p12/so10 p10/sck10 (/txd0 note 4 ) 0 note 1 note 1 note 1 note 1 note 1 note 1 stop p11 (/rxd0 note 4 ) p12 p10 (/txd0 note 4 ) note 2 1 0 1 note 1 note 1 1 slave reception note 3 si10 p12 sck10 (input) note 3 1 1 note 1 note 1 0 0 1 slave transmission note 3 p11 (/rxd0 note 4 ) so10 sck10 (input) note 3 1 1 1 0 0 1 slave transmission/ reception note 3 si10 so10 sck10 (input) note 3 1 0 1 note 1 note 1 0 1 master reception si10 p12 sck10 (output) 1 1 note 1 note 1 0 0 0 1 master transmission p11 (/rxd0 note 4 ) so10 sck10 (output) 1 1 1 0 0 0 1 master transmission/ reception si10 so10 sck10 (output) notes 1. can be set as port function. 2. to use p10/sck10(/txd0 note 4 ) as port pins, clear ckp10 to 0. 3. to use the slave mode, set cks102, cks101, and cks100 to 1, 1, 1. 4. chapter 13 serial interface csi10 user?s manual u15836ej5v0ud 275 (2) communication operation in the 3-wire serial i/o mode, data is tr ansmitted or received in 8-bit units. each bit of the dat a is transmitted or received in synchronization with the serial clock. data can be transmitted or received if bit 6 (trmd10) of serial operation mode register 10 (csim10) is 1. transmission/reception is started when a value is writt en to transmit buffer register 10 (sotb10). in addition, data can be received when bit 6 (trmd10) of seri al operation mode register 10 (csim10) is 0. reception is started when dat a is read from serial i/o shift register 10 (sio10). after communication has been started, bi t 0 (csot10) of csim10 is set to 1. when communication of 8-bit data has been completed, a communication completion interrupt request flag (csiif10) is set, and csot10 is cleared to 0. then the next communication is enabled. caution do not access the control register and data register when csot10 = 1 (during serial communication). figure 13-5. timing in 3-wire serial i/o mode (1/2) (1) transmission/reception ti ming (type 1; trmd10 = 1, di r10 = 0, ckp10 = 0, dap10 = 0) aah abh 56h adh 5ah b5h 6ah d5h 55h (communication data) 55h is written to sotb10. sck10 sotb10 sio10 csot10 csiif10 so10 si10 (receive aah) read/write trigger intcsi10 chapter 13 serial interface csi10 user?s manual u15836ej5v0ud 276 figure 13-5. timing in 3-wire serial i/o mode (2/2) (2) transmission/reception ti ming (type 2; trmd10 = 1, di r10 = 0, ckp10 = 0, dap10 = 1) abh 56h adh 5ah b5h 6ah d5h sck10 sotb10 sio10 csot10 csiif10 so10 si10 (input aah) aah 55h (communication data) 55h is written to sotb10. read/write trigger intcsi10 chapter 13 serial interface csi10 user?s manual u15836ej5v0ud 277 figure 13-6. timing of clock/data phase (a) type 1; ckp10 = 0, dap10 = 0 d7 d6 d5 d4 d3 d2 d1 d0 sck10 so10 writing to sotb10 or reading from sio10 si10 capture csiif10 csot10 (b) type 2; ckp10 = 0, dap10 = 1 d7 d6 d5 d4 d3 d2 d1 d0 sck10 so10 writing to sotb10 or reading from sio10 si10 capture csiif10 csot10 (c) type 3; ckp10 = 1, dap10 = 0 d7 d6 d5 d4 d3 d2 d1 d0 sck10 so10 writing to sotb10 or reading from sio10 si10 capture csiif10 csot10 (d) type 4; ckp10 = 1, dap10 = 1 d7 d6 d5 d4 d3 d2 d1 d0 sck10 so10 writing to sotb10 or reading from sio10 si10 capture csiif10 csot10 chapter 13 serial interface csi10 user?s manual u15836ej5v0ud 278 (3) timing of output to so10 pin (first bit) when communication is started, the value of transmit buffe r register 10 (sotb10) is output from the so10 pin. the output operation of the first bit at this time is described below. figure 13-7. output operation of first bit (1) when ckp10 = 0, dap10 = 0 (or ckp10 = 1, dap10 = 0) sck10 sotb10 sio10 so10 writing to sotb10 or reading from sio10 first bit 2nd bit output latch the first bit is directly latched by the sotb10 register to the output latch at the falling (or rising) edge of sck10, and output from the so10 pin via an output selector. th en, the value of the sotb10 register is transferred to the sio10 register at the next rising (or fa lling) edge of sck10, and shifted one bit. at the same time, the first bit of the receive data is stored in the s io10 register via the si10 pin. the second and subsequent bits are latc hed by the sio10 register to the output latch at the next falling (or rising) edge of sck10, and the data is output from the so10 pin. (2) when ckp10 = 0, dap10 = 1 (or ckp10 = 1, dap10 = 1) sck10 sotb10 sio10 so10 writing to sotb10 or reading from sio10 first bit 2nd bit 3rd bit output latch the first bit is directly latched by the sotb10 register at the falling edge of the write signal of the sotb10 register or the read signal of the sio10 register, and output from the so10 pin via an output selector. then, the value of the sotb10 register is transfe rred to the sio10 register at the next falling (or rising) edge of sck10, and shifted one bit. at the same time, the first bit of the rece ive data is stored in the sio10 register via the si10 pin. the second and subsequent bits are latc hed by the sio10 register to the out put latch at the next rising (or falling) edge of sck10, and the data is output from the so10 pin. chapter 13 serial interface csi10 user?s manual u15836ej5v0ud 279 (4) output value of so10 pin (last bit) after communication has been completed, the so10 pin holds the output value of the last bit. figure 13-8. output valu e of so10 pin (last bit) (1) type 1; when ckp10 = 0 and dap10 = 0 (or ckp10 = 1, dap10 = 0) sck10 sotb10 sio10 so10 writing to sotb10 or reading from sio10 ( ? ? ? user?s manual u15836ej5v0ud 280 chapter 14 interrupt functions 14.1 interrupt function types the following two types of inte rrupt functions are used. (1) maskable interrupts these interrupts undergo mask control. maskable interrup ts can be divided into a high interrupt priority group and a low interrupt priority group by setting the priority specification flag registers (pr0l, pr0h, pr1l). multiple interrupt servicing of high-priority interrupts c an be applied to low priority interrupts. if two or more interrupts with the same priority are simultaneously ge nerated, each interrupt is serviced according to its predetermined priority (see table 14-1 ). a standby release signal is generated and the stop m ode and halt mode are released by maskable interrupts. six external interrupt requests and 12 internal interr upt requests are provided as maskable interrupts. (2) software interrupt this is a vectored interrupt generated by executing the brk instruction. it is acknowledged even when interrupts are disabled. the software interrupt does not undergo interrupt priority control. 14.2 interrupt sources and configuration a total of 19 interrupt sources exist for maskable and softw are interrupts. in addition, maximum total of 5 reset sources are also provided (see table 14-1 ). chapter 14 interrupt functions user?s manual u15836ej5v0ud 281 table 14-1. interrupt source list interrupt source interrupt type default priority note 1 name trigger internal/ external vector table address basic configuration type note 2 0 intlvi low-voltage detection note 3 internal 0004h (a) 1 intp0 0006h 2 intp1 0008h 3 intp2 000ah 4 intp3 000ch 5 intp4 000eh 6 intp5 pin input edge detection external 0010h (b) 7 intsre6 uart6 reception error generation 0012h 8 intsr6 end of uart6 reception 0014h 9 intst6 end of uart6 transmission 0016h 10 intcsi10/ intst0 note 4 end of csi10 communication/end of uart0 transmission 0018h 11 inttmh1 match between tmh1 and cmp01 (when compare register is specified) 001ah 12 inttmh0 match between tmh0 and cmp00 (when compare register is specified) 001ch 13 inttm50 match between tm50 and cr50 (when compare register is specified) 001eh 14 inttm000 match between tm00 and cr000 (when compare register is specified) 0020h 15 inttm010 match between tm00 and cr010 (when compare register is specified) 0022h 16 intad end of a/d conversion 0024h maskable 17 intsr0 note 4 end of uart0 reception internal 0026h (a) software ? brk brk instruction execution ? 003eh (c) reset reset input poc power-on-clear note 5 lvi low-voltage detection note 6 clock monitor x1 input clock stop detection reset ? wdt wdt overflow ? 0000h ? notes 1. the default priority is the priority applicable when two or more maskable interrupts are generated simultaneously. 0 is the highest priority, and 17 is the lowest. 2. basic configuration types (a) to (c) co rrespond to (a) to (c) in figure 14-1. 3. when bit 1 (lvimd) = 0 is selected for t he low-voltage detection register (lvim). 4. the interrupt sources intst0 and intsr0 are available only in the pd780102, 780103, and 78f0103. 5. when ?poc used? is selected by mask option. 6. when lvimd = 1 is selected. chapter 14 interrupt functions user?s manual u15836ej5v0ud 282 figure 14-1. basic configuration of interrupt function (a) internal maskable interrupt internal bus interrupt request if mk ie pr isp priority controller vector table address generator standby release signal (b) external maskable inte rrupt (intp0 to intp5) internal bus interrupt request if mk ie pr isp priority controller vector table address generator standby release signal external interrupt edge enable register (egp, egn) edge detector (c) software interrupt internal bus interrupt request priority controller vector table address generator if: interrupt request flag ie: interrupt enable flag isp: in-service priority flag mk: interrupt mask flag pr: priority specification flag chapter 14 interrupt functions user?s manual u15836ej5v0ud 283 14.3 registers controlling interrupt function the following 6 types of registers are used to control the interrupt functions. ? ? ? ? ? ? chapter 14 interrupt functions user?s manual u15836ej5v0ud 284 (1) interrupt request flag re gisters (if0l, if0h, if1l) the interrupt request flags are set to 1 when the correspo nding interrupt request is g enerated or an instruction is executed. they are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon application of reset input. when an interrupt is acknowledged, the interrupt req uest flag is automatically cleared and then the interrupt routine is entered. if0l, if0h, and if1l are set by a 1-bit or 8-bit memory manipulation instruction. when if0l and if0h are combined to form 16-bit register if0, they are set by a 16-bit memory manipulation instruction. reset input clears these registers to 00h. figure 14-2. format of interrupt request flag register (if0l, if0h, if1l) address: ffe0h after reset: 00h r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> if0l sreif6 pif5 pif4 pif3 pif2 pif1 pif0 lviif address: ffe1h after reset: 00h r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> if0h tmif010 tmif000 tmif50 tmifh0 tmifh1 dualif0 note 1 stif6 srif6 address: ffe2h after reset: 00h r/w symbol 7 6 5 4 3 2 <1> <0> if1l 0 0 0 0 0 0 srif0 note 2 adif xxifx interrupt request flag 0 no interrupt request signal is generated 1 interrupt request is generated, interrupt request status notes 1. this is csiif10 in the pd780101. 2. pd780102, 780103, and 78f0103 only. cautions 1. be sure to clear bits 2 to 7 of if1l to 0. 2. when operating a timer, seri al interface, or a/d converter a fter standby release, operate it once after clearing the interrupt request flag. an interrupt request flag may be set by noise. 3. when manipulating a flag of the interrupt request flag register , use a 1-bit memory manipulation instruction (clr1). when desc ribing in c language, use a bit manipulation instruction such as ??if0l.0 = 0;?? or ??_asm(? ?clr1 if0l, 0??);?? becau se the compiled assembler must be a 1-bit memory manipulation instruction (clr1). if a program is described in c language using an 8-bit memory manipulation instruction such as ??if0l &= 0xfe;?? and compiled, it becomes the assembler of three instructions. mov a, if0l and a, #0feh mov if0l, a in this case, even if the request flag of anothe r bit of the same interrupt request flag register (if0l) is set to 1 at the timing between ??mov a, if0l?? and ??mov if0l, a??, the flag is cleared to 0 at ??mov if0l, a? ?. therefore, care must be exerci sed when using an 8-bit memory manipulation instruction in c language. chapter 14 interrupt functions user?s manual u15836ej5v0ud 285 (2) interrupt mask flag registers (mk0l, mk0h, mk1l) the interrupt mask flags are used to enable/disable the corresponding maskable interrupt servicing. mk0l, mk0h, and mk1l are set by a 1-bit or 8-bit memory manipulation instruction. when mk0l and mk0h are combined to form a 16-bit register mk0, they are se t with a 16-bit memory manipulation instruction. reset input sets these registers to ffh. figure 14-3. format of interrupt mask flag register (mk0l, mk0h, mk1l) address: ffe4h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> mk0l sremk6 pmk5 pmk4 pmk3 pmk2 pmk1 pmk0 lvimk address: ffe5h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> mk0h tmmk010 tmmk000 tmmk50 tmmkh0 tmmkh1 dualmk0 note 1 stmk6 srmk6 address: ffe6h after reset: ffh r/w symbol 7 6 5 4 3 2 <1> <0> mk1l 1 1 1 1 1 1 srmk0 note 2 admk xxmkx interrupt servicing control 0 interrupt servicing enabled 1 interrupt servicing disabled notes 1. this is csimk10 in the chapter 14 interrupt functions user?s manual u15836ej5v0ud 286 (3) priority specification flag registers (pr0l, pr0h, pr1l) the priority specification flag regist ers are used to set the corresponding maskable interrupt priority order. pr0l, pr0h, and pr1l are set by a 1-bit or 8-bit memo ry manipulation instruction. if pr0l and pr0h are combined to form 16-bit register pr0, they are se t with a 16-bit memory manipulation instruction. reset input sets these registers to ffh. figure 14-4. format of prio rity specification flag regi ster (pr0l, pr0h, pr1l) address: ffe8h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> pr0l srepr6 ppr5 ppr4 ppr3 ppr2 ppr1 ppr0 lvipr address: ffe9h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> pr0h tmpr010 tmpr000 tmpr50 tmprh0 tmprh1 dualpr0 note 1 stpr6 srpr6 address: ffeah after reset: ffh r/w symbol 7 6 5 4 3 2 <1> <0> pr1l 1 1 1 1 1 1 srpr0 note 2 adpr xxprx priority level selection 0 high priority level 1 low priority level notes 1. this is csipr10 in the pd780101. 2. pd780102, 780103, and 78f0103 only. caution be sure to set bits 2 to 7 of pr1l to 1. chapter 14 interrupt functions user?s manual u15836ej5v0ud 287 (4) external interrupt rising edge en able register (egp), external interrupt falling edge enable register (egn) these registers specify the valid edge for intp0 to intp5. egp and egn are set by a 1-bit or 8-bit memory manipulation instruction. reset input clears these registers to 00h. figure 14-5. format of external interr upt rising edge enable register (egp) and external interrupt falling edge enable register (egn) address: ff48h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 egp 0 0 egp5 egp4 egp3 egp2 egp1 egp0 address: ff49h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 egn 0 0 egn5 egn4 egn3 egn2 egn1 egn0 egpn egnn intpn pin valid edge selection (n = 0 to 5) 0 0 edge detection disabled 0 1 falling edge 1 0 rising edge 1 1 both rising and falling edges table 14-3 shows the ports corresponding to egpn and egnn. table 14-3. ports correspo nding to egpn and egnn detection enable register edge detection port interrupt request signal egp0 egn0 p120 intp0 egp1 egn1 p30 intp1 egp2 egn2 p31 intp2 egp3 egn3 p32 intp3 egp4 egn4 p33 intp4 egp5 egn5 p16 intp5 caution select the port mode by clearing egpn and egnn to 0 because an edge may be detected when the external interrupt function is switched to the port function. remark n = 0 to 5 chapter 14 interrupt functions user?s manual u15836ej5v0ud 288 (5) program status word (psw) the program status word is a register used to hold the instruction exec ution result and the current status for an interrupt request. the ie flag that sets maskable interr upt enable/disable and the isp fl ag that controls multiple interrupt servicing are mapped to the psw. besides 8-bit read/write, this register can carry out op erations using bit manipulation instructions and dedicated instructions (ei and di). when a vect ored interrupt request is acknowledged, if the brk instruction is executed, the contents of the psw are aut omatically saved into a stack and the ie flag is reset to 0. if a maskable interrupt request is acknowledged, the contents of the priority specification flag of t he acknowledged interrupt are transferred to the isp flag. the psw contents are also saved into the stack with t he push psw instruction. they are restored from the stack with the reti, retb, and pop psw instructions. reset input sets psw to 02h. figure 14-6. format of program status word <7> ie <6> z <5> rbs1 <4> ac <3> rbs0 2 0 <1> isp 0 cy psw after reset 02h isp high-priority interrupt servicing (low-priority interrupt disabled) ie 0 1 disabled priority of interrupt currently being serviced interrupt request acknowledgment enable/disable used when normal instruction is executed enabled interrupt request not acknowledged, or low- priority interrupt servicing (all maskable interrupts enabled) 0 1 chapter 14 interrupt functions user?s manual u15836ej5v0ud 289 14.4 interrupt servicing operations 14.4.1 maskable interrupt request acknowledgment a maskable interrupt request becomes acknowledgeable when the interrupt request flag is set to 1 and the mask (mk) flag corresponding to that interrupt request is cleared to 0. a vectored interrupt request is acknowledged if interrupts are in the interrupt enabled stat e (when the ie flag is set to 1). however, a low-priority interrupt request is not acknowledged during servicing of a higher priority interrupt request (when the isp flag is reset to 0). the times from generation of a maskable interrupt request until interrupt servicing is performed are listed in table 14-4 below. for the interrupt request acknowledgment timing, see figures 14-8 and 14-9 . table 14-4. time from ge neration of maskable interrupt request until servicing minimum time maximum time note when chapter 14 interrupt functions user?s manual u15836ej5v0ud 290 figure 14-7. interrupt request acknowledgment processing algorithm start chapter 14 interrupt functions user?s manual u15836ej5v0ud 291 figure 14-8. interrupt request ac knowledgment timing (minimum time) 8 clocks 7 clocks instruction instruction psw and pc saved, jump to interrupt servicing interrupt servicing program cpu processing chapter 14 interrupt functions user?s manual u15836ej5v0ud 292 14.4.3 multiple interrupt servicing multiple interrupt servicing occurs when another interrupt re quest is acknowledged during execution of an interrupt. multiple interrupt servicing does not occur unless the inte rrupt request acknowledgment enabled state is selected (ie = 1). when an interrupt request is acknowledged, inte rrupt request acknowledgment becomes disabled (ie = 0). therefore, to enable multiple interrupt se rvicing, it is necessary to set (1) the ie flag with the ei instruction during interrupt servicing to enable interrupt acknowledgment. moreover, even if interrupts are enabled, multiple interr upt servicing may not be enabled, this being subject to interrupt priority control. two types of priority control are available: default priority control and programmable priority control. programmable priority control is used for multiple interrupt servicing. in the interrupt enabled state, if an in terrupt request with a priority equal to or higher than that of the interrupt currently being serviced is generated, it is acknowledged for mu ltiple interrupt servicing. if an interrupt with a priority lower than that of the interrupt current ly being serviced is generated during interr upt servicing, it is not acknowledged for multiple interrupt servicing. interrupt requests that are not enabled because interrupts are in the interrupt disabled state or because they have a lower priority are held pending. when servicing of t he current interrupt ends, the pending interrupt request is acknowledged following execution of at least one main processing instruction execution. table 14-5 shows relationship between interrupt requests enabled for multiple interrupt servicing and figure 14-10 shows multiple interrupt servicing examples. table 14-5. relationship between interrupt requests enabled for multiple interrupt servicing during interrupt servicing maskable interrupt request pr = 0 pr = 1 multiple interrupt request interrupt being serviced ie = 1 ie = 0 ie = 1 ie = 0 software interrupt request isp = 0 chapter 14 interrupt functions user?s manual u15836ej5v0ud 293 figure 14-10. examples of multip le interrupt se rvicing (1/2) example 1. multiple inte rrupt servicing occurs twice main processing intxx servicing intyy servicing intzz servicing ei ei ei reti reti reti intxx (pr = 1) intyy (pr = 0) intzz (pr = 0) ie = 0 ie = 0 ie = 0 ie = 1 ie = 1 ie = 1 during servicing of interrupt intxx, two interrupt re quests, intyy and intzz, are acknowledged, and multiple interrupt servicing takes place. before each interrupt request is acknowledged, the ei instruction must always be issued to enable interrupt request acknowledgment. example 2. multiple interrupt servicing does not occur due to priority control main processing intxx servicing intyy servicing intxx (pr = 0) intyy (pr = 1) ei reti ie = 0 ie = 0 ei 1 instruction execution reti ie = 1 ie = 1 interrupt request intyy issued during servicing of interrupt intxx is not acknowledged because its priority is lower than that of intxx, and mu ltiple interrupt servicing does not take place. the intyy interrupt request is held pending, and is acknowledged following execution of one main processing instruction. pr = 0: higher priority level pr = 1: lower priority level ie = 0: interrupt request acknowledgment disabled chapter 14 interrupt functions user?s manual u15836ej5v0ud 294 figure 14-10. examples of multip le interrupt se rvicing (2/2) example 3. multiple interrupt servicing do es not occur because inte rrupts are not enabled main processing intxx servicing intyy servicing ei 1 instruction execution reti reti intxx (pr = 0) intyy (pr = 0) ie = 0 ie = 0 ie = 1 ie = 1 interrupts are not enabled during servicing of interrupt int xx (ei instruction is not issued), therefore, interrupt request intyy is not acknowledged and multiple interrupt serv icing does not take place. the intyy interrupt request is held pending, and is acknowledged following ex ecution of one main processing instruction. pr = 0: higher priority level ie = 0: interrupt request acknowledgment disabled chapter 14 interrupt functions user?s manual u15836ej5v0ud 295 14.4.4 interrupt request hold there are instructions where, even if an interrupt request is issued for t hem while another instruction is being executed, request acknowledgment is held pending until the end of execution of the ne xt instruction. these instructions (interrupt request hol d instructions) are listed below. ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? user?s manual u15836ej5v0ud 296 chapter 15 standby function 15.1 standby function and configuration 15.1.1 standby function table 15-1. relationship between operat ion clocks in each operation status ring-osc oscillator prescaler clock supplied to peripherals note 2 status operation mode x1 oscillator note 1 rstop = 0 rstop = 1 cpu clock after release mcm0 = 0 mcm0 = 1 reset stopped ring-osc stopped stop stopped note 3 stopped halt oscillating oscillating oscillating stopped note 4 ring-osc x1 notes 1. when ?cannot be stopped? is select ed for ring-osc by a mask option. 2. when ?can be stopped by software? is selected for ring-osc by a mask option. 3. operates using the cpu clock at stop instruction execution. 4. operates using the cpu clock at halt instruction execution. caution the rstop setting is valid only when ?can be stopped by software? is set for ring-osc by a mask option. remark rstop: bit 0 of the ring-osc mode register (rcm) mcm0: bit 0 of the main clock mode register (mcm) the standby function is designed to redu ce the operating current consumption of the system. the following two modes are available. chapter 15 standby function user?s manual u15836ej5v0ud 297 (1) halt mode halt instruction execution sets the ha lt mode. the halt mode is intended to stop the cpu operation clock. if the x1 input clock and ring-osc clock oscillator are operat ing before the halt mode is set, oscillation of the x1 input clock and ring-osc clock continues. in this mode, operating current is not decreased as much as in the stop mode. however, the halt m ode is effective for restarting operation immediately upon interrupt request generation and carrying out intermittent operations. (2) stop mode stop instruction execution sets the stop mode. in the stop mode, the x1 oscillator stops, stopping the whole system, thereby considerably r educing the cpu operating current. because this mode can be cleared by an interrupt reques t, it enables intermittent operations to be carried out. however, because a wait time is required to secure th e oscillation stabilization time after the stop mode is released, select the halt mode if it is necessary to start processing immediately upon interrupt request generation. in either of these two modes, all the contents of registers, flags and data me mory just before the standby mode is set are held. the i/o port output latches an d output buffer statuses are also held. cautions 1. when shifting to the stop mode, be su re to stop the peripheral hardware operation before executing stop instruction. 2. the following sequence is recommended for operating current reduction of the a/d converter when the standby function is used: first cl ear bit 7 (adcs) of the a/d converter mode register (adm) to 0 to stop the a/d conversi on operation, and then execute the halt or stop instruction. 3. if the ring-osc oscillator is operating before the stop mode is set, oscillation of the ring- osc clock cannot be stopped in the stop mode. however, when the ri ng-osc clock is used as the cpu clock, the cpu operation is stopped for 17/f r (s) after stop mode is released. chapter 15 standby function user?s manual u15836ej5v0ud 298 15.1.2 registers controlling standby function the standby function is controlled by the following two registers. ? oscillation stabilization time c ounter status register (ostc) ? oscillation stabilization time select register (osts) remark for the registers that start, st op, or select the clock, see chapter 5 clock generator . (1) oscillation stabilization time c ounter status register (ostc) this is the status register of the x1 input clock oscillation stabilization time counter. if the ring-osc clock is used as the cpu clock, the x1 input clock o scillation stabilization time can be checked. ostc can be read by a 1-bit or 8-bit memory manipulation instruction. when reset is released (reset by reset input, poc, lvi, clock monitor, and wdt), the stop instruction, and mstop (bit 7 of moc register) = 1 clear ostc to 00h. figure 15-1. format of oscillation stabilizati on time counter status register (ostc) address: ffa3h after reset: 00h r symbol 7 6 5 4 3 2 1 0 ostc 0 0 0 most11 most 13 most14 most15 most16 oscillation stabilization time status most11 most13 mo st14 most15 most16 f xp = 10 mhz f xp = 12 mhz note 1 0 0 0 0 2 11 /f xp min. 204.8 s min. 170.7 s min. 1 1 0 0 0 2 13 /f xp min. 819.2 s min. 682.7 s min. 1 1 1 0 0 2 14 /f xp min. 1.64 ms min. 1.37 ms min. 1 1 1 1 0 2 15 /f xp min. 3.27 ms min. 2.73 ms min. 1 1 1 1 1 2 16 /f xp min. 6.55 ms min. 5.46 ms min. note expanded-specification products of st andard products and (a) grade products only chapter 15 standby function user?s manual u15836ej5v0ud 299 cautions 1. after the above time has elapsed, th e bits are set to 1 in order from most11 and remain 1. 2. if the stop mode is entered and th en released while the ring-osc clock is being used as the cpu clo ck, set the oscillation stabilization time as follows. ? chapter 15 standby function user?s manual u15836ej5v0ud 300 (2) oscillation stabilization time select register (osts) this register is used to select the x1 oscillation stabil ization wait time when stop mo de is released. the wait time set by osts is valid only after stop mode is released when the x1 input clock is selected as the cpu clock. after stop mode is released when the ring-os c clock is selected as the cpu clock, check the oscillation stabilization time using ostc. osts can be set by an 8-bit memory manipulation instruction. reset input sets osts to 05h. figure 15-2. format of oscillation stabiliz ation time select register (osts) address: ffa4h after reset: 05h r/w symbol 7 6 5 4 3 2 1 0 osts 0 0 0 0 0 osts2 osts1 osts0 oscillation stabilization time selection osts2 osts1 osts0 f xp = 10 mhz f xp = 12 mhz note 0 0 1 2 11 /f xp 204.8 s 170.7 s 0 1 0 2 13 /f xp 819.2 s 682.7 s 0 1 1 2 14 /f xp 1.64 ms 1.37 ms 1 0 0 2 15 /f xp 3.27 ms 2.73 ms 1 0 1 2 16 /f xp 6.55 ms 5.46 ms other than above setting prohibited note expanded-specification products of st andard products and (a) grade products only cautions 1. to set the stop mode when the x1 input clock is used as the cpu clock, set osts before executing the stop instruction. 2. execute the osts setting after confi rming that the oscillation stabilization time has elapsed as expect ed in the ostc. 3. if the stop mode is entered and th en released while the ring-osc clock is being used as the cpu clo ck, set the oscillation stabilization time as follows. ? desired ostc oscillation stabilization time oscillation stabilization time set by osts the x1 oscillation stabilization time counter counts only dur ing the oscillation stabilization time set by osts. therefo re, note that only the statuses during the oscillation stabilization time set by osts are set to ostc a fter stop mode has been released. 4. the wait time when stop mode is released does not include the time after stop mode release until clock oscillation starts (?a? below) regardless of whether stop mode is released by r eset input or interrupt generation. a stop mode release x1 pin voltage waveform remark f x : x1 input clock oscillation frequency chapter 15 standby function user?s manual u15836ej5v0ud 301 15.2 standby function operation 15.2.1 halt mode (1) halt mode the halt mode is set by executing t he halt instruction. halt mode c an be set when the cpu clock before the setting was the x1 input clock or ring-osc clock. the operating statuses in t he halt mode are shown below. table 15-2. operating statuses in halt mode when halt instruction is executed while cpu is operating using x1 input clock when halt instruction is executed while cpu is operating using ring-osc clock halt mode setting item ring-osc oscillation continues ring-osc oscillation stopped note 1 x1 input clock oscillation continues x1 input clock oscillation stopped system clock clock supply to the cpu is stopped cpu operation stopped port (output latch) holds the status before halt mode was set 16-bit timer/event counter 00 o perable operation not guaranteed 8-bit timer/event counter 50 operabl e operation not guaranteed when count clock other than ti50 is selected 8-bit timer h0 operable oper ation not guaranteed when count clock other than tm50 output is selected during 8-bit timer/event counter 50 operation 8-bit timer h1 operable oper ation not guaranteed when count clock other than f r /2 7 is selected ring-osc cannot be stopped note 2 operable ? chapter 15 standby function user?s manual u15836ej5v0ud 302 (2) halt mode release the halt mode can be released by the following two sources. (a) release by unmasked interrupt request when an unmasked interrupt request is generated, the halt mode is released. if interrupt acknowledgement is enabled, vectored interrupt servicin g is carried out. if interrupt acknowledgement is disabled, the next address instruction is executed. figure 15-3. halt mode release by interrupt request generation halt instruction wait wait operating mode halt mode operating mode oscillation x1 input clock or ring-osc clock status of cpu standby release signal interrupt request remarks 1. the broken lines indicate the case when the interrupt request which has released the standby mode is acknowledged. 2. the wait time is as follows: when vectored interrupt servicing is carried out: 8 or 9 clocks when vectored interrupt servicing is not carried out: 2 or 3 clocks chapter 15 standby function user?s manual u15836ej5v0ud 303 (b) release by reset input when the reset signal is input, halt mode is rele ased, and then, as in the case with a normal reset operation, the program is executed after br anching to the reset vector address. figure 15-4. halt mode release by reset input (1) when x1 input clock is used as cpu clock halt instruction reset signal x1 input clock operating mode halt mode reset period operation stopped operating mode oscillates oscillation stopped oscillates status of cpu (x1 input clock) oscillation stabilization time (2 11 /f xp to 2 16 /f xp ) (ring-osc clock) (17/f r ) (2) when ring-osc clo ck is used as cpu clock halt instruction reset signal ring-osc clock operating mode halt mode reset period operation stopped operating mode oscillates oscillation stopped oscillates status of cpu (ring-osc clock) (17/f r ) (ring-osc clock) remarks 1. f xp : x1 input clock oscillation frequency 2. f r : ring-osc clock oscillation frequency table 15-3. operation in response to interrupt request in halt mode release source mk ? ? chapter 15 standby function user?s manual u15836ej5v0ud 304 15.2.2 stop mode (1) stop mode setting and operating statuses the stop mode is set by executing t he stop instruction. it can be set when the cpu clock before the setting was the x1 input clock or ring-osc clock. caution because the interrupt request signal is used to clear the standby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is immediately cleared if set. thus, the stop mode is reset to the halt mode immediately after execution of the stop instruction and the system returns to the operating mode as soon as the wait time set using the oscillation stabilizat ion time select register (osts) has elapsed. the operating statuses in t he stop mode are shown below. table 15-4. operating statuses in stop mode when stop instruction is executed while cpu is operating using x1 input clock halt mode setting item ring-osc oscillation continues ring-osc oscillation stopped note 1 when stop instruction is executed while cpu is operating using ring-osc clock system clock only x1 oscillator oscillation is stopped. clock supply to the cpu is stopped. cpu operation stopped port (output latch) holds the status before stop mode was set 16-bit timer/event counter 00 operation stopped 8-bit timer/event counter 50 operable onl y when ti50 is selected as count clock 8-bit timer h0 operable when tm50 output is selected as count clock during 8-bit timer/event counter 50 operation 8-bit timer h1 operable note 2 operation stopped operable note 2 ring-osc cannot be stopped note 3 operable ? operable watchdog timer ring-osc can be stopped note 3 operation stopped a/d converter operation stopped uart0 note 4 uart6 operable only when tm50 output is selected as serial clock duri ng 8-bit timer/event counter 50 operation serial interface csi10 operable only when external sc k10 is selected as serial clock clock monitor operation stopped power-on-clear function note 5 operable low-voltage detection function operable external interrupt operable notes 1. when ?stopped by software? is selected for ring-osc by a mask option and ring-osc is stopped by software (for mask options, see chapter 20 mask options ). 2. operable only when f r /2 7 is selected as count clock. 3. ?ring-osc cannot be stopped? or ?ring-osc can be stopped by software? can be selected by a mask option. 4. pd780102, 780103, and 78f0103 only. 5. when ?poc used? is selected by a mask option. chapter 15 standby function user?s manual u15836ej5v0ud 305 (2) stop mode release figure 15-5. operation timing wh en stop mode is released ring-osc clock is selected as cpu clock when stop instruction is executed ring-osc clock x1 input clock x1 input clock is selected as cpu clock when stop instruction is executed stop mode release stop mode operation stopped (17/f r ) clock switched by software ring-osc clock x1 input clock halt status (oscillation stabilization time set by osts) x1 input clock chapter 15 standby function user?s manual u15836ej5v0ud 306 the stop mode can be released by the following two sources. (a) release by unmasked interrupt request when an unmasked interrupt request is generated, the stop mode is released. after the oscillation stabilization time has elapsed, if interrupt acknowledg ment is enabled, vectored interrupt servicing is carried out. if interrupt acknowledgment is disabled, the next address instruction is executed. figure 15-6. stop mode release by interrupt request generation (1) when x1 input clock is used as cpu clock operating mode operating mode oscillates oscillates stop instruction stop mode wait (set by osts) standby release signal oscillation stabilization wait status oscillation stopped x1 input clock status of cpu oscillation stabilization time (set by osts) (x1 input clock) (x1 input clock) (halt mode status) (2) when ring-osc clo ck is used as cpu clock operating mode operating mode oscillates stop instruction stop mode standby release signal ring-osc clock status of cpu (ring-osc clock) operation stopped (17/f r ) (ring-osc clock) remarks 1. the broken lines indicate the case when the interrupt request that has released the standby mode is acknowledged. 2. f r : ring-osc clock oscillation frequency chapter 15 standby function user?s manual u15836ej5v0ud 307 (b) release by reset input when the reset signal is input, stop mode is released and a reset operation is performed after the oscillation stabilization time has elapsed. figure 15-7. stop mode release by reset input (1) when x1 input clock is used as cpu clock stop instruction reset signal x1 input clock operating mode stop mode reset period operation stopped operating mode oscillates oscillation stopped oscillates status of cpu (x1 input clock) oscillation stabilization time (2 11 /f xp to 2 16 /f xp ) (ring-osc clock) (17/f r ) oscillation stopped (2) when ring-osc clo ck is used as cpu clock stop instruction reset signal ring-osc clock operating mode stop mode reset period operation stopped operating mode oscillates oscillation stopped oscillates status of cpu (ring-osc clock) (17/f r ) (ring-osc clock) remarks 1. f xp : x1 input clock oscillation frequency 2. f r : ring-osc clock oscillation frequency table 15-5. operation in response to interrupt request in stop mode release source mk ? ? user?s manual u15836ej5v0ud 308 chapter 16 reset function the following five operations are available to generate a reset signal. (1) external reset input via reset pin (2) internal reset by watchdog timer program loop detection (3) internal reset by clock monitor x1 input clock oscillation stop detection (4) internal reset by comparison of supply voltage and detection voltage of power-on-clear (poc) circuit (5) internal reset by comparison of supply voltage and detection voltage of low-power-supply detector (lvi) external and internal resets have no functional differences . in both cases, program ex ecution starts at the address at 0000h and 0001h when the reset signal is input. a reset is applied when a low level is input to the reset pin, th e watchdog timer overflow s, x1 clock oscillation stop is detected by the clock monitor, or by poc and lvi circuit voltage detection, and each item of hardware is set to the status shown in table 16-1. each pin is high impedan ce during reset input or during the oscillation stabilization time just after reset release, except for p130, which is low-level output. when a high level is input to the reset pin, the reset is released and progr am execution starts using the ring- osc clock after the cpu clock operation has stopped for 17/f r (s). a reset generated by the watchdog timer and clock monitor sources is automatically released after th e reset, and program executi on starts using the ring-osc clock after the cpu clock operation has stopped for 17/f r (s) (see figures 16-2 to 16-4 ). reset by poc and lvi circuit power supply detection is automatically released when v dd > v poc or v dd > v lvi after the reset, and program execution starts using the ring-osc clock afte r the cpu clock operation has stopped for 17/f r (s) (see chapter 18 power-on-clear circuit and chapter 19 low-voltage detector ). cautions 1. for an external reset, input a low level for 10 chapter 16 reset function user?s manual u15836ej5v0ud 309 figure 16-1. block di agram of reset function clmrf lvirf wdtrf reset control flag register (resf) internal bus watchdog timer reset signal clock monitor reset signal reset power-on-clear circuit reset signal low-voltage detector reset signal reset signal reset signal to lvim/lvis register clear set set clear clear set caution an lvi circuit internal r eset does not reset the lvi circuit. remarks 1. lvim: low-voltage detection register 2. lvis: low-voltage detection level selection register chapter 16 reset function user?s manual u15836ej5v0ud 310 figure 16-2. timing of reset by reset input delay delay hi-z normal operation cpu clock reset period (oscillation stop) operation stop (17/f r ) normal operation (reset processing, ring-osc clock) reset internal reset signal port pin (except p130) x1 input clock ring-osc clock port pin (p130) note note set p130 to high-level output by software. remark when reset is effected, p130 outputs a low level. if p130 is set to output a high level before reset is effected, the output signal of p130 can be du mmy-output as the reset signal to the cpu. figure 16-3. timing of reset du e to watchdog timer overflow hi-z normal operation reset period (oscillation stop) cpu clock watchdog timer overflow internal reset signal port pin (except p130) operation stop (17/f r ) normal operation (reset processing, ring-osc clock) x1 input clock ring-osc clock note port pin (p130) note set p130 to high-level output by software. caution a watchdog timer internal reset resets the watchdog timer. remark when reset is effected, p130 outputs a low level. if p130 is set to output a high level immediately after reset is effected, the output signal of p130 can be dummy-output as the reset signal to the cpu. chapter 16 reset function user?s manual u15836ej5v0ud 311 figure 16-4. timing of reset in stop mode by reset input delay delay hi-z normal operation cpu clock reset period (oscillation stop) reset internal reset signal port pin (except p130) stop instruction execution stop status (oscillation stop) operation stop (17/f r ) normal operation (reset processing, ring-osc clock) x1 input clock ring-osc clock port pin (p130) note note set p130 to high-level output by software. remarks 1. when reset is effected, p130 outputs a low level. if p130 is set to output a high level immediately after reset is effected, the output signal of p130 ca n be dummy-output as the reset signal to the cpu. 2. for the reset timing of the power-on-clear circuit and low-voltage detector, see chapter 18 power-on-clear circuit and chapter 19 low-voltage detector . chapter 16 reset function user?s manual u15836ej5v0ud 312 table 16-1. hardware statuses a fter reset acknowledgment (1/2) hardware status after reset acknowledgment note 1 program counter (pc) the contents of the reset vector table (0000h, 0001h) are set. stack pointer (sp) undefined program status word (psw) 02h data memory undefined note 2 ram general-purpose registers undefined note 2 port registers (p0 to p3, p12, p13) (output latches) 00h (undefined only for p2) port mode registers (pm0, pm1, pm3, pm12) ffh pull-up resistor option registers (pu0, pu1, pu3, pu12) 00h input switch control register (isc) 00h internal memory size switching register (ims) cfh internal expansion ram size sw itching register (ixs) 0ch processor clock control register (pcc) 00h ring-osc mode register (rcm) 00h main clock mode register (mcm) 00h main osc control register (moc) 00h oscillation stabilization time select register (osts) 05h oscillation stabilization time counter status register (ostc) 00h timer counter 00 (tm00) 0000h capture/compare registers 000, 010 (cr000, cr010) 0000h mode control register 00 (tmc00) 00h prescaler mode register 00 (prm00) 00h capture/compare control register 00 (crc00) 00h 16-bit timer/event counter 00 timer output control register 00 (toc00) 00h timer counter 50 (tm50) 00h compare register 50 (cr50) 00h timer clock selection register 50 (tcl50) 00h 8-bit timer/event counter 50 mode control register 50 (tmc50) 00h compare registers 00, 10, 01, 11 (cmp00, cmp10, cmp01, cmp11) 00h 8-bit timer/event counters h0, h1 mode registers (tmhmd0, tmhmd1) 00h mode register (wdtm) 67h watchdog timer enable register (wdte) 9ah conversion result register (adcr) undefined mode register (adm) 00h analog input channel specification register (ads) 00h power-fail comparison mode register (pfm) 00h a/d converter power-fail comparison threshold register (pft) 00h notes 1. during reset input or oscillation stabilization time wa it, only the pc contents among the hardware statuses become undefined. all other hardware statuses remain unchanged after reset. 2. when a reset is executed in the standby mode, the pre-reset status is held even after reset. chapter 16 reset function user?s manual u15836ej5v0ud 313 table 16-1. hardware statuses after reset acknowledgment (2/2) hardware status after reset acknowledgment receive buffer register 0 (rxb0) ffh transmit shift register 0 (txs0) ffh asynchronous serial interface oper ation mode register 0 (asim0) 01h serial interface uart0 note 1 baud rate generator control register 0 (brgc0) 1fh receive buffer register 6 (rxb6) ffh transmit buffer register 6 (txb6) ffh asynchronous serial interface oper ation mode register 6 (asim6) 01h asynchronous serial interface rece ption error status register 6 (asis6) 00h asynchronous serial interface tr ansmission status register 6 (asif6) 00h clock selection register 6 (cksr6) 00h baud rate generator control register 6 (brgc6) ffh serial interface uart6 asynchronous serial interface control register 6 (asicl6) 16h transmit buffer register 10 (sotb10) undefined serial i/o shift regi ster 10 (sio10) 00h serial operation mode register 10 (csim10) 00h serial interface csi10 serial clock selection register 10 (csic10) 00h clock monitor mode register (clm) 00h reset function reset control flag register (resf) 00h note 2 low-voltage detection register (lvim) 00h note 2 low-voltage detector low-voltage detection level selection register (lvis) 00h note 2 request flag registers 0l, 0h, 1l (if0l, if0h, if1l) 00h mask flag registers 0l, 0h, 1l (mk0l, mk0h, mk1l) ffh priority specification flag register s 0l, 0h, 1l (pr0l, pr0h, pr1l) ffh external interrupt rising edge enable register (egp) 00h interrupt external interrupt falling edge enable register (egn) 00h notes 1. pd780102, 780103, and 78f0103 only. 2. these values vary depending on the reset source. reset source register reset input reset by poc reset by wdt reset by clm reset by lvi resf see table 16-2 . lvim lvis cleared (00h) cleared (00h) cleared (00h) cleared (00h) held chapter 16 reset function user?s manual u15836ej5v0ud 314 16.1 register for confirming reset source many internal reset generation sources exist in the 78k0/ kb1. the reset control flag register (resf) is used to store which source has generated the reset request. resf can be read by an 8-bit memory manipulation instruction. reset input, reset input by power-on-clear (poc ) circuit, and reading resf clear resf to 00h. figure 16-5. format of reset control flag register (resf) address: ffach after reset: 00h note r symbol 7 6 5 4 3 2 1 0 resf 0 0 0 wdtrf 0 0 clmrf lvirf wdtrf internal reset request by watchdog timer (wdt) 0 internal reset request is not generated, or resf is cleared. 1 internal reset request is generated. clmrf internal reset req uest by clock monitor (clm) 0 internal reset request is not generated, or resf is cleared. 1 internal reset request is generated. lvirf internal reset request by low-voltage detector (lvi) 0 internal reset request is not generated, or resf is cleared. 1 internal reset request is generated. note the value after reset varies depending on the reset source. caution do not read data via a 1-bi t memory manipulation instruction. the status of resf when a reset request is generated is shown in table 16-2. table 16-2. resf status when reset request is generated reset source flag reset input reset by poc reset by wdt reset by clm reset by lvi wdtrf set (1) held held clmrf held set (1) held lvirf cleared (0) cleared (0) held held set (1) user?s manual u15836ej5v0ud 315 chapter 17 clock monitor 17.1 functions of clock monitor the clock monitor samples the x1 input clock using the on-chip ring-osc, and generates an internal reset signal when the x1 input clock is stopped. when a reset signal is generated by the clock monitor, bit 1 (clmrf) of the reset control flag register (resf) is set to 1. for details of resf, see chapter 16 reset function . the clock monitor automatically stops under the following conditions. ? reset is released and during the oscillation stabilization time ? in stop mode and during the oscillation stabilization time ? when the x1 input clock is stopped by software (msto p = 1) and during the oscillation stabilization time ? when the ring-osc clock is stopped remark mstop: bit 7 of the main osc control register (moc) 17.2 configuration of clock monitor the clock monitor includes the following hardware. table 17-1. configuration of clock monitor item configuration control register clock monitor mode register (clm) figure 17-1. block diag ram of clock monitor operation mode controller x1 input clock ring-osc clock clme clock monitor mode register (clm) internal bus x1 oscillation monitor circuit internal reset signal x1 oscillation control signal (mstop) x1 oscillation stabilization status (ostc overflow) remark mstop: bit 7 of the main osc control register (moc) ostc: oscillation stabilization time counter status register (ostc) chapter 17 clock monitor user?s manual u15836ej5v0ud 316 17.3 register controlling clock monitor the clock monitor is controlled by the clock monitor mode register (clm). (1) clock monitor mode register (clm) this register sets the operation mode of the clock monitor. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 17-2. format of clock monitor mode register (clm) 7 0 clme 0 1 symbol clm address: ffa9h after reset: 00h r/w 6 0 disables clock monitor operation enables clock monitor operation 5 0 4 0 3 0 enables/disables clock monitor operation 2 0 1 0 <0> clme cautions 1. once bit 0 (clme) is set to 1, it cannot be cleared to 0 except by re set input or the internal reset signal. 2. if the reset signal is generated by the clock monitor, clme is cleared to 0 and bit 1 (clmrf) of the reset control flag regi ster (resf) is set to 1. chapter 17 clock monitor user?s manual u15836ej5v0ud 317 17.4 operation of clock monitor this section explains the functions of the clock monitor. the monitor star t and stop conditions are as follows. chapter 17 clock monitor user?s manual u15836ej5v0ud 318 figure 17-3. timing of clock monitor (1/4) (1) when internal reset is executed by oscillation stop of x1 input clock 4 clocks of ring-osc clock x1 input clock ring-osc clock internal reset signal clme clmrf (2) clock monitor status after reset input (clme = 1 is set after reset input and during x1 input clock oscillation stabilization time) cpu operation clock monitor status clme ring-osc clock x1 input clock reset oscillation stopped oscillation stabilization time normal operation clock supply stopped normal operation (ring-osc clock) monitoring monitoring stopped monitoring waiting for end of oscillation stabilization time oscillation stopped 17 clocks set to 1 by software reset reset input clears bit 0 (clme) of the clock monitor mode register (clm) to 0 and stops the clock monitor operation. even if clme is set to 1 by software during the oscillation stabilization time (reset value of osts register is 05h (2 16 /f xp )) of the x1 input clock, monitoring is not performed un til the oscillation stabilizat ion time of the x1 input clock ends. monitoring is automatically started at the end of the oscillation stabilization time. chapter 17 clock monitor user?s manual u15836ej5v0ud 319 figure 17-3. timing of clock monitor (2/4) (3) clock monitor status after reset input (clme = 1 is set after reset input and at the e nd of x1 input clock oscillation stabilization time) cpu operation clock monitor status clme reset ring-osc clock x1 input clock reset oscillation stabilization time normal operation clock supply stopped normal operation (ring-osc clock) monitoring monitoring stopped monitoring 17 clocks set to 1 by software reset input clears bit 0 (clme) of the clock monitor mode register (clm) to 0 and stops the clock monitor operation. when clme is set to 1 by software at the end of the oscillation stabilization time (reset value of osts register is 05h (2 16 /f xp )) of the x1 input clock, monitoring is started. (4) clock monitor status a fter stop mode is released (clme = 1 is set when cpu clock operates on x1 input clock and before entering stop mode) clock monitor status monitoring monitoring stopped monitoring clme ring-osc clock x1 input clock (cpu clock) cpu operation normal operation stop oscillation stabilization time normal operation oscillation stopped oscillation stabilization time (time set by osts register) when bit 0 (clme) of the clock monitor mode register (c lm) is set to 1 before entering stop mode, monitoring automatically starts at the end of the x1 input clock oscillation stabilization time. monitoring is stopped in stop mode and during the oscillation stabilization time. chapter 17 clock monitor user?s manual u15836ej5v0ud 320 figure 17-3. timing of clock monitor (3/4) (5) clock monitor status a fter stop mode is released (clme = 1 is set when cpu clock operates on ri ng-osc clock and before entering stop mode) clock monitor status monitoring monitoring stopped monitoring stopped monitoring clme ring-osc clock (cpu clock) x1 input clock cpu operation normal operation 17 clocks clock supply stopped normal operation oscillation stopped oscillation stabilization time (time set by osts register) stop when bit 0 (clme) of the clock monitor mode register (c lm) is set to 1 before entering stop mode, monitoring automatically starts at the end of the x1 input clock oscillation stabilization time. monitoring is stopped in stop mode and during the oscillation stabilization time. (6) clock monitor status after x1 input clock oscillation is stopped by software clock monitor status clme ring-osc clock mstop x1 input clock oscillation stabilization time (time set by osts register) normal operation (ring-osc clock or subsystem clock note ) monitoring monitoring stopped monitoring cpu operation monitoring stopped oscillation stopped when bit 0 (clme) of the clock monitor mode register (clm) is set to 1 before or while oscillation of the x1 input clock is stopped, monitoring automatical ly starts at the end of the x1 input clock oscillation stabilization time. monitoring is stopped when oscillation of the x1 input clo ck is stopped and during the osc illation stabilization time. chapter 17 clock monitor user?s manual u15836ej5v0ud 321 figure 17-3. timing of clock monitor (4/4) (7) clock monitor status after ring-osc clock oscillation is stopped by software ring-osc clock x1 input clock cpu operation normal operation (x1 input clock or subsystem clock) oscillation stopped rstop note clock monitor status monitoring monitoring stopped monitoring clme when bit 0 (clme) of the clock monitor mode register (clm) is set to 1 before or while oscillation of the ring-osc clock is stopped, monitoring automatically starts afte r the ring-osc clock is stopped. monitoring is stopped when oscillation of the ring-osc clock is stopped. note if it is specified by a mask option that ring-osc cannot be stopped, the setting of bit 0 (rstop) of the ring-osc mode register (rcm) is invalid. to set rsto p, be sure to confirm that bit 1 (mcs) of the main clock mode register (mcm) is 1. user?s manual u15836ej5v0ud 322 chapter 18 power-on-clear circuit 18.1 functions of power-on-clear circuit the power-on-clear circuit (poc) has the following functions. ? ? ? ? ? ? chapter 18 power-on-clear circuit user?s manual u15836ej5v0ud 323 18.2 configuration of power-on-clear circuit a block diagram of the power-on-clear circuit is shown in figure 18-1. figure 18-1. block diagram of power-on-clear circuit ? chapter 18 power-on-clear circuit user?s manual u15836ej5v0ud 324 18.4 cautions for power-on-clear circuit in a system where the supply voltage (v dd ) fluctuates for a certain period in the vicinity of the poc detection voltage (v poc ), the system may be repeatedly reset and released from the reset status. in this case, the time from release of reset to the start of the oper ation of the microcontroller can be arbitrarily set by taking the following action. chapter 18 power-on-clear circuit user?s manual u15836ej5v0ud 325 figure 18-3. example of software pr ocessing after release of reset (2/2) ? user?s manual u15836ej5v0ud 326 chapter 19 low-voltage detector 19.1 functions of low-voltage detector the low-voltage detector (lvi) has following functions. ? compares supply voltage (v dd ) and detection voltage (v lvi ), and generates an internal interrupt signal or internal reset signal when v dd < v lvi . ? detection levels note of supply voltage can be changed by software. ? interrupt or reset function can be selected by software. ? operable in stop mode. note detection levels of supply voltage differ as follows. expanded-specification produc t of standard products and (a) grade products: 8 levels conventional product of standard products and (a) grade products: 7 levels (a1) grade products and (a2) grade products: 5 levels when the low-voltage detector is used to reset, bit 0 (lvirf) of the reset control flag register (resf) is set to 1 if reset occurs. for details of resf, see chapter 16 reset function . chapter 19 low-voltage detector user?s manual u15836ej5v0ud 327 19.2 configuration of low-voltage detector a block diagram of the low-voltage detector is shown below. figure 19-1. block diagram of low-voltage detector lvis1 lvis0 lvion lvie ? ? ? chapter 19 low-voltage detector user?s manual u15836ej5v0ud 328 (1) low-voltage detection register (lvim) this register sets low-voltag e detection and the operation mode. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears lvim to 00h. figure 19-2. format of low-volta ge detection register (lvim) <0> lvif <1> lvimd 2 0 3 0 <4> lvie 5 0 6 0 <7> lvion symbol lvim address: ffbeh after reset: 00h r/w note 1 lvion notes 2, 3 enables low-voltage detection operation 0 disables operation 1 enables operation lvie notes 2, 4, 5 specifies reference voltage generator 0 disables operation 1 enables operation lvimd note 2 low-voltage detection operation mode selection 0 generates interrupt signal when supply voltage (v dd ) < detection voltage (v lvi ) 1 generates internal reset signal when supply voltage (v dd ) < detection voltage (v lvi ) lvif note 6 low-voltage detection flag 0 supply voltage (v dd ) > detection voltage (v lvi ), or when operation is disabled 1 supply voltage (v dd ) < detection voltage (v lvi ) notes 1. bit 0 is read-only. 2. lvion, lvie, and lvimd are cleared to 0 in the case of a reset other than an lvi reset. these are not cleared to 0 in the case of an lvi reset. 3. when lvion is set to 1, operation of the com parator in the lvi circuit is started. use software to instigate a wait of at least 0.2 ms from when lvion is set to 1 until the voltage is confirmed at lvif. 4. if ?poc cannot be used? is selected by a mask opti on, wait for 2 ms or more by software from when lvie is set to 1 until lvion is set to 1. 5. if ?poc used? is selected by a mask option, se tting of lvie is invalid because the reference voltage generator in the lvi circuit always operates. 6. the value of lvif is output as the interru pt request signal intlvi when lvion = 1 and lvimd = 0. caution to stop lvi, follow either of the procedures below. ? when using 8-bit memory manipulation instruction: write 00h to lvim. ? when using 1-bit memory manipulation instru ction: clear lvion to 0 first and then clear lvie to 0. chapter 19 low-voltage detector user?s manual u15836ej5v0ud 329 (2) low-voltage detection level selection register (lvis) this register selects the low-voltage detection level. this register can be set by an 8-bit memory manipulation instruction. reset input clears lvis to 00h. figure 19-3. format of low-voltage dete ction level selection register (lvis) 0 lvis0 1 lvis1 2 lvis2 3 0 4 0 5 0 6 0 7 0 symbol lvis address: ffbfh after reset: 00h r/w lvis2 lvis1 lvis0 detection level 0 0 0 v lvi0 (4.3 v 0.2 v) 0 0 1 v lvi1 (4.1 v 0.2 v) 0 1 0 v lvi2 (3.9 v 0.2 v) 0 1 1 v lvi3 (3.7 v 0.2 v) 1 0 0 v lvi4 (3.5 v 0.2 v) note 1 1 0 1 v lvi5 (3.3 v 0.15 v) notes 1, 2 1 1 0 v lvi6 (3.1 v 0.15 v) notes 1, 2 1 1 1 v lvi7 (2.85 v 0.15 v) notes 1, 3, 4 notes 1. when the detection voltage of the poc circuit is specified as v poc = 3.5 v 0.2 v by a mask option, do not select v lvi4 to v lvi7 as the lvi detection voltage. even if v lvi4 to v lvi7 are selected, the poc circuit has priority. 2. this can be set only with the expanded-specific ation products and conventional products of standard products and (a) grade products. 3. when the detection voltage of the poc circuit is specified as v poc = 2.85 v 0.15 v by a mask option, do not select v lvi7 as the lvi detection voltage. even if v lvi7 is selected, the poc circuit has priority. 4. this can be set only with the expanded-specific ation products of standard products and (a) grade products. caution be sure to clear bits 3 to 7 to 0. chapter 19 low-voltage detector user?s manual u15836ej5v0ud 330 19.4 operation of low-voltage detector the low-voltage detector can be us ed in the following two modes. ? used as reset compares the supply voltage (v dd ) and detection voltage (v lvi ), and generates an internal reset signal when v dd < v lvi . ? used as interrupt compares the supply voltage (v dd ) and detection voltage (v lvi ), and generates an interrupt signal (intlvi) when v dd < v lvi . the operation is set as follows. (1) when used as reset ? when starting operation <1> mask the lvi interrupt (lvimk = 1). <2> set the detection voltage using bits 2 to 0 (lvis2 to lvis0) of the low-voltage detection level selection register (lvis). <3> set bit 4 (lvie) of the low-voltage detection regist er (lvim) to 1 (enables reference voltage generator operation). <4> use software to instigate a wait of at least 2 ms. <5> set bit 7 (lvion) of lvim to 1 (enables lvi operation). <6> use software to instigate a wait of at least 0.2 ms. <7> wait until it is checked that (supply voltage (v dd ) > detection voltage (v lvi )) by bit 0 (lvif) of lvim. <8> set bit 1 (lvimd) of lvim to 1 (generates internal reset signal when supply voltage (v dd ) < detection voltage (v lvi )). figure 19-4 shows the timing of the internal reset signal generated by the low-voltage detector. the numbers in this timing chart correspond to <1> to <8> above. cautions 1. <1> must always be executed. when lvimk = 0, an interrupt may occur immediately after the processing in <5>. 2. if ?poc used? is selected by a mask opt ion, procedures <3> and <4> are not required. 3. if supply voltage (v dd ) > detection voltage (v lvi ) when lvim is set to 1, an internal reset signal is not generated. ? when stopping operation either of the following pr ocedures must be executed. ? when using 8-bit memory manipulation instruction: write 00h to lvim. ? when using 1-bit memory manipulation instruction: clear lvimd to 0, lvion to 0, and lvie to 0 in that order. chapter 19 low-voltage detector user?s manual u15836ej5v0ud 331 figure 19-4. timing of low-voltage dete ctor internal reset signal generation supply voltage (v dd ) lvi detection voltage (v lvi ) poc detection voltage (v poc ) h lvif flag lvirf flag note 3 note 2 lvi reset signal poc reset signal internal reset signal cleared by software not cleared not cleared not cleared not cleared not cleared not cleared cleared by software <2> <1> note 1 <5> <7> <8> time clear clear clear clear <3> <4> 2 ms or longer <6> 0.2 ms or longer lvimk flag (set by software) lvie flag (set by software) lvion flag (set by software) lvimd flag (set by software) notes 1. the lvimk flag is set to ?1? by reset input. 2. the lvif flag may be set (1). 3. lvirf is bit 0 of the reset control flag register (resf). for details of resf, see chapter 16 reset function . remark <1> to <8> in figure 19-4 above correspond to <1> to <8> in the description of ?when starting operation? in 19.4 (1) when used as reset . chapter 19 low-voltage detector user?s manual u15836ej5v0ud 332 (2) when used as interrupt ? when starting operation <1> mask the lvi interrupt (lvimk = 1). <2> set the detection voltage using bits 2 to 0 (lvis2 to lvis0) of the low-voltage detection level selection register (lvis). <3> set bit 4 (lvie) of the low-voltage detection regist er (lvim) to 1 (enables reference voltage generator operation). <4> use software to instigate a wait of at least 2 ms. <5> set bit 7 (lvion) of lvim to 1 (enables lvi operation). <6> use software to instigate a wait of at least 0.2 ms. <7> wait until it is checked that (supply voltage (v dd ) > detection voltage (v lvi )) by bit 0 (lvif) of lvim. <8> clear the interrupt request flag of lvi (lviif) to 0. <9> release the interrupt mask flag of lvi (lvimk). <10> execute the ei instruction (w hen vectored interrupts are used). figure 19-5 shows the timing of the interrupt signal ge nerated by the low-voltage detector. the numbers in this timing chart correspond to <1> to <9> above. caution if ?poc used? is selected by a mask option, procedures <3> a nd <4> are not required. ? when stopping operation either of the following pr ocedures must be executed. ? when using 8-bit memory manipulation instruction: write 00h to lvim. ? when using 1-bit memory manipulation instruction: clear lvion to 0 first, and then clear lvie to 0. chapter 19 low-voltage detector user?s manual u15836ej5v0ud 333 figure 19-5. timing of low-voltage detector interrupt signal generation supply voltage (v dd ) lvi detection voltage (v lvi ) poc detection voltage (v poc ) time lvif flag intlvi lviif flag internal reset signal <2> <1> note 1 <5> <7> <8> cleared by software <3> <4> 2 ms or longer <9> cleared by software <6> 0.2 ms or longer lvimk flag (set by software) lvie flag (set by software) lvion flag (set by software) note 2 note 2 notes 1. the lvimk flag is set to ?1? by reset input. 2. the lvif and lviif flags may be set (1). remark <1> to <9> in figure 19-5 above correspond to <1> to <9> in the description of ?when starting operation? in 19.4 (2) when used as interrupt . chapter 19 low-voltage detector user?s manual u15836ej5v0ud 334 19.5 cautions for low-voltage detector in a system where the supply voltage (v dd ) fluctuates for a certain period in t he vicinity of the lvi detection voltage (v lvi ), the operation is as follows depending on how the low-voltage detector is used. (1) when used as reset the system may be repeatedly reset and released from the reset status. in this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking action (a) below. (2) when used as interrupt interrupt requests may be frequently generated. take action (b) below. in this system, take the following actions. chapter 19 low-voltage detector user?s manual u15836ej5v0ud 335 figure 19-6. example of software pr ocessing after release of reset (1/2) ? chapter 19 low-voltage detector user?s manual u15836ej5v0ud 336 figure 19-6. example of software pr ocessing after release of reset (2/2) ? user?s manual u15836ej5v0ud 337 chapter 20 mask options mask rom versions are provided with the following mask options. 1. power-on-clear (poc) circuit ? ? ? ? ? user?s manual u15836ej5v0ud 338 chapter 21 chapter 21 chapter 21 ? chapter 21 pd78f0103 user?s manual u15836ej5v0ud 341 table 21-3. wiring between pd78f0103 and dedicated flash programmer (2/2) (2) uart (uart0, uart6) pin configuration of dedicated flash progra mmer with uart0 with uart0+hs with uart6 signal name i/o pin function pin name pin no. pin name pin no. pin name pin no. si/rxd input receive signal txd0/ sck10/p10 15 txd0/ sck10/p10 15 txd6/p13 18 so/txd output transmit signal rxd0/si10/ p11 16 rxd0/si10/ p11 16 rxd6/p14 19 sck output transfer clock not needed not needed not needed not needed not needed not needed x1 8 x1 8 x1 8 clk output clock to pd78f0103 x2 note 9 x2 note 9 x2 note 9 /reset output reset signal reset 10 reset 10 reset 10 v pp output write voltage v pp 5 v pp 5 v pp 5 h/s input handshake signal not needed not needed hs/p15/toh0 20 not needed not needed v dd 7 v dd 7 v dd 7 v dd i/o v dd voltage generation/voltage monitor av ref 28 av ref 28 av ref 28 v ss 6 v ss 6 v ss 6 gnd ? ground av ss 29 av ss 29 av ss 29 note when using the clock out of the flash programmer, c onnect clk of the programmer to x1, and connect its inverse signal to x2. chapter 21 chapter 21 chapter 21 chapter 21 chapter 21 chapter 21 chapter 21 chapter 21 chapter 21 pd78f0103 user?s manual u15836ej5v0ud 350 if flashpro iii/flashpro iv is used as the dedicated flas h programmer, flashpro iii/flashpro iv generates the following signal for the pd78f0103. for details, refer to t he flashpro iii/flashpro iv manual. table 21-4. pin connection flashpro iii/flashpro iv pd78f0103 connection signal name i/o pin function pin name csi10 uart0 uart6 v pp output write voltage v pp v dd i/o v dd voltage generation/voltage monitor v dd , av ref gnd ? ground v ss , av ss clk output clock output to pd78f0103 x1, x2 note { { { /reset output reset signal reset si/rxd input receive signal so10/txd0/txd6 so/txd output transmit signal si10/rxd0/rxd6 sck output transfer clock sck10 h/s input handshake signal hs note when using the clock out of the flash programmer, co nnect clk of the programmer to x1, and connect its inverse signal to x2. remark : be sure to connect the pin. { : the pin does not have to be connected if the signal is generated on the target board. : the pin does not have to be connected. : in handshake mode chapter 21 pd78f0103 user?s manual u15836ej5v0ud 351 21.5 handling of pins on board to write the flash memory on-board, connectors that connect the dedicated flash programmer must be provided on the target system. first provide a function that select s the normal operation mode or flash memory programming mode on the board. when the flash memory programming mode is set, all the pins not used for programming the flash memory are in the same status as immediately after re set. therefore, if the external device does not recognize the state immediately after reset, the pins must be handled as described below. 21.5.1 v pp pin in the normal operation mode, connect the v pp pin to v ss . in addition, a write voltage of 10.0 v (typ.) is supplied to the v pp pin in the flash memory programming mode. perform the following pin handling. (1) connect pull-down resistor r vpp = 10 k ? to the v pp pin. (2) switch the input of the v pp pin to the programmer side by using a ju mper on the board or to gnd directly. figure 21-13. example of connection of v pp pin pd78f0103 v pp dedicated flash programmer connection pin pull-down resistor (r vpp ) 21.5.2 serial interface pins the pins used by each serial interface are listed below. table 21-5. pins used by each serial interface serial interface pins used csi10 so10, si10, sck10 csi10 + hs so10, si10, sck10, hs/p15 uart0 txd0, rxd0 uart0 + hs txd0, rxd0, hs/p15 uart6 txd6, rxd6 to connect the dedicated flash programmer to the pins of a serial interface that is co nnected to another device on the board, care must be exercised so that signals do not collide or that the other device does not malfunction. chapter 21 chapter 21 chapter 21 chapter 21 chapter 21 user?s manual u15836ej5v0ud 357 chapter 22 instruction set this chapter lists each instruction set of the 78k0/kb1 in table form. for details of each operation and operation code, refer to the separate document 78k/0 series instructions user?s manual (u12326e) . 22.1 conventions used in operation list 22.1.1 operand identifier s and specification methods operands are written in the ?operand? column of each instruction in accordan ce with the specification method of the instruction operand identifier (refer to the assembler s pecifications for details). when there are two or more methods, select one of them. uppercase letters and the sym bols #, !, $ and [ ] are keywords and must be written as they are. each symbol has the following meaning. ? ? ? ? chapter 22 instruction set user?s manual u15836ej5v0ud 358 22.1.2 description of operation column a: a register; 8-bit accumulator x: x register b: b register c: c register d: d register e: e register h: h register l: l register ax: ax register pair; 16-bit accumulator bc: bc register pair de: de register pair hl: hl register pair pc: program counter sp: stack pointer psw: program status word cy: carry flag ac: auxiliary carry flag z: zero flag rbs: register bank select flag ie: interrupt request enable flag ( ): memory contents indicated by addre ss or register contents in parentheses x h , x l : higher 8 bits and lower 8 bits of 16-bit register ?? chapter 22 instruction set user?s manual u15836ej5v0ud 359 22.2 operation list clocks flag instruction group mnemonic operands bytes note 1 note 2 operation zaccy r, #byte 2 4 ? r byte saddr, #byte 3 6 7 (saddr) byte sfr, #byte 3 ? 7 sfr byte a, r note 3 1 2 ? a r r, a note 3 1 2 ? r a a, saddr 2 4 5 a (saddr) saddr, a 2 4 5 (saddr) a a, sfr 2 ? 5 a sfr sfr, a 2 ? 5 sfr a a, !addr16 3 8 9 a (addr16) !addr16, a 3 8 9 (addr16) a psw, #byte 3 ? 7 psw byte a, psw 2 ? 5 a psw psw, a 2 ? 5 psw a a, [de] 1 4 5 a (de) [de], a 1 4 5 (de) a a, [hl] 1 4 5 a (hl) [hl], a 1 4 5 (hl) a a, [hl + byte] 2 8 9 a (hl + byte) [hl + byte], a 2 8 9 (hl + byte) a a, [hl + b] 1 6 7 a (hl + b) [hl + b], a 1 6 7 (hl + b) a a, [hl + c] 1 6 7 a (hl + c) mov [hl + c], a 1 6 7 (hl + c) a a, r note 3 1 2 ? a ? r a, saddr 2 4 6 a ? (saddr) a, sfr 2 ? 6 a ? sfr a, !addr16 3 8 10 a ? (addr16) a, [de] 1 4 6 a ? (de) a, [hl] 1 4 6 a ? (hl) a, [hl + byte] 2 8 10 a ? (hl + byte) a, [hl + b] 2 8 10 a ? (hl + b) 8-bit data transfer xch a, [hl + c] 2 8 10 a ? (hl + c) notes 1. when the internal high-speed ram area is acce ssed or for an instruction with no data access 2. when an area except the internal high-speed ram area is accessed 3. except ?r = a? remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to the internal rom program. chapter 22 instruction set user?s manual u15836ej5v0ud 360 clocks flag instruction group mnemonic operands bytes note 1 note 2 operation zaccy rp, #word 3 6 ? ? ? ? ? ? ? ? ? ? ? ? ? ? chapter 22 instruction set user?s manual u15836ej5v0ud 361 clocks flag instruction group mnemonic operands bytes note 1 note 2 operation zaccy a, #byte 2 4 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? chapter 22 instruction set user?s manual u15836ej5v0ud 362 clocks flag instruction group mnemonic operands bytes note 1 note 2 operation zaccy a, #byte 2 4 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? chapter 22 instruction set user?s manual u15836ej5v0ud 363 clocks flag instruction group mnemonic operands bytes note 1 note 2 operation zaccy addw ax, #word 3 6 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? chapter 22 instruction set user?s manual u15836ej5v0ud 364 clocks flag instruction group mnemonic operands bytes note 1 note 2 operation zaccy cy, saddr.bit 3 6 7 cy ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? chapter 22 instruction set user?s manual u15836ej5v0ud 365 clocks flag instruction group mnemonic operands bytes note 1 note 2 operation zaccy call !addr16 3 7 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? chapter 22 instruction set user?s manual u15836ej5v0ud 366 clocks flag instruction group mnemonic operands bytes note 1 note 2 operation zaccy saddr.bit, $addr16 3 8 9 pc ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? chapter 22 instruction set user?s manual u15836ej5v0ud 367 22.3 instructions listed by addressing type (1) 8-bit instructions mov, xch, add, addc, sub, subc, and, or, xor, cmp, mulu, divuw, inc, dec, ror, rol, rorc, rolc, ror4, rol4, push, pop, dbnz second operand first operand #byte a r note sfr saddr !addr16 psw [de] [hl] [hl + byte] [hl + b] [hl + c] $addr16 1 none a add addc sub subc and or xor cmp mov xch add addc sub subc and or xor cmp mov xch mov xch add addc sub subc and or xor cmp mov xch add addc sub subc and or xor cmp mov mov xch mov xch add addc sub subc and or xor cmp mov xch add addc sub subc and or xor cmp ror rol rorc rolc r mov mov add addc sub subc and or xor cmp inc dec b, c dbnz sfr mov mov saddr mov add addc sub subc and or xor cmp mov dbnz inc dec !addr16 mov psw mov mov push pop [de] mov [hl] mov ror4 rol4 [hl + byte] [hl + b] [hl + c] mov x mulu c divuw note except r = a chapter 22 instruction set user?s manual u15836ej5v0ud 368 (2) 16-bit instructions movw, xchw, addw, subw, cmpw, push, pop, incw, decw second operand first operand #word ax rp note sfrp saddrp !addr16 sp none ax addw subw cmpw movw xchw movw movw movw movw rp movw movw note incw decw push pop sfrp movw movw saddrp movw movw !addr16 movw sp movw movw note only when rp = bc, de, hl (3) bit manipulation instructions mov1, and1, or1, xor1, set1, clr1, not1, bt, bf, btclr second operand first operand a.bit sfr.bit saddr.bit psw.bit [hl].bit cy $addr16 none a.bit mov1 bt bf btclr set1 clr1 sfr.bit mov1 bt bf btclr set1 clr1 saddr.bit mov1 bt bf btclr set1 clr1 psw.bit mov1 bt bf btclr set1 clr1 [hl].bit mov1 bt bf btclr set1 clr1 cy mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 set1 clr1 not1 chapter 22 instruction set user?s manual u15836ej5v0ud 369 (4) call instructions/branch instructions call, callf, callt, br, bc, bnc, bz, bnz, bt, bf, btclr, dbnz second operand first operand ax !addr16 !addr11 [addr5] $addr16 basic instruction br call br callf callt br bc bnc bz bnz compound instruction bt bf btclr dbnz (5) other instructions adjba, adjbs, brk, ret, reti, retb, sel, nop, ei, di, halt, stop user?s manual u15836ej5v0ud 370 chapter 23 electrical specifications (standard products, (a) grade products) (expanded-specification products) target products (expanded-specificat ion products): products with a rank note e or after ? pd780101, 780102, 780103, 780101(a), 780102(a), and 780 103(a) for which orders were received on or after mid-march, 2004 ? pd78f0103 and 78f0103(a) for which orders were received on or after mid-july, 2004 note the rank is indicated by the 5th digit from the le ft in the 3rd column (lot number) marked on the package. lot number year code week code rank absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit v dd ? 0.3 to +6.5 v v ss ? 0.3 to +0.3 v av ref ? 0.3 to v dd + 0.3 note 1 v av ss ? 0.3 to +0.3 v supply voltage v pp pd78f0103, 78f0103(a) only note 2 ? 0.3 to +10.5 v v i1 p00 to p03, p10 to p17, p20 to p23, p30 to p33, p120, x1, x2, reset ? 0.3 to v dd + 0.3 note 1 v input voltage v i2 v pp in flash programming mode ( pd78f0103, 78f0103(a) only) ? 0.3 to +10.5 v output voltage v o ? 0.3 to v dd + 0.3 note 1 v analog input voltage v an av ss ? 0.3 to av ref + 0.3 note 1 and ? 0.3 to v dd + 0.3 note 1 v per pin ? 10 ma p30 to p33, p120 ? 30 ma total of pins p00 to p03, p10 to p17, p130 ? 30 ma output current, high i oh total of all pins ? 50 ma per pin 20 ma p30 to p33, p120 35 ma total of pins p00 to p03, p10 to p17, p130 35 ma output current, low i ol total of all pins 60 ma in normal operation mode ? 40 to +85 operating ambient temperature t a in flash memory programming ? 10 to +85 c pd780101, 780102, 780103, 780101(a), 780102(a), 780103(a) ? 65 to +150 storage temperature t stg pd78f0103, 78f0103(a) ? 40 to +125 c note 1. must be 6.5 v or lower. (refer to note 2 on the next page.) chapter 23 electrical specifications (standard products, (a) grade products) (expanded-specification products) user?s manual u15836ej5v0ud 371 note 2. make sure that the following conditions of the v pp voltage application timing are satisfied when the flash memory is written. ? when supply voltage rises v pp must exceed v dd 10 s or more after v dd has reached the lower-limit value (2.5 v) of the operating voltage range (see a in the figure below). ? when supply voltage drops v dd must be lowered 10 s or more after v pp falls below the lower-limit value (2.5 v) of the operating voltage range of v dd (see b in the figure below). 2.5 v v dd 0 v 0 v v pp 2.5 v a b caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute m aximum ratings are not exceeded. remark unless specified otherwise, the characteristics of alter nate-function pins are the same as those of port pins. chapter 23 electrical specifications (standard products, (a) grade products) (expanded-specification products) user?s manual u15836ej5v0ud 372 x1 oscillator characteristics (t a = ? 40 to +85 c, 2.5 v v dd 5.5 v, 2.5 v av ref v dd , v ss = av ss = 0 v) resonator recommended circuit parameter conditions min. typ. max. unit 4.0 v v dd 5.5 v 2.0 12 3.5 v v dd < 4.0 v 2.0 10 3.0 v v dd < 3.5 v 2.0 8.38 ceramic resonator c1 x2 x1 v ss c2 oscillation frequency (f xp ) note 2.5 v v dd < 3.0 v 2.0 5.0 mhz 4.0 v v dd 5.5 v 2.0 12 3.5 v v dd < 4.0 v 2.0 10 3.0 v v dd < 3.5 v 2.0 8.38 crystal resonator c1 x2 x1 v ss c2 oscillation frequency (f xp ) note 2.5 v v dd < 3.0 v 2.0 5.0 mhz 4.0 v v dd 5.5 v 2.0 12 3.5 v v dd < 4.0 v 2.0 10 3.0 v v dd < 3.5 v 2.0 8.38 x1 input frequency (f xp ) note 2.5 v v dd < 3.0 v 2.0 5.0 mhz 4.0 v v dd 5.5 v 38 500 3.5 v v dd < 4.0 v 46 500 3.0 v v dd < 3.5 v 56 500 external clock x2 x1 x1 input high-/low- level width (t xph , t xpl ) 2.5 v v dd < 3.0 v 96 500 ns note indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. cautions 1. when using the x1 oscillator, wire as follo ws in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. ? keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line th rough which a high fluctuating current flows. always make the ground point of the osci llator capacitor the same potential as v ss . do not ground the capacitor to a ground pa ttern through which a high current flows. do not fetch signals from the oscillator. 2. since the cpu is started by the ring-osc after reset is released, check th e oscillation stabilization time of the x1 input clock using th e oscillation stabilization time counter status register (ostc). determine the o scillation stabilization time of the ostc register and oscillation stabilization time select register (osts) after sufficiently evaluating the oscillation stabilization time with the resonator to be used. ring-osc oscillator characteristics (t a = ? 40 to +85 c, 2.5 v v dd 5.5 v, 2.5 v av ref v dd , v ss = av ss = 0 v) resonator parameter conditions min. typ. max. unit on-chip ring-osc oscillator oscillation frequency (f r ) 120 240 480 khz chapter 23 electrical specifications (standard products, (a) grade products) (expanded-specification products) user?s manual u15836ej5v0ud 373 recommended oscillator constants caution for the resonator selection of the ? chapter 23 electrical specifications (standard products, (a) grade products) (expanded-specification products) user?s manual u15836ej5v0ud 374 (b) pd78f0103 x1 oscillation: ceramic resonator (t a = ? 40 to +85 c) recommended circuit constants oscillation voltage range manufacturer part number smd/lead frequency (mhz) c1 (pf) c2 (pf) min. (v) max. (v) cstcc2m00g56-r0 smd 2.00 internal (47) internal (47) cstcc2m45g56-r0 smd 2.457 internal (47) internal (47) cstcr4m00g53-r0 cstcr4m00g53093-r0 smd internal (15) internal (15) cstls4m00g53-b0 cstls4m00g53093-b0 lead 4.00 internal (15) internal (15) cstcr5m00g53-r0 cstcr5m00g53093-r0 smd internal (15) internal (15) cstls5m00g53-b0 cstls5m00g53093-b0 lead 5.00 internal (15) internal (15) cstcr6m00g53-r0 cstcr6m00g53u-r0 smd internal (15) internal (15) cstls6m00g53-b0 cstls6m00g53u-b0 lead 6.00 internal (15) internal (15) cstce8m38g52-r0 smd internal (10) internal (10) cstls8m38g53-b0 cstls8m38g53093-b0 lead 8.388 internal (15) internal (15) cstce10m0g52-r0 smd internal (10) internal (10) cstls10m0g53-b0 cstls10m0g53093-b0 lead 10.0 internal (15) internal (15) murata mfg. cstce12m0g52-r0 smd 12.0 internal (10) internal (10) 2.5 5.5 caution the oscillator constants shown above are reference values based on evaluation in a specific environment by the resonator ma nufacturer. if it is necess ary to optimize the oscillator characteristics in the actual app lication, apply to the resonato r manufacturer for evaluation on the implementation circuit. the oscillation vo ltage and oscillation frequency only indicate the oscillator characteristic. use th e 78k0/kb1 so that the internal operation conditions are within the specifications of the dc and ac characteristics. chapter 23 electrical specifications (standard products, (a) grade products) (expanded-specification products) user?s manual u15836ej5v0ud 375 (c) ? chapter 23 electrical specifications (standard products, (a) grade products) (expanded-specification products) user?s manual u15836ej5v0ud 376 dc characteristics (t a = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? chapter 23 electrical specifications (standard products, (a) grade products) (expanded-specification products) user?s manual u15836ej5v0ud 377 dc characteristics (t a = ? ? ? ? ? chapter 23 electrical specifications (standard products, (a) grade products) (expanded-specification products) user?s manual u15836ej5v0ud 378 dc characteristics (3/4): ? chapter 23 electrical specifications (standard products, (a) grade products) (expanded-specification products) user?s manual u15836ej5v0ud 379 dc characteristics (4/4): ? chapter 23 electrical specifications (standard products, (a) grade products) (expanded-specification products) user?s manual u15836ej5v0ud 380 ac characteristics (1) basic operation (t a = ? 2.7 v note selection of f sam = f xp , f xp /4, f xp /256 is possible using bits 0 and 1 (prm000, prm001) of prescaler mode register 00 (prm00). note that when selectin g the ti000 valid edge as the count clock, f sam = f xp. t cy vs. v dd (x1 input clock operation) 5.0 1.0 2.0 0.4 0.2 0.1 supply voltage v dd [v] cycle time t cy [ s] 0 10.0 1.0 2.0 3.0 4.0 5.0 6.0 5.5 20.0 16.0 0.238 0.166 3.5 2.5 chapter 23 electrical specifications (standard products, (a) grade products) (expanded-specification products) user?s manual u15836ej5v0ud 381 (2) serial interface (t a = ? ? ? chapter 23 electrical specifications (standard products, (a) grade products) (expanded-specification products) user?s manual u15836ej5v0ud 382 ac timing test points (excluding x1 input) 0.8v dd 0.2v dd test points 0.8v dd 0.2v dd clock timing x1 input v ih4 (min.) v il4 (max.) 1/f xp t xl t xh ti timing ti000, ti010 t til0 t tih0 ti50 1/f ti5 t til5 t tih5 interrupt request input timing intp0 to intp5 t intl t inth reset input timing reset t rsl chapter 23 electrical specifications (standard products, (a) grade products) (expanded-specification products) user?s manual u15836ej5v0ud 383 serial transfer timing 3-wire serial i/o mode: si10 so10 t kcym t klm t khm t sikm t ksim input data t ksom output data sck10 remark m = 1, 2 a/d converter characteristics (t a = ? chapter 23 electrical specifications (standard products, (a) grade products) (expanded-specification products) user?s manual u15836ej5v0ud 384 poc circuit characteristics (t a = ? 40 to +85 c) parameter symbol conditions min. typ. max. unit v poc0 mask option = 3.5 v note 1 3.3 3.5 3.7 v detection voltage v poc1 mask option = 2.85 v note 2 2.7 2.85 3.0 v v dd : 0 v 2.7 v 0.0015 ms power supply rise time t pth v dd : 0 v 3.3 v 0.002 ms response delay time 1 note 3 t pthd when power supply rises, after reaching detection voltage (max.) 3.0 ms response delay time 2 note 4 t pd when v dd falls 1.0 ms minimum pulse width t pw 0.2 ms notes 1. when flash memory version pd78f0103m5, 78f0103m6, 78f0103m5( a), or 78f0103m6(a) is used 2. when flash memory version pd78f0103m3, 78f0103m4, 78f0103m3( a), or 78f0103m4(a) is used 3. time required from voltage detection to reset release. 4. time required from voltage detection to internal reset output. poc circuit timing supply voltage (v dd ) time detection voltage (min.) detection voltage (typ.) detection voltage (max.) t pth t pthd t pw t pd chapter 23 electrical specifications (standard products, (a) grade products) (expanded-specification products) user?s manual u15836ej5v0ud 385 lvi circuit characteristics (t a = ? 40 to +85 c) parameter symbol conditions min. typ. max. unit v lvi0 4.1 4.3 4.5 v v lvi1 3.9 4.1 4.3 v v lvi2 3.7 3.9 4.1 v v lvi3 3.5 3.7 3.9 v v lvi4 3.3 3.5 3.7 v v lvi5 3.15 3.3 3.45 v v lvi6 2.95 3.1 3.25 v detection voltage v lvi7 2.7 2.85 3.0 v response time note 1 t ld 0.2 2.0 ms minimum pulse width t lw 0.2 ms reference voltage stabilization wait time note 2 t lwait0 0.5 2.0 ms operation stabilization wait time note 3 t lwait1 0.1 0.2 ms notes 1. time required from voltage detection to interrupt output or internal reset output. 2. time required from setting lvie to 1 to reference voltage stabilization when poc-off is selected by mask option (for the flash memory version, when the pd78f0103m1, 78f0103m2, 78f0103m1(a), or 78f0103m2(a) is used). 3. time required from setting lvion to 1 to operation stabilization. remarks 1. v lvi0 > v lvi1 > v lvi2 > v lvi3 > v lvi4 > v lvi5 > v lvi6 > v lvi7 2. v pocn < v lvim (n = 0 or 1, m = 0 to 7) lvi circuit timing supply voltage (v dd ) time detection voltage (min.) detection voltage (typ.) detection voltage (max.) t lwait0 t lw t ld t lwait1 lvie 1 lvion 1 data memory stop mode low supply vo ltage data retention characteristics (t a = ? 40 to +85 c) parameter symbol conditions min. typ. max. unit data retention supply voltage v dddr when poc-off is selected by mask option note 1.6 5.5 v release signal set time t srel 0 s note when flash memory version pd78f0103m1, 78f0103m2, 78f0103m1( a), or 78f0103m2(a) is used chapter 23 electrical specifications (standard products, (a) grade products) (expanded-specification products) user?s manual u15836ej5v0ud 386 flash memory programming characteristics: pd78f0103, 78f0103(a) (t a = +10 to +60 c, 2.7 v v dd 5.5 v, 2.7 v av ref v dd , v ss = av ss = 0 v) (1) write erase characteristics parameter symbol conditions min. typ. max. unit v pp supply voltage v pp2 during flash memory programming 9.7 10.0 10.3 v v dd supply current i dd when v pp = v pp2 , f xp = 10 mhz, v dd = 5.5 v 37 ma v pp supply current i pp v pp = v pp2 100 ma step erase time note 1 t er 0.199 0.2 0.201 s overall erase time note 2 t era when step erase time = 0.2 s 20 s/chip writeback time note 3 t wb 49.4 50 50.6 ms number of writebacks per 1 writeback command note 4 c wb when writeback time = 50 ms 60 times number of erases/writebacks c erwb 16 times step write time note 5 t wr 48 50 52 s overall write time per word note 6 t wrw when step write time = 50 s (1 word = 1 byte) 48 520 s number of rewrites per chip note 7 c erwr 1 erase + 1 write after erase = 1 rewrite 20 times/ area notes 1. the recommended setting value of the step erase time is 0.2 s. 2. the prewrite time before erasure and the erase verify time (writeback time) are not included. 3. the recommended setting value of the writeback time is 50 ms. 4. writeback is executed once by the issu ance of the writeback command. therefore, the number of retries must be the maximum value minus the number of commands issued. 5. the recommended setting value of the step write time is 50 s. 6. the actual write time per word is 100 s longer. the internal verify time during or after a write is not included. 7. when a product is first written after shipment, ?erase write? and ?write only? are both taken as one rewrite. example: p: write, e: erase shipped product p e p e p: 3 rewrites shipped product e p e p e p: 3 rewrites remark the range of the operating clock during flash memory programming is the same as the range during normal operation. chapter 23 electrical specifications (standard products, (a) grade products) (expanded-specification products) user?s manual u15836ej5v0ud 387 (2) serial write operation characteristics parameter symbol conditions min. typ. max. unit set time from v dd user?s manual u15836ej5v0ud 388 chapter 24 electrical specifications (standard products, (a) grade products) (c onventional products) target products (conventional products): products with rank note i or k ? pd780101, 780102, 780103, 780101(a), 780102(a), and 780 103(a) for which orders were received on or before mid-march, 2004 ? pd78f0103 and 78f0103(a) for which orders were received on or before mid-july, 2004 note the rank is indicated by the 5th digit from the le ft in the 3rd column (lot number) marked on the package. lot number year code week code rank absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit v dd ? 0.3 to +6.5 v v ss ? 0.3 to +0.3 v av ref ? 0.3 to v dd + 0.3 note 1 v av ss ? 0.3 to +0.3 v supply voltage v pp pd78f0103, 78f0103(a) only note 2 ? 0.3 to +10.5 v v i1 p00 to p03, p10 to p17, p20 to p23, p30 to p33, p120, x1, x2, reset ? 0.3 to v dd + 0.3 note 1 v input voltage v i2 v pp in flash programming mode ( pd78f0103, 78f0103(a) only) ? 0.3 to +10.5 v output voltage v o ? 0.3 to v dd + 0.3 note 1 v analog input voltage v an av ss ? 0.3 to av ref + 0.3 note 1 and ? 0.3 to v dd + 0.3 note 1 v per pin ? 10 ma p30 to p33, p120 ? 30 ma total of pins p00 to p03, p10 to p17, p130 ? 30 ma output current, high i oh total of all pins ? 50 ma per pin 20 ma p30 to p33, p120 35 ma total of pins p00 to p03, p10 to p17, p130 35 ma output current, low i ol total of all pins 60 ma in normal operation mode ? 40 to +85 operating ambient temperature t a in flash memory programming ? 10 to +85 c pd780101, 780102, 780103, 780101(a), 780102(a), 780103(a) ? 65 to +150 storage temperature t stg pd78f0103, 78f0103(a) ? 40 to +125 c note 1. must be 6.5 v or lower. (refer to note 2 on the next page.) chapter 24 electrical specifications (s tandard products, (a) grade pr oducts) (conventional products) user?s manual u15836ej5v0ud 389 note 2. make sure that the following conditions of the v pp voltage application timing are satisfied when the flash memory is written. ? when supply voltage rises v pp must exceed v dd 10 s or more after v dd has reached the lower-limit value (2.7 v) of the operating voltage range (see a in the figure below). ? when supply voltage drops v dd must be lowered 10 s or more after v pp falls below the lower-limit value (2.7 v) of the operating voltage range of v dd (see b in the figure below). 2.7 v v dd 0 v 0 v v pp 2.7 v a b caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute m aximum ratings are not exceeded. remark unless specified otherwise, the characteristics of alter nate-function pins are the same as those of port pins. chapter 24 electrical specifications (sta ndard products, (a) grade pr oducts) (conventional products) user?s manual u15836ej5v0ud 390 x1 oscillator characteristics (t a = ? 40 to +85 c, 2.7 v v dd 5.5 v, 2.7 v av ref v dd , v ss = av ss = 0 v) resonator recommended circuit parameter conditions min. typ. max. unit 4.0 v v dd 5.5 v 2.0 10 3.3 v v dd < 4.0 v 2.0 8.38 ceramic resonator c1 x2 x1 v ss c2 oscillation frequency (f xp ) note 2.7 v v dd < 3.3 v 2.0 5.0 mhz 4.0 v v dd 5.5 v 2.0 10 3.3 v v dd < 4.0 v 2.0 8.38 crystal resonator c1 x2 x1 v ss c2 oscillation frequency (f xp ) note 2.7 v v dd < 3.3 v 2.0 5.0 mhz 4.0 v v dd 5.5 v 2.0 10 3.3 v v dd < 4.0 v 2.0 8.38 x1 input frequency (f xp ) note 2.7 v v dd < 3.3 v 2.0 5.0 mhz 4.0 v v dd 5.5 v 46 500 3.3 v v dd < 4.0 v 56 500 external clock x2 x1 x1 input high-/low- level width (t xph , t xpl ) 2.7 v v dd < 3.3 v 96 500 ns note indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. cautions 1. when using the x1 oscillator, wire as follo ws in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. ? keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line th rough which a high fluctuating current flows. always make the ground point of the osci llator capacitor the same potential as v ss . do not ground the capacitor to a ground pa ttern through which a high current flows. do not fetch signals from the oscillator. 2. since the cpu is started by the ring-osc after reset is released, check th e oscillation stabilization time of the x1 input clock using th e oscillation stabilization time counter status register (ostc). determine the o scillation stabilization time of the ostc register and oscillation stabilization time select register (osts) after sufficiently evaluating the oscillation stabilization time with the resonator to be used. ring-osc oscillator characteristics (t a = ? 40 to +85 c, 2.7 v v dd 5.5 v, 2.7 v av ref v dd , v ss = av ss = 0 v) resonator parameter conditions min. typ. max. unit on-chip ring-osc oscillator oscillation frequency (f r ) 120 240 480 khz chapter 24 electrical specifications (s tandard products, (a) grade pr oducts) (conventional products) user?s manual u15836ej5v0ud 391 recommended oscillator constants caution for the resonator selection of the pd780101(a), 78010 2(a), and 780103(a) and oscillator constants, users are required to either evaluate the oscillati on themselves or apply to the resonator manufacturer for evaluation. (a) pd780101, 780102, 780103 x1 oscillation: ceramic resonator (t a = ? 40 to +85 c) recommended circuit constants oscillation voltage range manufacturer part number smd/lead frequency (mhz) c1 (pf) c2 (pf) min. (v) max. (v) cstcc2m00g56-r0 smd 2.00 internal (47) internal (47) cstcr4m00g55-r0 cstcr4m00g55u-r0 smd internal (39) internal (39) cstls4m00g56-b0 cstls4m00g56u-b0 lead 4.00 internal (47) internal (47) cstcr4m19g55-r0 cstcr4m19g55u-r0 smd internal (39) internal (39) cstls4m19g56-b0 cstls4m19g56u-b0 lead 4.194 internal (47) internal (47) cstcr4m91g55-r0 cstcr4m91g55u-r0 smd internal (39) internal (39) cstls4m91g56-b0 cstls4m91g56u-b0 lead 4.915 internal (47) internal (47) cstcr5m00g55-r0 cstcr5m00g55u-r0 smd internal (39) internal (39) cstls5m00g56-b0 cstls5m00g56u-b0 lead 5.00 internal (47) internal (47) cstcr6m00g55-r0 cstcr6m00g55u-r0 smd internal (39) internal (39) cstls6m00g56-b0 cstls6m00g56u-b0 lead 6.00 internal (47) internal (47) cstce8m00g52-r0 smd internal (10) internal (10) cstls8m00g53-b0 cstls8m00g53u-b0 lead 8.00 internal (15) internal (15) cstce10m0g52-r0 smd internal (10) internal (10) cstls10m0g53-b0 murata mfg. cstls10m0g53u-b0 lead 10.0 internal (15) internal (15) 2.7 5.5 caution the oscillator constants shown above are reference values based on evaluation in a specific environment by the resonator ma nufacturer. if it is necess ary to optimize the oscillator characteristics in the actual app lication, apply to the resonato r manufacturer for evaluation on the implementation circuit. the oscillation vo ltage and oscillation frequency only indicate the oscillator characteristic. use th e 78k0/kb1 so that the internal operation conditions are within the specifications of the dc and ac characteristics. chapter 24 electrical specifications (sta ndard products, (a) grade pr oducts) (conventional products) user?s manual u15836ej5v0ud 392 (b) pd78f0103 x1 oscillation: ceramic resonator (t a = ? 40 to +85 c) recommended circuit constants oscillation voltage range manufacturer part number smd/lead frequency (mhz) c1 (pf) c2 (pf) min. (v) max. (v) cstcc2m00g56-r0 smd 2.00 internal (47) internal (47) cstcc2m45g56-r0 smd 2.457 internal (47) internal (47) cstcr4m00g53-r0 cstcr4m00g53093-r0 smd internal (15) internal (15) cstls4m00g53-b0 cstls4m00g53093-b0 lead 4.00 internal (15) internal (15) cstcr5m00g53-r0 cstcr5m00g53093-r0 smd internal (15) internal (15) cstls5m00g53-b0 cstls5m00g53093-b0 lead 5.00 internal (15) internal (15) cstcr6m00g53-r0 cstcr6m00g53u-r0 smd internal (15) internal (15) cstls6m00g53-b0 cstls6m00g53u-b0 lead 6.00 internal (15) internal (15) cstce8m38g52-r0 smd internal (10) internal (10) cstls8m38g53-b0 cstls8m38g53093-b0 lead 8.388 internal (15) internal (15) cstce10m0g52-r0 smd internal (10) internal (10) cstls10m0g53-b0 murata mfg. cstls10m0g53093-b0 lead 10.0 internal (15) internal (15) 2.7 5.5 caution the oscillator constants shown above are reference values based on evaluation in a specific environment by the resonator ma nufacturer. if it is necess ary to optimize the oscillator characteristics in the actual app lication, apply to the resonato r manufacturer for evaluation on the implementation circuit. the oscillation vo ltage and oscillation frequency only indicate the oscillator characteristic. use th e 78k0/kb1 so that the internal operation conditions are within the specifications of the dc and ac characteristics. chapter 24 electrical specifications (s tandard products, (a) grade pr oducts) (conventional products) user?s manual u15836ej5v0ud 393 (c) ? chapter 24 electrical specifications (sta ndard products, (a) grade pr oducts) (conventional products) user?s manual u15836ej5v0ud 394 dc characteristics (t a = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? chapter 24 electrical specifications (s tandard products, (a) grade pr oducts) (conventional products) user?s manual u15836ej5v0ud 395 dc characteristics (2/3): ? chapter 24 electrical specifications (sta ndard products, (a) grade pr oducts) (conventional products) user?s manual u15836ej5v0ud 396 dc characteristics (3/3): ? chapter 24 electrical specifications (s tandard products, (a) grade pr oducts) (conventional products) user?s manual u15836ej5v0ud 397 ac characteristics (1) basic operation (t a = ? chapter 24 electrical specifications (sta ndard products, (a) grade pr oducts) (conventional products) user?s manual u15836ej5v0ud 398 (2) serial interface (t a = ? 40 to +85 c, 2.7 v v dd 5.5 v, 2.7 v av ref v dd , v ss = av ss = 0 v) (a) uart mode (uart6, dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit transfer rate 312.5 kbps (b) uart mode (uart0, dedicate d baud rate generator output): pd780102, 780103, 78f0103, 780102(a), 780103(a), and 78f0103(a) only parameter symbol conditions min. typ. max. unit transfer rate 312.5 kbps (c) 3-wire serial i/o mode (master m ode, sck10... internal clock output) parameter symbol conditions min. typ. max. unit 4.0 v v dd 5.5 v 200 ns 3.3 v v dd < 4.0 v 240 ns sck10 cycle time t kcy1 2.7 v v dd < 3.3 v 400 ns sck10 high-/low-level width t kh1 , t kl1 t kcy1 /2 ? 10 ns si10 setup time (to sck10 ) t sik1 30 ns si10 hold time (from sck10 ) t ksi1 30 ns delay time from sck10 to so10 output t kso1 c = 100 pf note 30 ns note c is the load capacitance of the sck10 and so10 output lines. (d) 3-wire serial i/o mode (slave m ode, sck10... external clock input) parameter symbol conditions min. typ. max. unit sck10 cycle time t kcy2 400 ns sck10 high-/low-level width t kh2 , t kl2 t kcy2 /2 ns si10 setup time (to sck10 ) t sik2 80 ns si10 hold time (from sck10 ) t ksi2 50 ns delay time from sck10 to so10 output t kso2 c = 100 pf note 120 ns note c is the load capacitance of the so10 output line. chapter 24 electrical specifications (s tandard products, (a) grade pr oducts) (conventional products) user?s manual u15836ej5v0ud 399 ac timing test points (excluding x1 input) 0.8v dd 0.2v dd test points 0.8v dd 0.2v dd clock timing x1 input v ih4 (min.) v il4 (max.) 1/f xp t xl t xh ti timing ti000, ti010 t til0 t tih0 ti50 1/f ti5 t til5 t tih5 interrupt request input timing intp0 to intp5 t intl t inth reset input timing reset t rsl chapter 24 electrical specifications (sta ndard products, (a) grade pr oducts) (conventional products) user?s manual u15836ej5v0ud 400 serial transfer timing 3-wire serial i/o mode: si10 so10 t kcym t klm t khm t sikm t ksim input data t ksom output data sck10 remark m = 1, 2 a/d converter characteristics (t a = ? chapter 24 electrical specifications (s tandard products, (a) grade pr oducts) (conventional products) user?s manual u15836ej5v0ud 401 poc circuit characteristics (t a = ? 40 to +85 c) parameter symbol conditions min. typ. max. unit v poc0 mask option = 3.5 v note 1 3.3 3.5 3.7 v detection voltage v poc1 mask option = 2.85 v note 2 2.7 2.85 3.0 v v dd : 0 v 2.7 v 0.0015 ms power supply rise time t pth v dd : 0 v 3.3 v 0.002 ms response delay time 1 note 3 t pthd when power supply rises, after reaching detection voltage (max.) 3.0 ms response delay time 2 note 4 t pd when v dd falls 1.0 ms minimum pulse width t pw 0.2 ms notes 1. when flash memory version pd78f0103m5, 78f0103m6, 78f0103m5( a), or 78f0103m6(a) is used 2. when flash memory version pd78f0103m3, 78f0103m4, 78f0103m3( a), or 78f0103m4(a) is used 3. time required from voltage detection to reset release. 4. time required from voltage detection to internal reset output. poc circuit timing supply voltage (v dd ) time detection voltage (min.) detection voltage (typ.) detection voltage (max.) t pth t pthd t pw t pd chapter 24 electrical specifications (sta ndard products, (a) grade pr oducts) (conventional products) user?s manual u15836ej5v0ud 402 lvi circuit characteristics (t a = ? ? chapter 24 electrical specifications (s tandard products, (a) grade pr oducts) (conventional products) user?s manual u15836ej5v0ud 403 flash memory programming characteristics: the prewrite time before erasure and the erase verify time (writeback time) are not included. 3. the recommended setting value of the writeback time is 50 ms. 4. writeback is executed once by the issu ance of the writeback command. therefore, the number of retries must be the maximum value minus the number of commands issued. 5. the recommended setting value of the step write time is 50 chapter 24 electrical specifications (sta ndard products, (a) grade pr oducts) (conventional products) user?s manual u15836ej5v0ud 404 (2) serial write operation characteristics parameter symbol conditions min. typ. max. unit set time from v dd user?s manual u15836ej5v0ud 405 chapter 25 electrical specifi cations ((a1) grade products) target products: pd780101(a1), 780102(a1), 780103(a1), 78f0103(a1) absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit v dd ? 0.3 to +6.5 v v ss ? 0.3 to +0.3 v av ref ? 0.3 to v dd + 0.3 note 1 v av ss ? 0.3 to +0.3 v supply voltage v pp pd78f0103(a1) only note 2 ? 0.3 to +10.5 v v i1 p00 to p03, p10 to p17, p20 to p23, p30 to p33, p120, x1, x2, reset ? 0.3 to v dd + 0.3 note 1 v input voltage v i2 v pp in flash programming mode ( pd78f0103(a1) only) ? 0.3 to +10.5 v output voltage v o ? 0.3 to v dd + 0.3 note 1 v analog input voltage v an av ss ? 0.3 to av ref + 0.3 note 1 and ? 0.3 to v dd + 0.3 note 1 v per pin ? 8 ma p30 to p33, p120 ? 24 ma total of pins p00 to p03, p10 to p17, p130 ? 24 ma output current, high i oh total of all pins ? 40 ma per pin 16 ma p30 to p33, p120 28 ma total of pins p00 to p03, p10 to p17, p130 28 ma output current, low i ol total of all pins 48 ma pd780101(a1), 780102(a1), 780103(a1) ? 40 to +110 in normal operation mode ? 40 to +105 operating ambient temperature t a pd78f0103(a1) in flash memory programming ? 10 to +85 c pd780101(a1), 780102(a1), 780103(a1) ? 65 to +150 storage temperature t stg pd78f0103(a1) ? 40 to +125 c note 1. must be 6.5 v or lower. (refer to note 2 on the next page.) caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute m aximum ratings are not exceeded. remark unless specified otherwise, the characteristics of alter nate-function pins are the same as those of port pins. chapter 25 electrical specifications ((a1) grade products) user?s manual u15836ej5v0ud 406 note 2. make sure that the following conditions of the v pp voltage application timing are satisfied when the flash memory is written. ? ? chapter 25 electrical specifications ((a1) grade products) user?s manual u15836ej5v0ud 407 x1 oscillator characteristics (t a = ? 40 to +110 c note 1 , 3.3 v v dd 5.5 v, 3.3 v av ref v dd , v ss = av ss = 0 v) resonator recommended circuit parameter conditions min. typ. max. unit 4.5 v v dd 5.5 v 2.0 10 4.0 v v dd < 4.5 v 2.0 8.38 ceramic resonator c1 x2 x1 v ss c2 oscillation frequency (f xp ) note 2 3.3 v v dd < 4.0 v 2.0 5.0 mhz 4.5 v v dd 5.5 v 2.0 10 4.0 v v dd < 4.5 v 2.0 8.38 crystal resonator c1 x2 x1 v ss c2 oscillation frequency (f xp ) note 2 3.3 v v dd < 4.0 v 2.0 5.0 mhz 4.5 v v dd 5.5 v 2.0 10 4.0 v v dd < 4.5 v 2.0 8.38 x1 input frequency (f xp ) note 2 3.3 v v dd < 4.0 v 2.0 5.0 mhz 4.5 v v dd 5.5 v 46 500 4.0 v v dd < 4.5 v 56 500 external clock x2 x1 x1 input high-/low- level width (t xh , t xl ) 3.3 v v dd < 4.0 v 96 500 ns notes 1. t a = ? 40 to +110 c: pd780101(a1), 780102(a1), 780103(a1) t a = ? 40 to +105 c: pd78f0103(a1) 2. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. cautions 1. when using the x1 oscillator, wire as follo ws in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. ? keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line th rough which a high fluctuating current flows. always make the ground point of the osci llator capacitor the same potential as v ss . do not ground the capacitor to a ground pa ttern through which a high current flows. do not fetch signals from the oscillator. 2. since the cpu is started by the ring-osc after reset is released, check th e oscillation stabilization time of the x1 input clock using th e oscillation stabilization time counter status register (ostc). determine the o scillation stabilization time of the ostc register and oscillation stabilization time select register (osts) after sufficiently evaluating the oscillation stabilization time with the resonator to be used. remark for the resonator selection and oscillator constant, us ers are required to either evaluate the oscillation themselves or apply to the resonat or manufacturer for evaluation. ring-osc oscillator characteristics (t a = ? 40 to +110 c note , 3.3 v v dd 5.5 v, 3.3 v av ref v dd , v ss = av ss = 0 v) resonator parameter conditions min. typ. max. unit on-chip ring-osc oscillator oscillation frequency (f r ) 120 240 490 khz note t a = ? 40 to +110 c: pd780101(a1), 780102(a1), 780103(a1) t a = ? 40 to +105 c: pd78f0103(a1) chapter 25 electrical specifications ((a1) grade products) user?s manual u15836ej5v0ud 408 dc characteristics (1/4): pd78f0103(a1) (t a = ? 40 to +105 c, 3.3 v v dd 5.5 v, 3.3 v av ref v dd , v ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit per pin 4.0 v v dd 5.5 v ? 4 ma total of p30 to p33, p120 4.0 v v dd 5.5 v ? 20 ma total of p00 to p03, p10 to p17, p130 4.0 v v dd 5.5 v ? 20 ma 4.0 v v dd 5.5 v ? 25 ma output current, high i oh total of all pins 3.3 v v dd < 4.0 v ? 8 ma per pin 4.0 v v dd 5.5 v 8 ma total of p30 to p33, p120 4.0 v v dd 5.5 v 24 ma total of p00 to p03, p10 to p17, p130 4.0 v v dd 5.5 v 24 ma 4.0 v v dd 5.5 v 30 ma output current, low i ol total of all pins 3.3 v v dd < 4.0 v 8 ma v ih1 p12, p13, p15 0.7v dd v dd v v ih2 p00 to p03, p10, p11, p14, p16, p17, p30 to p33, p120, reset 0.8v dd v dd v v ih3 p20 to p23 note 1 0.7av ref av ref v input voltage, high v ih4 x1, x2 v dd ? 0.5 v dd v v il1 p12, p13, p15 0 0.3v dd v v il2 p00 to p03, p10, p11, p14, p16, p17, p30 to p33, p120, reset 0 0.2v dd v v il3 p20 to p23 note 1 0 0.3av ref v input voltage, low v il4 x1, x2 0 0.4 v total of p30 to p33, p120 pins i oh = ? 20 ma 4.0 v v dd 5.5 v, i oh = ? 4 ma v dd ? 1.0 v total of p00 to p03, p10 to p17, p130 pins i oh = ? 20 ma 4.0 v v dd 5.5 v, i oh = ? 4 ma v dd ? 1.0 v output voltage, high v oh i oh = ? 100 a 3.3 v v dd < 4.0 v v dd ? 0.5 v total of p30 to p33, p120 pins i ol = 24 ma 4.0 v v dd 5.5 v, i ol = 8 ma 1.3 v total of p00 to p03, p10 to p17, p130 pins i ol = 24 ma 4.0 v v dd 5.5 v, i ol = 8 ma 1.3 v output voltage, low v ol i ol = 400 a 3.3 v v dd < 4.0 v 0.4 v v i = v dd p00 to p03, p10 to p17, p30 to p33, p120, reset 10 a i lih1 v i = av ref p20 to p23 10 a input leakage current, high i lih2 v i = v dd x1, x2 note 2 20 a i lil1 p00 to p03, p10 to p17, p20 to p23, p30 to p33, p120, reset ? 10 a input leakage current, low i lil2 v i = 0 v x1, x2 note 2 ? 20 a output leakage current, high i loh v o = v dd 10 a output leakage current, low i lol v o = 0 v ? 10 a pull-up resistance value r v i = 0 v 10 30 120 k ? v pp supply voltage v pp1 in normal operation mode 0 0.2v dd v notes 1. when used as a digital input port, set av ref = v dd . 2. when the inverse level of x1 is input to x2. remark unless specified otherwise, the characteristics of alter nate-function pins are the same as those of port pins. chapter 25 electrical specifications ((a1) grade products) user?s manual u15836ej5v0ud 409 dc characteristics (2/4): pd780101(a1), 780102(a1), 780103(a1) (t a = ? 40 to +110 c, 3.3 v v dd 5.5 v, 3.3 v av ref v dd , v ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit per pin 4.0 v v dd 5.5 v ? 4 ma total of p30 to p33, p120 4.0 v v dd 5.5 v ? 20 ma total of p00 to p03, p10 to p17, p130 4.0 v v dd 5.5 v ? 20 ma 4.0 v v dd 5.5 v ? 32 ma output current, high i oh total of all pins 3.3 v v dd < 4.0 v ? 8 ma per pin 4.0 v v dd 5.5 v 8 ma total of p30 to p33, p120 4.0 v v dd 5.5 v 24 ma total of p00 to p03, p10 to p17, p130 4.0 v v dd 5.5 v 24 ma 4.0 v v dd 5.5 v 40 ma output current, low i ol total of all pins 3.3 v v dd < 4.0 v 8 ma v ih1 p12, p13, p15 0.7v dd v dd v v ih2 p00 to p03, p10, p11, p14, p16, p17, p30 to p33, p120, reset 0.8v dd v dd v v ih3 p20 to p23 note 1 0.7av ref av ref v input voltage, high v ih4 x1, x2 v dd ? 0.5 v dd v v il1 p12, p13, p15 0 0.3v dd v v il2 p00 to p03, p10, p11, p14, p16, p17, p30 to p33, p120, reset 0 0.2v dd v v il3 p20 to p23 note 1 0 0.3av ref v input voltage, low v il4 x1, x2 0 0.4 v total of p30 to p33, p120 pins i oh = ? 20 ma 4.0 v v dd 5.5 v, i oh = ? 4 ma v dd ? 1.0 v total of p00 to p03, p10 to p17, p130 pins i oh = ? 20 ma 4.0 v v dd 5.5 v, i oh = ? 4 ma v dd ? 1.0 v output voltage, high v oh i oh = ? 100 a 3.3 v v dd < 4.0 v v dd ? 0.5 v total of p30 to p33, p120 pins i ol = 24 ma 4.0 v v dd 5.5 v, i ol = 8 ma 1.3 v total of p00 to p03, p10 to p17, p130 pins i ol = 24 ma 4.0 v v dd 5.5 v, i ol = 8 ma 1.3 v output voltage, low v ol i ol = 400 a 3.3 v v dd < 4.0 v 0.4 v v i = v dd p00 to p03, p10 to p17, p30 to p33, p120, reset 10 a i lih1 v i = av ref p20 to p23 10 a input leakage current, high i lih2 v i = v dd x1, x2 note 2 20 a i lil1 p00 to p03, p10 to p17, p20 to p23, p30 to p33, p120, reset ? 10 a input leakage current, low i lil2 v i = 0 v x1, x2 note 2 ? 20 a output leakage current, high i loh v o = v dd 10 a output leakage current, low i lol v o = 0 v ? 10 a pull-up resistance value r v i = 0 v 10 30 120 k ? notes 1. when used as a digital input port, set av ref = v dd . 2. when the inverse level of x1 is input to x2. remark unless specified otherwise, the characteristics of alter nate-function pins are the same as those of port pins. chapter 25 electrical specifications ((a1) grade products) user?s manual u15836ej5v0ud 410 dc characteristics (3/4): pd78f0103(a1) (t a = ? 40 to +105 c, 3.3 v v dd 5.5 v, 3.3 v av ref v dd , v ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit when a/d converter is stopped 11.6 20.6 ma i dd1 x1 crystal oscillation operating mode note 2 f xp = 10 mhz, v dd = 5.0 v 10% note 3 when a/d converter is operating note 4 12.6 22.6 ma when peripheral functions are stopped 1.4 3.9 ma i dd2 x1 crystal oscillation halt mode f xp = 10 mhz, v dd = 5.0 v 10% when peripheral functions are operating 6.6 ma i dd3 ring-osc operating mode note 5 v dd = 5.0 v 10% 0.37 2.61 ma i dd4 ring-osc halt mode note 5 v dd = 5.0 v 10% 0.19 1.86 ma poc: off, ring: off 0.1 1100 a poc: off, ring: on 14 1200 a poc: on note 6 , ring: off 3.5 1100 a supply current note 1 i dd5 stop mode v dd = 5.0 v 10% poc: on note 6 , ring: on 17.5 1200 a notes 1. total current flowing through the internal power supply (v dd ). peripheral operation current is included (however, the current that flows through the pull-up resistors of ports is not included). 2. i dd1 includes peripheral operation current. 3. when pcc = 00h. 4. total current flowing through v dd and av ref pins. 5. when x1 oscillator is stopped. 6. including when lvie (bit 4 of lvim) = 1 in the pd78f0103m1(a1) and 78f0103m2(a1). chapter 25 electrical specifications ((a1) grade products) user?s manual u15836ej5v0ud 411 dc characteristics (4/4): pd780101(a1), 780102(a1), 780103(a1) (t a = ? 40 to +110 c, 3.3 v v dd 5.5 v, 3.3 v av ref v dd , v ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit when a/d converter is stopped 6 11.7 ma i dd1 x1 crystal oscillation operating mode note 2 f xp = 10 mhz, v dd = 5.0 v 10% note 3 when a/d converter is operating note 4 7 13.7 ma when peripheral functions are stopped 1.3 3.4 ma i dd2 x1 crystal oscillation halt mode f xp = 10 mhz, v dd = 5.0 v 10% when peripheral functions are operating 5.6 ma i dd3 ring-osc operating mode note 5 v dd = 5.0 v 10% 0.18 1.52 ma i dd4 ring-osc halt mode note 5 v dd = 5.0 v 10% 0.05 1.00 ma poc: off, ring: off 0.1 800 a poc: off, ring: on 14 900 a poc: on note 6 , ring: off 3.5 800 a supply current note 1 i dd5 stop mode v dd = 5.0 v 10% poc: on note 6 , ring: on 17.5 900 a notes 1. total current flowing through the internal power supply (v dd ). peripheral operation current is included (however, the current that flows through the pull-up resistors of ports is not included). 2. i dd1 includes peripheral operation current. 3. when pcc = 00h. 4. total current flowing through v dd and av ref pins. 5. when x1 oscillator is stopped. 6. including when lvie (bit 4 of lvim) = 1 with poc-off selected by a mask option. chapter 25 electrical specifications ((a1) grade products) user?s manual u15836ej5v0ud 412 ac characteristics (1) basic operation (t a = ? ? ? chapter 25 electrical specifications ((a1) grade products) user?s manual u15836ej5v0ud 413 (2) serial interface (t a = ? ? ? ? chapter 25 electrical specifications ((a1) grade products) user?s manual u15836ej5v0ud 414 ac timing test points (excluding x1 input) 0.8v dd 0.2v dd test points 0.8v dd 0.2v dd clock timing x1 input v ih4 (min.) v il4 (max.) 1/f xp t xl t xh ti timing ti000, ti010 t til0 t tih0 ti50 1/f ti5 t til5 t tih5 interrupt request input timing intp0 to intp5 t intl t inth reset input timing reset t rsl chapter 25 electrical specifications ((a1) grade products) user?s manual u15836ej5v0ud 415 serial transfer timing 3-wire serial i/o mode: si10 so10 t kcym t klm t khm t sikm t ksim input data t ksom output data sck10 remark m = 1, 2 a/d converter characteristics (t a = ? ? ? chapter 25 electrical specifications ((a1) grade products) user?s manual u15836ej5v0ud 416 poc circuit characteristics (t a = ? 40 to +110 c note 1 ) parameter symbol conditions min. typ. max. unit detection voltage v poc0 mask option = 3.5 v note 2 3.3 3.5 3.72 v power supply rise time t pth v dd : 0 v 3.3 v 0.002 ms response delay time 1 note 3 t pthd when power supply rises, after reaching detection voltage (max.) 3.0 ms response delay time 2 note 4 t pd when v dd falls 1.0 ms minimum pulse width t pw 0.2 ms notes 1. t a = ? 40 to +110 c: pd780101(a1), 780102(a1), 780103(a1) t a = ? 40 to +105 c: pd78f0103(a1) 2. when flash memory version pd78f0103m5(a1) or 78f0103m6(a1) is used 3. time required from voltage detection to reset release. 4. time required from voltage detection to internal reset output. poc circuit timing supply voltage (v dd ) time detection voltage (min.) detection voltage (typ.) detection voltage (max.) t pth t pthd t pw t pd chapter 25 electrical specifications ((a1) grade products) user?s manual u15836ej5v0ud 417 lvi circuit characteristics (t a = ? ? ? ? ? ? chapter 25 electrical specifications ((a1) grade products) user?s manual u15836ej5v0ud 418 flash memory programming characteristics: chapter 25 electrical specifications ((a1) grade products) user?s manual u15836ej5v0ud 419 (2) serial write operation characteristics parameter symbol conditions min. typ. max. unit set time from v dd user?s manual u15836ej5v0ud 420 chapter 26 electrical specifi cations ((a2) grade products) target products: pd780101(a2), 780102(a2), 780103(a2) absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit v dd ? 0.3 to +6.5 v v ss ? 0.3 to +0.3 v av ref ? 0.3 to v dd + 0.3 note v supply voltage av ss ? 0.3 to +0.3 v input voltage v i1 p00 to p03, p10 to p17, p20 to p23, p30 to p33, p120, x1, x2, reset ? 0.3 to v dd + 0.3 note v output voltage v o ? 0.3 to v dd + 0.3 note v analog input voltage v an av ss ? 0.3 to av ref + 0.3 note and ? 0.3 to v dd + 0.3 note v per pin ? 7 ma p30 to p33, p120 ? 21 ma total of pins p00 to p03, p10 to p17, p130 ? 21 ma output current, high i oh total of all pins ? 35 ma per pin 14 ma p30 to p33, p120 24.5 ma total of pins p00 to p03, p10 to p17, p130 24.5 ma output current, low i ol total of all pins 42 ma operating ambient temperature t a in normal operation mode ? 40 to +125 c storage temperature t stg ? 65 to +150 c note must be 6.5 v or lower. caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute m aximum ratings are not exceeded. remark unless specified otherwise, the characteristics of alter nate-function pins are the same as those of port pins. chapter 26 electrical specifications ((a2) grade products) user?s manual u15836ej5v0ud 421 x1 oscillator characteristics (t a = ? ? chapter 26 electrical specifications ((a2) grade products) user?s manual u15836ej5v0ud 422 dc characteristics (1/2) (t a = ? 40 to +125 c, 3.3 v v dd 5.5 v, 3.3 v av ref v dd , v ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit per pin 4.0 v v dd 5.5 v ? 3.5 ma total of p30 to p33, p120 4.0 v v dd 5.5 v ? 17.5 ma total of p00 to p03, p10 to p17, p130 4.0 v v dd 5.5 v ? 17.5 ma 4.0 v v dd 5.5 v ? 28 ma output current, high i oh total of all pins 3.3 v v dd < 4.0 v ? 7 ma per pin 4.0 v v dd 5.5 v 7 ma total of p30 to p33, p120 4.0 v v dd 5.5 v 21 ma total of p00 to p03, p10 to p17, p130 4.0 v v dd 5.5 v 21 ma 4.0 v v dd 5.5 v 35 ma output current, low i ol total of all pins 3.3 v v dd < 4.0 v 7 ma v ih1 p12, p13, p15 0.7v dd v dd v v ih2 p00 to p03, p10, p11, p14, p16, p17, p30 to p33, p120, reset 0.8v dd v dd v v ih3 p20 to p23 note 1 0.7av ref av ref v input voltage, high v ih4 x1, x2 v dd ? 0.5 v dd v v il1 p12, p13, p15 0 0.3v dd v v il2 p00 to p03, p10, p11, p14, p16, p17, p30 to p33, p120, reset 0 0.2v dd v v il3 p20 to p23 note 1 0 0.3av ref v input voltage, low v il4 x1, x2 0 0.4 v total of p30 to p33, p120 pins i oh = ? 17.5 ma 4.0 v v dd 5.5 v, i oh = ? 3.5 ma v dd ? 1.0 v total of p00 to p03, p10 to p17, p130 pins i oh = ? 17.5 ma 4.0 v v dd 5.5 v, i oh = ? 3.5 ma v dd ? 1.0 v output voltage, high v oh i oh = ? 100 a 3.3 v v dd < 4.0 v v dd ? 0.5 v total of p30 to p33, p120 pins i ol = 21 ma 4.0 v v dd 5.5 v, i ol = 7 ma 1.3 v total of p00 to p03, p10 to p17, p130 pins i ol = 21 ma 4.0 v v dd 5.5 v, i ol = 7 ma 1.3 v output voltage, low v ol i ol = 400 a 3.3 v v dd < 4.0 v 0.4 v v i = v dd p00 to p03, p10 to p17, p30 to p33, p120, reset 10 a i lih1 v i = av ref p20 to p23 10 a input leakage current, high i lih2 v i = v dd x1, x2 note 2 20 a i lil1 p00 to p03, p10 to p17, p20 to p23, p30 to p33, p120, reset ? 10 a input leakage current, low i lil2 v i = 0 v x1, x2 note 2 ? 20 a output leakage current, high i loh v o = v dd 10 a output leakage current, low i lol v o = 0 v ? 10 a pull-up resistance value r v i = 0 v 10 30 120 k ? notes 1. when used as a digital input port, set av ref = v dd . 2. when the inverse level of x1 is input to x2. remark unless specified otherwise, the characteristics of alter nate-function pins are the same as those of port pins. chapter 26 electrical specifications ((a2) grade products) user?s manual u15836ej5v0ud 423 dc characteristics (2/2) (t a = ? 40 to +125 c, 3.3 v v dd 5.5 v, 3.3 v av ref v dd , v ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit when a/d converter is stopped 5.2 10.6 ma i dd1 x1 crystal oscillation operating mode note 2 f xp = 8.38 mhz, v dd = 5.0 v 10% note 3 when a/d converter is operating note 4 6.2 12.6 ma when peripheral functions are stopped 1.2 3.6 ma i dd2 x1 crystal oscillation halt mode f xp = 8.38 mhz, v dd = 5.0 v 10% when peripheral functions are operating 5.5 ma i dd3 ring-osc operating mode note 5 v dd = 5.0 v 10% 0.18 1.92 ma i dd4 ring-osc halt mode note 5 v dd = 5.0 v 10% 0.05 1.4 ma poc: off, ring: off 0.1 1200 a poc: off, ring: on 14 1300 a poc: on note 6 , ring: off 3.5 1200 a supply current note 1 i dd5 stop mode v dd = 5.0 v 10% poc: on note 6 , ring: on 17.5 1300 a notes 1. total current flowing through the internal power supply (v dd ). peripheral operation current is included (however, the current that flows through the pull-up resistors of ports is not included). 2. i dd1 includes peripheral operation current. 3. when pcc = 00h. 4. total current flowing through v dd and av ref pins. 5. when x1 oscillator is stopped. 6. including when lvie (bit 4 of lvim) = 1 with poc-off selected by a mask option. chapter 26 electrical specifications ((a2) grade products) user?s manual u15836ej5v0ud 424 ac characteristics (1) basic operation (t a = ? chapter 26 electrical specifications ((a2) grade products) user?s manual u15836ej5v0ud 425 (2) serial interface (t a = ? ? chapter 26 electrical specifications ((a2) grade products) user?s manual u15836ej5v0ud 426 ac timing test points (excluding x1 input) 0.8v dd 0.2v dd test points 0.8v dd 0.2v dd clock timing x1 input v ih4 (min.) v il4 (max.) 1/f xp t xl t xh ti timing ti000, ti010 t til0 t tih0 ti50 1/f ti5 t til5 t tih5 interrupt request input timing intp0 to intp5 t intl t inth reset input timing reset t rsl chapter 26 electrical specifications ((a2) grade products) user?s manual u15836ej5v0ud 427 serial transfer timing 3-wire serial i/o mode: si10 so10 t kcym t klm t khm t sikm t ksim input data t ksom output data sck10 remark m = 1, 2 chapter 26 electrical specifications ((a2) grade products) user?s manual u15836ej5v0ud 428 a/d converter characteristics (t a = ? 40 to +125 c, 3.3 v v dd 5.5 v, 3.3 v av ref v dd , v ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 10 10 10 bit 4.0 v av ref 5.5 v 0.2 0.7 %fsr overall error notes 1, 2 3.3 v av ref < 4.0 v 0.3 0.9 %fsr 4.0 v av ref 5.5 v 16 48 s conversion time t conv 3.3 v av ref < 4.0 v 19 48 s 4.0 v av ref 5.5 v 0.7 %fsr zero-scale error notes 1, 2 3.3 v av ref < 4.0 v 0.9 %fsr 4.0 v av ref 5.5 v 0.7 %fsr full-scale error notes 1, 2 3.3 v av ref < 4.0 v 0.9 %fsr 4.0 v av ref 5.5 v 5.5 lsb integral non-linearity error note 1 3.3 v av ref < 4.0 v 7.5 lsb 4.0 v av ref 5.5 v 2.5 lsb differential non-linearity error note 1 3.3 v av ref < 4.0 v 3.0 lsb analog input voltage v ain av ss av ref v notes 1. excludes quantization error ( 1/2 lsb). 2. this value is indicated as a ratio (%fsr) to the full-scale value. poc circuit characteristics (t a = ? 40 to +125 c) parameter symbol conditions min. typ. max. unit detection voltage v poc0 mask option = 3.5 v 3.3 3.5 3.76 v power supply rise time t pth v dd : 0 v 3.3 v 0.002 ms response delay time 1 note 1 t pthd when power supply rises, after reaching detection voltage (max.) 3.0 ms response delay time 2 note 2 t pd when v dd falls 1.0 ms minimum pulse width t pw 0.2 ms notes 1. time required from voltage detection to reset release. 2. time required from voltage detection to internal reset output. poc circuit timing supply voltage (v dd ) time detection voltage (min.) detection voltage (typ.) detection voltage (max.) t pth t pthd t pw t pd chapter 26 electrical specifications ((a2) grade products) user?s manual u15836ej5v0ud 429 lvi circuit characteristics (t a = ? ? user?s manual u15836ej5v0ud 430 chapter 27 package drawing s s h j t i g d e f c b k p l u n item b c i l m n 30-pin plastic ssop (7.62 mm (300)) a k d e f g h j p 30 16 115 a detail of lead end m m t millimeters 0.65 (t.p.) 0.45 max. 0.13 0.5 6.1 + ? + ? user?s manual u15836ej5v0ud 431 chapter 28 recommended soldering conditions these products should be soldered and mount ed under the following recommended conditions. for soldering methods and conditions other than those recommended below, please contact an nec electronics sales representative. for technical information, see the following website. semiconductor device mount manual (h ttp://www.necel.com/pkg/en/mount/index.html) table 28-1. surface mounting type soldering cond itions (1/2) (1) 30-pin plastic ssop (7.62 mm (300)) pd780101mc- -5a4, 780102mc- -5a4, 780103mc- -5a4, pd780101mc(a)- -5a4, 780102mc(a)- -5a4, 780103mc(a)- -5a4, pd780101mc(a1)- -5a4, 780102mc(a1)- -5a4, 780103mc(a1)- -5a4, pd780101mc(a2)- -5a4, 780102mc(a2)- -5a4, 780103mc(a2)- -5a4 soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. (at 210 c or higher), count: 3 times or less, exposure limit: 7 days note (after that, prebake at 125 c for 10 hours) ir35-107-3 vps package peak temperature: 215 c, time: 40 seconds max. (at 200 c or higher), count: 3 times or less, exposure limit: 7 days note (after that, prebake at 125 c for 10 hours) vp15-107-3 wave soldering solder bath temperature: 260 c max., time: 10 seconds max., count: once, preheating temperature: 120 c max. (package surface temperature), exposure limit: 7 days note (after that, prebake at 125 c for 10 hours) ws60-107-1 partial heating pin temperature: 300 c max., time: 3 seconds max. (per pin row) ? note after opening the dry pack, store it at 25 c or less and 65% rh or less for the allowable storage period. caution do not use different soldering methods together ( except for partial heating). chapter 28 recommended soldering conditions user?s manual u15836ej5v0ud 432 table 28-1. surface mounting type soldering cond itions (2/2) (2) 30-pin plastic ssop (7.62 mm (300)) pd78f0103m1mc-5a4, 78f010 3m2mc-5a4, 78f0103m3mc- 5a4, 78f0103m4mc-5a4, pd78f0103m5mc-5a4, 78f010 3m6mc-5a4, 78f0103m1mc(a)-5a4, 78f0103m2mc(a)-5a4, pd78f0103m3mc(a)-5a4, 78f0103m4m c(a)-5a4, 78f0103m5mc(a)-5a4, pd78f0103m6mc(a)-5a4, 78f0103m1m c(a1)-5a4, 78f0103m2mc(a1)-5a4, pd78f0103m5mc(a1)-5a4, 78f0103m6mc(a1)-5a4 soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. (at 210 c or higher), count: 2 times or less, exposure limit: 3 days note (after that, prebake at 125 c for 10 hours) ir35-103-2 vps package peak temperature: 215 c, time: 40 seconds max. (at 200 c or higher), count: 2 times or less, exposure limit: 3 days note (after that, prebake at 125 c for 10 hours) vp15-103-2 wave soldering solder bath temperature: 260 c max., time: 10 seconds max., count: once, preheating temperature: 120 c max. (package surface temperature), exposure limit: 3 days note (after that, prebake at 125 c for 10 hours) ws60-103-1 partial heating pin temperature: 300 c max., time: 3 seconds max. (per pin row) ? note after opening the dry pack, store it at 25 c or less and 65% rh or less for the allowable storage period. caution do not use different soldering methods together ( except for partial heating). user?s manual u15836ej5v0ud 433 chapter 29 cautions for wait 29.1 cautions for wait this product has two internal system buses. one is a cpu bus and the other is a peripheral bus t hat interfaces with the low-speed peripheral hardware. because the clock of the cpu bus and the clock of the peripheral bus are asynchronous, unexpected illegal data may be passed if an access to the cpu conflict s with an access to the peripheral hardware. when accessing the peripheral hardware that may cause a conflict, therefore, the cpu repeatedly executes processing, until the correct data is passed. as a result, the cpu does not start the next instruction processing but waits. if this happens, the number of execution clocks of an instruction incr eases by the number of wait clocks (f or the number of wait clocks, see table 29- 1 ). this must be noted when r eal-time processing is performed. chapter 29 cautions for wait user?s manual u15836ej5v0ud 434 29.2 peripheral hardware that generates wait table 29-1 lists the register s that issue a wait request when accessed by the cpu, and the number of cpu wait clocks. table 29-1. registers that generate wait and number of cpu wait clocks peripheral hardware register a ccess number of wait clocks watchdog timer wdtm write 3 clocks (fixed) serial interface uart0 asis0 read 1 clock (fixed) serial interface uart6 asis6 read 1 clock (fixed) adm write ads write pfm write pft write 2 to 5 clocks note (when adm.5 flag = ?1?) 2 to 9 clocks note (when adm.5 flag = ?0?) adcr read 1 to 5 clocks (when adm.5 flag = ?1?) 1 to 9 clocks (when adm.5 flag = ?0?) a/d converter chapter 29 cautions for wait user?s manual u15836ej5v0ud 435 29.3 example of wait occurrence <1> watchdog timer user?s manual u15836ej5v0ud 436 appendix a development tools the following development t ools are available for the development of systems that employ the 78k0/kb1. figure a-1 shows the developm ent tool configuration. ? support for pc98-nx series unless otherwise specified, products supported by ibm pc/at tm compatibles are compatible with pc98-nx series computers. when using pc98-nx series computer s, refer to the explanation for ibm pc/at compatibles. ? windows unless otherwise specified, ?windows? means the following oss. ? windows 3.1 ? windows 95 ? windows 98 ? windows nt tm ver. 4.0 ? windows 2000 ? windows xp appendix a development tools user?s manual u15836ej5v0ud 437 figure a-1. development tool configuration (1/3) (1) when using the in-circuit em ulators ie-78k0-ns, ie-78k0-ns-a language processing software ? ? ? ? ? ? ? ? appendix a development tools user?s manual u15836ej5v0ud 438 figure a-1. development tool configuration (2/3) (2) when using the in-circuit emulator ie-78k0k1-et in-circuit emulator note 3 emulation probe power supply unit language processing software ? ? ? ? ? ? ? ? appendix a development tools user?s manual u15836ej5v0ud 439 figure a-1. development tool configuration (3/3) (3) when using the in-circu it emulator qb-78k0kx1h in-circuit emulator note 3 emulation probe power supply unit language processing software ? assembler package ? c compiler package ? device file ? c library source file note 1 debugging software ? integrated debugger ? system simulator host machine (pc or ews) usb interface cable conversion socket or conversion adapter target system flash programmer flash memory write adapter flash memory ? software package ? project manager (windows only) note 2 software package flash memory write environment control software notes 1. the c library source file is not included in the software package. 2. the project manager pm plus is included in the assembler package. the pm plus is only used for windows. 3. in-circuit emulator qb-78k0kx1h is supplied with integrated debugger id78k0-qb, flash memory programmer pg-fpl (78k0/kx1 pr oducts are not supported), power supply unit, and usb interface cable. any other products are sold separately. appendix a development tools user?s manual u15836ej5v0ud 440 a.1 software package development tools (software) common to the 78k/0 series are combined in this package. sp78k0 78k/0 series software package part number: appendix a development tools user?s manual u15836ej5v0ud 441 remark ? appendix a development tools user?s manual u15836ej5v0ud 442 a.5 debugging tools (hardware) a.5.1 when using in-circuit emul ators ie-78k0-ns and ie-78k0-ns-a remark operations where the oscillation frequencies exceed 10 mhz can only be supported by the versions of the ie-78k0-ns with post n adminis trative symbols, ie-78k0-ns-a wit h post g administrative symbols, and ie-780148-ns-em1 with post e administrative symbols. ie-78k0-ns in-circuit emulator the in-circuit emulator serves to d ebug hardware and software when developing application systems using a 78k/0 series pr oduct. it corresponds to the integrated debugger (id78k0-ns). this emulator should be used in combination with a power supply unit, emulation probe, and the interface adapter required to connect this emulator to the host machine. ie-78k0-ns-pa performance board this board is connected to the ie-78k0-ns to expand its functions. adding this board adds a coverage function and enhances debugging functions such as tracer and timer functions. ie-78k0-ns-a in-circuit emulator product that combines the ie-78k0-ns and ie-78k0-ns-pa ie-70000-mc-ps-b power supply unit this adapter is used for supplying power from a 100 v to 240 v ac outlet. ie-70000-98-if-c interface adapter this adapter is required when using a pc-980 0 series computer (except notebook type) as the host machine (c bus compatible). ie-70000-cd-if-a pc card interface this is pc card and interface cable requi red when using a notebook-type computer as the host machine (pcmcia socket compatible). ie-70000-pc-if-c interface adapter this adapter is required when using an ibm pc/at compatible computer as the host machine (isa bus compatible). ie-70000-pci-if-a interface adapter this adapter is required when using a computer with a pci bus as the host machine. ie-780148-ns-em1 emulation board this board emulates the operations of the peripheral hardware peculiar to a device. it should be used in combination with an in-circuit emulator. np-30mc emulation probe this probe is used to connect the in-circuit emulator to the target system and is designed for use with a 30-pin plastic ssop (mc-5a4 type). nspack30bk yspack30bk hspack30bk yq-guide conversion socket this conversion socket connects the np- 30mc to a target system board designed to mount a 30-pin plasti c ssop (mc-5a4 type). ? nspack30bk: socket for connecting target ? yspack30bk: socket for connecting emulator ? hspack30bk: cover for mounting device ? yq-guide: guide pin remarks 1. np-30mc is a product of naito densei machida mfg. co., ltd. tel: +81-45-475-4191 naito densei machida mfg. co., ltd. 2. nspack30bk, yspack30bk, hspack30bk, and yq -guide are products of tokyo eletech corporation. for further information, contact daimaru kogyo co., ltd. tokyo electronics department (tel: +81-3-3820-7112) osaka electronics department (tel: +81-6-6244-6672) appendix a development tools user?s manual u15836ej5v0ud 443 a.5.2 when using in-circu it emulator ie-78k0k1-et remark operations where the oscillation frequencies exceed 10 mhz can only be supported by the versions of the ie-78k0k1-et with post c administrative symbols. ie-78k0k1-et note in-circuit emulator the in-circuit emulator serves to d ebug hardware and software when developing application systems using a 78k0/kx1 produc t. it corresponds to the integrated debugger (id78k0-ns). this emulator should be used in combination with a power supply unit, emulation probe, and the interface adapter required to connect this emulator to the host machine. ie-70000-98-if-c interface adapter this adapter is required when using a pc-980 0 series computer (except notebook type) as the host machine (c bus compatible). ie-70000-cd-if-a pc card interface this is pc card and interface cable requi red when using a notebook-type computer as the host machine (pcmcia socket compatible). ie-70000-pc-if-c interface adapter this adapter is required when using an ibm pc/at compatible computer as the host machine (isa bus compatible). ie-70000-pci-if-a interface adapter this adapter is required when using a computer with a pci bus as the host machine. this is supplied with ie-78k0k1-et. np-30mc emulation probe this probe is used to connect the in-circuit emulator to the target system and is designed for use with a 30-pin plastic ssop (mc-5a4 type). nspack30bk yspack30bk hspack30bk yq-guide conversion socket this conversion socket connects the np- 30mc to a target system board designed to mount a 30-pin plasti c ssop (mc-5a4 type). ? nspack30bk: socket for connecting target ? yspack30bk: socket for connecting emulator ? hspack30bk: cover for mounting device ? yq-guide: guide pin note ie-78k0k1-et is supplied with a power supply unit and pci bus interface adapter ie-70000-pci-if-a. it is also supplied with integrated debugger id78k0-n s and a device file as control software. remarks 1. np-30mc is a product of naito densei machida mfg. co., ltd. tel: +81-45-475-4191 naito densei machida mfg. co., ltd. 2. nspack30bk, yspack30bk, hspack30bk, and yq -guide are products of tokyo eletech corporation. for further information, contact daimaru kogyo co., ltd. tokyo electronics department (tel: +81-3-3820-7112) osaka electronics department (tel: +81-6-6244-6672) appendix a development tools user?s manual u15836ej5v0ud 444 a.5.3 when using in-circu it emulator qb-78k0kx1h qb-78k0kx1h note 1 in-circuit emulator this in-circuit emulator serves to debug hardware and software when developing application systems using the 78k0/kx1 and 78k0/kx1+. it corresponds to the integrated debugger (id78k0-qb). this emulator should be used in combination with a power supply unit and emulation probe, and the usb is used to connect this emulator to the host machine. qb-144-ca-01 note 2 check pin adapter this check pin adapter is used in waveform monitoring using the oscilloscope, etc. qb-80-ep-01t emulation probe this emulation probe is flexible type and used to connect the in-circuit emulator and target system. qb-30mc-ea-01t exchange adapter this exchange adapter is used to perform pin co nversion from the in-circuit emulator to target connector. qb-30mc-ys-01t space adapter this space adapter is used to adjust the height between the target system and in-circuit emulator. qb-30mc-yq-01t yq connector this yq connector is used to connect the target connector and exchange adapter. qb-30mc-hq-01t mount adapter this mount adapter is used to mount the target device with socket. qb-30mc-nq-01t target connector this target connector is used to mount on the target system. notes 1. the qb-78k0kx1h is supplied with a power supply unit, usb interface cable, and flash memory programmer pg-fpl (78k0/kx1 products are not supported). as control software, integrated debugger id78k0-qb is supplied. 2. under development remark the packed contents differ depending on the part number, as follows. ? qb-78k0kx1h-zzz: in-circuit emulator only ? qb-78k0kx1h-t30mc: in-circuit emulator and supplied products (emulation probe, exchange adapter, yq connector, and target connector) appendix a development tools user?s manual u15836ej5v0ud 445 a.6 debugging tools (software) this is a system simulator for the 78k /0 series. the sm78k0 is windows-based software. it is used to perform debugging at the c source level or assembler level while simulating the operation of the target system on a host machine. use of the sm78k0 allows the execution of application logical testing and performance testing on an independent basis from hardware development, thereby providing higher development efficiency and software quality. the sm78k0 should be used in combination with the device file (df780103) (sold separately). sm78k0 system simulator part number: s sm78k0 this debugger supports the in-circuit emulat ors for the 78k/0 series. the id78k0-ns and id78k0-qb are windows-based software. it has improved c-compatible debugging functions and can be display the results of tracing with the source program using an int egrating window function that associates the source program, disassemble display, and me mory display with the trace result. it should be used in combination with t he device file (sold separately). id78k0-ns (supporting in-circuit emulator ie-78k0-ns, ie-78k0-ns-a, ie-78k0k1-et), id78k0-qb (supporting in-circuit emulator qb-78k0kx1h) integrated debugger part number: s id78k0-ns, s id78k0-qb remark in the part number differs depending on the host machine and os used. s sm78k0 s id78k0-ns s id78k0-qb host machine os supply medium ab17 windows (japanese version) bb17 pc-9800 series, ibm pc/at compatibles windows (english version) cd-rom user?s manual u15836ej5v0ud 446 appendix b notes on target system design b.1 when using ie-78k0-ns, ie -78k0-ns-a, or ie-78k0k1-et the following show the conditions w hen connecting the emulation probe to the conversion adapter. follow the configuration below and consider t he shape of parts to be mounted on the target system when designing a system. figure b-1. distance between in-circu it emulator and conversion adapter 150 mm in-circuit emulator ie-78k0-ns, ie-78k0-ns-a, or ie-78k0k1-et emulation board ie-780148-ns-em1 target system cn1 78010x probe board emulation probe np-30mc conversion adapter: yspack30bk, nspack30bk board on end of np-30mc remarks 1. the np-30mc is a product of nait o densei machida mfg. co., ltd. 2. the yspack30bk and nspack30bk are produc ts of tokyo eletech corporation. appendix b notes on target system design user?s manual u15836ej5v0ud 447 figure b-2. connection condition of target system 31 mm 37 mm emulation probe np-30mc 13 mm emulation board ie-780148-ns-em1 15 mm 20 mm 5 mm board on end of np-30mc conversion adapter yspack30bk, nspack30bk guide pin yq-guide target system remarks 1. np-30mc is a product of naito densei machida mfg. co., ltd. 2. yspack30bk, nspack30bk, and yq-guide are products of tokyo eletech corporation. appendix b notes on target system design user?s manual u15836ej5v0ud 448 b.2 when using qb-78k0kx1h this section shows areas on the tar get system where component mounting is prohibited and areas where there are component mounting height restrictions. figure b-3. restriction area on target system 12.5 11.5 13.375 10 12.5 11.5 17.375 10 : exchange adapter area: com ponents up to 17.45 mm in height can be mounted note : emulation probe tip area: co mponents up to 24.45 mm in height can be mounted note note height can be regulated by usi ng space adapters (each adds 2.4 mm) user?s manual u15836ej5v0ud 449 appendix c register index c.1 register index (in al phabetical order with respect to register names) [a] a/d conversion resu lt regist er (a dcr) .......................................................................................... .............................194 a/d converter mode register (adm).............................................................................................. ..............................192 analog input channel specification re gister (ads) .............................................................................. ........................194 asynchronous serial interface control register 6 (asi cl6)...................................................................... ....................243 asynchronous serial interface operat ion mode regist er 0 (a sim0) ................................................................ .............213 asynchronous serial interface operat ion mode regist er 6 (a sim6) ................................................................ .............237 asynchronous serial interface recepti on error status regi ster 0 ( asis0)........................................................ .............215 asynchronous serial interface recepti on error status regi ster 6 ( asis6)........................................................ .............239 asynchronous serial interface transmi ssion status regi ster 6 ( asif6) ........................................................... .............240 [b] baud rate generator contro l register 0 (brg c0)................................................................................. ........................216 baud rate generator contro l register 6 (brg c6)................................................................................. ........................242 [c] capture/compare contro l register 00 (crc0 0).................................................................................... ........................117 clock monitor mode re gister (clm) .............................................................................................. ..............................316 clock selection regi ster 6 (c ksr6)............................................................................................. ................................241 [e] 8-bit timer compare re gister 50 (cr50)......................................................................................... ..............................150 8-bit timer coun ter 50 (t m50).................................................................................................. ....................................149 8-bit timer h compare register 00 (cmp00) ...................................................................................... ..........................164 8-bit timer h compare register 01 (cmp01) ...................................................................................... ..........................164 8-bit timer h compare register 10 (cmp10) ...................................................................................... ..........................164 8-bit timer h compare register 11 (cmp11) ...................................................................................... ..........................164 8-bit timer h mode re gister 0 (tmhmd0)......................................................................................... ...........................165 8-bit timer h mode re gister 1 (tmhmd1)......................................................................................... ...........................165 8-bit timer mode contro l register 50 (tmc 50) ................................................................................... ..........................152 external interrupt falling edg e enable regist er (egn).......................................................................... ........................287 external interrupt rising e dge enable regist er (egp)........................................................................... ........................287 [i] input switch contro l register (isc) ............................................................................................ ...................................244 internal memory size s witching regist er (ims) .................................................................................. ..........................339 interrupt mask flag re gister 0h (mk0h) ......................................................................................... .............................285 interrupt mask flag re gister 0l (mk0l)......................................................................................... ...............................285 interrupt mask flag re gister 1l (mk1l)......................................................................................... ...............................285 interrupt request flag register 0h (if0h) ...................................................................................... ...............................284 interrupt request flag register 0l (if 0l) ...................................................................................... ................................284 interrupt request flag register 1l (if 1l) ...................................................................................... ................................284 appendix c register index user?s manual u15836ej5v0ud 450 [l] low-voltage detection level selection regi ster (l vis).......................................................................... ........................329 low-voltage detecti on register (lvim).......................................................................................... ...............................328 [m] main clock mode register (mcm) ................................................................................................. ................................ 93 main osc control register (moc) ................................................................................................ ................................ 94 [o] oscillation stabilization time c ounter status r egister (ostc).................................................................. ...............95, 298 oscillation stabilization time select regi ster (osts).......................................................................... ....................96, 300 [p] port mode regist er 0 (p m0) ..................................................................................................... ..............................84, 120 port mode regist er 1 (p m1) ...................................................................................................84 , 153, 168, 217, 244, 271 port mode regist er 3 (p m3) ..................................................................................................... ..................................... 84 port mode regist er 12 (p m12) ................................................................................................... ................................... 84 port regist er 0 (p0)........................................................................................................... ............................................ 86 port regist er 1 (p1)........................................................................................................... ............................................ 86 port regist er 2 (p2)........................................................................................................... ............................................ 86 port regist er 3 (p3)........................................................................................................... ............................................ 86 port register 12 (p12) ......................................................................................................... .......................................... 86 port register 13 (p13) ......................................................................................................... .......................................... 86 power-fail comparison mo de register (pfm) ...................................................................................... .........................195 power-fail comparison th reshold regi ster (pft) ................................................................................. .........................195 prescaler mode regi ster 00 (prm00)............................................................................................. .............................119 priority specification fl ag register 0h (p r0h) ................................................................................. .............................286 priority specification fl ag register 0l (p r0l) ................................................................................. ..............................286 priority specification fl ag register 1l (p r1l) ................................................................................. ..............................286 processor clock cont rol regist er (pcc) ......................................................................................... ............................... 91 pull-up resistor opti on register 0 (pu0) ....................................................................................... ................................. 87 pull-up resistor opti on register 1 (pu1) ....................................................................................... ................................. 87 pull-up resistor opti on register 3 (pu3) ....................................................................................... ................................. 87 pull-up resistor opti on register 12 (pu 12) ..................................................................................... ............................... 87 [r] receive buffer regi ster 0 (rxb0) ............................................................................................... .................................212 receive buffer regi ster 6 (rxb6) ............................................................................................... .................................236 reset control flag register (resf) ............................................................................................. .................................314 ring-osc mode r egister (rcm) ................................................................................................... ............................... 92 [s] serial clock selection register 10 (csic10) .................................................................................... .............................270 serial i/o shift regi ster 10 (sio10) ........................................................................................... ...................................268 serial operation mode register 10 (csim 10) ..................................................................................... ..........................269 16-bit timer capture/compar e register 000 (c r000) .............................................................................. ......................112 16-bit timer capture/compar e register 010 (c r010) .............................................................................. ......................114 16-bit timer count er 00 (t m00)................................................................................................. ...................................112 16-bit timer mode contro l register 00 (tmc 00).................................................................................. ..........................115 appendix c register index user?s manual u15836ej5v0ud 451 16-bit timer output cont rol register 00 (t oc00)................................................................................ ...........................117 [t] timer clock selection register 50 (tcl50) ...................................................................................... ............................151 transmit buffer regi ster 10 (s otb10)........................................................................................... ..............................268 transmit buffer regi ster 6 (txb6).............................................................................................. ..................................236 transmit shift regi ster 0 (txs0) ............................................................................................... ...................................212 [w] watchdog timer enable register (wdte) .......................................................................................... ..........................182 watchdog timer mode r egister (wdtm) ............................................................................................ .........................181 appendix c register index user?s manual u15836ej5v0ud 452 c.2 register index (in alphabetical or der with respect to register symbol) [a] adcr: a/d conversion result regist er ........................................................................................... ......................194 adm: a/d converte r mode re gister............................................................................................... .....................192 ads: analog input channel specific ation re gister ............................................................................... ..............194 asicl6: asynchronous serial in terface control register 6....................................................................... ...............243 asif6: asynchronous serial interface transmission status register 6 ............................................................ ......240 asim0: asynchronous serial interf ace operation mode register 0................................................................. .......213 asim6: asynchronous serial interf ace operation mode register 6................................................................. .......237 asis0: asynchronous serial interface re ception error stat us regist er 0......................................................... ......215 asis6: asynchronous serial interface re ception error stat us regist er 6......................................................... ......239 [b] brgc0: baud rate generato r control r egister 0 .................................................................................. ...................216 brgc6: baud rate generato r control r egister 6 .................................................................................. ...................242 [c] cksr6: clock select ion register 6 .............................................................................................. ..........................241 clm: clock monito r mode re gister............................................................................................... .....................316 cmp00: 8-bit timer h compare regi ster 00 ....................................................................................... .....................164 cmp01: 8-bit timer h compare regi ster 01 ....................................................................................... .....................164 cmp10: 8-bit timer h compare regi ster 10 ....................................................................................... .....................164 cmp11: 8-bit timer h compare regi ster 11 ....................................................................................... .....................164 cr000: 16-bit timer capture/ compare regi ster 000............................................................................... ................112 cr010: 16-bit timer capture/ compare regi ster 010............................................................................... ................114 cr50: 8-bit timer co mpare regi ster 50.......................................................................................... ......................150 crc00: capture/compare control regi ster 00 ..................................................................................... ..................117 csic10: serial clock se lection regi ster 10 ..................................................................................... ........................270 csim10: serial operat ion mode regi ster 10...................................................................................... ......................269 [e] egn: external interrupt falling edge enabl e regi ster ........................................................................... ..............287 egp: external interrupt rising edge enabl e regi ster ............................................................................ ..............287 [i] if0h: interrupt reques t flag regi ster 0h ....................................................................................... ......................284 if0l: interrupt reques t flag regi ster 0l ....................................................................................... ......................284 if1l: interrupt reques t flag regi ster 1l ....................................................................................... ......................284 ims: internal memory si ze switchin g regi ster................................................................................... ................339 isc: input switch control r egist er............................................................................................. ........................244 [l] lvim: low-voltage de tection re gister........................................................................................... ......................328 lvis: low-voltage detection level selecti on regi ster ........................................................................... ..............329 [m] mcm: main clo ck mode re gister.................................................................................................. ........................ 93 appendix c register index user?s manual u15836ej5v0ud 453 mk0h: interrupt mask flag regist er 0h .......................................................................................... ......................285 mk0l: interrupt mask flag regist er 0l.......................................................................................... .......................285 mk1l: interrupt mask flag regist er 1l.......................................................................................... .......................285 moc: main osc c ontrol r egister ................................................................................................. ........................94 [o] ostc: oscillation stabilization ti me counter stat us regi ster ................................................................... .......95, 298 osts: oscillation stabilizati on time select register ........................................................................... ............96, 300 [p] p0: port r egister 0............................................................................................................ ................................86 p1: port r egister 1............................................................................................................ ................................86 p2: port r egister 2............................................................................................................ ................................86 p3: port r egister 3............................................................................................................ ................................86 p12: port r egister 12.......................................................................................................... ................................86 p13: port r egister 13.......................................................................................................... ................................86 pcc: processor cloc k control register .......................................................................................... ......................91 pfm: power-fail compar ison mode regist er ....................................................................................... ...............195 pft: power-fail comparis on threshol d regi ster .................................................................................. ..............195 pm0: port mode register 0...................................................................................................... ....................84, 120 pm1: port mode regist er 1.......................................................................................... 84, 153, 168 , 217, 244, 271 pm3: port mode register 3...................................................................................................... ............................84 pm12: port mode register 12.................................................................................................... ............................84 pr0h: priority specificat ion flag r egister 0h .................................................................................. .....................286 pr0l: priority specificat ion flag r egister 0l.................................................................................. ......................286 pr1l: priority specificat ion flag r egister 1l.................................................................................. ......................286 prm00: prescaler m ode register 00 .............................................................................................. .......................119 pu0: pull-up resistor option regi ster 0........................................................................................ ........................87 pu1: pull-up resistor option regi ster 1........................................................................................ ........................87 pu3: pull-up resistor option regi ster 3........................................................................................ ........................87 pu12: pull-up resistor option regi ster 12...................................................................................... ........................87 [r] rcm: ring-osc m ode register .................................................................................................... .......................92 resf: reset contro l flag re gister .............................................................................................. .........................314 rxb0: receive buffe r regist er 0 ................................................................................................ .........................212 rxb6: receive buffe r regist er 6 ................................................................................................ .........................236 [s] sio10: serial i/o sh ift register 10............................................................................................ ............................268 sotb10: transmit bu ffer regist er 10 ............................................................................................ ..........................268 [t] tcl50: timer clock sele ction regi ster 50....................................................................................... ......................151 tm00: 16-bit time r counter 00 .................................................................................................. ..........................112 tm50: 8-bit time r counte r 50 ................................................................................................... ...........................149 tmc00: 16-bit timer mode control regi ster 00................................................................................... ....................115 tmc50: 8-bit timer mode control re gister 50.................................................................................... .....................152 tmhmd0: 8-bit timer h mode regi ster 0.......................................................................................... .........................165 appendix c register index user?s manual u15836ej5v0ud 454 tmhmd1: 8-bit timer h mode regi ster 1 .......................................................................................... .........................165 toc00: 16-bit timer output control re gister 00 ................................................................................. .....................117 txb6: transmit buffe r register 6 ............................................................................................... .........................236 txs0: transmit shi ft register 0 ................................................................................................ ...........................212 [w] wdte: watchdog timer enable re gister........................................................................................... ....................182 wdtm: watchdog time r mode r egist er ............................................................................................. ...................181 user?s manual u15836ej5v0ud 455 appendix d list of cautions this appendix lists cautions described in this document. ?classification (hard/soft)? in table is as follows. hard: cautions for microcontroller internal/external hardware soft: cautions for software such as register settings or programs (1/20) chapter classification function details of function cautions page peripheral function: count clock, base clock the specifications of the peripheral f unctions (such as the timer, serial interface, and a/d converter) at v dd = 2.7 to 5.5 v remain unchanged. consequently when selecting the count cl ock or base cloc k of a peripheral function, set to satisfy the following conditions. ? v dd = 4.0 to 5.5 v: count clock or base clock 10 mhz ? v dd = 3.3 to 4.0 v: count clock or base clock 8.38 mhz ? v dd = 2.7 to 3.3 v: count clock or base clock 5 mhz ? v dd = 2.5 to 2.7 v: count clock or base clock 2.5 mhz p.17 operating frequency rating flash memory rewrite the flash memory within the ranges of f x = 2 to 10 mhz and v dd = 2.7 to 5.5 v as before. p.17 connect the ic (internally connected) pin directly to v ss . p.22 connect the av ss pin to v ss . p.22 chapter 1 hard pin processing ? connect the v pp pin to v ss during normal operation. p.22 ims: internal memory size switching register regardless of the internal memory capac ity, the initial values of internal memory size switching register (ims) of all products in the 78k0/kb1 are fixed (ims = cfh). therefore, set the value corresponding to each product as indicated below. pd780101: 42h pd780102: 04h pd780103: 06h pd78f0103: value corresponding to mask rom version p.39 sfr area: special function register do not access addresses to which sfrs are not assigned. p.45 chapter 3 soft memory space sp: stack pointer since reset input makes the sp contents undefined, be sure to initialize the sp before use. p.51 p10, p11, p12 when using p10/sck10 (/txd0), p11/si10 (/rxd0), and p12/so10 as general-purpose ports, do not write to serial clock sele ction register 10 (csic10). p.76 chapter 4 soft port function ? in the case of a 1-bit memory manipulat ion instruction, although a single bit is manipulated, the port is accessed as an 8-bit unit. therefore, on a port with a mixture of input and output pins, the output latch contents for pins specified as input ar e undefined, even for bits other than the manipulated bit. p.88 chapter 5 soft ring-osc rcm: ring-osc mode register make sure that bit 1 (mcs) of the main clock mode register (mcm) is 1 before setting rstop. p.92 appendix d list of cautions user?s manual u15836ej5v0ud 456 (2/20) chapter classification function details of function cautions page hard mcm: main clock mode register when the ring-osc clock is selected as the clock to be supplied to the cpu, the divided clock of the ring-osc oscillator output (f x ) is supplied to the peripheral hardware (f x = 240 khz (typ.)). operation of the peripheral hardware with the ring-osc clock c annot be guaranteed. therefore, when the ring-osc clock is selected as the cl ock supplied to the cpu, do not use peripheral hardware. in addition, stop the peripheral hardware before switching the clock supplied to the cpu from the x1 input clock to the ring- osc clock. note, however, that th e following peripheral hardware can be used when the cpu operates on the ring-osc clock. ? watchdog timer ? clock monitor ? 8-bit timer h1 when f r /2 7 is selected as the count clock ? peripheral hardware with an external clock selected as the clock source (except when the external count clock of tm00 is selected (ti000 valid edge)) p.93 moc: main osc control register make sure that bit 1 (mcs) of the main clock mode register (mcm) is 0 before setting mstop. p.94 after the above time has elapsed, the bi ts are set to 1 in order from most11 and remain 1. p.95 soft if the stop mode is entered and then released while the ring-osc clock is being used as the cpu clock, set the os cillation stabilization time as follows. ? desired ostc oscillation stabilization time oscillation stabilization time set by osts the x1 oscillation stabilization time counter counts up to the oscillation stabilization time set by osts. note, therefore, that only the status up to the oscillation stabilization time set by osts is set to ostc after stop mode is released. p.95 hard ostc: oscillation stabilization time counter status register the wait time when stop mode is released does not include the time after stop mode release until clock oscillation starts (?a? below) regardless of whether stop mode is released by reset input or interrupt generation. p.95 to set the stop mode when the x1 input clock is used as the cpu clock, set osts before executing the stop instruction. p.96 execute the osts setting after confirming that the oscillation stabilization time has elapsed as expected in the ostc. p.96 soft if the stop mode is entered and then released while the ring-osc clock is being used as the cpu clock, set the os cillation stabilization time as follows. ? desired ostc oscillation stabilization time oscillation stabilization time set by osts the x1 oscillation stabilization time counter counts up to the oscillation stabilization time set by osts. note, therefore, that only the status up to the oscillation stabilization time set by osts is set to ostc after stop mode is released. p.96 chapter 5 hard main clock osts: oscillation stabilization time select register the wait time when stop mode is released does not include the time after stop mode release until clock oscillation starts (?a? below) regardless of whether stop mode is released by reset input or interrupt generation. p.96 appendix d list of cautions user?s manual u15836ej5v0ud 457 (3/20) chapter classification function details of function cautions page x1 oscillator ? when using the x1 oscillator, wire as follows in the area enclosed by the broken lines in the figure 5-8 to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring wi th the other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. always make the ground point of the oscillator capacitor the same potential as v ss . do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. p.97 hard prescaler ? when the ring-osc clock is selected as the clock supplied to the cpu, the prescaler generates various clocks by dividing the ring-osc oscillator output (f x = 240 khz (typ.)). p.99 the rstop setting is valid only when ?can be stopped by software? is set for ring-osc by a mask option. p.104 ring-osc ? to calculate the maximum time, set f r = 120 khz. p.105 chapter 5 soft cpu clock ? setting the following values is prohibited when the cpu operates on the ring- osc clock. ? pcc2, pcc1, pcc0 = 0, 0, 1 (sett able only for standard products and (a) grade products) ? pcc2, pcc1, pcc0 = 0, 1, 0 ? pcc2, pcc1, pcc0 = 0, 1, 1 ? pcc2, pcc1, pcc0 = 1, 0, 0 p.106 set a value other than 0000h in cr000 in the mode in which clear & start occurs on a match of tm00 and cr000. p.113 soft if cr000 is set to 0000h in the free-running mode and in the clear mode using the valid edge of the ti000 pin, an interrupt request (inttm000) is generated when the value of cr000 changes from 0000h to 0001h following tm00 overflow (ffffh). moreover, inttm000 is generated after a match of tm00 and cr000 is detected, a valid edge of the ti010 pin is detected, and the timer is cleared by a one-shot trigger. p.113 when p01 is used as the valid edge input pin of ti010, it cannot be used as the timer output (to00). moreover, when p01 is used as to00, it cannot be used as the valid edge input pin of ti010. p.113 hard when cr000 is used as a capture register, read data is undefined if the register read time and capture trigger i nput conflict (the capture data itself is the correct value). if timer count stop and capture trigger input conflict, the captured data is undefined. p.113 pp.113, cr000: 16-bit timer capture/ compare register 000 do not rewrite cr000 during tm00 operation. 121, 126, 138 chapter 6 soft 16-bit timer/ event counter 00 (tm00) cr010: 16-bit timer capture/ compare register 010 if the cr010 register is cleared to 0000h, an interrupt request (inttm010) is generated when the value of cr010 changes from 0000h to 0001h following tm00 overflow (ffffh). moreover, inttm010 is generated after a match of tm00 and cr010 is detected, a valid edge of the ti000 pin is detected, and the timer is cleared by a one-shot trigger. p.114 appendix d list of cautions user?s manual u15836ej5v0ud 458 (4/20) chapter classification function details of function cautions page hard when cr010 is used as a capture register, read data is undefined if the register read time and capture trigger i nput conflict (the capture data itself is the correct value). if count stop input and capture trigger input conflict, the captured data is undefined. p.114 cr010: 16-bit timer capture/compare register 010 cr010 can be rewritten during tm00 operation. for details, see caution 2 in figure 6-15. p.114 16-bit timer counter 00 (tm00) starts operation at the moment tmc002 and tmc003 are set to values other than 0, 0 (operation stop mode), respectively. clear tmc002 and tmc003 to 0, 0 to stop operation. p.115 timer operation must be stopped before wr iting to bits other than the ovf00 flag. p.116 set the valid edge of the ti000/p00 pin using prescaler mode register 00 (prm00). p.116 tmc00: 16-bit timer mode control register 00 if any of the following modes: the mode in which clear & start occurs on match between tm00 and cr000, the mode in which clear & start occurs at the ti000 valid edge, or free-running mode is selected, when the set value of cr000 is ffffh and the tm00 value changes from ffffh to 0000h, the ovf00 flag is set to 1. p.116 timer operation must be stopped before setting crc00. p.117 soft when the mode in which clear & start occurs on a match between tm00 and cr000 is selected with 16-bit timer mode control register 00 (tmc00), cr000 should not be specified as a capture register. p.117 hard crc00: capture/compare control register 00 to ensure that the capture operation is performed properly, the capture trigger requires a pulse two cycles longer than the count clock selected by prescaler mode register 00 (prm00). p.117 timer operation must be stopped before setting other than toc004. p.118 lvs00 and lvr00 are 0 when they are read. p.118 ospt00 is automatically cleared afte r data is set, so 0 is read. p.118 soft do not set ospt00 to 1 other than in one-shot pulse output mode. p.118 hard a write interval of two cycles or more of the count clock selected by prescaler mode register 00 (prm00) is requir ed to write to ospt00 successively. p.118 do not set lvs00 to 1 before toe00, and do not set lvs00 and toe00 to 1 simultaneously. p.118 soft toc00: 16-bit timer output control register 00 do not make settings <1> and <2> below simultaneously. in addition, follow the setting procedure shown below. <1> setting of toc001, toc004, toe00, and ospe00: setting of timer output operation <2> setting of lvs00 and lvr00: setting of timer output f/f p.118 chapter 6 hard 16-bit timer/ event counter 00 (tm00) prm00: prescaler mode register 00 when the ring-osc clock is selected as the clock to be supplied to the cpu, the clock of the ring-osc oscillator is divided and supplied as the count clock. if the count clock is the ring-osc clock, the operat ion of 16-bit timer/event counter 00 is not guaranteed. when an external clock is used and when the ring-osc clock is selected and supplied to the cpu, the operation of 16-bit timer/event counter 00 is not guaranteed, either, because the ring-osc clock is supplied as the sampling clock to eliminate noise. p.119 appendix d list of cautions user?s manual u15836ej5v0ud 459 (5/20) chapter classification function details of function cautions page always set data to prm00 after stopping the timer operation. p.119 if the valid edge of ti000 is to be set for the count clock, do not set the clear & start mode using the valid edge of ti000 and the capture trigger. p.119 soft if the ti000 or ti010 pin is high level i mmediately after syst em reset, the rising edge is immediately detected after the rising edge or both the rising and falling edges are set as the valid edge(s) of the ti000 pin or ti010 pin to enable the operation of 16-bit timer counter 00 (t m00). care is therefore required when pulling up the ti000 or ti010 pin. however, when the ti000 or ti010 pin is high level and re-enabling operation after the operation has been stopped, the rising edge is not detected. p.120 hard prm00: prescaler mode register 00 when p01 is used as the ti010 valid edge input pin, it cannot be used as the timer output (to00), and when used as to00, it cannot be used as the ti010 valid edge input pin. p.120 cr010: 16-bit timer capture/compare register 010 to change the value of the duty factor (the value of the cr010 register) during operation, see caution 2 in figure 6- 15 ppg output operation timing. p.124 values in the following range should be set in cr000 and cr010: 0000h cr010 < cr000 ffffh p.125 cr000, cr010: 16-bit timer capture/compare registers 000, 010 the cycle of the pulse generated through ppg output (cr000 setting value + 1) has a duty of (cr010 setting va lue + 1)/(cr000 setting value + 1). p.125 ppg output in the ppg output operation, change the pulse width (rewrite cr010) during tm00 operation using the following procedure. <1> disable the timer output inversion operation by match of tm00 and cr010 (toc004 = 0) <2> disable the inttm010 interrupt (tmmk010 = 1) <3> rewrite cr010 <4> wait for 1 cycle of the tm00 count clock <5> enable the timer output inversion operation by match of tm00 and cr010 (toc004 = 1) <6> clear the interrupt request flag of inttm010 (tmif010 = 0) <7> enable the inttm010 interrupt (tmmk010 = 0) p.126 pulse width measurement to use two capture registers, set the ti000 and ti010 pins. p.127 external event counter when reading the external event counter count value, tm00 should be read. p.137 soft do not set the ospt00 bit to 1 while the one-shot pulse is being output. to output the one-shot pulse again, wait until the current one-shot pulse output is completed. p.140 chapter 6 hard 16-bit timer/ event counter 00 (tm00) one-shot pulse output: software trigger when using the one-shot pulse output of 16-bit timer/event counter 00 with a software trigger, do not change the level of the ti000 pin or its alternate- function port pin. because the external trigger is valid ev en in this case, the timer is cleared and started even at the level of the ti000 pin or its alternate-function port pin, resulting in the output of a pulse at an undesired timing. p.140 appendix d list of cautions user?s manual u15836ej5v0ud 460 (6/20) chapter classification function details of function cautions page do not set the cr000 and cr010 registers to 0000h. p.141 soft one-shot pulse output: software trigger 16-bit timer counter 00 starts operating as soon as the tmc003 and tmc002 bits are set to a value other than 00 (operation stop mode). p.142 hard even if the external trigger is gene rated again while the one-shot pulse is being output, it is ignored. p.142 do not set the cr000 and cr010 registers to 0000h. p.143 soft one-shot pulse output: external trigger 16-bit timer counter 00 starts operating as soon as the tmc002 and tmc003 bits are set to a value other than 00 (operation stop mode). p.144 hard timer start errors an error of up to one clock may occur in the time required for a match signal to be generated after timer start. this is because 16-bit timer counter 00 (tm00) is started asynchronously to the count clock. p.145 16-bit timer capture/compare registers 000, 010 setting in the mode in which clear & start occurs on match between tm00 and cr000, set 16-bit timer capture/compare registers 000, 010 (cr000, cr010) to other than 0000h. this means a 1-pulse count operation cannot be performed when 16-bit timer/event counter 00 is used as an external event counter. p.145 capture register data retention timing the values of 16-bit timer capture/compare registers 000 and 010 (cr000 and cr010) are not guaranteed after 16-bit timer/event counter 00 has been stopped. p.145 valid edge setting set the valid edge of the ti000 pin after setting bits 2 and 3 (tmc002 and tmc003) of 16-bit timer mode control register 00 (tmc00) to 0, 0, respectively, and then stopping timer oper ation. the valid edge is set using bits 4 and 5 (es000 and es001) of prescaler mode register 00 (prm00). p.145 one-shot pulse output: software trigger when a one-shot pulse is output, do not set the ospt00 bit to 1. do not output the one-shot pulse again until inttm000, which occurs upon a match with the cr000 register, or inttm010, which occurs upon a match with the cr010 register, occurs. p.145 soft one-shot pulse output: external trigger if the external trigger occurs again while a one-shot pulse is output, it is ignored. p.145 hard one-shot pulse output function when using the one-shot pulse output of 16-bit timer/event counter 00 with a software trigger, do not change the level of the ti000 pin or its alternate function port pin. because the external trigger is valid ev en in this case, the timer is cleared and started even at the level of the ti000 pin or its alternate function port pin, resulting in the output of a pulse at an undesired timing. p.145 the ovf00 flag is also set to 1 in the following case. if any of the following modes: the mode in which clear & start occurs on a match between tm00 and cr000, the mode in which clear & start occurs on a ti000 valid edge, or the free-running mode, is selected cr000 is set to ffffh. tm00 is counted up from ffffh to 0000h. p.146 chapter 6 soft 16-bit timer/ event counter 00 (tm00) operation of ovf00 flag even if the ovf00 flag is cleared befor e the next count clock (before tm00 becomes 0001h) after the occurrence of tm00 overflow, the ovf00 flag is re- set newly and clear is disabled. p.146 appendix d list of cautions user?s manual u15836ej5v0ud 461 (7/20) chapter classification function details of function cautions page conflicting operations when the read period of the 16-bit timer capture/compare register (cr000/cr010) and capture trigger input (cr000/cr010 used as capture register) conflict, capture trigger input has priority. the data read from cr000/cr010 is undefined. p.146 soft even if 16-bit timer counter 00 (tm00) is read, the value is not captured by 16- bit timer capture/compare register 010 (cr010). p.147 regardless of the cpu?s operation m ode, when the timer stops, the input signals to the ti000/ti010 pi ns are not acknowledged. p.147 timer operation the one-shot pulse output mode operates correctly only in the free-running mode and the mode in which clear & start occurs at the ti000 valid edge. in the mode in which clear & start occurs on a match between the tm00 register and cr000 register, one-shot pulse output is not possible because an overflow does not occur. p.147 if ti000 valid edge is specified as the count clock, a capture operation by the capture register specified as the trigger for ti000 is not possible. p.147 to ensure the reliability of the capture operation, the capture trigger requires a pulse two cycles longer than the count clock selected by prescaler mode register 00 (prm00). p.147 capture operation the capture operation is performed at the falling edge of the count clock. an interrupt request input (inttm000/inttm010), however, is generated at the rise of the next count clock. p.147 compare operation a capture operation may not be performed for cr000/cr010 set in compare mode even if a capture trigger has been input. p.147 if the ti000 or ti010 pin is high level immediately after sy stem reset and the rising edge or both the rising and falling edges are specified as the valid edge of the ti000 or ti010 pin to enable the 16-bit timer counter 00 (tm00) operation, a rising edge is detected imm ediately after the operation is enabled. be careful therefore when pulling up the ti000 or ti010 pin. however, when the ti000 or ti010 pin is high level, the rising edge is not detected at restart after the operation has been stopped. p.147 chapter 6 hard 16-bit timer/ event counter 00 (tm00) edge detection the sampling clock used to eliminate noise differs when the ti000 valid edge is used as the count clock and when it is used as a capture trigger. in the former case, the count clock is f x , and in the latter case the count clock is selected by prescaler mode register 00 (prm00). the capture operation is started only after a valid level is detected twice by sampling the valid edge, thus eliminating noise wi th a short pulse width. p.147 in the clear & start mode entered on a match of tm50 and cr50 (tmc506 = 0), do not write other values to cr50 during operation. p.150 soft cr50: 8-bit timer compare register 50 in pwm mode, make the cr50 rewrite peri od 3 count clocks of the count clock (clock selected by tcl50) or more. p.150 hard when the ring-osc clock is selected as the clock to be supplied to the cpu, the clock of the ring-osc oscillator is divided and supplied as the count clock. if the count clock is the ring-osc clock, the operat ion of 8-bit timer/event counter 50 is not guaranteed. p.151 chapter 7 soft 8-bit timer/ event counter 50 (tm50) tcl50: timer clock selection register 50 when rewriting tcl50 to other than the same data, stop the timer operation beforehand. p.151 appendix d list of cautions user?s manual u15836ej5v0ud 462 (8/20) chapter classification function details of function cautions page tcl50: timer clock selection register 50 be sure to clear bits 3 to 7 to 0. p.151 the settings of lvs50 and lvr50 are valid in other than pwm mode. p.153 do not make settings <1> to <4> below simultaneously. in addition, follow the setting procedure shown below. <1> setting of tmc501 and tmc506: setting of operation mode <2> setting of toe50 if enabling output: enabling timer output <3> setting of lvs50 and lvr50 (see caution 1): setting of timer f/f <4> setting of tce50 p.153 tmc50: 8-bit timer mode control register 50 stop operation before rewriting tmc506. p.153 interval timer/ square-wave output do not write other values to cr50 during operation. pp.154, 157 in pwm mode, make the cr50 rewrite peri od 3 count clocks of the count clock (clock selected by tcl50) or more. p.158 soft pwm output when reading from cr50 between <1> and <2 > in figure 7-11, the value read differs from the actual value (read va lue: m, actual value of cr50: n). p.160 chapter 7 hard 8-bit timer/ event counter 50 (tm50) timer start error an error of up to one clock may occur in the time required for a match signal to be generated after timer start. this is be cause 8-bit timer counter 50 (tm50) is started asynchronously to the count clock. p.160 cmp0n: 8-bit timer h compare register 0n cmp0n cannot be rewritten during timer count operation. p.164 soft cmp1n: 8-bit timer h compare register 1n in the pwm output mode be sure to set cmp1n when starting the timer count operation (tmhen = 1) after the timer count operation was stopped (tmhen = 0) (be sure to set again even if setting the same value to cmp1n). p.164 hard when the ring-osc clock is selected as the clock to be supplied to the cpu, the clock of the ring-osc oscillator is divided and supplied as the count clock. if the count clock is the ri ng-osc clock, the operation of 8-bit timer h0 is not guaranteed. p.167 when tmhe0 = 1, setting the other bits of tmhmd0 is prohibited. p.167 soft tmhmd0: 8-bit timer h mode register 0 in the pwm output mode, be sure to set 8-bit timer h compare register 10 (cmp10) when starting the timer count operation (tmhe0 = 1) after the timer count operation was stopped (tmhe0 = 0) (be sure to set again even if setting the same value to cmp10). p.167 hard when the ring-osc clock is selected as the clock to be supplied to the cpu, the clock of the ring-osc oscillator is divided and supplied as the count clock. if the count clock is the ri ng-osc clock, the operation of 8-bit timer h1 is not guaranteed (except when cks12, cks11, cks10 = 1, 0, 1 (f r /2 7 )). p.168 when tmhe1 = 1, setting the other bits of tmhmd1 is prohibited. p.168 chapter 8 soft 8-bit timers h0, h1 (tmh0, tmh1) tmhmd1: 8-bit timer h mode register 1 in the pwm output mode, be sure to set 8-bit timer h compare register 11 (cmp11) when starting the timer count operation (tmhe1 = 1) after the timer count operation was stopped (tmhe1 = 0) (be sure to set again even if setting the same value to cmp11). p.168 appendix d list of cautions user?s manual u15836ej5v0ud 463 (9/20) chapter classification function details of function cautions page hard in pwm output mode, three operation cloc ks (signal selected using the cksn2 to cksn0 bits of the tmhmdn registe r) are required to transfer the cmp1n register value after rewriting the register. p.173 be sure to set the cmp1n register when starting the timer count operation (tmhen = 1) after the timer count operation was stopped (tmhen = 0) (be sure to set again even if setting the sa me value to the cmp1n register). p.173 chapter 8 soft 8-bit timers h0, h1 (tmh0, tmh1) pwm output make sure that the cmp1n register setting value (m) and cmp0n register setting value (n) are within the following range. 00h appendix d list of cautions user?s manual u15836ej5v0ud 464 (10/20) chapter classification function details of function cautions page soft a/d conversion must be stopped before rewriting bits fr0 to fr2 to values other than the identical data. p.193 hard for the sampling time of the a/d conver ter and the a/d conversion start delay time, see (11) in 10.6 cautions for a/d converter. p.193 adm: a/d converter mode register if data is written to adm, a wait cycle is generated. for details, see chapter 29 cautions for wait. p.193 be sure to clear bits 2 to 7 of ads to 0. p.194 ads: analog input channel specification register if data is written to ads, a wait cycle is generated. for details, see chapter 29 cautions for wait. p.194 when writing to the a/d converter mode register (adm) and analog input channel specification register (ads), the contents of adcr may become undefined. read the conversion result following conversion completion before writing to adm and ads. using timing other than the above may cause an incorrect conversion result to be read. p.194 adcr: a/d conversion result register if data is read from adcr, a wait cycle is generated. for details, see chapter 29 cautions for wait. p.194 pfm: power-fail comparison mode register if data is written to pfm, a wait cycle is generated. for details, see chapter 29 cautions for wait. p.195 pft: power-fail comparison threshold register if data is written to pft, a wait cycl e is generated. for details, see chapter 29 cautions for wait. p.195 make sure the period of <1> to <3> is 14 appendix d list of cautions user?s manual u15836ej5v0ud 465 (11/20) chapter classification function details of function cautions page adcr read has priority. after the read operation, the new conversion result is written to adcr. p.204 soft conflicting operations adm or ads write has priority. adcr write is not performed, nor is the conversion end interrupt signal (intad) generated. p.204 noise countermeasures to maintain the 10-bit resolution, attention must be paid to noise input to the av ref and ani0 to ani3 pins. because the effect increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be connected externally, as s hown in figure 10-19, to reduce noise. p.205 the analog input pins (ani0 to ani3) are al so used as input port pins (p20 to p23). when a/d conversion is performed with any of ani0 to ani3 selected, do not access port 2 while conversion is in progress; otherwise the conversion resolution may be degraded. p.205 ani0/p20 to ani3/p23 if a digital pulse is applied to the pins adjacent to the pins currently being used for a/d conversion, the expected val ue of the a/d conversion may not be obtained due to coupling noise. therefor e, do not apply a pulse to the pins adjacent to the pin undergoing a/d conversion. p.205 input impedance of ani0 to ani3 pins in this a/d converter, the internal sampling capacitor is charged and sampling is performed for approx. one sixth of the conversion time. since only the leakage current flows other than during sampling and the current for charging the capacitor also flows during sampling, the input impedance fluctuates and has no meaning. to perform sufficient sampling, however, it is recommended to make the output impedance of the analog input source 10 k ? or lower, or attach a capacitor of around 100 pf to the ani0 to ani3 pins (see figure 10-19). p.205 hard av ref pin input impedance a series resistor string of several tens of k ? is connected between the av ref and av ss pins. therefore, if the output impedance of the reference voltage source is high, this will result in a series connection to the series resistor string between the av ref and av ss pins, resulting in a large reference voltage error. p.205 interrupt request flag (adif) the interrupt request flag (adif) is not cleared even if the analog input channel specification regi ster (ads) is changed. therefore, if an analog input pin is changed during a/d conversion, the a/d conversion result and adif for the pr e-change analog input may be set just before the ads rewrite. caution is ther efore required since, at this time, when adif is read immediately after the ads rewrite, adif is set despite the fact a/d conversion for the post-chan ge analog input has not finished. when a/d conversion is stopped and then resumed, clear adif before the a/d conversion operation is resumed. p.206 chapter 10 soft a/d converter conversion results just after a/d conversion start the first a/d conversion value immediatel y after a/d conversion starts may not fall within the rating range if the adcs bit is set to 1 within 14 s after the adce bit was set to 1, or if the adcs bi t is set to 1 with the adce bit = 0. take measures such as polling the a/d conversion end interrupt request (intad) and removing the fi rst conversion result. p.206 appendix d list of cautions user?s manual u15836ej5v0ud 466 (12/20) chapter classification function details of function cautions page soft a/d conversion result register (adcr) read operation when a write operation is performed to the a/d converter mode register (adm) and analog input channel specification regi ster (ads), the contents of adcr may become undefined. read the conv ersion result following conversion completion before writing to adm and ads. using a timing other than the above may cause an incorrect conversion result to be read. p.206 chapter 10 hard a/d converter a/d converter sampling time and a/d conversion start delay time the a/d converter sampling time differs depending on the set value of the a/d converter mode register (adm). a delay time exists until actual sampling is started after a/d converter operation is enabled. when using a set in which the a/d conver sion time must be strictly observed, care is required regarding the contents shown in figure 10-21 and table 10-3. p.207 if clock supply to se rial interface uart0 is not stopped (e.g., in the halt mode), normal operation continues. if clock supply to seri al interface uart0 is stopped (e.g., in the stop mode), each register stops operating, and holds the value immediately before cl ock supply was stopped. the t x d0 pin also holds the value immediat ely before clock supply was stopped and outputs it. however, the operation is not guaranteed after clock supply is resumed. therefore, reset the circuit so that power0 = 0, rxe0 = 0, and txe0 = 0. p.209 set power0 = 1 and then set txe0 = 1 (transmission) or rxe0 = 1 (reception) to start communication. p.209 uart mode txe0 and rxe0 are synchronized by the base clock (f xclk0 ) set by brgc0. to enable transmission or rec eption again, set txe0 or rxe0 to 1 at least two clocks of base clock after txe0 or rxe0 has been cleared to 0. if txe0 or rxe0 is set within two clocks of base clock, the transmission circuit or reception circuit may not be initialized. p.209 txs0: transmit shift register 0 do not write the next transmit data to txs0 before the transmission completion interrupt signal (intst0) is generated. p.212 at startup, set power0 to 1 and then set txe0 to 1. to stop the operation, clear txe0 to 0, and then clear power0 to 0. p.214 at startup, set power0 to 1 and then set rxe0 to 1. to stop the operation, clear rxe0 to 0, and then clear power0 to 0. p.214 set power0 to 1 and then set rxe0 to 1 while a high level is input to the rxd0 pin. if power0 is set to 1 and rxe0 is set to 1 while a low level is input, reception is started. p.214 txe0 and rxe0 are synchronized by the base clock (f xclk0 ) set by brgc0. to enable transmission or rec eption again, set txe0 or rxe0 to 1 at least two clocks of base clock after txe0 or rxe0 has been cleared to 0. if txe0 or rxe0 is set within two clocks of base clock, the transmission circuit or reception circuit may not be initialized. p.214 clear the txe0 and rxe0 bits to 0 before rewriting the ps01, ps00, and cl0 bits. p.214 make sure that txe0 = 0 when rewriting the sl0 bit. reception is always performed with ?number of stop bits = 1? , and therefore, is not affected by the set value of the sl0 bit. p.214 chapter 11 soft serial interface uart0 asim0: asynchronous serial interface operation mode register 0 be sure to set bit 0 to 1. p.214 appendix d list of cautions user?s manual u15836ej5v0ud 467 (13/20) chapter classification function details of function cautions page the operation of the pe0 bit differs depending on the set values of the ps01 and ps00 bits of asynchronous serial interface operation mode register 0 (asim0). p.215 only the first bit of the receive data is checked as the stop bit, regardless of the number of stop bits. p.215 if an overrun error occurs, the next receive data is not written to receive buffer register 0 (rxb0) but discarded. p.215 soft asis0: asynchronous serial interface reception error status register 0 if data is read from asis0, a wait cycle is generated. for details, see chapter 29 cautions for wait. p.215 hard when the ring-osc clock is selected as the clock to be supplied to the cpu, the clock of the ring-osc oscillator is divided and supplied as the count clock. if the base clock is the ring-osc clock, the operat ion of serial interface uart0 is not guaranteed. p.217 soft make sure that bit 6 (txe0) and bit 5 (rxe0) of the asim0 register = 0 when rewriting the mdl04 to mdl00 bits. p.217 h brgc0: baud rate generator control register 0 the baud rate value is the output clock of the 5-bit counter divided by 2. p.217 power0, txe0, rxe0: bits 7, 6, 5 of asim0 clear power0 to 0 after clearing txe0 and rxe0 to 0 to set the operation stop mode. to start the operation, set power0 to 1, and then set txe0 and rxe0 to 1. p.218 uart mode take relationship with the other party of communication when setting the port mode register and port register. p.219 uart transmission after transmit data is written to txs0, do not write the next transmit data before the transmission completion interrupt signal (intst0) is generated. p.222 be sure to read receive buffer register 0 (rxb0) even if a reception error occurs. otherwise, an overrun error will occur when the next data is received, and the reception error status will persist. p.223 reception is always performed with the ?number of stop bits = 1?. the second stop bit is ignored. p.223 uart reception be sure to read asynchronous serial inte rface reception error status register 0 (asis0) before reading rxb0. p.223 keep the baud rate error during transmission to within the permissible error range at the reception destination. p.226 error of baud rate make sure that the baud rate error dur ing reception satisfies the range shown in (4) permissible baud rate range during reception. p.226 chapter 11 soft serial interface uart0 permissible baud rate range during reception make sure that the baud rate error duri ng reception is within the permissible error range, by using the calculation expression shown below. p.228 hard the t x d6 output inversion function invert s only the transmission side and not the reception side. to use this functi on, the reception side must be ready for reception of inverted data. p.230 chapter 12 soft serial interface uart6 uart mode if clock supply to se rial interface uart6 is not stopped (e.g., in the halt mode), normal operation continues. if clock supply to seri al interface uart6 is stopped (e.g., in the stop mode), each register stops operating, and holds the value immediately before cl ock supply was stopped. the t x d6 pin also holds the value immediat ely before clock supply was stopped and outputs it. however, the operation is not guaranteed after clock supply is resumed. therefore, reset the circuit so that power6 = 0, rxe6 = 0, and txe6 = 0. p.230 appendix d list of cautions user?s manual u15836ej5v0ud 468 (14/20) chapter classification function details of function cautions page uart mode if data is continuously transmitte d, the communication timing from the stop bit to the next start bit is extended two operating clocks of the macro. however, this does not affect the result of communication because the reception side initializes the timing when it has detected a start bit. do not use the continuous transmission function if the interface is incorporated in lin. p.230 do not write data to txb6 when bit 1 (txbf6) of asynchronous serial interface transmission status register 6 (asif6) is 1. p.236 txb6: transmit buffer register 6 do not refresh (write the same value to) txb6 by software during a communication operation (when bit 7 (power6) and bit 6 (txe6) of asynchronous serial interface operati on mode register 6 (asim6) are 1 or when bit 7 (power6) and bit 5 (rxe6) of asim6 are 1). p.236 at startup, set power6 to 1 and then set txe6 to 1. to stop the operation, clear txe6 to 0 and then clear power6 to 0. p.238 at startup, set power6 to 1 and then set rxe6 to 1. to stop the operation, clear rxe6 to 0 and then clear power6 to 0. p.238 set power6 to 1 and then set rxe6 to 1 while a high level is input to the rxd6 pin. if power6 is set to 1 and rxe6 is set to 1 while a low level is input, reception is started. p.238 clear the txe6 and rxe6 bits to 0 before rewriting the ps61, ps60, and cl6 bits. p.238 fix the ps61 and ps60 bits to 0 when mounting the device on lin. p.238 make sure that txe6 = 0 when rewriting the sl6 bit. reception is always performed with ?the number of stop bits = 1?, and therefore, is not affected by the set value of the sl6 bit. p.238 asim6: asynchronous serial interface operation mode register 6 make sure that rxe6 = 0 when rewriting the isrm6 bit. p.238 the operation of the pe6 bit differs depending on the set values of the ps61 and ps60 bits of asynchronous serial interface operation mode register 6 (asim6). p.239 the first bit of the receive data is ch ecked as the stop bit, regardless of the number of stop bits. p.239 if an overrun error occurs, the next receive data is not written to receive buffer register 6 (rxb6) but discarded. p.239 asis6: asynchronous serial interface reception error status register 6 if data is read from asis6, a wait cycle is generated. for details, see chapter 29 cautions for wait. p.239 to transmit data continuously, write the first transmit data (first byte) to the txb6 register. be sure to check that the txbf6 flag is ?0?. if so, write the next transmit data (second byte) to the t xb6 register. if data is written to the txb6 register while the txbf6 flag is ?1?, the transmit data cannot be guaranteed. p.240 soft asif6: asynchronous serial interface transmission status register 6 to initialize the transmission unit upon co mpletion of continuous transmission, be sure to check that the txsf6 flag is ?0? after generation of the transmission completion interrupt, and then execute initia lization. if initia lization is executed while the txsf6 flag is ?1?, the transmit data cannot be guaranteed. p.240 chapter 12 hard serial interface uart6 cksr6: clock selection register 6 when the ring-osc clock is selected as the clock to be supplied to the cpu, the clock of the ring-osc oscillator is divided and supplied as the count clock. if the base clock is the ring-osc clock, the operat ion of serial interface uart6 is not guaranteed. p.241 appendix d list of cautions user?s manual u15836ej5v0ud 469 (15/20) chapter classification function details of function cautions page cksr6: clock selection register 6 make sure power6 = 0 when rewriting tps63 to tps60. p.241 soft make sure that bit 6 (txe6) and bit 5 (rxe6) of the asim6 register = 0 when rewriting the mdl67 to mdl60 bits. p.242 hard brgc6: baud rate generator control register 6 the baud rate value is the output clock of the 8-bit counter divided by 2. p.242 asicl6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (power6) and bit 6 (txe6) of asim6 = 1 or bit 7 (power6) and bit 5 (rxe6) of asim6 = 1). note, however, that communication is started by the refresh operation because bit 6 (sbrt6) of asicl6 is cleared to 0 when communication is completed (when an interrupt signal is generated). p.243 in the case of an sbf reception error, return the mode to the sbf reception mode again. the status of the sbrf6 flag is held (1). p.243 before setting the sbrt6 bit, make sure that bit 7 (power6) and bit 5 (rxe6) of asim6 = 1. p.243 the read value of the sbrt6 bit is always 0. sbrt6 is automatically cleared to 0 after sbf reception has been correctly completed. p.243 asicl6: asynchronous serial interface control register 6 before rewriting the dir6 and txdlv6 bits, clear the txe6 and rxe6 bits to 0. p.243 power6, txe6, rxe6: bits 7, 6, 5 of asim6 clear power6 to 0 after clearing txe6 and rxe6 to 0 to set the operation stop mode. to start the operation, set power6 to 1, and then set txe6 and rxe6 to 1. p.245 uart mode take relationship with the other party of communication when setting the port mode register and port register. p.246 parity types and operation fix the ps61 and ps60 bits to 0 when the device is incorporated in lin. p.249 the txbf6 and txsf6 flags of the asif6 register change from ?10? to ?11?, and to ?01? during continuous transmission. to check the status, therefore, do not use a combination of the txbf6 and txsf6 flags for judgment. read only the txbf6 flag when execut ing continuous transmission. p.251 continuous transmission when the device is incorporated in a li n, the continuous transmission function cannot be used. make sure that asyn chronous serial interface transmission status register 6 (asif6) is 00h before writing transmit data to transmit buffer register 6 (txb6). p.251 txbf6 during continuous transmission: bit 1 of asif6 to transmit data continuously, write the first transmit data (first byte) to the txb6 register. be sure to check that the txbf6 flag is ?0?. if so, write the next transmit data (second byte) to the t xb6 register. if data is written to the txb6 register while the txbf6 flag is ?1?, the transmit data cannot be guaranteed. p.251 to initialize the transmission unit upon co mpletion of continuous transmission, be sure to check that the txsf6 flag is ?0? after generation of the transmission completion interrupt, and then execute initia lization. if initia lization is executed while the txsf6 flag is ?1?, the transmit data cannot be guaranteed. p.251 chapter 12 soft serial interface uart6 txsf6 during continuous transmission: bit 1 of asif6 during continuous transmission, an ov errun error may occur, which means that the next transmission was completed before execution of intst6 interrupt servicing after transmission of one dat a frame. an overrun error can be detected by developing a program that can count the number of transmit data and by referencing the txsf6 flag. p.251 appendix d list of cautions user?s manual u15836ej5v0ud 470 (16/20) chapter classification function details of function cautions page be sure to read receive buffer register 6 (rxb6) even if a reception error occurs. otherwise, an overrun error will occur when the next data is received, and the reception error status will persist. p.255 reception is always performed with the ?number of stop bits = 1?. the second stop bit is ignored. p.255 normal reception be sure to read asynchronous serial inte rface reception error status register 6 (asis6) before reading rxb6. p.255 keep the baud rate error during transmission to within the permissible error range at the reception destination. p.262 generation of serial clock make sure that the baud rate error dur ing reception satisfies the range shown in (4) permissible baud rate range during reception. p.262 chapter 12 soft serial interface uart6 permissible baud rate range during reception make sure that the baud rate error duri ng reception is within the permissible error range, by using the calculation expression shown below. p.264 sotb10: transmit buffer register 10 do not access sotb10 when csot10 = 1 (during serial communication). p.268 sio10: serial i/o shift register 10 do not access sio10 when csot10 = 1 (during serial communication). p.268 soft csim10: serial operation mode register 10 be sure to clear bit 5 to 0. p.269 hard when the ring-osc clock is selected as the clock supplied to the cpu, the clock of the ring-osc oscillator is divided and supplied as the serial clock. at this time, the operation of serial interface csi10 is not guaranteed. p.271 do not write to csic10 while csie10 = 1 (operation enabled). p.271 clear ckp10 to 0 to use p10/sck10 (/txd0), p11/si10 (/rxd0), and p12/so10 as general-purpose port pins. p.271 csic10: serial clock selection register 10 the phase type of the data clock is type 1 after reset. p.271 3-wire serial i/o mode take relationship with the other part y of communication when setting the port mode register and port register. p.273 communication operation do not access the control register and data register when csot10 = 1 (during serial communication). p.275 chapter 13 soft serial interface csi10 so10 output if a value is written to trmd10, dap10, and dir10, the output value of so10 changes. p.279 if1l: interrupt request flag register be sure to clear bits 2 to 7 of if1l to 0. p.284 chapter 14 soft interrupt if0l, if0h, if1l: interrupt request flag registers when operating a timer, serial interfac e, or a/d converter after standby release, operate it once after clearing t he interrupt request flag. an interrupt request flag may be set by noise. p.284 appendix d list of cautions user?s manual u15836ej5v0ud 471 (17/20) chapter classification function details of function cautions page if0l, if0h, if1l: interrupt request flag registers when manipulating a flag of the interrupt request flag register, use a 1-bit memory manipulation instruction (clr 1). when describing in c language, use a bit manipulation instruction such as ?i f0l.0 = 0;? or ?_asm(?clr1 if0l, 0?);? because the compiled assembler must be a 1-bit memory manipulation instruction (clr1). if a program is described in c language using an 8-bit memory manipulation instruction such as ?if0l &= 0xfe;? and compiled, it becomes the assembler of three instructions. mov a, if0l and a, #0feh mov if0l, a in this case, even if the request flag of another bit of the same interrupt request flag register (if0l) is set to 1 at the timing between ?mov a, if0l? and ?mov if0l, a?, the flag is cleared to 0 at ?mov if0l, a?. therefore, care must be exercised when using an 8-bit memory manipulation instruction in c language. p.284 mk1l: interrupt mask flag register be sure to set bits 2 to 7 of mk1l to 1. p.285 pr1l: priority specification flag register be sure to set bits 2 to 7 of pr1l to 1. p.286 egp, egn: external interrupt rising, falling edge enable register select the port mode by clearing egpn and egnn to 0 because an edge may be detected when the external interrupt function is switched to the port function. p.287 software interrupt request acknowledgment do not use the reti instruction for restoring from the software interrupt. p.291 chapter 14 soft interrupt interrupt request hold the brk instruction is not one of the above-listed interrupt request hold instructions. however, the software interrupt activated by executing the brk instruction causes the ie flag to be cleared to 0. therefore, even if a maskable interrupt request is generated during execution of the brk instruction, the interrupt request is not acknowledged. p.295 soft the rstop setting is valid only when ?can be stopped by software? is set for ring-osc by a mask option. p.296 hard ? when shifting to the stop mode, be su re to stop the peripheral hardware operation before executing stop instruction. p.297 soft stop mode, halt mode the following sequence is recommended for operating current reduction of the a/d converter when the standby function is used: first clear bit 7 (adcs) of the a/d converter mode register (adm ) to 0 to stop the a/d conversion operation, and then execute the halt or stop instruction. p.297 chapter 15 hard standby function stop mode if the ring-osc oscillator is operating bef ore the stop mode is set, oscillation of the ring-osc clock cannot be stopped in the stop mode. however, when the ring-osc clock is used as the cp u clock, the cpu operation is stopped for 17/f r (s) after stop mode is released. p.297 appendix d list of cautions user?s manual u15836ej5v0ud 472 (18/20) chapter classification function details of function cautions page after the above time has elapsed, the bi ts are set to 1 in order from most11 and remain 1. p.299 soft if the stop mode is entered and then released while the ring-osc clock is being used as the cpu clock, set the os cillation stabilization time as follows. ? desired ostc oscillation stabilization time oscillation stabilization time set by osts the x1 oscillation stabilization time counter counts only during the oscillation stabilization time set by osts. theref ore, note that only the statuses during the oscillation stabilization time set by osts are set to ostc after stop mode has been released. p.299 hard ostc: oscillation stabilization time counter status register the wait time when stop mode is released does not include the time after stop mode release until clock oscillation starts (?a? below) regardless of whether stop mode is released by reset input or interrupt generation. p.299 to set the stop mode when the x1 input clock is used as the cpu clock, set osts before executing the stop instruction. p.300 execute the osts setting after confirming that the oscillation stabilization time has elapsed as expected in the ostc. p.300 soft if the stop mode is entered and then released while the ring-osc clock is being used as the cpu clock, set the os cillation stabilization time as follows. ? desired ostc oscillation stabilization time oscillation stabilization time set by osts the x1 oscillation stabilization time counter counts only during the oscillation stabilization time set by osts. theref ore, note that only the statuses during the oscillation stabilization time set by osts are set to ostc after stop mode has been released. p.300 hard osts: oscillation stabilization time select register the wait time when stop mode is released does not include the time after stop mode release until clock oscillation starts (?a? below) regardless of whether stop mode is released by reset input or interrupt generation. p.300 chapter 15 soft standby function stop mode setting and operating statuses because the interrupt request signal is used to clear the standby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is immediately cleared if set. thus, the stop mode is reset to the halt m ode immediately after execution of the stop instruction and the system returns to the operating mode as soon as the wait time set using the oscillation stabilization time select register (osts) has elapsed. p.304 for an external reset, input a low level for 10 s or more to the reset pin. p.308 during reset input, the x1 input clock and ring-osc clock stop oscillating. p.308 ? when the stop mode is released by a reset, the stop mode contents are held during reset input. however, the port pins become high-impedance, except for p130, which is set to low-level output. p.308 lvi circuit internal reset an lvi circuit internal reset doe s not reset the lvi circuit. p.309 hard reset timing due to watchdog timer overflow a watchdog timer internal reset resets the watchdog timer. p.310 chapter 16 soft reset function resf: reset control flag register do not read data via a 1-bit memo ry manipulation instruction. p.314 appendix d list of cautions user?s manual u15836ej5v0ud 473 (19/20) chapter classification function details of function cautions page once bit 0 (clme) is set to 1, it cannot be cleared to 0 except by reset input or the internal reset signal. p.316 chapter 17 soft clock monitor clm: clock monitor mode register if the reset signal is generated by the cloc k monitor, clme is cleared to 0 and bit 1 (clmrf) of the reset control fl ag register (resf) is set to 1. p.316 functions of power-on-clear circuit if an internal reset signal is generated in the poc circuit, the reset control flag register (resf) is cleared to 00h. p.322 chapter 18 soft power-on- clear circuit (poc) cautions for power-on-clear circuit in a system where the supply voltage (v dd ) fluctuates for a certain period in the vicinity of the poc detection voltage (v poc ), the system may be repeatedly reset and released from the reset status. in this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action. p.324 lvim: low-voltage detection register to stop lvi, follow either of the procedures below. ? when using 8-bit memory manipulati on instruction: write 00h to lvim. ? when using 1-bit memory manipulation instruction: clear lvion to 0 first and then clear lvie to 0. p.328 lvis: low-voltage detection level selection register be sure to clear bits 3 to 7 to 0. p.329 <1> must always be executed. when lvimk = 0, an interrupt may occur immediately after the processing in <5>. p.330 if ?poc used? is selected by a mask opt ion, procedures <3> and <4> are not required. p.330 when used as reset if supply voltage (v dd ) > detection voltage (v lvi ) when lvim is set to 1, an internal reset signal is not generated. p.330 when used as interrupt if ?poc used? is selected by a mask opt ion, procedures <3> and <4> are not required. p.332 chapter 19 soft low- voltage detector (lvi) cautions for low- voltage detector in a system where the supply voltage (v dd ) fluctuates for a certain period in the vicinity of the lvi detection voltage (v lvi ), the operation is as follows depending on how the low-voltage detector is used. (1) when used as reset the system may be repeatedly reset and released from the reset status. in this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking action (a) below. (2) when used as interrupt interrupt requests may be frequently generated. take action (b) below. p.334 hard ? there are differences in noise immunity and noise radiation between the flash memory and mask rom versions. when pr e-producing an application set with the flash memory version and then ma ss-producing it with the mask rom version, be sure to conduct sufficient evaluations for the commercial samples (not engineering samples) of the mask rom versions. p.338 the initial value of ims is ?setting prohibited (cfh)?. be sure to set the value of the relevant mask rom version at initialization. p.339 ims: internal memory size switching register when using a mask rom version, be sure to set ims to the value indicated in table 21-2. p.339 chapter 21 soft pd78f0 103 uart0, uart6 when uart0 or uart6 is select ed, the receive clock is calculated based on the reset command sent from the dedicated flash programmer after the v pp pulse has been received. p.355 appendix d list of cautions user?s manual u15836ej5v0ud 474 (20/20) chapter classification function details of function cautions page absolute maximum ratings product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. pp.371, 389, 405, 420 when using the x1 oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring wi th the other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. always make the ground point of the oscillator capacitor the same potential as v ss . do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. pp.372, 390, 407, 421 x1 oscillator since the cpu is started by the ring-osc after reset is released, check the oscillation stabilization time of the x1 input clock using the oscillation stabilization time counter status register (ostc). determine the oscillation stabilization time of the ostc register and oscillation stabilization time select register (osts) after sufficiently evaluating the oscillation stabilization time with the resonator to be used. pp.372, 390, 407, 421 for the resonator selection of the pd780101(a), 780102(a), and 780103(a) and oscillator constants, users are requi red to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. pp.373, 391 chapters 23, 24, 25, 26 hard electrical specifications recommended oscillator constants the oscillator constant s shown above are reference values based on evaluation in a specific environment by the resonator manufacturer. if it is necessary to optimize the oscillator characteristics in the actual application, apply to the resonator manufacturer for evaluation on the implementation circuit. the oscillation voltage and oscillation frequency only indicate the oscillator characteristic. use the 78k0/kb1 so that the internal operation conditions are within the specifications of the dc and ac characteristics. pp.373, 374, 375, 391, 392, 393 chapter 28 hard recommended soldering conditions ? do not use different soldering methods together (except for partial heating). pp.431, 432 user?s manual u15836ej5v0ud 475 appendix e revision history e.1 major revisions in this edition (1/2) page description throughout addition of description for expanded-specification products of standard products and (a) grade products p. 9 addition of differences between 78k0/kb1 and 78k0/kb1+ to introduction p. 17 addition of 1.1 expanded-specification products and co nventional products (standard products, (a) grade products only) p. 23 modification of 1.6 kx1 series lineup p. 91 addition of note to figure 5-2 format of processor clock control register (pcc) p. 92 addition of minimum instruction execution time with x1 input clock (at 12 mhz operation) and notes 2 and 3 to table 5-2 relationship between cpu clock and minimum instruction execution time p. 95 addition of oscillation stabilization time status (f xp = 12 mhz) to figure 5-6 format of oscillation stabilization time counter status register (ostc) p. 96 addition of oscillation stabilization time (f xp = 12 mhz) and cautions 1 and 2 to figure 5-7 format of oscillation stabilization time select register (osts) p. 105 modification of table 5-5 maximum time required to switch between ring-osc clock and x1 input clock and addition of note p. 106 addition of caution to table 5-6 maximum time required for cpu clock switchover p. 116 addition of description of appendix e revision history user?s manual u15836ej5v0ud 476 (2/2) page description p. 310 modification of figure 16-2 timing of reset by reset input p. 310 modification of figure 16-3 timing of reset due to watchdog timer overflow p. 311 modification of figure 16-4 timing of reset in stop mode by reset input p. 326 modification of note in 19.1 functions of low-voltage detector p. 329 addition of notes 3 and 4 to figure 19-3 format of low-voltage detection level selection register (lvis) p. 370 addition of chapter 23 electrical specifications (standard products, (a) grade products) (expanded-specification products) p. 388 p. 390 chapter 24 electrical specifications (standard products, (a) grade products) (conventional products) ? modification of descrip tion of target products ? addition of caution 2 to x1 oscillator characteristics p. 407 pp. 410, 411 chapter 25 electrical specifications ((a1) grade products) ? addition of caution 2 to x1 oscillator characteristics ? addition of value of supply current (i dd4 ) in ring-osc, halt mode to dc characteristics p. 421 p. 423 chapter 26 electrical specifications ((a2) grade products) ? addition of caution 2 to x1 oscillator characteristics ? addition of value of supply current (i dd4 ) in ring-osc, halt mode to dc characteristics p. 439 addition of (3) when using the in-circuit emulator qb-78k0kx1h to figure a-1 development tool configuration p. 444 addition of a.5.3 when using in-circuit emulator qb-78k0kx1h p. 448 addition of b.2 when using qb-78k0kx1h p. 455 addition of appendix d list of cautions appendix e revision history user?s manual u15836ej5v0ud 477 e.2 revision history of previous editions a history of the revisions up to this edition is shown below. ?applied to:? indicates the chapters to which the revision was applied. (1/9) edition description applied to: x1 input clock oscillation stabilization time 2 12 /f x , 2 14 /f x , 2 15 /f x , 2 16 /f x , 2 17 /f x ? ? ? ? ? appendix e revision history user?s manual u15836ej5v0ud 478 (2/9) edition description applied to: addition of 9.4.4 watchdog timer operation in halt mode (when ?ring-osc can be stopped by software? is selected by mask option) chapter 9 watchdog timer addition of (11) a/d converter sampling time and a/d conversion start delay time in 10.6 cautions for a/d converter chapter 10 a/d converter modification of reset value in 13.2 (2) serial i/o shift register 10 (sio10) chapter 13 serial interface csi10 modification of mani pulatable bit unit in 15.1.2 (1) oscillation stabilization time counter status register (ostc) modification of a/d converter item in table 15-2 operating statuses in halt mode chapter 15 standby function addition of 18.4 cautions for power-on-clear circuit chapter 18 power-on- clear circuit modification of figure 19-3 format of low-vo ltage detection level selection register (lvis) addition of 19.5 cautions for low-voltage detector chapter 19 low- voltage detector modification of the following contents in chapter 23 electrical specifications (target values) ? ? ? ? ? ? ? ? ? ? ? appendix e revision history user?s manual u15836ej5v0ud 479 (3/9) edition description applied to: modification of figure 6-1 block diagram of 16-bit timer/event counter 00 modification of cautions 1 and 2 in 6.2 (2) 16-bit timer capture/compare register 000 (cr000) , and modification of caution 1 in (3) 16-bit timer capture/compare register 010 (cr010) addition of caution 1 to figure 6-5 format of prescaler mode register 00 (prm00) addition of note to figure 6-8 interval timer configuration diagram modification of caution 1 of figure 6-10 control register settings for ppg output operation addition of figure 6-11 configuration of ppg output and figure 6-12 ppg output operation timing addition of note to figure 6-15 timing of pulse width measurement operation with free-running counter and one capture register (with both edges specified) , figure 6-18 timing of pulse width measurement operation with free-running counter (with both edges specified) , and figure 6-20 timing of pulse width measurement operation with free-running counter and two capture registers (with rising edge specified) modification of figure 6-24 configuration diagram of external event counter addition of 6.4.6 one-shot pulse output operation modification of figure 6-34 capture register data retention timing addition of description <2> to 6.5 (4) capture register data retention timing deletion of 6.5 (7) conflicting operations from old edition chapter 6 16-bit timer/event counter 00 modification of figure 7-1 block diagram of 8-bit timer/event counter 50 addition of caution 1 to figure 7-2 format of timer clock selection register 50 (tcl50) deletion of caution 1 of old edition and modification of caution 2 of figure 7-3 format of 8-bit timer mode control register 50 (tmc50) addition of remark to figure 7-8 pwm output operation timing chapter 7 8-bit timer/event counter 50 addition of square-wave output to 8.1 functions of 8-bit timers h0 and h1 , and modification of pwm pulse generator mode to pwm output modification of figure 8-1 block diagram of 8-bit timer h0 modification of figure 8-2 block diagram of 8-bit timer h1 addition of note and caution 1 to figure 8-3 format of 8-bit timer h mode register 0 (tmhmd0) addition of figure 8-5 format of port mode register 1 (pm1) modification of 8.4.1 operation as interval timer of old edition to 8.4.1 operation as interval timer/square-wave output modification of (a) basic operation of figure 8-7 timing of interval timer/square- wave output operation modification of descript ion of duty ratio in 8.4.2 (1) usage chapter 8 8-bit timers h0 and h1 addition of description to 10.2 (2) a/d conversion result register (adcr) , modification of description in (3) sample & hold circuit and (4) voltage comparator , and partial modification of caution 2 in (6) ani0 to ani3 pins 3rd modification of note 1 of figure 10-4 format of a/d converter mode register (adm) chapter 10 a/d converter appendix e revision history user?s manual u15836ej5v0ud 480 (4/9) edition description applied to: modification of figure 10-6 format of analog input channel specification register (ads) addition of description to 10.3 (3) power-fail comparison mode register (pfm) , and modification of figure 10-7 format of power-fail comparison mode register (pfm) modification of expressions in 10.4.2 input voltage and conversion results partial modification of description in 10.6 (5) ani0/p20 to ani3/p23 addition of description to 10.6 (9) conversion results just after a/d conversion start chapter 10 a/d converter modification of caution 3 of 11.1 functions of serial interface uart0 modification of figure 11-1 block diagram of serial interface uart0 modification of caution 3 in figure 11-2 format of asynchronous serial interface operation mode register 0 (asim0) and 11.4.2 (1) (a) asynchronous serial interface operation mode register 0 (asim0) addition of note and caution 1 to figure 11-4 format of baud rate generator control register 0 (brgc0) and 11.4.3 (2) (a) baud rate generator control register 0 (brgc0) addition of figure 11-5 format of port mode register 1 (pm1) and 11.4.2 (1) (c) port mode register 1 (pm1) modification of figure 11-11 configuration of baud rate generator modification of term in 11.4.3 (4) permissible baud rate range during reception and 12.4.3 (4) permissible baud rate range during reception as follows transfer rate appendix e revision history user?s manual u15836ej5v0ud 481 (5/9) edition description applied to: addition of items of software interrupt requests to table 14-5 interrupt request enabled for multiple interrupt servicing during interrupt servicing chapter 14 interrupt functions modification of table 15-1 relationship between halt and stop modes and clock modification of following items in table 15-2 operating statuses in halt mode and table 15-4 operating statuses in stop mode ? system clock ? 16-bit timer/event counter 00 ( table 15-2 only) ? 8-bit timer h0 ? watchdog timer ? serial interface uart0 ? serial interface uart6 chapter 15 standby function modification of figure 16-1 block diagram of reset function chapter 16 reset function addition of description to (4) and (5) of figure 17-3 timing of clock monitor chapter 17 clock monitor addition of note to description of 18.1 functions of power-on-clear circuit modification of figure 18-1 block diagram of power-on-clear circuit chapter 18 power-on- clear circuit addition of note to description of 19.1 functions of low-voltage detector modification of figure 19-1 block diagram of low-voltage detector addition of note 2 to figure 19-3 format of low-voltage detection level selection register (lvis) modification of figure 19-7 example of software processing of lvi interrupt chapter 19 low-voltage detector addition of note to description of chapter 20 mask options chapter 20 mask options revision of chapter 21 pd78f0103 (no change to 21.1 internal memory size switching register ) chapter 21 pd78f0103 revision of chapter 23 electrical specifications chapter 23 electrical specifications addition of chapter 25 recommended soldering conditions chapter 25 recommended soldering conditions addition of a.3 control software deletion of ?np-36gs? and ?ngs-30? from a.5 debugging tools (hardware) of old edition, and addition of in-circu it emulator ?ie-78k0k1-et? modification of ordering name of rx78k0 in a.7 embedded software appendix a development tools 3rd addition of appendix b notes on target system design appendix b notes on target system design addition of products pd780101(a2), 780102(a2), 780103(a2) modification of names of the followi ng special function registers (sfrs) ? ports 0 to 3, 12, and 13 port registers 0 to 3, 12, and 13 throughout addition of caution 3 to 1.4 pin configuration (top view) modification of 1.5 k1 family lineup modification of outline of timer in 1.7 outline of functions chapter 1 outline 4th addition of table 2-1 pin i/o buffer power supplies chapter 2 pin functions appendix e revision history user?s manual u15836ej5v0ud 482 (6/9) edition description applied to: addition of table 4-1 pin i/o buffer power supplies modification of table 4-3 port configuration deletion of input switch control register (isc) from and addition of port registers (p0 to p3, p12, and p13) to 4.3 registers controlling port function chapter 4 port functions modification of figure 5-1 block diagram of clock generator addition of cautions 2 and 3 to figure 5-6 format of oscillation stabilization time counter status register (ostc) modification of figure 5-8 external circuit of x1 oscillator and figure 5-9 examples of incorrect resonator connection modification of note in figure 5-12 switching from ring-osc clock to x1 input clock (flowchart) chapter 5 clock generator addition of figures ? figure 6-2 format of 16-bit timer counter 00 (tm00) ? figure 6-3 format of 16-bit timer capture/compare register 000 (cr000) ? figure 6-4 format of 16-bit timer capture/compare register 010 (cr010) modification of tables ? table 6-2 cr000 capture trigger and valid edges of ti000 and ti010 pins ? table 6-3 cr010 capture trigger and valid edge of ti000 pin (crc002 = 1) modification of caution 1 in 6.2 (3) 16-bit timer capture/compare register 010 (cr010) modification of caution 3 to figure 6-6 format of capture/compare control register 00 (crc00) addition of description to caution 5 and addition of caution 6 in figure 6-7 format of 16-bit timer output control register 00 (toc00) addition of register settings ? 6.4.1 interval timer operation ? 6.4.2 ppg output operations ? 6.4.3 pulse width measurement operations ? 6.4.4 external event counter operation ? 6.4.5 square-wave output operation ? 6.4.6 one-shot pulse output operation 4th addition of setting of prescaler mode register 00 (prm00) ? figure 6-10 control register settings for interval timer operation ? figure 6-13 control register settings for ppg output operation ? figure 6-17 control register settings for pulse width measurement with free-running counter and one capture register (when ti000 and cr010 are used) ? figure 6-20 control register settings for measurement of two pulse widths with free-running counter ? figure 6-22 control register settings for pulse width measurement with free-running counter and two capture registers (with rising edge specified) ? figure 6-24 control register settings for pulse width measurement by means of restart (with rising edge specified) ? figure 6-26 control register settings in external event counter mode (with rising edge specified) ? figure 6-29 control register settings in square-wave output mode ? figure 6-31 control register settings for one-shot pulse output with software trigger ? figure 6-33 control register settings for one-shot pulse output with external trigger (with rising edge specified) chapter 6 16-bit timer/event counter 00 appendix e revision history user?s manual u15836ej5v0ud 483 (7/9) edition description applied to: modification of figures ? figure 6-12 timing of interval timer operation ? figure 6-15 ppg output operation timing ? figure 6-34 timing of one-shot pulse output operation with external trigger (with rising edge specified) chapter 6 16-bit timer/event counter 00 addition of figures ? figure 7-2 format of 8-bit timer counter 50 (tm50) ? figure 7-3 format of 8-bit timer compare register 50 (cr50) modification of figure 7-7 interval timer operation timing modification of descri ption of frequency in 7.4.3 operation as square-wave output addition of description of cycle, active level width, and duty to 7.4.4 (1) pwm output basic operation chapter 7 8-bit timer/event counter 50 modification of figure 8-11 operation timing in pwm output mode chapter 8 8-bit timers h0 and h1 modification of figure 10-1 block diagram of a/d converter partial modification of description of 10.2 configuration of a/d converter addition of description of a/d conv ersion result register (adcr) to 10.3 registers used in a/d converter partial modification of description of 10.4.1 basic operations of a/d converter addition of description of successive approximation register (sar) to 10.4.2 input voltage and conversion results modification of caution 3 in ?when used as power-fail function? in 10.4.3 a/d converter operation mode modification of figure 10-21 timing of a/d converter sampling and a/d conversion start delay addition of description of (12) internal equivalent circuit to 10.6 cautions for a/d converter chapter 10 a/d converter modification of cautions 1 , 2 , 4 and addition of note 2 and caution 3 to figure 11- 2 format of asynchronous serial interface operation mode register 0 (asim0) modification of description of 11.4.1 operation stop mode modification of description of 11.4.2 asynchronous serial interface (uart) mode (1) registers used modification of table 11-3 cause of reception error chapter 11 serial interface uart0 ( pd780102, 780103, 78f0103 only) modification of figures ? figure 12-1 lin transmission operation ? figure 12-2 lin reception operation ? figure 12-3 port configuration for lin reception operation ? figure 12-4 block diagram of serial interface uart6 modification of cautions 1 , 2 and addition of note 2 and caution 3 to figure 12-5 format of asynchronous serial interface operation mode register 6 (asim6) addition of input switch control register (isc) to 12.3 registers controlling serial interface uart6 modification of description of 12.4.1 operation stop mode modification of description of 12.4.2 asynchronous serial interface (uart) mode (1) registers used modification of description of 12.4.2 (2) (d) continuous transmission 4th modification of table 12-3 cause of reception error chapter 12 serial interface uart6 appendix e revision history user?s manual u15836ej5v0ud 484 (8/9) edition description applied to: modification of figure 13-1 block diagram of serial interface csi10 addition of notes 2 and 3 to figure 13-2 format of serial operation mode register 10 (csim10) modification of caution 2 and addition of caution 3 to figure 13-3 format of serial clock selection register 10 (csic10) modification of description of 13.4.1 operation stop mode modification of description of 13.4.2 3-wire serial i/o mode (1) registers used addition of (5) so10 output to 13.4.2 3-wire serial i/o mode chapter 13 serial interface csi10 addition of caution 3 to figure 14-2 format of interrupt request flag register (if0l, if0h, if1l) chapter 14 interrupt functions modification of table 15-1 relationship between halt and stop modes and clock in old edition to table 15-1 relationship between operation clocks in each operation status addition of cautions 2 and 3 to figure 15-1 format of oscillation stabilization time counter status register (ostc) modification of table 15-2 operating statuses in halt mode chapter 15 standby function modification of figures ? ? ? ? ? ? ? ? ? appendix e revision history user?s manual u15836ej5v0ud 485 (9/9) edition description applied to: partial modification of description of 21.5.2 (2) malfunction of other device modification of description of 21.5.4 port pins partial modification of caution to 21.5.6 power supply chapter 21 ? ? ? ? ? ? ? ? ? |
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