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WS1103 cdma cell 3x3 power amplifer module (824-849 mhz) data sheet functional block diagram v cc2 (8) v cont (3) v ref (4) rf output (7) da input ma tch inter st age ma tch output ma tch module mmi c pa rf input (2) v cc1 (1) bias circuit & control logic description the WS1103 is a cdma(code division multiple access) power amplifer module designed for handsets operat - ing in the 824-849 mhz bandwidth. the WS1103 features coolpam circuit technology that ofers state-of-the-art reliability, temperature stability and ruggedness. digital mode control of coolpam reduces current consumption, which enables extended talk time of mobile devices. the WS1103 meets stringent cdma linearity requirements to and beyond 28 dbm output power. the 3 mm x 3 mm form factor 8-pin surface mount package is self contained, incorporating 50 ohm input and output matching networks. features ? excellent linearity ? low quiescent current ? high efciency pae at 28 dbm: 41.2% pae at 16 dbm: 17.7% ? 8-pin surface mounting package 3 mm x 3 mm x 1.0 mm ? internal 50 ohm matching networks for both rf input and output ? rohs compliant applications ? digital cdma cellular ? wireless local loop order information part number no. of devices container WS1103-tr1 1,000 7 tape and reel WS1103-blk 100 bulk free datasheet http:///
2 table 1. absolute maximum ratings [1] parameter symbol min. nominal max. unit rf input power pin C C 10.0 dbm dc supply voltage vcc 0 3.4 5.0 v reference voltage vref 0 2.85 3.3 v control voltage vcont 0 2.85 3.3 v storage temperature tstg -55 C +125 c table 2. recommended operating conditions parameter symbol min. nominal max. unit dc supply voltage vcc 3.2 3.4 4.2 v dc reference voltage vref 2.75 2.85 2.95 v mode control voltage C high power mode C low power mode vcont vcont 0 2.0 0 2.85 0.5 3.0 v v operating frequency fo 824 849 mhz ambient temperature ta -30 25 85 c table 3. power range truth table power mode symbol vref vcont [2] range high power mode pr2 2.85 low ~ 28 dbm low power mode pr1 2.85 high ~ 16 dbm shut down mode C 0 - C notes: 1. no damage assuming only one parameter is set at limit at a time with all other parameters set at or below nominal value. 2. high (2.0 C 3.0 v), low (0.0 v C 0.5 v). free datasheet http:///
3 table 4. electrical characteristics for cdma mode (vcc = 3.4 v, vref = 2.85 v, t = 25c, zin/zout = 50 ohm) characteristics symbol condition min. typ. max. unit operating frequency range f 824 C 849 mhz gain gain_hi high power mode, pout =28 dbm 24 29.5 db gain_low low power mode, pout = 16 dbm 14 17.5 db power added efciency pae_hi high power mode, pout = 28 dbm 36 41.2 % pae_ low low power mode, pout = 16 dbm 13.6 17.7 % total supply current icc_hi high power mode, pout = 28 dbm 450 515 ma icc_ low low power mode, pout = 16 dbm 65 85 ma quiescent current iq_hi high power mode 93 125 ma iq_ low low power mode 13 25 ma reference current iref_hi high power mode, pout = 28 dbm 2 7 ma iref_low low power mode, pout = 16 dbm 3 8 ma control current icont low power mode, pout = 16 dbm 0.2 1 ma total current in power-down mode ipd vref = 0 v 0.2 5 a adjacent 900 khz ofset acpr1_hi high power mode, pout = 28 dbm -55 -47 dbc channel 1.98 mhz ofset acpr2_hi -59 -57 dbc power ratio 900 khz ofset acpr1_ low low power mode, pout = 16 dbm -59 -47 dbc 1.98 mhz ofset acpr2_ low -66 -57 dbc harmonic second 2f0 high power mode, pout = 28 dbm -39 -30 dbc suppression third 3f0 -56 -40 dbc input vswr vswr 2:1 2.5:1 stability (spurious output) s vswr 6:1, all phase -60 dbc noise power in rx band rxbn -136.5 -132 dbm/hz ru no damage ruggedness pout <28 dbm, pin <10 dbm, all phase 10:1 vswr high power mode free datasheet http:///
4 characteristics data (vcc = 3.4 v, vref = 2.85 v, t = 25c, zin/zout = 50 ohm) figure 4. adjacent channel power ratio 1 vs. output power figure 1. total current vs. output power figure 2. gain vs. output power figure 3. power added efciency vs. output power figure 5. adjacent channel power ratio 2 vs. output power 0 50 10 0 15 0 20 0 25 0 30 0 35 0 40 0 45 0 50 0 0 5 10 15 20 25 30 po ut (d bm ) current (ma) 824 mhz 836.5 mhz 849 mhz 10 15 20 25 30 35 0 5 10 15 20 25 30 pout (dbm) gain (db) 824 mhz 836.5 mhz 849 mhz 0 20 15 10 5 25 30 35 45 40 0 5 10 15 20 25 30 pout (dbm) pae (%) 824 mhz 836.5 mhz 849 mhz -75 -55 -60 -65 -70 -50 -45 -40 0 5 10 15 20 25 30 pout (dbm) acpr1 (dbc) 824 mhz 836.5 mhz 849 mhz -75 -80 -85 -55 -60 -65 -70 -50 -45 0 5 10 15 20 25 30 pout (dbm) acpr2 (dbc) 824 mhz 836.5 mhz 849 mhz free datasheet http:///
5 evaluation board description figure 6. evaluation board schematic figure 7. evaluation board assembly diagram 1 vcc1 2 rf in 3 vcont 4 vref vcc2 8 rf out 7 gnd 6 gnd 5 vref vcont rf in vcc1 vcc2 rf out c3 100pf c2 100pf c5 4.7uf c1 330pf c4 4.7uf 0 ohm r1 1103 pyyww aaaaa free datasheet http:///
6 figure 8. package dimensional drawing and pin descriptions (all dimensions are in millimeters) package dimensions and pin descriptions figure 9. marking specifcations 0.80 0.40 1.40 1 2 3 3 0.1 pin 1 mark 3 0.1 top view side view x-ray bottom view pin descriptions 4 8 7 6 5 0.7 0.40 1.0 0.1 0.60 0.40 3.0 1.20 1.40 2.80 0.15 x 45 r 0.10 pin # name description 1 vcc1 supply voltage 2 rf in rf input 3 vcont control voltage 4 vref reference voltage 5 gnd ground 6 gnd ground 7 rf out rf output 8 vcc2 supply voltage pin 1 mark manufacturing part number lot number p manufacturing info yy manufacturing year ww work week aaaaa assembly lot 1103 pyyww aaaaa free datasheet http:///
7 peripheral circuit in handset figure 10. peripheral circuit calibration calibration procedure is shown in figure 11. two calibration tables, high mode and low mode respective - ly, are required for cool pam, which is due to gain difer - ence in each mode. for continuous output power at the mode change points, the input power should be adjust - ed according to gain step during the mode change. ofset value (diference between rising point and falling point) ofset value, which is the diference between the rising point (output power where pa mode changes from low mode to high mode) and falling point (output power where pa mode changes from high mode to low mode), should be adopted to prevent system oscillation. 3 to 5 db is recommended for hysteresis. average current & talk time probability distribution function implies that what is important for longer talk time is the efciency of low or medium power range rather than the efciency at full power. WS1103 idle current is 13 ma and operating current at 16 dbm is 65 ma at nominal condition. this pa with low current consumption prolongs talk time by no less than 30 minutes compared to other pas. figure 11. calibration procedure figure 12. setting of ofset between rising and falling power figure 13. cdma power distribution function tx_agc low mode high mode min. pw r falling rising max. pw r pout gain low mode high mode falling rising pout 5.00 4.50 4.00 3.50 3.00 2.50 2.00 1.50 1.00 0.50 0 700 600 cdg urban conventional pa m digitally controlled pa m cool pa m cdg suburban 500 400 300 200 100 0 -50 -40 -30 -20 -10 pa out (dbm) 0 pdf (%) current (ma) 10 20 30 vcc1 vcc2 rf in rf out vcont gnd gnd vref duplexer tx filter msm pa_ro pa_on rf out output matching circuit rf in WS1103 c1 c8 c7 c6 l1 c2 v batt c5 c4 +2.85 v c 3 notes: ? recommended voltage for vref is 2.85 v. ? place c1 near to vref pin. ? place c3 and c4 close to pin 1 (vcc1) and pin 10 (vcc2). these capacitors can affect the rf performance. ? use 50 ? transmission line between pam and duplexer and make it as short as possible to reduce conduction loss. ? -type circuit topology is good to use for matching circuit between pa and duplexer. notes: ? recommended voltage for vref is 2.85 v. ? place c1 near to vref pin. ? place c3 and c4 close to pin 1 (vcc1) and pin 8 (vcc2). these capacitors can afect the rf performance. ? use 50 w transmission line between pam and duplexer and make it as short as possible to reduce conduction loss. ? -type circuit topology is good to use for matching circuit between pa and duplexer. free datasheet http:///
8 figure 14. metallization figure 15. solder mask opening pcb design guidelines the recommended ws1403 pcb land pattern is shown in figure 14 and figure 15. the substrate is coated with solder mask between the i/o and conductive paddle to protect the gold pads from short circuit that is caused by solder bleeding/bridging. stencil design guidelines a properly designed solder screen or stencil is required to ensure optimum amount of solder paste is deposited onto the pcb pads. the recommended stencil layout is shown in figure 16. reducing the stencil opening can potentially generate more voids. on the other hand, stencil openings larger than 100% will lead to excessive solder paste smear or bridging across the i/o pads or conductive paddle to adjacent i/o pads. considering the fact that solder paste thickness will directly afect the quality of the solder joint, a good choice is to use laser cut stencil composed of 0.100 mm (4 mils) or 0.127 mm (5 mils) thick stainless steel which is capable of producing the required fne stencil outline. 0.1 0.25 0.6 0.4 0.8 ? 0.3 mm on 0.5 mm pitch 0.8 0.5 0.7 0.55 1.4 1.325 0.4 0.6 0.5 0.8 1.05 1.1 figure 16. solder paste stencil aperture free datasheet http:///
9 figure 17. tape and reel format C 3 mm x 3 mm tape and reel information p0 y y p2 (1) p10 (3) d0 dimensions no ta tion millimeters a0 3.40 0.10 b0 3.40 0.10 k0 1.35 0.10 d0 1.55 0.05 d1 1.60 0.10 p0 4.00 0.10 p1 8.00 0.10 p2 2.00 0.05 p10 40.00 0.20 e 1.75 0.10 f 5.50 0.05 w 12.00 0.30 t 0.30 0.05 x x p1 (2) d1 f (1) w a section x - x section y - y a0 k0 0.1 r 0.5 r 1.0 det ail a t b0 1103 pyyww aaaaa f free datasheet http:///
10 reel drawing figure 18. plastic reel format (all dimensions are in millimeters) free datasheet http:///
11 table 6. moisture classifcation level and floor life msl level floor life (out of bag) at factory ambient = < 30c/60% rh or as stated 1 unlimited at = < 30c/85% rh 2 1 year 2a 4 weeks 3 168 hours 4 72 hours 5 48 hours 5a 24 hours 6 mandatory bake before use. after bake, must be refowed within the time limit specifed on the label note: 1. the msl level is marked on the msl label on each shipping bag. handling and storage esd (electrostatic discharge) electrostatic discharge occurs naturally in the environ - ment. with the increase in voltage potential, the outlet of neutralization or discharge will be sought. if the ac - quired discharge route is through a semiconductor device, destructive damage will result. esd countermeasure methods should be developed and used to control potential esd damage during handling in a factory environment at each manufacturing site. msl (moisture sensitivity level) plastic encapsulated surface mount package is sensitive to damage induced by absorbed moisture and temperature. avago technologies follows jedec standard j-std 020b. each component and package type is classifed for moisture sensitivity by soaking a known dry package at various temperatures and relative humidity, and times. after soak, the components are subjected to three consecutive simulated refows. the out of bag exposure time maximum limits are determined by the classifcation test describe below which corresponds to a msl classifcation level 6 to 1 according to the jedec standard ipc/jedec j-std-020b and j-std-033. WS1103 is msl3. thus, according to the j-std-033 p.11 the maximum manufacturers exposure time (met) for this part is 168 hours. after this time period, the part would need to be removed from the reel, de-taped and then re-baked. msl classifcation refow temperature for the WS1103 is targeted at 260c +0/-5c. figure 19 and table 7 show typical smt profle for maximum temperature of 260 +0/-5c. table 5. esd classifcation pin # name description hbm cdm classifcation 1 vcc1 supply voltage 2000 v 200 v class 2 2 rfin rf input 2000 v 200 v class 2 3 vcont control voltage 2000 v 200 v class 2 4 vref reference voltage 2000 v 200 v class 2 5 gnd ground 2000 v 200 v class 2 6 gnd ground 2000 v 200 v class 2 7 rf out rf output 2000 v 200 v class 2 8 vcc2 supply voltage 2000 v 200 v class 2 note: 1. module products should be considered extremely esd sensitive. free datasheet http:///
12 figure 19. typical smt refow profle for maximum temperature = 260 +0/-5c tim e tempera ture tp t 25 c to peak ts prehea t t l t p ts max ts min t l critical zone t l to t p ramp up ramp dow n 25 table 7. typical smt refow profle for maximum temperature = 260 +0/-5c profle feature sn-pb solder pb-free solder average ramp-up rate (tl to tp) 3c/sec max 3c/sec max preheat - temperature min (tsmin) - temperature max (tsmax) - time (min to max) (ts) 100c 150c 60-120 sec 150c 200c 60-180 sec tsmax to tl - ramp-up rate 3c /sec max time maintained above: - temperature (tl) - time (tl) 183c 60-150 sec 217c 60-150 sec peak temperature (tp) 240 +0/-5c 260 +0/-5c time within 5c of actual peak temperature (tp) 10-30 sec 20-40 sec ramp-down rate 6c /sec max 6c /sec max time 25c to peak temperature 6 min max. 8 min max. free datasheet http:///
13 storage condition packages described in this document must be stored in sealed moisture barrier, antistatic bags. shelf life in a sealed moisture barrier bag is 12 months at <40c and 90% relative humidity (rh) j-std-033 p.7. out-of-bag time duration after unpacking the device must be soldered to the pcb within 168 hours as listed in the j-std-020b p.11 with factory conditions <30c and 60% rh. baking it is not necessary to re-bake the part if both conditions (storage conditions and out-of bag conditions) have been satisfed. baking must be done if at least one of the conditions above have not been satisfed. the baking conditions are 125c for 12 hours j-std-033 p.8. caution tape and reel materials typically cannot be baked at the temperature described above. if out-of-bag exposure time is exceeded, parts must be baked for a longer time at low temperatures, or the parts must be de-reeled, de-taped, re-baked and then put back on tape and reel. (see moisture sensitive warning label on each shipping bag for information of baking). board rework component removal, rework and remount if a component is to be removed from the board, it is recommended that localized heating be used and the maximum body temperatures of any surface mount component on the board not exceed 200c. this method will minimize moisture related component damage. if any component temperature exceeds 200c, the board must be baked dry per 4-2 prior to rework and/or component removal. component temperatures shall be measured at the top center of the package body. any smd packages that have not exceeded their foor life can be exposed to a maximum body temperature as high as their specifed maximum refow temperature. removal for failure analysis not following the above requirements may cause moisture/refow damage that could hinder or com- pletely prevent the determination of the original failure mechanism. baking of populated boards some smd packages and board materials are not able to withstand long duration bakes at 125c. examples of this are some fr-4 materials, which cannot withstand a 24 hr bake at 125c. batteries and electrolytic capacitors are also temperature sensitive. with component and board temperature restrictions in mind, choose a bake temperature from table 4-1 in j-std 033; then determine the appropriate bake duration based on the component to be removed. for additional considerations see ipc-7711 andipc-7721. derating due to factory environmental conditions factory foor life exposures for smd packages removed from the dry bags will be a function of the ambient environmental conditions. a safe, yet conservative, handling approach is to expose the smd packages only up to the maximum time limits for each moisture sensitivity level as shown in table 7. this approach, however, does not work if the factory humidity or temperature is greater than the testing conditions of 30c/60% rh. a solution for addressing this problem is to derate the exposure times based on the knowledge of moisture difusion in the component package materials ref. jesd22-a120). recommended equivalent total foor life exposures can be estimated for a range of humidities and temperatures based on the nominal plastic thickness for each device. table 8 lists equivalent derated foor lives for humidities ranging from 20-90% rh for three temperatures, 20c, 25c, and 30c. this table is applicable to smds molded with novolac, biphenyl or multifunctional epoxy mold compounds. the following assumptions were used in calculating table 8: 1. activation energy for difusion = 0.35ev (smallest known value). 2. for 60% rh, use difusivity = 0.121exp ( -0.35ev/kt) mm2/s (this used smallest known difusivity @ 30c). 3. for >60% rh, use difusivity = 1.320exp ( -0.35ev/kt) mm2/s (this used largest known difusivity @ 30c). free datasheet http:///
14 table 8. recommended equivalent total floor life (days) @ 20c, 25c and 30c for ics with novolac, biphenyl and multifunctional epoxies (refow at same temperature at which the component was classifed) maximum percent relative humidity package type and body thickness moisture sensitivity level 5% 10% 20% 30% 40% 50% 60% 70% 80% 90% body thickness 3.1 mm including pqfps >84 pin, plccs (square) all mqfps or all bgas 1 mm level 2a 60 78 103 41 53 69 33 42 57 28 36 47 10 14 19 7 10 13 6 8 10 30c 25c 20c level 3 10 13 17 9 11 14 8 10 13 7 9 12 7 9 12 5 7 10 4 6 8 4 5 7 30c 25c 20c level 4 5 6 8 4 5 7 4 5 7 4 5 7 3 5 7 3 4 6 3 3 5 2 3 4 2 3 4 30c 25c 20c level 5 4 5 7 3 5 7 3 4 6 2 4 5 2 3 5 2 3 4 2 2 3 1 2 2 1 2 3 30c 25c 20c level 5a 2 3 5 1 2 4 1 2 3 1 2 3 1 2 3 1 2 2 1 1 2 1 1 2 1 1 2 30c 25c 20c body 2.1 mm thickness <3.1 mm including plccs (rectangular) 18-32 pin soics (wide body) soics 20 pins, pqfps 80 pins level 2a 86 148 39 51 69 28 27 49 4 6 8 3 4 5 2 3 4 30c 25c 20c level 3 19 25 32 12 15 19 9 12 15 8 10 13 7 9 12 3 5 7 2 3 5 2 3 4 30c 25c 20c level 4 7 9 11 5 7 9 4 5 7 4 5 6 3 4 6 3 4 5 2 3 4 2 2 3 1 2 3 30c 25c 20c level 5 4 5 6 3 4 5 3 3 5 2 3 4 2 3 4 2 3 4 1 2 3 1 1 3 1 1 2 30c 25c 20c level 5a 2 2 3 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 1 2 0.5 1 2 0.5 1 1 30c 25c 20c body thickness <2.1 mm including soics <18 pin all tqfps, tsops all bgas <1 mm body thickness level 2a 28 1 2 2 1 1 2 1 1 1 30c 25c 20c level 3 11 14 20 7 10 13 1 2 2 1 1 2 1 1 1 30c 25c 20c level 4 9 12 17 5 7 9 4 5 7 3 4 6 1 2 2 1 1 2 1 1 1 30c 25c 20c level 5 13 18 26 5 6 8 3 4 6 2 3 5 2 3 4 1 2 2 1 1 2 1 1 1 30c 25c 20c level 5a 10 13 18 3 5 6 2 3 4 1 2 3 1 2 2 1 2 2 1 1 2 1 1 2 0.5 1 1 30c 25c 20c free datasheet http:///
for product information and a complete list of distributors, please go to our website: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies in the united states and other countries. data subject to change. copyright ? 2005-2008 avago technologies. all rights reserved. av02-0290en - august 26, 2008 free datasheet http:///

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