View A2SI-G1-MT_7056427.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev. 2.8 copyright ? 2008, zmd ag a 2 si / a2si-e universal actuator-sensor interface ic datasheet features ? as-i complete specification v2.11 compliant ? integrated eeprom ? additional addressing channel using an opto- electronic interface ? extended address mode operation as pro- grammable option (up to 62 slaves) ? high impedance as-i line input, additional pins for further impedance optimizations ? dc voltage output, approximately 24 volts, not stabilized ? 5 volt dc voltage output, stabilized, cmos logic can be supplied directly (e.g. c) ? led status indicator output (compliant with the standard indication recommendation) ? integrated watchdog all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 1/39 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 a sip a sin 0v ird fid osc2 osc1 do1 do3 do2 gn d p3 p2 p1 u in u out u5r cap led u5rd dsr pst di3 do0 di2 di1 di0 p0 a 2 si / a 2 si-e description a2si is a monolithic cmos integrated circuit certi- fied for as-i (actuator sensor-interface) networks. as-i networks are intended for industrial automa- tion. the main advantage of as-i solutions is that actua- tors and sensors are connected using a two-wire unshielded cable that is easy to install. this cable transports both power and information/data. as-i network communication is based on the mas- ter-slave principle. the network can be extended (to cable lengths greater than 100m) by using the a2si in the repeater mode configuration. as-i is a standard for the automation industry based on iec 62026-2 and en 50295. the device is available in a 28-pin ssop package (a2si) or sop package (a2si-e), respectively. application support configuration of the chip is handled through pro- gramming of the on-chip e2prom. zmd provides special tools to ease product evaluation and selec- tion of different operation modes. as-interface programmer 2.0 usb (ordering code: 3600100145) evaluation board equipped with a2si can be ordered from bihl+wiedemann gmbh (www.bihl-wiedemann.de) further application support is available through e- mail hotline under asi@zmd.de
datasheet zentrum mikroelektronik dresden ag a 2 si / a2si-e rev. 2.8, copyright ? 2008, zmd ag all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 2/39 table of contents page 0 read this first .......................................................................................................................................... 3 0.1 i mportant n otice .................................................................................................................................... 3 0.2 r eferences ............................................................................................................................................. 3 0.3 ic r evision h istory ................................................................................................................................. 3 1 general device specification ............................................................................................................ 6 1.1 a bsolute m aximum r atings (n on o perating ) ....................................................................................... 6 1.2 o perating c onditions ............................................................................................................................ 7 1.3 emc b ehavior ......................................................................................................................................... 8 1.4 q uality s tandards ................................................................................................................................. 8 1.5 h umidity c lass ........................................................................................................................................ 8 1.6 p ackage p in a ssignment ......................................................................................................................... 9 2 basic functional description ......................................................................................................... 11 2.1 f unctional b lock d iagram ................................................................................................................... 11 3 operational modes .............................................................................................................................. 1 4 3.1 d escription of d igital l ogic ................................................................................................................ 14 3.2 m aster /r epeater -m ode ....................................................................................................................... 15 3.2.1 ird input (cmos input) ................................................................................................................ 15 3.2.2 as-i input ............................................................................................................................... ........ 16 3.2.3 ports ............................................................................................................................... ................ 16 3.3 s lave m ode ............................................................................................................................... ............. 17 3.3.1 ird input mode (photo diode input) ........................................................................................... 17 3.3.2 as-i input mode ............................................................................................................................. 17 3.3.3 ports ............................................................................................................................... ................ 18 3.3.4 watchdog ............................................................................................................................... ........ 18 3.3.5 led output ............................................................................................................................... ..... 19 3.3.6 overtemp shutdown ..................................................................................................................... 19 3.3.7 state machine ............................................................................................................................... .19 3.3.8 summary of master calls ............................................................................................................. 20 3.4 p rogram m ode ............................................................................................................................... ....... 20 4 dc and ac characteristics ............................................................................................................... 21 4.1 d igital i nput and o utput p ins .............................................................................................................. 21 4.2 a ddressing c hannel i nput ird ............................................................................................................ 25 4.3 f ault i ndication i nput , fid ................................................................................................................... 25 4.4 v oltage o utputs ............................................................................................................................... ... 26 4.5 as- i b us l oad ............................................................................................................................... ......... 27 4.6 i nput i mpedance c ontrol ..................................................................................................................... 28 4.7 o scillator ............................................................................................................................... .............. 28 5 development information data ...................................................................................................... 29 6 application circuits ............................................................................................................................ 31 6.1 emc p recautions ............................................................................................................................... .. 31 7 package outline ............................................................................................................................... ..... 34 7.1 a 2 si ssop package ............................................................................................................................... 34 7.2 a 2 si-e sop package .............................................................................................................................. 3 5 8 package marking ............................................................................................................................... ... 36 9 ordering information ......................................................................................................................... 37 10 contact information ....................................................................................................................... 38 10.1 zmd s ales c ontacts ........................................................................................................................ 38 10.2 as-i nternational a ssociation ......................................................................................................... 38
datasheet zentrum mikroelektronik dresden ag a 2 si / a2si-e rev. 2.8 copyright ? 2008, zmd ag all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 3/39 0 read this first 0.1 important notice products sold by zmd are covered exclusively by the warranty, patent indemnification and other provisions ap- pearing in zmd standard "terms of sale". zmd makes no warranty (express, statutory, implied and/or by de- scription), including without limitation any warranties of merchantability and/or fitness for a particular purpose, regarding the information set forth in the materials pert aining to zmd products, or regarding the freedom of any products described in the materials from patent and/or other infringement. zmd reserves the right to discontinue production and change specifications and prices of its products at any ti me and without notice. zmd products are intended for use in commercial app lications. applications requiring extended temperature range, unusual environmental requirements, or high reliability applicatio ns, such as military, medical life-support or life- sustaining equipment, are specifically not recommen ded without additional mutually agreed upon processing by zmd for such applications. zmd reserves the right to change the detail specificati ons as may be required to permit improvements in the design of its products. 0.2 references [1] as-interface complete specific ation version 3.0, dated 16.09.2004 0.3 ic revision history revision date technical changes note a september 1999 first by ami marketed silicon version ic revision a did not have a revision code marking. ics without a revision code are equivalent to revision a. b january 2002 first by zmd marketed silicon version
datasheet zentrum mikroelektronik dresden ag a 2 si / a2si-e rev. 2.8, copyright ? 2008, zmd ag all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 4/39 uart (telegram che- cker) the telegram reception under worst case ca- pacitive and worst case inductive network con- ditions was improved in response to sugges- tions of the technical committee of the as- international association. uart (master mode) the digital man-code communication channel does now support a more cost effective two- wire data transfer between the a2si and the master control logic. it is not necessary to rely on the additional ?receive_strobe? signal, which is supplied at the parameter port p2 in master mode to verify the correctness of the man output signal at the led port. the man signal is now distinctively disturbed if an erro- neous telegram was detected at the as-i input. this allows to spare at least one opto coupler in between the a2si and the master control. main state ma- chine slave mode (communication watchdog) if running, the communication watchdog will now become turned off as soon as the volatile slave address register is changed to zero (0x0). this occurs after the reception of a de- lete_address call or at a reset of the a2si. in all previous revisions, a running communica- tion watchdog could only be turned off by a reset of the a2si (reception of reset_ slave call or external reset). in case the watchdog was running and a master did not submit a reset_slave call prior to an address assign- ment, the write access to the non-volatile e2prom memory could have been interrupted. because a data corruption is likely in such an event, the a2si resumed to the fail save state of slave address zero (0x0) and did not re- spond to the newly assigned address until the address assignment call was repeated. oscillator the loop gain of t he oscillator was increased to support a broader variety of 8mhz crystals. effected part of the a2si description of modification c august 2002 infrared input channel (slave mode) it appeared the infrared input channel (ird) was sensitive against coupled noise in some application circuits. in order to make the photo current input more robust for a broad variety of designs, the analog receiver circuit had been changed. this resulted in a much better per- formance in terms of noise sensitivity but re- quired a slightly lower sign al sensitivity as well. see the updated data sheet for more informa- tion. the replacement of a2si revision b with revision c neither has any impact to required external components nor requires a change of the external circuitry. the cap-pin of an ic of revision c shall be connected to a series of one ca- pacitor and one re- sistor, in the same manner like on revi- sion b. suggested values are c=4.7nf, r=430?680 ohms. see the data sheet and the application notes for more de- tailed information. c november 2008 the production of the a 2 si device will discontinue in 2009. please use the asi4u device ( http://www.zmd.biz/pdf/asi4u%20datasheet_rev.1.7.pdf ) in order to replace the a 2 si in existing applications.
datasheet zentrum mikroelektronik dresden ag a 2 si / a2si-e rev. 2.8 copyright ? 2008, zmd ag all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 5/39
datasheet zentrum mikroelektronik dresden ag a 2 si / a2si-e rev. 2.8, copyright ? 2008, zmd ag all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 6/39 1 general device specification 1.1 absolute maximum ratings (non operating) any stress above the listed absolute maximum ratings may cause permanent damage to the device. the given conditions represent a stress rating only. functional operat ion of the device at those conditions or at any other stress above the operational limits is not implied. exposure to maximum rating conditions for extended times may effect device performance, functionality, and reliability table 1: absolute maximum ratings symbol parameter min. max. unit s note v 0v ,v gnd voltage reference 0 0 v v asip positive as-i supply voltage -0.3 40 v v asin negative as-i supply voltage -0.3 20 v 1 v asip-asin voltage difference from asip to asin (v asip - v asin ) -0.3 40 v 2 v asipp as-i supply pulse voltage, voltage difference between pins asip and asin (from asip to asin) 50 v 3 v uin aux. power supply input voltage -0.3 40 v v uinpv aux. power supply input voltage pulse 50 v 3 v inputs1 voltage at pins di3 - di0, do3 - do0, p3 - p0, dsr, pst, led, fid, u out -0.3 v uin + 0.3 v v inputs1 40v v inputs2 voltage at pins osc1, osc2, ird, cap, u5r, u5rd -0.3 7 v i in input current into any pin except supply pins -25 25 ma h humidity non-condensing 4 v hbm1 electrostatic discharge ? human body model (hbm1) 4000 v 5 v hbm2 electrostatic discharge ? human body model (hbm2) 2000 v 6 v edm electrostatic discharge ? equipment discharge model (edm) 400 v 7 stg storage temperature -55 125 c p tot total power dissipation 0.85/1.11 w 8, 9 1 asin-pin shall be shorted to 0v-pin on pcb. 2 reverse polarity protection has to be performed externally. 3 pulse with 50s, repetition rate 0.5 hz. 4 level 4 according to jedec-020a is guaranteed 5 hbm1: c = 100pf charged to vhbm1 with resistor r = 1.5k in series, valid for asip-asin only. 6 hbm2: c = 100pf charged to vhbm2 with resistor r = 1.5k in series, valid for all pins except asip-asin. 7 edm: c = 200pf charged to vedm with no resistor in series, valid for asip-asin only. 8 p tot = 0.85 w for a 2 si, 1.11 w for a 2 si-e 9 at maximum operating temperature, the allowed total power dissipation depends on the additional thermal resistance from case to ambient and on the operation ambient temperature (see figure 1 for a 2 si, see figure 2 for a 2 si-e ). caution: electrostatic sensitive device permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to high-energy electrostatic discharge.
datasheet zentrum mikroelektronik dresden ag a 2 si / a2si-e rev. 2.8 copyright ? 2008, zmd ag all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 7/39 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 1,1 1,2 1,3 -25 0 25 50 75 100 ta /c p tot / w ptot (1l) ptot (2l) p tot = f(ta); 1l / 2l = 1 layer / 2 layer pcb ptot = f (ta); 1l / 2l = 1 layer / 2 layer pcb 0,2 0,3 0,4 0,5 0,6 0,7 0, 8 9 1 -25 0 25 50 75 100 ta 0, ptot (2l) ptot (1l) 1.2 operating conditions table 2: operating conditions symbol parameter min. max. units note v uin positive supply voltage 16 33.1 v 1 v asin negative as-i supply voltage 0 0 v 2 v 0v , v gnd negative supply voltage 0 0 v i asi supply current at v asi = 30v 9 ma 3 i cl1 max. output sink current at pins do3 - do0, dsr 10 ma i cl2 max. output sink current at pins p0 - p3, pst 10 ma amb ambient temperature range, operating range -25 85/105 c 4 1 dc voltage 2 asin shall be shorted with 0v to ensure pr oper functionality of transmitter circuit. 3 fc = 8.000 mhz, no load at any pin without reaction of the ci rcuit, asip is short-cut to ui n and asin to 0v respectively. 4 amb -25c to 85c for a 2 si, -25c to 105c for a 2 si-e table 3: chrystal frequency symbol parameter nom. unit note f c crystal frequency 8.000 mhz figure 2: maximum power dissipation for a 2 si , ptot = f(ambient temperature) figure 1: maximum power dissipation for a 2 si-e , ptot = f(ambient temperature)
datasheet zentrum mikroelektronik dresden ag a 2 si / a2si-e rev. 2.8, copyright ? 2008, zmd ag all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 8/39 1.3 emc behavior the ic fulfills the requirements defined in as-interface complete specification v2. 11 [1] and related test re- quirements as-interface slave ics. the above specified behavior is correct by design and has to be proven while ic characterization. 1.4 quality standards the quality of the ic will be ensured according to the zmd quality standards. zmd is a qualified supplier accord- ing to iso/ts 16949:2002 and iso 14001:2004. the following reference documents ap ply for the development process: ? management regulation: 0410 product development procedure ? process specification: 1.5m cmos-technology functional device parameters are valid for dev ice operating conditions specified in chapter 1.2 at page 3 . pro- duction device tests are performed within the recommended ranges of v ltgp - v ltgn , amb = + 25c (+ 85/105c and - 25c on sample base only) unless otherwise stated. 1.5 humidity class level 4 according to jedec-020d is guaranteed.
datasheet zentrum mikroelektronik dresden ag a 2 si / a2si-e rev. 2.8 copyright ? 2008, zmd ag 1.6 package pin assignment all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 9/39 a sip 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 a sin 0v ird fid osc2 osc1 do1 do3 do2 gn d p3 p2 p1 u in u out u5r cap led u5rd dsr pst di3 do0 di2 di1 di0 p0 a 2 si / a 2 si-e figure 3: pin configuration, 28-pin ssop
datasheet zentrum mikroelektronik dresden ag a 2 si / a2si-e rev. 2.8, copyright ? 2008, zmd ag all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 10/39 table 4: pin description pin # name type description 1 asip inout to be connected to the as-i-line asi+ via reverse polarity protection diode 2 asin inout to be connected to the as-i-line asi- 3 0v supply common 0v for all ports except asip/asin (to be connected to asi- line) 4 ird in addressing channel input 5 fid in input peripheral fault indication 6 osc2 inout crystal osc illator (8 mhz x-tal) 7 osc1 in crystal oscillator / external clock input 8 do3 out output of data d3 9 do2 out output of data d2 10 do1 out output of data d1 11 do0 out output of data d0 12 gnd supply digital io ground, must be connected to pin 0v 13 p3 i/o input/output of parameter p3 14 p2 i/o input/output of parameter p2 / receive strobe in ?master mode? 15 p1 i/o input/output of parameter p1 / power fail in ?master mode? 16 p0 i/o input/output of parameter p0 / data clock in ?master mode? 17 di0 in input of data d0 18 di1 in input of data d1 19 di2 in input of data d2 20 di3 in input of data d3 21 pst out parameter strobe output 22 dsr i/o data strobe output/reset input 23 u5rd supply digital 5v supply input, should be connected to u5r 24 led out output led "as-i-diagnosis" / addressing channel output 25 cap in/out for connection of external rc components 26 u5r out internal 5v supply that might be used to supply external circuits as well 27 u out out supply of external circuitry (e .g. sensor, actuator, etc.), approx. v uin minus 7 volt 28 u in supply input of the power supply block (us ually to be connected to the as-i-line asi+ via reverse polarity protection diode)
datasheet zentrum mikroelektronik dresden ag a 2 si / a2si-e rev. 2.8 copyright ? 2008, zmd ag 2 basic functional description 2.1 functional block diagram figure 4: block diagram following device functions are associated with the different blocks of the ic: power supply an on-chip electronic inductor provides a de-coupled voltage at pin u out and the power supply regulates the internal 5v operating volt age. the de-coupling circuit (electronic coil) is connected between u in and u out pins and guarantees a high impedance seen at u in . an external capacitor and resistor are required to allow a low-pass filter with a very high time constant. this high time-constant value is necessary to maximize the input impedance. the de-coupling circuit limits the current that can be drawn from u out . the power supply will shut down the de-coupling circuit in case of an over load condition to prevent a total malfunction of the complete as-i line. the regulated 5 vo lt supply voltage is connected to pin u5r. two external capacitors are necessary to cope wi th fast internal and external load changes (spikes). current drawn from pin u5r (up to 4 ma) has to be subtracted from the total load current. the power supply circuit dissipates the major amount of power. the total power dissipation shall not exceed the specified values of fehler! verweisquelle konnte nicht gefunden werden.. the ground reference voltage for both uout and u5r is defined by the 0v pin. this pi n must be connected to asi- (ref. fehler! verweisquelle konnte nicht gefunden werden.). transmitter the transmitter draws a modulated current between asip and asin pins to generate the communication signals. the shape of the current corresponds to the integral of a sin2- function. the transmitter uses a current dac and a high current driver. in order to activate high current drive capability, a small current will be turned on automatically prior to each transmission (slave mode only). the current will be ramped up slowly to avoid false voltage pulses on the as-i line. the amount of circuitry between asi+ and asi- pins is minimized to allow high impedance values. when the transmitter is turned on, the receiver is turned off to all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 11/39
datasheet zentrum mikroelektronik dresden ag a 2 si / a2si-e rev. 2.8, copyright ? 2008, zmd ag all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 12/39 reduce power consumption.
datasheet zentrum mikroelektronik dresden ag a 2 si / a2si-e rev. 2.8 copyright ? 2008, zmd ag all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 13/39 receiver the receiver detects signals on the as-i line and delivers the appropriate pulses to the digi- tal logic. the dc value of the input signal is removed and the ac signal is band-pass fil- tered. the digital output signals are extracted from the sin 2 -shaped input pulses by a set of comparators. the maximum voltage of the fi rst negative pulse determines the threshold level for all following pulses. the maximum value is digitally filtered to guarantee stable conditions (burst spikes have no effect). th is approach combines a fast adaptation to changing signal amplitudes with a high detecti on safety. the receiver delivers positive (p- pulse) and negative (n-pulse) pulses to the ic's logic. the logic resets the comparators after receiving the re c-reset signal. when the receiver is turned on, the transmitter is turned off to reduce power consumption. digital logic the digital logic block performs analysis of the received signal, controls reaction of the ic, transmits slave response, switches i/o-ports, and controls the internal eeprom. its princi- pal function is described in detail in section 3.1 . protection cir- cuitry the device has several protection cells that pr event disruption and ma lfunction of the com- plete as-i line. the thermal detection shuts down the power supply in case of over-heating condition (sili- con temperature > 140c typically for more than 2 seconds) and when u out is shorted to gnd for more than 2 seconds. the device can only be reactivated by a power-on reset. an over-heating condition can occur by overloading any output pin. therefore, the circuit moni- tors the operating conditions of the power supply (effectively monitors u out ) and measures the temperature of the silicon. power fail de- tection the power-fail detector consists of a comparator that generates a logic signal in case the power supply drops below 22v dc (power-fail) for a time of more than t loff (0.8 0.1 ms). the power fail signal will be presented at pin p1 in master mode only. power-fail detection monitors the value of the asi p voltage. it will activate a logic signal if power fails for more than 1ms. the device is then buffered by the external capacitor at u out and the internal circuitry will be reset when u5r supply voltage fails infrared diode input the photo current input can be used as an al ternative communication pin in slave mode. the ird circuitry will be turned off when the communication has been switched to as-i line. in slave mode the logic sets ird input to ph oto-detector mode and disables cmos mode. in this photo-detector mode, signals of an ex ternal photo diode are amplified. in cmos mode (master/repeater mode only), input signals have to be cmos levels between 0v and v u5r
datasheet zentrum mikroelektronik dresden ag a 2 si / a2si-e rev. 2.8, copyright ? 2008, zmd ag 3 operational modes 3.1 description of digital logic the digital logic is structured in four parts: 1) the uart, which analyses the incoming signal from the as-i line and ensures correct timing of output signals; 2) the state machine, which controls the reaction of the ic; 3) the ports, which contain registers and digital i/o?s; 4) and finally the e2prom, which cont ains the non-volatile data of the a 2 si circuit. all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 14/39 data-out-0 data-out-1 data-out-2 data-out-3 data-strb reset data-in-0 data-in-1 data-in-2 data-in-3 param-out-0 param-out-1 param-out-2 param-out-3 param-strb param-in-0 param-in-1 param-in-2 param-in-3 ird-in fault-in led-out over-heat u out s houtdown ports do-r eg -0 do-r eg -1 do-r eg -2 do-r eg -3 di-r eg -0 di-r eg -1 di-r eg -2 di-r eg -3 po-r eg -0 po-r eg -1 po-r eg -2 po-r eg -3 pi-0 pi-1 pi-2 pi-3 e 2 prom state machine r ec -r eg -0 r ec -r eg -1 r ec -r eg -2 r ec -r eg -3 r ec -r eg -4 r ec -r eg -5 r ec -r eg -6 r ec -r eg -7 r ec -r eg -8 r ec -r eg -9 r ec -r eg -10 r ec -s trb s end -r eg -0 s end -r eg -1 s end -r eg -2 s end -r eg -3 s end -s trb p-pulse n-pulse send-d send-sby rec-reset a dd-clk a dd-out a dd-in digital logic power-fail power-on reset p-pulse uart figure 5: digital logic
datasheet zentrum mikroelektronik dresden ag a 2 si / a2si-e rev. 2.8 copyright ? 2008, zmd ag 3.2 master/repeater-mode 3.2.1 ird input (cmos input) the ic sends signals retrieved from pin ird to as-i li ne as an as-i telegram. the input signal is manchester- coded and active low. a falling edge of the ird signal, whic h is conducted to add-in, starts the receiving proc- ess and triggers the activity-checker . receive-muxer selects pin ird as input for the receive data the ird signal is connected with send-muxer to send-d via add-in. the ird signal is latched every 500 ns as long as there is activity on the input pin. if ther e is a high level on the ird input longer then 7.0 s, activity- check er will recognize this as no activity and receive-muxer is returning to idle state. the information on pin ird is transported to pin send-d with a delay of 2.0 s up to 2.5 s. the sender is always in non-standby mode. the send-sby signal is constant lo w and there is no gener ation of add-clk. all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 15/39 r ec -r eg -0 r ec -r eg -1 r ec -r eg -2 r ec -r eg -3 r ec -r eg -4 r ec -r eg -5 r ec -r eg -6 r ec -r eg -7 r ec -r eg -8 r ec -r eg -9 r ec -r eg -10 uart s end -r eg -0 s end -r eg -1 s end -r eg -2 s end -r eg -3 receive register send muxer send-d a dd-out receive muxer man code checker control unit pulse encoder a ctivity checker send register strobe unit p-pulse n-pulse a dd-in rec-strb a dd-clk send-sby rec-reset send-strb figure 6: uart block diagram
datasheet zentrum mikroelektronik dresden ag a 2 si / a2si-e rev. 2.8, copyright ? 2008, zmd ag all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 16/39 3.2.2 as-i input a signal on the as-i-line generates signals at the receiv er output that are pulse coded with a minimal pulse width of 750 ns up to 875 ns. a pulse on the as- i line starts the receiver and triggers the activity-checker through n-pulse or p-pulse. the receive-muxer selects as-i-line pins as input for the receive data. the n- pulse and p-pulse signals are latched every 250 ns as long as there is activity on the input pins. if there is a pulse distance on the as-i-line inputs longer then 7.0 s, the receiver will recognize this as no activity and the receive-muxer is going to the idle state. the pulse-encoder is used to convert the active high pulse-coded signal to a active low manchester-ii-coded (man) signal. it will also check the pulse stream for timi ng and pulse errors (e.g. alternation error). in mas- ter/repeater mode the pulse-encoder additionally resynchronizes an error-free man telegram into a proper 3 s time base. this is to eliminate the pulse jitter of the transformed as-i telegram. the synchronized man signal is sent to add-out through the send-muxer. add-out is connected to led-out on a higher hierarchy level. all in all, information on the as-i-line pins is transported to pin led-out with a delay of 2.5 s up to 3.0 s. in master/repeater mode the sender is never in sta ndby mode, hence send-sby signal is always low. a generation of add-clk is provided to simplify exter nal processing of manchester-coded data. the rising edge of the add-clk signal is in the middle of the second half of the manchester data assuring that correct binary data can be clocked into a shift register. the add-clk star ts with a rising edge 2.0 s after the falling edge of the start bit at add-out with a period of 6.0 s and a ratio of 1:1. the last rising edge of the add-clk signal occurs 2.0 s after the falling edge of the end bit at add-out. if the received signal in the master mode is a valid slave an swer with start bit, four (4) data bits, parity, and end bit and if a pause is following with a length greater than 6.0 s, the uart generates the active high rec-strb signal with a pulse width of 500 ns. the rec-strb signal is connected to the p2 parameter output in this mode. it appears 10.0 to 10.5 s after the rising edge of the end bit on as-i-line. 3.2.3 ports functional assignments of some ic ports depend on the op erational mode of the ic. thus, these ports perform multiple functions that are related to a particular mode of the ic. in master mode, following signals and ports are connected: table 5: pin configuration in master/slave function pin slave function master repeater p0 parameter output port bit 0 rec-clk rec-clk p1 parameter output port bit 1 power- fail - p2 parameter output port bit 2 rec-strb - led led fault indicator output/addressing channel output man-out man-out ird addressing chan- nel input man-in man-in
datasheet zentrum mikroelektronik dresden ag a 2 si / a2si-e rev. 2.8 copyright ? 2008, zmd ag all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 17/39 3.3 slave mode after ic-reset, receive-muxer is watching the two input channels (as-i-line and ird pin) depending on a multi- plex select signal mpx. mpx has a frequency of about 1.0 khz. if mpx is low, the receive-muxer selects the as-i-line and vice versa if it is high, it selects the ir d pin as data input. the channel, from which a valid master call is received first, will be locked until the next ic-reset occurs. 3.3.1 ird input mode (photo diode input) the photo diode current on the ird input is manchester-coded and low active (ref. 4.2 addressing channel input ird ). a low level of the ird signal starts the receiver and triggers the activity-checker . the control-unit is enabling the receive-register and the received information is clocked every 6 s into the receive-register . if there is a high level on the ird input longer then 7.0 s, the control-unit will recognize this as no activity and the receive-register will be disabled. if the received inform ation is a correct master call with start-bit , eleven data-bits , parity-bit , end-bit , and following pause of either greater than 6.0 s (synchronous mode) or 18.0 s (asynchronous mode), the uart generates the internal active high rec-strb signal with a pulse width of 500 ns. if the received telegram contained an error, the control-unit will not generate the rec-strb signal but go to its asynchronous state waiting for a pause at the ird input. after a pause was detected, the uart is ready to re- ceive the next telegram from the ird input. if a rec-strb signal is generated, it occurs 9.5 s up to 10.0 s (synchronous mode) or 21.0 s up to 21.5 s (asynchronous mode), respectively , after the rising edge of the end-bit on the ird pin signal. if the slave was in asynchronous state, it now transf orms to synchronous state. the rec-muxer is locked to the ird input until the next ic-reset. after the generation of a rec-strb signal the control-unit is waiting for about 6.0 s for the send-strb to be generated by the main-state-machine . if the control-unit receives the active high send-strb si gnal, it starts the transmission of the send-register data. therefore, the send-register data will be converted to an active low manchester ii-coded (man) signal which is sent to the led-out pin via add-out. the first falling edge of the man signal occurs 11.75 s (syn- chronous mode) or 12.25 s (asynchronous mode) after the rising edge of the rec-strb signal. hence, the delay from the rising edge of the end-bit of the master call (ird input) to the first falling edge of the slave re- sponse (led output) is 21.25 to 21.75 s (synchro nous mode) or 33.25 to 33.75 s (asynchronous mode). after the pause was detected, the uart is ready to receive the next telegram from the ird input. in case the control-unit will not receive a send-strb signal within th e given time frame (for instance, if this slave was not addressed), it will check for activity on t he ird input. otherwise, it will ju st wait for the end of the response time (60 s). in both cases the control-unit stays synchronou s. once a slave pause was detected, the uart is ready to receive the nex t telegram from the ird input 3.3.2 as-i input mode a signal on the as-i-line generates two pulse-coded signals (n-pulse, p-pulse) at the receiver output with a minimum pulse width of 750 to 875 ns. a pulse on the as-i line starts the receiver and triggers the activity- checker through n-pulse or p-pulse. the pulse-encoder is used to convert the active high pulse coded signal to an active low manchester-ii-coded (man) signal. it will also check the pulse stream for ti ming and pulse errors (e.g . alternation error). the control- unit enables the receive-register so that the received information can be clocked in every 6 s. if there is a pulse distance on the as-i-line input longer than 7.0 s, the control-unit recognizes this as no activity and dis- ables the receive-register . if the received information is a correct master call with start-bit, eleven data-bits, parity-bit, end-bit, and follow- ing pause of either greater than 6.0 s (synchronous mode) or 18.0 s (asynchronous mode), the uart gen- erates the internal active high rec-strb signal. if the re ceived telegram contained an error, the control-unit will not generate the rec-strb signal but go to its asynchronous state wait ing for a pause at the as-i line in- put. after a pause was detected the uart is ready to receive the next telegram from the as-i line input.
datasheet zentrum mikroelektronik dresden ag a 2 si / a2si-e rev. 2.8, copyright ? 2008, zmd ag all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 18/39 if a rec-strb signal is generated, it occurs 10.0 to 10.5 s (synchronous mode) or 21.5 to 22 s (asynchro- nous mode), respectively, after the rising edge (receiver comparator switching point) of the end-bit on the as-i line input. if the slave was in asynchronous state, it now transforms to synchronous state. the rec-muxer is locked to the as-i line input until the next ic-reset. after the generation of a rec-strb signal the control-unit is waiting for about 6.0 s for the send-strb to be generated by the main-state-machine. if the control-unit receives the active high send-strb sign al (pulse width 500 ns), it starts the transmission of the send-register data. therefore, th e send-register data will be converted to an active low manchester ii- coded (man) signal which is sent to the as-i line transmitter via send-d. the first falling edge of the man sig- nal occurs 11.75 s (synchronous mode) or 12.25 s (asynchronous mode) after the rising edge of the rec- strb signal. hence, the delay from the rising edge of the end-bit of t he master call (as-i input) to the first falling edge of the slave response (as-i output) is 21.75 to 22.25 s (syn chronous mode) or 33.75 to 34.25 s (asynchronous mode). the send-sby will always be set low 0.5 s after the rising edge of rec-strb. this is to turn on the transmit- ter and let it settle at its operation point. the small offset current, which is required to operate the transmitter, will be ramped up slowly to avoid any false voltage pulses on the as-i line. if all data is sent, the control-unit sets the sender in standby mode (send-sby is high) and checks for a slave pause on the as-i line input. after the pause was detected, t he uart is ready to receive the next telegram from the as-i line input. in case the control-unit will not receive a send-strb sign al within the given time fr ame (for instance, if this slave was not addressed), it will check for activity on the as-i line. if any activity is detected in a time frame of about 60 s (another slave is transmitti ng data), the control-unit will wait for the next pause (slave pause). oth- erwise, it will just wait for the end of the response time (60 s). in both cases the c ontrol-unit stay s synchronus. once a slave pause was detected, the uart is ready to receive the next telegram from the as-i line input. 3.3.3 ports although the a2si can still store the as-i slave io-configur ation code it does not decode the value to configure the direction of the data-port signals. the a2si rather has distinctive data-out and data-in ports which do al- ways work in parallel. if bi-directional data i/o is desired on top of a single da ta-port only (for backwards compatibilit y), the data-out pins and the data-in pins need to be shorted on the circui t board respectively and the non-volatile multiplex flag has to be set true. in that case the output ports will switch to high impedanc e state for a certain time following the rising edge of the data-strobe and allow the input data to be put on the data-port. the input data will be read inverted if the non-volatile invert_dat a_in flag is true. this feature will simplify the circuitry for npn-inputs. note: the multiplex and the invert_data_in flags are conf iguration flags which are stored in the firmware re- gion of the internal e2prom. for a complete overview of the e2prom content please see the a2si application notes. the parameter port is always in bi-directional mode. t he input data is the result of a wired-and between the open drain output drivers and the application drivers. 3.3.4 watchdog compliant to the as-i complete specification, the ic contains an independent watchdog which is generally en- abled by setting watchdog_active flag in the e2prom to true. the watchdog will be activated for any slave addres s uneven to zero (0) after the reception of a write_parameter request at the parti cular slave address. it will be deactivated by any circuit reset and after the reception of a delete_address request.
datasheet zentrum mikroelektronik dresden ag a 2 si / a2si-e rev. 2.8 copyright ? 2008, zmd ag all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 19/39 when activated, the watchdog will be reset by ever y write_parameter and data_exchange request received by the slave. if no such request was received by the particular slave within 40ms, a hardware reset will be performed and all data and parameter outputs are switched inactive. 3.3.5 led output an active fid (logic high) signal causes a flashing st atus led (frequency approx. 2hz) and bit 1 of the as-i slave status-register (s1) is set as we ll. if fid is not active (logic low), s1 is cleared. in that case the status led operation depends on the data-exchange-disable flag. the data-exchange-disable is set to true by each rese t of the a2si. it becomes clea red (set to false) after the first reception of a write_parameter request. if the data-exchange-disable flag is set, no data exchang e can be performed through the data ports which is indicated by a steady-on led. note: an active fid has priority and will cause a flas hing led even if the data-exchange-disable flag is set. if the uart has selected the ird input channel, the le d output is again overwritt en by the addressing channel output. in this mode the led pin does not operate as i ndicator led output and periphery failures or status in- formation can not be signaled. 3.3.6 overtemp shutdown the a2si continuously observes its silicon die temperat ure. if the temperature rise s above 140c the ic will be put into shut-down and stay there until the next power-on reset occurs. 3.3.7 state machine the so-called main-state-machine performs the central cont rol of the a2si ic in terms of operation mode selec- tion, eeprom access control, processing of master reques ts and the control of the ic ports. the main-state- machine interfaces with the uart through the receive- and the send-register as well as certain strobe sig- nals. to avoid the situation in which a slave ic gets locked in a not allowed state (i.e by emission of strong electro- magnetic radiation) and thereby would jeopardize the entir e system, all prohibited states of the state machine will lead to a reset which is comparable to the as-i call ?reset slave (res)?.
datasheet zentrum mikroelektronik dresden ag a 2 si / a2si-e rev. 2.8, copyright ? 2008, zmd ag 3.3.8 summary of master calls table 6: a2si master calls and related save responses all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 20/39 master request slave response instruction mne st cb a4 a3 a2 a 1 a 0i 4 i 3 i2 i1 i0 pb eb sb i3 i2 i1 i0 pb eb data exchange dexg 0 0 a4 a3 a2 a1 a0 0 d3 ~sel d2 d1 d0 pb 1 0 d3 e3 d2 e2 d1 e1 d0 e0 pb 1 write parameter wpar 0 0 a4 a3 a2 a1 a0 1 p3 ~sel p2 p1 p0 pb 1 0 p3 i3 p2 i2 p1 i1 p0 i0 pb 1 address assignment adra 0000000a4a3a2a1a0pb1 00110pb1 write extented id code-1 wid1 01000000id3id2id1id0pb1 00000pb1 delete address dela 01a4a3a2a1a000 sel000pb1 00000pb1 reset slave res 0 1 a4a3a2a1a0 1 1 ~sel 100pb1 00110pb1 read io configuration rdio 0 1 a4 a3 a2 a1 a0 1 0 sel 0 0 0 pb 1 0 io3io2io1io0 pb 1 read id code rdid 0 1 a4 a3 a2 a1 a0 1 0 sel 0 0 1 pb 1 0 id3 id2 id1 id0 pb 1 read id code-1 rid1 0 1 a4 a3 a2 a1 a0 1 0 sel 0 1 0 pb 1 0 id3 id2 id1 id0 pb 1 read id code-2 rid2 0 1 a4 a3 a2 a1 a0 1 0 sel 0 1 1 pb 1 0 id3 id2 id1 id0 pb 1 read status rdst 0 1 a4 a3 a2 a1 a0 1 1 ~sel 1 1 0 pb 1 0 s3 s2 s1 s0 pb 1 broadcast (reset) br01 011111110101pb1 --- no slave response --- enter program mode prgm010000011101pb1 --- no slave response --- note: in extended address mode the "select bit" defines whether the a-slave or b-slave is being addressed. dependent on the typ e of master call the i3 bit carries the select bit informati on (sel) or the inverted select bit information (~sel). 3.4 program mode provided that the non-volatile configuration flag, program-mode-disable , has not been set, the device can be transferred in program mo de by utilizing the ?enter program mode? call. please refer to the a2si application notes [4] for details of the programming process. as-i complete specification compliance note: in order to ensure full compliance with the as-i complete specification, the program-mode-disable flag must be set in the final manufacturing and configuration process before an as-i slave device is being delivered to field application users.
datasheet zentrum mikroelektronik dresden ag a 2 si / a2si-e rev. 2.8 copyright ? 2008, zmd ag all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 21/39 4 dc and ac characteristics all parameters are valid for the recommended range of v asip - v asin , v uin - v 0v , and amb. the devices are tested within the recommended range of v asip - v asin , v in - v 0v , amb = +25c (+ 85c and - 25c for a 2 si or + 105c and - 25c for a 2 si-e on sample base only) unless otherwise stated. unused input pins shall be con- nected to a suitable potential within the application circuit because there are no internal pull-up/down resistors. it is recommended to connect these pins either to 0v or via resistor to u out or u5r respectively. with an external low signal at the data strobe pin dsr (pull-down open drain driver) for more than 44s, the ic will execute its reset procedure. during power on procedure all dat a and parameter port s will stay on high- impedance state. if the ic has been put in its initialization procedure by an external reset via dsr, the led pin should not be tog- gled externally to avoid that the ic control logic transfers to test mode. 4.1 digital input and output pins table 7: input/output voltage and current symbol parameter min. max. units note pins di0 - di3, p0 - p3, dsr, fid, pst v il voltage range for input ?low? level, not p0 ? p3 0 2.5 v v il voltage range for input ?low? level, only p0 ? p3 0 2.4 v v ich voltage range for input ?high? level 3.5 v uout v v hyst hysteresis for switching level 0.25 v 1 i il current range for input ?low? level -20 -5 a i ich current range for input ?high? level -10 10 a v o = 5v i ihv current range for high voltage input 2 ma v o = 30v pins do0 - do3, p0 - p3, dsr, pst v ol1 voltage range for output ?low? level 0 1 v i ol1 = 10ma v ol2 voltage range for output ?low? level 0 0.4 v i ol2 = 2ma i oh output leakage current -10 10 a v oh = 4.5v cdl capacitance at pin dsr 10 pf 2 pin led v ol voltage range for output ?low? level 0 1 v i ol1 = 10ma 3 i oh output leakage current -10 30 a v oh = 40v 4 1 switching level approximately 3v, i.e. 3v vhyst. 2 for higher capacitive load an external pull-up resist or connected to uout is necessary to reach vih 3.5v at dsr in less than 35 s after the beginning of a dsr = low pulse , otherwise a reset will be executed. 3 the output driver sends a ?low? (led on). 4 the output driver sends a ?high? (equivalent to tri-state, led off).
datasheet zentrum mikroelektronik dresden ag a 2 si / a2si-e rev. 2.8, copyright ? 2008, zmd ag table 8: timing parameter port symbol parameter min. max. units note t setup valid output data; p0 - p3 to pst-h/l 0.1 0.5 s figure 7 t pst pst pulse width 5 6 s t pi-latch pst-h/l to parameter input latch 11 13.5 s 1 t cycle next cycle 150 s 1 the parameter input data must be stable within the period that is defined by minimum and maximum t pi-latch . all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 22/39 pst tsetup tpst tcycle tpi-latch parameter port output data parameter input value (pix) = parameter output value (pox) wired and with external signal source value keep stable min max po0-po3 figure 7: timing diagram parameter port p0 - p3
datasheet zentrum mikroelektronik dresden ag a 2 si / a2si-e rev. 2.8 copyright ? 2008, zmd ag table 9: timing data port outputs symbol parameter min. max. units note t setup valid output data; do0 - do3 to dsr-h/l 0.1 0.5 s figure 8 t hold valid output data; do0 - do3 to dsr-l/h 0.1 0.5 s t dstr dsr pulse width 5 6 s t di-latch dsr-h/l to data input latch 11 13.5 s 1 t cycle next cycle 150 s 1 the data input must be stable within the period that is defined by minimum and maximum of t di-latch . all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 23/39 dsr tsetup tdsr tcycle tdi-latch data port output data keep stable min max do0-do3 thold data remains, if multiplex flag is not set hi-z, if multiplex flag is set data port input data di0-di3 figure 8: timing diagram data port do0 - do3
datasheet zentrum mikroelektronik dresden ag a 2 si / a2si-e rev. 2.8, copyright ? 2008, zmd ag table 10: timing reset signal symbol parameter min. max. units note t alm1 ext. dsr (no reset) 35 s figure 9 t alm2 ext. dsr to do0 - do3 hi-z 44 s t reset1 reset time after dsr = external l ->h transition 2 ms all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 24/39 dsr do0-do3 talm1 talm2 >0 treset1 hi-z po0-po3 hi-z data port output data parameter port output data figure 9: timing diagram external reset via dsr
datasheet zentrum mikroelektronik dresden ag a 2 si / a2si-e rev. 2.8 copyright ? 2008, zmd ag 4.2 addressing channel input ird the addressing channel input ird is a dedicated photo-diode input. the photo-diode can be connected to the pins ird and 0v directly. the ird input is a ac current input. a valid signal at the current input has to have a certain amplitude (range) and should not exceed a certain of fset value. a logic "low" at the ird input will be detected, if the present signal value drops below i irdo , and a "high? will be detected, if its present value is greater than i irdo + i irda . min i irda max i irda max i irdo time ird input current figure 10: photo current waveform table 11: ac current amplitude of ir diode input in slave mode symbol parameter min. max. units note i irdo input current offset 10 a pp i irda input current amplitude 10 100 a pp ic revision a&b i irda input current amplitude 25 100 a pp ic revision c table 12: digital input ird in master/repeater mode symbol parameter min. max. units note v il voltage range for input ?low? level 0 2.5 v v ich voltage range for input ?high? level 3.5 v u5r v t r /t f rise/fall time 100 ns 1 1 in order to avoid jittery on the as-i line, the rise/fall time of the ird input signal should be as low as possible. 4.3 fault indication input, fid the fault indication input fid is a digital input dedicated for a periphery fault messaging signal. the s1 status bit is equivalent to the fid input signal. a fid transition w ill occur at s1 with a certain delay, because a synchro- nizer circuit is put in between. all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 25/39
datasheet zentrum mikroelektronik dresden ag a 2 si / a2si-e rev. 2.8, copyright ? 2008, zmd ag all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 26/39 4.4 voltage outputs table 13: properties of voltage output pins u out and u5r symbol parameter min. max. units note v uout u out output supply voltage v uin - v dropmax v uin - v dropmin v i uout = 30ma v uoutp u out output voltage pulse deviation 1.5 v 1 t uoutp u out output voltage pulse deviation width 2 ms 1 v drop voltage drop from pin u in to pin u out 6.5 7.7 v v uin > 22v v u5r 5v supply voltage 4.5 5.5 v i uout u out output supply current 0 30 ma i u5r = 0 ma, 2 i 5v u5r output supply current 0 4 ma i uout < 26 ma i o total voltage output current i uout + i 5v 30 ma i uouts short circuit output current 50 ma c luout load capacitance at u out 10 470 f c l5v load capacitance at u5r 1 f 1 cout = 10 f, output current switches from 0 to 30 ma and vice versa. 2 11.0v < vout < 27.6v.
datasheet zentrum mikroelektronik dresden ag a 2 si / a2si-e rev. 2.8 copyright ? 2008, zmd ag all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 27/39 4.5 as-i bus load the following parameters are determined with short-cu t between the pins asip and uin and the pins asin and 0v, respectively. table 14: as-i bus interface properties (pins asip/asin and u in ) symbol parameter min. max. units note v uin input as-i voltage at u in v uoutmin + v dropmax v uoutmax + v dropmin v 1 i lin input current limit at u in 56 ma v sig input signal voltage difference between asip and asin 3 8 v pp i sig modulated output peak current from asip to asin 55 68 ma p c zener parasitic capacitance of the external over-voltage protection diode (zener diode) 20 pf 2 r in1 equivalent resistor of the device 16 k 2, 3 l in1 equivalent inductor of the device 18 mh 2, 3 c in1 equivalent capacitor of the device 30 pf 2, 3 r in2 equivalent resistor of the device 16 k 2, 3 l in2 equivalent inductor of the device 12 18 mh 2, 3 c in2 equivalent capacitor of the device 15 + (l-12mh)* 2.5pf/mh pf 2, 3 1 dc parameter 2 the equivalent circuit of a slave (which is calculated from the impedance of the device and the paralleled external over-volt age protection diode (zener diode)) has to satisfy the comp lete as-i-specification v.2.1 concerning the requirements for the extended address range. 3 subtracting the maximum parasitic capacitance of the exter nal over voltage protection diode (20pf) either the triple r in1 , l in1 and c in1 or the triple r in2 , l in2 and c in2 has to be committed by the device to fulfill the complete as-i-specification v2.1.
datasheet zentrum mikroelektronik dresden ag a 2 si / a2si-e rev. 2.8, copyright ? 2008, zmd ag all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 28/39 4.6 input impedance control table 15: cap pin symbol parameter min. max. units note r cap external filter resistor 0 2.2 k 1 c cap external filter capacitor 4.7 100 nf 1, 2 1 recommended values for optimal impedance are: r cap = 1.2 k and c cap = 10 nf(ic revision a) r cap = 430 ? 680 and c cap = 4.7 nf(ic revision b and c) see chapter fehler! verweisquelle konnte nicht gefunden werden. , packa- ge marking, for details on how to di stinguish different ic versions. 2 the de-coupling capacitor and serial resist or define internal low-pass filter time constant; lower values decrease the impeda nce but im- prove the turn-on time. higher values do not improve the impedanc e but do increase the turn-on time. the turn-on time also depe nds on the load capacitor at uout. after connecting the slave to the power the capacitor is char ged with the maximum current iuout. the im pedance will increase when the voltage allows the analog circuitry to fully operate. 4.7 oscillator table 16: oscillator pi ns (osc1 and osc2) symbol parameter min. max. units note c osc external parasitic capacitor at oscillator pins osc1, osc2 0 5 pf v il input ?low? voltage 0 1.5 v 1 v ich input ?high? voltage 3.5 v u5r v 1 for external clock applied to osc1 only.
datasheet zentrum mikroelektronik dresden ag a 2 si / a2si-e rev. 2.8 copyright ? 2008, zmd ag 5 development information data table 17: information data symbol parameter min. max. units note v lsigon receiver comparator threshold level (see figure 11 ) 45 50 % related to am- plitude of 1 st pulse t reset1 reset time after master call ?reset as-i-slave? or dsr = external l ->h transition 2 ms 1 t reset2 reset time after power on 30 ms 2 t reset3 reset time after power on with high capacitive load 1000 ms 3 v asip-pf v asip voltage to detect power fail (master mode only) 21.5 23.5 v t loff power supply break down time (master mode only) 0.7 0.9 ms 4 v por1f v u5r voltage to trigger internal reset procedure, falling voltage 3.0 4.0 v 1 v por1r v u5r voltage to trigger init procedure, rising volt- age 2.5 3.5 v 1 t low power-on reset pulse width 4 6 s t shut chip temperature for thermal shut down (overheat- ing) 125 160 c conditions: asynchronous mode, reset to default comparator level at ?line pause?. 1 guaranteed by design only. 2 ?power_on? starts latest at v uin = 18v, external capacitor at pin u out = 10f. 3 c uout = 470f, treset3 is guaranteed by design only. 4 c uout > 10f, no power fail generated at v asip < v asip-pf for t < t loff (in master mode only). all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 29/39 first negative pulse of the as-i telegram v lsigon v lsigon = (0.45 - 0.50) * v sig / 2 "dc level" the ic determines the amplitude of the first negative pulse of the as-i telegram. this amplitude is asserted to be v sig / 2. v sig / 2 figure 11: receiver comparator set up
datasheet zentrum mikroelektronik dresden ag a 2 si / a2si-e rev. 2.8, copyright ? 2008, zmd ag v asip v por1r v por1f v uin v u5r por (active low) no reset, but if the break down time exceeds t loff , a power-fail signal will be generated reset will be initalized < ca. 15v 0v t loff v asip-pf t low power-on reset will be active, if the v u5r drops below v por1f master mode only all modes v asin figure 12: power-fail generation (in master mode) and reset behavior (all modes) all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 30/39
datasheet zentrum mikroelektronik dresden ag a 2 si / a2si-e rev. 2.8 copyright ? 2008, zmd ag 6 application circuits the following figures show typi cal application cases of the a 2 si ic. in figure 13 you can find a typical applica- tion circuit for a 2 si in slave operation mode. figure 14 shows an application circuit in which the a 2 si is replacing an asi3+ circuit. finally, figure 15 shows how the a 2 si circuit can be used to perform the analog/digital inter- face between the as-i-line and the master electronics. furthe rmore this figure shows that the ic can be used in repeater applications as well. 6.1 emc precautions precaution must be taken to avoid radio frequency interfer ence. it is recommended to keep input lines as short as possible and to connect unused inputs to u out through a pull-up resistor. furthermore, the supply pins should be de-coupled with ceramic capacitors (10 to 100 nf) in addition to the normal de-coupling capacitors. also, it is recommended to connect a pull-up resistor from dsr (pin 22) to u out or u5r in order to avoid unin- tentional reset under difficult emc conditions. all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 31/39 note: figure 13 and figure 14 show all digital (data and parameter) ports without the application specific connections . for correct function, it is important to consider that all output drivers are open dr ain stages and hence each port must be connected with an appropriat e pull-up resistor. asi asi 8 mhz c cap dsr pst fid led ird gnd 0v u in u out u5r u5rd osc1 cap a sip a sin 10 a 2 si f 2.2f osc2 0v +24v +5v di0 di1 di2 di3 do0 do1 do2 do3 p0 p1 p2 p3 di_0 di_1 di_2 di_3 do_0 do_1 do_2 do_3 p0 p1 p2 p3 ds&reset pst fault input 39v/1w r cap red green 17 18 19 20 11 10 9 8 16 15 14 13 22 21 5 23 26 27 24 4 12 3 25 2 1 6 7 28 22 k 10n 10n figure 13: typical application, slave mode
datasheet zentrum mikroelektronik dresden ag a 2 si / a2si-e rev. 2.8, copyright ? 2008, zmd ag all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 32/39 note: depending on i/o-configuration, do- and di -ports are connected and multiplex-flag is set. asi asi c cap dsr pst fid led ird gnd 0v u in u out u5r u5rd cap a sip a sin 10 f 2.2f a 2 si 8 mhz osc1 osc2 0v +2 4v +5 v di0 di1 di2 di3 do0 do1 do2 do3 p0 p1 p2 p3 dio-0 dio-1 dio-2 dio-3 p0 p1 p2 p3 ds&reset ps 39v/1w r cap 10n 10n 22 21 5 24 4 26 17 18 19 20 11 10 9 8 16 15 14 13 23 27 12 7 6 28 1 2 25 3 22 k figure 14: typical asi3+ compatible application
datasheet zentrum mikroelektronik dresden ag a 2 si / a2si-e rev. 2.8 copyright ? 2008, zmd ag all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 33/39 for further information see also a2si application note. asi+ asi? 8 mhz c cap dsr pst fid led ird gnd 0v u in u out u5r u5rd osc1 cap a sip a sin 2. 2f 10 f a 2 si osc2 di0 di1 di2 di3 do0 do1 do2 do3 p0 p1 p2 p3 39v +u b vo gnd +u b vo gnd +u b vo gnd +u b vo gnd +5v rec-clk (optional) rec-strb (optional) receive data send 0v isolation /p ow e r-fai r cap 10n 10n 27 16 15 14 13 22 5 24 23 26 4 21 12 3 25 2 1 6 7 28 l figure 15: master/repeater application
datasheet zentrum mikroelektronik dresden ag a 2 si / a2si-e rev. 2.8, copyright ? 2008, zmd ag 7 package outline 7.1 a 2 si ssop package figure 16: ssop package figure 17: package dimensions table 18: package dimensions (mm) symbol a a1 a2 b c d e e h l nominal 1.86 0.13 1.73 0.30 0.15 10.20 5.30 7.80 0.75 4 maximum 1.99 0.21 1.78 0.38 0.20 10.33 5.38 7.90 0.95 8 minimum 1.73 0.05 1.68 0.25 0.13 10.07 5.20 0.65 bsc 7.65 0.55 0 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 34/39
datasheet zentrum mikroelektronik dresden ag a 2 si / a2si-e rev. 2.8 copyright ? 2008, zmd ag 7.2 a 2 si-e sop package figure 18: sop package figure 19: package dimensions table 19: package dimensions (mm) symbol a a1 b c e d e l h h nominal 1,27 0,25 x 45 maximum 2,35 0,10 0,33 0,23 17,70 7,40 0,41 10,01 0 minimum 2,65 0,30 0,51 0,32 18,10 7,60 1,27 10,64 8 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 35/39
datasheet zentrum mikroelektronik dresden ag a 2 si / a2si-e rev. 2.8, copyright ? 2008, zmd ag 8 package marking pin 1 top view bottom view all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 36/39 top marking: a2si / a2si-e product name zmd manufacturer r- revision code xxxx date code (year and week) y assembly location zz traceability bottom marking: llllll zmd lot number the yellow dot indicating pre-programmed master function is printed at the pin 1 marking . note: ic revision a did not have a revision code marking. ics without a revision code are equivalent to re- vision a. revision b shows ?b-?, revision c shows ?c-?. 2 a si zmd r-yywwlzz g1 llllll + pin 1 figure 20: package marking
datasheet zentrum mikroelektronik dresden ag a 2 si / a2si-e rev. 2.8 copyright ? 2008, zmd ag 9 ordering information ordering code package rohs con- form temperature range delivery variant min. order quantity (moq) remarks a2si-g1-st rev.c y -25.. +85c tube standard 705 (47 parts/tube) a2si-g1-sr rev.c y -25.. +85c tape& reel standard 1500 a2si-g1-sr-7 rev.c y -25.. +85c tape& reel standard 500 7 inch reel A2SI-G1-MT rev.c y -25.. +85c tube master 705 (47 parts/tube) a2si-g1-mr rev.c ss0p28/ 5,3mm y -25.. +85c tape& reel master 1500 a2si-e-g1-st rev.c y -25..+105c tube standard 540 (27 parts/tube) a2si-e-g1-sr rev.c y -25..+105c tape& reel standard 1000 a2si-e-g1-mt rev.c y -25..+105c tube master 540 (27 parts/tube) a2si-e-g1-mr rev.c sop28/ 300mil y -25..+105c tape& reel master 1000 example: a2si-e-g1-sr-7 rev.c all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 37/39 package material (optional) g1??green? plastic package with lead-free terminals - pure sn none?standard plastic package package type / operating temp. range (optiona design revision rev.c?3 rd design revision** l) p28 / -25 to +85c none?sso reel diameter (optional, only for delivery form tape on reel) none?standard reel diameter: 13? 7?reel diameter 7? e?sop28 / -25 to +105c delivery form t?in tube r?in tape on reel device type s?slave ic m?master ic*
datasheet zentrum mikroelektronik dresden ag a 2 si / a2si-e rev. 2.8, copyright ? 2008, zmd ag 10 contact information 10.1 zmd sales contacts zmd ag grenzstrasse 28 01109 dresden, germany phone: +49 (0)351.8822.306 fax: +49 (0)351.8822.337 e-mail: sales@zmd.de zmd stuttgart office nord-west-ring 34 70974 filderstadt - bernhausen phone: +49 (0)711.674.517-0 fax: +49 (0)711.674.517-99 e-mail: sales@zmd.de zmd america inc. 201 old country road, ste 204 melville, ny 11747 phone: +1 (631) 549-2666 fax: +1 (631) 549-2882 e-mail: sensors@zmda.com please also see www.zmd.biz for most current information on zmd as-in terface products and technical product support. 10.2 as-international association documentation and promotional materials as well as detail ed technical specifications regarding the as-interface bus standard are available from: as-international association: contact - rolf becker zum taubengarten 52 d-63571 gelnhausen po box 1103 zip (63551) phone: +49 6051 47 32 12 fax: +49 6051 4732 82 e-mail: info@as-interface.net internet: www.as-interface.net all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 38/39 refer to www.as-interface.net for contact information on local as-inte rface associations which provide special support within europe, in the us and in japan.
datasheet zentrum mikroelektronik dresden ag a 2 si / a2si-e rev. 2.8 copyright ? 2008, zmd ag all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 39/39 notes: products sold by zmd are covered exclusiv ely by the warranty, patent indemnification and other provisions appearing in zmd stan dard "terms of sale". zmd makes no warranty (express, statutory, implied and/or by descripti on), including without limitation any warranties of merchanta bility and/or fitness for a particular purpose, regarding the information set forth in the materials pertaining to zmd products, or regarding the freedom of any produ cts described in the materials from patent and/or other infringement. zmd reserves the right to di scontinue production and change specifications and prices of its products at any time and without notice. zmd products are intended for use in commercial applications. applications requiring extended temperature range, unusua l environmental requirements, or high reliability applications, such as mili tary, medical life-support or life-sustain ing equipment, are spec ifically not recomm ended without additional mutually agreed upon processing by zmd for such applications. zmd reserves the right to change the detail specifications as may be required to permit improvements in the design of its produ cts.

▲Up To Search▲

Price & Availability of A2SI-G1-MT

	To Download A2SI-G1-MT Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .