copyright 1995 by dallas semiconductor corporation. all rights reserved. for important information regarding patents and other intellectual property rights, please refer to dallas semiconductor data books. ds1803 addressable dual digital potentiometer ds1803 062097 1/10 features ? 3v or 5v power supplies ? ultralow power consumption ? two digitally controlled, 256position potentiometers ? 14pin tssop (173 mil) and 16pin soic (150 mil) packaging available for surface mount applications ? addressable using 3chip select inputs ? serial/synchronous bus interface ? operating temperature industrial: 40 c to +85 c ? standard resistance values: ds1803010 10k w ds1803050 50k w ds1803100 100k w pin assignment 1 2 3 4 5 6 7 14 13 12 11 10 9 8 vcc nc h0 l0 w0 sda scl h1 l1 w1 a2 a1 a0 gnd ds1803e 14pin tssop (173 mil) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 vcc nc h0 l0 w0 nc sda scl h1 nc l1 w1 a2 a1 a0 gnd ds1803z 16pin soic (150 mil) ds1803 16pin dip (300 mil) see mech. drawings section pin description l0, l1 low end of resistor h0, h1 high end of resistor w0, w1 wiper terminal of resistor v cc 3v/5v power supply input a0 ..a2 chip select inputs sda serial data i/o scl serial clock input gnd ground nc no connection description the ds1803 is an addressable device having two inde- pendently controlled potentiometers. each potentiome- ter's wiper can be set to one of 256 positions. device control is achieved via a 2wire serial interface having a data i/o terminal and a clock input terminal. device addressing is provided through three chip select input terminals and correct communication protocol. addres- sing capability, when operating in a bus topology, allows up to eight devices to be controlled by the serial inter- face. the exact wiper position of each potentiometer can be written or read. the ds1803 is available in a 16pin dip, 16pin soic and 14pin tssop package. the device is available in three standard resistance val- ues: 10k w , 50k w , and 100k w , and is specified over the industrial temperature range.
ds1803 062097 2/10 device operation the ds1803 is an addressable, digitally controlled device which has two 256position potentiometers. a functional block diagram of the part is shown in figure 1. communication and control of the device is accom- plished via a 2wire serial interface having signals sda and sdl. device addressing is attained using the device chip select inputs a0, a1, a2 and correct com- munication protocol over the 2wire serial interface. each potentiometer is composed of a 256 position resis- tor array. two 8bit registers, each assigned to a respective potentiometer, are used to set wiper position on the resistor array. the wiper terminal is multiplexed to one of 256 positions on the resistor array based on its corresponding 8bit register value. for example, the highend terminals, h0 and h1, have wiper position val- ues ff(hex) while the lowend terminals, l0 and l1, have wiper position values 00(hex). the ds1803 is a volatile device that does not maintain the position of the wiper during powerdown or loss of power. on powerup, the ds1803 wipers' position will be set to position 00(hex) the lowend terminals. the user may then reset the wiper value to a desired position. communication with the ds1803 takes place over the 2wire serial interface consisting of the bidirectional data terminal, sda, and the serial clock input, scl. complete details of the 2wire interface are discussed in the section entitled a2wire serial buso. the 2wire interface and chip select inputs a0, a1, and a2 allow operation of up to eight devices in a bus topol- ogy; with a0, a1, and a2 being the address of the device. application considerations the ds1803 is offered in three standard resistor values which include the 10k w , 50k w , and 100k w . the resolu- tion of the potentiometer is defined as r tot /255, where r tot is the total resistor value of the potentiometer. the ds1803 is designed to operate using 3v or 5v power supplies over the industrial (40 c to +85 c) tempera- ture range. maximum input signal levels across the potentiometer cannot exceed the operating power sup- ply of the device. 2wire serial data bus the ds1803 supports a bidirectional 2wire bus and data transmission protocol. a device that sends data on the bus is defined as a transmitter, and a device receiv- ing data as a receiver. the device that controls the mes- sage is called a amastero. the devices that are con- trolled by the master are aslaveso. the bus must be controlled by a master device which generates the serial clock (scl), controls the bus access, and generates the start and stop conditions. the ds1803 operates as a slave on the 2wire bus. connections to the bus are made via the opendrain i/o lines sda and scl. the following bus protocol has been defined (see figure 2). ? data transfer may be initiated only when the bus is not busy. ? during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high will be interpreted as control signals. accordingly, the following bus conditions have been defined: bus not busy: both data and clock lines remain high. start data transfer: a change in the state of the data line, from high to low, while the clock is high, defines a start condition. stop data transfer: a change in the state of the data line, from low to high, while the clock line is high, defines the stop condition. data valid: the state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line must be changed during the low period of the clock signal. there is one clock pulse per bit of data. figure 2 details how data transfer is accomplished on the 2wire bus. depending upon the state of the r/w * bit, two types of data transfer are possible.
ds1803 062097 3/10 each data transfer is initiated with a start condition and terminated with a stop condition. the number of data bytes transferred between start and stop conditions is not limited, and is determined by the mas- ter device. the information is transferred bytewise and each receiver acknowledges with a ninth bit. within the bus specifications a regular mode (100 khz clock rate) and a fast mode (400 khz clock rate) are defined. the ds1803 works in both modes. acknowledge: each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. the master device must generate an extra clock pulse which is associated with this acknowledge bit. a device that acknowledges must pull down the sda line during the acknowledge clock pulse in such a way that the sda line is stable low during the high period of the acknowledge related clock pulse. of course, setup and hold times must be taken into account. a master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. in this case, the slave must leave the data line high to enable the master to generate the stop condition. 1. data transfer from a master transmitter to a slave receiver: the first byte transmitted by the master is the control byte (slave address). next fol- lows a number of data bytes. the slave returns an acknowledge bit after each received byte. 2. data transfer from a slave transmitter to a mas- ter receiver: the first byte (the slave address) is transmitted by the master. the slave then returns an acknowledge bit. next follows a number of data bytes transmitted by the slave to the master. the master returns an acknowledge bit after all received bytes other than the last byte. at the end of the last received byte, a `not acknowledge' is returned. the master device generates all of the serial clock pulses and the start and stop conditions. a transfer is ended with a stop condition or with a repeated start condition. since a repeated start condition is also the beginning of the next serial transfer, the bus will not be released. the ds1803 may operate in the following two modes: 1. slave receiver mode: serial data and clock are received through sda and scl. after each byte is received, an acknowledge bit is transmitted. start and stop conditions are recognized as the begin- ning and end of a serial transfer. address recogni- tion is performed by hardware after reception of the slave address and direction bit. 2. slave transmitter mode: the first byte is received and handled as in the slave receiver mode. how- ever, in this mode the direction bit will indicate that the transfer direction is reversed. serial data is transmitted on sda by the ds1803 while the serial clock is input on scl. start and stop conditions are recognized as the beginning and end of a serial transfer. slave address a control byte is the first byte received following the start condition from the master device. the control byte consist of a four bit control code; for the ds1803, this is set as 0101 binary for read/write operations. the next three bits of the control byte are the device select bits (a2, a1, a0). they are used by the master device to select which of eight devices are to be accessed. the select bits are in effect the three least significant bits of the slave address. additionally, a2, a1 and a0 can be changed anytime during a powered condition of the part. the last bit of the control byte (r/w *) defines the operation to be performed. when set to a one a read operation is selected, and when set to a zero a write operation is selected. figure 3 shows the control byte structure for the ds1803. following the start condition, the ds1803 monitors the sda bus checking the device type identifier being transmitted. upon receiving the 0101 address code and appropriate device select bits, the slave device outputs an acknowledge signal on the sda line.
ds1803 062097 4/10 command and protocol the command and protocol structure of the ds1803 allows the user to read or write the potentiometer(s). the command structures for the part are presented in figures 4 and 5. potentiometer data values and control and command values are always transmitted most sig- nificant bit (msb) first. during communications the receiving unit always generates the acknowledge. reading the ds1803 as shown in figure 4, the ds1803 provides one read command operation. this operation allows the user to read both potentiometers. specifically, the r/w bit of the control byte is set equal to a 1 for a read operation. communication to read the ds1803 begins with a start condition which is issued by the master device. the control byte from the master device will follow the start condition. once the control byte has been received by the ds1803, the part will respond with an acknowledge. the read/write bit of the control byte as stated should be set equal to `1' for reading the ds1803. when the master has received the acknowledge from the ds1803, the master can then begin to receive potentiometer wiper data. the value of the potentiome- ter0 wiper position will be the first returned from the ds1803. once the eight bits of the potentiometer0 wiper position has been transmitted, the master will need to issue an acknowledge, unless it is the only byte to be read, in which case the master issues a not acknowledge. if desired the master may stop the communication transfer at this point by issuing the stop condition. however, if the value of the potentiom- eter1 wiper position value is needed communication transfer can continue by clocking the remaining eight bits of the potentiometer1 value, followed by an not acknowledge. final communication transfer is ter- minated by issuing the stop command. again the flow of the read operation is presented in figure 4. writing the ds1803 a data flow diagram for writing the ds1803 is shown in figure 5. the ds1803 has three write command opera- tions. these include write pot0, write pot1, and write pot0/1. the write pot0 command allows the user to write the value of potentiometer0 and as an option the the value of potentiometer1. the write1 command allows the user to write the value of potentiometer1 only. the last write command, write0/1, allows the user to write both potentiometers to the same value with one command and one data value being issued. all the write operations begin with a start condition. following the start condition, the master device will issue the control byte. the read/write bit of the control byte will be set to `0' for writing the ds1803. once the control byte has been issued and the master receives the acknowledgment from the ds1803, the command byte is transmitted to the ds1803. as mentioned above, there exist three write operations that can be used with the ds1803. the binary value of each write command is shown in figure 5 and also in the table 1. 2wire command words table 1 command command value write potentiometer0 101010 01 write potentiometer1 101010 10 write both pots 101011 11
ds1803 062097 5/10 absolute maximum ratings* voltage on any pin relative to ground 1.0v to +7.0v operating temperature 40 c to +85 c; industrial storage temperature 55 c to +125 c soldering temperature 260 c for 10 seconds * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. recommended dc operating conditions (40 c to+85 c) parameter symbol min typ max units notes supply voltage v cc +2.7 5.5 v 1 resistor inputs l, h, w gnd0.5 v cc +0.5 v 1 gnd gnd gnd gnd dc electrical conditions (40 c to+85 c; v cc =2.7v to 5.5v) parameter symbol condition min typ max units notes supply current active i cc 200 m a 3 input leakage i li 1 +1 m a wiper resistance r w 400 1000 w wiper current i w 1 ma input logic 1 v ih 0.7v cc v cc +0.5 v 1, 2 input logic 0 v il gnd0.5 0.3v cc v 1, 2 input logic levels a0, a1, a2 input logic 1 input logic 0 0.7v cc gnd0.5 v cc +0.5 0.3v cc v 14 input current each i/o pin 0.4 ds1803 062097 6/10 analog resistor characteristics (40 c to+85 c; v cc =2.7v to 5.5v) parameter symbol min typ max units notes endtoend resistor tolerance 20 +20 % absolute linearity 0.75 lsb 13 relative linearity 0.3 lsb 14 3 db cutoff frequency f cutoff hz 11 temperature coefficient 650 ppm/c capacitance c i 5 pf ac electrical characteristics (40 c to+85 c; v cc =2.7v to 5.5v) parameter symbol min typ max units notes scl clock frequency f sci 0 0 400 100 khz 16 17 bus free time between stop and start condition t buf 1.3 4.7 m s 16 17 hold time (repeated) start condition t hd:sta 0.6 4.0 m s 5 low period of scl clock t low 1.3 4.7 m s high period of scl clock t high 0.6 4.0 m s data hold time t hd:dat 0 0 0.9 m s 6, 7 data setup time t su:dat 100 250 ns 8 rise time of both sda and scl signals t r 20+0.1c b 300 1000 ns 9 fall time of both sda and scl signals t f 20+0.1c b 300 300 ns 9 setup time for stop condition t su:sto 0.6 4.0 m s capacitive load for each bus line c b 400 pf notes: 1. all voltages are referenced to ground. 2. i/o pins of fast mode devices must not obstruct the sda and scl lines if v dd is switched off. 3. i cc specified with sda pin open scl = 400 khz clock rate. 4. i cc specified with v cc at 5.0v and sda, scl = 5.0v, 40 c to +85 c. 5. after this period, the first clock pulse is generated.
ds1803 062097 7/10 6. a device must internally provide a hold time of at least 300 ns for the sda signal (referred to the v ihmin of the scl signal) in order to bridge the undefined region of the falling edge of scl. 7. the maximum t hd:dat has only to be met if the device does not stretch the low period (t low ) of the scl signal. 8. a fast mode device can be used in a standard mode system, but the requirement t su:dat > 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t rmax + t su:dat = 1000 + 250=1250 ns before the scl line is released. 9. c b total capacitance of one bus line in picofarads, timing referenced to (0.9)(v cc ) and (0.1)(v cc ). 10. typical values are for t a = 25 c and nominal supply voltage. 11. 3 db cutoff frequency characteristics for the ds1803 depend on potentiometer total resistance: ds1803010; 1 mhz, ds180350; 200 khz, ds1803100; 100 khz. 12. address inputs, a0, a1, and a2, should be tied to either v cc or gnd depending on the desired address selections. 13. absolute linearity is used to determine wiper voltage versus expected voltage as determined by wiper position. device test limits are 1.6 lsb. 14. relative linearity is used to determine the change in voltage between successive tap positions. device test limits 0.5 lsb. 15. fast mode. 16. standard mode.
ds1803 062097 8/10 ds1803 block diagram figure 1 l0 h0 l1 h1 256to1 multiplexer 256to1 multiplexer command/ control unit w0 w1 potentiometer0 potentiometer1 wiper0 (8bit register) wiper1 (8bit register) a0 a1 a2 device address selection scl sda 2wire serial interface 2wire data transfer overview figure 2 start condition stop condition or repeated start condition repeated if more bytes are transferred sda scl msb slave address r/w direction bit acknowledgement signal from receiver acknowledgement signal from receiver 12 7 6 8 9 1 2 37 8 9 ack ack
msb lsb 0 1 0 1 a2 a1 a0 0 start ack msb lsb ack msb lsb ack pot0/1 value command control data r/w=0 10101111 stop byte byte byte ds1803 062097 9/10 control byte figure 3 msb lsb device identifier device address 0 1 0 1 a2 a1 a0 r/w 2wire read protocols figure 4 msb lsb 0101a2a1a01 start ack msb lsb ack msb lsb ack pot0 pot1 data byte control byte data byte stop r/w=1 optional 2wire write protocols figure 5 write pot0 msb lsb 0 1 0 1 a2 a1 a0 0 start ack msb lsb ack msb lsb ack pot0 command control data r/w=0 10101001 msb lsb ack pot1 data stop optional byte byte byte byte write pot1 msb lsb 0 1 0 1 a2 a1 a0 0 start ack msb lsb ack msb lsb ack pot1 command control data r/w=0 10101010 stop byte byte byte write pot0/1 (same value)
ds1803 062097 10/10 timing diagram figure 6 sda scl t buf t hd:sta t low t r t f t hd:dat t high t su:dat t su:sta t su:sto t sp t hd:sta stop start repeated start ds1803 ordering information ordering number package operating temperature version ds1803010 16l dip 40 c to +85 c 10k w ds1803050 16l dip 40 c to +85 c 50k w ds1803100 16l dip 40 c to +85 c 100k w ds1803e010 14l tssop (173 mil) 40 c to +85 c 10k w ds1803e050 14l tssop (173 mil) 40 c to +85 c 50k w ds1803e100 14l tssop (173 mil) 40 c to +85 c 100k w ds1803z010 16l soic (150 mil) 40 c to +85 c 10k w ds1803z050 16l soic (150 mil) 40 c to +85 c 50k w ds1803z100 16l soic (150 mil) 40 c to +85 c 100k w
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