NTE1757 integrated circuit remote control receiver description: the NTE1757 is an mos/lsi integrated circuit in an 18?lead dip tpye package designed for use as a receiver of remote control signals generated by the nte1755 transmitter circuit, using ppm (pulse position modulation) encoding technique. the receiver has 5 digital outputs whose response to ppm codes may be programmed by six control lines. it has a handshake interface which provides communication with microprocessors and computers. features; 5 open drain outputs with enable handshake or interrupt microprocessor and computer interface signals on?chip oscillator 6 control lines to program output response 3 selectable output modes absolute maximum ratings: v dd supply and all inputs wrt, v ss +0.3 to ?25v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg ?55 to +125 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating ambient temperature range, t a ?10 to +65 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . electrical characteristics : (v ss = 0v, v dd = ?16v, t a = +25 c unless otherwise specified) parameter pin test conditions min typ max unit supply voltage 9 12 ? 18 v supply current 9 ? 6 ? ma input logic level high (?1?) 3?8, 17 ?1 ? 0 v input logic level low (?0?) 3?8, 17 v dd v dd +3.5 v output logic level high (?1?) 10, 12?16 50k to v dd ?1 ? 0 v output logic level low (?0?) 10, 12?16 50k to v dd v dd v dd +0.5 v oscillator frequency 1 typical t c : c = 22nf, r = 100k ? 15 3k 150k hz ppm input logic level high (?1?) 2 ?1 ? 0 v ppm input logic level low (?0?) 2 v dd ? ?6 v ppm input pulse width 2 t = 1/f osc 1 ? 22t osc s power clear time constant 11 1 400 ? ms note 1. r osc (pin 1) is 56k ? , f osc 1 / 0.15cr
pin functions: positive logic: logic ?1? = v ss , 0v logic ?0? = v dd , 16v 1. oscillator tc an rc time constant at this pin defines the internal clock frequency. the clock frequency may be varied from 15hz to 150khz. 2. ppm input the output of the front end amplifier is connected to this pin; the signal must consist of a normal logic ? 0 ? level with pulses to logic ? 1 ? . 3?8. control word c 0 to c 5 six control bits form the control word which programs the response of the five outputs. (see table 1). 9. v dd ? 12v to ? 18v power supply. 10. data ready open drain output. an output of logic ? 1 ? indicates the reception of a valid ppm word. it will remain at logic ? 1 ? for the duration of transmission. 11. power clear a capacitor and resistor connected to this pin define the time delay for the power clear circuit. 12?16. outputs e?a open drain outputs which respond to the ppm input as defined in table 1. 17. output enable a logic ? 1 ? will enable outputs a to e. a logic ? 0 ? will turn all outputs off. 18. v ss 0v (ground). operating notes: the receiver operates on a time scale fixed by an internal oscillator and its external timing components. the oscillator may be adjusted to any value between 15hz and 150khz (allowing different receivers to respond to different transmission rates within the same area). a counter is reset whenever a pulse is received and allowed to count at half the oscillator frequency. for example, at an oscillator frequency of 1.5khz, resetting is blocked for the first 14ms and windows from 22ms to 40ms determine whether a ? 1 ? or ? 0 ? is present. periods between pulses of 40ms to 80ms are recognized as word intervals. checks are made to ensure 6 pulses of 5 bits, are received for a word to be valid, and only after two consecutive and identical words is the receiver allowed to respond to the incoming code. by means of the six control lines, the outputs can respond to the ppm input data in three ways: 1. 5 bit binary output with combinations of latched or momentary output as shown in table 1. 2. 4 independent outputs with combinations of latched or momentary output as shown in table 1. any output on 1 or 4 receivers can be addressed by each ppm word. 3. the ppm word can be an address or data depending on the logic state of bit ? e ? . if ppm bit ? e ? is ? 0 ? , the remaining four bits ( ? a ? , ? b ? , ? c ? , and ? d ? ) control the outputs a to d. outputs can be all latched or all momentary. table 1: control word control output response interpretation pf ppm words c5 c4 c3 c2 c1 c0 mode e d c b a e d c b a e d c b a 0 0 0 0 0 0 1 la la la la la e d c b a 0 0 0 0 0 1 1 la la la la m 0 0 0 0 1 1 1 la la la m m 0 0 0 1 1 1 1 la la m m m ppm decoded on all outputs 0 0 1 1 1 1 1 la m m m m on all outputs immediately 0 1 1 1 1 1 1 m m m m m 0 0 1 0 z z 2 ? s/r s/r s/r s/r 0 y y z z 1 y y z z 0 1 0 0 z z 2 ? s/r s/r s/r m 0 1 0 1 z z 2 ? s/r s/r m m output receiver output receiver 0 1 1 0 z z 2 ? s/r m m m output address receiver address output address receiver address sets an s/r type resets an s/r type output output or pulses a momentary output momentary output 1 0 z z z z 3 ? la la la la 0 z z z z 1 d c b a 1 1 z z z z 3 ? m m m m address receiver data ppm data sent address mode receiver address data mode ppm data sent to outputs of addressed receiver receiver
notes: 1. control mode 1: direct response to the ppm code 2. control mode 2: zz is a 2 bit address for the receiver yy selects one of 4 outputs yy output 00 a 01 b 10 c 11 d 3. control mode 3: zzzz is a 4 bit address that selects, by which of 16ppm codes a receiver will be selected. if ppm bit e = ? 1 ? , the rest of that ppm word will be read as data. if ppm bit e = ? 0 ? , the rest of that ppm word will be read as an address. pin connection diagram v cc v dd c data ready output enable e power on clear 1 2 3 4 osc time constant ppm input c0 c1 5 c2 6 c3 7 c4 8 c5 18 17 16 15 a b 14 13 d 12 11 9 10 control inputs binary outputs .870 (22.1) max .800 (20.3) .125 (3.17) min .100 (2.54) .250 (6.35) .150 (3.8) 19 18 10
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