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s-1009 series www.sii-ic.com super-low current consumption super high-accuracy voltage detector with delay circuit (external delay time setting) ? seiko instruments inc., 2009-2011 rev.4.2 _00 seiko instruments inc. 1 the s-1009 series is a super high-accuracy voltage detecto r developed using cmos process. the detection voltage is fixed internally with an accuracy of 0.5%. it operates with super low curr ent consumption of 270 na typ. the release signal can be delayed by setting a capacitor externally. delay time accuracy is 15%. two output forms nch open drain and cmos output are available. compared with conventional cmos voltage detectors, the s-1009 series is the most suitable for the portable devices due to the super-low current consumption, super high-accuracy and small packages. ? features ? super-low current consumption 270 na typ. (1.2 v ? v det < 2.3 v) ? super high-accuracy detection voltage 0.5% (2.4 v ? v det 4.6 v) 12 mv (0.8 v ? v det < 2.4 v) ? operating voltage range 0.6 v to 10.0 v (cmos output products) ? hysteresis characteristics 5% 1% ? delay time accuracy 15% (c d = 4.7 nf) ? detection voltage 0.8 v to 4.6 v (0.1 v step) ? output form nch open drain output (active ?l?) cmos output (active ?l?) ? lead-free (sn 100%), halogen-free *1 *1. refer to ? ? product name structure ? for details. ? applications ? power monitor and reset for cpus and microcomputers ? constant voltage power monitor for tvs, dvd recorders and home appliances ? power supply monitor for portable devices such as notebook pcs, digital still cameras and mobile phones ? packages ? sc-82ab ? sot-23-5
super-low current consumption super high-accuracy voltage de tector with delay circuit (external delay time setting) s-1009 series rev.4.2 _00 seiko instruments inc. 2 ? block diagrams 1. nch open drain output products vss *1 *1 v ref ? + out vdd cd delay circuit *1 *1. parasitic diode figure 1 2. cmos output products vss *1 *1 v ref ? + out vdd cd delay circuit *1 *1 *1. parasitic diode figure 2
super-low current consumption super high-accuracy voltage de tector with delay circuit (external delay time setting) rev.4.2 _00 s-1009 series seiko instruments inc. 3 ? product name structure users can select the detection volta ge value, output form, and package type for the s-1009 series. refer to ? 1. product name ? regarding the contents of product name, ? 2. packages ? regarding the package drawings and ? 3. product name list ? regarding details of product name. 1. product name s-1009 x xx i ? xxxx u output form n: nch open drain output (active ?l?) c: cmos output (active ?l?) package abbreviation and ic packing specifications *1 m4t1: sc-82ab, tape m5t1: sot-23-5, tape detection voltage value 08 to 46 (e.g., when the detection voltage is 1.5 v, it is expressed as 15.) environmental code u: lead-free (sn 100%), halogen-free *1. refer to the tape specifications. 2. packages drawing code package name package tape reel sc-82ab np004-a-p-sd np004-a-c-sd np004-a-c-s1 np004-a-r-sd sot-23-5 mp005-a-p-sd mp005-a-c-sd mp005-a-r-sd
super-low current consumption super high-accuracy voltage de tector with delay circuit (external delay time setting) s-1009 series rev.4.2 _00 seiko instruments inc. 4 3. product name list 3. 1 nch open drain output products table 1 detection voltage sc-82ab sot-23-5 0.8 v 12 mv s-1009n08i-n4t1u s-1009n08i-m5t1u 0.9 v 12 mv s-1009n09i-n4t1u s-1009n09i-m5t1u 1.0 v 12 mv s-1009n10i-n4t1u s-1009n10i-m5t1u 1.1 v 12 mv s-1009n11i-n4t1u S-1009N11I-M5T1U 1.2 v 12 mv s-1009n12i-n4t1u s-1009n12i-m5t1u 1.3 v 12 mv s-1009n13i-n4t1u s-1009n13i-m5t1u 1.4 v 12 mv s-1009n14i-n4t1u s-1009n14i-m5t1u 1.5 v 12 mv s-1009n15i-n4t1u s-1009n15i-m5t1u 1.6 v 12 mv s-1009n16i-n4t1u s-1009n16i-m5t1u 1.7 v 12 mv s-1009n17i-n4t1u s-1009n17i-m5t1u 1.8 v 12 mv s-1009n18i-n4t1u s-1009n18i-m5t1u 1.9 v 12 mv s-1009n19i-n4t1u s-1009n19i-m5t1u 2.0 v 12 mv s-1009n20i-n4t1u s-1009n20i-m5t1u 2.1 v 12 mv s-1009n21i-n4t1u s-1009n21i-m5t1u 2.2 v 12 mv s-1009n22i-n4t1u s-1009n22i-m5t1u 2.3 v 12 mv s-1009n23i-n4t1u s-1009n23i-m5t1u 2.4 v 0.5% s-1009n24i-n4t1u s-1009n24i-m5t1u 2.5 v 0.5% s-1009n25i-n4t1u s-1009n25i-m5t1u 2.6 v 0.5% s-1009n26i-n4t1u s-1009n26i-m5t1u 2.7 v 0.5% s-1009n27i-n4t1u s-1009n27i-m5t1u 2.8 v 0.5% s-1009n28i-n4t1u s-1009n28i-m5t1u 2.9 v 0.5% s-1009n29i-n4t1u s-1009n29i-m5t1u 3.0 v 0.5% s-1009n30i-n4t1u s-1009n30i-m5t1u 3.1 v 0.5% s-1009n31i-n4t1u s-1009n31i-m5t1u 3.2 v 0.5% s-1009n32i-n4t1u s-1009n32i-m5t1u 3.3 v 0.5% s-1009n33i-n4t1u s-1009n33i-m5t1u 3.4 v 0.5% s-1009n34i-n4t1u s-1009n34i-m5t1u 3.5 v 0.5% s-1009n35i-n4t1u s-1009n35i-m5t1u 3.6 v 0.5% s-1009n36i-n4t1u s-1009n36i-m5t1u 3.7 v 0.5% s-1009n37i-n4t1u s-1009n37i-m5t1u 3.8 v 0.5% s-1009n38i-n4t1u s-1009n38i-m5t1u 3.9 v 0.5% s-1009n39i-n4t1u s-1009n39i-m5t1u 4.0 v 0.5% s-1009n40i-n4t1u s-1009n40i-m5t1u 4.1 v 0.5% s-1009n41i-n4t1u s-1009n41i-m5t1u 4.2 v 0.5% s-1009n42i-n4t1u s-1009n42i-m5t1u 4.3 v 0.5% s-1009n43i-n4t1u s-1009n43i-m5t1u 4.4 v 0.5% s-1009n44i-n4t1u s-1009n44i-m5t1u 4.5 v 0.5% s-1009n45i-n4t1u s-1009n45i-m5t1u 4.6 v 0.5% s-1009n46i-n4t1u s-1009n46i-m5t1u
super-low current consumption super high-accuracy voltage de tector with delay circuit (external delay time setting) rev.4.2 _00 s-1009 series seiko instruments inc. 5 3. 2 cmos output products table 2 detection voltage sc-82ab sot-23-5 0.8 v 12 mv s-1009c08i-n4t1u s-1009c08i-m5t1u 0.9 v 12 mv s-1009c09i-n4t1u s-1009c09i-m5t1u 1.0 v 12 mv s-1009c10i-n4t1u s-1009c10i-m5t1u 1.1 v 12 mv s-1009c11i-n4t1u s-1009c11i-m5t1u 1.2 v 12 mv s-1009c12i-n4t1u s-1009c12i-m5t1u 1.3 v 12 mv s-1009c13i-n4t1u s-1009c13i-m5t1u 1.4 v 12 mv s-1009c14i-n4t1u s-1009c14i-m5t1u 1.5 v 12 mv s-1009c15i-n4t1u s-1009c15i-m5t1u 1.6 v 12 mv s-1009c16i-n4t1u s-1009c16i-m5t1u 1.7 v 12 mv s-1009c17i-n4t1u s-1009c17i-m5t1u 1.8 v 12 mv s-1009c18i-n4t1u s-1009c18i-m5t1u 1.9 v 12 mv s-1009c19i-n4t1u s-1009c19i-m5t1u 2.0 v 12 mv s-1009c20i-n4t1u s-1009c20i-m5t1u 2.1 v 12 mv s-1009c21i-n4t1u s-1009c21i-m5t1u 2.2 v 12 mv s-1009c22i-n4t1u s-1009c22i-m5t1u 2.3 v 12 mv s-1009c23i-n4t1u s-1009c23i-m5t1u 2.4 v 0.5% s-1009c24i-n4t1u s-1009c24i-m5t1u 2.5 v 0.5% s-1009c25i-n4t1u s-1009c25i-m5t1u 2.6 v 0.5% s-1009c26i-n4t1u s-1009c26i-m5t1u 2.7 v 0.5% s-1009c27i-n4t1u s-1009c27i-m5t1u 2.8 v 0.5% s-1009c28i-n4t1u s-1009c28i-m5t1u 2.9 v 0.5% s-1009c29i-n4t1u s-1009c29i-m5t1u 3.0 v 0.5% s-1009c30i-n4t1u s-1009c30i-m5t1u 3.1 v 0.5% s-1009c31i-n4t1u s-1009c31i-m5t1u 3.2 v 0.5% s-1009c32i-n4t1u s-1009c32i-m5t1u 3.3 v 0.5% s-1009c33i-n4t1u s-1009c33i-m5t1u 3.4 v 0.5% s-1009c34i-n4t1u s-1009c34i-m5t1u 3.5 v 0.5% s-1009c35i-n4t1u s-1009c35i-m5t1u 3.6 v 0.5% s-1009c36i-n4t1u s-1009c36i-m5t1u 3.7 v 0.5% s-1009c37i-n4t1u s-1009c37i-m5t1u 3.8 v 0.5% s-1009c38i-n4t1u s-1009c38i-m5t1u 3.9 v 0.5% s-1009c39i-n4t1u s-1009c39i-m5t1u 4.0 v 0.5% s-1009c40i-n4t1u s-1009c40i-m5t1u 4.1 v 0.5% s-1009c41i-n4t1u s-1009c41i-m5t1u 4.2 v 0.5% s-1009c42i-n4t1u s-1009c42i-m5t1u 4.3 v 0.5% s-1009c43i-n4t1u s-1009c43i-m5t1u 4.4 v 0.5% s-1009c44i-n4t1u s-1009c44i-m5t1u 4.5 v 0.5% s-1009c45i-n4t1u s-1009c45i-m5t1u 4.6 v 0.5% s-1009c46i-n4t1u s-1009c46i-m5t1u
super-low current consumption super high-accuracy voltage de tector with delay circuit (external delay time setting) s-1009 series rev.4.2 _00 seiko instruments inc. 6 ? pin configurations 1. sc-82ab table 3 pin no. symbol description 1 vss gnd pin 2 vdd input voltage pin 3 cd connection pin for delay capacitor 4 out voltage detection output pin 4 3 1 2 sc-82ab top view figure 3 2. sot-23-5 table 4 pin no. symbol description 1 out voltage detection output pin 2 vdd input voltage pin 3 vss gnd pin 4 nc *1 no connection 5 cd connection pin for delay capacitor *1. the nc pin is electrically open. the nc pin can be connected to vdd or vss. 5 4 1 3 2 sot-23-5 top view figure 4
super-low current consumption super high-accuracy voltage de tector with delay circuit (external delay time setting) rev.4.2 _00 s-1009 series seiko instruments inc. 7 ? absolute maximum ratings table 5 (ta = + 25c unless otherwise specified) item symbol absolute maximum rating unit power supply voltage v dd ? v ss 12 v cd pin input voltage v cd v ss ? 0.3 to v dd + 0.3 v nch open drain output products v ss ? 0.3 to 12.0 v output voltage cmos output products v out v ss ? 0.3 to v dd + 0.3 v output current i out 50 ma sc-82ab 350 *1 mw power dissipation sot-23-5 p d 600 *1 mw operating ambient temperature t opr ? 40 to + 85 c storage temperature t stg ? 40 to + 125 c *1. when mounted on board [mounted board] (1) board size: 114.3 mm 76.2 mm t1.6 mm (2) name: jedec standard51-7 caution the absolute maximum ratings are rated values exceeding which the product could suffer physical damage. these values must therefor e not be exceeded under any conditions. 0 50 100 150 0 power dissipation (p d ) [mw] ambient temperature (ta) [ c] 200 100 300 500 700 sot-23-5 sc-82ab 400 600 figure 5 power dissipation of package
super-low current consumption super high-accuracy voltage de tector with delay circuit (external delay time setting) s-1009 series rev.4.2 _00 seiko instruments inc. 8 ? electrical characteristics 1. nch open drain output products table 6 (ta = + 25c unless otherwise specified) item symbol conditions min. typ. max. unit test circuit 0.8 v ? v det < 2.4 v ? v det(s) ? 0.012 ? v det(s) ? v det(s) + 0.012 v 1 detection voltage *1 ? v det 2.4 v ? v det 4.6 v ? v det(s) 0.995 ? v det(s) ? v det(s) 1.005 v 1 hysteresis width v hys ? ? v det 0.04 ? v det 0.05 ? v det 0.06 v 1 0.8 v ? v det < 1.2 v ? 0.30 0.90 a 2 1.2 v ? v det < 2.3 v ? 0.27 0.90 a 2 2.3 v ? v det < 3.6 v ? 0.42 0.90 a 2 current consumption i ss v dd = + v det + 0.6 v 3.6 v ? v det 4.6 v ? 0.39 0.90 a 2 operating voltage v dd ? 0.7 ? 10.0 v 1 v dd = 0.7 v s-1009n08 to 14 0.14 0.40 ? ma 3 v dd = 1.2 v s-1009n15 to 46 0.73 1.33 ? ma 3 output current i out output transistor, nch, v ds = 0.5 v v dd = 2.4 v s-1009n27 to 46 1.47 2.39 ? ma 3 leakage current i leak output transistor, nch, v dd = 10.0 v, v out = 10.0 v ? ? 0.08 a 3 delay time t d c d = 4.7 nf 22.1 26.0 29.9 ms 4 0.8 v ? v det < 0.9 v ? 180 430 ppm/c 1 0.9 v ? v det < 1.2 v ? 120 370 ppm/c 1 detection voltage temperature coefficient *2 ? v det ta ? ? v det ta = ? 40c to + 85c 1.2 v ? v det 4.6 v ? 100 350 ppm/c 1 *1. ? v det : actual detection voltage value, ? v det(s) : specified detection voltage value (the center value of the detection voltage range in table 1 .) *2. the temperature change of the detection voltage [mv/c] is calculated by using the following equation. ? v det ta [] mv/c *1 = ? v det(s) (typ.) [] v *2 ? v det ta ? ? v det [] ppm/c *3 1000 *1. temperature change of the detection voltage *2. specified detection voltage *3. detection voltage temperature coefficient
super-low current consumption super high-accuracy voltage de tector with delay circuit (external delay time setting) rev.4.2 _00 s-1009 series seiko instruments inc. 9 2. cmos output products table 7 (ta = + 25c unless otherwise specified) item symbol conditions min. typ. max. unit test circuit 0.8 v ? v det < 2.4 v ? v det(s) ? 0.012 ? v det(s) ? v det(s) + 0.012 v 1 detection voltage *1 ? v det 2.4 v ? v det 4.6 v ? v det(s) 0.995 ? v det(s) ? v det(s) 1.005 v 1 hysteresis width v hys ? ? v det 0.04 ? v det 0.05 ? v det 0.06 v 1 0.8 v ? v det < 1.2 v ? 0.30 0.90 a 2 1.2 v ? v det < 2.3 v ? 0.27 0.90 a 2 2.3 v ? v det < 3.6 v ? 0.42 0.90 a 2 current consumption i ss v dd = + v det + 0.6 v 3.6 v ? v det 4.6 v ? 0.39 0.90 a 2 operating voltage v dd ? 0.6 ? 10.0 v 1 v dd = 0.7 v s-1009c08 to 14 0.14 0.40 ? ma 3 v dd = 1.2 v s-1009c15 to 46 0.73 1.33 ? ma 3 output transistor, nch, v ds = 0.5 v v dd = 2.4 v s-1009c27 to 46 1.47 2.39 ? ma 3 v dd = 4.8 v s-1009c08 to 39 1.62 2.60 ? ma 5 output current i out output transistor, pch, v ds = 0.5 v v dd = 6.0 v s-1009c40 to 46 1.78 2.86 ? ma 5 delay time t d c d = 4.7 nf 22.1 26.0 29.9 ms 4 0.8 v ? v det < 0.9 v ? 180 430 ppm/c 1 0.9 v ? v det < 1.2 v ? 120 370 ppm/c 1 detection voltage temperature coefficient *2 ? v det ta ? ? v det ta = ? 40c to + 85c 1.2 v ? v det 4.6 v ? 100 350 ppm/c 1 *1. ? v det : actual detection voltage value, ? v det(s) : specified detection voltage value (the center value of the detection voltage range in table 2 .) *2. the temperature change of the detection voltage [mv/c] is calculated by using the following equation. ? v det ta [] mv/c *1 = ? v det(s) (typ.) [] v *2 ? v det ta ? ? v det [] ppm/c *3 1000 *1. temperature change of the detection voltage *2. specified detection voltage *3. detection voltage temperature coefficient
super-low current consumption super high-accuracy voltage de tector with delay circuit (external delay time setting) s-1009 series rev.4.2 _00 seiko instruments inc. 10 ? test circuits 1. s-1009 series v dd vdd vss out r *1 100 k v v cd 2. s-1009 series v dd out a vdd vss cd *1. r is unnecessary for cmos output products. figure 6 figure 7 3. v ds v dd out a v v vdd vss cd s-1009 series 4. s-1009 series vdd vss out r *1 100 k cd oscilloscope p.g. *1. r is unnecessary for cmos output products. *1. r is unnecessary for cmos output products. figure 8 figure 9 5. v dd v ds out a v v vdd vss cd s-1009 series figure 10
super-low current consumption super high-accuracy voltage de tector with delay circuit (external delay time setting) rev.4.2 _00 s-1009 series seiko instruments inc. 11 ? timing chart 1. nch open drain output products v out vdd vss r 100 k release voltage ( + v det ) detection voltage ( ? v det ) v dd v ss minimum operating voltage hysteresis width (v hys ) v dd v ss cd output from the out pin t d figure 11 2. cmos output products t d v vdd vss release voltage ( + v det ) detection voltage ( ? v det ) v dd v ss minimum operating voltage hysteresis width (v hys ) output from the out pin v ss v dd out cd remark when v dd is the minimum operating voltage or less, the output voltage from the out pin is indefinite in the shaded area. figure 12
super-low current consumption super high-accuracy voltage de tector with delay circuit (external delay time setting) s-1009 series rev.4.2 _00 seiko instruments inc. 12 ? operation 1. basic operation: cmos output (active ?l?) (1) when the power supply voltage (v dd ) is the release voltage ( + v det ) or more, the nch transistor is off and the pch transistor is on to output v dd (?h?). since the nch transistor n1 in figure 13 is off, the comparator input voltage is (r b + r c ) ? v dd r a + r b + r c . (2) although v dd decreases to + v det or less, the output is v dd when v dd is the detection voltage ( ? v det ) or more. when v dd decreases to ? v det or less (a in figure 14 ), the nch transistor is on and the pch transistor is off so that v ss is output. the nch transistor n1 in figure 13 is turned on, and the input voltage to the comparator is r b ? v dd r a + r b . (3) the output is indefinite by decreasing v dd to the ic?s minimum operating voltage or less. if the output is pulled up, it will be v dd . (4) v ss is output by increasing v dd to the minimum operating voltage or more. although v dd exceeds ? v det and v dd is less than + v det , the output is v ss . (5) when increasing v dd to + v det or more (b in figure 14 ), the nch transistor is off and the pch transistor is on so that v dd is output. v dd output to the out pin delays in t d by the delay circuit. vss *1 *1 v ref ? + out vdd cd delay circuit *1 *1 c d pch nch n1 r c r a r b *1. parasiteic diode figure 13 operation 1 hysteresis width (v hys ) a b v dd v ss minimum operating voltage output from out pin v dd v ss (1) (2) (3) (5) (4) release voltage ( + v det ) detection voltage ( ? v det ) t d figure 14 operation 2
super-low current consumption super high-accuracy voltage de tector with delay circuit (external delay time setting) rev.4.2 _00 s-1009 series seiko instruments inc. 13 2. delay circuit the delay circuit delays the output signal to the out pin from the time at which the power voltage (v dd ) exceeds the release voltage ( + v det ) when v dd is turned on. the output signal is not delayed when v dd decreases to the detection voltage ( ? v det ) or less (refer to figure 14 ). the delay time (t d ) is determined by the time constant of the built-in constant current (approx. 100 na) and the attached external capacitor (c d ), or the delay time (t d0 ) when the cd pin is open, and calculated from the following equation. t d [ms] = delay coefficient c d [nf] + t d0 [ms] delay coefficient ( + 85c) : min. 2.82, typ. 4.20, max. 5.72 delay coefficient ( + 25c) : min. 4.70, typ. 5.47, max. 6.24 delay coefficient ( ? 40c) : min. 5.64, typ. 8.40, max. 12.01 t d0 ( ? 40c to + 85c) : min. 0.01 ms, typ. 0.10 ms, max. 0.24 ms when the c d value is sufficiently large, the t d0 value can be disregarded. caution 1. when the cd pin is open, a double pulse shown in figure 15 may appear at release. to avoid the double pulse, attach 100 pf or larger capacitor to the cd pin. do not apply voltage to the cd pin from the exterior. v out time figure 15 2. print circuit board layout should be made in such a way that no current flows into or flows from the cd pin since the impedance of the cd pin is high, otherwise correct delay time cannot be provided. 3. there is no limit for the capacitance of the external capacitor (c d ) as long as the leakage current of the capaci tor can be ignored against the buil t-in constant current value. leakage current causes deviation in delay time. when the leakage current is larger than the built-in constant current, no release takes place.
super-low current consumption super high-accuracy voltage de tector with delay circuit (external delay time setting) s-1009 series rev.4.2 _00 seiko instruments inc. 14 3. other characteristics 3. 1 temperature characteristics of detection voltage the shaded area in figure 16 shows the temperature characteristics of the detection voltage in the operating temperature range. ? 40 25 + 0.945 mv/c ? v det [v] 85 ta [c] ? 0.945 mv/c ? v det25 *1 *1. ? v det25 is an actual detection voltage value at + 25c. figure 16 temperature characteristics of detection voltage (example for ? v det = 2.7 v) 3. 2 temperature characteristics of release voltage the temperature change + v det ta of the release voltage is calculated by using the temperature change ? v det ta of the detection voltage as follows: + v det ta = + v det ? v det ? v det ta the temperature change of the release voltage and the detection voltage has the same sign consequently. 3. 3 temperature characteristics of hysteresis voltage the temperature change of the hysteresis voltage is expressed as + v det ta ? ? v det ta and is calculated as follows: + v det ta ? ? v det ta = v hys ? v det ? v det ta
super-low current consumption super high-accuracy voltage de tector with delay circuit (external delay time setting) rev.4.2 _00 s-1009 series seiko instruments inc. 15 ? standard circuit vdd out vss r *1 100 k c d *2 cd *1. r is unnecessary for cmos output products. *2. the delay capacitor (c d ) should be connected directly to the cd pin and to the vss pin. figure 17 caution the above connection diagram and constant will not guarantee successful operation. perform thorough evaluation using the actual application to set the constant.
super-low current consumption super high-accuracy voltage de tector with delay circuit (external delay time setting) s-1009 series rev.4.2 _00 seiko instruments inc. 16 ? explanation of terms 1. detection voltage ( ? v det ), release voltage ( + v det ) the detection voltage ( ? v det ) is a voltage at which the output turns to ?l?. the detection voltage varies slightly among products of the same specification. the variation of detection voltage between the specified minimum ( ? v det ) min. and the maximum ( ? v det ) max. is called the detection voltage range (refer to figure 18 ). example: in the s-1009c15, the detection voltage is either one in the range of 1.488 ( ? v det ) 1.512. this means that some s-1009c15s have ? v det = 1.488 v and some have ? v det = 1.512 v. the release voltage is a voltage at which the output turns to ?h?. the release voltage varies slightly among products of the same specification. the variation of release voltages between the specified minimum ( + v det ) min. and the maximum ( + v det ) max. is called the release voltage range (refer to figure 19 ). the range is calculated from the actual detection voltage ( ? v det ) of a product and is in the range of ? v det 1.04 + v det ? v det 1.06. example: for the s-1009c15, the release voltage is either one in the range of 1.548 ( + v det ) 1.602. this means that some s-1009c15s have + v det = 1.548 v and some have + v det = 1.602 v. detection voltage detection voltage range v dd ( ? v det ) min. ( ? v det ) max. out release voltage release voltage range v dd ( + v det ) min. ( + v det ) max. out delay time figure 18 detection voltage (cmos output products) figure 19 release voltage (cmos output products)
super-low current consumption super high-accuracy voltage de tector with delay circuit (external delay time setting) rev.4.2 _00 s-1009 series seiko instruments inc. 17 2. hysteresis width (v hys ) the hysteresis width is the voltage difference between the detection voltage and the release voltage (the voltage at point b ? the voltage at point a = v hys in figure 14 ). setting the hysteresis width between the detection voltage and the release voltage, prevents malfunction caused by noise on the input voltage. 3. delay time (t d ) the delay time in the s-1009 series is a period from the input voltage to the v dd pin exceeding the release voltage ( + v det ) until the output from the out pin inverts. the delay time changes according to the external capacitor (c d ). t d v dd out v + v det figure 20 delay time 4. through-type current through-type current is a current that flows instantaneously at the time of detection and release of a voltage detector. the through-type current is large in cmos output products, small in nch open drain output products. 5. oscillation in applications where a resistor is connected to the voltage detector input ( figure 21 ), taking a cmos active ?l? product for example, the thr ough-type current which is generated when t he output goes from ?l? to ?h? (release) causes a voltage drop equal to [through-type current] [input resistance] across the resistor. when the input voltage drops below the detection voltage ( ? v det ) as a result, the output voltage goes to low level. in this state, the through-type current stops and its resultant voltage drop disappears, and the output goes from ?l? to ?h?. the through-type current is then generated again, a voltage drop appears, and repeating the process finally induces oscillation. out vss vdd r b r a v in s-1009c figure 21 an example for bad implementation due to detection voltage change
super-low current consumption super high-accuracy voltage de tector with delay circuit (external delay time setting) s-1009 series rev.4.2 _00 seiko instruments inc. 18 ? precautions ? do not apply an electrostatic discharge to this ic that exceeds the performance ratings of the built-in electrostatic protection circuit. ? in cmos output products of the s-1009 series, the throu gh-type current flows at the detection and the release. if the input impedance is high, oscillation may occur due to the voltage drop by the through-type current during releasing. ? in cmos output products oscillation may occur when a pull-down resistor is used, and falling speed of the power supply voltage (v dd ) is slow near the detection voltage. ? when designing for mass production using an application circuit described herein, the product deviation and temperature characteristics of the external parts should be taken into consideration. sii shall not bear any responsibility for patent infringements related to products using the circuits described herein. ? sii claims no responsibility for any disputes arising out of or in connection with any infringement by products including this ic of patents owned by a third party.
super-low current consumption super high-accuracy voltage de tector with delay circuit (external delay time setting) rev.4.2 _00 s-1009 series seiko instruments inc. 19 ? characteristics (typical data) 1. detection voltage (v det ) ? temperature (ta) s-1009n08 0.90 0.85 0.80 0.75 0.70 v det [v] ta [c] ? 40 85 ? 25 250 75 50 +v det ?v det s-1009n11 1.20 1.15 1.10 1.05 1.00 v det [v] ta [c] ? 40 85 ? 25 250 75 50 +v det ?v det s-1009n12 ? 40 v det [v] 1.00 ta [c] 1.40 1.10 1.20 1.30 85 ? 25 250 75 50 +v det ?v det s-1009n46 ? 40 v det [v] 4.20 ta [c] 5.00 4.40 4.60 4.80 85 ? 25 250 75 50 +v det ?v det 2. hysteresis voltage width (v hys ) ? temperature (ta) s-1009n08 8 3 ? 40 ta [c] 7 6 5 4 v hys [%] ? 40 85 ? 25 250 75 50 s-1009n11 8 3 ? 40 ta [c] 7 6 5 4 v hys [%] ? 40 85 ? 25 250 75 50 s-1009n12 ? 40 v hys [%] 3 ta [c] 8 4 5 6 7 85 ? 25 250 75 50 s-1009n46 ? 40 v hys [%] 3 ta [c] 8 4 5 6 7 85 ? 25 250 75 50
super-low current consumption super high-accuracy voltage de tector with delay circuit (external delay time setting) s-1009 series rev.4.2 _00 seiko instruments inc. 20 3. current consumption (i ss ) ? input voltage (v dd ) s-1009c08 ta = + 25c 1.50 1.25 1.00 0.75 0.50 0.25 0 0246810 i ss [a] v dd [v] s-1009c11 ta = + 25c 1.00 0 0246810 i ss [a] v dd [v] 0.75 0.50 0.25 s-1009c12 ta = + 25c 0 i ss [a] 0 v dd [v] 1.0 0.50 0.25 0.75 10 46 2 8 s-1009c46 ta = + 25c 0 i ss [a] 0 v dd [v] 1.0 0.50 0.25 0.75 10 46 2 8 4. current consumption (i ss ) ? temperature (ta) s-1009n08 v dd = + v det + 0.6 v 1.00 0.75 0.50 0.25 0 ta [c] i ss [a] ? 40 85 ? 25 250 75 50 s-1009n11 v dd = + v det + 0.6 v 1.00 0.75 0.50 0.25 0 ta [c] i ss [a] ? 40 85 ? 25 250 75 50 s-1009n12 v dd = + v det + 0.6 v ? 40 i ss [a] 0 ta [c] 1.00 0.25 0.50 0.75 85 ? 25 250 75 50 s-1009n46 v dd = + v det + 0.6 v ? 40 i ss [a] 0 ta [c] 1.00 0.25 0.50 0.75 85 ? 25 250 75 50
super-low current consumption super high-accuracy voltage de tector with delay circuit (external delay time setting) rev.4.2 _00 s-1009 series seiko instruments inc. 21 5. nch transistor output current (i out ) ? v ds 6. pch transistor output current (i out ) ? v ds s-1009n46 ta = + 25c 0 i out [ma] 0 v ds [v] 15.0 5.0 2.5 10.0 7.5 12.5 4.0 1.0 1.5 0.5 3.0 3.5 2.5 2.0 v dd = 3.6 v 2.4 v 1.2 v 1.0 v s-1009c08 ta = + 25c 0 i out [ma] 0 v ds [v] 40.0 10.0 30.0 20.0 10.0 4.02.0 8.0 6.0 v dd = 8.4 v 7.2 v 6.0 v 4.8 v 3.6 v 2.4 v 1.2 v 7. nch transistor output current (i out ) ? input voltage (v dd ) 8. pch transistor output current (i out ) ? input voltage (v dd ) s-1009n46 v ds = 0.5 v 0 i out [ma] 0 v dd [v] 4.0 1.0 3.0 2.0 6.0 3.02.01.0 5.0 4.0 ta = ?40c +25c +85c s-1009c08 v ds = 0.5 v 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0246810 v dd [v] i out [ma] ta = ?40c +25c +85c
super-low current consumption super high-accuracy voltage de tector with delay circuit (external delay time setting) s-1009 series rev.4.2 _00 seiko instruments inc. 22 9. minimum operating voltage ? input voltage (v dd ) s-1009n08 pull-up to v dd pull-up resistance: 100 k 1.2 1.0 0.8 0.6 0.4 0.2 0 0 0.2 0.4 0.6 0.8 1.0 v dd [v] v out [v] ta = ?40c +25c +85c s-1009n11 pull-up to v dd pull-up resistance: 100 k 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 0.2 0.4 0.6 0.8 1.0 1.2 v dd [v] v out [v] ta = ?40c +25c +85c s-1009n12 pull-up to v dd pull-up resistance: 100 k 0 v out [v] 0 v dd [v] 1.6 0.4 1.2 0.8 1.4 0.80.60.40.2 1.2 1.0 ta = ?40c +25c +85c s-1009n46 pull-up to v dd pull-up resistance: 100 k 0 v out [v] 0 v dd [v] 6.0 1.0 3.0 2.0 4.0 5.0 5.04.03.02.01.0 ta = ?40c +25c +85c s-1009n08 pull-up to 10 v pull-up resistance: 100 k 12.0 10.0 8.0 6.0 4.0 2.0 0 0 0.2 0.4 0.6 0.8 1.0 v dd [v] v out [v] ta = ?40c +25c +85c s-1009n11 pull-up to 10 v pull-up resistance: 100 k 12.0 0 0 0.2 0.4 0.6 0.8 1.0 1.2 v dd [v] v out [v] 10.0 8.0 6.0 4.0 2.0 ta = ?40c +25c +85c s-1009n12 pull-up to 10 v pull-up resistance: 100 k 0 v out [v] 0 v dd [v] 12.0 2.0 8.0 6.0 10.0 4.0 1.4 0.80.60.40.2 1.2 1.0 ta = ?40c +25c +85c s-1009n46 pull-up to 10 v pull-up resistance: 100 k 0 v out [v] 0 v dd [v] 12.0 2.0 6.0 4.0 8.0 10.0 5.04.03.02.01.0 ta = ?40c +25c +85c
super-low current consumption super high-accuracy voltage de tector with delay circuit (external delay time setting) rev.4.2 _00 s-1009 series seiko instruments inc. 23 10. dynamic response ? c out (cd pin; open) s-1009c08 0.00001 response time [ms] 0.001 output pin capacitance [ f] 1 0.01 0.1 0.1 0.0001 0.01 0.001 t plh t phl s-1009n08 0.00001 response time [ms] 0.001 output pin capacitance [ f] 10 1 0.01 0.1 0.1 0.0001 0.01 0.001 t plh t phl s-1009c11 0.00001 response time [ms] 0.001 output pin capacitance [ f] 1 0.01 0.1 0.1 0.0001 0.01 0.001 t plh t phl s-1009n11 0.00001 response time [ms] 0.001 output pin capacitance [ f] 10 1 0.01 0.1 0.1 0.0001 0.01 0.001 t plh t phl s-1009c12 0.00001 response time [ms] 0.001 output pin capacitance [ f] 1 0.01 0.1 0.1 0.0001 0.01 0.001 t plh t phl s-1009n12 0.00001 response time [ms] 0.001 output pin capacitance [ f] 10 1 0.01 0.1 0.1 0.0001 0.01 0.001 t plh t phl s-1009c46 0.00001 response time [ms] 0.001 output pin capacitance [ f] 1 0.01 0.1 0.1 0.0001 0.01 0.001 t plh t phl s-1009n46 0.00001 response time [ms] 0.001 output pin capacitance [ f] 10 1 0.01 0.1 0.1 0.0001 0.01 0.001 t plh t phl
super-low current consumption super high-accuracy voltage de tector with delay circuit (external delay time setting) s-1009 series rev.4.2 _00 seiko instruments inc. 24 v ih *1 output voltage input voltage v il * 2 v dd t phl t plh 1 s 1 s v dd 10% v dd 90% *1. v ih = 10 v *2. v il = 0.7 v out vss vdd s-1009 series v r *1 100 k c out v dd v cd *1. r is unnecessary for cmos output products. figure 23 measurement ci rcuit for response time figure 22 measurement condi tion for response time caution the above connection diagram and constant will not guarantee successful operation. perform thorough evaluation using the actual application to set the constant. 11. delay time ? cd pin capacitance (c d ) (no output pin capacitance) s-1009n08 ta = + 25c 0.1 t d [ms] 0.1 1 c d [nf] 10000 10 1000 100 1000 1 100 10 s-1009n11 ta = + 25c 0.1 t d [ms] 0.1 1 c d [nf] 10000 10 1000 100 1000 1 100 10 s-1009n12 ta = + 25c 0.1 t d [ms] c d [nf] 1000 1 100 10 0.1 1 10000 10 1000 100 s-1009n46 ta = + 25c 0.1 t d [ms] c d [nf] 1000 1 100 10 0.1 1 10000 10 1000 100
super-low current consumption super high-accuracy voltage de tector with delay circuit (external delay time setting) rev.4.2 _00 s-1009 series seiko instruments inc. 25 12. delay time ? temperature (ta) s-1009n08 c d = 4.7 nf 50 0 ta [c] 40 30 20 10 t d [ms] ? 40 85 ? 25 250 75 50 s-1009n11 c d = 4.7 nf 50 0 ta [c] 40 30 20 10 t d [ms] ? 40 85 ? 25 250 75 50 s-1009n12 c d = 4.7 nf ? 40 t d [ms] 0 ta [c] 50 20 10 30 40 85 ? 25 250 75 50 s-1009n46 c d = 4.7 nf ? 40 t d [ms] 0 ta [c] 50 20 10 30 40 85 ? 25 250 75 50 1 s t d v dd 90% input voltage output voltage v il *2 v ss v ih *1 *1. v ih = 10 v *2. v il = 0.7 v out vss vdd s-1009 series v r *1 100 k v dd v cd *1. r is unnecessary for cmos output products. figure 25 measurement circuit for delay time figure 24 measurement condition for delay time caution the above connection diagram and constant will not guarantee successful operation. perform thorough evaluation using the actual application to set the constant.
super-low current consumption super high-accuracy voltage de tector with delay circuit (external delay time setting) s-1009 series rev.4.2 _00 seiko instruments inc. 26 ? application circuit examples 1. microcomputer reset circuits in microcomputers, when the power supply voltage is lower than the guaranteed operating voltage, an unspecified operation may be performed or the contents of the memory register may be lost. when power supply voltage returns to the normal level, the microcomputer needs to be initialized. otherwise, the s-1009 series may malfunction after that. reset circuits to protect microcomputer in the event of current being momentarily switched off or lowered. using the s-1009 series which has the low operating voltage, a high accuracy detection voltage and hysteresis, reset circuits can be easily constructed as seen in figure 26 and 27 . vss vdd microcomputer s-1009c vss (only for nch open drain output products) vdd1 vdd2 microcomputer s-1009n figure 26 example of reset circuit (s-1009c) figure 27 example of reset circuit (s-1009n) caution the above connection diagram and constant will not guarantee successful operation. perform thorough evaluation using the actual application to set the constant.
super-low current consumption super high-accuracy voltage de tector with delay circuit (external delay time setting) rev.4.2 _00 s-1009 series seiko instruments inc. 27 2. power-on reset circuit a power-on reset circuit can be constructed using the s-1009 series (nch open drain output products only). (nch open drain output product) out vin vss vdd s-1009n r a *1 c di *2 (r a 100 k ) r 100 k *1. r should be 100 k or less to prevent oscillation. *2. diode di instantaneously discharges the charge stored in the capacitor (c) at the power falling, di can be removed when the delay of the falling time is not important. figure 28 v dd [v] t [s] out [v] t [s] figure 29 remark when the power rises sharply, the output may instant aneously be set to the ?h? level due to the ic?s indefinite area (the output voltage is indefinite when it is the ic?s minimum operating voltage or less), as seen in figure 30. v dd [v] t [s] out [v] t [s] figure 30 caution 1. the above connection diagram and constant will not guarantee successful operation. perform thorough evaluation using the actual application to set the constant. 2. note that the hysteresis width may be larger as the following equation shows when using the above connection. perform thorough evaluation using the actual application to set the constant. maximum hysteresis width = v hys + r a ? 20 a
super-low current consumption super high-accuracy voltage de tector with delay circuit (external delay time setting) s-1009 series rev.4.2 _00 seiko instruments inc. 28 3. change of detection voltage in the nch open drain output products of s-1009 series, users do not need a specific value of detection voltage, the detection voltage can be changed by using a resistance divider or a diode, as seen in figure 31 and 32 . in figure 31 , hysteresis width also changes. (nch open drain ouput product) r a *1 out vin vss vdd s-1009n r b (r a 100 k ) r 100 k detection voltage = r a + r b r b ? ? v det hysteresis width = r a + r b r b ? v hys (nch open drain output product) v f1 out vin vss vdd s-1009n r 100 k detection voltage = v f1 + ( ? v det ) *1. r a should be 100 k or less to prevent oscillation. caution if r a and r b are large, the hysteresis width may also be larger than the value given by the above equation due to the through-type current (which flows slightly in an nch open drain product). figure 32 figure 31 caution 1. the above connection diagram and constant will not guarantee successful operation. perform thorough evaluation using the actual application to set the constant. 2. note that the hysteresis width may be larger as the following equation shows when using the above connections. perform thorough evaluation using the actual application to set the constant. maximum hysteresis width = r a + r b r b ? v hys + r a ? 20 a
super-low current consumption super high-accuracy voltage de tector with delay circuit (external delay time setting) rev.4.2 _00 s-1009 series seiko instruments inc. 29 marking specifications 1. sc-82ab (1) to (3) : product code (refer to product name vs. product code ) 4 3 1 2 sc-82ab top view (1) (2) (3) product name vs. product code 1. 1 nch open drain output products 1. 2 cmos output products product code product code product name (1) (2) (3) product name (1) (2) (3) s-1009n08i-n4t1u t 8 a s-1009c08i-n4t1u t 6 a s-1009n09i-n4t1u t 8 b s-1009c09i-n4t1u t 6 b s-1009n10i-n4t1u t 8 c s-1009c10i-n4t1u t 6 c s-1009n11i-n4t1u t 8 d s-1009c11i-n4t1u t 6 d s-1009n12i-n4t1u t 8 e s-1009c12i-n4t1u t 6 e s-1009n13i-n4t1u t 8 f s-1009c13i-n4t1u t 6 f s-1009n14i-n4t1u t 8 g s-1009c14i-n4t1u t 6 g s-1009n15i-n4t1u t 8 h s-1009c15i-n4t1u t 6 h s-1009n16i-n4t1u t 8 i s-1009c16i-n4t1u t 6 i s-1009n17i-n4t1u t 8 j s-1009c17i-n4t1u t 6 j s-1009n18i-n4t1u t 8 k s-1009c18i-n4t1u t 6 k s-1009n19i-n4t1u t 8 l s-1009c19i-n4t1u t 6 l s-1009n20i-n4t1u t 8 m s-1009c20i-n4t1u t 6 m s-1009n21i-n4t1u t 8 n s-1009c21i-n4t1u t 6 n s-1009n22i-n4t1u t 8 o s-1009c22i-n4t1u t 6 o s-1009n23i-n4t1u t 8 p s-1009c23i-n4t1u t 6 p s-1009n24i-n4t1u t 8 q s-1009c24i-n4t1u t 6 q s-1009n25i-n4t1u t 8 r s-1009c25i-n4t1u t 6 r s-1009n26i-n4t1u t 8 s s-1009c26i-n4t1u t 6 s s-1009n27i-n4t1u t 8 t s-1009c27i-n4t1u t 6 t s-1009n28i-n4t1u t 8 u s-1009c28i-n4t1u t 6 u s-1009n29i-n4t1u t 8 v s-1009c29i-n4t1u t 6 v s-1009n30i-n4t1u t 8 w s-1009c30i-n4t1u t 6 w s-1009n31i-n4t1u t 8 x s-1009c31i-n4t1u t 6 x s-1009n32i-n4t1u t 8 y s-1009c32i-n4t1u t 6 y s-1009n33i-n4t1u t 8 z s-1009c33i-n4t1u t 6 z s-1009n34i-n4t1u t 9 a s-1009c34i-n4t1u t 7 a s-1009n35i-n4t1u t 9 b s-1009c35i-n4t1u t 7 b s-1009n36i-n4t1u t 9 c s-1009c36i-n4t1u t 7 c s-1009n37i-n4t1u t 9 d s-1009c37i-n4t1u t 7 d s-1009n38i-n4t1u t 9 e s-1009c38i-n4t1u t 7 e s-1009n39i-n4t1u t 9 f s-1009c39i-n4t1u t 7 f s-1009n40i-n4t1u t 9 g s-1009c40i-n4t1u t 7 g s-1009n41i-n4t1u t 9 h s-1009c41i-n4t1u t 7 h s-1009n42i-n4t1u t 9 i s-1009c42i-n4t1u t 7 i s-1009n43i-n4t1u t 9 j s-1009c43i-n4t1u t 7 j s-1009n44i-n4t1u t 9 k s-1009c44i-n4t1u t 7 k s-1009n45i-n4t1u t 9 l s-1009c45i-n4t1u t 7 l s-1009n46i-n4t1u t 9 m s-1009c46i-n4t1u t 7 m remark please contact our sales office for produc ts with specifications other than the above.
super-low current consumption super high-accuracy voltage de tector with delay circuit (external delay time setting) s-1009 series rev.4.2 _00 seiko instruments inc. 30 2. sot-23-5 (1) to (3) : product code (refer to product name vs. product code ) (4) : lot number 5 4 1 3 2 (1) (2) (3) (4) sot-23-5 to p vie w product name vs. product code 2. 1 nch open drain output products 2. 2 cmos output products product code product code product name (1) (2) (3) product name (1) (2) (3) s-1009n08i-m5t1u t 8 a s-1009c08i-m5t1u t 6 a s-1009n09i-m5t1u t 8 b s-1009c09i-m5t1u t 6 b s-1009n10i-m5t1u t 8 c s-1009c10i-m5t1u t 6 c S-1009N11I-M5T1U t 8 d s-1009c11i-m5t1u t 6 d s-1009n12i-m5t1u t 8 e s-1009c12i-m5t1u t 6 e s-1009n13i-m5t1u t 8 f s-1009c13i-m5t1u t 6 f s-1009n14i-m5t1u t 8 g s-1009c14i-m5t1u t 6 g s-1009n15i-m5t1u t 8 h s-1009c15i-m5t1u t 6 h s-1009n16i-m5t1u t 8 i s-1009c16i-m5t1u t 6 i s-1009n17i-m5t1u t 8 j s-1009c17i-m5t1u t 6 j s-1009n18i-m5t1u t 8 k s-1009c18i-m5t1u t 6 k s-1009n19i-m5t1u t 8 l s-1009c19i-m5t1u t 6 l s-1009n20i-m5t1u t 8 m s-1009c20i-m5t1u t 6 m s-1009n21i-m5t1u t 8 n s-1009c21i-m5t1u t 6 n s-1009n22i-m5t1u t 8 o s-1009c22i-m5t1u t 6 o s-1009n23i-m5t1u t 8 p s-1009c23i-m5t1u t 6 p s-1009n24i-m5t1u t 8 q s-1009c24i-m5t1u t 6 q s-1009n25i-m5t1u t 8 r s-1009c25i-m5t1u t 6 r s-1009n26i-m5t1u t 8 s s-1009c26i-m5t1u t 6 s s-1009n27i-m5t1u t 8 t s-1009c27i-m5t1u t 6 t s-1009n28i-m5t1u t 8 u s-1009c28i-m5t1u t 6 u s-1009n29i-m5t1u t 8 v s-1009c29i-m5t1u t 6 v s-1009n30i-m5t1u t 8 w s-1009c30i-m5t1u t 6 w s-1009n31i-m5t1u t 8 x s-1009c31i-m5t1u t 6 x s-1009n32i-m5t1u t 8 y s-1009c32i-m5t1u t 6 y s-1009n33i-m5t1u t 8 z s-1009c33i-m5t1u t 6 z s-1009n34i-m5t1u t 9 a s-1009c34i-m5t1u t 7 a s-1009n35i-m5t1u t 9 b s-1009c35i-m5t1u t 7 b s-1009n36i-m5t1u t 9 c s-1009c36i-m5t1u t 7 c s-1009n37i-m5t1u t 9 d s-1009c37i-m5t1u t 7 d s-1009n38i-m5t1u t 9 e s-1009c38i-m5t1u t 7 e s-1009n39i-m5t1u t 9 f s-1009c39i-m5t1u t 7 f s-1009n40i-m5t1u t 9 g s-1009c40i-m5t1u t 7 g s-1009n41i-m5t1u t 9 h s-1009c41i-m5t1u t 7 h s-1009n42i-m5t1u t 9 i s-1009c42i-m5t1u t 7 i s-1009n43i-m5t1u t 9 j s-1009c43i-m5t1u t 7 j s-1009n44i-m5t1u t 9 k s-1009c44i-m5t1u t 7 k s-1009n45i-m5t1u t 9 l s-1009c45i-m5t1u t 7 l s-1009n46i-m5t1u t 9 m s-1009c46i-m5t1u t 7 m remark please contact our sales office for produc ts with specifications other than the above.

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www.sii-ic.com ? the information described herein is subject to change without notice. ? seiko instruments inc. is not responsible for any pr oblems caused by circuits or diagrams described herein whose related industrial properties, patents, or ot her rights belong to third parties. the application circuit examples explain typical applications of the products, and do not guarant ee the success of any specific mass-production design. ? when the products described herein are regulated produ cts subject to the wassenaar arrangement or other agreements, they may not be exported without authoriz ation from the appropriate governmental authority. ? use of the information described he rein for other purposes and/or repr oduction or copying without the express permission of seiko instrum ents inc. is strictly prohibited. ? the products described herein cannot be used as par t of any device or equipment affecting the human body, such as exercise equipment, medical equipment, security systems, gas equipment, or any apparatus installed in airplanes and other vehicles, without prior written permission of seiko instruments inc. ? although seiko instruments inc. exerts the greatest possible effort to ensure high quality and reliability, the failure or malfunction of semiconductor products may oc cur. the user of these products should therefore give thorough consideration to safety design, including redundancy, fire-prevention measures, and malfunction prevention, to prevent any accidents, fires, or community damage that may ensue.

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