protection products 1 www.semtech.com preliminary protection products sfc05-4 chipclamp ? ? ? ? ? flip chip tvs diode array description features device dimensions schematic & pin configuration revision 8/11/04 the sfc05-4 is a quad flip chip tvs array. they are state-of-the-art devices that utilize solid-state silicon- avalanche technology for superior clamping perfor- mance and dc electrical characteristics. the sfc series tvs diodes are designed to protect sensitive semiconductor components from damage or latch-up due to electrostatic discharge (esd) and other voltage induced transient events. the sfc05-4 is a 6-bump, 0.5mm pitch flip chip array with a 3x2 bump grid. it measures 1.5 x 1.0 x 0.65mm. this small outline makes the sfc05-4 especially well suited for portable applications. flip chip tvs devices are compatible with current pick and place equipment and assembly methods. each device will protect up to four data or i/o lines. the flip chip design results in lower inductance, virtu- ally eliminating voltage overshoot due to leads and interconnecting bond wires. they may be used to meet the esd immunity requirements of iec 61000-4-2, level 4 (15kv air, 8kv contact discharge). applications mechanical characteristics ? cell phone handsets and accessories ? personal digital assistants (pda?s) ? notebook and hand held computers ? portable instrumentation ? smart cards ? mp3 players ? gps ? 300 watts peak pulse power (t p = 8/20s) ? transient protection for data lines to iec 61000-4-2 (esd) 15kv (air), 8kv (contact) iec 61000-4-4 (eft) 40a (5/50ns) iec 61000-4-5 (lightning) 24a (8/20s) ? small chip scale package requires less board space ? low profile (< 0.65mm) ? no need for underfill material ? protects four i/o or data lines ? low clamping voltage ? working voltage: 5v ? solid-state silicon-avalanche technology ? jedec mo-211, 0.50 mm pitch flip chip package ? non-conductive top side coating ? marking : marking code ? packaging : tape and reel sfc05-4 maximum dimensions (mm) 3 x 2 grid csp tvs (bottom view)
2 ? 2004 semtech corp. www.semtech.com preliminary protection products sfc05-4 absolute maximum rating electrical characteristics r e t e m a r a pl o b m y ss n o i t i d n o cm u m i n i ml a c i p y tm u m i x a ms t i n u e g a t l o v f f o - d n a t s e s r e v e rv m w r 5v e g a t l o v n w o d k a e r b e s r e v e rv r b i t a m 1 =6 v t n e r r u c e g a k a e l e s r e v e ri r v m w r c 5 2 = t , v 5 =0 1a e g a t l o v g n i p m a l cv c i p p t , a 5 = p s 0 2 / 8 = d n u o r g o t o / i y n a 5 . 9v e g a t l o v g n i p m a l cv c i p p t , a 4 2 = p s 0 2 / 8 = d n u o r g o t o / i y n a 1 1v e c n a t i c a p a c n o i t c n u jc j v r z h m 1 = f , v 0 =0 5 3f p g n i t a rl o b m y se u l a vs t i n u ) s 0 2 / 8 = p t ( r e w o p e s l u p k a e pp k p 0 0 3s t t a w ) s 0 2 / 8 = p t ( t n e r r u c e s l u p k a e pi p p 4 2a ) r i a ( 2 - 4 - 0 0 0 1 6 c e i r e p d s e ) t c a t n o c ( 2 - 4 - 0 0 0 1 6 c e i r e p d s e v d s e 5 2 > 5 1 > v k e r u t a r e p m e t g n i t a r e p ot j 5 2 1 + o t 5 5 -c e r u t a r e p m e t e g a r o t st g t s 0 5 1 + o t 5 5 -c
3 ? 2004 semtech corp. www.semtech.com preliminary protection products sfc05-4 typical characteristics non-repetitive peak pulse power vs. pulse time power derating curve 0 10 20 30 40 50 60 70 80 90 100 110 0 25 50 75 100 125 150 ambient temperature - t a ( o c) % of rated power or i pp clamping voltage vs. peak pulse current 0 10 20 30 40 50 60 70 80 90 100 110 0 5 10 15 20 25 30 time (s) percent of i pp e -t td = i pp /2 waveform parameters: tr = 8s td = 20s pulse waveform 0.01 0.1 1 10 0.1 1 10 100 1000 pulse duration - t p (s) peak pulse power - p pk (kw) 0.00 1.00 2.00 3.00 4.00 5.00 6.00 7.00 8.00 9.00 10.00 0 5 10 15 20 25 30 peak pulse current - i pp (a) clamping voltage - v c (v) waveform parameters: tr = 8s td = 20s forward voltage vs. forward current capacitance vs. reverse voltage 0 1 2 3 4 0 1020304050 forward current - i f (a) forward voltage -v f (v) waveform parameters: tr = 8s td = 20s 0 50 100 150 200 250 300 012345 reverse voltage - v r (v) capacitance - c j (pf) f = 1mhz
4 ? 2004 semtech corp. www.semtech.com preliminary protection products sfc05-4 typical characteristics (continued) esd clamping (8kv contact discharge)
5 ? 2004 semtech corp. www.semtech.com preliminary protection products sfc05-4 device connection options the sfc05-4 has solder bumps located in a 3 x 2 matrix layout on the active side of the device. the bumps are designated by the numbers 1 - 3 along the horizontal axis and letters a - b along the vertical axis. the lines to be protected are connected at bumps a1, b1, a3, and b3. bumps a2 and b2 are connected to ground. all path lengths should be kept as short as possible to minimize the effects of parasitic inductance in the board traces. flip chip tvs flip chip tvs devices are wafer level chip scale pack- ages. they eliminate external plastic packages and leads and thus result in a significant board space savings. manufacturing costs are minimized since they do not require an intermediate level interconnect or interposer layer for reliable operation. their compatibil- ity with current pick and place equipment further reduces manufacturing costs. certain precautions and design considerations have to be observed, however, for maximum solder joint reliability. these include solder pad definition, board finish, and assembly parameters. printed circuit board mounting non-solder mask defined (nsmd) land patterns are recommended for mounting the sfc05-4. solder mask defined (smd) pads produce stress points near the solder mask on the pcb side that can result in solder joint cracking when exposed to extreme fatigue conditions. the recommended pad size is 0.225 0.010 mm with a solder mask opening of 0.350 0.025 mm. grid courtyard the recommended grid placement courtyard is 1.3 x 1.8 mm. the grid courtyard is intended to encompass the land pattern and the component body that is centered in the land pattern. when placing parts on a pcb, the highest recommended density is when one courtyard touches another. applications information device schematic and pin configuration layout example nsmd package footprint to protected ic to protected ic to connector ground
6 ? 2004 semtech corp. www.semtech.com preliminary protection products sfc05-4 printed circuit board finish a uniform board finish is critical for good assembly yield. two finishes that provide uniform surface coat- ings are immersion nickel gold and organic surface protectant (osp). a non-uniform finish such as hot air solder leveling (hasl) can lead to mounting problems and should be avoided. stencil design a properly designed stencil is key to achieving ad- equate solder volume without compromising assembly yields. a 0.100mm thick, laser cut, electro-polished stencil with 0.275mm square apertures and rounded corners is recommended. reflow profile the flip chip tvs can be assembled using the reflow requirements for ipc/jedec standard j-std-020 for assembly of small body components. during reflow, the component will self-align itself on the pad. circuit board layout recommendations for suppres- sion of esd good circuit board layout is critical for the suppression of esd induced transients. the following guidelines are recommended: z place the tvs near the input terminals or connec- tors to restrict transient coupling. z minimize the path length between the tvs and the protected line. z minimize all conductive loops including power and ground loops. z the esd transient return path to ground should be kept as short as possible. z never run critical signals near board edges. z use ground planes whenever possible. applications information (continued) stencil design assembly guideline for pb-free soldering the following are recommendations for the assembly of this device: r e t e m a r a p y l b m e s s an o i t a d n e m m o c e r n o i t i s o p m o c l l a b r e d l o su c 7 . 0 / g a 8 . 3 / n s 5 . 5 9 n g i s e d l i c n e t s r e d l o sn g i s e d b p n s e h t s a e m a s s s e n k c i h t l i c n e t s r e d l o s) " 4 0 0 . 0 ( m m 0 0 1 . 0 n o i t i s o p m o c e t s a p r e d l o s) 9 . 0 - 5 . 0 ( u c ) 4 - 3 ( g a n s e p y t e t s a p r e d l o sr e l l a m s r o e r e h p s e z i s 4 e p y t e l i f o r p w o l f e r r e d l o s0 2 0 - d t s - j c e d e j r e p n g i s e d d a p r e d l o s b c pn g i s e d b p n s e h t s a e m a s h s i n i f d a p b c pi n u a r o p s o
7 ? 2004 semtech corp. www.semtech.com preliminary protection products sfc05-4 land pattern outline drawing 0.1500.025 0.10 c 0.05 c 12 3 a a b 6x ?0.175-0.225 0.005 c a b controlling dimensions are in millimeters notes: 1. 3. sn63/pb37 eutectic bump. 1.470.03 0.970.03 a b c 0.40-0.60 0.50-0.75 3. 0.50 0.50 2. reference jedec registration mo-211. index area a1 corner
8 ? 2004 semtech corp. www.semtech.com preliminary protection products sfc05-4 marking codes r e b m u n t r a p g n i k r a m e d o c 4 - 5 0 c f su 5 4 f r e b m u n t r a p h c t i p n o i t p o r e p y t q l e e r e z i s l e e r f w . 4 - 5 0 c f sm m 40 0 0 , 3h c n i 7 t f w . 4 - 5 0 c f s ) 1 ( m m 40 0 0 , 3h c n i 7 m w . 4 - 5 0 c f sm m 20 0 0 , 6h c n i 7 t m w . 4 - 5 0 c f s ) 1 ( m m 20 0 0 , 6h c n i 7 ordering information tape specifications device orientation pin a1 pin a1 pin a1 contact information semtech corporation protection products division 200 flynn rd., camarillo, ca 93012 phone: (805)498-2111 fax (805)498-3804 marking codes notes (1) lead free solder balls tape and reel specification t t t t t op coating: op coating: op coating: op coating: op coating: the top (non-bump side) of the device is a white non-conductive coating. the coating is laser markable and increases mechanical durability. this material is compliant with ul 94v-0 flammability requirements. chipclamp is a mark of semtech corporation
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