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| document no. u17854ej6v0ud00 (6th edition) date published august 2007 ns printed in japan 2006 pd78f1142 pd78f1143 pd78f1144 pd78f1145 pd78f1146 78k0r/ke3 16-bit single-chip microcontrollers user?s manual the 78k0r/ke3 has an on-chip debug function. do not use this product for mass production because its reliab ility cannot be guaranteed after the on-chip debug function has been used, due to issues with respect to the number of times the flash memory can be rewritten. nec electronics does not accept complaints concerning this product after the on-chip debug function has been used.
user?s manual u17854ej6v0ud 2 [memo] user?s manual u17854ej6v0ud 3 1 2 3 4 voltage application waveform at input pin waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between v il (max) and v ih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between v il (max) and v ih (min). handling of unused input pins unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. precaution against esd a strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. status before initialization power-on does not necessarily define the initial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the reset signal is received. a reset operation must be executed immediately after power-on for devices with reset functions. power on/off sequence in the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. when switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. the correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. input of signal during power off state do not input signals or an i/o pull-up power supply while the device is not powered. the current injection that results from input of such a signal or i/o pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. notes for cmos devices 5 6 user?s manual u17854ej6v0ud 4 windows and windows nt are registered trademarks or trademarks of microsoft co rporation in the united states and/or other countries. pc/at is a trademark of internati onal business machines corporation. eeprom is a trademark of nec electronics corporation. superflash is a registered trademark of silicon storage t echnology, inc. in several countries including the united states and japan. caution: this product uses superflash ? technology licensed from silicon storage technology, inc. the information in this document is current as of august, 2007. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) ? ? ? ? ? ? m8e 02. 11-1 (1) (2) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. "standard": "special": "specific": user?s manual u17854ej6v0ud 5 introduction readers this manual is intended for user engineer s who wish to understand the functions of the 78k0r/ke3 and design and develop applic ation systems and programs for these devices. the target products are as follows. 78k0r/ke3: pd78f1142, 78f1143, 78f 1144, 78f1145, 78f1146 purpose this manual is intended to give users an understanding of the functions described in the organization below. organization the 78k0r/ke3 manual is separated into two parts: this manual and the instructions edition (common to the 78k0r microcontroller series). 78k0r/ke3 user?s manual (this manual) 78k0r microcontroller user?s manual instructions ? pin functions ? internal block functions ? interrupts ? other on-chip peripheral functions ? electrical specifications ? cpu functions ? instruction set ? explanation of each instruction how to read this manual it is assumed that the readers of this ma nual have general knowledge of electrical engineering, logic circuits, and microcontrollers. ? to gain a general understanding of functions: read this manual in the order of the contents . the mark ? user?s manual u17854ej6v0ud 6 conventions data significance: higher digits on the left and lower digits on the right active low representations: (overscore over pin and signal name) note : footnote for item marked with note in the text caution : information requiring particular attention remark : supplementary information numerical representations: binary ... or b decimal ... hexadecimal ... h related documents the related documents indicated in this pu blication may include preliminary versions. however, preliminary versions are not marked as such. documents related to devices document name document no. 78k0r/ke3 user?s manual this manual 78k0r microcontroller instructions user?s manual u17792e 78k0r microcontroller self progr amming library type01 user?s manual note u18706e note this document is under engineering mana gement. for details, consult an nec electronics sales representative . documents related to development tools (software) (user?s manuals) document name document no. operation u17838e cc78k0r ver. 1.00 c compiler language u17837e operation u17836e ra78k0r ver. 1.00 assembler package language u17835e sm+ system simulator operation u18010e pm+ ver. 6.20 u17990e id78k0r-qb ver. 3.20 integrated debugger operation u17839e documents related to development tools (hardware) (user?s manuals) document name document no. qb-mini2 on-chip debug emulator with programming function u18371e qb-78k0rkx3 in-circuit emulator u17866e documents related to fl ash memory programming document name document no. pg-fp4 flash memory programmer user?s manual u15260e caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document when designing. user?s manual u17854ej6v0ud 7 other documents document name document no. semiconductor selection guide ? products and packages ? x13769x semiconductor device mount manual note quality grades on nec semiconductor devices c11531e nec semiconductor device reliability/quality control system c10983e guide to prevent damage for semiconductor devi ces by electrostatic discharge (esd) c11892e note see the ?semiconductor device m ount manual? website (h ttp://www.necel.com/pkg/en/mount/index.html). caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document when designing. user?s manual u17854ej6v0ud 8 contents chapter 1 outline ........................................................................................................... ................. 16 1.1 features.................................................................................................................. ....................... 16 1.2 applications .............................................................................................................. .................... 17 1.3 ordering information...................................................................................................... .............. 17 1.4 pin configuration (top view) .............................................................................................. ........ 18 1.5 78k0r microcontroller lineup .............................................................................................. ...... 21 1.6 block diagram ............................................................................................................. ................. 22 1.7 outline of functions...................................................................................................... ............... 23 chapter 2 pin functions .................................................................................................... ........... 25 2.1 pin function list ......................................................................................................... ................. 25 2.2 description of pin functions .............................................................................................. ........ 30 2.2.1 p00 to p06 (por t 0) ..................................................................................................... ...................... 30 2.2.2 p10 to p17 (por t 1) ..................................................................................................... ...................... 31 2.2.3 p20 to p27 (por t 2) ..................................................................................................... ...................... 32 2.2.4 p30, p31 (por t 3)....................................................................................................... ....................... 32 2.2.5 p40 to p43 (por t 4) ..................................................................................................... ...................... 33 2.2.6 p50 to p55 (por t 5) ..................................................................................................... ...................... 34 2.2.7 p60 to p63 (por t 6) ..................................................................................................... ...................... 34 2.2.8 p70 to p77 (por t 7) ..................................................................................................... ...................... 34 2.2.9 p120 to p124 (por t 12) .................................................................................................. ................... 35 2.2.10 p130 (por t 13) ......................................................................................................... ....................... 36 2.2.11 p140, p141 (por t 14) ................................................................................................... ................... 36 2.2.12 av ref ............................................................................................................................... ............... 36 2.2.13 av ss ............................................................................................................................... ................ 36 2.2.14 reset .................................................................................................................. ......................... 36 2.2.15 regc................................................................................................................... .......................... 37 2.2.16 v dd , ev dd ............................................................................................................................... ........ 37 2.2.17 v ss , ev ss ............................................................................................................................... ......... 37 2.2.18 flmd0 .................................................................................................................. ......................... 37 2.3 pin i/o circuits and recomme nded connection of unused pins .... ....................................... 38 chapter 3 cpu architecture ................................................................................................. ..... 42 3.1 memory space .............................................................................................................. ................ 42 3.1.1 internal progr am memory space ........................................................................................... ........... 49 3.1.2 mi rror ar ea............................................................................................................. ........................... 51 3.1.3 internal dat a memory space.............................................................................................. ............... 52 3.1.4 special function register (sfr) area .................................................................................... ............ 53 3.1.5 extended special function register (2nd sfr: 2nd special func tion registe r) area ....................... 53 3.1.6 data me mory addr essing .................................................................................................. ............... 54 3.2 processor registers....................................................................................................... .............. 59 3.2.1 contro l regist ers ....................................................................................................... ........................ 59 3.2.2 general-pur pose registers............................................................................................... ................. 61 user?s manual u17854ej6v0ud 9 3.2.3 es and cs regist ers ..................................................................................................... ....................63 3.2.4 special functi on register s (sfrs)....................................................................................... ...............64 3.2.5 extended specia l function registers (2nd sfrs: 2nd special function register s)............................70 3.3 instruction address addressing . ........................................................................................... .... 75 3.3.1 relati ve addre ssing ..................................................................................................... .....................75 3.3.2 immedi ate addres sing.................................................................................................... ...................75 3.3.3 table indi rect addr essing ............................................................................................... ...................76 3.3.4 register di rect addr essing .............................................................................................. ..................77 3.4 addressing for processing data a ddresses............................................................................. 78 3.4.1 impli ed addre ssing...................................................................................................... ......................78 3.4.2 regist er addre ssing ..................................................................................................... .....................78 3.4.3 direct addre ssing ....................................................................................................... .......................79 3.4.4 short di rect addr essing ................................................................................................. ....................80 3.4.5 sfr addressi ng .......................................................................................................... ......................81 3.4.6 register i ndirect addr essi ng............................................................................................ ..................82 3.4.7 based addre ssing ........................................................................................................ .....................83 3.4.8 based in dexed addr essing................................................................................................ ................86 3.4.9 stack addre ssing ........................................................................................................ ......................87 chapter 4 port functions ................................................................................................... ........ 88 4.1 port functions ............................................................................................................ .................. 88 4.2 port configuration ........................................................................................................ ............... 91 4.2.1 po rt 0 .................................................................................................................. ..............................92 4.2.2 po rt 1 .................................................................................................................. ..............................98 4.2.3 po rt 2 .................................................................................................................. ............................104 4.2.4 po rt 3 .................................................................................................................. ............................106 4.2.5 po rt 4 .................................................................................................................. ............................107 4.2.6 po rt 5 .................................................................................................................. ............................112 4.2.7 po rt 6 .................................................................................................................. ............................114 4.2.8 po rt 7 .................................................................................................................. ............................116 4.2.9 po rt 12 ................................................................................................................. ...........................117 4.2.10 po rt 13 ................................................................................................................ ..........................120 4.2.11 po rt 14 ................................................................................................................ ..........................121 4.3 registers controlling port functi on ....................................................................................... . 123 4.4 port function operations.................................................................................................. ........ 130 4.4.1 writi ng to i/o port..................................................................................................... .......................130 4.4.2 reading from i/o port ................................................................................................... ..................130 4.4.3 operatio ns on i/o port .................................................................................................. ..................130 4.4.4 connecting to external device with different power potent ial (2.5v, 3 v) ........................................131 4.5 settings of port mode register and output latch when using alternate function........... 133 4.6 cautions on 1-bit manipulation in struction for port register n (pn) .................................... 135 chapter 5 clock generator .................................................................................................. .. 136 5.1 functions of clock generator.................................... .......................................................... ..... 136 5.2 configuration of clock genera tor .......................................................................................... .. 137 5.3 registers controlling clock generator ..................... .............................................................. 13 9 5.4 system clock oscillator ................................................................................................... ......... 153 5.4.1 x1 oscill ator ........................................................................................................... .........................153 user?s manual u17854ej6v0ud 10 5.4.2 xt1 oscilla tor .......................................................................................................... ........................153 5.4.3 internal hi gh-speed os cillator .......................................................................................... ................156 5.4.4 internal lo w-speed os cillator........................................................................................... .................156 5.4.5 pr escaler ............................................................................................................... ..........................156 5.5 clock generator operation ................................................................................................. ...... 157 5.6 controlling clock......................................................................................................... ............... 161 5.6.1 example of controlli ng high-speed syst em clock.......................................................................... ...161 5.6.2 example of controlling intern al high-speed osc illation clock............................................................ 164 5.6.3 example of cont rolling subsyst em clock.................................................................................. ........166 5.6.4 example of controlling intern al low-speed osci llation clock ............................................................. 168 5.6.5 cpu clock stat us transiti on diagr am..................................................................................... ...........169 5.6.6 condition before changing cpu clock and processi ng after changing cpu cl ock ..........................174 5.6.7 time required for switchover of cpu clock and main system cl ock ................................................175 5.6.8 conditions before clock osc illation is stopp ed .......................................................................... .......176 chapter 6 timer array unit................................................................................................ ...... 177 6.1 functions of timer array unit............................................................................................. ...... 177 6.1.1 functions of eac h channel when it oper ates indepe ndently ............................................................177 6.1.2 functions of each channel when it operates with another channe l .................................................178 6.1.3 lin-bus supporting function (cha nnel 7 only) ............................................................................ ......178 6.2 configuration of timer array unit ........................... .............................................................. ... 179 6.3 registers controlling timer array unit...................... .............................................................. 184 6.4 channel output (to0n pin) co ntrol......................................................................................... . 205 6.4.1 to0n pin output ci rcuit config uration................................................................................... ............205 6.4.2 to0n pin output setting ................................................................................................. ................206 6.4.3 cautions on cha nnel output operation .................................................................................... ......206 6.4.4 collective mani pulation of to0n bits .................................................................................... ...........210 6.4.5 timer interrupt and to0n pi n output at o peration start.................................................................2 11 6.5 channel input (ti0n pin) control ..................... ..................................................................... .... 212 6.5.1 ti0n edge det ection circuit ............................................................................................. .................212 6.6 basic function of timer array unit ......................... ............................................................... .. 213 6.6.1 overview of single-operation func tion and combination-op eration fu nction.....................................213 6.6.2 basic rules of comb ination-operat ion func tion........................................................................... ......213 6.6.3 applicable range of basic rules of combi nation-operation functi on..................................................214 6.7 operation of timer array unit as independent ch annel ........................................................ 215 6.7.1 operation as interv al timer/squar e wave output .......................................................................... ....215 6.7.2 operation as ex ternal event count er ..................................................................................... ..........219 6.7.3 operation as frequency divi der .......................................................................................... .............222 6.7.4 operation as input pulse interval measur ement ........................................................................... ...226 6.7.5 operation as in put signal high-/low-le vel width me asurem ent......................................................... 230 6.8 operation of plural channels of timer array unit .................................................................. 234 6.8.1 operation as pwm f unction ............................................................................................... .............234 6.8.2 operation as one-s hot pulse output function............................................................................. ......241 6.8.3 operation as mult iple pwm output func tion ............................................................................... .....248 chapter 7 real-time counter................................................................................................ ... 255 7.1 functions of real-time coun ter............................................................................................ ... 255 7.2 configuration of real-time counter .......................... .............................................................. 255 user?s manual u17854ej6v0ud 11 7.3 registers controlling real-time counter ............................................................................... 257 7.4 real-time counter operation .................................... ........................................................... .... 269 7.4.1 starting operation of real-tim e coun ter ................................................................................. ...........269 7.4.2 reading/writi ng real-tim e count er ....................................................................................... ............270 7.4.3 setting alarm of real-tim e count er ...................................................................................... .............272 chapter 8 watchdog timer ................................................................................................... .... 273 8.1 functions of watchdog timer .................................... ........................................................... ... 273 8.2 configuration of watchdog timer . .......................................................................................... . 274 8.3 register controlling wa tchdog timer ..................................................................................... 27 5 8.4 operation of watchdog timer.................................... ........................................................... .... 276 8.4.1 controlling operat ion of watc hdog timer................................................................................. .........276 8.4.2 setting overflow ti me of watc hdog ti mer ................................................................................. ........277 8.4.3 setting window open pe riod of watc hdog ti mer............................................................................ ...278 8.4.4 setting watchdog ti mer interval interrupt ............................................................................... ..........279 chapter 9 clock output/buzzer output controller................................................. 280 9.1 functions of clock output/buzze r output controller ..................... ....................................... 280 9.2 configuration of clock output /buzzer output controller ..................................................... 281 9.3 registers controlling clock out put/buzzer output controller............................................. 281 9.4 operations of clock output/bu zzer output controller ................... ....................................... 283 9.4.1 operation as output pin................................................................................................. ..................283 chapter 10 a/d converter ................................................................................................... ...... 284 10.1 function of a/d converter .................................... ............................................................ ...... 284 10.2 configuration of a/d converter ........................................................................................... ... 285 10.3 registers used in a/d converter .......................................................................................... . 287 10.4 a/d converter operations ................................................................................................. ...... 296 10.4.1 basic operations of a/d c onverter...................................................................................... ...........296 10.4.2 input voltage and conversion results................................................................................... ..........298 10.4.3 a/d converte r operati on mode ........................................................................................... ...........299 10.5 how to read a/d converter characteristics table. .............................................................. 301 10.6 cautions for a/d converter............................................................................................... ...... 303 chapter 11 serial array unit .............................................................................................. ... 307 11.1 functions of serial array unit ................................. .......................................................... ..... 307 11.1.1 3-wire serial i/o (csi00, csi10)....................................................................................... .............307 11.1.2 uart (uart0 , uart1, uart3)............................................................................................. .....308 11.1.3 simplified i 2 c (iic 10) .....................................................................................................................3 08 11.2 configuration of serial array unit ........................... ............................................................ ... 309 11.3 registers controlling serial array unit ................................................................................. 3 14 11.4 operation stop mode ...................................................................................................... ......... 336 11.4.1 stoppin g the operati on by units........................................................................................ .............336 11.4.2 stoppin g the operation by chann els..................................................................................... .........337 11.5 operation of 3-wire serial i/o (csi00, csi10) communication ........................................... 339 11.5.1 master transmission .................................................................................................... ..................340 11.5.2 master recept ion ....................................................................................................... ....................349 user?s manual u17854ej6v0ud 12 11.5.3 master trans mission/rec eption .......................................................................................... ............355 11.5.4 slave transmi ssion ..................................................................................................... ...................363 11.5.5 slave reception ........................................................................................................ .....................372 11.5.6 slave trans mission/rec eption ........................................................................................... .............378 11.5.7 calculating tr ansfer clock frequency................................................................................... ...........387 11.6 operation of uart (uart0, uart1, uart3) communication ........................................... 389 11.6.1 uart transmi ssion ...................................................................................................... .................390 11.6.2 uart recept ion......................................................................................................... ....................400 11.6.3 lin transmi ssion ....................................................................................................... ....................407 11.6.4 lin reception.......................................................................................................... .......................410 11.6.5 calculat ing baud rate .................................................................................................. ..................415 11.7 operation of simplified i 2 c (iic10) communication.............................................................. 419 11.7.1 address fi eld transmi ssion ............................................................................................. ...............420 11.7.2 data transmi ssion...................................................................................................... ....................425 11.7.3 data reception......................................................................................................... ......................428 11.7.4 stop conditi on gener ation.............................................................................................. ................431 11.7.5 calculati ng transfe r rate .............................................................................................. ..................432 11.8 processing procedure in case of error ................... .............................................................. 435 11.9 relationship between register settings and pins . .............................................................. 437 chapter 12 serial interface iic0.......................................................................................... .. 442 12.1 functions of serial interfac e iic0 ....................................................................................... .... 442 12.2 configuration of serial inte rface iic0 ................................................................................... .. 445 12.3 registers to controlling serial interface iic0....... ................................................................. 448 12.4 i 2 c bus mode functions .......................................................................................................... 4 60 12.4.1 pin c onfigurat ion ...................................................................................................... .....................460 12.5 i 2 c bus definitions and control methods .............................................................................. 461 12.5.1 start conditi ons ....................................................................................................... ......................461 12.5.2 a ddresses .............................................................................................................. .......................462 12.5.3 transfer direct ion specif ication....................................................................................... ...............462 12.5.4 transfer cl ock setting method .......................................................................................... .............463 12.5.5 ackno wledge (a ck) ...................................................................................................... ................464 12.5.6 stop condition ......................................................................................................... ......................466 12.5.7 wait ................................................................................................................... ............................467 12.5.8 canc eling wait ......................................................................................................... ......................469 12.5.9 interrupt request (intiic0) ge neration timing and wait cont rol......................................................470 12.5.10 address matc h detection method ........................................................................................ ........471 12.5.11 erro r detec tion....................................................................................................... ......................471 12.5.12 exte nsion code........................................................................................................ ....................471 12.5.13 arbi tration........................................................................................................... .........................472 12.5.14 wake up func tion ....................................................................................................... ..................473 12.5.15 communicati on reserv ation............................................................................................. ............474 12.5.16 ca utions .............................................................................................................. ........................478 12.5.17 communica tion oper ations.............................................................................................. ............479 12.5.18 timing of i 2 c interrupt request (int iic0) occu rrence ...................................................................487 12.6 timing charts ............................................................................................................ ............... 508 user?s manual u17854ej6v0ud 13 chapter 13 multiplier ....................................................................................................... ........... 515 13.1 functions of multiplier.................................................................................................. ........... 515 13.2 configuration of multiplier . ............................................................................................. ........ 516 13.3 operation of multiplier .................................................................................................. ........... 517 chapter 14 dma controller.................................................................................................. ... 518 14.1 functions of dma controller .................................... .......................................................... .... 518 14.2 configuration of dma controller............................. ............................................................. .. 519 14.3 registers to controlling dma controller................ ............................................................... 522 14.4 operation of dma controller ................................... ........................................................... .... 525 14.4.1 operat ion proc edure .................................................................................................... .................525 14.4.2 trans fer m ode.......................................................................................................... .....................526 14.4.3 termination of dma tr ansfer ............................................................................................ .............526 14.5 example of setting of dma controller..................... .............................................................. 52 7 14.5.1 csi consec utive trans mission ........................................................................................... ............527 14.5.2 consecut ive capturing of a/d conversion results........................................................................ ..529 14.5.3 uart consec utive reception + ack transmi ssion ........................................................................53 1 14.5.4 holding dma trans fer pending by dwaitn................................................................................. ..533 14.5.5 forced terminat ion by so ftware......................................................................................... ............534 14.6 cautions on using dma controller ........................................................................................ 5 35 chapter 15 interrupt functions ............................................................................................ 5 37 15.1 interrupt function types........................................... ...................................................... ........ 537 15.2 interrupt sources and configuration ..................................................................................... 5 38 15.3 registers controlling interrupt functions .............. .............................................................. 541 15.4 interrupt servicing operati ons ........................................................................................... .... 551 15.4.1 maskable interr upt acknow ledgment...................................................................................... .......551 15.4.2 software interrupt request ack nowledg ment .............................................................................. ...553 15.4.3 multiple in terrupt se rvicing ........................................................................................... .................554 15.4.4 interrupt request hold ................................................................................................. ...................557 chapter 16 key interrupt function ..................................................................................... 558 16.1 functions of key interrupt ............................................................................................... ....... 558 16.2 configuration of key interrupt................................. .......................................................... ..... 558 16.3 register controlling key interrupt ........................... ............................................................ .. 559 chapter 17 standby function ................................................................................................ .. 560 17.1 standby function and conf iguration..................................................................................... 56 0 17.1.1 standby func tion ....................................................................................................... ....................560 17.1.2 registers contro lling standby function ................................................................................. .........560 17.2 standby function operation..................................... .......................................................... .... 563 17.2.1 ha lt m ode.............................................................................................................. .....................563 17.2.2 st op m ode .............................................................................................................. ....................568 user?s manual u17854ej6v0ud 14 chapter 18 reset function.................................................................................................. ...... 574 18.1 register for confirming reset source ......................... .......................................................... 58 2 chapter 19 power-on-clear circuit...................................................................................... 583 19.1 functions of power-on-clear circuit........................ .............................................................. 583 19.2 configuration of power-on-clea r circuit ............................................................................... 584 19.3 operation of power-on-clear circuit ........................ .............................................................. 584 19.4 cautions for power-on-clear circuit ........................ .............................................................. 587 chapter 20 low-voltage detector ....................................................................................... 589 20.1 functions of low-voltage detector.......................... .............................................................. 589 20.2 configuration of low-voltage detector ................................................................................. 590 20.3 registers controlling low-voltage detector............... .......................................................... 590 20.4 operation of low-voltage detector .......................... .............................................................. 595 20.4.1 when us ed as re set ..................................................................................................... .................596 20.4.2 when used as interrupt ................................................................................................. ................602 20.5 cautions for low-voltage detector .......................... .............................................................. 608 chapter 21 regulator ........................................................................................................ ......... 612 21.1 regulator overview ............................................................................................................. ... 612 21.2 registers controlling regulator............................................................................................ 612 chapter 22 option byte..................................................................................................... .......... 614 22.1 functions of option by tes ................................................................................................ ...... 614 22.1.1 user option byte (000c0h to 000c2h/010c0h to 010c 2h) .........................................................614 22.1.2 on-chip debug option byte (000c 3h/ 010c 3h)............................................................................. 615 22.2 format of user option byte ............................................................................................... ..... 615 22.3 format of on-chip debug option byte......................... .......................................................... 617 22.4 setting of option byte ................................................................................................... .......... 617 chapter 23 flash memory .................................................................................................... ...... 618 23.1 writing with flash memory programmer ............................................................................... 618 23.2 programming environment .................................................................................................. ... 620 23.3 communication mode ....................................................................................................... ....... 620 23.4 connection of pins on board.............................................................................................. .... 621 23.4.1 fl md0 pin.............................................................................................................. .......................621 23.4.2 t ool0 pi n.............................................................................................................. .......................622 23.4.3 r eset pin .............................................................................................................. ......................622 23.4.4 po rt pins .............................................................................................................. ..........................623 23.4.5 re gc pin ............................................................................................................... .......................623 23.4.6 x1 an d x2 pins ......................................................................................................... .....................623 23.4.7 powe r suppl y........................................................................................................... ......................623 23.5 registers that control flash memory .................................................................................... 62 3 23.6 programming method ....................................................................................................... ....... 624 23.6.1 controlli ng flash memory............................................................................................... ................624 user?s manual u17854ej6v0ud 15 23.6.2 flash memory programmi ng mode .......................................................................................... .....624 23.6.3 selecting communicati on mode ........................................................................................... .........625 23.6.4 communi cation co mmands................................................................................................. ..........625 23.7 security settings........................................................................................................ .............. 627 23.8 flash memory programming by self-programming . ............................................................ 629 23.8.1 boot swap func tion..................................................................................................... ...................631 23.8.2 flash shield window f unction ........................................................................................... .............633 chapter 24 on-chip debug function ..................................................................................... 634 24.1 connecting qb-mini2 to 78k0r/ke3 ........................... ......................................................... 634 24.2 on-chip debug security id.................................................................................................... 63 5 24.3 securing of user resources ................................................................................................... 63 5 chapter 25 bcd correction circuit ....................... .............................................................. 637 25.1 bcd correction circuit function .................................. ........................................................ 637 25.2 registers used by bcd correction circuit .............. ............................................................ 637 25.3 bcd correction circuit operation ........................................................................................ 638 chapter 26 instruction set .................................................................................................. ..... 640 26.1 conventions used in operation list ........................ .............................................................. 6 40 26.1.1 operand identifiers and specificat ion me thods .......................................................................... ...640 26.1.2 description of operation column........................................................................................ ............641 26.1.3 description of flag operati on colu mn ................................................................................... ..........642 26.1.4 prefix instruct ion ..................................................................................................... ..................642 26.2 operation list ........................................................................................................... ................ 643 chapter 27 electrical specifications................................................................................. 660 chapter 28 package drawings................................................................................................. 704 appendix a development tools .............................................................................................. 7 08 a.1 software package.......................................................................................................... ............ 711 a.2 language processing software .. ............................................................................................ . 711 a.3 control software.......................................................................................................... .............. 712 a.4 flash memory programming tools ................................ ......................................................... 712 a.4.1 when using flash memory programme r fg-fp5, fl-pr5, fg -fp4, and fl -pr4..........................712 a.4.2 when using on-chip debug emulator with programm ing function qb-mini2 ..................................713 a.5 debugging tools (hardwar e) ................................................................................................ ... 713 a.5.1 when using in-circu it emulator qb-78k 0rkx3 .............................................................................. 713 a.5.2 when using on-chip debug emulator with programm ing function qb-mini2 ..................................714 a.6 debugging tools (s oftware)................................................................................................ ..... 715 appendix b revision history ................................................................................................ ..... 716 b.1 major revisions in this edition ........................................................................................... .... 716 b.2 revision history of preceding ed itions .................................................................................. 72 0 user?s manual u17854ej6v0ud 16 chapter 1 outline 1.1 features { minimum instruction execution time can be changed from high speed (0.05 s: @ 20 mhz operation with high- speed system clock) to ultra low-speed (61 s: @ 32.768 khz operation with subsystem clock) { general-purpose register: 8 bits 32 registers (8 bits 8 registers 4 banks) { rom, ram capacities item part number program memory (rom) data memory (ram) pd78f1142 64 kb 4 kb pd78f1143 96 kb 6 kb pd78f1144 128 kb 8 kb pd78f1145 192 kb 10 kb pd78f1146 flash memory 256 kb 12 kb { on-chip single-power-supply flash memory (with prohib ition of chip erase/block erase/writing function) { self-programming (with boot swap func tion/flash shield window function) { on-chip debug function { on-chip power-on-clear (poc) circuit and low-voltage detector (lvi) { on-chip watchdog timer (operable with the on-chip internal low-speed oscillation clock) { on-chip multiplier (16 bits 16 bits) { on-chip key interrupt function { on-chip clock output/buzzer output controller { on-chip bcd adjustment { i/o ports: 55 (n-ch open drain: 4) { timer: 10 channels ? 16-bit timer: 8 channels ? watchdog timer: 1 channel ? real-time counter: 1 channel { serial interface ? uart/csi: 1 channel ? uart/csi/simplified i 2 c: 1 channel ? uart (lin-bus supported): 1 channel ? i 2 c: 1 channel { 10-bit resolution a/d converter (av ref = 2.3 to 5.5 v): 8 channels { power supply voltage: v dd = 1.8 to 5.5 v { operating ambient temperature: t a = ? 40 to +85 c chapter 1 outline user?s manual u17854ej6v0ud 17 1.2 applications { home appliances ? laser printer motors ? clothes washers ? air conditioners ? refrigerators { home audio systems { digital cameras, digital video cameras 1.3 ordering information ? flash memory version (lead-free products) note under development caution the 78k0r/ke3 has an on-ch ip debug function. do not u se this product for mass production, because its reliability cannot be gu aranteed after the on-chip debu g function has been used, with respect to the number of times the flash memory can be rewritten. nec electronics does not accept complaints about this product after the on-chip debug function has been used. part number package pd78f1142gk-gaj-ax 64-pin plastic lqfp (12 12) pd78f1143gk-gaj-ax 64-pin plastic lqfp (12 12) pd78f1144gk-gaj-ax 64-pin plastic lqfp (12 12) pd78f1145gk-gaj-ax 64-pin plastic lqfp (12 12) pd78f1146gk-gaj-ax 64-pin plastic lqfp (12 12) pd78f1142gb-gah-ax 64-pin plastic lqfp (fine pitch) (10 10) pd78f1143gb-gah-ax 64-pin plastic lqfp (fine pitch) (10 10) pd78f1144gb-gah-ax 64-pin plastic lqfp (fine pitch) (10 10) pd78f1145gb-gah-ax 64-pin plastic lqfp (fine pitch) (10 10) pd78f1146gb-gah-ax 64-pin plastic lqfp (fine pitch) (10 10) pd78f1142ga-hab-ax note 64-pin plastic tqfp (fine pitch) (7 7) pd78f1143ga-hab-ax note 64-pin plastic tqfp (fine pitch) (7 7) pd78f1144ga-hab-ax note 64-pin plastic tqfp (fine pitch) (7 7) pd78f1145ga-hab-ax note 64-pin plastic tqfp (fine pitch) (7 7) pd78f1146ga-hab-ax note 64-pin plastic tqfp (fine pitch) (7 7) pd78f1142f1-an1-a note 64-pin plastic fbga (5 5) pd78f1143f1-an1-a note 64-pin plastic fbga (5 5) pd78f1144f1-an1-a note 64-pin plastic fbga (5 5) pd78f1145f1-an1-a note 64-pin plastic fbga (5 5) pd78f1146f1-an1-a note 64-pin plastic fbga (5 5) chapter 1 outline user?s manual u17854ej6v0ud 18 1.4 pin configuration (top view) ? 64-pin plastic lqfp (12 12) ? 64-pin plastic lqfp (fine pitch) (10 10) ? 64-pin plastic tqfp (fine pitch) (7 7) note 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p140/pclbuz0/intp6 p141/pclbuz1/intp7 p00/ti00 p01/to00 p02/so10/txd1 p03/si10/rxd1/sda10 p04/sck10/scl10 p130 p20/ani0 p21/ani1 p22/ani2 p23/ani3 p24/ani4 p25/ani5 p26/ani6 p27/ani7 p60/scl0 p61/sda0 p62 p63 p31/ti03/to03/intp4 p77/kr7/intp11 p76/kr6/intp10 p75/kr5/intp9 p74/kr4/intp8 p73/kr3 p72/kr2 p71/kr1 p70/kr0 p06/ti06/to06 p05/ti05/to05 p30/intp3/rtc1hz av ss av ref p10/sck00 p11/si00/rxd0 p12/so00/txd0 p13/txd3 p14/rxd3 p15/rtcdiv/rtccl p16/ti01/to01/intp5 p17/ti02/to02 p55 p54 p53 p52 p51/intp2 p50/intp1 p120/intp0/exlvi p43 p42/ti04/to04 p41/tool1 p40/tool0 reset p124/xt2 p123/xt1 flmd0 p122/x2/exclk p121/x1 regc v ss ev ss v dd ev dd 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 note under development cautions 1. make av ss the same potential as ev ss and v ss . 2. make ev dd the same potential as v dd . 3. connect the regc pin to vss via a capacitor (0.47 to 1 f). chapter 1 outline user?s manual u17854ej6v0ud 19 ? 64-pin plastic fbga (5 5) note 1 hgfedcba 2 3 4 5 6 7 8 abcdefgh top view bottom view index mark pin no. pin name pin no. pin name pin no. pin name pin no. pin name a1 p30/intp3/rtc1hz c1 p17/ti02/to02 e1 p13/txd3 g1 av ref a2 p05/ti05/to05 c2 p10/sck00 e2 p15/rtcdiv/rtccl g2 p24/ani4 a3 p06/ti06/to06 c3 p53 e3 p54 g3 p23/ani3 a4 p74/kr4/intp8 c4 p70/kr0 e4 p52 g4 p22/ani2 a5 p76/kr6/intp10 c5 p63 e5 p77/kr7/intp11 g5 p02/so10/txd1 a6 p62 c6 p60/scl0 e6 p41/tool1 g6 p00/ti00 a7 p61/sda0 c7 v ss e7 reset g7 p140/pclbuz0 /intp6 a8 ev dd c8 p121/x1 e8 flmd0 g8 p124/xt2 b1 p51/intp2 d1 p16/ti01/to01 /intp5 f1 p11/si00/rxd0 h1 avss b2 p50/intp1 d2 p14/rxd3 f2 p12/so00/txd0 h2 p26/ani6 b3 p27/ani7 d3 p55 f3 p20/ani0 h3 p25/ani5 b4 p03/si10/rxd1 /sda10 d4 p71/kr1 f4 p130 h4 p21/ani1 b5 p75/kr5/intp9 d5 p72/kr2 f5 p73/kr3 h5 p04/sck10/scl10 b6 p31/ti03/to03/intp4 d6 p40/tool0 f6 p43 h6 p01/to00 b7 v dd d7 regc f7 p42/ti04/to04 h7 p141/pclbuz1 /intp7 b8 ev ss d8 p122/x2/exclk f8 p123/xt1 h8 p120/intp0/exlvi note under development cautions 1. make av ss the same potential as ev ss and v ss . 2. make ev dd the same potential as v dd . 3. connect the regc pin to vss via a capacitor (0.47 to 1 f). chapter 1 outline user?s manual u17854ej6v0ud 20 pin identification ani0-ani7: analog input av ref : analog reference voltage av ss : analog ground ev dd : power supply for port ev ss : ground for port exclk: external clock input (main system clock) exlvi: external potential input for low-voltage detector flmd0: flash programming mode intp0-intp11: external interrupt input kr0-kr7: key return p00-p06: port 0 p10-p17: port 1 p20-p27: port 2 p30, p31: port 3 p40-p43: port 4 p50-p55: port 5 p60-p63: port 6 p70-p77: port 7 p120-p124: port 12 p130: port 13 p140, p141: port 14 pclbuz0, pclbuz1: programmable clock output/ buzzer output regc: regulator capacitance reset: reset rtc1hz: real-time counter correction clock (1 hz) output rtccl: real-time counter clock (32 khz original oscillation) output rtcdiv: real-time counter clock (32 khz divided frequency) output rxd0, rxd1, rxd3: receive data sck00, sck10: serial clock input/output scl0, scl10: serial clock input/output sda0, sda10: serial data input/output si00, si10: serial data input so00, so10: serial data output ti00-ti06: timer input to00-to06: timer output tool0: data input/output for tool tool1: clock output for tool txd0, txd1, txd3: transmit data v dd : power supply v ss : ground x1, x2: crystal oscillat or (main system clock) xt1, xt2: crystal oscillator (subsystem clock) chapter 1 outline user?s manual u17854ej6v0ud 21 1.5 78k0r microcontroller lineup 78k0r/ke3 78k0r/kf3 78k0r/kg3 78k0r/kh3 78k0r/kj3 rom ram 64 pins 80 pins 100 pi ns 128 pins 144 pins 512 kb 30 kb ? ? pd78f1168 note pd78f1178 note pd78f1188 note 384 kb 24 kb ? ? pd78f1167 note pd78f1177 note pd78f1187 note 256 kb 12 kb pd78f1146 pd78f1156 pd78f1166 pd78f1176 note pd78f1186 note 192 kb 10 kb pd78f1145 pd78f1155 pd78f1165 pd78f1175 note pd78f1185 note 128 kb 8 kb pd78f1144 pd78f1154 pd78f1164 pd78f1174 note pd78f1184 note 96 kb 6 kb pd78f1143 pd78f1153 pd78f1163 ? ? 64 kb 4 kb pd78f1142 pd78f1152 pd78f1162 ? ? note under development chapter 1 outline user?s manual u17854ej6v0ud 22 1.6 block diagram port 0 p00 to p06 7 port 1 p10 to p17 port 2 p20 to p27 8 port 3 p30, p31 2 port 4 port 5 v ss , ev ss flmd0 v dd , ev dd 8 port 6 p60 to p63 4 port 7 p70 to p77 port 12 p121 to p124 port 13 p130 8 p40 to p43 4 p50 to p55 6 port 14 p140, p141 2 buzzer output pclbuz0/p140, pclbuz1/p141 clock output control voltage regulator regc interrupt control ram 78k0r cpu core flash memory window watchdog timer low-speed internal oscillator power on clear/ low voltage indicator poc/lvi control reset control key return 8 kr0/p70 to kr7/p77 exlvi/p120 system control reset x1/p121 x2/exclk/p122 high-speed internal oscillator xt1/p123 xt2/p124 multiplier on-chip debug tool0/p40 tool1/p41 realtime counter direct memory access control serial array unit0 (4ch) uart0 serial array unit1 (4ch) uart3 linsel uart1 csi00 iic10 rxd0/p11 txd0/p12 rxd1/p03 txd1/p02 sck00/p10 so00/p12 si00/p11 scl10/p04 sda10/p03 rxd3/p14 txd3/p13 timer array unit (8ch) ch0 ch1 ti00/p00 to00/p01 ti01/to01/p16 ch2 ti02/to02/p17 ch3 ti03/to03/p31 ch4 ti04/to04/p42 ch5 ti05/to05/p05 ch6 ti06/to06/p06 ch7 intp1/p50, intp2/p51 2 intp0/p120 intp5/p16 intp8/p74 to intp11/p77 4 intp3/p30, intp4/p31 2 intp6/p140, intp7/p141 2 rxd3/p14 (linsel) csi10 sck10/p04 so10/p02 si10/p03 rxd3/p14 (linsel) serial interface iic0 sda0/p61 scl0/p60 a/d converter 8 ani0/p20 to ani7/p27 av ref av ss 4 p120 2 rtc1hz/p30 rtcdiv/rtccl/p15 bcd adjustment chapter 1 outline user?s manual u17854ej6v0ud 23 1.7 outline of functions (1/2) item pd78f1142 pd78f1143 pd78f1144 pd78f1145 pd78f1146 flash memory (self-programming supported) 64 kb 96 kb 128 kb 192 kb 256 kb internal memory ram 4 kb 6 kb 8 kb 10 kb 12 kb memory space 1 mb high-speed system clock x1 (crystal/ceramic) oscillation, extern al main system clock input (exclk) 2 to 20 mhz: v dd = 2.7 to 5.5 v, 2 to 5 mhz: v dd = 1.8 to 5.5 v main system clock (oscillation frequency) internal high-speed oscillation clock internal oscillation 8 mhz (typ.): v dd = 1.8 to 5.5 v subsystem clock (oscillation frequency) xt1 (crystal) oscillation 32.768 khz (typ.): v dd = 1.8 to 5.5 v internal low-speed oscillation clock (for wdt) internal oscillation 240 khz (typ.): v dd = 1.8 to 5.5 v general-purpose register 8 bits 32 registers (8 bits 8 registers 4 banks) 0.05 s (high-speed system clock: f mx = 20 mhz operation) 0.125 s (internal high-speed oscillation clock: f ih = 8 mhz (typ.) operation) minimum instruction execution time 61 s (subsystem clock: f sub = 32.768 khz operation) instruction set ? 8-bit operation, 16-bit operation ? multiply (16 bits 16 bits) ? bit manipulation (set, reset, test, and boolean operation), etc. i/o port total: 55 cmos i/o: 46 cmos input: 4 cmos output: 1 n-ch open-drain i/o (6 v tolerance): 4 timer ? 16-bit timer: 8 channels ? watchdog timer: 1 channel ? real-time counter: 1 channel timer outputs 7 (pwm output: 6) rtc outputs 2 ? 1 hz (subsystem clock: f sub = 32.768 khz) ? 512 hz, 16.384 khz, or 32.768 khz (subsystem clock: f sub = 32.768 khz) clock output/buzzer output 2 ? 2.44 khz, 4.88 khz, 9.76 khz, 1.25 mhz, 2.5 mhz, 5 mhz, 10 mhz (peripheral hardware clock: f main = 20 mhz operation) ? 256 hz, 512 hz, 1.024 khz, 2.048 khz, 4.096 khz, 8.192 khz, 16.384 khz, 32.768 khz (subsystem clock: f sub = 32.768 khz operation) a/d converter 10-bit resolution 8 channels (av ref = 2.3 to 5.5 v) chapter 1 outline user?s manual u17854ej6v0ud 24 (2/2) item pd78f1142 pd78f1143 pd78f1144 pd78f1145 pd78f1146 serial interface ? uart supporting lin-bus: 1 channel ? uart/csi: 1 channel ? uart/csi/simplified i 2 c: 1 channel ? i 2 c bus: 1 channel multiplier 16 bits 16 bits = 32 bits dma controller 2 channels internal 25 vectored interrupt sources external 13 key interrupt key interrupt (int kr) occurs by detecting falling edge of the key input pins (kr0 to kr7). reset ? reset by reset pin ? internal reset by watchdog timer ? internal reset by power-on-clear ? internal reset by low-voltage detector ? internal reset by illegal instruction execution note 1 on-chip debug function provided power supply voltage v dd = 1.8 to 5.5 v operating ambient temperature t a = ? 40 to +85 c package 64-pin plastic lqfp (12 12) (0.65 mm pitch) 64-pin plastic lqfp (fine pitch) (10 10) (0.5 mm pitch) 64-pin plastic tqfp (fine pitch) (7 7) (0.4 mm pitch) note 2 64-pin plastic fbga (5 5) (0.5 mm pitch) note 2 notes 1. the illegal instruction is generated wh en instruction code ffh is executed. reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip debug emulator. 2. under development user?s manual u17854ej6v0ud 25 chapter 2 pin functions 2.1 pin function list there are three types of pi n i/o buffer power supplies: av ref , ev dd , and v dd . the relationship between these power supplies and the pins is shown below. table 2-1. pin i/o buffer power supplies power supply corresponding pins av ref p20 to p27 ev dd ? port pins other than p20 to p27 and p121 to p124 ? reset pin and flmd0 pin v dd ? p121 to p124 ? pins other than port pins (except reset pin and flmd0 pin ) chapter 2 pin functions user?s manual u17854ej6v0ud 26 (1) port functions (1/2) function name i/o function after reset alternate function p00 ti00 p01 to00 p02 so10/txd1 p03 si10/rxd1/sda10 p04 sck10/scl10 p05 ti05/to05 p06 i/o port 0. 7-bit i/o port. input of p03 and p04 can be set to ttl input buffer. output of p02 to p04 can be set to n-ch open-drain output (v dd tolerance). input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port ti06/to06 p10 sck00 p11 si00/rxd0 p12 so00/txd0 p13 txd3 p14 rxd3 p15 rtcdiv/rtccl p16 ti01/to01/intp5 p17 i/o port 1. 8-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port ti02/to02 p20 to p27 i/o port 2. 8-bit i/o port. input/output can be specified in 1-bit units. digital input port ani0 to ani7 p30 rtc1hz/intp3 p31 i/o port 3. 2-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port ti03/to03/intp4 p40 note tool0 p41 tool1 p42 ti04/to04 p43 i/o port 4. 4-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port ? p50 intp1 p51 intp2 p52 ? p53 ? p54 ? p55 i/o port 5. 6-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port ? p60 scl0 p61 sda0 p62 ? p63 i/o port 6. 4-bit i/o port. output of p60 to p63 can be set to n-ch open-drain output (6 v tolerance). input/output can be specified in 1-bit units. input port ? p70 to p73 kr0 to kr3 p74 to p77 i/o port 7. 8-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port kr4/intp8 to kr7/ intp11 note if on-chip debugging is enabled by using an option by te, be sure to pull up the p40/tool0 pin externally (see caution in 2.2.5 p40 to p43 (port 4) ). chapter 2 pin functions user?s manual u17854ej6v0ud 27 (1) port functions (2/2) function name i/o function after reset alternate function p120 i/o intp0/exlvi p121 x1 p122 x2/exclk p123 xt1 p124 input port 12. 1-bit i/o port and 4-bit input port. for only p120, use of an on-chip pull-up resistor can be specified by a software setting. input port xt2 p130 output port 13. 1-bit output port. output port ? p140 pclbuz0/intp6 p141 i/o port 14. 2-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port pclbuz1/intp7 chapter 2 pin functions user?s manual u17854ej6v0ud 28 (2) non-port functions (1/2) function name i/o function afte r reset alternate function ani0-ani7 input a/d converte r analog input digital input port p20 to p27 exlvi input potential input for external low-voltage detection input port p120/intp0 intp0 p120/exlvi intp1 p50 intp2 p51 intp3 p30/rtc1hz intp4 p31/ti03/to03 intp5 p16/ti01/to01 intp6 p140/pclbuz0 intp7 p141/pclbuz1 intp8 intp9 intp10 intp11 input external interrupt request i nput for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified input port p74/kr4 to p77/kr7 kr0-kr3 p70 to p73 kr4-kr7 input key interrupt input input port p74/intp8 to p77/intp11 pclbuz0 p140/intp6 pclbuz1 output clock output/buzzer output input port p141/intp7 regc ? connecting regulator output (2.5 v) stabilization capacitance for internal operation. connect to v ss via a capacitor (0.47 to 1 f). ? ? rtcdiv output real-time counter clock (32 kh z divided frequency) output input port p15/rtccl rtccl output real-time counter clock (32 khz or iginal oscillation) output input port p15/rtcdiv rtc1hz output real-time counter correction clock (1 hz) output input port p30/intp3 reset input system reset input ? ? rxd0 input serial data input to uart0 input port p11/si00 rxd1 input serial data input to uart1 input port p03/si10/sda10 rxd3 input serial data input to uart3 input port p14 sck00 p10 sck10 i/o clock input/output for csi00 and csi10 input port p04/scl10 scl0 i/o clock input/output for i 2 c input port p60 scl10 i/o clock input/output for simplified i 2 c input port p04/sck10 sda0 serial data i/o for i 2 c input port p61 sda10 i/o clock input/output for simplified i 2 c input port p03/si10/rxd1 si00 p11/rxd0 si10 i/o serial data input to csi00 and csi10 input port p03/rxd1/sda10 so00 p12/txd0 so10 output serial data output from csi00 and csi10 input port p02/txd1 chapter 2 pin functions user?s manual u17854ej6v0ud 29 (2) non-port functions (2/2) function name i/o function afte r reset alternate function ti00 external count clock input to 16-bit timer 00 p00 ti01 external count clock input to 16-bit timer 01 p16/to01/intp5 ti02 external count clock input to 16-bit timer 02 p17/to02 ti03 external count clock input to 16-bit timer 03 p31/to03/intp4 ti04 external count clock input to 16-bit timer 04 p42/to04 ti05 external count clock input to 16-bit timer 05 p05/to05 ti06 input external count clock input to 16-bit timer 06 input port p06/to06 to00 16-bit timer 00 output p01 to01 16-bit timer 01 output p16/ti01/intp5 to02 16-bit timer 02 output p17/ti02 to03 16-bit timer 03 output p31/ti03/intp4 to04 16-bit timer 04 output p42/ti04 to05 16-bit timer 05 output p05/ti05 to06 output 16-bit timer 06 output input port p06/ti06 txd0 output serial data output from uart0 input port p12/so00 txd1 output serial data output from uart1 input port p02/so10 txd3 output serial data output from uart3 input port p13 x1 ? input port p121 x2 ? resonator connection for main system clock input port p122/exclk exclk input external clock input for ma in system clock input port p122/x2 xt1 ? input port p123 xt2 ? resonator connection for subsystem clock input port p124 v dd ? positive power supply (p121 to p124 and other than ports) ? ? ev dd ? positive power supply for ports (other than p20 to p27, p121 to p124) ? ? av ref ? ? a/d converter reference voltage input ? positive power supply for p20 to p27, and a/d converter ? ? v ss ? ground potential (p121 to p124 and other than ports) ? ? ev ss ? ground potential for ports (other than p20 to p27 and p121 to p124) ? ? av ss ? ground potential for a/d converter, p20 to p27. use this pin with the same potential as ev ss and v ss . ? ? flmd0 ? flash memory programming mode setting ? ? tool0 i/o data i/o for flash memory programmer/debugger input port p40 tool1 output clock output for debugger input port p41 chapter 2 pin functions user?s manual u17854ej6v0ud 30 2.2 description of pin functions 2.2.1 p00 to p06 (port 0) p00 to p06 function as a 7-bit i/o port. these pins also function as timer i/o, serial interface data i/o, and clock i/o. input to the p03 and p04 pins can be s pecified through a normal input buffer or a ttl input buffer in 1-bit units, using port input mode register 0 (pim0). output from the p02 to p04 pins can be specified as normal cmos output or n-ch open-drain output (v dd tolerance) in 1-bit units, using port output mode register 0 (pom0). the following operation modes can be specified in 1-bit units. (1) port mode p00 to p06 function as a 7-bit i/o port. p00 to p06 can be set to input or output port in 1-bit units using port mode register 0 (pm0). use of an on -chip pull-up resistor can be specified by pull-up resistor option register 0 (pu0). (2) control mode p00 to p06 function as timer i/o, se rial interface data i/o, and clock i/o. (a) ti00, ti05, ti06 thess are the pins for inputting an external count clock/capture trigger to 16-bit timer 00, 05, and 06. (b) to00, to05, to06 these are the timer output pins of 16-bit timer 00, 05, and 06. (c) si10 this is a serial data input pi n of serial interface csi10. (d) so10 this is a serial data output pin of serial interface csi10. (e) sck10 this is a serial clock i/o pin of serial interface csi10. (f) txd1 this is a serial data output pin of serial interface uart1. (g) rxd1 this is a serial data input pi n of serial interface uart1. (h) sda10 this is a serial data i/o pin of serial interface for simplified i 2 c. chapter 2 pin functions user?s manual u17854ej6v0ud 31 (i) scl10 this is a serial clock i/o pin of serial interface for simplified i 2 c. caution to use p02/so10/txd1 and p04/sck10/ scl10 as general-pur pose ports, set serial communication operation setting register 02 (scr0 2) to the default status (0087h). in addition, clear port output mode register 0 (pom0) to 00h. 2.2.2 p10 to p17 (port 1) p10 to p17 function as an 8-bit i/o port. these pins al so function as external interrupt request input, serial interface data i/o, clock i/o, timer i/o, and real-tim e counter clock output. the following operation modes can be specified in 1-bit units. (1) port mode p10 to p17 function as an 8-bit i/o port. p10 to p17 can be set to input or output por t in 1-bit units using port mode register 1 (pm1). use of an on -chip pull-up resistor can be specified by pull-up resistor option register 1 (pu1). (2) control mode p10 to p17 function as external interru pt request input, serial interface dat a i/o, clock i/o, time r i/o, and real-time counter clock output. (a) si00 this is a serial data input pi n of serial interface csi00. (b) so00 this is a serial data output pin of serial interface csi00. (c) sck00 this is a serial clock i/o pin of serial interface csi00. (d) rxd0 this is a serial data input pi n of serial interface uart0. (e) rxd3 this is a serial data input pi n of serial interface uart3. (f) txd0 this is a serial data output pin of serial interface uart0. (g) txd3 this is a serial data output pin of serial interface uart3. (h) ti01, ti02 these are the pins for inputting an external count clock/capture trigger to 16-bit timers 01 and 02. chapter 2 pin functions user?s manual u17854ej6v0ud 32 (i) to01, to02 these are the timer output pins of 16-bit timers 01 and 02. (j) intp5 this is an external interrupt request input pin for whic h the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. (k) rtcdiv this is a real-time counter clo ck (32 khz, divided) output pin. (l) rtccl this is a real-time counter clock (32 kh z, original oscillation) output pin. cautions 1. to use p10/sck00 and p12/so 00/txd0 as general-purpose ports, set serial communication operation setting register 00 (s cr00) to the default status (0087h). 2. do not enable outputting rtccl and rtcdiv at the same time. 2.2.3 p20 to p27 (port 2) p20 to p27 function as an 8-bit i/o port. these pins also function as a/d converter analog input. the following operation modes can be specified in 1-bit units. (1) port mode p20 to p27 function as an 8-bit i/o port. p20 to p27 can be set to input or output por t in 1-bit units using port mode register 2 (pm2). (2) control mode p20 to p27 function as a/d converter analog input pins (ani0 to ani7). when using these pins as analog input pins, see 10.6 (5) ani0/p20 to ani7/p27 . caution ani0/p20 to ani7/p27 are set in the digital input (general-purpose port) mode after release of reset. 2.2.4 p30, p31 (port 3) p30 and p31 function as a 2-bit i/o port. these pins also function as external interrupt request input, timer i/o, and real-time counter correction clock output. the following operation modes can be specified in 1-bit units. (1) port mode p30 and p31 function as a 2- bit i/o port. p30 and p31 can be set to input or output port in 1-bit units using port mode register 3 (pm3). use of an on -chip pull-up resistor can be specified by pull-up resistor option register 3 (pu3). (2) control mode p30 and p31 function as external interrupt request input, timer i/o, and real -time counter correction clock output. (a) intp3, intp4 these are the external interrupt request input pins fo r which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. chapter 2 pin functions user?s manual u17854ej6v0ud 33 (b) ti03 this is a pin for inputting an external count clock/capture trigger to 16-bit timer 03. (c) to03 this is a timer output pin from 16-bit timer 03. (d) rtc1hz this is a real-time counter correction clock (1 hz) output pin. 2.2.5 p40 to p43 (port 4) p40 to p43 function as an 4-bit i/o port. these pi ns also function as data i/o for a flash memory programmer/debugger, clock output, and timer i/o. the following operation modes can be specified in 1-bit units. (1) port mode p40 to p43 function as an 4-bit i/o port. p40 to p43 can be set to input or output por t in 1-bit units using port mode register 4 (pm4). use of an on -chip pull-up resistor can be specified by pull-up resistor option register 4 (pu4). be sure to connect an external pull-up resistor to p40 when on-chip debugging is enabled (by using an option byte). (2) control mode p40 to p43 function as data i/o for a flash memo ry programmer/debugger, clock output, and timer i/o. (a) tool0 this is a data i/o pin for a flash memory programmer/debugger. be sure to pull up this pin externally when on-chip debugging is enabled (pulling it down is prohibited). (b) tool1 this is a clock output pin for a debugger. when the on-chip debug function is used, p41/tool1 pin can be used as follows by the mode setting on the debugger. 1-line mode: can be used as a port (p41). 2-line mode: used as a tool1 pin a nd cannot be used as a port (p41). (c) ti04 this is a pin for inputting an external count clock/capture trigger to 16-bit timers 04. (d) to04 this is a timer output pin from 16-bit timers 04. caution the function of the p40/tool0 pin var ies as described in (a) to (c) below. in the case of (b) or (c), make the specified connection. (a) in normal operation mode and when on-chi p debugging is disabled (ocdenset = 0) by an option byte (000c3h) => use this pin as a port pin (p40). chapter 2 pin functions user?s manual u17854ej6v0ud 34 (b) in normal operation mode and when on-chip debugging is enabled (ocdenset = 1) by an option byte (000c3h) => connect this pin to ev dd via an external resistor, a nd always input a high level to the pin before reset release. (c) when on-chip debug functi on is used, or in write mode of flash memory programmer => use this pin as tool0. directly connect this pin to the on-c hip debug emulator or a flash memory programmer, or pull it up by connecting it to ev dd via an external resistor. 2.2.6 p50 to p55 (port 5) p50 to p55 function as an 6-bit i/o port. these pins also function as external interrupt request input. the following operation modes can be specified in 1-bit units. (1) port mode p50 to p55 function as an 6-bit i/o port. p50 to p55 can be set to input or output por t in 1-bit units using port mode register 5 (pm5). use of an on -chip pull-up resistor can be specified by pull-up resistor option register 5 (pu5). (2) control mode p50 to p55 function as external interrupt request input. (a) intp1, intp2 these are the external interrupt request input pins fo r which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. 2.2.7 p60 to p63 (port 6) p60 to p63 function as an 4-bit i/o port. these pins also function as serial interface data i/o and clock i/o. the following operation modes can be specified in 1-bit units. (1) port mode p60 to p63 function as an 4-bit i/o port. p60 to p63 can be set to input port or output port in 1-bit units using port mode register 6 (pm6). output of p60 to p63 is n-ch open-drain output (6 v tolerance). (2) control mode p60 to p63 function as serial interface data i/o and clock i/o. (a) sda0 this is a serial data i/o pin of serial interface iic0. (b) scl0 this is a serial clock i/o pi n of serial interface iic0. 2.2.8 p70 to p77 (port 7) p70 to p77 function as an 8-bit i/o port. these pins also function as key interrupt input and external interrupt request input. the following operation modes can be specified in 1-bit units. chapter 2 pin functions user?s manual u17854ej6v0ud 35 (1) port mode p70 to p77 function as an 8-bit i/o port. p70 to p77 can be set to input or output por t in 1-bit units using port mode register 7 (pm7). use of an on -chip pull-up resistor can be specified by pull-up resistor option register 7 (pu7). (2) control mode p70 to p77 function as key interrupt input, and external interrupt request input. (a) kr0 to kr7 these are the key interrupt input pins (b) intp8 to intp11 these are the external interrupt request input pins fo r which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. 2.2.9 p120 to p124 (port 12) p120 functions as a 1-bit i/o port. p121 to p124 function as a 4-bit input port. these pins also function as external interrupt request input, potential input fo r external low-voltage det ection, connecting resonator for main system clock, connecting resonator for subsystem clock, and exte rnal clock input for main system clock. the following operation modes can be specified in 1-bit units. (1) port mode p120 functions as a 1-bit i/o port. p120 can be set to input or output port using port mode register 12 (pm12). use of an on-chip pull-up resistor can be specified by pull-up resistor option register 12 (pu12). p121 to p124 function as a 4-bit input port. (2) control mode p120 to p124 function as external interrupt request in put, potential input for exter nal low-voltage detection, connecting resonator for main system clock, connecting re sonator for subsystem clock, and external clock input for main system clock. (a) intp0 this is an external interrupt request input pin for whic h the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. (b) exlvi this is a potential input pin for external low-voltage detection. (c) x1, x2 these are the pins for connecting a resonator for main system clock. (d) exclk this is an external clock inpu t pin for main system clock. (e) xt1, xt2 these are the pins for connecting a resonator for subsystem clock. chapter 2 pin functions user?s manual u17854ej6v0ud 36 2.2.10 p130 (port 13) p130 functions as a 1-bit output port. remark when the device is reset, p130 outputs a low level. therefore, to output a high level from p130 before the device is reset, the output signa l of p130 can be used as a pseudo reset signal of the cpu (see the figure for remark in 4.2.10 port 13 ). 2.2.11 p140, p141 (port 14) p140 and p141 function as a 2-bit i/o port. these pins also function as external interrupt request input and clock/buzzer output. the following operation modes can be specified in 1-bit units. (1) port mode p140 and p141 function as a 2-bit i/o port. p140 and p141 c an be set to input or output port in 1-bit units using port mode register 14 (pm14). use of an on-chip pull-up resistor can be specified by pull-up resistor option register 14 (pu14). (2) control mode p140 and p141 function as external interrupt request input, and clock/buzzer output. (a) intp6, intp7 these are the external interrupt request input pins fo r which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. (b) pclbuz0, pclbuz1 these are the clock/buzzer output pins. 2.2.12 av ref this is the a/d converter reference voltage input pin and the positive power supply pin of p20 to p27 and a/d converter. when all pins of port 2 are used as the an alog port pins, make the potential of av ref be such that 2.3 v av ref v dd . when one or more of the pins of port 2 are used as the digital port pins or when the a/d converter is not used, make av ref the same potential as ev dd or v dd . 2.2.13 av ss this is the ground potential pi n of a/d converter, p20 to p27. even wh en the a/d converter is not used, always use this pin with the same potential as ev ss and v ss . 2.2.14 reset this is the active-low system reset input pin. when the external reset pin is not used, connect this pin directly to v dd or via a resistor. chapter 2 pin functions user?s manual u17854ej6v0ud 37 2.2.15 regc this is the pin for connecting regulator output (2.5 v) stabilization capacitance for internal operation. connect this pin to v ss via a capacitor (0.47 to 1 f). however, when using the stop m ode that has been entered since operation of the internal high-speed oscillation clo ck and external main system clock, 0.47 f is recommended. also, use a capacitor with good characteristics, si nce it is used to stabilize internal voltage. regc v ss caution keep the wiring length as short as possible for the broken- line part in the above figure. 2.2.16 v dd , ev dd v dd is the positive power supply pin for p121 to p124 and other than ports. ev dd is the positive power supply pin for ports other than p20 to p27 and p121 to p124. 2.2.17 v ss , ev ss v ss is the ground potential pin for p121 to p124 and other than ports. ev ss is the ground potential pin for ports ot her than p20 to p27 and p121 to p124. 2.2.18 flmd0 this is a pin for setting flash memory programming mode. perform either of the following processing. (a) in normal operation mode it is recommended to leave this pin open during normal operation. the flmd0 pin must always be kept at the v ss level before reset release but does not have to be pulled down externally because it is internally pulled down by reset. however, pulling it down must be kept selected (i.e., flmdpup = ?0?, default value) by using bit 7 (flmdpup) of the backgroun d event control register (bectl) (see 23.5 (1) back ground event control register ). to pull it down externally, use a resistor of 200 k or smaller. self programming and the rewriting of flash memory with the programmer can be prohibited using hardware, by directly connecting this pin to the v ss pin. (b) in self programming mode it is recommended to leave this pin open when using the self programming function. to pull it down externally, use a resistor of 100 k to 200 k . in the self programming mode, the setting is swit ched to pull up in the self programming library. (c) in flash memory programming mode directly connect this pin to a flash memory progr ammer when data is written by the flash memory programmer. this supplies a writing voltage of the v dd level to the flmd0 pin. the flmd0 pin does not have to be pulled down externally because it is internally pulled down by reset. to pull it down externally, use a resistor of 1 k to 200 k . chapter 2 pin functions user?s manual u17854ej6v0ud 38 2.3 pin i/o circuits and recomme nded connection of unused pins table 2-2 shows the types of pin i/o circuits and the recommended connections of unused pins. table 2-2. connection of unused pins (1/2) pin name i/o circuit type i/o recommended connection of unused pins p00/ti00 8-r p01/to00 p02/so10/txd1 5-ag p03/si10/rxd1/sda10 p04/sck10/scl10 5-an p05/ti05/to05 p06/ti05/to05 p10/sck00 p11/si00/rxd0 8-r p12/so00/txd0 p13/txd3 5-ag p14/rxd3 8-r p15/rtcdiv/rtccl 5-ag p16/ti01/to01/intp5 p17/ti02/to02 8-r input: independently connect to ev dd or ev ss via a resistor. output: leave open. p20/ani0 to p27/ani7 note 11-g input: independently connect to av ref or av ss via a resistor. output: leave open. p30/rtc1hz/intp3 p31/ti03/to03/intp4 input: independently connect to ev dd or ev ss via a resistor. output: leave open. p40/tool0 8-r chapter 2 pin functions user?s manual u17854ej6v0ud 39 table 2-2. connection of unused pins (2/2) pin name i/o circuit type i/o recommended connection of unused pins p121/x1 note p122/x2/exclk note p123/xt1 note p124/xt2 note 37-b input independently connect to v dd or v ss via a resistor. p130 3-c output leave open. p140/pclbuz0/intp6 p141/pclbuz1/intp7 8-r i/o input: independently connect to ev dd or ev ss via a resistor. output: leave open. av ref ? ? chapter 2 pin functions user?s manual u17854ej6v0ud 40 figure 2-1. pin i/o circuit list (1/2) type 2 type 5-ag schmitt-triggered input with hysteresis characteristics in pull-up enable data output disable input enable ev dd p-ch ev dd ev ss p-ch in/out n -ch type 2-w type 5-an in pull-down enable n-ch pull-up enable p-ch ev dd ev ss schmitt-triggered input with hysteresis characteristics pull-up enable data output disable p-ch ev dd ev dd ev ss p-ch in/out n -ch cmos ttl input characteristic type 3-c type 8-r ev dd p-ch n-ch data out ev ss data output disable ev dd p-ch in/out n-ch ev ss pull-up enable ev dd p-ch chapter 2 pin functions user?s manual u17854ej6v0ud 41 figure 2-1. pin i/o circuit list (2/2) type 11-g type 13-r data output disable av ref p-ch in/out n-ch p-ch n-ch input enable + _ av ss av ss comparator series resistor string voltage in/out n -ch data output disable ev ss type 13-p type 37-b data output disable input enable in/out n -ch ev ss x1, xt1 input enable input enable amp enable p-ch n-ch x2, xt2 user?s manual u17854ej6v0ud 42 chapter 3 cpu architecture 3.1 memory space products in the 78k0r/ke3 can access a 1 mb memory s pace. figures 3-1 to 3-5 show the memory maps. figure 3-1. memory map ( pd78f1142) 00000h effffh f0000h f07ffh f0800h f0fffh f1000h feeffh fef00h ffedfh ffee0h ffeffh fff00h fffffh 00000h 0007fh 00080h 000bfh 000c0h 000c3h 000c4h 00fffh 01000h 0107fh 01080h 010bfh 010c0h 010c3h 010c4h 0ffffh 0ffffh 10000h special function register (sfr) 256 bytes ram 4 kb general-purpose register 32 bytes flash memory 64 kb special function register (2nd sfr) 2 kb mirror 55.75 kb vector table area 128 bytes callt table area 64 bytes program area option byte area note 1 4 bytes vector table area 128 bytes callt table area 64 bytes option byte area note 1 4 bytes program area reserved reserved program memory space data memory space on-chip debug security id setting area note 1 10 bytes 01fffh boot cluster 0 note 2 boot cluster 1 010cdh 010ceh on-chip debug security id setting area note 1 10 bytes 000cdh 000ceh notes 1. when boot swap is not used: set the option by tes to 000c0h to 000c3h, and the on-chip debug security ids to 000c4h to 000cdh. when boot swap is used: set the option bytes to 000c0h to 000c3h and 010c0h to 010c3h, and the on-chip debug security ids to 000c4h to 000cdh and 010c4h to 010cdh. 2. writing boot cluster 0 can be prohibited depending on the setting of security (see 23.7 security setting ). chapter 3 cpu architecture user?s manual u17854ej6v0ud 43 figure 3-2. memory map ( pd78f1143) 00000h effffh f0000h f07ffh f0800h f0fffh f1000h fe6ffh fe700h ffedfh ffee0h ffeffh fff00h fffffh 00000h 0007fh 00080h 000bfh 000c0h 000c3h 000c4h 00fffh 01000h 0107fh 01080h 010bfh 010c0h 010c3h 010c4h 17fffh 17fffh 18000h special function register (sfr) 256 bytes ram 6 kb general-purpose register 32 bytes flash memory 96 kb special function register (2nd sfr) 2 kb mirror 53.75 kb vector table area 128 bytes callt table area 64 bytes program area option byte area note 1 4 bytes vector table area 128 bytes callt table area 64 bytes option byte area note 1 4 bytes program area reserved reserved program memory space data memory space on-chip debug security id setting area note 1 10 bytes 01fffh boot cluster 0 note 2 boot cluster 1 010cdh 010ceh on-chip debug security id setting area note 1 10 bytes 000cdh 000ceh notes 1. when boot swap is not used: set the option by tes to 000c0h to 000c3h, and the on-chip debug security ids to 000c4h to 000cdh. when boot swap is used: set the option bytes to 000c0h to 000c3h and 010c0h to 010c3h, and the on-chip debug security ids to 000c4h to 000cdh and 010c4h to 010cdh. 2. writing boot cluster 0 can be prohibited depending on the setting of security (see 23.7 security setting ). chapter 3 cpu architecture user?s manual u17854ej6v0ud 44 figure 3-3. memory map ( pd78f1144) 00000h effffh f0000h f07ffh f0800h f0fffh f1000h fdeffh fdf00h ffedfh ffee0h ffeffh fff00h fffffh 00000h 0007fh 00080h 000bfh 000c0h 000c3h 000c4h 00fffh 01000h 0107fh 01080h 010bfh 010c0h 010c3h 010c4h 1ffffh 1ffffh 20000h special function register (sfr) 256 bytes ram 8 kb general-purpose register 32 bytes flash memory 128 kb special function register (2nd sfr) 2 kb mirror 51.75 kb vector table area 128 bytes callt table area 64 bytes program area option byte area note 1 4 bytes vector table area 128 bytes callt table area 64 bytes option byte area note 1 4 bytes program area reserved reserved program memory space data memory space on-chip debug security id setting area note 1 10 bytes 01fffh boot cluster 0 note 2 boot cluster 1 010cdh 010ceh on-chip debug security id setting area note 1 10 bytes 000cdh 000ceh notes 1. when boot swap is not used: set the option by tes to 000c0h to 000c3h, and the on-chip debug security ids to 000c4h to 000cdh. when boot swap is used: set the option bytes to 000c0h to 000c3h and 010c0h to 010c3h, and the on-chip debug security ids to 000c4h to 000cdh and 010c4h to 010cdh. 2. writing boot cluster 0 can be prohibited depending on the setting of security (see 23.7 security setting ). chapter 3 cpu architecture user?s manual u17854ej6v0ud 45 figure 3-4. memory map ( pd78f1145) 00000h effffh f0000h f07ffh f0800h f0fffh f1000h fd6ffh fd700h ffedfh ffee0h ffeffh fff00h fffffh 00000h 0007fh 00080h 000bfh 000c0h 000c3h 000c4h 00fffh 01000h 0107fh 01080h 010bfh 010c0h 010c3h 010c4h 2ffffh 2ffffh 30000h special function register (sfr) 256 bytes ram 10 kb general-purpose register 32 bytes flash memory 192 kb special function register (2nd sfr) 2 kb mirror 49.75 kb vector table area 128 bytes callt table area 64 bytes program area option byte area note 1 4 bytes vector table area 128 bytes callt table area 64 bytes option byte area note 1 4 bytes program area reserved reserved data memory space program memory space on-chip debug security id setting area note 1 10 bytes 01fffh boot cluster 0 note 2 boot cluster 1 010cdh 010ceh on-chip debug security id setting area note 1 10 bytes 000cdh 000ceh notes 1. when boot swap is not used: set the option by tes to 000c0h to 000c3h, and the on-chip debug security ids to 000c4h to 000cdh. when boot swap is used: set the option bytes to 000c0h to 000c3h and 010c0h to 010c3h, and the on-chip debug security ids to 000c4h to 000cdh and 010c4h to 010cdh. 2. writing boot cluster 0 can be prohibited depending on the setting of security (see 23.7 security setting ). chapter 3 cpu architecture user?s manual u17854ej6v0ud 46 figure 3-5. memory map ( pd78f1146) 00000h effffh f0000h f07ffh f0800h f0fffh f1000h fceffh fcf00h ffedfh ffee0h ffeffh fff00h fffffh 00000h 0007fh 00080h 000bfh 000c0h 000c3h 000c4h 00fffh 01000h 0107fh 01080h 010bfh 010c0h 010c3h 010c4h 3ffffh 3ffffh 40000h special function register (sfr) 256 bytes ram note 1 12 kb general-purpose register 32 bytes flash memory 256 kb special function register (2nd sfr) 2 kb mirror 47.75 kb vector table area 128 bytes callt table area 64 bytes program area option byte area note 2 4 bytes vector table area 128 bytes callt table area 64 bytes option byte area note 2 4 bytes program area reserved reserved data memory space program memory space on-chip debug security id setting area note 2 10 bytes 01fffh boot cluster 0 note 3 boot cluster 1 010cdh 010ceh on-chip debug security id setting area note 2 10 bytes 000cdh 000ceh notes 1. use of the area fcf00h to fd6ffh is prohibited when using the self-p rogramming function. since this area is used for self-programming library. 2. when boot swap is not used: set the option by tes to 000c0h to 000c3h, and the on-chip debug security ids to 000c4h to 000cdh. when boot swap is used: set the option bytes to 000c0h to 000c3h and 010c0h to 010c3h, and the on-chip debug security ids to 000c4h to 000cdh and 010c4h to 010cdh. 3. writing boot cluster 0 can be prohibited depending on the setting of security (see 23.7 security setting ). chapter 3 cpu architecture user?s manual u17854ej6v0ud 47 remark the flash memory is divided into blocks (one block = 2 kb). for the address values and block numbers, see table 3-1 correspondence between address va lues and block numbers in flash memory . block 00h block 01h block 1fh 2 kb 007ffh 00800h 00000h 00fffh 0f7ffh 0f800h fffffh chapter 3 cpu architecture user?s manual u17854ej6v0ud 48 correspondence between the address values and block numbers in the flash memory are shown below. table 3-1. correspondence between address values and block number s in flash memory address value block number address value block number address value block number address value block number 00000h to 007ffh 00h 10000h to 107ffh 20h 20000h to 207ffh 40h 30000h to 307ffh 60h 00800h to 00fffh 01h 10800h to 10fffh 21h 20800h to 20fffh 41h 30800h to 30fffh 61h 01000h to 017ffh 02h 11000h to 117ffh 22h 21000h to 217ffh 42h 31000h to 317ffh 62h 01800h to 01fffh 03h 11800h to 11fffh 23h 21800h to 21fffh 43h 31800h to 31fffh 63h 02000h to 027ffh 04h 12000h to 127ffh 24h 22000h to 227ffh 44h 32000h to 327ffh 64h 02800h to 02fffh 05h 12800h to 12fffh 25h 22800h to 22fffh 45h 32800h to 32fffh 65h 03000h to 037ffh 06h 13000h to 137ffh 26h 23000h to 237ffh 46h 33000h to 337ffh 66h 03800h to 03fffh 07h 13800h to 13fffh 27h 23800h to 23fffh 47h 33800h to 33fffh 67h 04000h to 047ffh 08h 14000h to 147ffh 28h 24000h to 247ffh 48h 34000h to 347ffh 68h 04800h to 04fffh 09h 14800h to 14fffh 29h 24800h to 24fffh 49h 34800h to 34fffh 69h 05000h to 057ffh 0ah 15000h to 157ffh 2ah 25000h to 257ffh 4ah 35000h to 357ffh 6ah 05800h to 05fffh 0bh 15800h to 15fffh 2bh 25800h to 25fffh 4bh 35800h to 35fffh 6bh 06000h to 067ffh 0ch 16000h to 167ffh 2ch 26000h to 267ffh 4ch 36000h to 367ffh 6ch 06800h to 06fffh 0dh 16800h to 16fffh 2dh 26800h to 26fffh 4dh 36800h to 36fffh 6dh 07000h to 077ffh 0eh 17000h to 177ffh 2eh 27000h to 277ffh 4eh 37000h to 377ffh 6eh 07800h to 07fffh 0fh 17800h to 17fffh 2fh 27800h to 27fffh 4fh 37800h to 37fffh 6fh 08000h to 087ffh 10h 18000h to 187ffh 30h 28000h to 287ffh 50h 38000h to 387ffh 70h 08800h to 08fffh 11h 18800h to 18fffh 31h 28800h to 28fffh 51h 38800h to 38fffh 71h 09000h to 097ffh 12h 19000h to 197ffh 32h 29000h to 297ffh 52h 39000h to 397ffh 72h 09800h to 09fffh 13h 19800h to 19fffh 33h 29800h to 29fffh 53h 39800h to 39fffh 73h 0a000h to 0a7ffh 14h 1a000h to 1a7ffh 34h 2a000h to 2a7ffh 54h 3a000h to 3a7ffh 74h 0a800h to 0afffh 15h 1a800h to 1afffh 35h 2a800h to 2afffh 55h 3a800h to 3afffh 75h 0b000h to 0b7ffh 16h 1b000h to 1b7ffh 36h 2b000h to 2b7ffh 56h 3b000h to 3b7ffh 76h 0b800h to 0bfffh 17h 1b800h to 1bfffh 37h 2b800h to 2bfffh 57h 3b800h to 3bfffh 77h 0c000h to 0c7ffh 18h 1c000h to 1c7ffh 38h 2c000h to 2c7ffh 58h 3c000h to 3c7ffh 78h 0c800h to 0cfffh 19h 1c800h to 1cfffh 39h 2c800h to 2cfffh 59h 3c800h to 3cfffh 79h 0d000h to 0d7ffh 1ah 1d000h to 1d7ffh 3ah 2d000h to 2d7ffh 5ah 3d000h to 3d7ffh 7ah 0d800h to 0dfffh 1bh 1d800h to 1dfffh 3bh 2d800h to 2dfffh 5bh 3d800h to 3dfffh 7bh 0e000h to 0e7ffh 1ch 1e000h to 1e7ffh 3ch 2e000h to 2e7ffh 5ch 3e000h to 3e7ffh 7ch 0e800h to 0efffh 1dh 1e800h to 1efffh 3dh 2e800h to 2efffh 5dh 3e800h to 3efffh 7dh 0f000h to 0f7ffh 1eh 1f000h to 1f7ffh 3eh 2f000h to 2f7ffh 5eh 3f000h to 3f7ffh 7eh 0f800h to 0ffffh 1fh 1f800h to 1ffffh 3fh 2f800h to 2ffffh 5fh 3f800h to 3ffffh 7fh remark pd78f1142: block numbers 00h to 1fh pd78f1143: block numbers 00h to 2fh pd78f1144: block numbers 00h to 3fh pd78f1145: block numbers 00h to 5fh pd78f1146: block numbers 00h to 7fh chapter 3 cpu architecture user?s manual u17854ej6v0ud 49 3.1.1 internal program memory space the internal program memory space stores the program and table data. normally, it is addressed with the program counter (pc). 78k0r/ke3 products incorporate internal rom (flash memory), as shown below. table 3-2. intern al rom capacity internal rom part number structure capacity pd78f1142 65536 8 bits (00000h to 0ffffh) pd78f1143 98303 8 bits (00000h to 17fffh) pd78f1144 131071 8 bits (00000h to 1ffffh) pd78f1145 196607 8 bits (00000h to 2ffffh) pd78f1146 flash memory 262143 8 bits (00000h to 3ffffh) the internal program memory space is divided into the following areas. (1) vector table area the 128-byte area 00000h to 0007fh is reserved as a ve ctor table area. the pr ogram start addresses for branch upon reset or generation of each interrupt r equest are stored in the vector table area. of the 16-bit address, the lower 8 bits are stored at ev en addresses and the higher 8 bits are stored at odd addresses. chapter 3 cpu architecture user?s manual u17854ej6v0ud 50 table 3-3. vector table vector table address interrupt source vector table address interrupt source 0002ah intiic0 00000h reset input, poc, lvi, wdt, trap 0002ch inttm00 00004h intwdti 0002eh inttm01 00006h intlvi 00030h inttm02 00008h intp0 00032h inttm03 0000ah intp1 00034h intad 0000ch intp2 00036h intrtc 0000eh intp3 00038h intrtci 00010h intp4 0003ah intkr 00012h intp5 00042h inttm04 00014h intst3 00044h inttm05 00016h intsr3 00046h inttm06 00018h intsre3 00048h inttm07 0001ah intdma0 0004ah intp6 0001ch intdma1 0004ch intp7 0001eh intst0/intcsi00 0004eh intp8 00020h intsr0 00050h intp9 00022h intsre0 00052h intp10 00024h intst1/intcsi10/intiic10 00054h intp11 00026h intsr1 0007eh brk 00028h intsre1 (2) callt instruction table area the 64-byte area 00080h to 000bfh can st ore the subroutine entry address of a 2-byte call instruction (callt). set the subroutine entry addr ess to a value in a range of 00000h to 0ffffh (becaus e an address code is of 2 bytes). to use the boot swap function, set a callt instruction table also at 01080h to 010bfh. (3) option byte area a 4-byte area of 000c0h to 000c3h can be used as an opt ion byte area. set the option byte at 010c0h to 010c3h when the boot swap is used. for details, see chapter 22 option byte . (4) on-chip debug security id setting area a 10-byte area of 000c4h to 000cdh and 010c4h to 010cdh can be used as an on-chip debug security id setting area. set the on-chip debug security id of 10 bytes at 000c4h to 000cdh when the boot swap is not used and at 000c4h to 000cdh and 010c4h to 010c dh when the boot swap is used. for details, see chapter 24 on-chip debug function . chapter 3 cpu architecture user?s manual u17854ej6v0ud 51 3.1.2 mirror area the pd78f1142 mirrors the data flash area of 00000h to 0ffffh, to f0000h to fffffh. the pd78f1143, 78f1144, 78f11 45, and 78f1146 mirrors t he data flash area of 00000h to 0ffffh or 10000h to 1ffffh, to f0000h to fffffh (the data flash area to be mirrored is set by the processor mode control register (pmc)). by reading data from f0000h to fffffh , the contents of the data flash c an be read with the shorter code. however, the data flash area is not mirrored to the sfr, extended sfr, ra m, and use prohibited areas. the mirror area can only be read and no instruction can be fetched from this area. the following show examples. example 1 pd78f1142 example 2 pd78f1146 (flash memory: 64 kb, ram: 4 kb) (flash memory: 256 kb, ram: 12 kb) setting maa = 0 setting maa = 1 flash memory flash memory flash memory 01000h 00fffh 00000h 0ef00h 0eeffh 10000h 0ffffh mirror f0000h effffh f0800h f07ffh f1000h f0fffh fef00h feeffh ffee0h ffedfh fff00h ffeffh fffffh special-function register ( sfr) 256 bytes general-purpose register 32 bytes ram 4 kb flash memory (same data as 01000h to 0eeffh) special-function register (2nd sfr) 2 kb reserved reserved remark maa: bit 0 of the processor mode control register (pmc). pmc register is described below. special-function register ( sfr) 256 bytes fffffh general-purpose register 32 bytes ffee0h ffedfh fff00h ffeffh ram 12 kb fcf00h fceffh flash memory (same data as 11000h to 1ceffh) f0800h f07ffh f1000h f0fffh reserved special-function register (2nd sfr) 2 kb f0000h effffh reserved mirror 40000h 3ffffh 00000h 1cf00h 1ceffh 11000h 10fffh flash memory flash memory flash memory chapter 3 cpu architecture user?s manual u17854ej6v0ud 52 ? processor mode control register (pmc) this register selects the flash memory s pace for mirroring to area from f0000h to fffffh. pmc can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to 00h. figure 3-6. format of configuration of processor mode control register (pmc) address: ffffeh after reset: 00h r/w symbol 7 6 5 4 3 2 1 <0> pmc 0 0 0 0 0 0 0 maa maa selection of flash memory space fo r mirroring to area from f0000h to fffffh 0 00000h to 0ffffh is mirrored to f0000h to fffffh 1 10000h to 1ffffh is mirrored to f0000h to fffffh cautions 1. set pmc only once during the initial settings prior to operating the dma controller. rewriting pmc other than during the init ial settings is prohibited. 2. after setting pmc, wait for at least one instruction and access the mirror area. 3. when the pd78f1142 is used, be sure to set bi t 0 (maa) of this register to 0. 3.1.3 internal data memory space 78k0r/ke3 products incorporate the following rams. table 3-4. internal ram capacity part number internal ram pd78f1142 4096 8 bits (fef00h to ffeffh) pd78f1143 6144 8 bits (fe700h to ffeffh) pd78f1144 8192 8 bits (fdf00h to ffeffh) pd78f1145 10240 8 bits (fd700h to ffeffh) pd78f1146 12288 8 bits (fcf00h to ffeffh) the 32-byte area ffee0h to ffeffh is assigned to four g eneral-purpose register banks consisting of eight 8-bit registers per bank. this area can be used as a program ar ea where instructions are written and executed. however, executing instructions is disabled in the general-purpose register. the internal high-speed ram can also be used as a stack memory. caution while using the self-programming function, the areas ffe20h to ffedfh and fcf00h to fd6ffh ( pd78f1146) cannot be used as stack memory. chapter 3 cpu architecture user?s manual u17854ej6v0ud 53 3.1.4 special function register (sfr) area on-chip peripheral hardware s pecial function registers (sfrs) are allo cated in the area fff00h to fffffh (see table 3-5 in 3.2.4 special function registers (sfrs) ). caution do not access addresses to which sfrs are not assigned. 3.1.5 extended special function register (2 nd sfr: 2nd special function register) area on-chip peripheral hardware special function registers (2 nd sfrs) are allocated in the area f0000h to f07ffh (see table 3-6 in 3.2.5 extended special function register s (2nd sfrs: 2nd special function registers) ). sfrs other than those in th e sfr area (fff00h to fffffh) are allocated to this area. an instruction that accesses the extended sfr area, however, is 1 byte l onger than an instruction t hat accesses the sfr area. caution do not access addresses to wh ich extended sfrs are not assigned. chapter 3 cpu architecture user?s manual u17854ej6v0ud 54 3.1.6 data memory addressing addressing refers to the method of specifying the address of the instruction to be ex ecuted next or the address of the register or memory relevant to the execution of instructions. several addressing modes are provided for addressing the memo ry relevant to the executi on of instructions for the 78k0r/ke3, based on operability and other considerations. for areas containing data memory in particular, special addressing methods designed for the functions of special function registers (sfr) and general-purpose registers are available for use. figures 3-7 to 3-11 show corre spondence between data memory and addressing. figure 3-7. correspondence between data memory and addressing ( pd78f1142) special function register (sfr) 256 bytes ram 4 kb general-purpose register 32 bytes flash memory 64 kb special function register (2nd sfr) 2 kb mirror 55.75 kb reserved reserved direct addressing register indirect addressing based addressing based indexed addressing short direct addressing sfr addressing register addressing 00000h 0ffffh 10000h effffh f0000h f07ffh f0800h f0fffh f1000h feeffh fef00h ffe1fh ffe20h ffedfh ffee0h ffeffh fff00h fff1fh fff20h fffffh chapter 3 cpu architecture user?s manual u17854ej6v0ud 55 figure 3-8. correspondence between data memory and addressing ( pd78f1143) special function register (sfr) 256 bytes ram 6 kb general-purpose register 32 bytes flash memory 96 kb special function register (2nd sfr) 2 kb mirror 53.75 kb reserved reserved direct addressing register indirect addressing based addressing based indexed addressing short direct addressing sfr addressing register addressing 00000h 17fffh 18000h effffh f0000h f07ffh f0800h f0fffh f1000h fe6ffh fe700h ffedfh ffee0h ffeffh fff00h fff1fh fff20h ffe1fh ffe20h fffffh chapter 3 cpu architecture user?s manual u17854ej6v0ud 56 figure 3-9. correspondence between data memory and addressing ( pd78f1144) special function register (sfr) 256 bytes ram 8 kb general-purpose register 32 bytes flash memory 128 kb special function register (2nd sfr) 2 kb mirror 51.75 kb reserved reserved direct addressing register indirect addressing based addressing based indexed addressing short direct addressing sfr addressing register addressing 00000h effffh f0000h f07ffh f0800h f0fffh f1000h fdeffh fdf00h ffedfh ffee0h ffeffh fff00h fff1fh fff20h ffe1fh ffe20h fffffh 1ffffh 20000h chapter 3 cpu architecture user?s manual u17854ej6v0ud 57 figure 3-10. correspondence between data memory and addressing ( pd78f1145) special function register (sfr) 256 bytes ram 10 kb general-purpose register 32 bytes flash memory 192 kb special function register (2nd sfr) 2 kb mirror 49.75 kb reserved reserved direct addressing register indirect addressing based addressing based indexed addressing short direct addressing sfr addressing register addressing 00000h effffh f0000h f07ffh f0800h f0fffh f1000h fd6ffh fd700h ffedfh ffee0h ffeffh fff00h fff1fh fff20h ffe1fh ffe20h fffffh 2ffffh 30000h chapter 3 cpu architecture user?s manual u17854ej6v0ud 58 figure 3-11. correspondence between data memory and addressing ( pd78f1146) special function register (sfr) 256 bytes ram 12 kb general-purpose register 32 bytes flash memory 256 kb special function register (2nd sfr) 2 kb mirror 47.75 kb reserved reserved direct addressing register indirect addressing based addressing based indexed addressing short direct addressing sfr addressing register addressing 00000h effffh f0000h f07ffh f0800h f0fffh f1000h fceffh fcf00h ffedfh ffee0h ffeffh fff00h fff1fh fff20h ffe1fh ffe20h fffffh 3ffffh 40000h note use of the area fcf00h to fd6ffh is prohibited when using the self-programming function. since this area is used for self-programming library. chapter 3 cpu architecture user?s manual u17854ej6v0ud 59 3.2 processor registers the 78k0r/ke3 products incorporate the following processor registers. 3.2.1 control registers the control registers control the program sequence, statuses and stack memory. the control registers consist of a program counter (pc), a program status word (psw) and a stack pointer (sp). (1) program counter (pc) the program counter is a 20-bit regist er that holds the address information of the next program to be executed. in normal operation, pc is automatically incremented acco rding to the number of byte s of the instruction to be fetched. when a branch instruction is execut ed, immediate data and regi ster contents are set. reset signal generation sets the reset vector table va lues at addresses 0000h and 0001h to the program counter. figure 3-12. format of program counter 19 pc 0 (2) program status word (psw) the program status word is an 8-bit r egister consisting of various flags set/reset by instruction execution. program status word contents are stored in the stack area upon interr upt request generation or push psw instruction execution and are re stored upon execution of the retb , reti and pop psw instructions. reset signal generation sets psw to 06h. figure 3-13. format of program status word ie z rbs1 ac rbs0 isp0 cy 70 isp1 psw (a) interrupt enable flag (ie) this flag controls the interrupt reques t acknowledge operations of the cpu. when 0, the ie flag is set to the interrupt disabled (di) state, and all maskable interrupt requests are disabled. when 1, the ie flag is set to the interrupt enabled (ei) state and interrupt request acknowledgment is controlled with an in-service priority flag (isp1, isp0 ), an interrupt mask flag for various interrupt sources, and a priority specification flag. the ie flag is reset (0) upon di instruction executi on or interrupt acknowledgment and is set (1) upon ei instruction execution. (b) zero flag (z) when the operation result is zero, this flag is se t (1). it is reset (0 ) in all other cases. (c) register bank select flags (rbs0, rbs1) these are 2-bit flags to select one of the four register banks. in these flags, the 2-bit information that indicates t he register bank selected by sel rbn instruction execution is stored. chapter 3 cpu architecture user?s manual u17854ej6v0ud 60 (d) auxiliary carry flag (ac) if the operation result has a carry from bit 3 or a borrow at bi t 3, this flag is set (1). it is reset (0) in all other cases. (e) in-service priority flags (isp1, isp0) this flag manages the priority of acknowledgeable maskabl e vectored interrupts. vectored interrupt requests specified lower than the value of i sp0 and isp1 by a priority specif ication flag register (prn0l, prn0h, prn1l, prn1h, prn2l, prn2h) (see 15.3 (3) ) can not be acknowledged. actual request acknowledgment is controlled by the interrupt enable flag (ie). remark n = 0, 1 (f) carry flag (cy) this flag stores overflow and underflow upon add/subtract instruction execution. it stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit operation instruction execution. (3) stack pointer (sp) this is a 16-bit register to hold the start address of the memory stack area. only the internal ram area can be set as the stack area. figure 3-14. format of stack pointer 15 sp sp15 sp14 sp13 sp12 sp11 sp10 sp9 sp8 sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 0 the sp is decremented ahead of write (save) to the stack memory and is incremented after read (restored) from the stack memory. each stack operation saves data as shown in figure 3-15. caution since reset signal genera tion makes the sp contents undefined, be sure to initialize the sp before using the stack. chapter 3 cpu architecture user?s manual u17854ej6v0ud 61 figure 3-15. data to be saved to stack memory pc7 to pc0 pc15 to pc8 pc19 to pc16 psw interrupt, brk instruction sp sp ? 4 sp ? 4 sp ? 3 sp ? 2 sp ? 1 sp call, callt instructions register pair lower register pair higher push rp instruction sp sp ? 2 sp ? 2 sp ? 1 sp (4-byte stack) (4-byte stack) pc7 to pc0 pc15 to pc8 pc19 to pc16 00h sp sp ? 4 sp ? 4 sp ? 3 sp ? 2 sp ? 1 sp 00h psw push rp instruction sp sp ? 2 sp ? 2 sp ? 1 sp 3.2.2 general-purpose registers general-purpose registers are mapped at particular addresses (ffee0h to ffeffh) of the data memory. the general-purpose registers consists of 4 bank s, each bank consisting of eight 8-bit r egisters (x, a, c, b, e, d, l, and h). each register can be used as an 8-bit register, and two 8-bit r egisters can also be used in a pair as a 16-bit register (ax, bc, de, and hl). these registers can be described in terms of function names (x, a, c, b, e, d, l, h, ax, bc, de, and hl) and absolute names (r0 to r7 and rp0 to rp3). register banks to be used for instructi on execution are set by the cpu control instruction (sel rbn). because of the 4-register bank configuration, an efficient program ca n be created by switching between a register for normal processing and a register for interrupts for each bank. caution it is prohibited to u se the general-purpose register (ff ee0h to ffeffh) space for fetching instructions or as a stack area. chapter 3 cpu architecture user?s manual u17854ej6v0ud 62 figure 3-16. configuration of general-purpose registers (a) function name register bank 0 register bank 1 register bank 2 register bank 3 ffeffh ffef8h ffee0h hl de bc ax h 15 0 7 0 l d e b c a x 16-bit processing 8-bit processing ffef0h ffee8h (b) absolute name register bank 0 register bank 1 register bank 2 register bank 3 ffeffh ffef8h ffee0h rp3 rp2 rp1 rp0 r7 15 0 7 0 r6 r5 r4 r3 r2 r1 r0 16-bit processing 8-bit processing ffef0h ffee8h chapter 3 cpu architecture user?s manual u17854ej6v0ud 63 3.2.3 es and cs registers the es register is used for data acce ss and the cs register is used to specify the higher address when a branch instruction is executed. the default value of the es register after reset is 0fh, and that of the cs register is 00h. figure 3-17. configuration of es and cs registers 0 0 0 0 es3 es2 es1 es0 70 es 6 5 4 3 21 0 0 0 0 cs3 cp2 cp1 cp0 70 cs 6 5 4 3 21 chapter 3 cpu architecture user?s manual u17854ej6v0ud 64 3.2.4 special function registers (sfrs) unlike a general-purpose register, each sfr has a special function. sfrs are allocated to the fff00h to fffffh area. sfrs can be manipulated like general-purpose regist ers, using operation, transfer, and bit manipulation instructions. the manipulable bit units, 1, 8, and 16, depe nd on the sfr type. each manipulation bit unit can be specified as follows. ? 1-bit manipulation describe the symbol reserved by the assembler for t he 1-bit manipulation instruction operand (sfr.bit). this manipulation can also be specified with an address. ? 8-bit manipulation describe the symbol reserved by the assembler for the 8-bit manipulation instruction operand (sfr). this manipulation can also be specified with an address. ? 16-bit manipulation describe the symbol reserved by the assembler for t he 16-bit manipulation instruction operand (sfrp). when specifying an address, describe an even address. table 3-5 gives a list of the sfrs. the meani ngs of items in the table are as follows. ? symbol symbol indicating the address of a special function register. it is a reserved word in the ra78k0r, and is defined as an sfr variable using the #pragma sfr di rective in the cc78k0r. when using the ra78k0r, id78k0r-qb, and sm+ for 78k0r, symbols c an be written as an instruction operand. ? r/w indicates whether the corresponding sfr can be read or written. r/w: read/write enable r: read only w: write only ? manipulable bit units ? ? indicates the manipulable bit unit (1, 8, or 16). ? ? ? indicates a bit unit for which manipulation is not possible. ? after reset indicates each register status upon reset signal generation. caution do not access addresses to wh ich extended sfrs are not assigned. remark for extended sfrs (2nd sfrs), see 3.2.5 extended special functi on registers (2nd sfrs: 2nd special function registers) . chapter 3 cpu architecture user?s manual u17854ej6v0ud 65 table 3-5. sfr list (1/5) manipulable bit range address special function register (sfr) name symbol r/w 1-bit 8-bit 16-bit after reset fff00h port register 0 p0 r/w ? 00h fff01h port register 1 p1 r/w ? 00h fff02h port register 2 p2 r/w ? 00h fff03h port register 3 p3 r/w ? 00h fff04h port register 4 p4 r/w ? 00h fff05h port register 5 p5 r/w ? 00h fff06h port register 6 p6 r/w ? 00h fff07h port register 7 p7 r/w ? 00h fff0ch port register 12 p12 r/w ? 00h fff0dh port register 13 p13 r/w ? 00h fff0eh port register 14 p14 r/w ? 00h fff10h txd0/ sio00 ? fff11h serial data register 00 ? sdr00 r/w ? ? 0000h fff12h rxd0 ? fff13h serial data register 01 ? sdr01 r/w ? ? 0000h fff14h txd3 ? fff15h serial data register 12 ? sdr12 r/w ? ? 0000h fff16h rxd3 ? fff17h serial data register 13 ? sdr13 r/w ? ? 0000h fff18h fff19h timer data register 00 tdr00 r/w ? ? 0000h fff1ah fff1bh timer data register 01 tdr01 r/w ? ? 0000h fff1eh 10-bit a/d conversion result register adcr r ? ? 0000h fff1fh 8-bit a/d conversion result register adcrh r ? ? 00h fff20h port mode register 0 pm0 r/w ? ffh fff21h port mode register 1 pm1 r/w ? ffh fff22h port mode register 2 pm2 r/w ? ffh fff23h port mode register 3 pm3 r/w ? ffh fff24h port mode register 4 pm4 r/w ? ffh fff25h port mode register 5 pm5 r/w ? ffh fff26h port mode register 6 pm6 r/w ? ffh fff27h port mode register 7 pm7 r/w ? ffh fff2ch port mode register 12 pm12 r/w ? ffh fff2eh port mode register 14 pm14 r/w ? ffh chapter 3 cpu architecture user?s manual u17854ej6v0ud 66 table 3-5. sfr list (2/5) manipulable bit range address special function register (sfr) name symbol r/w 1-bit 8-bit 16-bit after reset fff30h a/d converter mode register adm r/w ? 00h fff31h analog input channel specification register ads r/w ? 00h fff37h key return mode register krm r/w ? 00h fff38h external interrupt rising edge enable register 0 egp0 r/w ? 00h fff39h external interrupt falli ng edge enable register 0 egn0 r/w ? 00h fff3ah external interrupt rising edge enable register 1 egp1 r/w ? 00h fff3bh external interrupt falli ng edge enable register 1 egn1 r/w ? 00h fff3ch input switch control register isc r/w ? 00h fff3eh timer input select register 0 tis0 r/w ? 00h fff44h txd1/ sio10 ? fff45h serial data register 02 ? sdr02 r/w ? ? 0000h fff46h rxd1 ? fff47h serial data register 03 ? sdr03 r/w ? ? 0000h fff50h iic shift register 0 iic0 r/w ? ? 00h fff51h iic flag register 0 iicf0 r/w ? 00h fff52h iic control register 0 iicc0 r/w ? 00h fff53h iic slave address register 0 sva0 r/w ? ? 00h fff54h iic clock select register 0 iiccl0 r/w ? 00h fff55h iic function expansion register 0 iicx0 r/w ? 00h fff56h iic status register 0 iics0 r ? 00h fff64h fff65h timer data register 02 tdr02 r/w ? ? 0000h fff66h fff67h timer data register 03 tdr03 r/w ? ? 0000h fff68h fff69h timer data register 04 tdr04 r/w ? ? 0000h fff6ah fff6bh timer data register 05 tdr05 r/w ? ? 0000h fff6ch fff6dh timer data register 06 tdr06 r/w ? ? 0000h fff6eh fff6fh timer data register 07 tdr07 r/w ? ? 0000h chapter 3 cpu architecture user?s manual u17854ej6v0ud 67 table 3-5. sfr list (3/5) manipulable bit range address special function register (sfr) name symbol r/w 1-bit 8-bit 16-bit after reset fff90h fff91h sub-count register rsubc r ? ? 0000h fff92h second count register sec r/w ? ? 00h fff93h minute count register min r/w ? ? 00h fff94h hour count register hour r/w ? ? 12h note 1 fff95h week count register week r/w ? ? 00h fff96h day count register day r/w ? ? 01h fff97h month count register month r/w ? ? 01h fff98h year count register year r/w ? ? 00h fff99h watch error correction register subcud r/w ? ? 00h fff9ah alarm minute register alarmwm r/w ? ? 00h fff9bh alarm hour register alarmwh r/w ? ? 12h fff9ch alarm week register alarmww r/w ? ? 00h fff9dh real-time counter control register 0 rtcc0 r/w ? 00h fff9eh real-time counter control register 1 rtcc1 r/w ? 00h fff9fh real-time counter control register 2 rtcc2 r/w ? 00h fffa0h clock operation mode control register cmc r/w ? ? 00h fffa1h clock operation status control register csc r/w ? c0h fffa2h oscillation stabilization time counter status register ostc r ? 00h fffa3h oscillation stabilization time select register osts r/w ? ? 07h fffa4h system clock control register ckc r/w ? 09h fffa5h clock output select register 0 cks0 r/w ? 00h fffa6h clock output select register 1 cks1 r/w ? 00h fffa8h reset control flag register resf r ? ? 00h note 2 fffa9h low-voltage detection register lvim r/w ? 00h note 3 fffaah low-voltage detection level select register lvis r/w ? 0eh note 4 fffabh watchdog timer enable register wdte r/w ? ? 1a/9a note 5 fffach fffadh ? ttblh note 6 ? ? ? ? undefined fffaeh fffafh ? ttbll note 6 ? ? ? ? undefined notes 1. the value of this register is 00h if the ampm bit (bit 3 of the rtcc0 register) is set to 1 after reset. 2. the reset value of resf varies depending on the reset source. 3. the reset value of lvim varies depending on the reset source and the setting of the option byte. 4. the reset value of lvis varies depending on the reset source. 5. the reset value of wdte is determined by the setting of the option byte. 6. this sfr cannot be used by the us er, so do not operate it directly. chapter 3 cpu architecture user?s manual u17854ej6v0ud 68 table 3-5. sfr list (4/5) manipulable bit range address special function register (sfr) name symbol r/w 1-bit 8-bit 16-bit after reset fffb0h dma sfr address register 0 dsa0 r/w ? ? 00h fffb1h dma sfr address register 1 dsa1 r/w ? ? 00h fffb2h dma ram address register 0l dra0l r/w ? 00h fffb3h dma ram address register 0h dra0h dra0 r/w ? 00h fffb4h dma ram address register 1l dra1l r/w ? 00h fffb5h dma ram address register 1h dra1h dra1 r/w ? 00h fffb6h dma byte count register 0l dbc0l r/w ? 00h fffb7h dma byte count register 0h dbc0h dbc0 r/w ? 00h fffb8h dma byte count register 1l dbc1l r/w ? 00h fffb9h dma byte count register 1h dbc1h dbc1 r/w ? 00h fffbah dma mode control register 0 dmc0 r/w ? 00h fffbbh dma mode control register 1 dmc1 r/w ? 00h fffbch dma operation control register 0 drc0 r/w ? 00h fffbdh dma operation control register 1 drc1 r/w ? 00h fffbeh back ground event control register bectl r/w ? 00h fffc0h ? pfcmd note ? ? ? ? undefined fffc2h ? pfs note ? ? ? ? undefined fffc4h ? flpmc note ? ? ? ? undefined fffd0h interrupt request flag register 2l if2l r/w 00h fffd1h interrupt request flag register 2h if2h if2 r/w 00h fffd4h interrupt mask flag register 2l mk2l r/w ffh fffd5h interrupt mask flag register 2h mk2h mk2 r/w ffh fffd8h priority specificati on flag register 02l pr02l r/w ffh fffd9h priority specification flag register 02h pr02h pr02 r/w ffh fffdch priority specification flag register 12l pr12l r/w ffh fffddh priority specification flag register 12h pr12h pr12 r/w ffh fffe0h interrupt request flag register 0l if0l r/w 00h fffe1h interrupt request flag register 0h if0h if0 r/w 00h fffe2h interrupt request flag register 1l if1l r/w 00h fffe3h interrupt request flag register 1h if1h if1 r/w 00h fffe4h interrupt mask flag register 0l mk0l r/w ffh fffe5h interrupt mask flag register 0h mk0h mk0 r/w ffh fffe6h interrupt mask flag register 1l mk1l r/w ffh fffe7h interrupt mask flag register 1h mk1h mk1 r/w ffh fffe8h priority specificati on flag register 00l pr00l r/w ffh fffe9h priority specification flag register 00h pr00h pr00 r/w ffh fffeah priority specificati on flag register 01l pr01l r/w ffh fffebh priority specification flag register 01h pr01h pr01 r/w ffh fffech priority specification flag register 10l pr10l r/w ffh fffedh priority specification flag register 10h pr10h pr10 r/w ffh note do not directly operate this sfr, because it is to be used in the self programming library. chapter 3 cpu architecture user?s manual u17854ej6v0ud 69 table 3-5. sfr list (5/5) manipulable bit range address special function register (sfr) name symbol r/w 1-bit 8-bit 16-bit after reset fffeeh priority specificat ion flag register 11l pr11l ffh fffefh priority specification flag register 11h pr11h pr11 r/w ffh ffff0h ffff1h multiplication input data register a mula r/w ? ? 0000h ffff2h ffff3h multiplication input data register b mulb r/w ? ? 0000h ffff4h ffff5h higher multiplication result storage register muloh r ? ? 0000h ffff6h ffff7h lower multiplication result storage register mulol r ? ? 0000h ffffeh processor mode control register pmc r/w ? 00h remark for extended sfrs (2nd sfrs), see table 3-6 extended sfr (2nd sfr) list . chapter 3 cpu architecture user?s manual u17854ej6v0ud 70 3.2.5 extended special function registers (2nd sfrs: 2nd special function registers) unlike a general-purpose register, each extended sfr (2nd sfr) has a special function. extended sfrs are allocated to the f0 000h to f07ffh area. sfrs other than those in the sfr area (fff00h to fffffh) are allocated to this area. an instruction that accesse s the extended sfr area, however, is 1 byte longer than an instruction that accesses the sfr area. extended sfrs can be manipulated like general-purpose regist ers, using operation, trans fer, and bit manipulation instructions. the manipulable bit units, 1, 8, and 16, depe nd on the sfr type. each manipulation bit unit can be specified as follows. ? 1-bit manipulation describe the symbol reserved by the assembler for the 1- bit manipulation instruction operand (!addr16.bit). this manipulation can also be specified with an address. ? 8-bit manipulation describe the symbol reserved by the assembler for t he 8-bit manipulation instruction operand (!addr16). this manipulation can also be specified with an address. ? 16-bit manipulation describe the symbol reserved by the assembler for the 16-bit manipulation instruction operand (!addr16). when specifying an address, describe an even address. table 3-6 gives a list of the ext ended sfrs. the meanings of item s in the table are as follows. ? symbol symbol indicating the address of an extended sfr. it is a reserved word in the ra78k0r, and is defined as an sfr variable using the #pragma sfr di rective in the cc78k0r. when using the ra78k0r, id78k0r-qb, and sm+ for 78k0r, symbols can be written as an instruction operand. ? r/w indicates whether the corresponding extended sfr can be read or written. r/w: read/write enable r: read only w: write only ? manipulable bit units ? ? indicates the manipulable bit unit (1, 8, or 16). ? ? ? indicates a bit unit for which manipulation is not possible. ? after reset indicates each register status upon reset signal generation. caution do not access addresses to wh ich extended sfrs are not assigned. remark for sfrs in the sfr area, see 3.2.4 special functi on registers (sfrs) . chapter 3 cpu architecture user?s manual u17854ej6v0ud 71 table 3-6. extended sfr (2nd sfr) list (1/4) manipulable bit range address special function regist er (sfr) name symbol r/w 1-bit 8-bit 16-bit after reset f0017h a/d port configuration register adpc r/w ? ? 10h f0030h pull-up resistor option register 0 pu0 r/w ? 00h f0031h pull-up resistor option register 1 pu1 r/w ? 00h f0033h pull-up resistor option register 3 pu3 r/w ? 00h f0034h pull-up resistor option register 4 pu4 r/w ? 00h f0035h pull-up resistor option register 5 pu5 r/w ? 00h f0037h pull-up resistor option register 7 pu7 r/w ? 00h f003ch pull-up resistor option register 12 pu12 r/w ? 00h f003eh pull-up resistor option register 14 pu14 r/w ? 00h f0040h port input mode register 0 pim0 r/w ? 00h f0050h port output mode register 0 pom0 r/w ? 00h f0060h noise filter enable register 0 nfen0 r/w ? 00h f0061h noise filter enable register 1 nfen1 r/w ? 00h f00f0h peripheral enable register 0 per0 r/w ? 00h f00f2h internal high-speed oscilla tor trimming register hiotrm r/w ? ? 10h f00f3h operation speed mode control register osmc r/w ? ? 00h f00f4h regulator mode control register rmc r/w ? ? 00h f00feh bcd adjust result register bcdadj r ? ? undefined f0100h ssr00l ? f0101h serial status register 00 ? ssr00 r ? ? 0000h f0102h ssr01l ? f0103h serial status register 01 ? ssr01 r ? ? 0000h f0104h ssr02l ? f0105h serial status register 02 ? ssr02 r ? ? 0000h f0106h ssr03l ? f0107h serial status register 03 ? ssr03 r ? ? 0000h f0108h sir00l ? f0109h serial flag clear trigger register 00 ? sir00 r/w ? ? 0000h f010ah sir01l ? f010bh serial flag clear trigger register 01 ? sir01 r/w ? ? 0000h f010ch sir02l ? f010dh serial flag clear trigger register 02 ? sir02 r/w ? ? 0000h f010eh sir03l ? f010fh serial flag clear trigger register 03 ? sir03 r/w ? ? 0000h f0110h f0111h serial mode register 00 smr00 r/w ? ? 0020h f0112h f0113h serial mode register 01 smr01 r/w ? ? 0020h f0114h f0115h serial mode register 02 smr02 r/w ? ? 0020h f0116h f0117h serial mode register 03 smr03 r/w ? ? 0020h chapter 3 cpu architecture user?s manual u17854ej6v0ud 72 table 3-6. extended sfr (2nd sfr) list (2/4) manipulable bit range address special function regist er (sfr) name symbol r/w 1-bit 8-bit 16-bit after reset f0118h f0119h serial communication operation se tting register 00 scr00 r/w ? ? 0087h f011ah f011bh serial communication operation se tting register 01 scr01 r/w ? ? 0087h f011ch f011dh serial communication operation se tting register 02 scr02 r/w ? ? 0087h f011eh f011fh serial communication operation se tting register 03 scr03 r/w ? ? 0087h f0120h se0l f0121h serial channel enable status register 0 ? se0 r ? ? 0000h f0122h ss0l f0123h serial channel start register 0 ? ss0 r/w ? ? 0000h f0124h st0l f0125h serial channel stop register 0 ? st0 r/w ? ? 0000h f0126h sps0l ? f0127h serial clock select register 0 ? sps0 r/w ? ? 0000h f0128h f0129h serial output register 0 so0 r/w ? ? 0f0fh f012ah soe0l f012bh serial output enable register 0 ? soe0 r/w ? ? 0000h f0134h sol0l ? f0135h serial output level register 0 ? sol0 r/w ? ? 0000h f0144h ssr12l ? f0145h serial status register 12 ? ssr12 r ? ? 0000h f0146h ssr13l ? f0147h serial status register 13 ? ssr13 r ? ? 0000h f014ch sir12l ? f014dh serial flag clear trigger register 12 ? sir12 r/w ? ? 0000h f014eh sir13l ? f014fh serial flag clear trigger register 13 ? sir13 r/w ? ? 0000h f0154h f0155h serial mode register 12 smr12 r/w ? ? 0020h f0156h f0157h serial mode register 13 smr13 r/w ? ? 0020h f015ch f015dh serial communication operation se tting register 12 scr12 r/w ? ? 0087h f015eh f015fh serial communication operation se tting register 13 scr13 r/w ? ? 0087h f0160h se1l f0161h serial channel enable status register 1 ? se1 r ? ? 0000h f0162h ss1l f0163h serial channel start register 1 ? ss1 r/w ? ? 0000h chapter 3 cpu architecture user?s manual u17854ej6v0ud 73 table 3-6. extended sfr (2nd sfr) list (3/4) manipulable bit range address special function regist er (sfr) name symbol r/w 1-bit 8-bit 16-bit after reset f0164h st1l f0165h serial channel stop register 1 ? st1 r/w ? ? 0000h f0166h sps1l ? f0167h serial clock select register 1 ? sps1 r/w ? ? 0000h f0168h f0169h serial output register 1 so1 r/w ? ? 0f0fh f016ah soe1l f016bh serial output enable register 1 ? soe1 r/w ? ? 0000h f0174h sol1l ? f0175h serial output level register 1 ? sol1 r/w ? ? 0000h f0180h f0181h timer counter register 00 tcr00 r ? ? ffffh f0182h f0183h timer counter register 01 tcr01 r ? ? ffffh f0184h f0185h timer counter register 02 tcr02 r ? ? ffffh f0186h f0187h timer counter register 03 tcr03 r ? ? ffffh f0188h f0189h timer counter register 04 tcr04 r ? ? ffffh f018ah f018bh timer counter register 05 tcr05 r ? ? ffffh f018ch f018dh timer counter register 06 tcr06 r ? ? ffffh f018eh f018fh timer counter register 07 tcr07 r ? ? ffffh f0190h f0191h timer mode register 00 tmr00 r/w ? ? 0000h f0192h f0193h timer mode register 01 tmr01 r/w ? ? 0000h f0194h f0195h timer mode register 02 tmr02 r/w ? ? 0000h f0196h f0197h timer mode register 03 tmr03 r/w ? ? 0000h f0198h f0199h timer mode register 04 tmr04 r/w ? ? 0000h f019ah f019bh timer mode register 05 tmr05 r/w ? ? 0000h f019ch f019dh timer mode register 06 tmr06 r/w ? ? 0000h f019eh f019fh timer mode register 07 tmr07 r/w ? ? 0000h chapter 3 cpu architecture user?s manual u17854ej6v0ud 74 table 3-6. extended sfr (2nd sfr) list (4/4) manipulable bit range address special function regist er (sfr) name symbol r/w 1-bit 8-bit 16-bit after reset f01a0h tsr00l ? f01a1h timer status register 00 ? tsr00 r ? ? 0000h f01a2h tsr01l ? f01a3h timer status register 01 ? tsr01 r ? ? 0000h f01a4h tsr02l ? f01a5h timer status register 02 ? tsr02 r ? ? 0000h f01a6h tsr03l ? f01a7h timer status register 03 ? tsr03 r ? ? 0000h f01a8h tsr04l ? f01a9h timer status register 04 ? tsr04 r ? ? 0000h f01aah tsr05l ? f01abh timer status register 05 ? tsr05 r ? ? 0000h f01ach tsr06l ? f01adh timer status register 06 ? tsr06 r ? ? 0000h f01aeh tsr07l ? f01afh timer status register 07 ? tsr07 r ? ? 0000h f01b0h te0l f01b1h timer channel enable status register 0 ? te0 r ? ? 0000h f01b2h ts0l f01b3h timer channel start register 0 ? ts0 r/w ? ? 0000h f01b4h tt0l f01b5h timer channel stop register 0 ? tt0 r/w ? ? 0000h f01b6h tps0l ? f01b7h timer clock select register 0 ? tps0 r/w ? ? 0000h f01b8h to0l ? f01b9h timer output register 0 ? to0 r/w ? ? 0000h f01bah toe0l f01bbh timer output enable register 0 ? toe0 r/w ? ? 0000h f01bch tol0l ? f01bdh timer output level register 0 ? tol0 r/w ? ? 0000h f01beh tom0l ? f01bfh timer output mode register 0 ? tom0 r/w ? ? 0000h remark for sfrs in the sfr area, see table 3-5 sfr list . chapter 3 cpu architecture user?s manual u17854ej6v0ud 75 3.3 instruction address addressing 3.3.1 relative addressing [function] relative addressing stores in the progr am counter (pc) the result of adding a displacement value included in the instruction word (signed complement data: ? 128 to +127 or ? 32768 to +32767) to the program counter (pc)?s value (the start address of the next instruction), and s pecifies the program address to be used as the branch destination. relative addressing is applied only to branch instructions. figure 3-18. outline of relative addressing op code pc displace 8/16 bits 3.3.2 immediate addressing [function] immediate addressing stores immediate da ta of the instruction word in t he program counter, and specifies the program address to be used as the branch destination. for immediate addressing, call !!addr20 or br !!addr20 is used to specify 20-bit addresses and call !addr16 or br !addr16 is used to specify 16-bit addresses. 0000 is set to the higher 4 bits when specifying 16-bit addresses. figure 3-19. example of call !!addr20/br !!addr20 op code pc low addr. high addr. seg addr. figure 3-20. example of call !addr16/br !addr16 op code pc s low addr. high addr. pc pc h pc l 0000 chapter 3 cpu architecture user?s manual u17854ej6v0ud 76 3.3.3 table indirect addressing [function] table indirect addressing specifies a table address in the callt table area (0080h to 00bfh) with the 5-bit immediate data in the instruction word, stores the cont ents at that table address a nd the next address in the program counter (pc) as 16-bit data, and specifies the program address. table indirect addressing is applied only for callt instructions. in the 78k0r microcontrollers, branc hing is enabled only to the 64 kb space from 00000h to 0ffffh. figure 3-21. outline of table indirect addressing low addr. high addr. 0 0000 op code 00000000 10 table address pc s pc pc h pc l memory chapter 3 cpu architecture user?s manual u17854ej6v0ud 77 3.3.4 register direct addressing [function] register direct addressing stores in the program counter (pc) the cont ents of a general-purpose register pair (ax/bc/de/hl) and cs register of the current register bank specified with t he instruction word as 20-bit data, and specifies the program address. regi ster direct addressing can be applied only to the call ax, bc, de, hl, and br ax instructions. figure 3-22. outline of register direct addressing op code pc s pc pc h pc l cs rp chapter 3 cpu architecture user?s manual u17854ej6v0ud 78 3.4 addressing for processing data addresses 3.4.1 implied addressing [function] instructions for accessing registers (such as accumulators ) that have special functions are directly specified with the instruction word, without using any register specification field in the instruction word. [operand format] because implied addressing can be automatically empl oyed with an instruction, no particular operand format is necessary. implied addressing can be applied only to mulu x. figure 3-23. outline of implied addressing a register op code memory 3.4.2 register addressing [function] register addressing accesses a general-purpose register as an operand. the instruction word of 3-bit long is used to select an 8-bit register and the instruction word of 2-bit long is used to select a 16-bit register. [operand format] identifier description r x, a, c, b, e, d, l, h rp ax, bc, de, hl figure 3-24. outline of register addressing register op code memory chapter 3 cpu architecture user?s manual u17854ej6v0ud 79 3.4.3 direct addressing [function] direct addressing uses immediate data in the instructio n word as an operand address to directly specify the target address. [operand format] identifier description addr16 label or 16-bit immediate dat a (only the space from f0000h to fffffh is specifiable) es: addr16 label or 16-bit immediate data (higher 4- bit addresses are specified by the es register) figure 3-25. example of addr16 target memory op code memory low addr. high addr. fffffh f0000h figure 3-26. example of es:addr16 op code memory low addr. high addr. fffffh 00000h target memory es chapter 3 cpu architecture user?s manual u17854ej6v0ud 80 3.4.4 short direct addressing [function] short direct addressing directly specif ies the target addresses using 8-bit data in the instruction word. this type of addressing is applied only to the space from ffe20h to fff1fh. [operand format] identifier description saddr label, ffe20h to fff1fh immediate data, or 0fe20h to 0ff1fh immediate data (only the space from ffe20h to fff1fh is specifiable) saddrp label, ffe20h to fff1fh immediate data, or 0f e20h to 0ff1fh immediate data (even address only) (only the space from ffe20h to fff1fh is specifiable) figure 3-27. outline of short direct addressing op code memory saddr fff1fh ffe20h saddr remark saddr and saddrp are used to describe the values of addresses fe20h to ff1fh with 16-bit immediate data (higher 4 bits of actual address ar e omitted), and the values of addresses ffe20h to fff1fh with 20-bit immediate data. regardless of whether saddr or saddrp is used, addresses within the space from ffe20h to fff1fh are specified for the memory. chapter 3 cpu architecture user?s manual u17854ej6v0ud 81 3.4.5 sfr addressing [function] sfr addressing directly specifies the target sfr addresses us ing 8-bit data in the instruction word. this type of addressing is applied only to t he space from fff00h to fffffh. [operand format] identifier description sfr sfr name sfrp 16-bit-manipulatable sf r name (even address only) figure 3-28. outline of sfr addressing op code memory sfr fffffh fff00h sfr chapter 3 cpu architecture user?s manual u17854ej6v0ud 82 3.4.6 register indirect addressing [function] register indirect addressing directly specifies the target addresses using the contents of t he register pair specified with the instruction word as an operand address. [operand format] identifier description ? [de], [hl] (only the space from f0000h to fffffh is specifiable) ? es:[de], es:[hl] (higher 4-bit addresses are specified by the es register) figure 3-29. example of [de], [hl] target memory op code memory rp fffffh f0000h figure 3-30. example of es:[de], es:[hl] op code memory fffffh 00000h target memory es rp chapter 3 cpu architecture user?s manual u17854ej6v0ud 83 3.4.7 based addressing [function] based addressing uses the contents of a register pair specifi ed with the instruction word as a base address, and 8-bit immediate data or 16-bit immediate data as offset dat a. the sum of these val ues is used to specify the target address. [operand format] identifier description ? [hl + byte], [de + byte], [sp + byte] (only the space from f0000h to fffffh is specifiable) ? word[b], word[c] (only the space from f0000h to fffffh is specifiable) ? word[bc] (only the space from f0 000h to fffffh is specifiable) ? es:[hl + byte], es:[de + byte] (higher 4-bit addresses are specified by the es register) ? es:word[b], es:word[c] (higher 4-bit addresses are specified by the es register) ? es:word[bc] (higher 4-bit addresses are specified by the es register) figure 3-31. example of [sp+byte] target memory op code memory byte fffffh f0000h sp chapter 3 cpu architecture user?s manual u17854ej6v0ud 84 figure 3-32. example of [hl + byte], [de + byte] target memory op code memory byte fffffh f0000h rp (hl/de) figure 3-33. example of word[b], word[c] target memory memory fffffh f0000h r (b/c) op code low addr. high addr. figure 3-34. example of word[bc] target memory memory fffffh f0000h rp (bc) op code low addr. high addr. chapter 3 cpu architecture user?s manual u17854ej6v0ud 85 figure 3-35. example of es :[hl + byte], es:[de + byte] op code byte rp (hl/de) memory fffffh 00000h target memory es figure 3-36. example of es:word[b], es:word[c] r (b/c) memory fffffh 00000h target memory es op code low addr. high addr. figure 3-37. example of es:word[bc] rp (bc) memory fffffh 00000h target memory es op code low addr. high addr. chapter 3 cpu architecture user?s manual u17854ej6v0ud 86 3.4.8 based indexed addressing [function] based indexed addressing uses the content s of a register pair specified with the instruction word as the base address, and the content of the b regist er or c register similarly specified with the instruction word as offset address. the sum of these values is used to specify the target address. [operand format] identifier description ? [hl+b], [hl+c] (only the space from f0000h to fffffh is specifiable) ? es:[hl+b], es:[hl+c] (higher 4-bit addres ses are specified by the es register) figure 3-38. example of [hl+b], [hl+c] target memory memory fffffh f0000h r (b/c) rp (hl) op code figure 3-39. example of es:[hl+b], es:[hl+c] r (b/c) op code rp (hl) es memory fffffh 00000h target memory chapter 3 cpu architecture user?s manual u17854ej6v0ud 87 3.4.9 stack addressing [function] the stack area is indirectly addressed with the stack pointer (sp) contents. this addressing is automatically employed when the push, pop, subrout ine call, and return instructions are executed or the register is saved/restored upon generation of an interrupt request. stack addressing is applied only to the internal ram area. [operand format] identifier description ? push ax/bc/de/hl pop ax/bc/de/hl call/callt ret brk retb (interrupt request generated) reti user?s manual u17854ej6v0ud 88 chapter 4 port functions 4.1 port functions there are three types of pi n i/o buffer power supplies: av ref , ev dd , and v dd . the relationship between these power supplies and the pins is shown below. table 4-1. pin i/o buffer power supplies power supply corresponding pins av ref p20 to p27 ev dd ? port pins other than p20 to p27 and p121 to p124 ? reset pin and flmd0 pin v dd ? p121 to p124 ? pins other than port pins (except reset pin and flmd0 pin ) 78k0r/ke3 products are provi ded with the ports shown in figure 4-1, whic h enable variety of control operations. the functions of each port are shown in table 4-2. in addition to the func tion as digital i/o ports, these ports have several alternate f unctions. for details of the alternate functions, see chapter 2 pin functions . figure 4-1. port types p00 p06 p10 p17 p30 p31 p20 p27 p40 p43 p50 p55 p130 p140 p141 p60 p63 p70 p77 p120 p124 port 0 port 1 port 2 port 3 port 4 port 5 port 6 port 7 port 12 port 13 port 14 chapter 4 port functions user?s manual u17854ej6v0ud 89 table 4-2. port functions (1/2) function name i/o function after reset alternate function p00 ti00 p01 to00 p02 so10/txd1 p03 si10/rxd1/sda10 p04 sck10/scl10 p05 ti05/to05 p06 i/o port 0. 7-bit i/o port. input of p03 and p04 can be set to ttl input buffer. output of p02 to p04 can be set to n-ch open-drain output (v dd tolerance). input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port ti06/to06 p10 sck00 p11 si00/rxd0 p12 so00/txd0 p13 txd3 p14 rxd3 p15 rtcdiv/rtccl p16 ti01/to01/intp5 p17 i/o port 1. 8-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port ti02/to02 p20 to p27 i/o port 2. 8-bit i/o port. input/output can be specified in 1-bit units. digital input port ani0 to ani7 p30 rtc1hz/intp3 p31 i/o port 3. 2-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port ti03/to03/intp4 p40 note tool0 p41 tool1 p42 ti04/to04 p43 i/o port 4. 4-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port ? p50 intp1 p51 intp2 p52 ? p53 ? p54 ? p55 i/o port 5. 6-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port ? note if on-chip debugging is enabled by using an option by te, be sure to pull up the p40/tool0 pin externally (see caution in 2.2.5 p40 to p43 (port 4) ). chapter 4 port functions user?s manual u17854ej6v0ud 90 table 4-2. port functions (2/2) function name i/o function after reset alternate function p60 scl0 p61 sda0 p62 ? p63 i/o port 6. 4-bit i/o port. output of p60 to p63 can be set to n-ch open-drain output (6 v tolerance). input/output can be specified in 1-bit units. input port ? p70 to p73 kr0 to kr3 p74 to p77 i/o port 7. 8-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port kr4/intp8 to kr7/intp11 p120 i/o intp0/exlvi p121 x1 p122 x2/exclk p123 xt1 p124 input port 12. 1-bit i/o port and 4-bit input port. for only p120, use of an on-chip pull-up resistor can be specified by a software setting. input port xt2 p130 output port 13. 1-bit output port. output port ? p140 pclbuz0/intp6 p141 i/o port 14. 2-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port pclbuz1/intp7 chapter 4 port functions user?s manual u17854ej6v0ud 91 4.2 port configuration ports include the following hardware. table 4-3. port configuration item configuration control registers port mode registers (pm0 to pm7, pm12, pm14) port registers (p0 to p7, p12 to p14) pull-up resistor option registers (pu0, pu1, pu3 to pu5, pu7, pu12, pu14) port input mode registers (pim0) port output mode registers (pom0) a/d port configuration register (adpc) port total: 55 (cmos i/o: 46, cmos input: 4, cmos output: 1, n-ch open drain i/o: 4) pull-up resistor total: 38 chapter 4 port functions user?s manual u17854ej6v0ud 92 4.2.1 port 0 port 0 is a 7-bit i/o port with an output latch. port 0 can be set to the input mode or output mode in 1-bit units using port mode register 0 (pm0). when the p00 to p06 pi ns are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pu ll-up resistor option register 0 (pu0). input to the p03 and p04 pins can be specified through a normal input buffer or a ttl input buffer in 1-bit units using port input mode register 0 (pim0). output from the p02 to p04 pins can be specified as n-ch open-drain output (v dd tolerance) in 1-bit units using port output mode register 0 (pom0). this port can also be used for timer i/o , serial interface data i/o, and clock i/o. reset signal generation sets port 0 to input mode. figures 4-2 to 4-6 show block diagrams of port 0. cautions 1. to use p01/to00, p05/ ti05/to05, or p06/ti06/to06 as a genera l-purpose port, set bits 0, 5, and 6 (to00, to05, to06) of timer output register 0 (to0) and bits 0, 5, and 6 (toe00, toe05, toe06) of timer output enable register 0 (toe 0) to ?0?, which is the same as their default status setting. 2. to use p02/so10/txd1, p0 3/si10/rxd1/sda10 or p04/sck10/scl10 as a general-purpose port, note the serial array unit 0 setting. for deta ils, refer to table 11-7 relationship between register settings and pins (channel 2 of un it 0: csi10, uart1 transmission, iic10) and table 11-8 relationship between register setti ngs and pins (channel 3 of unit 0: uart1 reception). chapter 4 port functions user?s manual u17854ej6v0ud 93 figure 4-2. block diagram of p00 p00/ti00 wr pu rd wr port wr pm pu00 alternate function output latch (p00) pm00 ev dd p-ch selector internal bus pu0 pm0 p0 p0: port register 0 pu0: pull-up resistor option register 0 pm0: port mode register 0 rd: read signal wr : write signal chapter 4 port functions user?s manual u17854ej6v0ud 94 figure 4-3. block diagram of p01 p01/to00 wr pu rd wr port wr pm pu01 pm01 ev dd p-ch pu0 pm0 p0 selector alternate function output latch (p01) internal bus p0: port register 0 pu0: pull-up resistor option register 0 pm0: port mode register 0 rd: read signal wr : write signal chapter 4 port functions user?s manual u17854ej6v0ud 95 figure 4-4. block diagram of p02 p02/so10/txd1 wr pu rd wr port wr pm pu02 pm02 ev dd p-ch pu0 pm0 p0 pom02 pom0 wr pom selector internal bus output latch (p02) alternate function p0: port register 0 pu0: pull-up resistor option register 0 pm0: port mode register 0 pom0: port output mode register 0 rd: read signal wr : write signal chapter 4 port functions user?s manual u17854ej6v0ud 96 figure 4-5. block diagram of p03 and p04 p03/si10/rxd1/sda10, p04/sck10/scl10 wr pu rd wr port pu03, pu04 ev dd p-ch pu0 p0 wr pm pm0 pom03, pom04 pom0 wr pom pm03, pm04 cmos ttl pim0 pim03, pim04 wr pim alternate function output latch (p03, p04) alternate function selector internal bus p0: port register 0 pu0: pull-up resistor option register 0 pm0: port mode register 0 pim0: port input mode register 0 pom0: port output mode register 0 rd: read signal wr : write signal chapter 4 port functions user?s manual u17854ej6v0ud 97 figure 4-6. block diagram of p05 and p06 p05/ti05/to05, p06/ti06/to06 wr pu rd wr port wr pm ev dd p-ch pu0 pm0 p0 pm05, pm06 pu05, pu06 alternate function output latch (p05, p06) selector internal bus alternate function p0: port register 0 pu0: pull-up resistor option register 0 pm0: port mode register 0 rd: read signal wr : write signal chapter 4 port functions user?s manual u17854ej6v0ud 98 4.2.2 port 1 port 1 is an 8-bit i/o port with an output latch. port 1 can be set to the input mode or output mode in 1-bit units using port mode register 1 (pm1). when the p10 to p17 pi ns are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 1 (pu1). this port can also be used for external interrupt request input, serial in terface data i/o, cl ock i/o, timer i/o, and real-time counter clock output. reset signal generation sets port 1 to input mode. figures 4-7 to 4-11 show block diagrams of port 1. cautions 1. to use p10/sck00, p11/si00/rxd0, p12/ so00/txd0, p13/txd3 or p14/rxd3 as a general- purpose port, note the serial array unit setting. for details, refer to table 11-5 relationship between register settings and pi ns (channel 0 of unit 0: cs i00, uart0 transmission), table 11-6 relationship between register settings and pins (channel 1 of unit 0: uart0 reception) , table 11-9 relationship between regist er settings and pins (channel 2 of unit 1: uart3 transmission), and table 11-10 relations hip between register settings and pins (channel 3 of unit 1: uart3 reception). 2. to use p16/ti01/to01/intp5 or p17/ti02/to02 as a general-purpose port, set bits 1 and 2 (to01, to02) of timer output regi ster 0 (to0) and bits 1 and 2 (toe01, toe02) of timer output enable register 0 (toe0) to ?0?, which is the same as their default status setting. 3. to use p15/rtcdiv/ rtccl as a general-purpose port, set bit 4 (rcloe0) of real-time counter control register 0 (rtcc0) and bit 6 (rcl oe2) of real-time counter control register 2 (rtcc2) to ?0?, which is the same as their default status setting. chapter 4 port functions user?s manual u17854ej6v0ud 99 figure 4-7. block diagram of p10 p10/sck00 wr pu rd wr port wr pm pu10 pm10 ev dd p-ch pu1 pm1 p1 alternate function output latch (p10) selector internal bus alternate function p1: port register 1 pu1: pull-up resistor option register 1 pm1: port mode register 1 rd: read signal wr : write signal chapter 4 port functions user?s manual u17854ej6v0ud 100 figure 4-8. block diagram of p11 and p14 p11/si00/rxd0, p14/rxd3 wr pu rd wr port wr pm pu11, pu14 pm11, pm14 ev dd p-ch pu1 pm1 p1 output latch (p11, p14) selector internal bus alternate function p1: port register 1 pu1: pull-up resistor option register 1 pm1: port mode register 1 rd: read signal wr : write signal chapter 4 port functions user?s manual u17854ej6v0ud 101 figure 4-9. block diagram of p12 and p13 p12/so00/txd0, p13/txd3 wr pu rd wr port wr pm pu12, pu13 pm12, pm13 ev dd p-ch pu1 pm1 p1 alternate function output latch (p12, p13) selector internal bus p1: port register 1 pu1: pull-up resistor option register 1 pm1: port mode register 1 rd: read signal wr : write signal chapter 4 port functions user?s manual u17854ej6v0ud 102 figure 4-10. blo ck diagram of p15 p15/rtcdiv/rtccl wr pu rd wr port wr pm pu15 pm15 ev dd p-ch pu1 pm1 p1 output latch (p15) selector internal bus alternate function p1: port register 1 pu1: pull-up resistor option register 1 pm1: port mode register 1 rd: read signal wr : write signal chapter 4 port functions user?s manual u17854ej6v0ud 103 figure 4-11. block diagram of p16 and p17 p16/ti01/to01/intp5, p17/ti02/to02 wr pu rd wr port wr pm pu16, pu17 pm16, pm17 ev dd p-ch pm1 pu1 p1 alternate function output latch (p16, p17) selector internal bus alternate function p1: port register 1 pu1: pull-up resistor option register 1 pm1: port mode register 1 rd: read signal wr : write signal chapter 4 port functions user?s manual u17854ej6v0ud 104 4.2.3 port 2 port 2 is an 8-bit i/o port with an output latch. port 2 can be set to the input mode or output mode in 1-bit units using port mode register 2 (pm2). this port can also be used for a/d converter analog input. to use p20/ani0 to p27/ani7 as di gital input pins, set them in the di gital i/o mode by using the a/d port configuration register (adpc) and in the input mode by using pm2. use t hese pins starting from the lower bit. to use p20/ani0 to p27/ani7 as digi tal output pins, set them in the di gital i/o mode by using adpc and in the output mode by using pm2. to use p20/ani0 to p27/ani7 as analog input pins, se t them in the analog input mode by using the a/d port configuration register (adpc) and in the input mode by using pm2. use t hese pins starting from the upper bit. table 4-4. setting functions of p20/ani0 to p27/ani7 pins adpc pm2 ads p20/ani0 to p27/ani7 pins input mode ? digital input digital i/o selection output mode ? digital output selects ani. analog input (to be converted) input mode does not select ani. analog input (not to be converted) selects ani. analog input selection output mode does not select ani. setting prohibited all p20/ani0 to p27/ani7 are set in the digi tal input mode when the reset signal is generated. figure 4-12 shows a block diagram of port 2. caution make the av ref pin the same potential as the v dd pin when port 2 is used as a digital port. chapter 4 port functions user?s manual u17854ej6v0ud 105 figure 4-12. block di agram of p20 to p27 internal bus p20/ani0 to p27/ani7 rd wr port wr pm output latch (p20 to p27) pm20 to pm27 selector pm2 a/d converter p2 p2: port register 2 pm2: port mode register 2 rd: read signal wr : write signal chapter 4 port functions user?s manual u17854ej6v0ud 106 4.2.4 port 3 port 3 is a 2-bit i/o port with an output latch. port 3 can be set to the input mode or output mode in 1-bit units using port mode register 3 (pm3). when the p30 and p 31 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 3 (pu3). this port can also be used for external interrupt re quest input, timer i/o, and real-time counter correction clock output. reset signal generation sets port 3 to input mode. figure 4-13 shows block a diagram of port 3. cautions 1. to use p31/ti03/to03/intp4 as a genera l-purpose port, set bit 3 (to03) of timer output register 0 (to0) and bit 3 (toe03) of timer output enable register 0 (toe0) to ?0?, which is the same as their default status setting. 2. to use p30/rtc1hz/intp3 as a general-purpose por t, set bit 5 (rcloe1) of real-time counter control register 0 (rtcc0) to ?0?, which is the same as their default status setting. figure 4-13. block diagram of p30 and p31 p30/rtc1hz/intp3, p31/ti03/to03/intp4 wr pu rd wr port wr pm pu30, pu31 pm30, pm31 ev dd p-ch pu3 pm3 p3 alternate function output latch (p30, p31) selector internal bus alternate function p3: port register 3 pu3: pull-up resistor option register 3 pm3: port mode register 3 rd: read signal wr : write signal chapter 4 port functions user?s manual u17854ej6v0ud 107 4.2.5 port 4 port 4 is an 4-bit i/o port with an output latch. port 4 can be set to the input mode or output mode in 1-bit units using port mode register 4 (pm4). when the p40 to p47 pi ns are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 4 (pu4) note . this port can also be used for serial interface data i/o, clock i/o, flash memory programmer/debugger data i/o, clock output, and timer i/o. reset signal generation sets port 4 to input mode. figures 4-14 to 4-17 show block diagrams of port 4. note when a tool is connected, the p40 and p41 pi ns cannot be connected to a pull-up resistor. cautions 1. when a tool is connected, the p40 pin cannot be used as a port pin. when the on-chip debug function is used, p41 pi n can be used as follows by the mode setting on the debugger. 1-line mode: can be used as a port (p41). 2-line mode: used as a tool1 pin a nd cannot be used as a port (p41). 2. to use p42/ti04/to04 as a gene ral-purpose port, set bit 4 (to04) of timer output register 0 (to0) and bit 4 (toe04) of timer output enable re gister 0 (toe0) to ?0?, which is the same as their default status setting. chapter 4 port functions user?s manual u17854ej6v0ud 108 figure 4-14. blo ck diagram of p40 p40/tool0 rd wr port wr pm pm4 p4 wr pu ev dd p-ch pu4 pm40 pu40 alternate function output latch (p40) selector selector internal bus alternate function p4: port register 4 pu4: pull-up resistor option register 4 pm4: port mode register 4 rd: read signal wr : write signal chapter 4 port functions user?s manual u17854ej6v0ud 109 figure 4-15. blo ck diagram of p41 p41/tool1 wr pu rd wr port wr pm pu41 pm41 ev dd p-ch pu4 pm4 p4 output latch (p41) selector selector internal bus alternate function p4: port register 4 pu4: pull-up resistor option register 4 pm4: port mode register 4 rd: read signal wr : write signal chapter 4 port functions user?s manual u17854ej6v0ud 110 figure 4-16. blo ck diagram of p42 p42/ti04/to04 rd wr port wr pm pm4 p4 wr pu ev dd p-ch pu4 pm42 pu42 alternate function output latch (p42) selector internal bus alternate function p4: port register 4 pu4: pull-up resistor option register 4 pm4: port mode register 4 rd: read signal wr : write signal chapter 4 port functions user?s manual u17854ej6v0ud 111 figure 4-17. blo ck diagram of p43 p43 wr pu rd wr port wr pm pu43 pm43 ev dd p-ch pu4 pm4 p4 output latch (p43) selector internal bus p4: port register 4 pu4: pull-up resistor option register 4 pm4: port mode register 4 rd: read signal wr : write signal chapter 4 port functions user?s manual u17854ej6v0ud 112 4.2.6 port 5 port 5 is an 6-bit i/o port with an output latch. port 5 can be set to the input mode or output mode in 1-bit units using port mode register 5 (pm5). when the p50 to p55 pi ns are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 5 (pu5). this port can also be used for external interrupt request input. reset signal generation sets port 5 to input mode. figures 4-18 and 4-19 show block diagrams of port 5. figure 4-18. block diagram of p50 and p51 p50/intp1, p51/intp2 wr pu rd wr port wr pm pu50, pu51 pm50, pm51 ev dd p-ch pm5 pu5 p5 output latch (p50, p51) selector internal bus alternate function p5: port register 5 pu5: pull-up resistor option register 5 pm5: port mode register 5 rd: read signal wr : write signal chapter 4 port functions user?s manual u17854ej6v0ud 113 figure 4-19. block diag ram of p52 to p55 p52 to p55 wr pu rd wr port wr pm pu52 to pu55 pm52 to pm55 ev dd p-ch pm5 pu5 p5 output latch (p52 to p55) selector internal bus p5: port register 5 pu5: pull-up resistor option register 5 pm5: port mode register 5 rd: read signal wr : write signal chapter 4 port functions user?s manual u17854ej6v0ud 114 4.2.7 port 6 port 6 is an 4-bit i/o port with an output latch. port 6 can be set to the input mode or output mode in 1-bit units using port mode register 6 (pm6). the output of the p60 to p63 pins is n- ch open-drain output (6 v tolerance). this port can also be used for serial interface data i/o and clock i/o. reset signal generation sets port 6 to input mode. figures 4-20 and 4-21 show block diagrams of port 6. caution when using p60/scl0 or p61/sda0 as a general-purpose port, stop the operation of serial interface iic0. figure 4-20. block diagram of p60 and p61 p60/scl0, p61/sda0 rd wr port wr pm alternate function output latch (p60, p61) pm60, pm61 alternate function internal bus selector pm6 p6 p6: port register 6 pm6: port mode register 6 rd: read signal wr : write signal chapter 4 port functions user?s manual u17854ej6v0ud 115 figure 4-21. block diagram of p62 and p63 p62, p63 rd wr port wr pm output latch (p62, p63) pm62, pm63 internal bus selector pm6 p6 p6: port register 6 pm6: port mode register 6 rd: read signal wr : write signal chapter 4 port functions user?s manual u17854ej6v0ud 116 4.2.8 port 7 port 7 is an 8-bit i/o port with an output latch. port 7 can be set to the input mode or output mode in 1-bit units using port mode register 7 (pm7). when the p70 to p77 pi ns are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 7 (pu7). this port can also be used for key re turn input, and interrupt request input. reset signal generation sets port 7 to input mode. figure 4-22 shows a block diagram of port 7. figure 4-22. block di agram of p70 to p77 p70/kr0 to p73/kr3, p74/kr4/intp8 to p77/kr7/intp11 wr pu rd wr port wr pm pu70 to pu77 pm70 to pm77 ev dd p-ch pu7 pm7 p7 alternate function output latch (p70 to p77) internal bus selector p7: port register 7 pu7: pull-up resistor option register 7 pm7: port mode register 7 rd: read signal wr : write signal chapter 4 port functions user?s manual u17854ej6v0ud 117 4.2.9 port 12 p120 is a 1-bit i/o port with an output latch. port 12 ca n be set to the input mode or output mode in 1-bit units using port mode register 12 (pm12). when used as an inpu t port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 12 (pu12). p121 to p124 are 4-bit input ports. this port can also be used for external interrupt request input, potential input for external low-voltage detection, connecting resonator for main system clock, connecting res onator for subsystem clock, and external clock input for main system clock. reset signal generation sets port 12 to input mode. figures 4-23 to 4-25 show block diagrams of port 12. caution the function setting on p121 to p124 is a vailable only once after the reset release. the port once set for connection to an oscillato r cannot be used as an input port unless the reset is performed. figure 4-23. blo ck diagram of p120 p120/intp0/exlvi wr pu rd wr port wr pm pu120 pm120 ev dd p-ch pu12 pm12 p12 alternate function output latch (p120) internal bus selector p12: port register 12 pu12: pull-up resistor option register 12 pm12: port mode register 12 rd: read signal wr : write signal chapter 4 port functions user?s manual u17854ej6v0ud 118 figure 4-24. block di agram of p121 and p122 p122/x2/exclk rd exclk, oscsel cmc oscsel cmc p121/x1 rd internal bus cmc: clock operation m ode control register rd: read signal chapter 4 port functions user?s manual u17854ej6v0ud 119 figure 4-25. block di agram of p123 and p124 p124/xt2 rd oscsels cmc oscsels cmc p123/xt1 rd internal bus cmc: clock operation m ode control register rd: read signal chapter 4 port functions user?s manual u17854ej6v0ud 120 4.2.10 port 13 p130 is a 1-bit output-only port with an output latch. figures 4-26 show block diagrams of port 13. figure 4-26. blo ck diagram of p130 rd wr port p130 p13 output latch (p130) internal bus p13: port register 13 rd: read signal wr : write signal remark when reset is effected, p130 outputs a low level. if p130 is set to output a high level before reset is effected, the output signal of p130 ca n be dummy-output as the cpu reset signal. p130 set by software reset signal chapter 4 port functions user?s manual u17854ej6v0ud 121 4.2.11 port 14 port 14 is a 2-bit i/o port with an output latch. port 14 can be set to the input mode or output mode in 1-bit units using port mode register 14 (pm14). when the p140 and p141 pins are used as an input port, use of an on-chip pull- up resistor can be specified in 1-bit units by pull-up resistor option register 14 (pu14). this port can also be used for external interrupt request input and clock/buzzer output. reset signal generation sets port 14 to input mode. figures 4-27 show block diagrams of port 14. caution to use p140/pclbuz0/intp6 or p141/pclbuz 1/intp7 as a general-purpose port, set bit 7 of clock output select register 0 and 1 (cks0, cks1) to ?0?, which is the same as their default status setting. chapter 4 port functions user?s manual u17854ej6v0ud 122 figure 4-27. block di agram of p140 and p141 p140/pclbuz0/intp6, p141/pclbuz1/intp7 wr pu rd wr port wr pm pu140, pu141 pm140, pm141 ev dd p-ch pu14 pm14 p14 alternate function output latch (p140, p141) selector internal bus alternate function p14: port register 14 pu14: pull-up resistor option register 14 pm14: port mode register 14 rd: read signal wr : write signal chapter 4 port functions user?s manual u17854ej6v0ud 123 4.3 registers controlling port function port functions are controlled by t he following six types of registers. ? port mode registers (pm0 to pm7, pm12, pm14) ? port registers (p0 to p7, p12 to p14) ? pull-up resistor option registers (pu0 , pu1, pu3 to pu5, pu7, pu12, pu14) ? port input mode registers (pim0) ? port output mode registers (pom0) ? a/d port configuration register (adpc) (1) port mode registers (pm0 to pm7, pm12, pm14) these registers specify input or output mode for the port in 1-bit units. these registers can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets these registers to ffh. when port pins are used as alternate-function pi ns, set the port mode register by referencing 4.5 settings of port mode register and output latch when using alternate function . chapter 4 port functions user?s manual u17854ej6v0ud 124 figure 4-28. format of port mode register symbol 7 6 5 4 3 2 1 0 address after reset r/w pm0 1 pm06 pm05 pm04 pm03 pm02 pm01 pm00 fff20h ffh r/w pm1 pm17 pm16 pm15 pm14 pm13 pm12 pm11 pm10 fff21h ffh r/w pm2 pm27 pm26 pm25 pm24 pm23 pm22 pm21 pm20 fff22h ffh r/w pm3 1 1 1 1 1 1 pm31 pm30 fff23h ffh r/w pm4 1 1 1 1 pm43 pm42 pm41 pm40 fff24h ffh r/w pm5 1 1 pm55 pm54 pm53 pm52 pm51 pm50 fff25h ffh r/w pm6 1 1 1 1 pm63 pm62 pm61 pm60 fff26h ffh r/w pm7 pm77 pm76 pm75 pm74 pm73 pm72 pm71 pm70 fff27h ffh r/w pm12 1 1 1 1 1 1 1 pm120 fff2ch ffh r/w pm14 1 1 1 1 1 1 pm141 pm140 fff2eh ffh r/w pmmn pmn pin i/o mode selection (m = 0 to 7, 12, 14; n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) caution be sure to set bit 7 of pm0, bits 2 to 7 of pm3, bits 4 to 7 of pm 4, bits 6 and 7 of pm5, bits 4 to 7 of pm6, bits 1 to 7 of pm12, and bits 2 to 7 of pm14 to ??1??. chapter 4 port functions user?s manual u17854ej6v0ud 125 (2) port registers (p0 to p7, p12 to p14) these registers write the data t hat is output from the chip when data is output from a port. if the data is read in the input mode, the pin level is read. if it is read in the output mode, the output latch value is read note . these registers can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears these registers to 00h. note it is always 0 and never a pin level that is read out if a p2 is read during the input mode when p2 is set to function as an analog input for a a/d converter. chapter 4 port functions user?s manual u17854ej6v0ud 126 figure 4-29. format of port register symbol 7 6 5 4 3 2 1 0 address after reset r/w p0 0 p06 p05 p04 p03 p02 p01 p00 fff00h 00h (output latch) r/w p1 p17 p16 p15 p14 p13 p12 p11 p10 fff01h 00h (output latch) r/w p2 p27 p26 p25 p24 p23 p22 p21 p20 fff02h 00h (output latch) r/w p3 0 0 0 0 0 0 p31 p30 fff03h 00h (output latch) r/w p4 0 0 0 0 p43 p42 p41 p40 fff04h 00h (output latch) r/w p5 0 0 p55 p54 p53 p52 p51 p50 fff05h 00h (output latch) r/w p6 0 0 0 0 p63 p62 p61 p60 fff06h 00h (output latch) r/w p7 p77 p76 p75 p74 p73 p72 p71 p70 fff07h 00h (output latch) r/w p12 0 0 0 p124 p123 p122 p121 p120 fff0ch undefined r/w note p13 0 0 0 0 0 0 0 p130 fff0dh 00h (output latch) r/w p14 0 0 0 0 0 0 p141 p140 fff0eh 00h (output latch) r/w m = 0 to 7, 12 to 14; n = 0 to 7 pmn output data control (in output mode) input data read (in input mode) 0 output 0 input low level 1 output 1 input high level note p121 to p124 are read-only. chapter 4 port functions user?s manual u17854ej6v0ud 127 (3) pull-up resistor option registers (pu0 , pu1, pu3 to pu5, pu7, pu12, pu14) these registers specify whether the on-c hip pull-up resistors of p00 to p06, p 10 to p17, p30, p31, p40 to p43, p50 to p55, p70 to p77, p120, p140, or p141 are to be used or not. on-chip pull-up resistors can be used in 1- bit units only for the bits set to input mode of the pins to which the use of an on-ch ip pull-up resistor has been specified in pu0, pu1, pu3 to pu5, pu7, pu12, and pu14. on-chip pu ll-up resistors cannot be connected to bits set to output mode and bits used as alternate-functi on output pins, regardless of the settings of pu0, pu1, pu3 to pu5, pu7, pu12, and pu14. these registers can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears these registers to 00h. figure 4-30. format of pull-up resistor option register symbol 7 6 5 4 3 2 1 0 address after reset r/w pu0 0 pu06 pu05 pu04 pu03 pu02 pu01 pu00 f0030h 00h r/w pu1 pu17 pu16 pu15 pu14 pu13 pu12 pu11 pu10 f0031h 00h r/w pu3 0 0 0 0 0 0 pu31 pu30 f0033h 00h r/w pu4 0 0 0 0 pu43 pu42 pu41 pu40 f0034h 00h r/w pu5 0 0 pu55 pu54 pu53 pu52 pu51 pu50 f0035h 00h r/w pu7 pu77 pu76 pu75 pu74 pu73 pu72 pu71 pu70 f0037h 00h r/w pu12 0 0 0 0 0 0 0 pu120 f003ch 00h r/w pu14 0 0 0 0 0 0 pu141 pu140 f003eh 00h r/w pumn pmn pin on-chip pull-up resistor selection (m = 0, 1, 3 to 5, 7, 12, 14; n = 0 to 7) 0 on-chip pull-up resistor not connected 1 on-chip pull-up resistor connected chapter 4 port functions user?s manual u17854ej6v0ud 128 (4) port input mode registers (pim0) this register sets the input buffer of p03 or p04 in 1-bit units. ttl input buffer can be selected during serial communication with an external device of the different potential. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. figure 4-31. format of port input mode register address: f0040h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 pim0 0 0 0 pim04 pim03 0 0 0 pim0n p0n pin input buffer selection (n = 3, 4) 0 normal input buffer 1 ttl input buffer (5) port output mode registers (pom0) this register sets the output mode of p02 to p04 in 1-bit units. n-ch open drain output (v dd tolerance) mode can be selected during serial communication with an external device of the different potential, and for th e sda10 and sda20 pins during simplified i 2 c communication with an external device of the same potential. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. figure 4-32. format of port input mode register address: f0050h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 pom0 0 0 0 pom04 pom03 pom02 0 0 pommn pmn pin output mode selection (n = 2 to 4) 0 normal output mode 1 n-ch open-drain output (v dd tolerance) mode chapter 4 port functions user?s manual u17854ej6v0ud 129 (6) a/d port configuration register (adpc) this register switches the p20/ani0 to p27/ani7 pins to digital i/o of port or anal og input of a/d converter. adpc can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to 10h. figure 4-33. format of a/d port configuration register (adpc) address: f0017h after reset: 10h r/w symbol 7 6 5 4 3 2 1 0 adpc 0 0 0 adpc4 adpc3 adpc2 adpc1 adpc0 analog input (a)/digita l i/o (d) switching adpc4 adpc3 adpc2 adpc1 adpc0 ani7/ p27 ani6/ p26 ani5/ p25 ani4/ p24 ani3/ p23 ani2/ p22 ani1/ p21 ani0/ p20 0 0 0 0 0 a a a a a a a a 0 0 0 0 1 a a a a a a a d 0 0 0 1 0 a a a a a a d d 0 0 0 1 1 a a a a a d d d 0 0 1 0 0 a a a a d d d d 0 0 1 0 1 a a a d d d d d 0 0 1 1 0 a a d d d d d d 0 0 1 1 1 a d d d d d d d 0 1 0 0 0 d d d d d d d d 1 0 0 0 0 d d d d d d d d other than above setting prohibited cautions 1. set the channel used for a/d conversion to the input mode by using port mode registers 2 (pm2). 2. do not set the pin set by adpc as digital i/o by analog input channe l specification register (ads). 3. when using all ani0/p20 to ani7/p27 pins as digital i/o (d), the setting can be done by adpc4 to adpc0 = either 01000 or 10000. chapter 4 port functions user?s manual u17854ej6v0ud 130 4.4 port function operations port operations differ depending on whether the inpu t or output mode is set, as shown below. 4.4.1 writing to i/o port (1) output mode a value is written to the output latch by a transfer instruct ion, and the output latch content s are output from the pin. once data is written to the output latch, it is reta ined until data is written to the output latch again. the data of the output latch is clear ed when a reset signal is generated. (2) input mode a value is written to the output latch by a transfer instruction, but since the output buffer is off, the pin status does not change. once data is written to the output latch, it is reta ined until data is written to the output latch again. the data of the output latch is clear ed when a reset signal is generated. 4.4.2 reading from i/o port (1) output mode the output latch contents ar e read by a transfer instruction. t he output latch content s do not change. (2) input mode the pin status is read by a transfer instruct ion. the output latch c ontents do not change. 4.4.3 operations on i/o port (1) output mode an operation is performed on the output latch contents, and the result is wr itten to the output latch. the output latch contents are output from the pins. once data is written to the output latch, it is reta ined until data is written to the output latch again. the data of the output latch is clear ed when a reset signal is generated. (2) input mode the pin level is read and an operation is performed on its cont ents. the result of the op eration is written to the output latch, but since the output buffer is off, the pin status does not change. the data of the output latch is clear ed when a reset signal is generated. chapter 4 port functions user?s manual u17854ej6v0ud 131 4.4.4 connecting to external device with different power potential (2.5v, 3 v) when parts of ports 0 operate with v dd = 4.0 v to 5.5 v, i/o connections wi th an external device that operates on a 2.5 v or 3 v power supply voltage are possible. regarding inputs, cmos/ttl switching is possible on a bi t-by-bit basis by port input mode registers (pim0). moreover, regarding outputs, different power potentials can be supported by s witching the output buffer to the n-ch open drain (v dd withstand voltage) by the port output mode registers (pom0). (1) setting procedure when using i/o pins of uart1 and csi10 functions (a) use as 2.5 v or 3 v input port <1> after reset release, the port mode is the input mode (hi-z). <2> if pull-up is needed, externally pull up the pin to be used (on-chip pull-up resistor cannot be used). in case of uart1: p03 in case of csi10: p03, p04 <3> set the corresponding bit of the pim0 register to 1 to switch to t he ttl input buffer. <4> v ih /v il operates on 2.5 v or 3 v operating voltage. (b) use as 2.5 v or 3 v output port <1> after reset release, the port mode changes to the input mode (hi-z). <2> pull up externally the pin to be used (on-chip pull-up resistor cannot be used). in case of uart1: p02 in case of csi10: p02, p04 <3> set the output latch of the corresponding port to 1. <4> set the corresponding bit of the pom0 regist er to 1 to set the n-ch open drain output (v dd withstand voltage) mode. <5> set the output mode by manipulating the pm0 register. at this time, the output data is high level, so the pin is in the hi-z state. <6> operation is done only in the low level accordin g to the operating status of the serial array unit. chapter 4 port functions user?s manual u17854ej6v0ud 132 (2) setting procedure when using i/o pins of simplified iic10 functions <1> after reset release, the port mode is the input mode (hi-z). <2> externally pull up the pin to be used (on-chip pull-up resistor cannot be used). in case of simplified iic10: p03, p04 <3> set the output latch of the corresponding port to 1. <4> set the corresponding bit of the pom0 regist er to 1 to set the n-ch open drain output (v dd withstand voltage) mode. <5> set the corresponding bit of the pm0 register to the output mode (data i/o is possibl e in the output mode). at this time, the output data is high level, so the pin is in the hi-z state. <6> enable the operation of the serial array unit and set the mode to the simplified i 2 c mode. chapter 4 port functions user?s manual u17854ej6v0ud 133 4.5 settings of port mode register and output latch when using alternate function to use the alternate function of a por t pin, set the port mode register and output latch as shown in table 4-5. table 4-5. settings of port mode register a nd output latch when using alternate function (1/2) alternate function pin name function name i/o pm p p00 ti00 input 1 p01 to00 output 0 0 so10 output 0 1 p02 txd1 output 0 1 si10 input 1 rxd1 input 1 p03 sda10 i/o 0 1 input 1 sck10 output 0 1 p04 scl10 i/o 0 1 ti05 input 1 p05 to05 output 0 0 ti06 input 1 p06 to06 output 0 0 input 1 p10 sck00 output 0 1 si00 input 1 p11 rxd0 input 1 so00 output 0 1 p12 txd0 output 0 1 p13 txd3 output 0 1 p14 rxd3 input 1 rtcdiv output 0 0 p15 rtccl output 0 0 ti01 input 1 to01 output 0 0 p16 intp5 input 1 remark : don?t care pm : port mode register p : port output latch chapter 4 port functions user?s manual u17854ej6v0ud 134 table 4-5. settings of port mode register a nd output latch when using alternate function (2/2) alternate function pin name function name i/o pm p ti02 input 1 p17 to02 output 0 0 p20 to p27 note ani0 to ani7 note input 1 rtc1hz output 0 0 p30 intp3 input 1 ti03 input 1 to03 output 0 0 p31 intp4 input 1 p40 tool0 i/o p41 tool1 output ti04 input 1 p42 to04 output 0 0 p50 intp1 input 1 p51 intp2 input 1 p60 scl0 i/o 0 0 p61 sda0 i/o 0 0 p70 to p73 kr0 to kr3 input 1 intp8 to intp11 input 1 p74 to p77 kr4 to kr7 input 1 intp0 input 1 p120 exlvi input 1 pclbuz0 output 0 0 p140 intp6 input 1 pclbuz1 output 0 0 p141 intp7 input 1 remark : don?t care pm : port mode register p : port output latch note the function of the ani0/p20 to ani7/p27 pins can be selected by using the a/d port configuration register (adpc), the analog input channel specification register (ads), and pm2. table 4-6. setting functions of ani0/p20 to ani7/p27 pins adpc pm2 ads ani0/p20 to ani7/p27 pins input mode ? digital input digital i/o selection output mode ? digital output selects ani. analog input (to be converted) input mode does not select ani. analog input (not to be converted) selects ani. analog input selection output mode does not select ani. setting prohibited chapter 4 port functions user?s manual u17854ej6v0ud 135 4.6 cautions on 1-bit manipulation in struction for port register n (pn) when a 1-bit manipulation instruction is executed on a por t that provides both input and output functions, the output latch value of an input port that is not subject to manipulation may be written in addition to the targeted bit. therefore, it is recommended to rewr ite the output latch when switching a port from input mode to output mode. user?s manual u17854ej6v0ud 136 chapter 5 clock generator 5.1 functions of clock generator the clock generator generates the clock to be supplied to the cpu and peripheral hardware. the following three kinds of system clo cks and clock oscillators are selectable. (1) main system clock <1> x1 oscillator this circuit oscillates a clock of f x = 2 to 20 mhz by connecting a resonator to x1 and x2. oscillation can be stopped by executing the stop instru ction or setting of mstop (bit 7 of the clock operation status control register (csc)). <2> internal high-speed oscillator this circuit oscillates a clock of f ih = 8 mhz (typ.). after a reset release, the cpu always starts operating with this internal high-speed oscillation cl ock. oscillation can be stopped by executing the stop instruction or setting of hiostop (bit 0 of csc). an external main system clock (f ex = 2 to 20 mhz) can also be supplied from the exclk/x2/p122 pin. an external main system clock input can be disabled by executing the stop instruct ion or setting of mstop. as the main system clock, a high-spee d system clock (x1 clock or external ma in system clock) or internal high- speed oscillation clock can be selected by setting of mcm0 (bit 4 of the system clock control register (ckc)). (2) subsystem clock ? xt1 clock oscillator this circuit oscillates a clock of f sub = 32.768 khz by connecting a 32.768 khz resonator to xt1 and xt2. oscillation can be stopped by se tting xtstop (bit 6 of csc). remark f x : x1 clock oscillation frequency f ih : internal high-speed oscillation clock frequency f ex : external main system clock frequency f sub : subsystem clock frequency (3) internal low-speed oscillation clock (clock for watchdog timer) ? internal low-speed oscillator this circuit oscillates a clock of f il = 240 khz (typ.). the internal low-speed oscillation clock cannot be used as the cpu clock. the only hardware that operates with the internal low-speed oscillation clock is the watchdog timer. oscillation is stopped when the watchdog timer stops. remarks 1. f il : internal low-speed oscillation clock frequency 2. the watchdog timer stops in the following cases. ? when bit 4 (wdton) of an option byte (000c0h) = 0 ? if the halt or stop instruction is executed when bit 4 (wdton) of an option byte (000c0h) = 1 and bit 0 (wdstbyon) = 0 chapter 5 clock generator user?s manual u17854ej6v0ud 137 5.2 configuration of clock generator the clock generator includes the following hardware. table 5-1. configuration of clock generator item configuration control registers clock operation mode control register (cmc) clock operation status control register (csc) oscillation stabilization time counter status register (ostc) oscillation stabilization time select register (osts) system clock control register (ckc) peripheral enable register 0 (per0) operation speed mode control register (osmc) internal high-speed oscillator trimming register (hiotrm) oscillators x1 oscillator xt1 oscillator internal high-speed oscillator internal low-speed oscillator chapter 5 clock generator user?s manual u17854ej6v0ud 138 figure 5-1. block diag ram of clock generator f il xt1/p123 xt2//p124 f sub f clk css cls f main osts1 osts0 osts2 3 most 18 most 17 most 15 most 13 most 11 mstop stop exclk oscsel amph 4 f ih x1/p121 x2/exclk /p122 f mx oscsels f x f ex f xt xtstop cls hiostop mcm0 mcs md iv2 md iv1 md iv0 cpu f main /2 5 f main /2 4 f main /2 3 f main /2 2 f main /2 f main 1 most 10 most 9 most 8 tau0 en sau0 en sau1 en iic0 en adc en rtc en f sub /2 internal bus internal bus clock operation mode control register (cmc) clock operation status control register (csc) oscillation stabilization time select register (osts) system clock control register (ckc) x1 oscillation stabilization time counter oscillation stabilization time counter status register (ostc) high-speed system clock oscillator crystal/ceramic oscillation external input clock subsystem clock oscillator crystal oscillation clock operation mode control register (cmc) internal high-speed oscillator (8 mhz (typ.)) internal low-speed oscillator (240 khz (typ.)) clock operation status control register (csc) main system clock source selection watchdog timer real-time counter, clock output/buzzer output clock output/ buzzer output prescaler selector selection of cpu clock and peripheral hardware clock source controller peripheral enable register 0 (per0) timer array unit serial array unit 0 serial array unit 1 serial interface iic0 a/d converter real-time counter standby control controller chapter 5 clock generator user?s manual u17854ej6v0ud 139 remark f x : x1 clock oscillation frequency f ih : internal high-speed oscillation clock frequency f ex : external main system clock frequency f mx : high-speed system clock frequency f main : main system clock frequency f xt : xt1 clock oscillation frequency f sub : subsystem clock frequency f clk : cpu/peripheral hardware clock frequency f il : internal low-speed oscillation clock frequency 5.3 registers controlling clock generator the following nine registers are used to control the clock generator. ? clock operation mode control register (cmc) ? clock operation status control register (csc) ? oscillation stabilization time c ounter status register (ostc) ? oscillation stabilization time select register (osts) ? system clock control register (ckc) ? peripheral enable registers 0 (per0) ? operation speed mode control register (osmc) ? internal high-speed oscillator trimming register (hiotrm) chapter 5 clock generator user?s manual u17854ej6v0ud 140 (1) clock operation mode control register (cmc) this register is used to set the operation mode of t he x1/p121, x2/exclk/p122, xt 1/p123, and xt2/p124 pins, and to select a gain of the oscillator. cmc can be written only once by an 8-bit memory manipulati on instruction after reset release. this register can be read by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. figure 5-2. format of clock operat ion mode control register (cmc) address: fffa0h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 cmc exclk oscsel 0 oscsels 0 0 0 amph exclk oscsel high-speed system clock pin operation mode x1/p121 pin x2/exclk/p122 pin 0 0 input port mode input port 0 1 x1 oscillation mode crystal/ceramic resonator connection 1 0 input port mode input port 1 1 external clock input mode input port external clock input oscsels subsystem clock pin operat ion mode xt1/p123 pin xt2/p124 pin 0 input port mode input port 1 xt1 oscillation mode crystal resonator connection amph control of high-speed system clock oscillation frequency 0 2 mhz f mx 10 mhz 1 10 mhz < f mx 20 mhz cautions 1. cmc can be written only once after reset release, by an 8-bit memory manipulation instruction. 2. after reset release, set cmc before x1 or xt1 oscilla tion is started as set by the clock operation status control register (csc). 3. be sure to set amph to 1 if the x1 clock oscillation fr equency exceeds 10 mhz. 4. it is recommended to set the default value (00h) to cmc after reset release, even when the register is used at the defaul t value, in order to prevent malfunctioning during a program loop. remark f mx : high-speed system clock frequency chapter 5 clock generator user?s manual u17854ej6v0ud 141 (2) clock operation status control register (csc) this register is used to control the op erations of the high-speed system clock, internal high-speed oscillation clock, and subsystem clock (except the internal low-speed oscillation clock). csc can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to c0h. figure 5-3. format of clock operati on status control register (csc) address: fffa1h after reset: c0h r/w symbol <7> <6> 5 4 3 2 1 <0> csc mstop xtstop 0 0 0 0 0 hiostop high-speed system clock operation control mstop x1 oscillation mode external clock input mode input port mode 0 x1 oscillator operating external clock from exclk pin is valid 1 x1 oscillator stopped external clock from exclk pin is invalid ? subsystem clock operation control xtstop xt1 oscillation mode input port mode 0 xt1 oscillator operating 1 xt1 oscillator stopped ? hiostop internal high-speed oscillation clock operation control 0 internal high-speed oscillator operating 1 internal high-speed oscillator stopped cautions 1. after reset release, set the clo ck operation mode control register (cmc) before starting x1 oscillation as set by mstop or xt1 oscillation as set by xtstop. 2. to start x1 oscillation as set by msto p, check the oscillation stabilization time of the x1 clock by using the oscillation stabilization time count status register (ostc). 3. do not stop the clock selected fo r the cpu peripheral hardware clock (f clk ) with the osc register. chapter 5 clock generator user?s manual u17854ej6v0ud 142 cautions 4. the setting of the flags of the re gister to stop clock o scillation (invalidate the external clock input) and the condition befo re clock oscillation is to be stopped are as follows. table 5-2. condition before stoppin g clock oscillation and flag setting clock condition befo re stopping clock (invalidating external clock input) setting of csc register flags x1 clock external main system clock ? cls = 0 and mcs = 0 ? cls = 1 (cpu and peripheral hardware cl ocks operate with a clock other than the high-speed system clock.) mstop = 1 subsystem clock ? cls = 0 (cpu and peripheral hardware cl ocks operate with a clock other than the subsystem clock.) xtstop = 1 internal high-speed oscillation clock ? cls = 0 and mcs = 1 ? cls = 1 (cpu and peripheral hardware cl ocks operate with a clock other than the internal high-speed oscillator clock.) hiostop = 1 (3) oscillation stabilization time counter status register (ostc) this is the register that indicates the count status of the x1 clock osci llation stabilization time counter. the x1 clock oscillation stabilization time can be checked in the following case, ? if the x1 clock starts oscillation while the internal high -speed oscillation clock or subsystem clock is being used as the cpu clock. ? if the stop mode is entered and then released while the internal high-speed oscillation clock is being used as the cpu clock with the x1 clock oscillating. ostc can be read by a 1-bit or 8-bit memory manipulation instruction. when reset signal is generated, the stop instruction and mstop (bit 7 of csc register) = 1 clear ostc to 00h. remark the oscillation stabilization time counter starts counting in the following cases. ? when oscillation of the x1 clock starts (exclk, oscsel = 0, 1 mstop = 0) ? when the stop mode is released chapter 5 clock generator user?s manual u17854ej6v0ud 143 figure 5-4. format of oscillation stabilizati on time counter status register (ostc) address: fffa2h after reset: 00h r symbol 7 6 5 4 3 2 1 0 ostc most 8 most 9 most 10 most 11 most 13 most 15 most 17 most 18 oscillation stabilization time status most 8 most 9 most 10 most 11 most 13 most 15 most 17 most 18 f x = 10 mhz f x = 20 mhz 0 0 0 0 0 0 0 0 2 8 /f x max. 25.6 s max. 12.8 s max. 1 0 0 0 0 0 0 0 2 8 /f x min. 25.6 s min. 12.8 s min. 1 1 0 0 0 0 0 0 2 9 /f x min. 51.2 s min. 25.6 s min. 1 1 1 0 0 0 0 0 2 10 /f x min. 102.4 s min. 51.2 s min. 1 1 1 1 0 0 0 0 2 11 /f x min. 204.8 s min. 102.4 s min. 1 1 1 1 1 0 0 0 2 13 /f x min. 819.2 s min. 409.6 s min. 1 1 1 1 1 1 0 0 2 15 /f x min. 3.27 ms min. 1.64 ms min. 1 1 1 1 1 1 1 0 2 17 /f x min. 13.11 ms min. 6.55 ms min. 1 1 1 1 1 1 1 1 2 18 /f x min. 26.21 ms min. 13.11 ms min. cautions 1. after the above time has elapsed, the bits are set to 1 in order from most8 and remain 1. 2. the oscillation stabilization time counter counts up to the oscillation stabilization time set by osts. in the following cases, set the oscillation stabilization time of osts to the value greater than the count value which is to be checked by the ostc register after the oscillation starts. ? if the x1 clock starts oscillation whil e the internal high-speed oscillation clock or subsystem clock is being used as the cpu clock. ? if the stop mode is ente red and then released while the internal high-speed oscillation clock is being used as the cp u clock with the x1 clock oscillating. (note, therefore, that only the status up to the oscillation stabilization time set by osts is set to ostc after the stop mode is released.) 3. the x1 clock oscillation stabilization wait time does not include the time until clock oscillation starts (?a? below). stop mode release x1 pin voltage waveform a remark f x : x1 clock oscillation frequency chapter 5 clock generator user?s manual u17854ej6v0ud 144 (4) oscillation stabilization time select register (osts) this register is used to select the x1 clock oscillation stabilization wait time when the stop mode is released. when the x1 clock is selected as t he cpu clock, the operation automatically waits for the time set using osts after the stop mode is released. when the internal high-speed oscillation clock is selected as the cpu clock, confirm with ostc that the desired oscillation stabilization time has elaps ed after the stop mode is released. the oscillation stabilization time can be checked up to the time set using ostc. osts can be set by an 8-bit memory manipulation instruction. reset signal generation sets osts to 07h. chapter 5 clock generator user?s manual u17854ej6v0ud 145 figure 5-5. format of oscillation stabiliz ation time select register (osts) address: fffa3h after reset: 07h r/w symbol 7 6 5 4 3 2 1 0 osts 0 0 0 0 0 osts2 osts1 osts0 oscillation stabilization time selection osts2 osts1 osts0 f x = 10 mhz f x = 20 mhz 0 0 0 2 8 /f x 25.6 s setting prohibited 0 0 1 2 9 /f x 51.2 s 25.6 s 0 1 0 2 10 /f x 102.4 s 51.2 s 0 1 1 2 11 /f x 204.8 s 102.4 s 1 0 0 2 13 /f x 819.2 s 409.6 s 1 0 1 2 15 /f x 3.27 ms 1.64 ms 1 1 0 2 17 /f x 13.11 ms 6.55 ms 1 1 1 2 18 /f x 26.21 ms 13.11 ms cautions 1. to set the stop mode when the x1 clock is used as th e cpu clock, set the osts register before executi ng the stop instruction. 2. setting the oscillation stabilization time to 20 s or less is prohibited. 3. to change the setting of the osts regist er, be sure to confirm that the counting operation of the ostc register has been completed. 4. do not change the value of the osts register during the x1 clock oscillation stabilization time. 5. the oscillation stabilization time counter counts up to the oscillation stabilization time set by osts. in the following cases, set the oscillation stabilization time of osts to the value greater than the count value which is to be checked by the ostc register after the oscillation starts. ? if the x1 clock starts oscillation wh ile the internal high-speed oscillation clock or subsystem clock is being used as the cpu clock. ? if the stop mode is entered and then released while the in ternal high-speed oscillation clock is being used as the cp u clock with the x1 clock oscillating. (note, therefore, that only the status up to the oscillation stabilization time set by osts is set to ostc after the stop mode is released.) 6. the x1 clock oscillation stabilization wait time does not include the time until clock oscillation starts (?a? below). stop mode release x1 pin voltage waveform a remark f x : x1 clock oscillation frequency chapter 5 clock generator user?s manual u17854ej6v0ud 146 (5) system clock control register (ckc) this register is used to select a cpu/per ipheral hardware clock and a division ratio. ckc can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to 09h. figure 5-6. format of system clock control register (ckc) address: fffa4h after reset: 09h r/w note 1 symbol <7> <6> <5> <4> 3 2 1 0 ckc cls css mcs mcm0 1 mdiv2 mdiv1 mdiv0 cls status of cpu/peripheral hardware clock (f clk ) 0 main system clock (f main ) 1 subsystem clock (f sub ) mcs status of main system clock (f main ) 0 internal high-speed oscillation clock (f ih ) 1 high-speed system clock (f mx ) css mcm0 mdiv2 mdiv1 mdiv0 selection of cpu/peripheral hardware clock (f clk ) 0 0 0 f ih 0 0 1 f ih /2 (default) 0 1 0 f ih /2 2 0 1 1 f ih /2 3 1 0 0 f ih /2 4 0 0 1 0 1 f ih /2 5 0 0 0 f mx 0 0 1 f mx /2 0 1 0 f mx /2 2 0 1 1 f mx /2 3 1 0 0 f mx /2 4 0 1 1 0 1 f mx /2 5 note 2 1 note 3 note 3 f sub /2 other than above setting prohibited notes 1. bits 7 and 5 are read-only. 2. setting is prohibited when f mx < 4 mhz. 3. changing the value of the mcm0 bit is prohibited while css is set to 1. remarks 1. f ih : internal high-speed oscillation clock frequency f mx : high-speed system clock frequency f sub : subsystem clock frequency 2. : don?t care (cautions 1 to 3 are listed on the next page.) chapter 5 clock generator user?s manual u17854ej6v0ud 147 cautions 1. be sure to set bit 3 to 1. 2. the clock set by css, mcm0, and md iv2 to mdiv0 is supplied to the cpu and peripheral hardware. if the cpu clock is changed, therefore, the clock supplied to peripheral hardware (e xcept the real-time counter, clock output/buzzer output, and watchdog timer) is also changed at the same time. consequently, stop each peripheral function when changing the cp u/peripheral operating hardware clock. 3. if the peripheral hardware clock is used as the subsystem cl ock, the operations of the a/d converter and iic0 are not guaranteed. for the operating characteristics of the peri pheral hardware, refer to the chapters describing the various peripheral hardware as well as chapter 27 electrical specifications. the fastest instruction can be executed in 1 clock of the cpu clock in the 78k 0r/ke3. therefore, the relationship between the cpu clock (f clk ) and the minimum instruction execution time is as shown in table 5-3. table 5-3. relationship between cpu clo ck and minimum instruction execution time minimum instruction execution time: 1/f clk main system clock (css = 0) high-speed system clock (mcm0 = 1) internal high-speed oscillation clock (mcm0 = 0) subsystem clock (css = 1) cpu clock (value set by the mdiv2 to mdiv0 bits) at 10 mhz operation at 20 mhz operation at 8 mhz (typ.) operation at 32.768 khz operation f main 0.1 s 0.05 s 0.125 s (typ.) ? f main /2 0.2 s 0.1 s 0.25 s (typ.) (default) ? f main /2 2 0.4 s 0.2 s 0.5 s (typ.) ? f main /2 3 0.8 s 0.4 s 1.0 s (typ.) ? f main /2 4 1.6 s 0.8 s 2.0 s (typ.) ? f main /2 5 3.2 s 1.6 s 4.0 s (typ.) ? f sub /2 ? ? 61 s remark f main : main system clock frequency (f ih or f mx ) f sub : subsystem clock frequency chapter 5 clock generator user?s manual u17854ej6v0ud 148 (6) peripheral enable registers 0 (per0) these registers are used to enable or disable use of each peripheral hardware macro. clock supply to the hardware that is not used is also stopped so as to decrease the power consumption and noise. per0 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears theses registers to 00h. figure 5-7. format of peripheral enable register 0 (per0) (1/2) address: f00f0h after reset: 00h r/w symbol <7> 6 <5> <4> <3> <2> 1 <0> per0 rtcen 0 adcen iic0en sau1en sau0en 0 tau0en rtcen control of real-time counter (rtc) input clock note 0 stops input clock supply. ? sfr used by the real-time counter (rtc) cannot be written (can be read). ? operation of the real-time counter (rtc) continues. 1 supplies input clock. ? sfr used by the real-time counter (rtc) can be read and written. adcen control of a/d converter input clock 0 stops input clock supply. ? sfr used by the a/d converter cannot be written. ? the a/d converter is in the reset status. 1 supplies input clock. ? sfr used by the a/d converter can be read and written. iic0en control of serial interface iic0 input clock 0 stops input clock supply. ? sfr used by the serial interface iic0 cannot be written. ? the serial interface iic0 is in the reset status. 1 supplies input clock. ? sfr used by the serial interface iic0 can be read and written. note the input clock that can be controlled by rtce n is used when the register that is used by the real-time counter (rtc) is accessed from the cpu. rtcen cannot control supply of the operating clock (f sub ) to rtc. caution be sure to clear bits 1 and 6 of per0 register to 0. chapter 5 clock generator user?s manual u17854ej6v0ud 149 figure 5-7. format of peripheral en able register 0 (per0) (2/2) sau1en control of serial array unit 1 input clock 0 stops input clock supply. ? sfr used by the serial array unit 1 cannot be written. ? the serial array unit 1 is in the reset status. 1 supplies input clock. ? sfr used by the serial array unit 1 can be read and written. sau0en control of serial array unit 0 input clock 0 stops input clock supply. ? sfr used by the serial array unit 0 cannot be written. ? the serial array unit 0 is in the reset status. 1 supplies input clock. ? sfr used by the serial array unit 0 can be read and written. tau0en control of timer array unit input clock 0 stops input clock supply. ? sfr used by the timer array unit cannot be written. ? the timer array unit is in the reset status. 1 supplies input clock. ? sfr used by the timer array unit can be read and written. caution be sure to clear bits 1 and 6 of per0 register to 0. chapter 5 clock generator user?s manual u17854ej6v0ud 150 (7) operation speed mode control register (osmc) this register is used to control the step-up circui t of the flash memory for high-speed operation. if the microcontroller operat es at a low speed with a syst em clock of 10 mhz or less, the power consumption can be lowered by setting this register to the default value, 00h. osmc can be set by an 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. figure 5-8. format of operation speed mode control register (osmc) address: f00f3h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 osmc 0 0 0 0 0 0 0 fsel fsel f clk frequency selection 0 operates at a frequency of 10 mhz or less (default). 1 operates at a frequency higher than 10 mhz. cautions 1. osmc can be written only once after reset release, by an 8-bit memory manipulation instruction. 2. write ?1? to fsel before the following two operations. ? changing the clock prior to dividing f clk to a clock other than f ih . ? operating the dma controller. 3. the cpu waits when ?1? is written to the fsel flag. the wait time is 15 s to 20 s (target) when f clk = f ih , and 30 s to 40 s (target) when f clk = f ih /2. however, counting the oscillati on stabilization time of f x can continue even while the cpu is waiting. 4. to increase f clk to 10 mhz or higher, set f se l to ?1?, then change f clk after two or more clocks have elapsed. 5. even when set to fsel = 1, the system clock can be operated at a frequency of 10 mhz or less. when setting fsel to ?1 ?, however, do so while v dd 2.25 v. when set to fsel = 1, make sure that v dd 2.25 v at the following timings, even if f clk is divided. ? when releasing f ih or f ex from the stop mode selected for f clk ? when switching f clk from f sub to f main chapter 5 clock generator user?s manual u17854ej6v0ud 151 (8) internal high-speed oscilla tor trimming register (hiotrm) this register is used to adjust the accu racy of the internal high-speed oscillator. with self-measurement of the internal high-speed osc illator frequency via a subsystem clock using a crystal resonator, a timer using high-accuracy external clock inpu t (real-time counter or timer array unit), and so on, the register can adjust the accuracy. hiotrm can be set by an 8-bit memory manipulation instruction. reset signal generation sets this register to 10h. caution the frequency will vary if the temperature and v dd pin voltage change after accuracy adjustment. moreover, if the hiotrm register is set to an y value other than the in itial value (10h), the oscillation accuracy of the internal high- speed oscillation clock may exceed 8 mhz 5%, depending on the subseque nt temperature and v dd voltage change, or hiot rm register setting. when the temperature and v dd voltage change, accuracy adjustment must be executed regularly or before the frequen cy accuracy is required. chapter 5 clock generator user?s manual u17854ej6v0ud 152 figure 5-9. format of internal high-sp eed oscillator trimming register (hiotrm) address: f00f2h after reset: 10h r/w symbol 7 6 5 4 3 2 1 0 hiotrm 0 0 0 ttrm4 ttrm3 ttrm2 ttrm1 ttrm0 clock correction value (target) (2.7 v v dd 5.5 v) ttrm4 ttrm3 ttrm2 ttrm1 ttrm0 min. typ. max. 0 0 0 0 0 ? 5.54% ? 4.88% ? 4.02% 0 0 0 0 1 ? 5.28% ? 4.62% ? 3.76% 0 0 0 1 0 ? 4.99% ? 4.33% ? 3.47% 0 0 0 1 1 ? 4.69% ? 4.03% ? 3.17% 0 0 1 0 0 ? 4.39% ? 3.73% ? 2.87% 0 0 1 0 1 ? 4.09% ? 3.43% ? 2.57% 0 0 1 1 0 ? 3.79% ? 3.13% ? 2.27% 0 0 1 1 1 ? 3.49% ? 2.83% ? 1.97% 0 1 0 0 0 ? 3.19% ? 2.53% ? 1.67% 0 1 0 0 1 ? 2.88% ? 2.22% ? 1.36% 0 1 0 1 0 ? 2.23% ? 1.91% ? 1.31% 0 1 0 1 1 ? 1.92% ? 1.60% ? 1.28% 0 1 1 0 0 ? 1.60% ? 1.28% ? 0.96.% 0 1 1 0 1 ? 1.28% ? 0.96% ? 0.64% 0 1 1 1 0 ? 0.96% ? 0.64% ? 0.32% 0 1 1 1 1 ? 0.64% ? 0.32% 0% 1 0 0 0 0 0% (default) 1 0 0 0 1 +0% +0.32% +0.64% 1 0 0 1 0 +0.33% +0.65% +0.97% 1 0 0 1 1 +0.66% +0.98% +1.30% 1 0 1 0 0 +0.99% +1.31% +1.63% 1 0 1 0 1 +1.32% +1.64% +1.96% 1 0 1 1 0 +1.38% +1.98% +2.30% 1 0 1 1 1 +1.46% +2.32% +2.98% 1 1 0 0 0 +1.80% +2.66% +3.32% 1 1 0 0 1 +2.14% +3.00% +3.66% 1 1 0 1 0 +2.48% +3.34% +4.00% 1 1 0 1 1 +2.83% +3.69% +4.35% 1 1 1 0 0 +3.18% +4.04% +4.70% 1 1 1 0 1 +3.53% +4.39% +5.05% 1 1 1 1 0 +3.88% +4.74% +5.40% 1 1 1 1 1 +4.24% +5.10% +5.76% caution the internal high-speed oscillation frequen cy becomes faster/slower by increasing/decreasing the hiotrm value to a value larger/s maller than a certain value. a reversal, such as the frequency becoming slower/faster by in creasing/decreasing the hiot rm value does not occur. chapter 5 clock generator user?s manual u17854ej6v0ud 153 5.4 system clock oscillator 5.4.1 x1 oscillator the x1 oscillator oscillates with a cryst al resonator or ceramic resonator (2 to 20 mhz) connected to the x1 and x2 pins. an external clock can also be input. in this case, input the clock signal to the exclk pin. to use the x1 oscillator, set bits 7 and 6 (exclk, oscsel) of the clock operation mode control register (cmc) as follows. ? crystal or ceramic oscillation: exclk, oscsel = 0, 1 ? external clock input: exclk, oscsel = 1, 1 when the x1 oscillator is not used, set the input port mode (exclk, oscsel = 0, 0). when the pins are not used as input port pins, either, see table 2-2 connection of unused pins . figure 5-10 shows an example of the exte rnal circuit of the x1 oscillator. figure 5-10. example of extern al circuit of x1 oscillator (a) crystal or ceramic osc illation (b) external clock v ss x1 x2 crystal resonator or ceramic resonator exclk external clock cautions are listed on the next page. 5.4.2 xt1 oscillator the xt1 oscillator oscillates with a crystal resonator (standard: 32.768 khz) connected to the xt1 and xt2 pins. to use the xt1 oscillator, set bit 4 (oscsels) of t he clock operation mode control register (cmc) to 1. when the xt1 oscillator is not used, set the input port mode (oscsels = 0). when the pins are not used as input port pins, either, see table 2-2 connection of unused pins . figure 5-11 shows an example of the exte rnal circuit of the xt1 oscillator. figure 5-11. example of external circuit of xt1 oscillator (crystal oscillation) xt2 v ss xt1 32.768 khz cautions are listed on the next page. chapter 5 clock generator user?s manual u17854ej6v0ud 154 caution 1. when using the x1 oscillator and xt1 osc illator, wire as follows in the area enclosed by the broken lines in the figures 5-10 and 5-11 to avoid an adverse e ffect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. ? always make the ground point of the oscillator capacitor th e same potential as v ss . do not ground the capacitor to a ground pattern through which a high current flows. ? do not fetch signals from the oscillator. note that the xt1 oscillator is designed as a low-amplitude circuit for reducing power consumption. figure 5-12 shows examples of incorrect resonator connection. figure 5-12. examples of incorr ect resonator connection (1/2) (a) too long wiring (b) crossed signal line x2 v ss x1 x1 v ss x2 port remark when using the subsystem clock, replace x1 and x2 with xt1 and xt2, respectively. also, insert resistors in series on the xt2 side. chapter 5 clock generator user?s manual u17854ej6v0ud 155 figure 5-12. examples of incorr ect resonator connection (2/2) (c) wiring near high alternating current (d) current flowing through ground line of oscillator (potential at points a, b, and c fluctuates) v ss x1 x2 v ss x1 x2 ab c pmn v dd high current high current (e) signals are fetched v ss x1 x2 remark when using the subsystem clock, replace x1 and x2 with xt1 and xt2, respectively. also, insert resistors in series on the xt2 side. caution 2. when x2 and xt1 are wired in parallel, the crosstalk noi se of x2 may increase with xt1, resulting in malfunctioning. chapter 5 clock generator user?s manual u17854ej6v0ud 156 5.4.3 internal hi gh-speed oscillator the internal high-speed oscillator is incorporated in the 78k0r/ke3 (8 mhz (typ.)). oscillation can be controlled by bit 0 (hiostop) of the clock operat ion status control register (csc). after a reset release, the internal high-spe ed oscillator automatically starts oscillation. 5.4.4 internal low-speed oscillator the internal low-speed oscillator is incorporated in the 78k0r/ke3. the internal low-speed oscillation clock is used only as the watchdog timer clock. the internal low-speed oscillation clock cannot be used as the cpu clock. after a reset release, the internal low-speed oscillator au tomatically starts oscillation, and the watchdog timer is driven (240 khz (typ.)) if the watchdog time r operation is enabled by the option byte. the internal low-speed oscillator c ontinues oscillation except when the wa tchdog timer stops. when the watchdog timer operates, the internal low-speed oscillation clo ck does not stop, even in case of a program loop. 5.4.5 prescaler the prescaler generates cpu/peripheral hardware clock by dividing the main system clock and subsystem clock. chapter 5 clock generator user?s manual u17854ej6v0ud 157 5.5 clock generator operation the clock generator generates the following clocks and cont rols the operation modes of the cpu, such as standby mode (see figure 5-1 ). ? main system clock f main ? high-speed system clock f mx x1 clock f x external main system clock f ex ? internal high-speed oscillation clock f ih ? subsystem clock f sub ? internal low-speed oscillation clock f il ? cpu/peripheral hardware clock f clk the cpu starts operation when the internal high-speed osc illator starts outputting after a reset release in the 78k0r/ke3, thus enabling the following. (1) enhancement of security function when the x1 clock is set as the cpu clock by the default setting, the device cannot operate if the x1 clock is damaged or badly connected and therefore does not operate afte r reset is released. however, the start clock of the cpu is the internal high-speed oscillation clock, so the device can be started by the internal high-speed oscillation clock after a reset release. as a result, reset sources can be detected by software and the minimum amount of safety processing can be done during a nomalies to ensure that t he system terminates safely. (2) improvement of performance because the cpu can be star ted without waiting for the x1 clock o scillation stabilization time, the total performance can be improved. when the power supply voltage is turned on, the clock generator operation is shown in figure 5-13 and figure 5- 14. chapter 5 clock generator user?s manual u17854ej6v0ud 158 figure 5-13. clock generator operation wh en power supply voltage is turned on (when lvi default start function sto pped is set (option byte: lvioff = 1)) internal high-speed oscillation clock (f rh ) cpu clock high-speed system clock (f xh ) (when x1 oscillation selected) internal high-speed oscillation clock high-speed system clock switched by software subsystem clock (f sub ) (when xt1 oscillation selected) subsystem clock x1 clock oscillation stabilization time: 2 8 /f x to 2 18 /f x note 2 starting x1 oscillation is set by software. starting xt1 oscillation is set by software. reset processing <3> waiting for voltage stabilization internal reset signal 0 v 1.59 v (typ.) 1.8 v 0.5 v/ms (min.) power supply voltage (v dd ) <1> <2> <4> <5> <5> <4> note 1 1.92 to 6.17 ms <1> when the power is turned on, an internal reset signal is generated by the power-on-clear (poc) circuit. <2> when the power supply voltage exceeds 1.59 v (typ.), the reset is released and the internal high-speed oscillator automatically starts oscillation. <3> when the power supply voltage rises with a slope of 0.5 v/ms (min.), the cp u starts operation on the internal high-speed oscillation clock after the reset is released and after the stabilization times for the voltage of the power supply and regulator have elapsed, and then reset processing is performed. <4> set the start of oscillation of the x1 or xt1 clock via software (see (1) in 5.6.1 example of controlling high- speed system clock and (1) in 5.6.3 example of cont rolling subsystem clock) . <5> when switching the cpu clock to the x1 or xt1 clock, wait for the clock oscillation to stabilize, and then set switching via software (see (3) in 5.6.1 example of controlli ng high-speed system clock and (3) in 5.6.3 example of controlling subsystem clock ). notes 1. the internal voltage stabilization time includes the o scillation accuracy stabilization time of the internal high-speed oscillation clock. 2. when releasing a reset (above figure) or releas ing stop mode while the cpu is operating on the internal high-speed oscillation clock, confirm the osc illation stabilization time for the x1 clock using the oscillation stabilization time count er status register (ostc). if the cpu operates on the high-speed system clock (x1 oscillation), set the oscillation st abilization time when releasing stop mode using the oscillation stabilization time select register (osts). chapter 5 clock generator user?s manual u17854ej6v0ud 159 cautions 1. if the voltage rises wit h a slope of less than 0.5 v/ms (min .) from power application until the voltage reaches 1.8 v, input a lo w level to the reset pin from power application until the voltage reaches 1.8 v, or set the lvi default st art function stopped by using the option byte (lvioff = 0) (see figure 5-14). by doing so , the cpu operates with the same timing as <2> and thereafter in figure 5-13 afte r reset release by the reset pin. 2. it is not necessary to wait for the oscillati on stabilization time when an external clock input from the exclk pin is used. remark while the microcontroller is operating, a clock t hat is not used as the cpu clock can be stopped via software settings. the internal high-speed oscill ation clock and high-speed system clock can be stopped by executing the stop instruction (see (4) in 5.6.1 example of controlli ng high-speed system clock , (3) in 5.6.2 example of controlling inte rnal high-speed oscillation clock , and (4) in 5.6.3 example of controlling subsystem clock ). figure 5-14. clock generator operation wh en power supply voltage is turned on (when lvi default start function enable d is set (option byte: lvioff = 0)) internal high-speed oscillation clock (f rh ) cpu clock high-speed system clock (f xh ) (when x1 oscillation selected) internal high-speed oscillation clock high-speed system clock switched by software subsystem clock (f sub ) (when xt1 oscillation selected) subsystem clock x1 clock oscillation stabilization time: 2 8 /f x to 2 18 /f x note 2 starting x1 oscillation is set by software. starting xt1 oscillation is set by software. internal reset signal 0 v 2.07 v (typ.) power supply voltage (v dd ) <1> <3> <2> <4> <5> reset processing (43 to 160 s) <4> <5> note 1 <1> when the power is turned on, an internal reset signal is generated by the power-on-clear (poc) circuit. <2> when the power supply voltage exceeds 2.07 v (typ.), the reset is released and the internal high-speed oscillator automatically starts oscillation. <3> after the reset is released and reset processing is performed, the cpu starts operation on the internal high- speed oscillation clock. <4> set the start of oscillation of the x1 or xt1 clock via software (see (1) in 5.6.1 example of controlling high- speed system clock and (1) in 5.6.3 example of cont rolling subsystem clock) . <5> when switching the cpu clock to the x1 or xt1 clock, wait for the clock oscillation to stabilize, and then set switching via software (see (3) in 5.6.1 example of controlli ng high-speed system clock and (3) in 5.6.3 example of controlling subsystem clock ). chapter 5 clock generator user?s manual u17854ej6v0ud 160 notes 1. the internal reset processing time includes the o scillation accuracy stabilization time of the internal high-speed oscillation clock. 2. when releasing a reset (above figure) or releas ing stop mode while the cpu is operating on the internal high-speed oscillation clock, confirm the osc illation stabilization time for the x1 clock using the oscillation stabilization time count er status register (ostc). if the cpu operates on the high-speed system clock (x1 oscillation), set the oscillation st abilization time when releasing stop mode using the oscillation stabilization time select register (osts). cautions 1. a voltage oscillation stabilization ti me is required after the supply voltage reaches 1.59 v (typ.). if the supply voltage rises from 1.59 v (typ.) to 2.07 v (typ.) within the power supply oscillation stabilization time, the power supply o scillation stabilization time is automatically generated before reset processing. 2. it is not necessary to wait for the oscillation stabilization ti me when an external clock input from the exclk pin is used. remark while the microcontroller is operating, a clock t hat is not used as the cpu clock can be stopped via software settings. the internal high-speed oscill ation clock and high-speed system clock can be stopped by executing the stop instruction (see (4) in 5.6.1 example of controlli ng high-speed system clock , (3) in 5.6.2 example of controlling inte rnal high-speed oscillation clock , and (4) in 5.6.3 example of controlling subsystem clock ). chapter 5 clock generator user?s manual u17854ej6v0ud 161 5.6 controlling clock 5.6.1 example of control ling high-speed system clock the following two types of high-s peed system clocks are available. ? x1 clock: crystal/ceramic resonator is connected to the x1 and x2 pins. ? external main system clock: exter nal clock is input to the exclk pin. when the high-speed system clock is not used, the x1/p121 and x2/exclk/p122 pins can be used as input port pins. caution the x1/p121 and x2/exclk/p122 pins are in the input port mode after a reset release. the following describes examples of setti ng procedures for the following cases. (1) when oscillating x1 clock (2) when using external main system clock (3) when using high-speed system clo ck as cpu/peripheral hardware clock (4) when stopping high-speed system clock (1) example of setting procedure when oscillating the x1 clock <1> setting p121/x1 and p122/x2/exclk pins and setting oscillation frequency (cmc register) ? 2 mhz f x 10 mhz exclk oscsel 0 oscsels 0 0 0 amph 0 1 0 0/1 0 0 0 0 ? 10 mhz < f x 20 mhz exclk oscsel 0 oscsels 0 0 0 amph 0 1 0 0/1 0 0 0 1 remarks 1. f x : x1 clock oscillation frequency 2. for setting of the p123/xt1 and p124/xt2 pins, see 5.6.3 example of controlling subsystem clock . <2> controlling oscillation of x1 clock (csc register) if mstop is cleared to 0, the x1 oscillator starts oscillating. <3> waiting for the stabilization of the oscillation of x1 clock check the ostc register and wait for the necessary time. during the wait time, other software processing can be executed with the internal high-speed oscillation clock. cautions 1. the cmc register can be written only once after reset release, by an 8-bit memory manipulation instruction. therefore, it is necessary to also set the value of the oscsels bit at the same time. for oscsels bit, see 5.6.3 example of controlling subsystem clock. 2. set the x1 clock after th e supply voltage has reached the ope rable voltage of the clock to be used (see chapter 27 el ectrical specifications). chapter 5 clock generator user?s manual u17854ej6v0ud 162 (2) example of setting procedure when using the external main system clock <1> setting p121/x1 and p122/x2/exclk pins (cmc register) exclk oscsel 0 oscsels 0 0 0 amph 1 1 0 0/1 0 0 0 remarks 1. : don?t care 2. for setting of the p123/xt1 and p124/xt2 pins, see 5.6.3 (1) example of setting procedure when oscillati ng the subsystem clock . <2> controlling external main syst em clock input (csc register) when mstop is cleared to 0, the input of the external main system clock is enabled. cautions 1. the cmc register can be written only once after reset release, by an 8-bit memory manipulation instruction. therefore, it is necessary to also set the val ue of the oscsels bits at the same time. for oscsels bits, see 5.6.3 example of controlling subsystem clock. 2. set the external main system clock after the supply voltage has reached the operable voltage of the clock to be used ( see chapter 27 electrical specifications). (3) example of setting procedure wh en using high-speed system clock as cpu/peripheral hardware clock <1> setting high-speed system clock oscillation note (see 5.6.1 (1) example of setting proc edure when oscillating the x1 clock and (2) example of setting procedure when using th e external main system clock. ) note the setting of <1> is not necessary when hi gh-speed system clock is already operating. <2> setting the high-speed system clock as the source clock of the cpu/peripheral hardware clock and setting the division ratio of the set clock (ckc register) mcm0 mdiv2 mdiv1 mdiv0 selection of cpu/peripheral hardware clock (f clk ) 0 0 0 f mx 0 0 1 f mx /2 0 1 0 f mx /2 2 0 1 1 f mx /2 3 1 0 0 f mx /2 4 1 1 0 1 f mx /2 5 note note setting is prohibited when f mx < 4 mhz. chapter 5 clock generator user?s manual u17854ej6v0ud 163 <3> if some peripheral hardware macros are not used, s upply of the input clock to each hardware macro can be stopped. (per0 register) rtcen 0 adcen iic0en sau1en sau0en 0 tau0en xxxen input clock control 0 stops input clock supply. 1 supplies input clock. caution be sure to clear bits 1 and 6 of per0 register to 0. remark rtcen: control of the r eal-time counter input clock adcen: control of the a/d converter input clock iic0en: control of the serial interface iic0 input clock sau1en: control of the serial array unit 1 input clock sau0en: control of the serial array unit 0 input clock tau0en: control of the timer array unit input clock (4) example of setting procedure when stopping the high-speed system clock the high-speed system clock can be stopped (disabling clock input if the external clock is used) in the following two ways. ? executing the stop instruction ? setting mstop to 1 (a) to execute a stop instruction <1> setting to stop peripheral hardware stop peripheral hardware that cannot be used in the stop mode (for per ipheral hardware that cannot be used in stop mode, see chapter 17 standby function ). <2> setting the x1 clock oscillation stabilization time after stop mode is released if the x1 clock oscillates before t he stop mode is entered, set the va lue of the osts register before executing the stop instruction. <3> executing the stop instruction when the stop instruction is exec uted, the system is placed in t he stop mode and x1 oscillation is stopped (the input of the exte rnal clock is disabled). chapter 5 clock generator user?s manual u17854ej6v0ud 164 (b) to stop x1 oscillation (disabling exter nal clock input) by setting mstop to 1 <1> confirming the cpu clock status (ckc register) confirm with cls and mcs that the cpu is oper ating on a clock other than the high-speed system clock. when cls = 0 and mcs = 1, the high-speed system cl ock is supplied to the cpu, so change the cpu clock to the subsystem clock or internal high-speed oscillation clock. cls mcs cpu clock status 0 0 internal high-speed oscillation clock 0 1 high-speed system clock 1 subsystem clock <2> setting of x1 clock oscillation stabilizatio n time after restart of x1 clock oscillation note prior to setting "1" to mstop, set the osts regi ster to a value greater than the count value to be confirmed with the osts register afte r x1 clock oscillation is restarted. <3> stopping the high-speed system clock (csc register) when mstop is set to 1, x1 oscillation is stopp ed (the input of the external clock is disabled). note this setting is required to resume the x1 clo ck oscillation when the high-speed system clock is in the x1 oscillation mode. this setting is not required in the external clock input mode. caution be sure to confirm that mcs = 0 or cls = 1 when setting mstop to 1. in addition, stop peripheral hardware that is operating on the high-speed system clock. 5.6.2 example of controlling inte rnal high-speed oscillation clock the following describes examples of clock setting procedures for the following cases. (1) when restarting oscillation of the internal high-speed oscillation clock (2) when using internal high-speed oscillation clock as cpu/peripheral hardware clock (3) when stopping the internal high-speed oscillation clock (1) example of setting procedure wh en restarting oscillation of the in ternal high-speed oscillation clock note <1> setting restart of oscillation of the intern al high-speed oscillation clock (csc register) when hiostop is cleared to 0, the internal hi gh-speed oscillation clock restarts oscillation. note after a reset release, the internal high-speed oscilla tor automatically starts oscillating and the internal high-speed oscillation clock is selected as the cpu/peripheral hardware clock. (2) example of setting procedure when using intern al high-speed oscillation clock as cpu/peripheral hardware clock <1> restarting oscillation of the internal high-speed oscillation clock note (see 5.6.2 (1) example of setting pr ocedure when restarting internal high-speed oscillation clock ). note the setting of <1> is not necessary when the intern al high-speed oscillation clock is operating. chapter 5 clock generator user?s manual u17854ej6v0ud 165 <2> setting the internal high-speed oscillation clock as the source clock of the cpu/peripheral hardware clock and setting the division ratio of the set clock (ckc register) mcm0 mdiv2 mdiv1 mdiv0 selection of cpu/peripheral hardware clock (f clk ) 0 0 0 f ih 0 0 1 f ih /2 0 1 0 f ih /2 2 0 1 1 f ih /2 3 1 0 0 f ih /2 4 0 1 0 1 f ih /2 5 caution if switching the cpu/pe ripheral hardware clock from th e high-speed system clock to the internal high-speed oscillation clock after restarting the inte rnal high-speed oscillation clock, do so after 10 s or more have elapsed. if the switching is made immediately after the internal high-speed oscillation clock is restarted, the accuracy of the internal high-speed oscillati on cannot be guaranteed for 10 s. (3) example of setting procedure when stoppi ng the internal high-speed oscillation clock the internal high-speed oscillation clock can be stopped in the following two ways. ? executing the stop instruction ? setting hiostop to 1 (a) to execute a stop instruction <1> setting of peripheral hardware stop peripheral hardware that cannot be used in the stop mode (for per ipheral hardware that cannot be used in stop mode, see chapter 17 standby function ). <2> setting the x1 clock oscillation stabilization time after stop mode is released if the x1 clock oscillates before t he stop mode is entered, set the va lue of the osts register before executing the stop instruction. <3> executing the stop instruction when the stop instruction is ex ecuted, the system is placed in the stop mode and internal high- speed oscillation clock is stopped. (b) to stop internal high-speed osc illation clock by setting hiostop to 1 <1> confirming the cpu clock status (ckc register) confirm with cls and mcs that the cpu is operating on a clock other than the internal high-speed oscillation clock. when cls = 0 and mcs = 0, the internal high-speed oscillation clock is supplied to the cpu, so change the cpu clock to the high-spe ed system clock or subsystem clock. cls mcs cpu clock status 0 0 internal high-speed oscillation clock 0 1 high-speed system clock 1 subsystem clock chapter 5 clock generator user?s manual u17854ej6v0ud 166 <2> stopping the internal high-speed oscillation clock (csc register) when hiostop is set to 1, internal high-speed oscillation clock is stopped. caution be sure to confirm that mcs = 1 or cls = 1 when setting hiostop to 1. in addition, stop peripheral hardware that is operating on the internal high-speed oscillation clock. 5.6.3 example of cont rolling subsystem clock the subsystem clock can be oscillated by connecti ng a crystal resonator to the xt1 and xt2 pins. when the subsystem clock is not us ed, the xt1/p123 and xt2/p124 pins can be used as input port pins. caution the xt1/p123 and xt2/p124 pins are in the input port mode after a reset release. the following describes examples of setti ng procedures for the following cases. (1) when oscillating subsystem clock (2) when using subsystem clock as cpu clock (3) when stopping subsystem clock caution when the subsystem clock is used as the cpu cl ock, the subsystem clock is also supplied to the peripheral hardware (except th e real-time counter, clock out put/buzzer output, and watchdog timer). at this time, the oper ations of the a/d converter and iic0 are not guaranteed. for the operating characteristics of the peripheral hardware , refer to the chapters describing the various peripheral hardware as well as chapte r 27 electrical specifications. (1) example of setting procedure wh en oscillating the subsystem clock <1> setting p123/xt1 and p124/xt2 pins (cmc register) exclk oscsel 0 oscsels 0 0 0 amph 0/1 0/1 0 1 0 0 0 remarks 1. : don?t care 2. for setting of the p121/x1 and p122/x2 pins, see 5.6.1 example of controlling high- speed system clock . <2> controlling oscillation of subsystem clock (csc register) if xtstop is cleared to 0, the xt1 oscillator starts oscillating. <3> waiting for the stabilization of the subsystem clock oscillation wait for the oscillation stabilization time of the subsystem clock by software, using a timer function. caution the cmc register can be written only once after reset release, by an 8-bit memory manipulation instruction. therefore, it is necessary to also set the val ue of the exclk and oscsel bits at the same time. for exclk and oscsel bits, see 5.6.1 (1) example of setting procedure when oscillating the x1 clock or 5.6. 1 (2) example of setting pro cedure when using the external main system clock. chapter 5 clock generator user?s manual u17854ej6v0ud 167 (2) example of setting procedure when us ing the subsystem cl ock as the cpu clock <1> setting subsystem clock oscillation note (see 5.6.3 (1) example of setting procedur e when oscillating the subsystem clock .) note the setting of <1> is not necessary when while the subsystem clock is operating. <2> setting the subsystem clock as the sour ce clock of the cpu clock (ckc register) css selection of cpu/peripheral hardware clock (f clk ) 1 f sub /2 caution when the subsystem clock is used as the cp u clock, the subsystem cl ock is also supplied to the peripheral hardware (exc ept the real-time counter, clock output/buzzer output, and watchdog timer). at this time, the operati ons of the a/d converter and iic0 are not guaranteed. for the operating characteristics of the peripheral hardware, refer to the chapters describing the various peripheral hardware as well as chapter 27 electrical specifications. (3) example of setting procedure when stopping the subsystem clock <1> confirming the cpu clock status (ckc register) confirm with cls and mcs that the cpu is operat ing on a clock other than the subsystem clock. when cls = 1, the subsystem clock is supplied to t he cpu, so change the cpu clock to the internal high-speed oscillation clock or high-speed system clock. cls mcs cpu clock status 0 0 internal high-speed oscillation clock 0 1 high-speed system clock 1 subsystem clock <2> stopping the subsystem clock (csc register) when xtstop is set to 1, subsystem clock is stopped. cautions 1. be sure to confi rm that cls = 0 when setting xtstop to 1. in addition, stop the peripheral hardware if it is op erating on the subsystem clock. 2. the subsystem clock oscillation cannot be stopped using the stop instruction. chapter 5 clock generator user?s manual u17854ej6v0ud 168 5.6.4 example of controlling in ternal low-speed oscillation clock the internal low-speed oscillation clock cannot be used as the cpu clock. used only as the watchdog timer clock. the internal low-speed oscillator automat ically starts oscillation after a reset release, and the watchdog timer is driven (240 khz (typ.)) if the watchdog time r operation is enabled by the option byte. the internal low-speed oscillator c ontinues oscillation except when the wa tchdog timer stops. when the watchdog timer operates, the internal low-speed oscillation clo ck does not stop even in case of a program loop. (1) example of setting procedure when stoppi ng the internal low-speed oscillation clock the internal low-speed oscillation clock can be stopped in the following two ways. ? stop the watchdog timer in the halt/stop mode by th e option byte (bit 0 (wdstbyon) of 000c0h = 0), and execute the halt or stop instruction. ? stop the watchdog timer by the option byte (bit 4 (wdton) of 000c0h = 0). (2) example of setting procedure when restarting osc illation of the internal low-speed oscillation clock the internal low-speed oscillation clock can be restarted as follows. ? release the halt or stop mode (only when the watchdog timer is stopped in the halt/s top mode by the option byte (bit 0 (wdstbyon) of 000c0h) = 0) and when the watchdog timer is stopped as a result of executio n of the halt or stop instruction). chapter 5 clock generator user?s manual u17854ej6v0ud 169 5.6.5 cpu clock stat us transition diagram figure 5-15 shows the cpu clock status transition diagram of this product. figure 5-15. cpu clock stat us transition diagram power on reset release v dd 1.59 v 0.09 v note v dd 1.8 v v dd < 1.59 v 0.09 v note internal high-speed oscillation: woken up x1 oscillation/exclk input: stops (input port mode) xt1 oscillation: stops (input port mode) internal high-speed oscillation: operating x1 oscillation/exclk input: stops (input port mode) xt1 oscillation: stops (input port mode) cpu: operating with internal high- speed oscillation internal high-speed oscillation: operating x1 oscillation/exclk input: selectable by cpu xt1 oscillation: selectable by cpu cpu: internal high- speed oscillation stop internal high-speed oscillation: stops x1 oscillation/exclk input: stops xt1 oscillation: oscillatable cpu: internal high- speed oscillation halt internal high-speed oscillation: operating x1 oscillation/exclk input: oscillatable xt1 oscillation: oscillatable cpu: operating with x1 oscillation or exclk input cpu: x1 oscillation/exclk input stop cpu: x1 oscillation/exclk input halt internal high-speed oscillation: selectable by cpu x1 oscillation/exclk input: operating xt1 oscillation: selectable by cpu internal high-speed oscillation: stops x1 oscillation/exclk input: stops xt1 oscillation: oscillatable internal high-speed oscillation: oscillatable x1 oscillation/exclk input: operating xt1 oscillation: oscillatable cpu: operating with xt1 oscillation cpu: xt1 oscillation halt internal high-speed oscillation: selectable by cpu x1 oscillation/exclk input: selectable by cpu xt1 oscillation: operating internal high-speed oscillation: oscillatable x1 oscillation/exclk input: oscillatable xt1 oscillation: operating (b) (a) (c) (d) (e) (f) (g) (h) (i) note preliminary value and subject to change. remark if the low-power-supply detector (lvi) is set to on by default by the option bytes, the reset will not be released until the power supply voltage (v dd ) exceeds 2.07 v 0.2 v note . after the reset operation, the status will shift to (b) in the above figure. chapter 5 clock generator user?s manual u17854ej6v0ud 170 table 5-4 shows transition of the cpu clock and examples of setting the sfr registers. table 5-4. cpu clock transition a nd sfr register setting examples (1/4) (1) cpu operating with internal high-speed oscillation clock (b) a fter reset release (a) status transition sfr register setting (a) (b) sfr registers do not have to be set ( default status after reset release). (2) cpu operating with high-speed system clock (c) after reset release (a) (the cpu operates with the internal high-speed oscill ation clock immediately after a reset release (b).) (setting sequence of sfr registers) cmc register note 1 csc register osmc register ckc register setting flag of sfr register status transition exclk oscsel amph mstop fsel ostc register mcm0 (a) (b) (c) (x1 clock: 2 mhz f x 10 mhz) 0 1 0 0 0 must be checked 1 (a) (b) (c) (x1 clock: 10 mhz < f x 20 mhz) 0 1 1 0 1 note 2 must be checked 1 (a) (b) (c) (external main clock) 1 1 0/1 0 0/1 must not be checked 1 notes 1. the cmc and osmc registers can be written only onc e by an 8-bit memory manipulation instruction after reset release. 2. fsel = 1 when f clk > 10 mhz if a divided clock is selected and f clk 10 mhz, use with fsel = 0 is possible even if f x > 10 mhz. caution set the clock after the s upply voltage has reached the operable voltage of the clock to be set (see chapter 27 electrical specifications). (3) cpu operating with subsystem cl ock (d) after reset release (a) (the cpu operates with the internal high-speed oscill ation clock immediately after a reset release (b).) (setting sequence of sfr registers) cmc register note csc register ckc register setting flag of sfr register status transition oscsels xtstop waiting for oscillation stabilization css (a) (b) (d) 1 0 necessary 1 note the cmc register can be written only once by an 8-bit memory manipulation instru ction after reset release. remark (a) to (i) in table 5-4 correspond to (a) to (i) in figure 5-15. chapter 5 clock generator user?s manual u17854ej6v0ud 171 table 5-4. cpu clock transition a nd sfr register setting examples (2/4) (4) cpu clock changing from inte rnal high-speed oscillation clock (b) to high-speed system clock (c) (setting sequence of sfr registers) cmc register note 1 csc register osmc register ckc regi ster setting flag of sfr register status transition exclk oscsel amph osts register mstop fsel ostc register mcm0 (b) (c) (x1 clock: 2 mhz fx 10 mhz) 0 1 0 note 2 0 0 must be checked 1 (b) (c) (x1 clock: 10 mhz < fx 20 mhz) 0 1 1 note 2 0 1 note 3 must be checked 1 (b) (c) (external main clock) 1 1 0/1 note 2 0 0/1 must not be checked 1 unnecessary if these registers are already set unnecessary if the cpu is operating with the high-speed system clock notes 1. the cmc and osmc registers can be changed only once after reset release. this setting is not necessary if it has already been set. 2. set the oscillation stabilization time as follows. ? desired ostc oscillation stabilization time oscillation stabilization time set by osts 3. fsel = 1 when f clk > 10 mhz if a divided clock is selected and f clk 10 mhz, use with fsel = 0 is possible even if f x > 10 mhz. caution set the clock after the s upply voltage has reached the operable voltage of the clock to be set (see chapter 27 electrical specifications). (5) cpu clock changing from in ternal high-speed oscillation cl ock (b) to subsystem clock (d) (setting sequence of sfr registers) cmc register note csc register ckc register setting flag of sfr register status transition oscsels xtstop waiting for oscillation stabilization css (b) (d) 1 0 necessary 1 unnecessary if the cpu is operating with the subsystem clock note the cmc register can be written only once by an 8-bit memory manipulation instru ction after reset release. remark (a) to (i) in table 5-4 correspond to (a) to (i) in figure 5-15. chapter 5 clock generator user?s manual u17854ej6v0ud 172 table 5-4. cpu clock transition a nd sfr register setting examples (3/4) (6) cpu clock changing from high- speed system clock (c) to internal high-speed oscillation clock (b) (setting sequence of sfr registers) csc register ckc register setting flag of sfr register status transition hiostop oscillation accuracy stabilization time mcm0 (c) (b) 0 10 s 0 unnecessary if the cpu is operating with the internal high- speed oscillation clock (7) cpu clock changing from high-speed system clock (c) to subsystem clock (d) (setting sequence of sfr registers) cmc register note csc register ckc register setting flag of sfr register status transition oscsels xtstop waiting for oscillation stabilization css (c) (d) 1 0 necessary 1 unnecessary if the cpu is operating with the subsystem clock note the cmc register can be written only once by an 8-bit memory manipulation instru ction after reset release. (8) cpu clock changing from subsystem clock (d ) to internal high-speed oscillation clock (b) (setting sequence of sfr registers) csc register ckc register setting flag of sfr register status transition hiostop mcm0 css (d) (b) 0 0 0 unnecessary if the cpu is operating with the internal high-speed oscillation clock unnecessary if this register is already set remark (a) to (i) in table 5-4 correspond to (a) to (i) in figure 5-15. chapter 5 clock generator user?s manual u17854ej6v0ud 173 table 5-4. cpu clock transition a nd sfr register setting examples (4/4) (9) cpu clock changing from subsystem clock (d) to high-sp eed system clock (c) (setting sequence of sfr registers) cmc register note 1 csc register osmc register ckc register setting flag of sfr register status transition exclk oscsel amph osts register mstop fsel ostc register mcm0 css (d) (c) (x1 clock: 2 mhz f x 10 mhz) 0 1 0 note 2 0 0 must be checked 1 0 (d) (c) (x1 clock: 10 mhz < f x 20 mhz) 0 1 1 note 2 0 1 note 3 must be checked 1 0 (d) (c) (external main clock) 1 1 0/1 note 2 0 0/1 must not be checked 1 0 unnecessary if this register is already set unnecessary if the cpu is operating with the high-spe ed system clock unnecessary if these registers are already set notes 1. the cmc and osmc registers can be changed only on ce after reset release. this setting is not necessary if it has already been set. 2. set the oscillation stabilization time as follows. ? desired ostc oscillation stabilization time oscillation stabilization time set by osts 3. fsel = 1 when f clk > 10 mhz if a divided clock is selected and f clk 10 mhz, use with fsel = 0 is possible even if f x > 10 mhz. caution set the clock after the s upply voltage has reached the operable voltage of the clock to be set (see chapter 27 electrical specifications). (10) ? halt mode (e) set while cpu is operating with internal high- speed oscillation clock (b) ? halt mode (f) set while cpu is ope rating with high-speed system clock (c) ? halt mode (g) set while cpu is operating with subsystem clock (d) status transition setting (b) (e) (c) (f) (d) (g) executing halt instruction (11) ? stop mode (h) set while cpu is operating wit h internal high-speed oscillation clock (b) ? stop mode (i) set while cpu is ope rating with high-speed system clock (c) (setting sequence) status transition setting in x1 stop ? (b) (h) in x1 oscillation (c) (i) stopping peripheral functions that cannot operate in stop mode sets the osts register executing stop instruction remark (a) to (i) in table 5-4 correspond to (a) to (i) in figure 5-15. chapter 5 clock generator user?s manual u17854ej6v0ud 174 5.6.6 condition before changing cpu clo ck and processing after changing cpu clock condition before changing the cpu clock and processing after changing the cpu clock are shown below. table 5-5. changing cpu clock cpu clock before change after change condition before change processing after change x1 clock stabilization of x1 oscillation ? oscsel = 1, exclk = 0, mstop = 0 ? after elapse of oscillation stabilization time external main system clock enabling input of ex ternal clock from exclk pin ? oscsel = 1, exclk = 1, mstop = 0 internal high- speed oscillation clock subsystem clock stabilization of x1 oscillation ? oscsels = 1, xtstop = 0 ? after elapse of oscillation stabilization time operating current can be reduced by stopping internal high-speed oscillator (hiostop = 1). internal high- speed oscillation clock oscillation of internal high-speed oscillator ? rstop = 0 x1 oscillation can be stopped (mstop = 1). external main system clock transition not possible (to change the clock, set it again after executing reset once.) ? x1 clock subsystem clock stabilization of xt1 oscillation ? oscsels = 1, xtstop = 0 ? after elapse of oscillation stabilization time x1 oscillation can be stopped (mstop = 1). internal high- speed oscillation clock oscillation of internal high-speed oscillator ? rstop = 0 external main system clock input can be disabled (mstop = 1). x1 clock transition not possible (to change the clock, set it again after executing reset once.) ? external main system clock subsystem clock stabilization of xt1 oscillation ? oscsels = 1, xtstop = 0 ? after elapse of oscillation stabilization time external main system clock input can be disabled (mstop = 1). internal high- speed oscillation clock oscillation of internal high-speed oscillator and selection of internal high-speed oscillation clock as main system clock ? hiostop = 0, mcs = 0 x1 clock stabilization of x1 oscillation and selection of high-speed system clock as main system clock ? oscsel = 1, exclk = 0, mstop = 0 ? after elapse of oscillation stabilization time ? mcs = 1 subsystem clock external main system clock enabling input of ex ternal clock from exclk pin and selection of high-speed system clock as main system clock ? oscsel = 1, exclk = 1, mstop = 0 ? mcs = 1 xt1 oscillation can be stopped (xtstop = 1) chapter 5 clock generator user?s manual u17854ej6v0ud 175 5.6.7 time required for switchover of cpu clock and main system clock by setting bits 0 to 2, 4, and 6 (mdiv0 to mdiv2, mcm0, c ss) of the system clock contro l register (ckc), the cpu clock can be switched (between the main system clock and the subsystem clock) , main system clock can be switched (between the internal high-speed oscillation clock and the hi gh-speed system clock), and the division ratio of the main system clock can be changed. the actual switchover operation is not performed immediat ely after rewriting to ckc; operation continues on the pre-switchover clock for several cl ocks (see table 5-6 to table 5-9). whether the cpu is oper ating on the main system clock or the sub system clock can be ascertained using bit 7 (cls) of ckc. whether the main syst em clock is operating on the high-spee d system clock or internal high-speed oscillation clock can be ascertained using bit 5 (mcs) of ckc. when the cpu clock is switched, the perip heral hardware clock is also switched. table 5-6. maximum time required for main system clock switchover clock a switching directions clock b type f ih f mx type 2 (see table 5-8) f main f sub type 3 (see table 5-9) f main (changing the division ratio) f main type 1 (see table 5-7) f sub (changing the division ratio) f sub type 1 (see table 5-7) table 5-7. maximum number of clocks required in type 1 set value after switchover set value before switchover clock a clock b clock a 1 + f a /f b clock clock b 1 + f b /f a clock table 5-8. maximum number of clocks required in type 2 set value before switchover set value after switchover mcm0 mcm0 0 (f main = f ih ) 1 (f main = f mx ) f mx >f ih 1 + f mx /f ih clock 0 (f main = f ih ) f mx user?s manual u17854ej6v0ud 177 chapter 6 timer array unit the timer array unit has eight 16-bit timers per unit. each 16-bit timer is called a channel and can be used as an independent timer. in addition, two or more ?channels? can be used to create a high-accuracy timer. single-operation function comb ination-operation function ? interval timer ? square wave output ? external event counter ? divider function ? input pulse interval measurement ? measurement of high-/low-l evel width of input signal ? pwm output ? one-shot pulse output ? multiple pwm output channel 7 can be used to realize lin-bus reception proces sing in combination with uart3 of serial array unit 1. 6.1 functions of timer array unit the timer array unit has the following functions. 6.1.1 functions of each channel when it operates independently single-operation functions are those f unctions that can be used for any channel regardless of the operation mode of the other channel (for details, refer to 6.6.1 overview of single-operation function and combination-operation function ). (1) interval timer each timer of a unit can be used as a reference timer t hat generates an interrupt (in ttm0n) at fixed intervals. (2) square wave output a toggle operation is performed each time inttm0n is ge nerated and a square wave with a duty factor of 50% is output from a timer output pin (to0k). (3) external event counter each timer of a unit can be used as an event counter t hat generates an interrupt when the number of the valid edges of a signal input to the timer input pin (ti0k) has reached a specific value. (4) divider function a clock input from a timer inpu t pin (ti0k) is divided and output from an output pin (to0k). (5) input pulse inte rval measurement counting is started by the valid edge of a pulse signal in put to a timer input pin (ti0k). the count value of the timer is captured at the valid edge of the next pulse. in this way, the interval of the input pulse can be measured. (6) measurement of high-/low-l evel width of input signal counting is started by a single edge of the signal input to the timer i nput pin (ti0k), and the count value is captured at the other edge. in this way, the high-leve l or low-level width of the input signal can be measured. remark n: channel number (n = 0 to 7), k: i/o port number (k = 0 to 6) chapter 6 timer array unit user?s manual u17854ej6v0ud 178 6.1.2 functions of each channel when it operates with another channel combination-operation functions are th ose functions that are attained by us ing the master channel (mostly the reference timer that controls cycles) and the slave channel s (timers that operate follo wing the master channel) in combination (for details, refer to 6.6.1 overview of singl e-operation function and combination-operation function ). (1) pwm (pulse width modulator) output two channels are used as a set to generate a pulse with a specified period and a specified duty factor. (2) one-shot pulse output two channels are used as a set to generate a one-shot pulse with a specified delay time and a specified pulse width. (3) multiple pwm (pulse width modulator) output by extending the pwm function and using one master ch annel and two or more slave channels, up to seven types of pwm signals that have a specific pe riod and a specified duty fa ctor can be generated. 6.1.3 lin-bus supporting function (channel 7 only) (1) detection of wakeup signal the timer starts counting at the falli ng edge of a signal input to the serial data input pin (rxd3) of uart3 and the count value of the timer is captur ed at the rising edge. in this way, a low-level width can be measured. if the low-level width is greater than a specific value, it is recognized as a wakeup signal. (2) detection of sync break field the timer starts counting at the falling edge of a signal in put to the serial data input pin (rxd3) of uart3 after a wakeup signal is detected, and the count value of the timer is captured at t he rising edge. in this way, a low- level width is measured. if the low-level width is greater than a specific value, it is recognized as a sync break field. (3) measurement of pulse width of sync field after a sync break field is detected, the low-level width and high-level width of the signal input to the serial data input pin (rxd3) of uart3 are measured. from the bit interval of the sync field measured in this way, a baud rate is calculated. chapter 6 timer array unit user?s manual u17854ej6v0ud 179 6.2 configuration of timer array unit the timer array unit includes the following hardware. table 6-1. configuration of timer array unit item configuration timer/counter timer count er register 0n (tcr0n) register timer data register 0n (tdr0n) timer input ti00 to ti06 pins, rxd3 pin (for lin-bus) timer output to00 to to06 pins, output controller chapter 6 timer array unit user?s manual u17854ej6v0ud 180 figure 6-1. block diagram of timer array unit timer clock select register 0 (tps0) 4 4 f clk f clk /2 0 to f clk /2 15 selector f clk /2 0 to f clk /2 15 selector timer output register 0 (to0) 0 to03 to06 to05 to04 to02 to01 to00 timer output enable register 0 (toe0) tau0en peripheral enable register 0 (per0) timer channel enable status register 0 (te0) timer channel stop register 0 (tt0) timer channel start register 0 (ts0) prescaler te07 te03 te06 te05 te04 te02 te01 te00 toe03 toe06 toe05 toe04 toe02 toe01 toe00 ts07 ts03 ts06 ts05 ts04 ts02 ts01 ts00 tt07 tt03 tt06 tt05 tt04 tt02 tt01 tt00 0 tol03 tol06 tol05 tol04 tol02 tol01 tol00 0 tom03 tom06 tom05 tom04 tom02 tom01 tom00 timer output level register 0 (tol0) timer output mode register 0 (tom0) channel 2 channel 3 channel 4 channel 5 channel 6 channel 7 (lin-bus supported) rxd3 ti02 ti03 ti04 ti05 ti06 to02 to03 to04 to05 to06 inttm02 inttm03 inttm04 inttm05 inttm06 inttm07 noise filter enable register 1 (nfen1) (serial input pin) timer input select register 0 (tis0) tnfen 06 tnfen 05 tnfen 04 tnfen 03 tnfen 02 tnfen 01 tnfen 00 tis07 0 0 tis03 tis06 tis05 tis04 tis02 tis01 tis00 prs013 prs003 prs012 prs011 prs010 prs002 prs001 prs000 to00 inttm00 pm16 cks01 ccs01 mas ter01 sts012 sts011 sts010 md012 cis011 cis010 md013 md011 md010 ovf 01 ck00 ck01 mck tclk f xt /4 tis01 tnfen01 interrupt controller output controller output latch (p16) to01 (timer output pin) inttm01 (timer interrupt) timer status register 01 (tsr01) overflow timer data register 01 (tdr01) timer counter register 01 (tcr01) timer mode register 01 (tmr01) channel 0 channel 1 timer controller trigger selection count clock selection mode selection slave/master controller slave/master controller edge detection selector operating clock selection noise elimination enabled/disabled ti01 (timer input pin) ti00 trigger signal to slave channel clock signal to slave channel interrupt signal to slave channel isc1 f xt /4 tis07 selector selector chapter 6 timer array unit user?s manual u17854ej6v0ud 181 (1) timer/counter register 0n (tcr0n) tcr0n is a 16-bit read-only register and is used to count clocks. the value of this counter is incr emented or decremented in synchronization with the rising edge of a count clock. whether the counter is incr emented or decremented depends on the oper ation mode that is selected by the md0n3 to md0n0 bits of tmr0n. figure 6-2. format of timer/counter register 0n (tcr0n) address: f0180h, f0181h (tcr00) to f018eh, f018fh (tcr07) after reset: ffffh r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tcr0n (n = 0 to 7) the count value can be read by reading tcr0n. the count value is set to ffffh in the following cases. ? when the reset signal is generated ? when the tau0en bit of peripheral enable register 0 (per0) is cleared the count value is cleared to 0000h in the following cases. ? when the start trigger is input in the capture mode ? when capturing has been completed in the capture mode ? when counting of the slave channel has been completed in the pwm output mode ? when counting of the master/slave channel has been completed in the one-shot pulse output mode ? when counting of the slave channel has been completed in the multiple pwm output mode caution the count value is not captured to tdr0n even when tcr0n is read. f0181h (tcr00) f0180h (tcr00) chapter 6 timer array unit user?s manual u17854ej6v0ud 182 the tcr0n register read value differs as follows according to operation mode changes and the operating status. table 6-2. tcr0n register read value in various operation modes tcr0n register read value note operation mode count mode operation mode change after reset operation mode change after count operation paused (tt0n = 1) operation restart after count operation paused (tt0n = 1) during start trigger wait status after one count interval timer mode count down ffffh undefined stop value ? capture mode count up 0000h undefined stop value ? event counter mode count down ffffh undefined stop value ? one-count mode count down ffffh undefined stop value ffffh capture & one- count mode count up 0000h undefined stop value capture value of tdr0n register + 1 note the read values of the tcr0n regist er when ts0n has been set to "1" while te0n = 0 are shown. the read value is held in the tcr0n register unt il the count operation starts. remark n = 0 to 7 chapter 6 timer array unit user?s manual u17854ej6v0ud 183 (2) timer data register 0n (tdr0n) this is a 16-bit register from which a capture function and a compare function can be selected. the capture or compare function can be switched by selecting an operation mode by using the md0n3 to md0n0 bits of tmr0n. the value of tdr0n can be changed at any time. this register can be read or written in 16-bit units. reset signal generation clears this register to 0000h. figure 6-3. format of timer data register 0n (tdr0n) address: fff18h, fff19h (tdr00), fff1ah, fff1bh (tdr01), after reset: 0000h r/w fff64h, fff65h (tdr02) to fff6eh, fff6fh (tdr07) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tdr0n (n = 0 to 7) (i) when tdr0n is used as compare register counting down is started from the value set to tdr0n. when the count value reaches 0000h, an interrupt signal (inttm0n) is generated. tdr0n ho lds its value until it is rewritten. caution tdr0n does not perform a capture operation even if a capture trigger is input, when it is set to the compare function. (ii) when tdr0n is u sed as capture register the count value of tcr0n is captured to tdr0n when the capture trigger is input. a valid edge of the ti0k pin can be selected as the capt ure trigger. this selection is made by tmr0n. remark n = 0 to 7, k = 0 to 6 fff19h (tdr00) fff18h (tdr00) chapter 6 timer array unit user?s manual u17854ej6v0ud 184 6.3 registers controlling timer array unit timer array unit is controlled by the following registers. ? peripheral enable register 0 (per0) ? timer clock select register 0 (tps0) ? timer mode register 0n (tmr0n) ? timer status register 0n (tsr0n) ? timer channel enable status register 0 (te0) ? timer channel start register 0 (ts0) ? timer channel stop register 0 (tt0) ? timer input select register 0 (tis0) ? timer output enable register 0 (toe0) ? timer output register 0 (to0) ? timer output level register 0 (tol0) ? timer output mode register 0 (tom0) ? input switch control register (isc) ? noise filter enable register 1 (nfen1) ? port mode registers 0, 1, 3, 4 (pm0, pm1, pm3, pm4) ? port registers 0, 1, 3, 4 (p0, p1, p3, p4) remark n = 0 to 7 chapter 6 timer array unit user?s manual u17854ej6v0ud 185 (1) peripheral enable register 0 (per0) per0 is used to enable or disable use of each peripheral hardware macro. clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise. when the timer array unit is used, be sure to set bit 0 (tau0en) of this register to 1. per0 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clea rs this register to 00h. cautions 1. when setting the timer array unit, be sure to set tau0en to 1 first. if tau0en = 0, writing to a control register of the timer array uni t is ignored, and all read values are default values. 2. be sure to clear bits 1 and 6 of per0 register to 0. figure 6-4. format of peripheral enable register 0 (per0) address: f00f0h after reset: 00h r/w symbol <7> 6 <5> <4> <3> <2> 1 <0> per0 rtcen 0 adcen iic0en sau1en sau0en 0 tau0en tau0en control of timer array unit input clock 0 stops supply of input clock. ? sfr used by the timer array unit cannot be written. ? the timer array unit is in the reset status. 1 supplies input clock. ? sfr used by the timer array unit can be read/written. chapter 6 timer array unit user?s manual u17854ej6v0ud 186 (2) timer clock select register 0 (tps0) tps0 is a 16-bit register that is used to select two ty pes of operation clocks (ck00, ck01) that are commonly supplied to each channel. ck01 is selected by bits 7 to 4 of tps0, and ck00 is selected by bits 3 to 0. rewriting of tps0 during timer operation is possible only in the following cases. rewriting of prs000 to prs003 bits: possible only when all the channels set to cks0n = 0 are in the operation stopped state (te0n = 0) rewriting of prs010 to prs013 bits: possible only when all the channels set to cks0n = 1 are in the operation stopped state (te0n = 0) tps0 can be set by a 16-bit memory manipulation instruction. the lower 8 bits of tps0 can be set with an 8-bi t memory manipulation instruction with tps0l. reset signal generation clears this register to 0000h. figure 6-5. format of timer cl ock select register 0 (tps0) address: f01b6h, f01b7h after reset: 0000h r/w symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tps0 0 0 0 0 0 0 0 0 prs 013 prs 012 prs 011 prs 010 prs 003 prs 002 prs 001 prs 000 selection of operation clock (ck0m) note prs 0m3 prs 0m2 prs 0m1 prs 0m0 f clk = 2 mhz f clk = 5 mhz f clk = 10 mhz f clk = 20 mhz 0 0 0 0 f clk 2 mhz 5 mhz 10 mhz 20 mhz 0 0 0 1 f clk /2 1 mhz 2.5 mhz 5 mhz 10 mhz 0 0 1 0 f clk /2 2 500 khz 1.25 mhz 2.5 mhz 5 mhz 0 0 1 1 f clk /2 3 250 khz 625 khz 1.25 mhz 2.5 mhz 0 1 0 0 f clk /2 4 125 khz 312.5 khz 625 khz 1.25 mhz 0 1 0 1 f clk /2 5 62.5 khz 156.2 khz 312.5 khz 625 khz 0 1 1 0 f clk /2 6 31.25 khz 78.1 khz 156.2 khz 312.5 khz 0 1 1 1 f clk /2 7 15.62 khz 39.1 khz 78.1 khz 156.2 khz 1 0 0 0 f clk /2 8 7.81 khz 19.5 khz 39.1 khz 78.1 khz 1 0 0 1 f clk /2 9 3.91 khz 9.76 khz 19.5 khz 39.1 khz 1 0 1 0 f clk /2 10 1.95 khz 4.88 khz 9.76 khz 19.5 khz 1 0 1 1 f clk /2 11 976 hz 2.44 khz 4.88 khz 9.76 khz 1 1 0 0 f clk /2 12 488 hz 1.22 khz 2.44 khz 4.88 khz 1 1 0 1 f clk /2 13 244 hz 610 hz 1.22 khz 2.44 khz 1 1 1 0 f clk /2 14 122 hz 305 hz 610 hz 1.22 khz 1 1 1 1 f clk /2 15 61 hz 153 hz 305 hz 610 hz note when changing the clock selected for f clk (by changing the system clock control register (ckc) value), stop the timer array unit (tt0 = 00ffh). caution be sure to clear bits 15 to 8 to ?0?. remarks 1. f clk : cpu/peripheral hardware clock frequency 2. m = 0, 1 n = 0 to 7 chapter 6 timer array unit user?s manual u17854ej6v0ud 187 (3) timer mode register 0n (tmr0n) tmr0n sets an operation mode of channel n. it is us ed to select an operation clock (mck), a count clock, whether the timer operates as the master or a slave, a st art trigger and a capture trigger, the valid edge of the timer input, and an operation mode (interval, captur e, event counter, one-count, or capture & one-count). rewriting tmr0n is prohibited when the register is in operation (when te0 = 1). however, bits 7 and 6 (cis0n1, cis0n0) can be rewritten even while the register is operating with some functions (when te0 = 1) (for details, see 6.7 operation of timer arra y unit as independent channel and 6.8 operation of plural channels of timer array unit ). tmr0n can be set by a 16-bit memory manipulation instruction. reset signal generation clears this register to 0000h. figure 6-6. format of timer m ode register 0n (tmr0n) (1/3) address: f0190h, f0191h (tmr00) to f019eh, f019fh (tmr07) after reset: 0000h r/w symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tmr0n cks 0n 0 0 ccs 0n mast er0n sts 0n2 sts 0n1 sts 0n0 cis 0n1 cis 0n0 0 0 md 0n3 md 0n2 md 0n1 md 0n0 cks 0n selection of operation cl ock (mck) of channel n 0 operation clock ck00 set by prs register 1 operation clock ck01 set by prs register operation clock mck is used by the edge detector. a count clock (tclk) is generated depending on the setting of the ccs0n bit. ccs 0n selection of count clock (tclk) of channel n 0 operation clock mck specified by cks0n bit 1 valid edge of input signal input from ti0k pin count clock tclk is used for the timer/counter, output controller, and interrupt controller. mas ter 0n selection of operation in single-oper ation function or as slave channe l in combination-operation function /operation as master channel in comb ination-operation function of channel n 0 operates in single-operation f unction or as slave channel in combination-operation function. 1 operates as master channel in combination-operation function. only the even channel can be set as a master channel (master0n = 1). be sure to use the odd channel as a slave channel (master0n = 0). clear master0n to 0 for a channel that is used with the single-operation function. caution be sure to clear bits 14, 13, 5, and 4 to ?0?. remark n = 0 to 7, k = 0 to 6 chapter 6 timer array unit user?s manual u17854ej6v0ud 188 figure 6-6. format of timer m ode register 0n (tmr0n) (2/3) address: f0190h, f0191h (tmr00) to f019eh, f019fh (tmr07) after reset: 0000h r/w symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tmr0n cks 0n 0 0 ccs 0n mast er0n sts 0n2 sts 0n1 sts 0n0 cis 0n1 cis 0n0 0 0 md 0n3 md 0n2 md 0n1 md 0n0 sts 0n2 sts 0n1 sts 0n0 setting of start trigger or capture trigger of channel n 0 0 0 only software trigger start is valid (other trigger sources are unselected). 0 0 1 valid edge of ti0k pin input is used as both the start trigger and capture trigger. 0 1 0 both the edges of ti0k pin input are us ed as a start trigger and a capture trigger. 1 0 0 interrupt signal of the master channel is us ed (when the channel is used as a slave channel with the combination-operation function). other than above setting prohibited cis 0n1 cis 0n0 selection of ti0k pin input valid edge 0 0 falling edge 0 1 rising edge 1 0 both edges (when low-level width is measured) start trigger: falling edge, capture trigger: rising edge 1 1 both edges (when high-level width is measured) start trigger: rising edge, capture trigger: falling edge if both the edges are specified when the value of the sts 0n2 to sts0n0 bits is other than 010b, set the cis0n1 to cis0n0 bits to 10b. remark n = 0 to 7, k = 0 to 6 chapter 6 timer array unit user?s manual u17854ej6v0ud 189 figure 6-6. format of timer m ode register 0n (tmr0n) (3/3) address: f0190h, f0191h (tmr00) to f019eh, f019fh (tmr07) after reset: 0000h r/w symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tmr0n cks 0n 0 0 ccs 0n mast er0n sts 0n2 sts 0n1 sts 0n0 cis 0n1 cis 0n0 0 0 md 0n3 md 0n2 md 0n1 md 0n0 md 0n3 md 0n2 md 0n1 md 0n0 operation mode of channel n count operation of tcr independent operation 0 0 0 1/0 interval timer mode counting down possible 0 1 0 1/0 capture mode counting up possible 0 1 1 0 event counter mode counting down possible 1 0 0 1/0 one-count mode counting down impossible 1 1 0 0 capture & one-count mode counting up possible other than above setting prohibited the operation of md0n0 bits varies depending on each operation mode (see table below). operation mode (value set by the md0n3 to md0n1 bits (see table above)) md 0n0 setting of starting counting and interrupt 0 timer interrupt is not generated when counting is started (timer output does not change, either). ? interval timer mode (0, 0, 0) ? capture mode (0, 1, 0) 1 timer interrupt is generated when counting is started (timer output also changes). ? event counter mode (0, 1, 1) 0 timer interrupt is not generated when counting is started (timer output does not change, either). 0 start trigger is invalid during counting operation. at that time, interrupt is not generated, either. ? one-count mode (1, 0, 0) 1 start trigger is valid during counting operation note . at that time, interrupt is also generated. ? capture & one-count mode (1, 1, 0) 0 timer interrupt is not generated when counting is started (timer output does not change, either). start trigger is invalid during counting operation. at that time interrupt is not generated, either. other than above setting prohibited note if the start trigger (ts0n = 1) is issued during operation, t he counter is cleared, an interrupt is generated, and recounting is started. remark n = 0 to 7 chapter 6 timer array unit user?s manual u17854ej6v0ud 190 (4) timer status register 0n (tsr0n) tsr0n indicates the overflow status of the counter of channel n. tsr0n is valid only in the capture mode (md0n3 to md0n1 = 010b) and capture & one-count mode (md0n3 to md0n1 = 110b). it will not be set in any other mode. see table 6-3 for the operation of the ovf bit in each operation mode and set/clear conditions. tsr0n can be read by a 16-bit memory manipulation instruction. the lower 8 bits of tsr0n can be set with an 8-bi t memory manipulation instruction with tsr0nl. reset signal generation clears this register to 0000h. figure 6-7. format of timer status register 0n (tsr0n) address: f01a0h, f01a1h (tsr00) to f01aeh, f01afh (tsr07) after reset: 0000h r symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tsr0n 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ovf ovf counter overflow status of channel n 0 overflow does not occur. 1 overflow occurs. when ovf = 1, this flag is cleared (ovf = 0) when the next value is captured without overflow. table 6-3. ovf bit operation and set/cl ear conditions in each operation mode timer operation mode ovf set/clear conditions clear when no overflow has occurred upon capturing ? capture mode ? capture & one-count mode set when an overflow has occurred upon capturing clear ? interval timer mode ? event counter mode ? one-count mode set ? (use prohibited, not set and not cleared) remark the ovf bit does not change immediately after the counter has overflowed, but changes upon the subsequent capture. chapter 6 timer array unit user?s manual u17854ej6v0ud 191 (5) timer channel enable status register 0 (te0) te0 is used to enable or stop the timer operation of each channel. when a bit of timer channel start register 0 (ts0) is set to 1, the corresponding bit of this register is set to 1. when a bit of timer channel stop register 0 (tt0) is set to 1, the corresponding bit of this register is cleared to 0. te0 can be read by a 16-bit memory manipulation instruction. the lower 8 bits of te0 can be set with a 1-bit or 8-bit memory manipulation instruction with te0l. reset signal generation clears this register to 0000h. figure 6-8. format of timer channe l enable status register 0 (te0) address: f01b0h, f01b1h after reset: 0000h r symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 te0 0 0 0 0 0 0 0 0 te07 te06 te05 te04 te03 te02 te01 te00 te0n indication of operation enable/stop status of channel n 0 operation is stopped. 1 operation is enabled. remark n = 0 to 7 chapter 6 timer array unit user?s manual u17854ej6v0ud 192 (6) timer channel start register 0 (ts0) ts0 is a trigger register that is used to clear a time r counter (tcr0n) and start t he counting operation of each channel. when a bit (ts0n) of this register is set to 1, the co rresponding bit (te0n) of timer channel enable status register 0 (te0) is set to 1. ts0n is a trigger bit and cleared immediately when te0n = 1. ts0 can be set by a 16-bit memory manipulation instruction. the lower 8 bits of ts0 can be set with a 1-bit or 8-bit memory manipulation instruction with ts0l. reset signal generation clears this register to 0000h. figure 6-9. format of timer channel start register 0 (ts0) address: f01b2h, f01b3h after reset: 0000h r/w symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ts0 0 0 0 0 0 0 0 0 ts07 ts06 ts05 ts04 ts03 ts02 ts01 ts00 ts0n operation enable (start ) trigger of channel n 0 no trigger operation 1 te0n is set to 1 and the count operation becomes enabled. the tcr0n count operation start in the count ope ration enabled state varies depending on each operation mode (see table 6-4). caution be sure to clear bits 15 to 8 to ?0?. remarks 1. when the ts0 register is read, 0 is always read. 2. n = 0 to 7 table 6-4. operations from count operati on enabled state to tcr0n count start (1/2) timer operation mode operat ion when ts0n = 1 is set ? interval timer mode no operation is carried out from start tri gger detection (ts0n=1) until count clock generation. the first count clock loads the value of tdr0n to tcr0n and the subsequent count clock performs count down operation (see 6.3 (6) (a) start timing in interval timer mode ). ? event counter mode writing 1 to ts0n bit loads the value of tdr0n to tcr0n. the subsequent count clock performs count down operation. the external trigger detection selected by sts0n2 to sts0n0 bits in the tmr0n register does not start count operation (see 6.3 (6) (b) start timing in event counter mode ). ? capture mode no operation is carried out from star t trigger detection until count clock generation. the first count clock loads 0000h to tcr0n and the subsequent count clock performs count up operation (see 6.3 (6) (c) start timing in capture mode ). chapter 6 timer array unit user?s manual u17854ej6v0ud 193 table 6-4. operations from count operati on enabled state to tcr0n count start (2/2) timer operation mode operat ion when ts0n = 1 is set ? one-count mode when ts0n = 0, writing 1 to ts0n bit sets the start trigger wait state. no operation is carried out from star t trigger detection until count clock generation. the first count clock loads the value of tdr0n to tcr0n and the subsequent count clock performs count down operation (see 6.3 (6) (d) start timing in one- count mode ). ? capture & one-count mode when ts0n = 0, writing 1 to ts0n bit sets the start trigger wait state. no operation is carried out from star t trigger detection until count clock generation. the first count clock loads 0000h to tcr0n and the subsequent count clock performs count up operation (see 6.3 (6) (e) start timing in capture & one- count mode ). (a) start timing in interval timer mode <1> writing 1 to ts0n sets te0n = 1 <2> the write data to ts0n is held until count clock generation. <3> tcr0n holds the initial val ue until count clock generation. <4> on generation of count clock, the ?tdr0n va lue? is loaded to tcr0n and count starts. figure 6-10. start timing (in interval timer mode) ts0n (write) te0n count clock f clk tcr0n initial value tdr0n value when md0n0 = 1 is set <1> <2> <3> <4> start trigger detection signal ts0n (write) hold signal inttm0n caution in the first cycle operation of count clock after writing ts0n, an error at a maximum of one clock is generated since count start delays until count clock has been generated. when the information on count start timing is necessary, an interrupt can be generated at count start by setting md0n0 = 1. chapter 6 timer array unit user?s manual u17854ej6v0ud 194 (b) start timing in event counter mode <1> while te0n is set to 0, tcr0n holds the initial value. <2> writing 1 to ts0n sets 1 to te0n. <3> as soon as 1 has been written to ts0n and 1 has been set to te0n, the "tdr0n value" is loaded to tcr0n to start counting. <4> after that, the tcr0n value is count ed down according to the count clock. figure 6-11. start timing (in event counter mode) te0n f clk tcr0n tdr0n value <1> <1> <2> <3> tdr0n value-1 initial value ts0n (write) count clock start trigger detection signal ts0n (write) hold signal (c) start timing in capture mode <1> writing 1 to ts0n sets te0n = 1 <2> the write data to ts0n is held until count clock generation. <3> tcr0n holds the initial val ue until count clock generation. <4> on generation of count clock, 0000h is loaded to tcr0n and count starts. figure 6-12. start timing (in capture mode) te0n f clk tcr0n inttm0n 0000h <1> <2> <3> <4> initial value when md0n0 = 1 is set ts0n (write) count clock start trigger detection signal ts0n (write) hold signal caution in the first cycle operation of count clock after writing ts0n, an error at a maximum of one clock is generated since count start delays until count clock has been generated. when the information on count start timing is necessary, an interrupt can be generated at count start by setting md0n0 = 1. chapter 6 timer array unit user?s manual u17854ej6v0ud 195 (d) start timing in one-count mode <1> writing 1 to ts0n sets te0n = 1 <2> enters the start trigger input wait status, and tcr0n holds the initial value. <3> on start trigger detection , the ?tdr0n value? is loaded to tcr0n and count starts. figure 6-13. start timing (in one-count mode) te0n f clk tcr0n start trigger input wait status tdr0n value initial value <1> <2> <3> ts0n (write) count clock note start trigger detection signal ts0n (write) hold signal tin edge detection signal note when the one-count mode is set, the operation cloc k (mck) is selected as count clock (ccs0n = 0). caution an input signal sampling error is gene rated since operation starts upon start trigger detection (the error is one count clock when ti0k is used). chapter 6 timer array unit user?s manual u17854ej6v0ud 196 (e) start timing in capture & one-count mode <1> writing 1 to ts0n sets te0n = 1 <2> enters the start trigger input wait status, and tcr0n holds the initial value. <3> on start trigger detection , 0000h is loaded to tcr0n and count starts. figure 6-14. start timing (in capture & one-count mode) te0n f clk tcr0n 0000h ts0n (write) count clock note start trigger detection signal ts0n (write) hold signal tin edge detection signal start trigger input wait status initial value <2> <3> <1> note when the capture & one-count mode is set, the operat ion clock (mck) is selected as count clock (ccs0n = 0). caution an input signal sampling error is gene rated since operation starts upon start trigger detection (the error is one count clock when ti0k is used). chapter 6 timer array unit user?s manual u17854ej6v0ud 197 (7) timer channel stop register 0 (tt0) tt0 is a trigger register that is used to clear a ti mer counter (tcr0n) and start the counting operation of each channel. when a bit (tt0n) of this register is set to 1, the corresponding bit (te 0n) of timer channel enable status register 0 (te0) is cleared to 0. tt0n is a tri gger bit and cleared to 0 immediately when te0n = 0. tt0 can be set by a 16-bit memory manipulation instruction. the lower 8 bits of tt0 can be set with a 1-bit or 8-bit memory manipulation instruction with tt0l. reset signal generation clears this register to 0000h. figure 6-15. format of timer channel stop register 0 (tt0) address: f01b4h, f01b5h after reset: 0000h r/w symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tt0 0 0 0 0 0 0 0 0 tt07 tt06 tt05 tt04 tt03 tt02 tt01 tt00 tt0n operation stop trigger of channel n 0 no trigger operation 1 operation is stopped (s top trigger is generated). caution be sure to clear bits 15 to 8 to ?0?. remarks 1. when the tt0 register is read, 0 is always read. 2. n = 0 to 7 (8) timer input select register 0 (tis0) tis0 is used to select whether a signal input to the time r input pin (ti0n) or the subsystem clock divided by four (f xt /4) is valid for each channel. tis0 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clea rs this register to 00h. figure 6-16. format of timer input select register 0 (tis0) address: fff3eh after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 tis0 tis07 tis06 tis05 tis04 tis03 tis02 tis01 tis00 tis0n selection of timer input/sub system clock used with channel n 0 input signal of timer input pin (ti0n) 1 subsystem clock divided by 4 (f xt /4) caution since the 78k0r/ ke3 does not have the timer input pin on channel 7, normally the timer input on channel 7 cannot be used. when the lin-bus communication function is used, select the input signal of the rxd3 pin by setting isc1 (bit 1 of the input switch control register (isc)) to 1 and setting tis07 to 0. chapter 6 timer array unit user?s manual u17854ej6v0ud 198 (9) timer output enable register 0 (toe0) toe0 is used to enable or disable timer output of each channel. channel n for which timer output has been enabled become s unable to rewrite the value of the to0n bit of the timer output register (to0) described later by software, and the value reflecting the setting of the timer output function through the count operation is out put from the timer output pin (to0n). toe0 can be set by a 16-bit memory manipulation instruction. the lower 8 bits of toe0 can be set with a 1-bit or 8-bit memory manipulation instruction with toe0l. reset signal generation clears this register to 0000h. figure 6-17. format of timer out put enable register 0 (toe0) address: f01bah, f01bbh after reset: 0000h r/w symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 toe0 0 0 0 0 0 0 0 0 0 toe 06 toe 05 toe 04 toe 03 toe 02 toe 01 toe 00 toe 0n timer output enable/disable of channel n 0 the to0n operation stopped by count operation (timer channel output bit). writing to the to0n bit is enabled. the to0n pin functions as data output, and it outputs the level set to the to0n bit. the output level of the to0n pin can be manipulated by software. 1 the to0n operation enabled by count oper ation (timer channel output bit). writing to the to0n bit is di sabled (writing is ignored). the to0n pin functions as timer output, and the toe0n is set or reset depending on the timer operation. the to0n pin outputs the square-wave or pwm depending on the timer operation. caution be sure to clear bits 15 to 7 to ?0?. remark n = 0 to 6 chapter 6 timer array unit user?s manual u17854ej6v0ud 199 (10) timer output register 0 (to0) to0 is a buffer register of timer output of each channel. the value of each bit in this register is output from the timer output pin (to0n) of each channel. this register can be rewritten by software only when ti mer output is disabled (toe0n = 0). when timer output is enabled (toe0n = 1), rewriting this register by softw are is ignored, and the value is changed only by the timer operation. to use the p01/to00, p16/to01, p 17/to02, p31/to03, p42/ to04, p05/to05, or p06/to06 pin as a port function pin, set the corresponding to0n bit to ?0?. to0 can be set by a 16-bit memory manipulation instruction. the lower 8 bits of to0 can be set with an 8-bi t memory manipulation instruction with to0l. reset signal generation clears this register to 0000h. figure 6-18. format of timer output register 0 (to0) address: f01b8h, f01b9h after reset: 0000h r/w symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 to0 0 0 0 0 0 0 0 0 0 to0 6 to0 5 to0 4 to0 3 to0 2 to0 1 to0 0 to0 n timer output of channel n 0 timer output value is ?0?. 1 timer output value is ?1?. caution be sure to clear bits 15 to 7 to ?0?. remark n = 0 to 6 chapter 6 timer array unit user?s manual u17854ej6v0ud 200 (11) timer output level register 0 (tol0) tol0 is a register that controls t he timer output level of each channel. the setting of the inverted output of channel n by this register is reflec ted at the timing of set or reset of the timer output signal while the timer output is enabled (t oe0n = 1) in the combination-operation mode (tom0n = 1). in the toggle mode (tom0n = 0), this register setting is invalid. tol0 can be set by a 16-bit memory manipulation instruction. the lower 8 bits of tol0 can be set with an 8-bi t memory manipulation instruction with tol0l. reset signal generation clears this register to 0000h. figure 6-19. format of timer ou tput level register 0 (tol0) address: f01bch, f01bdh after reset: 0000h r/w symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tol0 0 0 0 0 0 0 0 0 0 tol 06 tol 05 tol 04 tol 03 tol 02 tol 01 tol 00 tol 0n control of timer output level of channel n 0 positive logic out put (active-high) 1 inverted output (active-low) caution be sure to clear bits 15 to 7 to ?0?. remarks 1. if the value of this register is rewritten during timer operation, the timer output is inverted when the timer output signal changes next, instead of imm ediately after the register value is rewritten. 2. n = 0 to 6 chapter 6 timer array unit user?s manual u17854ej6v0ud 201 (12) timer output mode register 0 (tom0) tom0 is used to control the timer output mode of each channel. when a channel is used for the single- operation function, set the corres ponding bit of the channel to be used to 0. when a channel is used for the combination-operatio n function (pwm output, one-shot pulse output, or multiple pwm output), set the corresponding bit of the master channel to 0 and the corresponding bit of the slave channel to 1. the setting of each channel n by this register is reflec ted at the timing when the timer output signal is set or reset while the timer output is enabled (toe0n = 1). tom0 can be set by a 16-bit memory manipulation instruction. the lower 8 bits of tom0 can be set with an 8-bi t memory manipulation instruction with tom0l. reset signal generation clears this register to 0000h. figure 6-20. format of timer ou tput mode register 0 (tom0) address: f01beh, f01bfh after reset: 0000h r/w symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tom0 0 0 0 0 0 0 0 0 0 tom 06 tom 05 tom 04 tom 03 tom 02 tom 01 tom 00 tom 0n control of timer output mode of channel n 0 toggle mode (to produce toggle output by timer interrupt request signal (inttm0n)) 1 combination-operation mode (output is set by the time r interrupt request signal (inttm0n) of the master channel, and reset by the timer interrupt reque st signal (inttm0m) of the slave channel) caution be sure to clear bits 15 to 7 to ?0?. remark n: channel number, m: slave channel number n = 0 to 6 (n = 0, 2, 4 for master channel) n < m 6 (where m is a consecutive integer greater than n) chapter 6 timer array unit user?s manual u17854ej6v0ud 202 (13) input switch control register (isc) isc is used to implement lin-bus communication operat ion with channel 7 in association with serial array unit 1. when bit 1 of this register is set to 1, the input signal of the serial data input pin (rxd3) is selected as a timer input signal. isc can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clea rs this register to 00h. figure 6-21. format of input switch control register (isc) address: fff3ch after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 isc 0 0 0 0 0 0 isc1 isc0 isc1 switching channel 7 input of timer array unit 0 not uses the input signal (normal operation). 1 input signal of r x d3 pin is used as timer input (wakeup signal detection). isc0 switching external interrupt (intp0) input 0 uses the input signal of the intp0 pin as an external interrupt (normal operation). 1 uses the input signal of the r x d3 pin as an external interrupt (to measure the pulse widths of t he sync break field and sync field). caution be sure to clear bits 7 to 2 to ?0?. remark since the 78k0r/ke3 does not have the timer input pin on channel 7, normally the timer input on channel 7 cannot be used. when the lin-bus comm unication function is used, select the input signal of the rxd3 pin by setting isc1 to 1 and setti ng tis07 (bit 7 of the timer input select register 0 (tis0)) to 0. (14) noise filter enable register 1 (nfen1) nfen1 is used to set whether the noise filter c an be used for the timer input signal to each channel. enable the noise filter by setting the corresponding bi ts to 1 on the pins in need of noise removal. when the noise filter is on, matc h detection and synchronization of the 2 clocks is performed with the cpu/peripheral hardware clock (f clk ). when the noise filter is off, only synchronization is performed with the cpu/peripheral hardware clock (f clk ). nfen1 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clea rs this register to 00h. chapter 6 timer array unit user?s manual u17854ej6v0ud 203 figure 6-22. format of noise filt er enable register 1 (nfen1) address: f0061h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 nfen1 0 tnfen06 tnfen05 tnfen04 tnfen03 tnfen02 tnfen01 tnfen00 tnfen06 enable/disable using noise filt er of ti06/to06/p06 pin input signal 0 noise filter off 1 noise filter on tnfen05 enable/disable using noise filt er of ti05/to05/p05 pin input signal 0 noise filter off 1 noise filter on tnfen04 enable/disable using noise filt er of ti04/to04/p42 pin input signal 0 noise filter off 1 noise filter on tnfen03 enable/disable using noise filter of ti03/to03/intp4/p31 pin input signal 0 noise filter off 1 noise filter on tnfen02 enable/disable using noise filt er of ti02/to02/p17 pin input signal 0 noise filter off 1 noise filter on tnfen01 enable/disable using noise filter of ti01/to01/intp5/p16 pin input signal 0 noise filter off 1 noise filter on tnfen00 enable/disable using noise f ilter of ti00/p00 pin input signal 0 noise filter off 1 noise filter on caution be sure to clear bits 7 to ?0?. chapter 6 timer array unit user?s manual u17854ej6v0ud 204 (15) port mode registers 0, 1, 3, 4 (pm0, pm1, pm3, pm4) these registers set input/output of por ts 0, 1, 3, and 4 in 1-bit units. when using the p01/to00, p05/to 05/ti05, p06/to06/ti06, p16/to01/ti01/intp5, p17/to02/ti02, p31/to03/ti03/intp4, and p42/to04/ ti04 pins for timer output, set pm01, pm05, pm06, pm16, pm17, pm31,and pm42 and the output la tches of p01, p05, p06, p16, p17, p31, and p42 to 0. when using the p00/ti00, p05/to 05/ti05, p06/to06/ti06, p16/to 01/ti01/intp5, p17/to02/ti02, p31/to03/ti03/intp4, and p42/to04/ti 04 pins for timer input, set pm00, pm05, pm06, pm16, pm17, pm31, and pm42 to 1. at this time, the output latches of p 00, p05, p06, p16, p17, p31, and p42 may be 0 or 1. pm0, pm1, pm3, and pm4 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation se ts these registers to ffh. figure 6-23. format of port mode registers 0, 1, 3, 4 (pm0, pm1, pm3, pm4) address: fff20h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm0 1 pm06 pm05 pm04 pm03 pm02 pm01 pm00 address: fff21h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm1 pm17 pm16 pm15 pm14 pm13 pm12 pm11 pm10 address: fff23h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm3 1 1 1 1 1 1 pm31 pm30 address: fff24h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm4 1 1 1 1 pm43 pm42 pm41 pm40 pmmn pmn pin i/o mode selection (m = 0, 1, 3, 4; n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) chapter 6 timer array unit user?s manual u17854ej6v0ud 205 6.4 channel output (to0n pin) control 6.4.1 to0n pin output circuit configuration figure 6-24. output circuit configuration interrupt signal of the master channel (inttm0n) tol0n tom0n toe0n <1> <2> <3> <4> <5> to0n write signal to0n pin to0n register set reset/toggle internal bus interrupt signal of the slave channel (inttm0p) controller the following describes the to0n pin output circuit. <1> when tom0n = 0 (toggle mode), the set value of t he tol0n register is ignored and only inttm0p (slave channel timer interrupt) is transmitted to the to0n register. <2> when tom0n = 1 (combination-operation mode), both inttm0n (master channel timer interrupt) and inttm0p (slave channel timer interrupt) are transmitted to the to0n register. at this time, the tol0n register becomes valid and the signals are controlled as follows: when tol0n = 0: forward operation (inttm0 set, inttm0p reset) when tol0n = 1: reverse operation (inttm0 reset, inttm0p set) when inttm0n and inttm0p are simultaneously generated, (0% output of pwm), inttm0p (reset signal) takes priority, and inttm0n (set signal) is masked. <3> when toe0n = 1, inttm0n (master channel timer interrupt) and inttm0p (slave channel timer interrupt) are transmitted to the to0n register. writing to t he to0n register (to0n write signal) becomes invalid. when toe0n = 1, the to0n pin output never chang es with signals other than interrupt signals. to initialize the to0n pin output level, it is nece ssary to set toe0n = 0 and to write a value to to0n. <4> when toe0n = 0, writing to to0n bit to the tar get channel (to0n write signal) becomes valid. when toe0n = 0, neither inttm0n (master channel time r interrupt) nor inttm0p (slave channel timer interrupt) is transmitted to to0n register. <5> the to0n register can always be read, and the to0n pin output level can be checked. remarks 1. n = 0 to 6 (n = 0, 2, or 4 for master channel) 2. p = n + 1, n + 2, n + 3 ... (where p 6) chapter 6 timer array unit user?s manual u17854ej6v0ud 206 6.4.2 to0n pin output setting the following figure shows the procedure and status transition of to0n out put pin from initial setting to timer operation start. figure 6-25. status transition from ti mer output setting to operation start tcr0n timer alternate-function pin timer output signal toe0n to0n (counter) undefined value (ffffh after reset) write operation enabled period to to0n <1> set the tom0n set the tol0n <4> set the port to output mode <2> set the to0n <3> set the toe0n <5> timer operation start write operation disabled period to to0n hi-z <1> the operation mode of timer output is set. ? tom0n bit (0: toggle mode, 1: combination-operation mode) ? tol0n bit (0: forward output, 1: reverse output) <2> the timer output signal is set to the initial status by setting to0n. <3> the timer output operation is enabled by wr iting 1 to toe0n (writing to to0n is disabled). <4> the port i/o setting is set to output (see 6.3 (15) port mode registers 0, 1, 3, 4 ). <5> the timer operation is enabled (ts0n = 1). remark n = 0 to 6 6.4.3 cautions on channel output operation (1) changing values set in registers to0, toe0,tol0, and tom0 during timer operation since the timer operations (operati ons of tcr0n and tdr0n) are indepen dent of the to0n output circuit and changing the values set in to0, toe0, tol0, and tom0 does not affect the timer operation, the values can be changed during timer operation. when the values set in toe0, tol0, and tom0 (except for to0) are changed close to the timer interrupt (inttm0n), the waveform output to the to0n pin ma y be different depending on whether the values are changed immediately before or immediately after the ti mer interrupt (inttm0n) signal generation timing. remark n = 0 to 6 chapter 6 timer array unit user?s manual u17854ej6v0ud 207 (2) default level of to0n pin and output level after timer operation start the following figure shows the to0n pin output level transition when writing has been done in the state of toe0n = 0 before port output is enabled and toe0n = 1 is set after changing the default level. (a) when operation starts with tom0n = 0 setting (toggle output) the setting of tol0n is invalid when tom0n = 0. when the timer operation starts after setting the default level, the toggle signal is generated an d the output level of to0n pin is reversed. figure 6-26. to0n pin output status at toggle output (tom0n = 0) toe0n to0n = 0, tol0n = 0 to0n = 1, tol0n = 0 to0n = 0, tol0n = 1 (same output waveform as tol0n = 0) to0n = 1, tol0n = 1 (same output waveform as tol0n = 0) default level, tol0n setting independent of tol0n setting port output is enabled to0n pin transition toggle toggle toggle toggle toggle hi-z hi-z hi-z hi-z dependent on to0n setting remarks 1. toggle: reverse to0n pin output status 2. n = 0 to 6 chapter 6 timer array unit user?s manual u17854ej6v0ud 208 (b) when operation starts with tom0n = 1 setti ng (combination-operation mode (pwm output)) when tom0n = 1, the active level is determined by tol0n setting. figure 6-27. to0n pin output stat us at pwm output (tom0n = 1) toe0n to0n = 0, tol0n = 0 (active high) to0n = 1, tol0n = 0 (active high) to0n = 0, tol0n = 1 (active low) to0n = 1, tol0n = 1 (active low) default level, tol0n setting dependent on tol0n setting dependent on to0n setting no change set reset set reset set hi-z hi-z hi-z hi-z to0n pin transition port output is enabled remarks 1. set: the output signal of to0n pin changes from inactive level to active level. reset: the output signal of to0n pin changes from active level to inactive level. 2. n = 0 to 6 (3) operation of to0n pin in combination-operation mode (tom0n = 1) (a) when tol0n setting has been changed during timer operation when the tol0n setting has been changed during timer operation, the setting becomes valid at the generation timing of to0n change condition. rewriti ng tol0n does not change the output level of to0n. the following figure shows the operation when the value of tol0n has been changed during timer operation (tom0n = 1). figure 6-28. operation when tol0n ha s been changed during timer operation internal set signal internal reset signal tol0n to0n pin set/reset signals are inverted to0n does not change remarks 1. set: the output signal of to0n pin changes from inactive level to active level. reset: the output signal of to0n pin changes from active level to inactive level. 2. n = 0 to 6 chapter 6 timer array unit user?s manual u17854ej6v0ud 209 (b) set/reset timing to realize 0%/100% output at pwm output, the to0n pi n/to0n set timing at master channel timer interrupt (inttm0n) generation is delayed by 1 count clock by the slave channel timer interrupt (inttm0p). if the set condition and reset condition are generated at the same time, a higher priority is given to the latter. figure 6-29 shows the set/reset operat ing statuses where the master/sla ve channels are set as follows. master channel: toe0n = 1, tom0n = 0, tol0n = 0 slave channel: toe0p = 1, tom0p = 1, tol0p = 0 figure 6-29. set/reset ti ming operating statuses to_reset (internal signal) to_reset (internal signal) (internal signal) inttm0n to0n pin/ to0n to0p pin/ to0p count clock f clk inttm0p to_set delays to_reset by 1 count clock with slave channel toggle set reset master channel slave channel remarks 1. to_reset: to0n pin reset/toggle signal to_set: to0n pin set signal 2. n = 0 to 6 (where n = 0, 2, or 4 for master channel) 3. p = n+1, n+2, n+3 ... (where p 6) chapter 6 timer array unit user?s manual u17854ej6v0ud 210 6.4.4 collective manipul ation of to0n bits in the to0 register, the setting bits for all the channels ar e located in one register in the same way as the ts0 register (channel start trigger). theref ore, to0n of all the channels can be manipu lated collectively. only specific bits can also be manipulated by setting the correspondi ng toe0n = 0 to a target to0n (channel output). figure 6-30. example of to0n bits collective manipulation before writing to0 0 0 0 0 0 0 0 0 0 to06 0 to05 1 to04 0 to03 0 to02 0 to01 1 to00 0 toe0 0 0 0 0 0 0 0 0 0 toe06 0 toe05 1 toe04 0 toe03 1 toe02 1 toe01 1 toe00 1 data to be written 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 after writing to0 0 0 0 0 0 0 0 0 0 to06 1 to05 1 to04 0 to03 0 to02 0 to01 1 to00 0 writing is done only to to0n bits with toe0n = 0, and writing to to0n bits with toe0n = 1 is ignored. to0n (channel output) to which toe0n = 1 is set is not affe cted by the write op eration. even if the write operation is done to to0n, it is ignored and the output change by timer operation is normally done. figure 6-31. to0n pin statuses by collective manipulation of toon bits to06 to05 to04 to03 to02 to01 to00 two or more to0n output can be changed simultaneously output does not change when value does not change before writing writing to to0n register is ignored when toe0n = 1 writing to to0n register (caution and remark are given on the next page.) o o chapter 6 timer array unit user?s manual u17854ej6v0ud 211 caution when toe0n = 1, even if the output by ti mer interrupt of each timer (inttm0n) contends with writing to to0n, output is normally done to to0n pin. remark n = 0 to 6 6.4.5 timer interrupt and to0n pin output at operation start in the interval timer mode or capture mode, the md0n0 bit in the tmr0n register sets whether or not to generate a timer interrupt at count start. when md0n0 is set to 1, the count operation start timing can be known by the timer interrupt (inttm0n) generation. in the other modes, neither timer interrupt at c ount operation start nor to 0n output is controlled. figures 6-32 and 6-33 show operation examples when the interval timer mode (toe0n = 1, tom0n = 0) is set. figure 6-32. when md0n0 is set to 1 tcr0n te0n to0n inttm0n count operation start when md0n0 is set to 1, a timer interrupt (inttm0n) is output at count operation start, and to0n performs a toggle operation. figure 6-33. when md0n0 is set to 0 tcr0n te0n to0n inttm0n count operation start when md0n0 is set to 0, a timer interrupt (inttm0n) is not output at count operation start, and to0n does not change either. after counting one cycle, inttm0n is output and to0n performs a toggle operation. remark n = 0 to 6 chapter 6 timer array unit user?s manual u17854ej6v0ud 212 6.5 channel input (ti0n pin) control 6.5.1 ti0n edge detection circuit (1) edge detection basic operation timing edge detection circuit sampling is done in accordance with the operation clock (mck). figure 6-34. edge detect ion basic operation timing f clk rising edge detection internal trigger falling edge detection internal trigger operation clock (mck) synchronized (noise filter) internal ti0n signal remark n = 0 to 6 chapter 6 timer array unit user?s manual u17854ej6v0ud 213 6.6 basic function of timer array unit 6.6.1 overview of single-operation func tion and combination-operation function the timer array unit consists of several channels and has a single-operation function that allows each channel to operate independently, and a combination-operation functi on that uses two or more channels in combination. the single-operation function can be used for any channel, regardless of the operation mode of the other channels. the combination-operation function is r ealized by combining a master channel (reference timer that mainly counts periods) and a slave channel (timer that operates in acco rdance with the master channel), and several rules must be observed when using this function. 6.6.2 basic rules of comb ination-operation function the basic rules of using the combinat ion-operation function are as follows. (1) only an even channel (channel 0, 2, 4, etc.) can be set as a master channel. (2) any channel, except channel 0, can be set as a slave channel. (3) the slave channel must be lower than the master channel. example: if channel 2 is set as a master channel, channel 3 or those that follow (ch annels 3, 4, 5, etc.) can be set as a slave channel. (4) two or more slave channels can be set for one master channel. (5) when two or more master channels are to be used, slave channels with a master channel between them may not be set. example: if channels 0 and 4 are set as master channel s, channels 1 to 3 can be set as the slave channels of master channel 0. channels 5 to 7 cannot be set as the slave channels of master channel 0. (6) the operating clock for a slave channel in combination with a master channel must be the same as that of the master channel. the cks bit (bit 15 of the tmr0n register) of the slave c hannel that operates in combination with the master channel must be the same value as that of the master channel. (7) a master channel can transmit inttm0n (interrupt), start software trigger, and count clock to the lower channels. (8) a slave channel can use the inttm0n (interrupt), star t software trigger, and count clock of the master channel, but it cannot transmit its own inttm0n (i nterrupt), start software trigger, and count clock to the lower channel. (9) a master channel cannot use the inttm0n (interrupt), start software trigger, and count clock from the higher master channel. (10) to simultaneously start channels that operate in combination, the ts0n bit of the channels in combination must be set at the same time. (11) during a counting operation, the ts0n bit of all channels that operate in combination or only the master channel can be set. ts0n of only a slave channel cannot be set. (12) to stop the channels in combination simultaneously, the tt0n bit of the channels in combination must be set at the same time. remark n = 0 to 7 chapter 6 timer array unit user?s manual u17854ej6v0ud 214 channel 1: slave channel 0: master channel group 1 (combination-operation function) * the operating clock of channel group 1 may be different from that of channel group 2. channel 2: slave channel 3: single-operation function channel 4: master channel 5: slave channel 6: single-operation function channel 7: single-operation function ck00 ck01 tau * a channel that singly operates may be between channel group 1 and channel group 2. channel group 2 (combination-operation function) 6.6.3 applicable range of basic ru les of combination-operation function the rules of the combination-operat ion function are applied in a channel group (a master channel and slave channels forming one combination-operation function). if two or more channel groups that do not operate in comb ination are specified, the bas ic rules of the combination- operation function in 6.6.2 basic rules of comb ination-operation function do not apply to the channel groups. example chapter 6 timer array unit user?s manual u17854ej6v0ud 215 6.7 operation of timer array unit as independent channel 6.7.1 operation as interval timer/square wave output (1) interval timer the timer array unit can be used as a reference timer that generates inttm0n (timer interrupt) at fixed intervals. the interrupt generation period can be calculated by the following expression. generation period of inttm0n (timer in terrupt) = period of count clock (set value of tdr0n + 1) (2) operation as square wave output to0k performs a toggle operation as soon as inttm0n has been generated, and outputs a square wave with a duty factor of 50%. the period and frequency for outputting a square wave from to0k can be calculated by the following expressions. ? period of square wave output from to0k = period of count clock (set value of tdr0n + 1) 2 ? frequency of square wave output from to0k = fr equency of count clock/{(set value of tdr0n + 1) 2} tcr0n operates as a down counter in the interval timer mode. tcr0n loads the value of tdr0n at the fi rst count clock after the channel start trigger bit (ts0n) is set to 1. if md0n0 of tmr0n = 0 at this time, inttm0n is not out put and to0k is not toggled. if md0n0 of tmr0n = 1, inttm0n is output and to0k is toggled. after that, tcr0n count down in synchronization with the count clock. when tcr0n = 0000h, inttm0n is output and to0k is toggled at the next count clock. at the same time, tcr0n loads the value of tdr0n again. after that, the same operation is repeated. tdr0n can be rewritten at any time. the new val ue of tdr0n becomes valid from the next period. figure 6-35. block diagram of operation as interval timer/square wave output timer counter (tcr0n) to0k pin interrupt signal (inttm0n) data register (tdr0n) interrupt controller output controller clock selection trigger selection operation clock ck00 ck01 ts0n remark n = 0 to 7, k = 0 to 6 chapter 6 timer array unit user?s manual u17854ej6v0ud 216 figure 6-36. example of basic timing of operati on as interval timer/square wave output (md0n0 = 1) ts0n te0n tdr0n tcr0n to0k inttm0n a a+1 b 0000h a+1 a+1 b+1 b+1 b+1 remark n = 0 to 7, k = 0 to 6 chapter 6 timer array unit user?s manual u17854ej6v0ud 217 figure 6-37. example of set contents of registers du ring operation as interval timer/square wave output (a) timer mode register 0n (tmr0n) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tmr0n cks0n 1/0 0 0 ccs0n 0 mas ter0n 0 sts0n2 0 sts0n1 0 sts0n0 0 cis0n1 0 cis0n0 0 0 0 md0n3 0 md0n2 0 md0n1 0 md0n0 1/0 operation mode of channel n 000b: interval timer setting of operation when counting is started 0: neither generates inttm0n nor inverts timer output when counting is started. 1: generates inttm0n and inverts timer output when counting is started. selection of ti0k pin input edge 00b: sets 00b because these are not used. start trigger selection 000b: selects only software start. slave/master selection 0: cleared to 0 when single-operation function is selected. count clock selection 0: selects operation clock. operation clock selection 0: selects ck00 as operation clock of channel n. 1: selects ck01 as operation clock of channel n. (b) timer output register 0 (to0) bit k to0 to0k 1/0 0: outputs 0 from to0k. 1: outputs 1 from to0k. (c) timer output enable register 0 (toe0) bit k toe0 toe0k 1/0 0: stops the to0k output operation by counting operation. 1: enables the to0k output operation by counting operation. (d) timer output level register 0 (tol0) bit k tol0 tol0k 0 0: cleared to 0 when tom0k = 0 (toggle mode) (e) timer output mode register 0 (tom0) bit k tom0 tom0k 0 0: sets toggle mode. remark n = 0 to 7, k = 0 to 6 chapter 6 timer array unit user?s manual u17854ej6v0ud 218 figure 6-38. operation procedure of inte rval timer/square wave output function software operation hardware status power-off status (clock supply is stopped and writing to each register is disabled.) sets the tau0en bit of the per0 register to 1. power-on status. each channel stops operating. (clock supply is started and writing to each register is enabled.) tau default setting sets the tps0 register. determines clock frequencies of ck00 and ck01. sets the tmr0n register (determines operation mode of channel). sets interval (period) value to the tdr0n register. channel stops operating. (clock is supplied and some power is consumed.) channel default setting to use the to0k output clears the tom0k bit of the tom0 register to 0 (toggle mode). clears the tol0k bit to 0. sets the to0k bit and determines default level of the to0k output. sets toe0k to 1 and enables operation of to0k. clears the port register and port mode register to 0. the to0k pin goes into hi-z output state. the to0k default setting level is output when the port mode register is in the output mode and the port register is 0. to0k does not change because channel stops operating. the to0k pin outputs the to0k set level. operation start sets toe0k to 1 (only when operation is resumed). sets the ts0n bit to 1. the ts0n bit automatically returns to 0 because it is a trigger bit. te0n = 1, and count operation starts. value of tdr0n is loaded to tcr0n at the count clock input. inttm0n is generated and to0k performs toggle operation if the md0n0 bit of the tmr0n register is 1. during operation set values of tmr0n, tom0, and tol0 registers cannot be changed. set value of the tdr0n register can be changed. the tcr0n register can always be read. the tsr0n register is not used. set values of the to0 and toe0 registers can be changed. counter (tcr0n) counts down. when count value reaches 0000h, the value of tdr0n is loaded to tcr0n again and the count operation is continued. by detecting tcr0n = 0000h, inttm0n is generated and to0k performs toggle operation. after that, the above operation is repeated. the tt0n bit is set to 1. the tt0n bit automatically returns to 0 because it is a trigger bit. te0n = 0, and count operation stops. tcr0n holds count value and stops. the to0k output is not initialized but holds current status. operation stop toe0k is cleared to 0 and value is set to to0 regi ster. the to0k pin outputs the to0k set level. tau stop to hold the to0k pin output level clears to0k bit to 0 after the value to be held is set to the port register. when holding the to0k pin outpu t level is not necessary switches the port mode register to input mode. the to0k pin output level is held by port function. the to0k pin output level goes into hi-z output state. the tau0en bit of the per0 register is cleared to 0. power-off status all circuits are initialized and sfr of each channel is also initialized. (the to0k bit is cleared to 0 and the to0k pin is set to port mode.) remark n = 0 to 7, k = 0 to 6 operation is resumed. chapter 6 timer array unit user?s manual u17854ej6v0ud 219 6.7.2 operation as external event counter the timer array unit can be used as an external event counter that counts the number of times the valid input edge (external event) is detected in the ti0k pin. when a specified count value is reached, the event counter generates an interrupt. the specified number of counts ca n be calculated by the following expression. specified number of counts = set value of tdr0n + 1 tcr0n operates as a down counter in the event counter mode. when the channel start trigger bit (ts0n) is set to 1, tcr0n loads the value of tdr0n. tcr0n counts down each time the valid input edge of the ti0k pin has been detected. when tcr0n = 0000h, tcr0n loads the value of tdr 0n again, and outputs inttm0n. after that, the above operation is repeated. to0k must not be used because its waveform depends on the external event and irregular. tdr0n can be rewritten at any time. the new value of tdr0n becomes valid during the next count period. figure 6-39. block diagram of oper ation as external event counter timer counter (tcr0n) edge detection interrupt signal (inttm0n) ti0k pin data register (tdr0n) interrupt controller clock selection trigger selection ts0n remark n = 0 to 7, k = 0 to 6 figure 6-40. example of basic timing of operation as external event counter ts0n te0n ti0k tdr0n tcr0n 0003h 0002h 0 0000h 1 3 0 1 2 0 1 2 1 2 3 2 inttm0n 4 events 4 events 3 events remark n = 0 to 7, k = 0 to 6 chapter 6 timer array unit user?s manual u17854ej6v0ud 220 figure 6-41. example of set contents of registers in external event counter mode (a) timer mode register 0n (tmr0n) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tmr0n cks0n 1/0 0 0 ccs0n 1 mas ter0n 0 sts0n2 0 sts0n1 0 sts0n0 0 cis0n1 1/0 cis0n0 1/0 0 0 md0n3 0 md0n2 1 md0n1 1 md0n0 0 operation mode of channel n 011b: event count mode setting of operation when counting is started 0: neither generates inttm0n nor inverts timer output when counting is started. selection of ti0k pin input edge 00b: detects falling edge. 01b: detects rising edge. 10b: detects both edges. 11b: setting prohibited start trigger selection 000b: selects only software start. slave/master selection 0: cleared to 0 when single-operation function is selected. count clock selection 1: selects the ti0k pin input valid edge. operation clock selection 0: selects ck00 as operation clock of channel n. 1: selects ck01 as operation clock of channel n. (b) timer output register 0 (to0) bit k to0 to0k 0 0: outputs 0 from to0k. (c) timer output enable register 0 (toe0) bit k toe0 toe0k 0 0: stops the to0k output operation by counting operation. (d) timer output level register 0 (tol0) bit k tol0 tol0k 0 0: cleared to 0 when tom0k = 0 (toggle mode). (e) timer output mode register 0 (tom0) bit k tom0 tom0k 0 0: sets toggle mode. remark n = 0 to 7, k = 0 to 6 chapter 6 timer array unit user?s manual u17854ej6v0ud 221 figure 6-42. operation procedure when ex ternal event counter function is used software operation hardware status power-off status (clock supply is stopped and writing to each register is disabled.) sets the tau0en bit of the per0 register to 1. power-on status. each channel stops operating. (clock supply is started and writing to each register is enabled.) tau default setting sets the tps0 register. determines clock frequencies of ck00 and ck01. channel default setting sets the tmr0n register (determines operation mode of channel). sets number of counts to the tdr0n register. clears the toe0k bit of the toe0 register to 0. channel stops operating. (clock is supplied and some power is consumed.) operation start sets the ts0n bit to 1. the ts0n bit automatically returns to 0 because it is a trigger bit. te0n = 1, and count operation starts. value of tdr0n is loaded to tcr0n and detection of the ti0k pin input edge is awaited. during operation set value of the tdr0n register can be changed. the tcr0n register can always be read. the tsr0n register is not used. set values of tmr0n, tom0, tol0, to0, and toe0 registers cannot be changed. counter (tcr0n) counts down each time input edge of the ti0k pin has been detected. when count value reaches 0000h, the value of tdr0n is loaded to tcr0n again, and the count operation is continued. by detecting tcr0n = 0000h, the inttm0n output is generated. after that, the above operation is repeated. operation stop the tt0n bit is set to 1. the tt0n bit automatically returns to 0 because it is a trigger bit. te0n = 0, and count operation stops. tcr0n holds count value and stops. tau stop the tau0en bit of the per0 register is cleared to 0. power-off status all circuits are initialized and sfr of each channel is also initialized. remark n = 0 to 7, k = 0 to 6 operation is resumed. chapter 6 timer array unit user?s manual u17854ej6v0ud 222 6.7.3 operation as frequency divider the timer array unit can be used as a frequency divider that divides a clock input to the ti0k pin and outputs the result from to0k. the divided clock frequency output from to0k c an be calculated by the following expression. ? when rising edge/falling edge is selected: divided clock frequency = input clock frequency/{(set value of tdr0n + 1) 2} ? when both edges are selected: divided clock frequency ? input clock frequency/(set value of tdr0n + 1) tcr0n operates as a down counter in the interval timer mode. after the channel start trigger bit (ts0n) is set to 1, t cr0n loads the value of tdr0n when the ti0k valid edge is detected. if md0n0 of tmr0n = 0 at this time, inttm0n is not output and to0k is not toggled. if md0n0 of tmr0n = 1, inttm0n is output an d to0k is toggled. after that, tcr0n counts down at t he valid edge of ti0k. when tcr0n = 0000h , it toggles to0k. at the same time, tcr0n loads the value of t dr0n again, and continues counting. if detection of both the edges of ti0k is selected, the duty factor error of the input clock affects the divided clock period of the to0k output. the period of the to0k output clock includes a sa mpling error of one period of the operation clock. clock period of to0k output = ideal to0k output clock period operation clock period (error) tdr0n can be rewritten at any time. the new value of tdr0n becomes valid during the next count period. figure 6-43. block diagram of operation as frequency divider timer counter (tcr0n) edge detection ti0k pin data register (tdr0n) clock selection trigger selection ts0n to0k pin output controller remark n = 0 to 7, k = 0 to 6 chapter 6 timer array unit user?s manual u17854ej6v0ud 223 figure 6-44. example of basic timing of operation as frequency divider (md0n0 = 1) ts0n te0n ti0k tdr0n tcr0n to0k inttm0n 0002h divided by 6 0001h 0 0000h 1 2 0 1 2 0 1 0 1 0 1 0 1 0 1 2 divided by 4 remark n = 0 to 7, k = 0 to 6 chapter 6 timer array unit user?s manual u17854ej6v0ud 224 figure 6-45. example of set contents of registers when frequency divider is used (a) timer mode register 0n (tmr0n) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tmr0n cks0n 1/0 0 0 ccs0n 1 mas ter0n 0 sts0n2 0 sts0n1 0 sts0n0 0 cis0n1 1/0 cis0n0 1/0 0 0 md0n3 0 md0n2 0 md0n1 0 md0n0 1/0 operation mode of channel n 000b: interval timer setting of operation when counting is started 0: neither generates inttm0n nor inverts timer output when counting is started. 1: generates inttm0n and inverts timer output when counting is started. selection of ti0k pin input edge 00b: detects falling edge. 01b: detects rising edge. 10b: detects both edges. 11b: setting prohibited start trigger selection 000b: selects only software start. slave/master selection 0: cleared to 0 when single-operation function is selected. count clock selection 1: selects the ti0k pin input valid edge. operation clock selection 0: selects ck00 as operation clock of channel n. 1: selects ck01 as operation clock of channel n. (b) timer output register 0 (to0) bit k to0 to0k 1/0 0: outputs 0 from to0k. 1: outputs 1 from to0k. (c) timer output enable register 0 (toe0) bit k toe0 toe0k 1/0 0: stops the to0k output operation by counting operation. 1: enables the to0k output operation by counting operation. (d) timer output level register 0 (tol0) bit k tol0 tol0k 0 0: cleared to 0 when tom0k = 0 (toggle mode) (e) timer output mode register 0 (tom0) bit k tom0 tom0k 0 0: sets toggle mode. remark n = 0 to 7, k = 0 to 6 chapter 6 timer array unit user?s manual u17854ej6v0ud 225 figure 6-46. operation procedure when frequency divider function is used software operation hardware status power-off status (clock supply is stopped and writing to each register is disabled.) sets the tau0en bit of the per0 register to 1. power-on status. each channel stops operating. (clock supply is started and writing to each register is enabled.) tau default setting sets the tps0 register. determines clock frequencies of ck00 and ck01. sets the tmr0n register (determines operation mode of channel). sets interval (period) value to the tdr0n register. channel stops operating. (clock is supplied and some power is consumed.) channel default setting clears the tom0k bit of the tom0 register to 0 (toggle mode). clears the tol0k bit to 0. sets the to0k bit and determines default level of the to0k output. sets toe0k to 1 and enables operation of to0k. clears the port register and port mode register to 0. the to0k pin goes into hi-z output state. the to0k default setting level is output when the port mode register is in output mode and the port register is 0. to0k does not change because channel stops operating. the to0k pin outputs the to0k set level. operation start sets the toe0k to 1 (only when operation is resumed). sets the ts0n bit to 1. the ts0n bit automatically returns to 0 because it is a trigger bit. te0n = 1, and count operation starts. value of tdr0n is loaded to tcr0n at the count clock input. inttm0n is generated and to0k performs toggle operation if the md0n0 bit of the tmr0n register is 1. during operation set value of the tdr0n register can be changed. the tcr0n register can always be read. the tsr0n register is not used. set values of to0 and toe0 registers can be changed. set values of tmr0n, tom0, and tol0 registers cannot be changed. counter (tcr0n) counts down. when count value reaches 0000h, the value of tdr0n is loaded to tcr0n again, and the count operation is continued. by detecting tcr0n = 0000h, inttm0n is generated and to0k performs toggle operation. after that, the above operation is repeated. the tt0n bit is set to 1. the tt0n bit automatically returns to 0 because it is a trigger bit. te0n = 0, and count operation stops. tcr0n holds count value and stops. the to0k output is not initialized but holds current status. operation stop toe0k is cleared to 0 and value is set to the to0 register. the to0k pin outputs the to0k set level. to hold the to0k pin output level clears to0k bit to 0 after the value to be held is set to the port register. when holding the to0k pin output level is not necessary switches the port mode register to input mode. the to0k pin output level is held by port function. the to0k pin output level goes into hi-z output state. tau stop the tau0en bit of the per0 register is cleared to 0. power-off status all circuits are initialized and sfr of each channel is also initialized. (the to0k bit is cleared to 0 and the to0k pin is set to port mode). remark n = 0 to 7, k = 0 to 6 operation is resumed. chapter 6 timer array unit user?s manual u17854ej6v0ud 226 6.7.4 operation as input pu lse interval measurement the count value can be captur ed at the ti0k valid edge and the interval of the pulse input to ti0k can be measured. the pulse interval can be calculated by the following expression. ti0k input pulse interval = period of count clock ((10000h tsr0n: ovf) + (capture value of tdr0n + 1)) caution the ti0k pin input is sampled using the ope rating clock selected with the cks0n bit of the tmr0n register, so an error equal to the number of operating clocks occurs. tcr0n operates as an up counter in the capture mode. when the channel start trigger (ts0n) is set to 1, tcr 0n counts up from 0000h in synchronization with the count clock. when the ti0k pin input valid edge is det ected, the count value is transferred (captured) to tdr0n and, at the same time, the counter (tcr0n) is cleared to 0000h, and the in ttm0n is output. if the counter overflows at this time, the ovf bit of the tsr0n register is set to 1. if the count er does not overflow, the ovf bit is cleared. after that, the above operation is repeated. as soon as the count value has been capt ured to the tdr0n register, the ovf bit of the tsr0n register is updated depending on whether the counter overflow s during the measurement pe riod. therefore, the ov erflow status of the captured value can be checked. if the counter reaches a full count for two or more periods , it is judged to be an overflow occurrence, and the ovf bit of the tsr0n register is set to 1. however, the ovf bit is configured as a cumulative flag, the correct interval value cannot be measured if an overflow occurs more than once. set sts0n2 to sts0n0 of the tmr0n regi ster to 001b to use the valid edges of ti0k as a start trigger and a capture trigger. when te0n = 1, instead of the ti0k pin input, a software operation (ts0n = 1) can be used as a capture trigger. figure 6-47. block diagram of operatio n as input pulse interval measurement timer counter (tcr0n) interrupt signal (inttm0n) data register (tdr0n) interrupt controller clock selection trigger selection operation clock ck00 ck01 edge detection ti0k pin ts0n remark n = 0 to 7, k = 0 to 6 chapter 6 timer array unit user?s manual u17854ej6v0ud 227 figure 6-48. example of basic timing of operati on as input pulse interval measurement (md0n0 = 0) ts0n te0n ti0k tdr0n tcr0n 0000h c b 0000h a c d inttm0n ffffh b a d ovf0n remark n = 0 to 7, k = 0 to 6 chapter 6 timer array unit user?s manual u17854ej6v0ud 228 figure 6-49. example of set contents of registers to measure input pulse interval (a) timer mode register 0n (tmr0n) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tmr0n cks0n 1/0 0 0 ccs0n 0 mas ter0n 0 sts0n2 0 sts0n1 0 sts0n0 1 cis0n1 1/0 cis0n0 1/0 0 0 md0n3 0 md0n2 1 md0n1 0 md0n0 1/0 operation mode of channel n 010b: ca p ture mode setting of operation when counting is started 0: does not generate inttm0n when counting is started. 1: generates inttm0n when counting is started. selection of ti0k pin input edge 00b: detects falling edge. 01b: detects rising edge. 10b: detects both edges. 11b: setting prohibited capture trigger selection 001b: selects the ti0k pin input valid edge. slave/master selection 0: cleared to 0 when single-operation function is selected. count clock selection 0: selects operation clock. operation clock selection 0: selects ck00 as operation clock of channel n. 1: selects ck01 as operation clock of channel n. (b) timer output register 0 (to0) bit k to0 to0k 0 0: outputs 0 from to0k. (c) timer output enable register 0 (toe0) bit k toe0 toe0k 0 0: stops to0k output operation by counting operation. (d) timer output level register 0 (tol0) bit k tol0 tol0k 0 0: cleared to 0 when tom0k = 0 (toggle mode). (e) timer output mode register 0 (tom0) bit k tom0 tom0k 0 0: sets toggle mode. remark n = 0 to 7, k = 0 to 6 chapter 6 timer array unit user?s manual u17854ej6v0ud 229 figure 6-50. operation procedure when input pulse interval measurement function is used software operation hardware status power-off status (clock supply is stopped and writing to each register is disabled.) sets the tau0en bit of the per0 register to 1. power-on status. each channel stops operating. (clock supply is started and writing to each register is enabled.) tau default setting sets the tps0 register. determines clock frequencies of ck00 and ck01. channel default setting sets the tmr0n register (determines operation mode of channel). channel stops operating. (clock is supplied and some power is consumed.) operation start sets ts0n bit to 1. the ts0n bit automatically returns to 0 because it is a trigger bit. te0n = 1, and count operation starts. tcr0n is cleared to 0000h at the count clock input. when the md0n0 bit of the tmr0n register is 1, inttm0n is generated. during operation set values of only the cis0n1 and cis0n0 bits of the tmr0n register can be changed. the tdr0n register can always be read. the tcr0n register can always be read. the tsr0n register can always be read. set values of tom0, tol0, to0, and toe0 registers cannot be changed. counter (tcrn) counts up from 0000h. when the ti0k pin input valid edge is detected, the count value is transferred (captured) to tdr0n. at the same time, tcr0n is cleared to 0000h, and the inttm0n signal is generated. if an overflow occurs at this time, the ovf bit of the tsr0n register is set; if an overflow does not occur, the ovf bit is cleared. after that, the above operation is repeated. operation stop the tt0n bit is set to 1. the tt0n bit automatically returns to 0 because it is a trigger bit. te0n = 0, and count operation stops. tcr0n holds count value and stops. the ovf bit of the tsr0n register is also held. tau stop the tau0en bit of the per0 register is cleared to 0. power-off status all circuits are initialized and sfr of each channel is also initialized. remark n = 0 to 7, k = 0 to 6 operation is resumed. chapter 6 timer array unit user?s manual u17854ej6v0ud 230 6.7.5 operation as input signal hi gh-/low-level width measurement by starting counting at one edge of ti 0k and capturing the number of count s at another edge, the signal width (high-level width/low-level width) of ti0k can be measured. the signal width of ti0k can be calculated by the following expression. signal width of ti0k input = period of count clock ((10000h tsrn: ovf) + (capture value of tdr0n + 1)) caution the ti0k pin input is sampled using the ope rating clock selected with the cks0n bit of the tmr0n register, so an error equal to the number of operating clocks occurs. tcr0n operates as an up counter in the capture & one-count mode. when the channel start trigger (ts0n) is set to 1, te0n is set to 1 and the ti0k pin st art edge detection wait status is set. when the ti0k start valid edge (rising edge of ti0k when the high-level width is to be measured) is detected, the counter counts up in synchronization with the count clock. when the valid capture edge (falling edge of ti0k when the high-level width is to be measured) is det ected later, the count value is transfe rred to tdr0n and, at the same time, inttm0n is output. if the counter overflows at this time, the ovf bit of the tsr0n register is set to 1. if the counter does not overflow, the ovf bit is cleared. tcr0n stops at the value ?value transferred to tdr0n + 1?, and the ti0k pin start edge detection wait status is set. after that, the above operation is repeated. as soon as the count value has been capt ured to the tdr0n register, the ovf bit of the tsr0n register is updated depending on whether the counter overflow s during the measurement pe riod. therefore, the ov erflow status of the captured value can be checked. if the counter reaches a full count for two or more periods , it is judged to be an overflow occurrence, and the ovf bit of the tsr0n register is set to 1. however, the ovf bi t is configured as an integral flag, and the correct interval value cannot be measured if an overflow occurs more than once. whether the high-level width or low-le vel width of the ti0k pin is to be measured can be selected by using the cis0n1 and cis0n0 bits of the tmr0n register. because this function is used to measure the signal width of the ti0k pin input, ts0n cannot be set to 1 while te0n is 1. cis0n1, cis0n0 of tmr0n = 10b: low-level width is measured. cis0n1, cis0n0 of tmr0n = 11b: high-level width is measured. figure 6-51. block diagram of operation as in put signal high-/low-le vel width measurement timer counter (tcr0n) interrupt signal (inttm0n) data register (tdr0n) interrupt controller clock selection trigger selection operation clock ck00 ck01 edge detection ti0k pin remark n = 0 to 7, k = 0 to 6 chapter 6 timer array unit user?s manual u17854ej6v0ud 231 figure 6-52. example of basic timing of operati on as input signal high-/low- level width measurement ts0n te0n ti0k tdr0n tcr0n b 0000h a c inttm0n ffffh b a c ovf0n 0000h remark n = 0 to 7, k = 0 to 6 chapter 6 timer array unit user?s manual u17854ej6v0ud 232 figure 6-53. example of set contents of regist ers to measure input signal high-/low-level width (a) timer mode register 0n (tmr0n) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tmr0n cks0n 1/0 0 0 ccs0n 0 mas ter0n 0 sts0n2 0 sts0n1 1 sts0n0 0 cis0n1 1 cis0n0 1/0 0 0 md0n3 1 md0n2 1 md0n1 0 md0n0 0 operation mode of channel n 110b: capture & one-count setting of operation when counting is started 0: does not generate inttm0n when counting is started. selection of ti0k pin input edge 10b: both edges (to measure low-level width) 11b: both edges (to measure high-level width) start trigger selection 010b: selects the ti0k pin input valid edge. slave/master selection 0: cleared to 0 when single-operation function is selected. count clock selection 0: selects operation clock. operation clock selection 0: selects ck00 as operation clock of channel n. 1: selects ck01 as operation clock of channel n. (b) timer output register 0 (to0) bit k to0 to0k 0 0: outputs 0 from to0k. (c) timer output enable register 0 (toe0) bit k toe0 toe0k 0 0: stops the to0k output operation by counting operation. (d) timer output level register 0 (tol0) bit k tol0 tol0k 0 0: cleared to 0 when tom0k = 0 (toggle mode). (e) timer output mode register 0 (tom0) bit k tom0 tom0k 0 0: sets toggle mode. remark n = 0 to 7, k = 0 to 6 chapter 6 timer array unit user?s manual u17854ej6v0ud 233 figure 6-54. operation procedure when input signal high-/low-level width measu rement function is used software operation hardware status power-off status (clock supply is stopped and writing to each register is disabled.) sets the tau0en bit of the per0 register to 1. power-on status. each channel stops operating. (clock supply is started and writing to each register is enabled.) tau default setting sets the tps0 register. determines clock frequencies of ck00 and ck01. channel default setting sets the tmr0n register (determines operation mode of channel). clears toe0k to 0 and stops operation of to0k. channel stops operating. (clock is supplied and some power is consumed.) sets the ts0n bit to 1. the ts0n bit automatically returns to 0 because it is a trigger bit. te0n = 1, and the ti0k pin start edge detection wait status is set. operation start detects ti0k pin input count start valid edge. clears tcr0n to 0000h and starts counting up. during operation set value of the tdr0n register can be changed. the tcr0n register can always be read. the tsr0n register is not used. set values of tmr0n, tom0, tol0, to0, and toe0 registers cannot be changed. when the ti0k pin start edge is detected, the counter (tcrn) counts up from 0000h. if a capture edge of the ti0k pin is detected, the count value is transferred to tdr0n and inttm0n is generated. if an overflow occurs at this time, the ovf bit of the tsr0n register is set; if an overflow does not occur, the ovf bit is cleared. tcr0n stops the count operation until the next ti0k pin start edge is detected. operation stop the tt0n bit is set to 1. tt0n bit automatically returns to 0 because it is a trigger bit. te0n = 0, and count operation stops. tcr0n holds count value and stops. the ovf bit of the tsr0n register is also held. tau stop the tau0en bit of per0 register is cleared to 0. power-off status all circuits are initialized and sfr of each channel is also initialized. remark n = 0 to 7, k = 0 to 6 operation is resumed. chapter 6 timer array unit user?s manual u17854ej6v0ud 234 6.8 operation of plural channels of timer array unit 6.8.1 operation as pwm function two channels can be used as a set to generate a pulse of any period and duty factor. the period and duty factor of the output pulse can be calculated by the following expressions. pulse period = {set value of tdr0n (master) + 1} count clock period duty factor [%] = {set value of tdr0m (s lave)}/{set value of tdr0n (master) + 1} 100 0% output: set value of tdr0m (slave) = 0000h 100% output: set value of tdr0m (slave) {set value of tdr0n (master) + 1} remark the duty factor exceeds 100% if the set value of tdr0m (slave) > (set value of tdr0n (master) + 1), it summarizes to 100% output. the master channel operates in the interval timer m ode and counts the periods. when the channel start trigger (ts0n) is set to 1, inttm0n is output. tcr0n coun ts down starting from the l oaded value of tdr0n, in synchronization with the count clock. when tcr0n = 0000h , inttm0n is output. tcr0n loads the value of tdr0n again. after that, it conti nues the similar operation. tcr0m of a slave channel operates in one-count mode, counts the duty fact or, and outputs a pwm waveform from the to0m pin. tcr0m of the slave c hannel loads the value of tdr0m, usi ng inttm0n of the master channel as a start trigger, and stops counting until the next start trigger (inttm0n of the master channel) is input. the output level of to0m bec omes active one count clock after generat ion of inttm0n from the master channel, and inactive when tcr0m = 0000h. caution to rewrite both tdr0n of the master channe l and tdr0m of the slave channel, a write access is necessary two times. the timing at which the values of t dr0n and tdr0m are loaded to tcr0n and trc0m is upon occurrence of inttm0n of the master channel. thus, when rewriting is performed split before and after occurrence of inttm0n of the master channel, the to0m pin cannot output the expected waveform. to rewrit e both tdr0n of the master and tdr0m of the slave, therefore, be sure to rewrite both the registers immediately after inttm0n is generated from the master channel. remark n = 0, 2, 4 m = n + 1 chapter 6 timer array unit user?s manual u17854ej6v0ud 235 figure 6-55. block diagram of operation as pwm function timer counter (tcr0n) interrupt signal (inttm0n) data register (tdr0n) interrupt controller clock selection trigger selection operation clock ck00 ck01 ts0n timer counter (tcr0m) interrupt signal (inttm0m) data register (tdr0m) interrupt controller clock selection trigger selection operation clock ck00 ck01 to0m pin output controller master channel (interval timer mode) slave channel (one-count mode) remark n = 0, 2, 4 m = n + 1 chapter 6 timer array unit user?s manual u17854ej6v0ud 236 figure 6-56. example of basic ti ming of operation as pwm function ts0n te0n tdr0n tcr0n to0n inttm0n a b 0000h ts0m te0m tdr0m tcr0m to0m inttm0m c c d 0000h c d master channel slave channel a+1 a+1 b+1 ffffh ffffh remark n = 0, 2, 4 m = n + 1 chapter 6 timer array unit user?s manual u17854ej6v0ud 237 figure 6-57. example of set contents of register s when pwm function (master channel) is used (a) timer mode register 0n (tmr0n) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tmr0n cks0n 1/0 0 0 ccs0n 0 mas ter0n 1 sts0n2 0 sts0n1 0 sts0n0 0 cis0n1 0 cis0n0 0 0 0 md0n3 0 md0n2 0 md0n1 0 md0n0 1 operation mode of channel n 000b: interval timer setting of operation when counting is started 1: generates inttm0n when counting is started. selection of ti0n pin input edge 00b: sets 00b because these are not used. start trigger selection 000b: selects only software start. slave/master selection 1: channel 1 is set as master channel. count clock selection 0: selects operation clock. operation clock selection 0: selects ck00 as operation clock of channel n. 1: selects ck01 as operation clock of channel n. (b) timer output register 0 (to0) bit n to0 to0n 0 0: outputs 0 from to0n. (c) timer output enable register 0 (toe0) bit n toe0 toe0n 0 0: stops the to0n output operation by counting operation. (d) timer output level register 0 (tol0) bit n tol0 tol0n 0 0: cleared to 0 when tom0n = 0 (toggle mode). (e) timer output mode register 0 (tom0) bit n tom0 tom0n 0 0: sets toggle mode. remark n = 0, 2, 4 chapter 6 timer array unit user?s manual u17854ej6v0ud 238 figure 6-58. example of set contents of regist ers when pwm function (slave channel) is used (a) timer mode register 0m (tmr0m) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tmr0m cks0m 1/0 0 0 ccs0m 0 mas ter0 m 0 sts0m2 1 sts0m1 0 sts0m0 0 cis0m1 0 cis0m0 0 0 0 md0m3 1 md0m2 0 md0m1 0 md0m0 1 operation mode of channel m 100b: one-count mode start trigger during operation 1: trigger input is valid. selection of ti0m pin input edge 00b: sets 00b because these are not used. start trigger selection 100b: selects inttm0n of master channel. slave/master selection 0: channel 0 is set as slave channel. count clock selection 0: selects operation clock. operation clock selection 0: selects ck00 as operation clock of channel m. 1: selects ck01 as operation clock of channel m. * make the same setting as master channel. (b) timer output register 0 (to0) bit m to0 to0m 1/0 0: outputs 0 from to0m. 1: outputs 1 from to0m. (c) timer output enable register 0 (toe0) bit m toe0 toe0m 1/0 0: stops the to0m output operation by counting operation. 1: enables the to0m output operation by counting operation. (d) timer output level register 0 (tol0) bit m tol0 tol0m 1/0 0: positive logic output (active-high) 1: inverted output (active-low) (e) timer output mode register 0 (tom0) bit n tom0 tom0n 1 1: sets the combination-operation mode. remark n = 0, 2, 4 m = n + 1 chapter 6 timer array unit user?s manual u17854ej6v0ud 239 figure 6-59. operation procedure wh en pwm function is used (1/2) software operation hardware status power-off status (clock supply is stopped and writing to each register is disabled.) sets the tau0en bit of the per0 register to 1. power-on status. each channel stops operating. (clock supply is started and writing to each register is enabled.) tau default setting sets the tps0 register. determines clock frequencies of ck00 and ck01. sets the tmr0n and tmr0m registers of two channels to be used (determines oper ation mode of channels). an interval (period) value is set to the tdr0n register of the master channel, and a duty factor is set to the tdr0m register of the slave channel. channel stops operating. (clock is supplied and some power is consumed.) channel default setting sets slave channel. the tom0m bit of the tom0 register is set to 1 (combination-operation mode). sets the tol0mbit. sets the to0m bit and determines default level of the to0m output. sets toe0m to 1 and enables operation of to0m. clears the port register and port mode register to 0. the to0n pin goes into hi-z output state. the to0n default setting level is output when the port mode register is in output mode and the port register is 0. to0m does not change because channel stops operating. the to0m pin outputs the to0m set level. remark n = 0, 2, 4 m = n + 1 chapter 6 timer array unit user?s manual u17854ej6v0ud 240 figure 6-59. operation procedure wh en pwm function is used (2/2) software operation hardware status operation start sets toe0m (slave) to 1 (only when operation is resumed). the ts0n (master) and ts0m (slave) bits of the ts0 register are set to 1 at the same time. the ts0n and ts0m bits automatically return to 0 because they are trigger bits. te0n = 1, te0m = 1 when the master channel starts counting, inttm0n is generated. triggered by this interrupt, the slave channel also starts counting. during operation set values of the tmr0n and tmr0m registers cannot be changed. set values of the tdr0n and tdr0m registers can be changed after inttm0n of the master channel is generated. the tcr0n and tcr0m registers can always be read. the tsr0n and tsr0m registers are not used. set values of the tol0, to0, and toe0 registers cannot be changed. the counter of the master channel loads the tdr0n value to tcr0n, and counts down. when the count value reaches tcr0n = 0000h, inttm0n output is generated. at the same time, the value of the tdr0n register is loaded to tcr0n, and the counter starts counting down again. at the slave channel, the value of tdr0m is loaded to tcr0m, triggered by inttm0n of the master channel, and the counter starts counting down. the output level of to0m becomes active one c ount clock after generation of the inttm0n output from the master channel. it becomes inactive when tcr0m = 0000h, and the counting operation is stopped. after that, the above operation is repeated. the tt0n (master) and tt0m (slave) bits are set to 1 at the same time. the tt0n and tt0m bits automatically return to 0 because they are trigger bits. te0n, te0m = 0, and count operation stops. tcr0n and tcr0m hold count value and stops. the to0m output is not initialized but holds current status. operation stop toe0m of slave channel is cleared to 0 and value is set to the to0m register. the to0m pin outputs the to0n set level. to hold the to0m pin output levels clears to0m bit to 0 after the value to be held is set to the port register. when holding the to0m pin output levels is not necessary switches the port mode register to input mode. the to0m pin output levels is held by port function. the to0m pin output levels go are into hi-z output state. tau stop the tau0en bit of the per0 register is cleared to 0. power-off status all circuits are initialized and sfr of each channel is also initialized. (the to0m bit is cleared to 0 and the to0m pin is set to port mode.) remark n = 0, 2, 4 m = n + 1 operation is resumed. chapter 6 timer array unit user?s manual u17854ej6v0ud 241 6.8.2 operation as one-shot pulse output function by using two channels as a set, a one-shot pulse having any delay pulse width can be generated from the signal input to the ti0n pin. the delay time and pulse width can be ca lculated by the following expressions. delay time = {set value of tdr0n (master) + 2} count clock period pulse width = {set value of tdr0m (slave)} count clock period the master channel operates in the one-count mode and counts the delays. tcr0n of the master channel starts operating upon start trigger detection and tcr0n loads the value of tdr0n. tcr0n counts down from the value of tdr0n it has loaded, in synchronization with the count clock. when tcr0n = 0000h, it outputs inttm0n and stops counting until the next start trigger is detected. the slave channel operates in the one-co unt mode and counts the pulse width. tcr0m of the slave channel starts operation using inttm0n of the master channel as a start trigger, and loads t he tdr0m value. tcr0m counts down from the value of tdr0m it has load ed, in synchronization with the count value. when tcr0m = 0000h, it outputs inttm0m and stops counting until the next start trigger (inttm0n of the master channel) is detected. the output level of to0m becomes active one count clock after genera tion of inttm0n from the master channel, and inactive when tcr0m = 0000h. instead of using the ti0n pin input, a one- shot pulse can also be output using the software operation (ts0n = 1) as a start trigger. caution the timing of loading of tdr0n of the master channel is different from that of tdr0m of the slave channel. if tdr0n and tdr0m are rewritten during operation, ther efore, an illegal waveform is output. be sure to rewrite tdr0n and tdr0m a fter inttm0n of the channel to be rewritten is generated. remark n = 0, 2, 4 m = n + 1 chapter 6 timer array unit user?s manual u17854ej6v0ud 242 figure 6-60. block diagram of operat ion as one-shot pulse output function timer counter (tcr0n) interrupt signal (inttm0n) data register (tdr0n) interrupt controller clock selection trigger selection operation clock ck00 ck01 ts0n timer counter (tcr0m) interrupt signal (inttm0m) data register (tdr0m) interrupt controller clock selection trigger selection operation clock ck00 ck01 to0m pin output controller master channel (one-count mode) slave channel (one-count mode) edge detection ti0n pin remark n = 0, 2, 4 m = n + 1 chapter 6 timer array unit user?s manual u17854ej6v0ud 243 figure 6-61. example of basic timing of operation as one-shot pulse output function te0n tdr0n tcr0n to0n inttm0n a b 0000h ts0m te0m tdr0m tcr0m to0m inttm0m 0000h b master channel slave channel a+2 b a+2 ffffh ffffh ti0n ts0n remark n = 0, 2, 4 m = n + 1 chapter 6 timer array unit user?s manual u17854ej6v0ud 244 figure 6-62. example of set contents of registers when one-shot pulse output func tion is used (master channel) (a) timer mode register 0n (tmr0n) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tmr0n cks0n 1/0 0 0 ccs0n 0 mas ter0n 1 sts0n2 0 sts0n1 0 sts0n0 1 cis0n1 1/0 cis0n0 1/0 0 0 md0n3 1 md0n2 0 md0n1 0 md0n0 0 operation mode of channel n 100b: one-count mode start trigger during operation 0: trigger input is invalid. selection of ti0n pin input edge 00b: detects falling edge. 01b: detects rising edge. 10b: detects both edges. 11b: setting prohibited start trigger selection 001b: selects the ti0n pin input valid edge. slave/master selection 1: channel 1 is set as master channel. count clock selection 0: selects operation clock. operation clock selection 0: selects ck00 as operation clock of channels n. 1: selects ck01 as operation clock of channels n. (b) timer output register 0 (to0) bit n to0 to0n 0 0: outputs 0 from to0n. (c) timer output enable register 0 (toe0) bit n toe0 toe0n 0 0: stops the to0n output operation by counting operation. (d) timer output level register 0 (tol0) bit n tol0 tol0n 0 0: cleared to 0 when tom0n = 0 (toggle mode). (e) timer output mode register 0 (tom0) bit n tom0 tom0n 0 0: sets toggle mode. remark n = 0, 2, 4 chapter 6 timer array unit user?s manual u17854ej6v0ud 245 figure 6-63. example of set contents of registers when one-shot pulse output func tion is used (slave channel) (a) timer mode register 0m (tmr0m) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tmr0m cks0m 1/0 0 0 ccs0m 0 mas ter0 m 0 sts0m2 1 sts0m1 0 sts0m0 0 cis0m1 0 cis0m0 0 0 0 md0m3 1 md0m2 0 md0m1 0 md0m0 0 operation mode of channel m 100b: one-count mode start trigger during operation 0: trigger input is invalid. selection of ti0m pin input edge 00b: sets 00b because these are not used. start trigger selection 100b: selects inttm0n of master channel. slave/master selection 0: channel 0 is set as slave channel. count clock selection 0: selects operation clock. operation clock selection 0: selects ck00 as operation clock of channel m. 1: selects ck01 as operation clock of channel m. * make the same setting as master channel. (b) timer output register 0 (to0) bit m to0 to0m 1/0 0: outputs 0 from to0m. 1: outputs 1 from to0m. (c) timer output enable register 0 (toe0) bit m toe0 toe0m 1/0 0: stops the to0m output operation by counting operation. 1: enables the to0m output operation by counting operation. (d) timer output level register 0 (tol0) bit m tol0 tol0m 1/0 0: positive logic output (active-high) 1: inverted output (active-low) (e) timer output mode register 0 (tom0) bit n tom0 tom0n 1 1: sets the combination-operation mode. remark n = 0, 2, 4 m = n + 1 chapter 6 timer array unit user?s manual u17854ej6v0ud 246 figure 6-64. operation procedure of one-shot pulse output function (1/2) software operation hardware status power-off status (clock supply is stopped and writing to each register is disabled.) sets the tau0en bit of the per0 register to 1. power-on status. each channel stops operating. (clock supply is started and writing to each register is enabled.) tau default setting sets the tps0 register. determines clock frequencies of ck00 and ck01. sets the tmr0n and tmr0m registers of two channels to be used (determines oper ation mode of channels). an output delay is set to the tdr0n register of the master channel, and a pulse width is set to the tdr0m register of the slave channel. channel stops operating. (clock is supplied and some power is consumed.) channel default setting sets slave channel. the tom0m bit of the tom0 register is set to 1 (combination-operation mode). sets the tol0m bit. sets the to0m bit and determines default level of the to0m output. sets toe0m to 1 and enables operation of to0m. clears the port register and port mode register to 0. the to0n pin goes into hi-z output state. the to0n default setting level is output when the port mode register is in output mode and the port register is 0. to0m does not change because channel stops operating. the to0m pin outputs the to0m set level. remark n = 0, 2, 4 m = n + 1 chapter 6 timer array unit user?s manual u17854ej6v0ud 247 figure 6-64. operation procedure of one-shot pulse output function (2/2) software operation hardware status sets toe0m (slave) to 1 (only when operation is resumed). the ts0n (master) and ts0m (slave) bits of the ts0 register are set to 1 at the same time. the ts0n and ts0m bits automatically return to 0 because they are trigger bits. te0n and te0m are set to 1 and the master channel enters the ti0n input edge detection wait status. counter stops operating. operation start detects the ti0n pin input valid edge of master channel. master channel starts counting. during operation set values of only the cisn1 and cisn0 bits of the tmr0n register can be changed. set values of the tmr0m, tdr0n, tdr0m, and tom0 registers cannot be changed. the tcr0n and tcr0m registers can always be read. the tsr0n and tsr0m registers are not used. set values of the tol0, to0, and toe0 registers can be changed. master channel loads the value of tdr0n to tcr0n when the ti0n pin valid input edge is detected, and the counter starts counting down. when the count value reaches tcr0n = 0000h, the inttm0n output is generated, and the counter stops until the next valid edge is input to the ti0n pin. the slave channel, triggered by inttm0n of the master channel, loads the value of tdr0m to tcr0m, and the counter starts counting down. the output level of to0m becomes active one count clock after generation of inttm0n from the master channel. it becomes inactive when tcr0m = 0000h, and the counting operation is stopped. after that, the above operation is repeated. the tt0n (master) and tt0m (slave) bits are set to 1 at the same time. the tt0n and tt0m bits automatically return to 0 because they are trigger bits. te0n, te0m = 0, and count operation stops. tcr0n and tcr0m hold count value and stops. the to0m output is not initialized but holds current status. operation stop toe0m of slave channel is cleared to 0 and value is set to the to0 register. the to0m pin outputs the to0n set level. to hold the to0m pin output levels clears to0m bit to 0 after the value to be held is set to the port register. when holding the to0m pin output levels is not necessary switches the port mode register to input mode. the to0m pin output levels is held by port function. the to0m pin output levels go are into hi-z output state. tau stop the tau0en bit of the per0 register is cleared to 0. power-off status all circuits are initialized and sfr of each channel is also initialized. (the to0m bit is cleared to 0 and the to0m pin is set to port mode.) remark n = 0, 2, 4 m = n + 1 operation is resumed. chapter 6 timer array unit user?s manual u17854ej6v0ud 248 6.8.3 operation as multiple pwm output function by extending the pwm function and using two or more sl ave channels, many pwm output signals can be produced. for example, when using two slave channels, the period and duty factor of an output pu lse can be calculated by the following expressions. pulse period = {set value of tdr0n (master) + 1} count clock period duty factor 1 [%] = {set value of tdr0m (s lave 1)}/{set value of tdr0n (master) + 1} 100 duty factor 2 [%] = {set value of tdr0m (s lave 2)}/{set value of tdr0n (master) + 1} 100 remark although the duty factor exceeds 100% if the set value of tdr0p (slave 1) > {set value of tdr0n (master) + 1} or if the {set value of tdr0q (slave 2)} > {set value of tdr0n (master) + 1}, it is summarized into 100% output. tcr0n of the master channel operates in the interval timer mode and counts the periods. tcr0p of the slave channel 1 operates in one-count mode, counts the du ty factor, and outputs a pwm waveform from the to0p pin. tcr0p l oads the value of tdr0p to tcr0p, using inttm0n of the master channel as a start trigger, and start counting down. when tcr0p = 0000h, tcr0p outputs inttm0p and st ops counting until the next start trigger (inttm0n of the master channel) has been i nput. the output level of to0p becomes active one count clock after generation of inttm0n from the ma ster channel, and inactive when tcr0p = 0000h. in the same way as tcr0p of the slave channel 1, t cr0q of the slave channel 2 operates in one-count mode, counts the duty factor, and outputs a pwm waveform from the to0q pin. tcr0q loads the value of tdr0q to tcr0q, using inttm0n of the master channel as a start tri gger, and starts counting down. when tcr0q = 0000h, tcr0q outputs inttm0q and stops counting until th e next start trigger (inttm0n of the master channel) has been input. the output level of to0q becomes active one count clock after generation of in ttm0n from the master channel, and inactive when tcr0q = 0000h. when channel 0 is used as the master channel as above, up to seven types of pwm signals can be output at the same time. caution to rewrite both tdr0n of the master channe l and tdr0p of the slave channel 1, write access is necessary at least twice. sin ce the values of tdr0n and tdr0p are loaded to tcr0n and tcr0p after inttm0n is generated from th e master channel, if rewriting is performed separately before and after generation of inttm0n from the mast er channel, the to0p pin cannot output the expected waveform. to rewrite both tdr0n of th e master and tdr0p of the slave, be sure to rewrite both the registers immediately after inttm0n is generated from th e master channel (this applies also to tdr0q of the slave channel 2) . remarks 1. n = 0, 2, 4 n < p < q 6 where p and q are consecutive integers following n (p = n + 1, q = n + 2) chapter 6 timer array unit user?s manual u17854ej6v0ud 249 figure 6-65. block diagram of operation as multiple pwm output function (output two types of pwms) timer counter (tcr0n) interrupt signal (inttm0n) data register (tdr0n) interrupt controller clock selection trigger selection operation clock ck00 ck01 ts0n timer counter (tcr0p) interrupt signal (inttm0p) data register (tdr0p) interrupt controller clock selection trigger selection operation clock ck00 ck01 to0p pin output controller master channel (interval timer mode) slave channel 1 (one-count mode) timer counter (tcr0q) interrupt signal (inttm0q) data register (tdr0q) interrupt controller clock selection trigger selection operation clock ck00 ck01 to0q pin output controller slave channel 2 (one-count mode) remarks 1. n = 0, 2, 4 2. p = n + 1 q = n + 2 chapter 6 timer array unit user?s manual u17854ej6v0ud 250 figure 6-66. example of basic timing of operation as mu ltiple pwm output function (output two types of pwms) ts0n te0n tdr0n tcr0n to0n inttm0n a b 0000h ts0p te0p tdr0p tcr0p to0p inttm0p c c d 0000h c d master channel slave channel 1 a+1 a+1 b+1 ffffh ffffh ts0q te0q tdr0q tcr0q to0q inttm0q e f 0000h e f slave channel 2 a+1 a+1 b+1 ffffh e f d remarks 1. n = 0, 2, 4 2. p = n + 1 q = n + 2 chapter 6 timer array unit user?s manual u17854ej6v0ud 251 figure 6-67. example of set contents of registers when multiple pwm output function (master channel) is used (a) timer mode register 0n (tmr0n) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tmr0n cks0n 1/0 0 0 ccs0n 0 mas ter0n 1 sts0n2 0 sts0n1 0 sts0n0 0 cis0n1 0 cis0n0 0 0 0 md0n3 0 md0n2 0 md0n1 0 md0n0 1 operation mode of channel n 000b: interval timer setting of operation when counting is started 1: generates inttm0n when counting is started. selection of ti0n pin input edge 00b: sets 00b because these are not used. start trigger selection 000b: selects only software start. slave/master selection 1: channel 1 is set as master channel. count clock selection 0: selects operation clock. operation clock selection 0: selects ck00 as operation clock of channel n. 1: selects ck01 as operation clock of channel n. (b) timer output register 0 (to0) bit n to0 to0n 0 0: outputs 0 from to0n. (c) timer output enable register 0 (toe0) bit n toe0 toe0n 0 0: stops the to0n output operation by counting operation. (d) timer output level register 0 (tol0) bit n tol0 tol0n 0 0: cleared to 0 when tom0n = 0 (toggle mode). (e) timer output mode register 0 (tom0) bit n tom0 tom0n 0 0: sets toggle mode. remark n = 0, 2, 4 chapter 6 timer array unit user?s manual u17854ej6v0ud 252 figure 6-68. example of set contents of registers when multiple pwm output function (slave channel) is used (output two types of pwms) (a) timer mode register 0p, 0q (tmr0p, tmr0q) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tmr0p cks0p 1/0 0 0 ccs0p 0 mas ter0p 0 sts0p2 1 sts0p1 0 sts0p0 0 cis0p1 0 cis0p0 0 0 0 md0p3 1 md0p2 0 md0p1 0 md0p0 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tmr0q cks0q 1/0 0 0 ccs0q 0 mas ter0q 0 sts0q2 1 sts0q1 0 sts0q0 0 cis0q1 0 cis0q0 0 0 0 md0q3 1 md0q2 0 md0q1 0 md0q0 1 operation mode of channel p, q 100b: one-count mode start trigger during operation 1: trigger input is valid. selection of ti0p and ti0q pin input edge 00b: sets 00b because these are not used. start trigger selection 100b: selects inttm0n of master channel. slave/master selection 0: channel 0 is set as slave channel. count clock selection 0: selects operation clock. operation clock selection 0: selects ck00 as operation clock of channel p, q. 1: selects ck01 as operation clock of channel p, q. * make the same setting as master channel. (b) timer output register 0 (to0) bit q bit p to0 to0q 1/0 to0p 1/0 0: outputs 0 from to0p or to0q. 1: outputs 1 from to0p or to0q. (c) timer output enable register 0 (toe0) bit q bit p toe0 toe0q 1/0 toe0p 1/0 0: stops the to0p or to0q output operation by counting operation. 1: enables the to0p or to0q output operation by counting operation. (d) timer output level register 0 (tol0) bit q bit p tol0 tol0q 1/0 tol0p 1/0 0: positive logic output (active-high) 1: inverted output (active-low) (e) timer output mode register 0 (tom0) bit q bit p tom0 tom0q 1 tom0p 1 1: sets the combination-operation mode. remark n = 0, 2, 4; p = n+1; q = n+2 chapter 6 timer array unit user?s manual u17854ej6v0ud 253 figure 6-69. operation procedure when mult iple pwm output function is used (1/2) software operation hardware status power-off status (clock supply is stopped and writing to each register is disabled.) sets the tau0en bit of the per0 register to 1. power-on status. each channel stops operating. (clock supply is started and writing to each register is enabled.) tau default setting sets the tps0 register. determines clock frequencies of ck00 and ck01. sets the tmr0n, tmr0p, and tmr0q registers of each channel to be used (determines operation mode of channels). an interval (period) value is set to the tdr0n register of the master channel, and a duty factor is set to the tdr0m register of the slave channel. channel stops operating. (clock is supplied and some power is consumed.) channel default setting sets slave channel. the tom0m bit of the tom0 register is set to 1 (combination-operation mode). clears the tol0p and tol0q bits to 0. sets the to0p and to0q bits and determines default level of the to0p and to0q outputs. sets toe0p or toe0q to 1 and enables operation of to0m. clears the port register and port mode register to 0. the to0n pin goes into hi-z output state. the to0p and to0q default setting levels are output when the port mode register is in output mode and the port register is 0. to0p or to0q does not change because channel stops operating. the to0p and to0q pins output the to0p and to0q set levels. remarks 1. n = 0, 2, 4 2. p = n + 1; q = n + 2 chapter 6 timer array unit user?s manual u17854ej6v0ud 254 figure 6-69. operation procedure when mult iple pwm output function is used (2/2) software operation hardware status operation start sets toe0p and toe0q (slave) to 1 (only when operation is resumed). the ts0n bit (master), and ts0p and ts0q (slave) bits of the ts0 register are set to 1 at the same time. the ts0n, ts0p, and ts0q bits automatically return to 0 because they are trigger bits. te0n = 1, te0p, te0q = 1 when the master channel starts counting, inttm0n is generated. triggered by this interrupt, the slave channel also starts counting. during operation set values of the tmr0n, tmr0p, tmr0q, tom0, and toe0 registers cannot be changed. set values of the tdr0n, tdr0p, and tdr0q registers can be changed after inttm0n of the master channel is generated. the tcr0n, tcr0p, and tcr0q registers can always be read. the tsr0n, tsr0p, and tsr 0q registers are not used. set values of the tom0, tol0, to0, and toe0 registers can be changed. the counter of the master channel loads the tdr0n value to tcr0n and counts down. when the count value reaches tcrn = 0000h, inttm0n output is generated. at the same time, the value of the tdr0n register is loaded to tcr0n, and the counter starts counting down again. at the slave channel 1, the values of tdr0p are transferred to tcr0p, triggered by inttm0n of the master channel, and the counter starts counting down. the output levels of to0p become active one count clock after generation of the inttm0n output from the master channel. it becomes inactive when tcr0p = 0000h, and the counting operation is stopped. at the slave channel 2, the values of tdr0q are transferred to tdr0q, triggered by inttm0n of the master channel, and the counter starts counting down. the output levels of to0q become active one count clock after generation of the inttm0n output from the master channel. it becomes inactive when tcr0q = 0000h, and the counting operation is stopped. after that, the above operation is repeated. the tt0n bit (master), tt0p, and tt0q (slave) bits are set to 1 at the same time. the tt0n, tt0p, and tt0q bits automatically return to 0 because they are trigger bits. te0n, te0p, te0q = 0, and count operation stops. tcr0n, tcr0p, and tcr0q hold count value and stops. the to0m output is not initialized but holds current status. operation stop toe0p or toe0q of slave channel is cleared to 0 and value is set to the to0p and to0q registers. the to0p and to0q pins output the to0p and to0q set levels. to hold the to0p and to0q pin output levels clears to0p and to0q bits to 0 after the value to be held is set to the port register. when holding the to0p and to0q pin output levels is not necessary switches the port mode register to input mode. the to0p and to0q pin output levels are held by port function. the to0p and to0q pin output levels go into hi-z output state. tau stop the tau0en bit of the per0 register is cleared to 0. power-off status all circuits are initialized and sfr of each channel is also initialized. (the to0p and to0q bits are cleared to 0 and the to0p and to0q pins are set to port mode.) remarks 1. n = 0, 2, 4 2. p = n + 1; q = n + 2 operation is resumed. user?s manual u17854ej6v0ud 255 chapter 7 real-time counter 7.1 functions of real-time counter the real-time counter ha s the following features. ? having counters of year, month, week, day, hour, minute, and second, and can count up to 99 years. ? constant-period interrupt function (period: 1 month to 0.5 seconds) ? alarm interrupt function (alarm: week, hour, minute) ? interval interrupt function ? pin output function of 1 hz ? pin output function of 512 hz or 16.384 khz or 32.768 khz 7.2 configuration of real-time counter the real-time counter includes the following hardware. table 7-1. configuration of real-time counter item configuration peripheral enable register 0 (per0) real-time counter control register 0 (rtcc0) real-time counter control register 1 (rtcc1) real-time counter control register 2 (rtcc2) sub-count register (rsubc) second count register (sec) minute count register (min) hour count register (hour) day count register (day) week count register (week) month count register (month) year count register (year) watch error correction register (subcud) alarm minute register (alarmwm) alarm hour register (alarmwh) control registers alarm week register (alarmww) chapter 7 real-time counter user?s manual u17854ej6v0ud 256 figure 7-1. block diagra m of real-time counter intrtc f sub rtce rcloe1 rcloe0 ampm ct2 ct1 ct0 rinte rcloe2 ict2 ict1 ict0 rtce ampm ct0 to ct2 rckdiv f sub rtc1hz/ intp3/p30 rckdiv rinte rtcdiv/rtccl/p15 intrtci rcloe2 f sub rwait wale walie wafg rwait rwst rifg rwst rifg 12-bit counter real-time counter control register 1 real-time counter control register 0 alarm week register (alarmww) (7-bit) alarm hour register (alarmwh) (6-bit) alarm minute register (alarmwm) (7-bit) year count register (year) (8-bit) month count register (month) (5-bit) week count register (week) (3-bit) day count register (day) (6-bit) hour count register (hour) (6-bit) minute count register (min) (7-bit) second count register (sec) (7-bit) wait control 0.5 seconds sub-count register (rsubc) (16-bit) count clock = 32.768 khz selector buffer buffer buffer buffer buffer buffer buffer count enable/ disable circuit watch error correction register (subcud) (8-bit) selector selector internal bus real-time counter control register 2 1 month 1 day 1 hour 1 minute chapter 7 real-time counter user?s manual u17854ej6v0ud 257 7.3 registers controlling real-time counter timer real-time counter is controlle d by the following 16 registers. (1) peripheral enable register 0 (per0) per0 is used to enable or disable use of each peripheral hardware macro. clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise. when the real-time counter is used, be sure to set bit 7 (rtcen) of this register to 1. per0 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clea rs this register to 00h. figure 7-2. format of peripheral enable register 0 (per0) address: f00f0h after reset: 00h r/w symbol <7> 6 <5> <4> <3> <2> 1 <0> per0 rtcen 0 adcen iic0en sau1en sau0en 0 tau0en rtcen control of real-time counter (rtc) input clock note 0 stops supply of input clock. ? sfr used by the real-time counter (rtc) cannot be written. ? the real-time counter (rtc) is in the reset status. 1 supplies input clock. ? sfr used by the real-time counter (rtc) can be read/written. note the input clock that can be controlled by rtce n is used when the register that is used by the real-time counter (rtc) is accessed from the cpu. rtcen cannot control supply of the operating clock (f sub ) to rtc. cautions 1. when using the real-time counter, first set rtcen to 1, while oscillation of the subsystem clock (f sub ) is stable. if rtcen = 0, writing to a control register of the real-time counter is ignored, and, even if the register is read, only the default value is read. 2. be sure to clear bits 1 a nd 6 of per0 register to 0. (2) real-time counter cont rol register 0 (rtcc0) the rtcc0 register is an 8-bit register that is used to start or stop the real-time co unter operation, control the rtccl and rtc1hz pins, and set a 12- or 24-hour system and the constant-per iod interrupt function. rtcc0 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clea rs this register to 00h. chapter 7 real-time counter user?s manual u17854ej6v0ud 258 figure 7-3. format of real-time c ounter control register 0 (rtcc0) address: fff9dh after reset: 00h r/w symbol <7> 6 <5> <4> 3 2 1 0 rtcc0 rtce 0 rcloe1 rcloe0 ampm ct2 ct1 ct0 rtce real-time counter operation control 0 stops counter operation. 1 starts counter operation. rcloe1 rtc1hz pin output control 0 disables output of rtc1hz pin (1 hz). 1 enables output of rtc1hz pin (1 hz). rcloe0 note rtccl pin output control 0 disables output of rtccl pin (32 khz). 1 enables output of rtccl pin (32 khz). ampm selection of 12-/24-hour system 0 12-hour system (a.m. and p.m. are displayed.) 1 24-hour system ? to change the value of ampm, set rwait (bit 0 of rtcc 1) to 1, and re-set the hour count register (hour). ? table 7-2 shows the displayed ti me digits that are displayed. ct2 ct1 ct0 constant-period interrupt (intrtc) selection 0 0 0 does not use constant-period interrupt function. 0 0 1 once per 0.5 s (synchronized with second count up) 0 1 0 once per 1 s (same time as second count up) 0 1 1 once per 1 m (second 00 of every minute) 1 0 0 once per 1 hour (minute 00 and second 00 of every hour) 1 0 1 once per 1 day (hour 00, minute 00, and second 00 of every day) 1 1 once per 1 month (day 1, hour 00 a.m., minute 00, and second 00 of every month) after changing the values of ct2 to ct0, clear the interrupt request flag. note rcloe0 and rcloe2 must not be enabled at the same time. caution if rcloe0 and rcloe1 are changed when rtce = 1, a pulse with a narrow width may be generated on the 32 khz and 1 khz output signals. remark : don?t care chapter 7 real-time counter user?s manual u17854ej6v0ud 259 table 7-2. displayed time digits 24-hour system 12-hour system 24-hour system 12-hour system 00 12 (am12) 12 32 (pm12) 01 01 (am1) 13 21 (pm1) 02 02 (am2) 14 22 (pm2) 03 03 (am3) 15 23 (pm3) 04 04 (am4) 16 24 (pm4) 05 05 (am5) 17 25 (pm5) 06 06 (am6) 18 26 (pm6) 07 07 (am7) 19 27 (pm7) 08 08 (am8) 20 28 (pm8) 09 09 (am9) 21 29 (pm9) 10 10 (am10) 22 30 (pm10) 11 11 (am11) 23 31 (pm11) (3) real-time counter cont rol register 1 (rtcc1) the rtcc1 register is an 8-bit regist er that is used to control the alarm interrupt function and the wait time of the counter. rtcc1 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clea rs this register to 00h. figure 7-4. format of real-time count er control register 1 (rtcc1) (1/2) address: fff9eh after reset: 00h r/w symbol <7> <6> 5 <4> <3> 2 <1> <0> rtcc1 wale walie 0 wafg rifg 0 rwst rwait wale alarm operation control 0 match operation is invalid. 1 match operation is valid. to set the registers of alarm (walie flag of rt cc1, alarmwm register, alarmwh register, and alarmww register), disable wale (clear it to ?0?). walie control of alarm interrupt (intrtc) function operation 0 does not generate interrupt on matching of alarm. 1 generates interrupt on matching of alarm. wafg alarm detection status flag 0 alarm mismatch 1 detection of matching of alarm this is a status flag that indicates detection of matching wi th the alarm. it is valid only when wale = 1 and is set to ?1? one clock (32 khz) after matching of the alarm is detected. this flag is cleared when ?0? is written to it. writing ?1? to it is invalid. chapter 7 real-time counter user?s manual u17854ej6v0ud 260 figure 7-4. format of real-time count er control register 1 (rtcc1) (2/2) rifg constant-period interrupt status flag 0 constant-period interrupt is not generated. 1 constant-period interrupt is generated. this flag indicates the status of generation of the const ant-period interrupt. when the constant-period interrupt is generated, it is set to ?1?. this flag is cleared when ?0? is written to it. writing ?1? to it is invalid. rwst wait status flag of real-time counter 0 counter is operating. 1 mode to read or write counter value this status flag indicates whether the setting of rwait is valid. before reading or writing the counter value, confirm that the value of this flag is 1. rwait wait control of real-time counter 0 sets counter operation. 1 stops sec to year counters. mode to read or write counter value this bit controls the operation of the counter. be sure to write ?1? to it to read or write the counter value. because rsubc continues operation, complete reading or writ ing of it in 1 second, and clear this bit back to 0. when rwait = 1, it takes up to 1 clock (32 khz) until the counter value can be read or written. if rsubc overflows when rwait = 1, it counts up after rwai t = 0. if the second count register is written, however, it does not count up because rsubc is cleared. caution if writing is performed to the wafg flag with a 1-bit manipulation instruction, the rifg flag may be cleared. therefore, to perform writin g to the wafg flag, be sure to use an 8-bit manipulation instruction, and at this time, set 1 to the rifg flag to invalidate writing. in the same way, to perform writing to the rifg flag, use an 8-bit manipulati on instruction and set 1 the wafr flag. remark fixed-cycle interrupts and alarm match interrupts use the same interrupt source (intrtc). when using these two types of interrupt s at the same time, which interrupt occurred can be judged by checking the fixed-cycle interrupt status flag (r ifg) and the alarm detecti on status flag (wafg) upon intrtc occurrence. chapter 7 real-time counter user?s manual u17854ej6v0ud 261 (4) real-time counter cont rol register 2 (rtcc2) the rtcc2 register is an 8-bit register that is used to control the interval interrupt function and the rtcdiv pin. rtcc2 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clea rs this register to 00h. figure 7-5. format of real-time c ounter control register 2 (rtcc2) address: fff9fh after reset: 00h r/w symbol <7> <6> <5> 4 3 2 1 0 rtcc2 rinte rcloe2 rckdiv 0 0 ict2 ict1 ict0 rinte ict2 ict1 ict0 interval interrupt (intrtci) selection 0 interval interrupt is not generated. 1 0 0 0 2 6 /f xt (1.953125 ms) 1 0 0 1 2 7 /f xt (3.90625 ms) 1 0 1 0 2 8 /f xt (7.8125 ms) 1 0 1 1 2 9 /f xt (15.625 ms) 1 1 0 0 2 10 /f xt (31.25 ms) 1 1 0 1 2 11 /f xt (62.5 ms) 1 1 1 2 12 /f xt (125 ms) change ict2, ict1, and ict0 when rinte = 0. rcloe2 note rtcdiv pin output control 0 output of rtcdiv pin is disabled. 1 output of rtcdiv pin is enabled. rckdiv selection of rtcdiv pin output frequency 0 rtcdiv pin outputs 512 hz. 1 rtcdiv pin outputs 16.384 khz. note rcloe0 and rcloe2 must not be enabled at the same time. caution when the output from rtcdiv pin is sto pped, the output continues after a maximum of two clocks of f xt and enters the low level. while 512 hz is output, and when th e output is stopped immediately after entering the high level, a pluse of at least one clock width of f xt may be generated. chapter 7 real-time counter user?s manual u17854ej6v0ud 262 (5) sub-count re gister (rsubc) the rsubc register is a 16-bit register that counts the reference time of 1 second of the real-time counter. it takes a value of 0000h to 7fffh and counts 1 second with a clock of 32.768 khz. rsubc can be set by a 16-bit memory manipulation instruction. reset signal generation clears this register to 0000h. cautions 1. when a correction is made by using the subcud regi ster, the value may become 8000h or more. 2. this register is also cl eared by reset effected by wr iting the second count register. 3. the value read from this register is not guar anteed if it is read du ring operation, because a value that is changing is read. figure 7-6. format of sub-count register (rsubc) address: fff90h after reset: 0000h r symbol 7 6 5 4 3 2 1 0 rsubc subc7 subc6 subc5 subc4 subc3 subc2 subc1 subc0 address: fff91h after reset: 0000h r symbol 7 6 5 4 3 2 1 0 rsubc subc15 subc14 subc13 subc12 subc11 subc10 subc9 subc8 (6) second count register (sec) the sec register is an 8-bit register that takes a value of 0 to 59 (dec imal) and indicates the count value of seconds. it counts up when the sub-counter overflows. when data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (32.768 khz) later. set a decimal value of 00 to 59 to this register in bcd code. if a value outside this range is set, the register value returns to the normal value after 1 period. sec can be set by an 8-bit memory manipulation instruction. reset signal generation clea rs this register to 00h. figure 7-7. format of second count register (sec) address: fff92h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 sec 0 sec40 sec20 sec10 sec8 sec4 sec2 sec1 chapter 7 real-time counter user?s manual u17854ej6v0ud 263 (7) minute count register (min) the min register is an 8-bit register that takes a valu e of 0 to 59 (decimal) and indicates the count value of minutes. it counts up when the second counter overflows. when data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (32.768 khz) later. set a decimal value of 00 to 59 to this register in bcd code. if a value outside this range is set, the register value returns to the normal value after 1 period. min can be set by an 8-bit memory manipulation instruction. reset signal generation clea rs this register to 00h. figure 7-8. format of minute count register (min) address: fff93h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 min 0 min40 min20 min10 min8 min4 min2 min1 (8) hour count register (hour) the hour register is an 8-bit register that takes a value of 0 to 23 or 1 to 12 (decimal) and indicates the count value of hours. it counts up when the minute counter overflows. when data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (32.768 khz) later. set a decimal value of 00 to 23, 01 to 12, or 21 to 32 to this register in bcd code. if a value outside this range is set, the register value returns to the normal value after 1 period. hour can be set by an 8-bit memory manipulation instruction. reset signal generation clea rs this register to 12h. however, the value of this register is 00h if the ampm bit (bit 3 of the rtcc0 regist er) is set to 1 after reset. figure 7-9. format of hour count register (hour) address: fff94h after reset: 12h r/w symbol 7 6 5 4 3 2 1 0 hour 0 0 hour20 hour10 ho ur8 hour4 hour2 hour1 caution bit 5 (hour20) of ho ur indicates am(0)/pm(1) if ampm = 0 (if the 12-hour system is selected). chapter 7 real-time counter user?s manual u17854ej6v0ud 264 (9) day count register (day) the day register is an 8-bit register that takes a value of 1 to 31 (dec imal) and indicates the count value of days. it counts up when the hour counter overflows. this counter counts as follows. ? 01 to 31 (january, march, may, july, august, october, december) ? 01 to 30 (april, june, september, november) ? 01 to 29 (february, leap year) ? 01 to 28 (february, normal year) when data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (32.768 khz) later. set a decimal value of 00 to 31 to this register in bcd code. if a value outside this range is set, the register value returns to the normal value after 1 period. day can be set by an 8-bit memory manipulation instruction. reset signal generation clea rs this register to 01h. figure 7-10. format of day count register (day) address: fff96h after reset: 01h r/w symbol 7 6 5 4 3 2 1 0 day 0 0 day20 day10 day8 day4 day2 day1 (10) week count register (week) the week register is an 8-bit register that takes a value of 0 to 6 (decimal) and indicates the count value of weekdays. it counts up in synchronization with the day counter. when data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (32.768 khz) later. set a decimal value of 00 to 06 to this register in bcd code. if a value outside this range is set, the register value returns to the normal value after 1 period. week can be set by an 8-bit memory manipulation instruction. reset signal generation clea rs this register to 00h. figure 7-11. format of week count register (week) address: fff95h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 week 0 0 0 0 0 week4 week2 week1 chapter 7 real-time counter user?s manual u17854ej6v0ud 265 (11) month count register (month) the month register is an 8-bit regist er that takes a value of 1 to 12 (decimal) and indicates the count value of months. it counts up when the day counter overflows. when data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (32.768 khz) later. set a decimal value of 01 to 12 to this register in bcd code. if a value outside this range is set, the register value returns to the normal value after 1 period. month can be set by an 8-bit memory manipulation instruction. reset signal generation clea rs this register to 01h. figure 7-12. format of month count register (month) address: fff97h after reset: 01h r/w symbol 7 6 5 4 3 2 1 0 month 0 0 0 month10 month8 month4 month2 month1 (12) year count register (year) the year register is an 8-bit register that takes a value of 0 to 99 (dec imal) and indicates the count value of years. it counts up when the month counter overflows. values 00, 04, 08, ?, 92, and 96 indicate a leap year. when data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (32.768 khz) later. set a decimal value of 00 to 99 to this register in bcd code. if a value outside this range is set, the register value returns to the normal value after 1 period. year can be set by an 8-bit memory manipulation instruction. reset signal generation clea rs this register to 00h. figure 7-13. format of year count register (year) address: fff98h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 year year80 year40 year20 year10 year8 year4 year2 year1 chapter 7 real-time counter user?s manual u17854ej6v0ud 266 (13) watch error correction register (subcud) this register is used to correct the count value of the sub-count register (rsubc). subcud can be set by an 8-bit memory manipulation instruction. reset signal generation clea rs this register to 00h. figure 7-14. format of watch e rror correction register (subcud) address: fff99h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 subcud dev f6 f5 f4 f3 f2 f1 f0 dev setting of watch error correction timing 0 corrects watch error when the second digits are at 00, 20, or 40. 1 corrects watch error only when the second digits are at 00. f6 setting of watch error correction method 0 increases by {(f5, f4, f3, f2, f1, f0) ? 1} 2. 1 decreases by {(/f5, /f4, /f3, /f2, /f1, /f0) + 1} 2. when (f6, f5, f4, f3, f2, f1, f0) = (*, 0, 0, 0, 0, 0, *), the watch error is not corrected. /f5 to /f0 are the inverted values of the corresponding bits (000011 when 111100). (14) alarm minute register (alarmwm) this register is used to set minutes of alarm. alarmwm can be set by an 8-bit memory manipulation instruction. reset signal generation clea rs this register to 00h. caution set a decimal value of 00 to 59 to this register in bcd code. if a value outside the range is set, the alarm is not detected. figure 7-15. format of ala rm minute register (alarmwm) address: fff9ah after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 alarmwm 0 wm40 wm20 wm10 wm8 wm4 wm2 wm1 chapter 7 real-time counter user?s manual u17854ej6v0ud 267 (15) alarm hour register (alarmwh) this register is used to set hours of alarm. alarmwh can be set by an 8-bit memory manipulation instruction. reset signal generation clea rs this register to 12h. however, the value of this register is 00h if the ampm bit (bit 3 of the rtcc0 regist er) is set to 1 after reset. caution set a decimal value of 00 to 23, 01 to 12, or 21 to 32 to this register in bcd code. if a value outside the range is set, the alarm is not detected. figure 7-16. format of alarm hour register (alarmwh) address: fff9bh after reset: 12h r/w symbol 7 6 5 4 3 2 1 0 alarmwh 0 0 wh20 wh10 wh8 wh4 wh2 wh1 caution bit 5 (wh20) of alarmwh indicates am(0)/pm(1) if ampm = 0 (if the 12-hour system is selected). chapter 7 real-time counter user?s manual u17854ej6v0ud 268 (16) alarm week register (alarmww) this register is used to set date of alarm. alarmww can be set by an 8-bit memory manipulation instruction. reset signal generation clea rs this register to 00h. caution set a decimal value of 00 to 23, 01 to 12, or 21 to 32 to this register in bcd code. if a value outside the range is set, the alarm is not detected. figure 7-17. format of alarm week register (alarmww) address: fff9ch after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 alarmww 0 ww6 ww5 ww4 ww3 ww2 ww1 ww0 here is an example of setting the alarm. day 12-hour display 24-hour display time of alarm sunday w w 0 monday w w 1 tuesday w w 2 wednesday w w 3 thursday w w 4 friday w w 5 saturday w w 6 hour 10 hour 1 minute 10 minute 1 hour 10 hour 1 minute 10 minute 1 every day, 0:00 a.m. 1 1 1 1 1 1 1 1 2 0 0 0 0 0 0 every day, 1:30 a.m. 1 1 1 1 1 1 1 0 1 3 0 0 1 3 0 every day, 11:59 a.m. 1 1 1 1 1 1 1 1 1 5 9 1 1 5 9 monday through friday, 0:00 p.m. 0 1 1 1 1 1 0 3 2 0 0 1 2 0 0 sunday, 1:30 p.m. 1 0 0 0 0 0 0 2 1 3 0 1 3 3 0 monday, wednesday, friday, 11:59 p.m. 0 1 0 1 0 1 0 3 1 5 9 2 3 5 9 chapter 7 real-time counter user?s manual u17854ej6v0ud 269 7.4 real-time counter operation 7.4.1 starting operation of real-time counter figure 7-18. procedure for starting operation of real-time counter setting ampm, ct2 to ct0 setting min rtce = 0 setting sec (clearing rsubc) start intrtc = 1? stops counter operation. selects 12-/24-hour system and interrupt (intrtc). sets second count register. sets minute count register. no yes setting hour sets hour count register. setting week sets week count register. setting day sets day count register. setting month sets month count register. setting year sets year count register. clearing if flags of interrupt clears interrupt request flags (rtcif, rtciif). clearing mk flags of interrupt clears interrupt mask flags (rtcmk, rtcimk). rtce = 1 starts counter operation. reading counter rtcen = 1 note supplies input clock. note first set rtcen to 1, while o scillation of the subsystem clock (f sub ) is stable. chapter 7 real-time counter user?s manual u17854ej6v0ud 270 7.4.2 reading/writing real-time counter read or write the counter when rwait = 1. figure 7-19. procedure for reading real-time counter reading min rwait = 1 reading sec start rwst = 1? stops sec to year counters. mode to read and write count values reads second count register. reads minute count register. no yes reading hour reads hour count register. reading week reads week count register. reading day reads day count register. reading month reads month count register. reading year reads year count register. rwait = 0 rwst = 0? note no yes sets counter operation. checks wait status of counter. end note be sure to confirm that rwst = 0 before setting stop mode. caution complete the series of opera tions of setting rwait to 1 to cl earing rwait to 0 within 1 second. remark sec, min, hour, week, day, month, and year may be read in any sequence. all the registers do not have to be set and only some registers may be read. chapter 7 real-time counter user?s manual u17854ej6v0ud 271 figure 7-20. procedure for writing real-time counter writing min rwait = 1 writing sec start rwst = 1? stops sec to year counters. mode to read and write count values no yes writing hour writing week writing day writing month writing year rwait = 0 rwst = 0? note no yes sets counter operation. checks wait status of counter. end writes second count register. writes minute count register. writes hour count register. writes week count register. writes day count register. writes month count register. writes year count register. note be sure to confirm that rwst = 0 before setting stop mode. caution complete the series of opera tions of setting rwait to 1 to cl earing rwait to 0 within 1 second. remark sec, min, hour, week, day, month, a nd year may be written in any sequence. all the registers do not have to be set an d only some registers may be written. chapter 7 real-time counter user?s manual u17854ej6v0ud 272 7.4.3 setting alarm of real-time counter set time of alarm when wale = 0. figure 7-21. alarm setting procedure wale = 0 setting alarmwm start intrtc = 1? match operation of alarm is invalid. sets alarm minute register. alarm processing yes walie = 1 interrupt is generated when alarm matches. setting alarmwh sets alarm hour register. setting alarmww sets alarm week register. wale = 1 match operation of alarm is valid. wafg = 1? no yes constant-period interrupt servicing match detection of alarm no remarks 1. alarmwm, alarmwh, and alarmww may be written in any sequence. 2. fixed-cycle interrupts and alarm match interrupts use the same interrupt source (intrtc). when using these two types of interrupt s at the same time, which interrupt occurred can be judged by checking the fixed-cycle interrupt status flag (rif g) and the alarm detection status flag (wafg) upon intrtc occurrence. user?s manual u17854ej6v0ud 273 chapter 8 watchdog timer 8.1 functions of watchdog timer the watchdog timer operates on the internal low-speed oscillation clock. the watchdog timer is used to detect an inadvertent program loop. if a program loop is detected, an internal reset signal is generated. program loop is detected in the following cases. ? if the watchdog timer counter overflows ? if a 1-bit manipulation instruction is execut ed on the watchdog timer enable register (wdte) ? if data other than ?ach? is written to wdte ? if data is written to wdte during a window close period when a reset occurs due to the watchdog timer, bit 4 (wdrf) of the reset control flag register (resf) is set to 1. for details of resf, see chapter 18 reset function . when 75% of the overflow time is reached, an interval interrupt can be generated. chapter 8 watchdog timer user?s manual u17854ej6v0ud 274 8.2 configuration of watchdog timer the watchdog timer includes the following hardware. table 8-1. configuration of watchdog timer item configuration control register watchdog timer enable register (wdte) how the counter operation is controlled, overflow time, wi ndow open period, and interval interrupt are set by the option byte. table 8-2. setting of option bytes and watchdog timer setting of watchdog timer option byte (000c0h) watchdog timer interval interrupt bit 7 (wdtint) window open period bits 6 and 5 (window1, window0) controlling counter operation of watchdog timer bit 4 (wdton) overflow time of watchdog timer bits 3 to 1 (wdcs2 to wdcs0) controlling counter operation of watchdog timer (in halt/stop mode) bit 0 (wdstbyon) remark for the option byte, see chapter 22 option byte . figure 8-1. block diagram of watchdog timer f il wdton of option byte (000c0h) wdtint of option byte (000c0h) interval time controller (count value overflow time 3/4) interval time interrupt wdcs2 to wdcs0 of option byte (000c0h) clock input controller 20-bit counter selector overflow signal reset output controller internal reset signal count clear signal window size decision signal window size check watchdog timer enable register (wdte) write detector to wdte except ach internal bus window1 and window0 of option byte (000c0h) f il /2 10 to f il /2 20 chapter 8 watchdog timer user?s manual u17854ej6v0ud 275 8.3 register controlling watchdog timer the watchdog timer is controlled by the watchdog timer enable register (wdte). (1) watchdog timer enable register (wdte) writing ?ach? to wdte clears the watchdog timer counter and starts counting again. this register can be set by an 8-bit memory manipulation instruction. reset signal generation sets this register to 9ah or 1ah note . figure 8-2. format of watchdog timer enable register (wdte) 0 1 2 3 4 5 6 7 symbol wdte address: fffabh after reset: 9ah/1ah note r/w note the wdte reset value differs depending on the wdton setting value of the option byte (000c0h). to operate watchdog timer, set wdton to 1. wdton setting value wdte reset value 0 (watchdog timer count operation disabled) 1ah 1 (watchdog timer count operation enabled) 9ah cautions 1. if a value other than ?ach? is writte n to wdte, an internal r eset signal is generated. 2. if a 1-bit memory manipulation instructio n is executed for wdte, an internal reset signal is generated. 3. the value read from wd te is 9ah/1ah (this differs fr om the written value (ach)). chapter 8 watchdog timer user?s manual u17854ej6v0ud 276 8.4 operation of watchdog timer 8.4.1 controlling operation of watchdog timer 1. when the watchdog timer is used, its operati on is specified by the option byte (000c0h). ? enable counting operation of the watchdog timer by setting bit 4 (wdton) of the option byte (000c0h) to 1 (the counter starts operating after a reset release) (for details, see chapter 22 ). wdton watchdog timer counter 0 counter operation disabled (counting stopped after reset) 1 counter operation enabled (counting started after reset) ? set an overflow time by using bits 3 to 1 (wdcs2 to wdcs0) of the option byte (000c0h) (for details, see 8.4.2 and chapter 22 ). ? set a window open period by using bits 6 and 5 (window1 and window0) of the option byte (000c0h) (for details, see 8.4.3 and chapter 22 ). 2. after a reset release, the watchdog timer starts counting. 3. by writing ?ach? to wdte after the watchdog timer starts counting and before the overflow time set by the option byte, the watchdog timer is cl eared and starts counting again. 4. after that, write wdte the second time or later afte r a reset release during the window open period. if wdte is written during a window close period, an internal reset signal is generated. 5. if the overflow time expires without ?ach? wri tten to wdte, an internal reset signal is generated. a internal reset signal is generated in the following cases. ? if a 1-bit manipulation instruction is execut ed on the watchdog timer enable register (wdte) ? if data other than ?ach? is written to wdte cautions 1. when data is written to wdte for th e first time after reset re lease, the watchdog timer is cleared in any timing regardl ess of the window open time, as long as the register is written before the overflow time, and the wa tchdog timer starts counting again. 2. if the watchdog timer is cleared by writi ng ?ach? to wdte, the actual overflow time may be different from the overflow time set by the option byte by up to 2/f il seconds. 3. the watchdog timer can be cleared imme diately before the c ount value overflows. chapter 8 watchdog timer user?s manual u17854ej6v0ud 277 cautions 4. the operation of the watchdog time r in the halt and stop modes differs as follows depending on the set value of bit 0 (wds tbyon) of the option byte (000c0h). wdstbyon = 0 wdstbyon = 1 in halt mode in stop mode watchdog timer operation stops. watchdog timer operation continues. if wdstbyon = 0, the watchdog timer resum es counting after the halt or stop mode is released. at this time, the counter is cleared to 0 and counting starts. when operating with the x1 oscillation clock after releasi ng the stop mode, the cpu starts operating after the oscillation stabilization time has elapsed. therefore, if the period between the stop mode release a nd the watchdog timer overflow is short, an overflow occurs during the o scillation stabilization time, causing a reset. consequently, set the ov erflow time in consideration of the oscillation stabilization time when operating with the x1 oscillation clock a nd when the watchdog timer is to be cleared after the stop mode release by an interval interrupt. 5. the watchdog timer continues its operati on during self-programming of the flash memory and eeprom tm emulation. during processing, the in terrupt acknowledge time is delayed. set the overflow time and window size taking this delay into consideration. 8.4.2 setting overflow time of watchdog timer set the overflow time of the watchdog timer by using bits 3 to 1 (wdcs2 to wdcs0) of the option byte (000c0h). if an overflow occurs, an internal reset signal is generat ed. the present count is cleared and the watchdog timer starts counting again by writing ?ach? to wdte dur ing the window open period before the overflow time. the following overflow time is set. table 8-3. setting of overflow time of watchdog timer wdcs2 wdcs1 wdcs0 overflow time of watchdog timer 0 0 0 2 10 /f il (3.88 ms) 0 0 1 2 11 /f il (7.76 ms) 0 1 0 2 12 /f il (15.52 ms) 0 1 1 2 13 /f il (31.03 ms) 1 0 0 2 15 /f il (124.12 ms) 1 0 1 2 17 /f il (496.48 ms) 1 1 0 2 18 /f il (992.97 ms) 1 1 1 2 20 /f il (3971.88 ms) caution the watchdog timer conti nues its operation during self-program ming of the flash memory and eeprom emulation. during processing, the inte rrupt acknowledge time is delayed. set the overflow time and window size taki ng this delay into consideration. remarks 1. f il : internal low-speed oscillation clock frequency 2. ( ): f il = 264 khz (max.) chapter 8 watchdog timer user?s manual u17854ej6v0ud 278 8.4.3 setting window open period of watchdog timer set the window open period of the watchdog timer by usi ng bits 6 and 5 (window1, window0) of the option byte (000c0h). the outline of the window is as follows. ? if ?ach? is written to wdte during the window open per iod, the watchdog timer is cleared and starts counting again. ? even if ?ach? is written to wdte during the window cl ose period, an abnormality is detected and an internal reset signal is generated. example : if the window open period is 25% window close period (75%) window open period (25%) counting starts overflow time counting starts again when ?ach? is written to wdte. internal reset signal is generated if ?ach? is written to wdte. caution when data is writte n to wdte for the first time after reset release, the watchdog timer is cleared in any timing regardless of the window open time , as long as the register is written before the overflow time, and the watchdog timer starts counting again. the window open period to be set is as follows. table 8-4. setting window op en period of watchdog timer window1 window0 window open period of watchdog timer 0 0 25% 0 1 50% 1 0 75% 1 1 100% cautions 1. the watchdog timer continues its operation during self-programmi ng of the flash memory and eeprom emulation. during processing, the interrupt acknowledge ti me is delayed. set the overflow time and window size t aking this delay into consideration. 2. when bit 0 (wdstbyon) of the option byte (000c0h) = 0, the window open period is 100% regardless of the values of window1 and window0. 3. do not set the window open period to 25% if the watchdog timer corresponds to either of the conditions below. ? when used at a supply voltage (v dd ) below 2.7 v. ? when stopping all main system clocks (internal high-speed osc illation clock, x1 clock, and external main system clock) by use of the stop mode or software. chapter 8 watchdog timer user?s manual u17854ej6v0ud 279 remark if the overflow time is set to 2 10 /f il , the window close time and open time are as follows. setting of window open period 25% 50% 75% 100% window close time 0 to 3.56 ms 0 to 2.37 ms 0 to 0.119 ms none window open time 3.56 to 3.88 ms 2.37 to 3.88 ms 0.119 to 3.88 ms 0 to 3.88 ms user?s manual u17854ej6v0ud 280 chapter 9 clock output/buzzer output controller 9.1 functions of clock output/buzzer output controller the clock output controller is intended for carrier output during remote controlled transmission and clock output for supply to peripheral ics. buzzer output is a function to output a square wave of buzzer frequency. one pin can be used to output a clock or buzzer sound. two output pins, pclbuz0 and pclbuz1, are available. pclbuz0 outputs a clock selected by cl ock output select register 0 (cks0). pclbuz1 outputs a clock selected by cl ock output select register 1 (cks1). figure 9-1 shows the block diagram of clock output/buzzer output controller. figure 9-1. block diagram of clo ck output/buzzer output controller f main f sub pcloe0 0 0 0 pcloe0 5 3 pclbuz0 note /intp6/p140 pclbuz1 note /intp7/p141 csel0 ccs02 ccs01 ccs00 pm141 pm140 pcloe1 0 0 0 csel1 ccs12 ccs11 ccs10 8 pcloe1 8 f main /2 11 to f main /2 13 clock/buzzer controller internal bus clock output select register 1 (cks1) prescaler prescaler selector selector clock/buzzer controller output latch (p141) internal bus clock output select register 0 (cks0) output latch (p140) f main /2 11 to f main /2 13 f main to f main /2 4 f main to f main /2 4 f sub to f sub /2 7 f sub to f sub /2 7 note the pclbuz0 and pclbuz1 pins can out put a clock of up to 10 mhz at 2.7 v v dd . setting a clock exceeding 5 mhz at v dd < 2.7 v is prohibited. chapter 9 clock output/buzzer output controller user?s manual u17854ej6v0ud 281 9.2 configuration of clock output/buzzer output controller the clock output/buzzer output controller includes the following hardware. table 9-1. configuration of clock output/buzzer output controller item configuration control registers clock output select registers 0, 1 (cks0, cks1) port mode register 14 (pm14) port register 14 (p14) 9.3 registers controlling clock ou tput/buzzer output controller the following two registers are used to control the clock output/buzzer output controller. ? clock output select registers 0, 1 (cks0, csk1) ? port mode register 14 (pm14) (1) clock output select regi sters 0, 1 (cks0, cks1) these registers set output enable/disable for clock output or for the buzzer frequency output pin (pclbuz0/pclbuz1), and set the output clock. select the clock to be output from pclbuz0 by using cks0. select the clock to be output from pclbuz1 by using cks1. cks0 and cks1 are set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears these registers to 00h. chapter 9 clock output/buzzer output controller user?s manual u17854ej6v0ud 282 figure 9-2. format of clock output select register n (cksn) address: fffa5h after reset: 00h r/w symbol <7> 6 5 4 3 2 1 0 cksn pcloen 0 0 0 cseln ccsn2 ccsn1 ccsn0 pcloen pclbuzn output enabl e/disable specification 0 output disable (default) 1 output enable pclbuzn output clock selection cseln ccsn2 ccsn1 ccsn0 f main = 5 mhz f main = 10 mhz f main = 20 mhz 0 0 0 0 f main 5 mhz 10 mhz note setting prohibited note 0 0 0 1 f main /2 2.5 mhz 5 mhz 10 mhz note 0 0 1 0 f main /2 2 1.25 mhz 2.5 mhz 5 mhz 0 0 1 1 f main /2 3 625 khz 1.25 mhz 2.5 mhz 0 1 0 0 f main /2 4 312.5 khz 625 khz 1.25 mhz 0 1 0 1 f main /2 11 2.44 khz 4.88 khz 9.76 khz 0 1 1 0 f main /2 12 1.22 khz 2.44 khz 4.88 khz 0 1 1 1 f main /2 13 610 hz 1.22 khz 2.44 khz 1 0 0 0 f sub 32.768 khz 1 0 0 1 f sub /2 16.384 khz 1 0 1 0 f sub /2 2 8.192 khz 1 0 1 1 f sub /2 3 4.096 khz 1 1 0 0 f sub /2 4 2.048 khz 1 1 0 1 f sub /2 5 1.024 khz 1 1 1 0 f sub /2 6 512 hz 1 1 1 1 f sub /2 7 256 hz note setting an output clock exceeding 10 mhz is prohibited when 2.7 v v dd . setting a clock exceeding 5 mhz at v dd < 2.7 v is also prohibited. cautions 1. change the output clock after disabling clock output (pcloen = 0). 2. if the selected clock (f main or f sub ) stops during clock output (pcloen = 1), the output becomes undefined. remarks 1. n = 0, 1 2. f main : main system clock frequency 3. f sub : subsystem clock frequency chapter 9 clock output/buzzer output controller user?s manual u17854ej6v0ud 283 (2) port mode register 14 (pm14) this register sets port 14 input/output in 1-bit units. when using the p140/intp6/pclbuz0 and p141/intp7/pc lbuz1 pins for clock output/buzzer output, clear pm140 and pm141 and the output latc hes of p140 and p141 to 0. pm14 is set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to ffh. figure 9-3. format of port mode register 14 (pm14) address: fff2eh after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm14 1 1 1 1 1 1 pm141 pm140 pm14n p14n pin i/o mode selection (n = 0, 1) 0 output mode (output buffer on) 1 input mode (output buffer off) 9.4 operations of clock output/buzzer output controller one pin can be used to output a clock or buzzer sound. two output pins, pclbuz0 and pclbuz1, are available. pclbuz0 outputs a clock/buzzer selected by clock output select register 0 (cks0). pclbuz1 outputs a clock/buzzer selected by clock output select register 1 (cks1). 9.4.1 operation as output pin pclbuzn is output as the following procedure. <1> select the output frequency with bits 0 to 3 (ccsn0 to ccsn2, cseln) of the clo ck output select register (cksn) of the pclbuzn pin (out put in disabled status). <2> set bit 7 (pcloen) of cksn to 1 to enable clock/buzzer output. remark the controller is designed not to output a pulse with a narrow width when it is used to output a clock and when clock output is enabled or disabled. as shown in figure 9-4, be sure to start output from the low period of the clock (marked with * in the figure). when stopping output, do so after the high-level period of the clock. figure 9-4. remote control output application example pcloen clock output ** remark n = 0, 1 user?s manual u17854ej6v0ud 284 chapter 10 a/d converter 10.1 function of a/d converter the a/d converter converts an analog input signal into a di gital value, and consists of up to 8 channels (ani0 to ani7) with a resolution of 10 bits. the a/d converter has the following function. ? 10-bit resolution a/d conversion 10-bit resolution a/d conversion is carried out repeatedly for one analog input channel selected from ani0 to ani7. each time an a/d conversion operation en ds, an interrupt request (intad) is generated. figure 10-1. block diag ram of a/d converter intad adcs fr2 fr1 adce fr0 av ss 4 ani0/p20 ani1/p21 ani2/p22 ani3/p23 ani4/p24 ani5/p25 ani6/p26 ani7/p27 lv1 lv0 5 adpc2 adpc1 adpc0 5 adpc3 ads2 ads1 ads0 adiss av ref av ss analog input channel specification register (ads) selector sample & hold circuit voltage comparator tap selector adcs bit controller successive approximation register (sar) a/d converter mode register (adm) a/d port configuration register (adpc) internal bus a/d conversion result register (adcr) adpc4 chapter 10 a/d converter user?s manual u17854ej6v0ud 285 10.2 configuration of a/d converter the a/d converter includes the following hardware. (1) ani0 to ani7 pins these are the analog input pins of the 8- channel a/d converter. they input analog signals to be converted into digital signals. pins other than the one selected as the analog input pin can be used as i/o port pins. (2) sample & hold circuit the sample & hold circuit samples the input voltage of the analog input pin selected by the selector when a/d conversion is started, and holds the samp led voltage value during a/d conversion. (3) series resistor string the series resistor stri ng is connected between av ref and av ss , and generates a voltage to be compared with the sampled voltage value. figure 10-2. circuit configuration of series resistor string adcs series resistor string av ref p-ch av ss (4) voltage comparator the voltage comparator compares the sampled voltage value and the output volt age of the series resistor string. (5) successive approximation register (sar) this register converts the result of comparison by the voltage comparator, starting from the most significant bit (msb). when the voltage value is converted into a digital valu e down to the least significant bit (lsb) (end of a/d conversion), the contents of the sar register are transfe rred to the a/d conversion result register (adcr). (6) 10-bit a/d conversion r esult register (adcr) the a/d conversion result is loaded from the successive approximation register to th is register each time a/d conversion is completed, and the adcr re gister holds the a/d conversion result in its higher 10 bits (the lower 6 bits are fixed to 0). (7) 8-bit a/d conversion result register (adcrh) the a/d conversion result is loaded from the successive approximation register to th is register each time a/d conversion is completed, and the adcrh register stores the higher 8 bi ts of the a/d conversion result. chapter 10 a/d converter user?s manual u17854ej6v0ud 286 (8) controller this circuit controls the conversion time of an input analog signal that is to be converted into a digital signal, as well as starting and stopping of t he conversion operation. when a/d c onversion has been completed, this controller generates intad. (9) av ref pin this pin inputs an analog power/reference voltage to the a/ d converter. when all pins of port 2 are used as the analog port pins, make the potential of av ref be such that 2.3 v av ref v dd . when one or more of the pins of port 2 are used as the digital port pins or when the a/d converter is not used, make av ref the same potential as ev dd or v dd . the signal input to ani0 to ani7 is converted into a digital signal, based on the voltage applied across av ref and av ss . (10) av ss pin this is the ground potential pin of the a/d converter. always use this pin at the same potential as that of the ev ss and v ss pins even when the a/d converter is not used. (11) a/d converter mode register (adm) this register is used to set the conver sion time of the analog input signal to be converted, and to start or stop the conversion operation. (12) a/d port configuration register (adpc) this register switches t he ani0/p20 to ani7/p27 pins to analog inpu t of a/d converter or digital i/o of port. (13) analog input channel sp ecification register (ads) this register is used to specify the port that inputs the analog voltage to be converted into a digital signal. (14) port mode registers 2 (pm2) this register switches the ani0/p20 to ani7/p27 pins to input or output. chapter 10 a/d converter user?s manual u17854ej6v0ud 287 10.3 registers used in a/d converter the a/d converter uses the following seven registers. ? peripheral enable register 0 (per0) ? a/d converter mode register (adm) ? a/d port configuration register (adpc) ? analog input channel specification register (ads) ? port mode registers 2 (pm2) ? 10-bit a/d conversion result register (adcr) ? 8-bit a/d conversion result register (adcrh) (1) peripheral enable register 0 (per0) per0 is used to enable or disable use of each peripher al hardware macro. clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise. when the a/d converter is used, be sure to se t bit 5 (adcen) of this register to 1. per0 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. cautions 1. when setting the a/d conver ter, be sure to set adcen to 1 fi rst. if adcen = 0, writing to a control register of the a/d converter is ignored , and, even if the register is read, only the default value is read. 2. be sure to clear bits 1 a nd 6 of per0 register to 0. figure 10-3. format of peripheral enable register 0 (per0) address: f00f0h after reset: 00h r/w symbol <7> 6 <5> <4> <3> <2> 1 <0> per0 rtcen 0 adcen iic0en sau1en sau0en 0 tau0en adcen control of a/d converter input clock 0 stops supply of input clock. ? sfr used by the a/d converter cannot be written. ? the a/d converter is in the reset status. 1 supplies input clock. ? sfr used by the a/d converter can be read/written. chapter 10 a/d converter user?s manual u17854ej6v0ud 288 (2) a/d converter mode register (adm) this register sets the conversion time for analog inpu t to be a/d converted, and starts/stops conversion. adm can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. figure 10-4. format of a/d converter mode register (adm) adce lv0 note 1 lv1 note 1 fr0 note 1 fr1 note 1 fr2 note 1 0 adcs a/d conversion operation control stops conversion operation enables conversion operation adcs 0 1 <0> 1 2 3 4 5 6 <7> adm address: fff30h after reset: 00h r/w symbol comparator operation control note 2 stops comparator operation enables comparator operation (comparator: 1/2av ref operation) adce 0 1 notes 1. for details of fr2 to fr0, lv 1, lv0, and a/d conversion, see table 10-2 a/d conversion time selection . 2. the operation of the compar ator is controlled by adcs and adce, and it takes 1 s from operation start to operation stabilization. theref ore, when adcs is set to 1 after 1 s or more has elapsed from the time adce is set to 1, the conversion result at that time has priority over the first conversion result. otherwise, ignore data of the first conversion. table 10-1. settings of adcs and adce adcs adce a/d co nversion operation 0 0 stop status (dc power consumption path does not exist) 0 1 conversion waiting mode (comparator: 1/2av ref operation, only comparator consumes power) 1 0 setting prohibited 1 1 conversion mode (comparator: 1/2av ref operation) figure 10-5. timing chart wh en comparator is used adce comparator adcs conversion operation conversion operation conversion stopped conversion waiting comparator: 1/2av ref operation note note to stabilize the internal circuit, the time from the rising of the adce bit to the falling of the adcs bit must be 1 s or longer. caution a/d conversion must be sto pped before rewriting bits fr0 to fr2, lv1, and lv0 to values other than the identical data. chapter 10 a/d converter user?s manual u17854ej6v0ud 289 table 10-2. a/d conversion time selection (1) 2.7 v av ref 5.5 v a/d converter mode register (adm) conversion time selection fr2 fr1 fr0 lv1 lv0 f clk = 2 mhz f clk = 10 mhz f clk = 20 mhz conversion clock (f ad ) 0 0 0 0 0 264/f clk 26.4 s 13.2 s f clk /12 0 0 1 0 0 176/f clk 17.6 s 8.8 s note f clk /8 0 1 0 0 0 132/f clk 13.2 s 6.6 s note f clk /6 0 1 1 0 0 88/f clk setting prohibited 8.8 s note f clk /4 1 0 0 0 0 66/f clk 33.0 s 6.6 s note f clk /3 1 0 1 0 0 44/f clk 22.0 s f clk /2 1 1 1 0 0 22/f clk 11.0 s note setting prohibited setting prohibited f clk other than above setting prohibited note this can be set only when 4.0 v av ref 5.5 v. caution set the conversion times with the following conditions. ? 4.0 v av ref 5.5 v: f ad = 0.6 to 3.6 mhz ? 2.7 v av ref < 4.0 v: f ad = 0.6 to 1.8 mhz (2) 2.3 v av ref 5.5 v a/d converter mode register (adm) conversion time selection fr2 fr1 fr0 lv1 lv0 f clk = 2 mhz f clk = 5 mhz conversion clock (f ad ) 0 0 0 0 1 480/f clk setting prohibited f clk /12 0 0 1 0 1 320/f clk 64.0 s note 1 f clk /8 0 1 0 0 1 240/f clk 48.0 s note 1 f clk /6 0 1 1 0 1 160/f clk setting prohibited 32.0 s f clk /4 1 0 0 0 1 120/f clk 60.0 s 24.0 s note 2 f clk /3 1 0 1 0 1 80/f clk 40.0 s 16.0 s note 3 f clk /2 1 1 1 0 1 40/f clk 20.0 s note 3 setting prohibited f clk other than above setting prohibited notes 1. this can be set only when 2.3 v av ref < 2.7 v. 2. this can be set only when 2.7 v av ref 5.5 v. 3. this can be set only when 4.0 v av ref 5.5 v. cautions 1. set the conversion ti mes with the following conditions. ? 4.0 v av ref 5.5 v: f ad = 1.2 to 3.6 mhz ? 2.7 v av ref < 4.0 v: f ad = 1.2 to 1.8 mhz ? 2.3 v av ref < 2.7 v: f ad = 0.6 to 1.44 mhz 2. when rewriting fr2 to fr0, lv1, and lv0 to other than the same data, stop a/d conversion once (adcs = 0) beforehand. 3. change lv1 and lv0 from the default value, when 2.3 v av ref < 2.7 v. 4. the above conversion time do es not include clock frequency e rrors. select conversion time, taking clock frequency erro rs into consideration. remark f clk : cpu/peripheral hardware clock frequency chapter 10 a/d converter user?s manual u17854ej6v0ud 290 figure 10-6. a/d converter sa mpling and a/d conversion timing adcs wait period conversion time conversion time sampling sampling timing intad adcs 1 or ads rewrite sampling sar clear sar clear transfer to adcr, intad generation successive conversion chapter 10 a/d converter user?s manual u17854ej6v0ud 291 (3) 10-bit a/d conversion r esult register (adcr) this register is a 16-bit register that stores the a/d conversion result. the lower 6 bits are fixed to 0. each time a/d conversion ends, the conversion result is loaded from the successive approximation register. the higher 8 bits of the conversion result are stored in fff1fh and the lower 2 bits are stored in the higher 2 bits of fff1eh. adcr can be read by a 16-bit memory manipulation instruction. reset signal generation clears this register to 0000h. figure 10-7. format of 10-bit a/d conversion result register (adcr) symbol address: fff1fh, fff1eh after reset: 0000h r fff1fh fff1eh 0 0 0 0 0 0 adcr caution when writing to the a/d converter mode register (adm), analog input chan nel specification register (ads), and a/d port configuration regi ster (adpc), the conten ts of adcr may become undefined. read the conversion result followin g conversion completion before writing to adm, ads, and adpc. using timing other than the abo ve may cause an incorrect conversion result to be read. chapter 10 a/d converter user?s manual u17854ej6v0ud 292 (4) 8-bit a/d conversion result register (adcrh) this register is an 8-bit register that stores the a/d conversion result. the higher 8 bits of 10-bit resolution are stored. adcrh can be read by an 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. figure 10-8. format of 8-bit a/d c onversion result register (adcrh) symbol adcrh address: fff1fh after reset: 00h r 76543210 caution when writing to the a/d converter mode register (adm), analog input chan nel specification register (ads), and a/d port configuration regi ster (adpc), the contents of adcrh may become undefined. read the conversion result followin g conversion completion before writing to adm, ads, and adpc. using timing other than the abo ve may cause an incorrect conversion result to be read. chapter 10 a/d converter user?s manual u17854ej6v0ud 293 (5) analog input channel specification register (ads) this register specifies the input channel of the analog voltage to be a/d converted. ads can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. figure 10-9. format of analog input channel specification register (ads) address: fff31h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 ads adiss 0 0 0 0 ads2 ads1 ads0 adiss ads2 ads1 ads0 analog input channel input source 0 0 0 0 ani0 p20/ani0 pin 0 0 0 1 ani1 p21/ani1 pin 0 1 0 ani2 p22/ani2 pin 0 1 1 ani3 p23/ani3 pin 1 0 0 ani4 p24/ani4 pin 1 0 1 ani5 p25/ani5 pin 1 1 0 ani6 p26/ani6 pin 1 1 1 ani7 p27/ani7 pin cautions 1. be sure to cl ear bits 3 to 6 to ?0?. 2 set a channel to be used fo r a/d conversion in the input mode by using port mode registers 2 (pm2). 3. do not set the pin that is set by adpc as digital i/o by ads. remark : don?t care chapter 10 a/d converter user?s manual u17854ej6v0ud 294 (6) a/d port configuration register (adpc) this register switches t he ani0/p20 to ani7/p27 pins to analog inpu t of a/d converter or digital i/o of port. adpc can be set by an 8-bit memory manipulation instruction. reset signal generation sets this register to 10h. figure 10-10. format of a/d port configuration register (adpc) address: f0017h after reset: 10h r/w symbol 7 6 5 4 3 2 1 0 adpc 0 0 0 adpc4 adpc3 adpc2 adpc1 adpc0 analog input (a)/digital i/o (d) switching adpc4 adpc3 adpc2 adpc1 adpc0 ani7 /p27 ani6 /p26 ani5 /p25 ani4 /p24 ani3 /p23 ani2 /p22 ani1 /p21 ani0 /p20 0 0 0 0 0 a a a a a a a a 0 0 0 0 1 a a a a a a a d 0 0 0 1 0 a a a a a a d d 0 0 0 1 1 a a a a a d d d 0 0 1 0 0 a a a a d d d d 0 0 1 0 1 a a a d d d d d 0 0 1 1 0 a a d d d d d d 0 0 1 1 1 a d d d d d d d 0 1 0 0 0 d d d d d d d d 1 0 0 0 0 d d d d d d d d other than above setting prohibited cautions 1. set a channel to be u sed for a/d conversion in the input mode by usi ng port mode registers 2 (pm2). 2. do not set the pin that is set by adpc as digital i/o by ads. 3. when using all ani0/p20 to ani7/p27 pins as digital i/o (d), the setting can be done by adpc4 to adpc0 = either 01000 or 10000. chapter 10 a/d converter user?s manual u17854ej6v0ud 295 (7) port mode registers 2 (pm2) when using the ani0/p20 to ani7/p27 pins for analog input port, set pm20 to pm27 to 1. the output latches of p20 to p27 at this time may be 0 or 1. if pm20 to pm27 are set to 0, they cannot be used as analog input port pins. pm2 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets these registers to ffh. caution if a pin is set as an analog input por t, not the pin level bu t ?0? is always read. figure 10-11. format of port mode registers 2 (pm2) address: fff22h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm2 pm27 pm26 pm25 pm24 pm23 pm22 pm21 pm20 pm2n p2n pin i/o mode selection (n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) ani0/p20 to ani7/p27 pins are as shown below depending on the settings of adpc, ads, and pm2. table 10-3. setting functions of ani0/p20 to ani7/p27 pins adpc pm2 ads ani0/p20 to ani7/p27 pins input mode ? digital input digital i/o selection output mode ? digital output selects ani. analog input (to be converted) input mode does not select ani. analog input (not to be converted) selects ani. analog input selection output mode does not select ani. setting prohibited chapter 10 a/d converter user?s manual u17854ej6v0ud 296 10.4 a/d converter operations 10.4.1 basic operations of a/d converter <1> set bit 5 (adcen) of peripheral enable register 0 (per0) to 1 to start the supply of the input clock to the a/d converter. <2> set bit 0 (adce) of the a/d converter mode register (adm) to 1 to start the operation of the comparator. <3> set channels for a/d conversion to analog input by usi ng bits the a/d port configur ation register (adpc) and set to input mode by using port mode registers 2 (pm2). <4> set a/d conversion time by using bits 5 to 1 (fr2 to fr0, lv1, and lv0) of adm. <5> select one channel for a/d conversion using the analog input channel specification register (ads). <6> start the conversion operation by setting bit 7 (adcs) of adm to 1. (<7> to <13> are operations performed by hardware.) <7> the voltage input to the selected analog input c hannel is sampled by the sample & hold circuit. <8> when sampling has been done for a certain time, the sa mple & hold circuit is placed in the hold state and the sampled voltage is held until the a/ d conversion operation has ended. <9> bit 9 of the successive approximation register (sar) is set. the series resistor string voltage tap is set to (1/2) av ref by the tap selector. <10> the voltage difference between the series resistor string voltage tap a nd sampled voltage is compared by the voltage comparator. if the analog input is greater than (1/2) av ref , the msb of sar remains set to 1. if the analog input is smaller than (1/2) av ref , the msb is reset to 0. <11> next, bit 8 of sar is automatically set to 1, and t he operation proceeds to the next comparison. the series resistor string voltage tap is selected according to the preset value of bit 9, as described below. ? bit 9 = 1: (3/4) av ref ? bit 9 = 0: (1/4) av ref the voltage tap and sampled voltage are compared and bit 8 of sar is manipulated as follows. ? analog input voltage voltage tap: bit 8 = 1 ? analog input voltage < voltage tap: bit 8 = 0 <12> comparison is continued in this way up to bit 0 of sar. <13> upon completion of the comparison of 10 bits, an effective digital result value remains in sar, and the result value is transferred to the a/d conversion resu lt register (adcr, adcrh) and then latched. at the same time, the a/d conversion end in terrupt request (intad) can also be generated. <14> repeat steps <7> to <13>, until adcs is cleared to 0. to stop the a/d converter, clear adcs to 0. to restart a/d conversion from the st atus of adce = 1, start from <6>. to start a/d conversion again when adce = 0, set adce to 1, wait for 1 s or longer, and start <6>. to change a channel of a/d conversion, start from <5>. caution make sure the period of <2> to <6> is 1 s or more. remark two types of a/d conversion re sult registers are available. ? adcr (16 bits): store 10-bit a/d conversion value ? adcrh (8 bits): store 8-bit a/d conversion value chapter 10 a/d converter user?s manual u17854ej6v0ud 297 figure 10-12. basic operation of a/d converter conversion time sampling time sampling a/d conversion undefined conversion result a/d converter operation sar adcr intad conversion result a/d conversion operations are performed continuously until bit 7 (adcs) of t he a/d converter mode register (adm) is reset (0) by software. if a write operation is performed to the analog input chan nel specification register (ads) during an a/d conversion operation, the conversion operation is in itialized, and if the adcs bit is set (1), conversion starts again from the beginning. reset signal generation clears the a/d conversion re sult register (adcr, adcrh) to 0000h or 00h. chapter 10 a/d converter user?s manual u17854ej6v0ud 298 10.4.2 input voltage and conversion results the relationship between the analog input voltage input to the analog input pins (ani0 to ani7) and the theoretical a/d conversion result (stored in the 10-bit a/d conver sion result register (adcr)) is shown by the following expression. sar = int ( 1024 + 0.5) adcr = sar 64 or ( ? 0.5) v ain < ( + 0.5) where, int( ): function which returns integer part of value in parentheses v ain : analog input voltage av ref : av ref pin voltage adcr: a/d conversion result register (adcr) value sar: successive approximation register figure 10-13 shows the relationship between the analo g input voltage and the a/d conversion result. figure 10-13. relationship between analog i nput voltage and a/d conversion result 1023 1022 1021 3 2 1 0 ffc0h ff80h ff40h 00c0h 0080h 0040h 0000h a/d conversion result sar adcr 1 2048 1 1024 3 2048 2 1024 5 2048 input voltage/av ref 3 1024 2043 2048 1022 1024 2045 2048 1023 1024 2047 2048 1 v ain av ref av ref 1024 av ref 1024 adcr 64 adcr 64 chapter 10 a/d converter user?s manual u17854ej6v0ud 299 10.4.3 a/d converter operation mode the operation mode of the a/d converter is the select mode. one channe l of analog input is selected from ani0 to ani7 by the analog input channel specification register (ads) and a/d co nversion is executed. (1) a/d conversion operation by setting bit 7 (adcs) of the a/d converter mode regist er (adm) to 1, the a/d conversion operation of the voltage, which is applied to the analog input pin specif ied by the analog input channel specification register (ads), is started. when a/d conversion has been completed, the result of the a/d c onversion is stored in t he a/d conversion result register (adcr), and an interrupt request signal (int ad) is generated. when one a/d conversion has been completed, the next a/d conversion oper ation is immediately started. if ads is rewritten during a/d conversion, the a/d conv ersion operation under execut ion is stopped and restarted from the beginning. if 0 is written to adcs during a/d conversion, a/d conv ersion is immediately stopped. at this time, the conversion result immediat ely before is retained. figure 10-14. a/d conversion operation anin rewriting adm adcs = 1 rewriting ads adcs = 0 anin anin anin anim anin anim anim stopped conversion result immediately before is retained a/d conversion adcr, adcrh intad conversion is stopped conversion result immediately before is retained remarks 1. n = 0 to 7 2. m = 0 to 7 chapter 10 a/d converter user?s manual u17854ej6v0ud 300 the setting methods are described below. <1> set bit 5 (adcen) of peripheral enable register 0 (per0) to 1. <2> set bit 0 (adce) of the a/d converter mode register (adm) to 1. <3> set the channel to be used in the analog input m ode by using bits 4 to 0 (adpc4 to adpc0) of the a/d port configuration register (adpc) and bits 7 to 0 (pm27 to pm20) of port mode register 2 (pm2). <4> select conversion time by using bits 5 to 1 (fr2 to fr0, lv1, and lv0) of adm. <5> select a channel to be used by using bits 7 and 2 to 0 (adiss, ads2 to ads0) of the analog input channel specification register (ads). <6> set bit 7 (adcs) of adm to 1 to start a/d conversion. <7> when one a/d conversion has been completed, an interrupt request signal (intad) is generated. <8> transfer the a/d conversion data to the a/d conversion result register (adcr, adcrh). chapter 10 a/d converter user?s manual u17854ej6v0ud 301 10.5 how to read a/d converter characteristics table here, special terms unique to the a/d converter are explained. (1) resolution this is the minimum analog input vo ltage that can be identif ied. that is, the perce ntage of the analog input voltage per bit of digital output is called 1lsb (least si gnificant bit). the percentage of 1lsb with respect to the full scale is expressed by %fsr (full scale range). 1lsb is as follows when the resolution is 10 bits. 1lsb = 1/2 10 = 1/1024 = 0.098%fsr accuracy has no relation to resolution, but is determined by overall error. (2) overall error this shows the maximum error value between the actual measured value and the theoretical value. zero-scale error, full-scale error, integral linearity error, and differential linearity errors that are combinations of these express the overall error. note that the quantization error is not included in the overall erro r in the characteristics table. (3) quantization error when analog values are converted to digital values, a 1/2lsb error naturally occurs. in an a/d converter, an analog input voltage in a range of 1/2lsb is converted to the same digita l code, so a quantization error cannot be avoided. note that the quantization erro r is not included in the overall error, zero -scale error, full-scale error, integral linearity error, and differential linearity error in the characteristics table. figure 10-15. overall error figur e 10-16. quanti zation error ideal line 0 ...... 0 1 ...... 1 digital output overall error analog input av ref 0 0......0 1 ...... 1 digital output quantization error 1/2lsb 1/2lsb analog input 0 av ref (4) zero-scale error this shows the difference between the actual measuremen t value of the analog input vo ltage and the theoretical value (1/2lsb) when the digital output changes from 0......000 to 0......001. if the actual measurement value is greater than the theore tical value, it shows the difference between the actual measurement value of the analog in put voltage and the theoretical val ue (3/2lsb) when the digital output changes from 0??001 to 0??010. chapter 10 a/d converter user?s manual u17854ej6v0ud 302 (5) full-scale error this shows the difference between the actual measuremen t value of the analog input vo ltage and the theoretical value (full-scale ? 3/2lsb) when the digital output chan ges from 1......110 to 1......111. (6) integral linearity error this shows the degree to which the conversion charac teristics deviate from the ideal linear relationship. it expresses the maximum value of the di fference between the actual measurement value and the ideal straight line when the zero-scale error and full-scale error are 0. (7) differential linearity error while the ideal width of code output is 1lsb, this indi cates the difference between the actual measurement value and the ideal value. figure 10-17. zero-scale error figure 10-18. full-scale error 111 011 010 001 zero-scale error ideal line 000 01 2 3 av ref digital output (lower 3 bits) analog input (lsb) 111 110 101 000 0 av ref ? 3 full-scale error ideal line analog input (lsb) digital output (lower 3 bits) av ref ? 2av ref ? 1 av ref figure 10-19. integral linearity error figure 10-20. differential linearity error 0 av ref digital output analog input integral linearity error ideal line 1 ...... 1 0 ...... 0 0 av ref digital output analog input differential linearity error 1 ...... 1 0 ...... 0 ideal 1lsb width (8) conversion time this expresses the time from the start of samp ling to when the digital output is obtained. the sampling time is included in the conv ersion time in the characteristics table. (9) sampling time this is the time the analog switch is turned on for the anal og voltage to be sampled by the sample & hold circuit. sampling time conversion time chapter 10 a/d converter user?s manual u17854ej6v0ud 303 10.6 cautions for a/d converter (1) operating current in stop mode the a/d converter stops operating in the stop mode. at this time, th e operating current can be reduced by clearing bit 7 (adcs) and bit 0 (adce) of the a/d converter mode register (adm) to 0. to restart from the standby status, clear bit 0 (adif) of interrupt request flag register 1l (if1l) to 0 and start operation. (2) input range of ani0 to ani7 observe the rated range of the ani0 to an i7 input voltage. if a voltage of av ref or higher and av ss or lower (even in the range of absolute maximum ratings) is input to an analog input channel, the converted value of that channel becomes undefined. in addition, the converted values of the other channels may also be affected. (3) conflicting operations <1> conflict between a/d conversion result regist er (adcr, adcrh) write and adcr or adcrh read by instruction upon the end of conversion adcr or adcrh read has priority. after the read op eration, the new co nversion result is written to adcr or adcrh. <2> conflict between adcr or adcrh write and a/d converter mode regi ster (adm) write, analog input channel specification register (ads), or a/d port configuration register (a dpc) write upon the end of conversion adm, ads, or adpc write has priority. adcr or adcrh write is not performed, nor is the conversion end interrupt signal (intad) generated. (4) noise countermeasures to maintain the 10-bit resolution, attent ion must be paid to noise input to the av ref pin and pins ani0 to ani7. <1> connect a capacitor with a low equivalent resistance and a good frequency response to the power supply. <2> the higher the output impedance of the analog input source, the greater the influence. to reduce the noise, connecting external c as shown in figure 10-21 is recommended. <3> do not switch these pins wit h other pins during conversion. <4> the accuracy is improved if the halt mode is set immediately after the start of conversion. chapter 10 a/d converter user?s manual u17854ej6v0ud 304 figure 10-21. analog input pin connection reference voltage input c = 100 to 1,000 pf if there is a possibility that noise equal to or higher than av ref or equal to or lower than av ss may enter, clamp with a diode with a small v f value (0.3 v or lower). av ref av ss v ss ani0 to ani7 (5) ani0/p20 to ani7/p27 <1> the analog input pins (ani0 to ani7) are also used as input port pins (p20 to p27). when a/d conversion is performed with any of ani0 to ani7 selected, do not access p20 to p27 while conversion is in progress; otherwis e the conversion resolution may be degraded. it is recommended to select pins used as p20 to p27 starting wit h the ani0/p20 that is the furthest from av ref . <2> if a digital pulse is applied to the pins adjacent to t he pins currently used for a/ d conversion, the expected value of the a/d conversion may not be obtained due to coupling noise. t herefore, do not apply a pulse to the pins adjacent to the pi n undergoing a/d conversion. (6) input impedance of ani0 to ani7 pins this a/d converter charges a sampling capacitor for sampling during sampling time. therefore, only a leakage current fl ows when sampling is not in progre ss, and a current that charges the capacitor flows during sampling. consequently, the input impedance fluctuates depending on whether sampling is in progress, and on the other states. to make sure that sampling is effective, however, it is recommended to keep the ou tput impedance of the analog input source to within 10 k , and to connect a capacitor of about 100 pf to the ani0 to ani7 pins (see figure 10- 21 ). (7) av ref pin input impedance a series resistor string of several tens of k is connected between the av ref and av ss pins. therefore, if the output impedance of t he reference voltage source is high, this will result in a series connection to the series resistor string between the av ref and av ss pins, resulting in a large reference voltage error. chapter 10 a/d converter user?s manual u17854ej6v0ud 305 (8) interrupt request flag (adif) the interrupt request flag (adif) is not cleared even if th e analog input channel specification register (ads) is changed. therefore, if an analog input pin is changed during a/d conversion, the a/d conversion result and adif for the pre-change analog input may be set just before the ads rewrit e. caution is therefore re quired since, at this time, when adif is read immediately after the ads rewrite, ad if is set despite the fact a/d conversion for the post- change analog input has not ended. when a/d conversion is stopped and then resumed, clear ad if before the a/d conversion operation is resumed. figure 10-22. timing of a/d conver sion end interrupt request generation ads rewrite (start of anin conversion) a/d conversion adcr adif anin anin anim anim anin anin anim anim ads rewrite (start of anim conversion) adif is set but anim conversion has not ended. remarks 1. n = 0 to 7 2. m = 0 to 7 (9) conversion results just after a/d conversion start the first a/d conversion value immediately after a/d conv ersion starts may not fall wit hin the rating range if the adcs bit is set to 1 within 1 s after the adce bit was set to 1, or if t he adcs bit is set to 1 with the adce bit = 0. take measures such as pollin g the a/d conversion end interrupt r equest (intad) and removing the first conversion result. (10) a/d conversion result regist er (adcr, adcrh) read operation when a write operation is performed to the a/d conver ter mode register (adm), analog input channel specification register (ads), and a/ d port configuration register (adp c), the contents of adcr and adcrh may become undefined. read the conversion re sult following conversion completion before writing to adm, ads, and adpc. using a timing other than the above may cause an incorrect conversion result to be read. chapter 10 a/d converter user?s manual u17854ej6v0ud 306 (11) internal equivalent circuit the equivalent circuit of the analog input block is shown below. figure 10-23. internal equi valent circuit of anin pin anin c1 c2 r1 table 10-4. resistance and capacitance valu es of equivalent circui t (reference values) av ref r1 c1 c2 4.0 v v dd 5.5 v 8.1 k 8 pf 5 pf 2.7 v v dd < 4.0 v 31 k 8 pf 5 pf 2.3 v v dd < 2.7 v 381 k 8 pf 5 pf remarks 1. the resistance and capacitance values shown in table 10-4 are not guaranteed values. 2. n = 0 to 7 user?s manual u17854ej6v0ud 307 chapter 11 serial array unit the serial array unit has four serial channels per unit and can use two or more of various serial interfaces (3-wire serial (csi), uart, and simplified i 2 c) in combination. function assignment of each channel supported by the 78k0r/ke3 is as s hown below (channels 2 and 3 of unit 1 are dedicated to uart3 (supporting lin-bus)). unit channel used as csi used as uart used as simplified i 2 c 0 csi00 ? 1 ? uart0 ? 2 csi10 iic10 0 3 ? uart1 ? 0 ? ? ? 1 ? ? ? 2 ? ? 1 3 ? uart3 (supporting lin-bus) ? (example of combination) when ?uart1? is used for ch annels 2 and 3 of unit 0, csi10 and iic10 cannot be used, but csi00 or uart0 can be used. 11.1 functions of serial array unit each serial interface supported by the 78k0r/ke3 has the following features. 11.1.1 3-wire serial i/o (csi00, csi10) this is a clocked communication function that uses thr ee lines: serial clock (sck) and serial data (si and so) lines. [data transmission/reception] ? data length of 7 or 8 bits ? phase control of transmit/receive data ? msb/lsb first selectable ? level setting of transmit/receive data [clock control] ? master/slave selection ? phase control of i/o clock ? setting of transfer period by prescaler and internal counter of each channel [interrupt function] ? transfer end interrupt/buffer empty interrupt [error detection flag] ? overrun error chapter 11 serial array unit user?s manual u17854ej6v0ud 308 11.1.2 uart (uart0, uart1, uart3) this is a start-stop synchronization function using two lines: serial data transmission (t x d) and serial data reception (r x d) lines. it transmits or receives data in asynchr onization with the party of communication (by using an internal baud rate). full-duplex uart communication ca n be realized by using two channels, one dedicated to transmission (even channel) and the other to reception (odd channel). [data transmission/reception] ? data length of 5, 7, or 8 bits ? select the msb/lsb first ? level setting of transmit/recei ve data and select of reverse ? parity bit appending and parity check functions ? stop bit appending [interrupt function] ? transfer end interrupt/buffer empty interrupt ? error interrupt in case of framing error, parity error, or overrun error [error detection flag] ? framing error, parity error, or overrun error the lin-bus is accepted in uart 3 (2 and 3 channels of unit 1) [lin-bus functions] ? wakeup signal detection ? sync break field (sbf) detection ? sync field measurement, baud rate calculation 11.1.3 simplified i 2 c (iic10) this is a clocked communication function to communicate wit h two or more devices by using two lines: serial clock (scl) and serial data (sda). this simplified i 2 c is designed for single communicati on with a device such as eeprom, flash memory, or a/d converter, and ther efore, it functions only as a master and does not have a function to detect wait states. make sure by using software, as well as operating the control regist ers, that the ac specif ications of the start and stop conditions are observed. [data transmission/reception] ? master transmission, master reception (onl y master function with a single master) ? ack output and ack detection functions ? data length of 8 bits (when an address is transmitted, the address is specified by the higher 7 bits, and the least significant bit is used for r/w control.) ? manual generation of start condition and stop condition [interrupt function] ? transfer end interrupt [error detection flag] ? parity error (ack error) * [functions not supported by simplified i 2 c] ? slave transmission, slave reception ? arbitration loss detection function ? wait detection functions remark to use an i 2 c bus of full function, see chapter 12 serial interface iic0 . external interrupt (intp0) or timer array unit (tau) is used. chapter 11 serial array unit user?s manual u17854ej6v0ud 309 11.2 configuration of serial array unit serial array unit includes the following hardware. table 11-1. configuration of serial array unit item configuration shift register 8 bits buffer register lower 8 bits of serial data register mn (sdrmn) note serial clock i/o sck00, sck10 pins (for 3-wire seri al i/o), scl10 pin (for simplified i 2 c) serial data input si00, si10 pins (for 3-wire serial i/o), r x d0, r x d1 pins (for uart), r x d3 pin (for uart supporting lin-bus) serial data output so00, so10 pins (for 3-wire serial i/o), t x d0, t x d1 pins (for uart), t x d3 pin (for uart supporting lin-bus), output controller serial data i/o sda10 pin (for simplified i 2 c) chapter 11 serial array unit user?s manual u17854ej6v0ud 310 figure 11-1 shows the block diagram of serial array unit 0. figure 11-1. block diagram of serial array unit 0 serial transfer end interrupt (when uart0: intsr0) serial clock select register 0 (sps0) prs 013 4 prs 003 prs 012 prs 011 prs 010 prs 002 prs 001 prs 000 4 f clk f clk /2 0 to f clk /2 11 selector f clk /2 0 to f clk /2 11 selector cks00 md001 ccs00 sts00 md002 mode selection csi00 or uart0 (for transmission) edge detection communication controller shift register serial data register 00 (sdr00) interrupt controller edge/level detection serial output register 0 (so0) 0 soe02 0 soe00 serial output enable register 0 (soe0) serial clock i/o pin (when csi00: sck00) pm10 sau0en peripheral enable register 0 (per0) serial data input pin (when csi00: si00) (when uart0: rxd0) serial data output pin (when csi00: so00) (when uart0: t x d0) serial mode register 00 (smr00) se03 se02 se01 se00 serial channel enable status register 0 (se0) st03 st02 st01 st00 serial channel stop register 0 (st0) ss03 ss02 ss01 ss00 serial channel start register 0 (ss0) (buffer register block) (clock division setting block) error controller txe 00 rxe 00 dap 00 ckp 00 serial communication operation setting register 00 (scr00) eoc 00 fect 00 pect 00 serial flag clear trigger register 00 (sir00) ovct 00 ptc 001 slc 000 ptc 000 dir 00 slc 001 dls 002 dls 001 dls 000 tsf 00 ovf 00 bff 00 fef 00 pef 00 serial status register 00 (ssr00) output controller serial transfer end interrupt (when csi00: intcsi00) (when uart0: intst0) error information clear channel 0 mode selection uart0 (for reception) communication controller channel 1 serial data input pin (when csi10: si10) (when iic10: sda10) (when uart1: r x d1) serial data output pin (when csi10: so10) (when iic10: sda10) (when uart1: t x d1) serial transfer end interrupt (when csi10: intcsi10) (when iic10: intiic10) (when uart1: intst1) mode selection csi10 or iic10 or uart1 (for transmission) communication controller channel 2 mode selection uart1 (for reception) communication controller channel 3 ck01 ck00 mck tclk sck prescaler output latch (p10) serial clock i/o pin (when csi10: sck10) (when iic10: scl10) serial transfer error interrupt (intsre0) serial transfer end interrupt (when uart1: intsr1) serial transfer error interrupt (intsre1) ck01 ck00 ck01 ck00 ck01 ck00 snfen 10 noise filter enable register 0 (nfen0) snfen 00 noise elimination enabled/ disabled snfen00 edge/level detection when uart0 edge/level detection edge/level detection noise elimination enabled/ disabled snfen10 when uart1 pm12 output latch (p12) 0 sol02 0 sol00 serial output level register 0 (sol0) error controller error controller selector clock controller selector communication status inttm02 1 1 cko02 1 cko00 so02 1 so00 0 0 00 0 0 00 chapter 11 serial array unit user?s manual u17854ej6v0ud 311 figure 11-2 shows the block diagram of serial array unit 1. figure 11-2. block diagram of serial array unit 1 prs 113 4 prs 103 prs 112 prs 111 prs 110 prs 102 prs 101 prs 100 4 f clk f clk /2 0 - f clk /2 11 f clk /2 0 - f clk /2 11 cks12 md121 ccs12 sts12 md122 sau1en txe 12 rxe 12 dap 12 ckp 12 eoc 12 fect 12 pect 12 ovct 12 ptc 121 slc 120 ptc 120 dir 12 slc 121 dls 122 dls 121 dls 120 tsf 12 ovf 12 bff 12 fef 12 pef 12 serial transfer end interrupt (when uart3: intst3) ck11 ck10 mck tclk cks13 md131 ccs13 sts13 md132 txe 13 rxe 13 dap 13 ckp 13 eoc 13 fect 13 pect 13 ovct 13 ptc 131 slc 130 ptc 130 dir 13 slc 131 dsl 132 dsl 131 dsl 130 tsf 13 ovf 13 bff 13 fef 13 pef 13 serial transfer end interrupt i (when uart3: intsr3) ck11 ck10 mck tclk serial data input pin (when uart3: rxd3) snfen30 snfen 30 serial data output pin (when uart3: txd3) pm14 or pm13 output latch (p14 or p13) 0 soe12 00 se13 se12 00 st13 st12 00 ss13 ss12 00 sol12 00 peripheral enable register 0 (per0) serial clock select register 1 (sps1) serial output register 1 (so1) noise filter enable register 0 (nfen0) serial output enable register 1 (soe1) serial channel enable status register 1 (se1) serial channel stop register 1 (st1) serial channel start register 1 (ss1) serial output level register 1 (sol1) prescaler channel 2 (lin-bus supported) serial data register 12 (sdr12) (buffer register block) (clock division setting block) shift register selector clock controller selector interrupt controller output controller mode selection uart3 (for transmission) communication controller serial flag clear trigger register 12 (sir12) noise elimination enabled/ disabled serial mode register 12 (smr12) communication status clear error information error controller serial status register 12 (ssr12) serial communication operation setting register 12 (scr12) selector selector channel 3 (lin-bus supported) serial data register 13 (sdr13) (buffer register block) (clock division setting block) shift register selector clock controller selector serial mode register 13 (smr13) edge/level detection when uart3 serial communication operation setting register 13 (scr13) serial status register 13 (ssr13) communication status error controller clear error information serial transfer error interrupt (intsre3) interrupt controller mode selection uart3 (for reception) communication controller serial flag clear trigger register 13 (sir13) 0 inttm03 1 1 1 11 so12 11 0 0 00 0 0 00 chapter 11 serial array unit user?s manual u17854ej6v0ud 312 (1) shift register this is an 8-bit register that converts para llel data into serial data or vice versa. during reception, it converts data inpu t to the serial pin into parallel data. when data is transmitted, the value set to this register is output as serial data from the serial output pin. the shift register cannot be dire ctly manipulated by program. to read or write the shift register, use the lowe r 8 bits of serial data register mn (sdrmn). 7 6 5 4 3 2 1 0 shift register (2) lower 8 bits of the serial data register mn (sdrmn) sdrmn is the transmit/receive data regist er (16 bits) of channel n. bits 7 to 0 function as a transmit/receive buffer register, and bits 15 to 9 are used as a register that sets the division ratio of the operation clock (mck). when data is received, parallel data converted by the shift register is stored in the lower 8 bits. when data is to be transmitted, set transmit to be transferred to the shift register to the lower 8 bits. the data stored in the lower 8 bits of this register is as follows, depending on the setting of bits 0 to 2 (dlsmn0 to dlsmn2) of the scrmn register, r egardless of the output sequence of the data. ? 5-bit data length (stored in bits 0 to 4 of sdrmn register) (settable in uart mode only) ? 7-bit data length (stored in bits 0 to 6 of sdrmn register) ? 8-bit data length (stored in bits 0 to 7 of sdrmn register) sdrmn can be read or written in 16-bit units. the lower 8 bits of sdrmn of sdrmn can be read or written note as the following sfr, depending on the communication mode. ? csip communication ? siop (csip data register) ? uartq reception ? rxdq (uartq receive data register) ? uartq transmission ? txdq (uartq transmit data register) ? iic10 communication ? sio10 (iic10 data register) reset signal generation clears this register to 0000h. remarks 1. after data is received, ?0? is stored in bits 0 to 7 in bit portions that exceed the data length. 2. m: unit number (m = 0, 1), n: channel number (n = 0 to 3), mn = 00 to 03, 12, 13 p: csi number (p = 00, 10), q: uart number (q = 0, 1, 3) note writing in 8-bit units is prohibited when the operation is stopped (semn = 0). chapter 11 serial array unit user?s manual u17854ej6v0ud 313 figure 11-3. format of serial data register mn (sdrmn) address: fff10h, fff11h (sdr00), fff12h, fff13h (sdr01), after reset: 0000h r/w fff44h, fff45h (sdr02), fff46h, fff47h (sdr03), fff14h, fff15h (sdr12), fff16h, fff17h (sdr13) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sdrmn 0 (m = 0, 1; n = 0 to 3) 7 6 5 4 3 2 1 0 shift register caution be sure to clear bit 8 to ?0?. remarks 1. for the function of the hi gher 7 bits of sdrmn, see 11.3 registers controlling serial array unit . 2. m: unit number (m = 0, 1), n: channel number (n = 0 to 3), mn = 00 to 03, 12, 13 p: csi number (p = 00, 10), q: uart number (q = 0, 1, 3) fff11h (sdr00) fff10h (sdr00) chapter 11 serial array unit user?s manual u17854ej6v0ud 314 11.3 registers controlling serial array unit serial array unit is controlled by the following registers. ? peripheral enable register 0 (per0) ? serial clock select register m (spsm) ? serial mode register mn (smrmn) ? serial communication operation setting register mn (scrmn) ? serial data register mn (sdrmn) ? serial status register mn (ssrmn) ? serial flag clear trigger register mn (sirmn) ? serial channel enable status register m (sem) ? serial channel start register m (ssm) ? serial channel stop register m (stm) ? serial output enable register m (soem) ? serial output level register m (solm) ? serial output register m (som) ? input switch control register (isc) ? noise filter enable register 0 (nfen0) ? port input mode registers 0 (pim0) ? port output mode registers 0 (pom0) ? port mode registers 0, 1 (pm0, pm1) ? port registers 0, 1 (p0, p1) remark m: unit number (m = 0, 1) n: channel number (n = 0 to 3) mn = 00 to 03, 12, 13 chapter 11 serial array unit user?s manual u17854ej6v0ud 315 (1) peripheral enable register 0 (per0) per0 is used to enable or disable use of each peripheral hardware macro. clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise. when serial array unit 0 is used, be sure to set bit 2 (sau0en) of this register to 1. when serial array unit 1 is used, be sure to set bit 3 (sau1en) of this register to 1. per0 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clea rs this register to 00h. figure 11-4. format of peripheral enable register 0 (per0) address: f00f0h after reset: 00h r/w symbol <7> 6 <5> <4> <3> <2> 1 <0> per0 rtcen 0 adcen iic0en sau1en sau0en 0 tau0en saumen control of serial array unit m input clock 0 stops supply of input clock. ? sfr used by serial array unit m cannot be written. ? serial array unit m is in the reset status. 1 supplies input clock. ? sfr used by serial array unit m can be read/written. cautions 1. when setting serial array unit m, be sure to set saumen to 1 first. if saumen = 0, writing to a control register of serial array unit m is igno red, and, even if the register is read, only the default value is read (excep t for input switch control regist er (isc), noise filter enable register (nfen0), port input mode register (pim0), port output mode register (pom0), port mode registers (pm0, pm1), and port registers (p0, p1)). 2. after setting the per0 register to 1, be su re to set the spsm register after 4 or more clocks have elapsed. 3. be sure to clear bits 1 and 6 of per0 register to 0. remark m: unit number (m = 0, 1) (2) serial clock select register m (spsm) spsm is a 16-bit register that is used to select two types of opera tion clocks (ckm0, ckm1) that are commonly supplied to each channel. ckm1 is selected by bits 7 to 4 of spsm, and ckm0 is selected by bits 3 to 0. rewriting spsm is prohibited when the register is in operation (when semn = 1). spsm can be set by a 16-bit memory manipulation instruction. the lower 8 bits of spsm can be set with an 8-bi t memory manipulation instruction with spsml. reset signal generation clears this register to 0000h. chapter 11 serial array unit user?s manual u17854ej6v0ud 316 figure 11-5. format of serial clock select register m (spsm) address: f0126h, f0127h (sps0), f0166h, f0167h (sps1) after reset: 0000h r/w symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 spsm 0 0 0 0 0 0 0 0 prs m13 prs m12 prs m11 prs m10 prs m03 prs m02 prs m01 prs m00 section of operation clock (ckmp) note 1 prs mp3 prs mp2 prs mp1 prs mp0 f clk = 2 mhz f clk = 5 mhz f clk = 10 mhz f clk = 20 mhz 0 0 0 0 f clk 2 mhz 5 mhz 10 mhz 20 mhz 0 0 0 1 f clk /2 1 mhz 2.5 mhz 5 mhz 10 mhz 0 0 1 0 f clk /2 2 500 khz 1.25 mhz 2.5 mhz 5 mhz 0 0 1 1 f clk /2 3 250 khz 625 khz 1.25 mhz 2.5 mhz 0 1 0 0 f clk /2 4 125 khz 313 khz 625 khz 1.25 mhz 0 1 0 1 f clk /2 5 62.5 khz 156 khz 313 khz 625 khz 0 1 1 0 f clk /2 6 31.3 khz 78.1 khz 156 khz 313 khz 0 1 1 1 f clk /2 7 15.6 khz 39.1 khz 78.1 khz 156 khz 1 0 0 0 f clk /2 8 7.81 khz 19.5 khz 39.1 khz 78.1 khz 1 0 0 1 f clk /2 9 3.91 khz 9.77 khz 19.5 khz 39.1 khz 1 0 1 0 f clk /2 10 1.95 khz 4.88 khz 9.77 khz 19.5 khz 1 0 1 1 f clk /2 11 977 hz 2.44 khz 4.88 khz 9.77 khz 1 1 1 1 inttm02 if m = 0, inttm03 if m = 1 note 2 other than above setting prohibited notes 1. when changing the clock selected for f clk (by changing the system clock control register (ckc) value), do so after having stopped (stm = 000fh) t he operation of the serial array unit (sau). when selecting inttm02 and inttm03 for the operation clock, also stop the timer array unit (tau) (tt0 = 00ffh). 2. sau can be operated at a fixed division ratio of the subsystem clock, regardless of the f clk frequency (main system clock, subsystem clock), by setting the tis02 (if m = 0) and tis03 (if m = 1) bits of the tis0 register of tau to 1, selecting f sub /4 for the input clock, and selecting inttm02 and inttm03 using the spsm register. when changing f clk , however, sau and tau must be stopped as described in note 1 above. cautions 1. be sure to clear bits 15 to 8 to ?0?. 2. after setting the per0 register to 1, be su re to set the spsm register after 4 or more clocks have elapsed. remarks 1. f clk : cpu/peripheral hardware clock frequency f sub : subsystem clock frequency 2. m: unit number (m = 0, 1), p = 0, 1 chapter 11 serial array unit user?s manual u17854ej6v0ud 317 (3) serial mode register mn (smrmn) smrmn is a register that sets an oper ation mode of channel n. it is al so used to select an operation clock (mck), specify whether the serial clock (sck) may be inpu t or not, set a start trigger, an operation mode (csi, uart, or i 2 c), and an interrupt source. this register is also us ed to invert the level of the receive data only in the uart mode. rewriting smrmn is prohibited when the register is in operation (when semn = 1). however, the mdmn0 bit can be rewritten during operation. smrmn can be set by a 16-bit memory manipulation instruction. reset signal generation sets this register to 0020h. figure 11-6. format of serial m ode register mn (smrmn) (1/2) address: f0110h, f0111h (smr00) to f0116h, f0117h (smr03), after reset: 0020h r/w f0154h, f0155h (smr12), f0156h, f0157h (smr13) symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 smrmn cks mn ccs mn 0 0 0 0 0 sts mn 0 sis mn0 1 0 0 md mn2 md mn1 md mn0 cks mn selection of operation cl ock (mck) of channel n 0 prescaler output clock ck m0 set by prs register 1 prescaler output clock ck m1 set by prs register operation clock mck is used by the edge detector. in addition, depending on the setting of the ccsmn bit and the higher 7 bits of the sdrmn register, a transfer clock (tclk) is generated. ccs mn selection of transfer clock (tclk) of channel n 0 divided operation clock mck specified by cksmn bit 1 clock input from sck pin (slave transfer in csi mode) transfer clock tclk is used for the sh ift register, communication controller, output controller, interrupt controller, and error controller. when ccsmn = 0, the division ratio of mck is set by the higher 7 bits of the sdrmn register. sts mn selection of start trigger source 0 only software trigger is valid (selected for csi, uart transmission, and simplified i 2 c). 1 valid edge of r x d pin (selected for uart reception) transfer is started when the above source is satisfied after 1 is set to the ssm register. caution be sure to clear bits 13 to 9, 7, 4, and 3 to ?0?. be sure to set bit 5 to ?1?. remark m: unit number (m = 0, 1), n: channel number (n = 0 to 3), mn = 00 to 03, 12, 13 chapter 11 serial array unit user?s manual u17854ej6v0ud 318 figure 11-6. format of serial m ode register mn (smrmn) (2/2) address: f0110h, f0111h (smr00) to f0116h, f0117h (smr03), after reset: 0020h r/w f0154h, f0155h (smr12), f0156h, f0157h (smr13) symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 smrmn cks mn ccs mn 0 0 0 0 0 sts mn 0 sis mn0 1 0 0 md mn2 md mn1 md mn0 sis mn0 controls inversion of level of receive data of channel n in uart mode 0 falling edge is detected as the start bit. the input communication data is captured as is. 1 rising edge is detected as the start bit. the input communication data is inverted and captured. md mn2 md mn1 setting of operation mode of channel n 0 0 csi mode 0 1 uart mode 1 0 simplified i 2 c mode 1 1 setting prohibited md mn0 selection of interrupt source of channel n 0 transfer end interrupt 1 buffer empty interrupt for successive transmission, the next transmit data is written by setting mdmn0 to 1 when sdrmn data has run out. remark m: unit number (m = 0, 1), n: channel number (n = 0 to 3), mn = 00 to 03, 12, 13 chapter 11 serial array unit user?s manual u17854ej6v0ud 319 (4) serial communication operati on setting register mn (scrmn) scrmn is a communication operation setting regi ster of channel n. it is used to set a data transmission/reception mode, phase of data and clock, whether an error signal is to be masked or not, parity bit, start bit, stop bit, and data length. rewriting scrmn is prohibited when the register is in operation (when semn = 1). scrmn can be set by a 16-bit memory manipulation instruction. reset signal generation sets this register to 0087h. figure 11-7. format of serial communication operation setting register mn (scrmn) (1/3) address: f0118h, f0119h (scr00) to f011eh, f011fh (scr03), after reset: 0087h r/w f015ch, f015dh (scr12), f015eh, f015fh (scr13) symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 scrmn txe mn rxe mn dap mn ckp mn 0 eoc mn ptc mn1 ptc mn0 dir mn 0 slc mn1 slc mn0 0 dls mn2 dls mn1 dls mn0 txe mn rxe mn setting of operation mode of channel n 0 0 does not start communication. 0 1 reception only 1 0 transmission only 1 1 transmission/reception dap mn ckp mn selection of data and clock phase in csi mode 0 0 d7 d6 d5 d4 d3 d2 d1 d0 sckp sop si p input timing 0 1 d7 d6 d5 d4 d3 d2 d1 d0 sckp sop si p input timing 1 0 d7 d6 d5 d4 d3 d2 d1 d0 sckp sop si p input timing 1 1 d7 d6 d5 d4 d3 d2 d1 d0 sckp sop si p input timing be sure to set dapmn, ckpmn = 0, 0 in the uart mode and simplified i 2 c mode. caution be sure to clear bits 3, 6, and 11 to ?0?. be sure to set bit 2 to ?1?. remark m: unit number (m = 0, 1), n: channel number (n = 0 to 3), mn = 00 to 03, 12, 13, p: csi number (p = 00, 10) chapter 11 serial array unit user?s manual u17854ej6v0ud 320 figure 11-7. format of serial communication operation setting register mn (scrmn) (2/3) address: f0118h, f0119h (scr00) to f011eh, f011fh (scr03), after reset: 0087h r/w f015ch, f015dh (scr12), f015eh, f015fh (scr13) symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 scrmn txe mn rxe mn dap mn ckp mn 0 eoc mn ptc mn1 ptc mn0 dir mn 0 slc mn1 slc mn0 0 dls mn2 dls mn1 dls mn0 eoc mn selection of masking of error interr upt signal (intsrex (x = 0, 1, 3)) 0 masks error interrupt intsrex (intsrx is not masked). 1 enables generation of error interrupt intsre x (intsrx is masked if an error occurs). set eocmn = 0 in the csi mode, simplified i 2 c mode, and during uart transmission. set eocmn = 1 during uart reception. setting of parity bit in uart mode ptc mn1 ptc mn0 transmission reception 0 0 does not output the parity bit. receives without parity 0 1 outputs 0 parity. no parity judgment 1 0 outputs even parity. judged as even parity. 1 1 outputs odd parity. judges as odd parity. be sure to set ptcmn1, ptcmn0 = 0, 0 in the csi mode and simplified i 2 c mode. dir mn selection of data transfer sequence in csi and uart modes 0 inputs/outputs data with msb first. 1 inputs/outputs data with lsb first. be sure to clear dirmn = 0 in the simplified i 2 c mode. slc mn1 slc mn0 setting of stop bit in uart mode 0 0 no stop bit 0 1 stop bit length = 1 bit 1 0 stop bit length = 2 bits 1 1 setting prohibited when the transfer end interrupt is selected, the interr upt is generated when all stop bits have been completely transferred. set 1 bit (slcmn1, slcmn0 = 0, 1) during uart reception and in the simplified i 2 c mode. set no stop bit (slcmn1, slcmn0 = 0, 0) in the csi mode. caution be sure to clear bits 3, 6, and 11 to ?0?. be sure to set bit 2 to ?1?. remark m: unit number (m = 0, 1), n: channel number (n = 0 to 3), mn = 00 to 03, 12, 13 chapter 11 serial array unit user?s manual u17854ej6v0ud 321 figure 11-7. format of serial communication operation setting register mn (scrmn) (3/3) address: f0118h, f0119h (scr00) to f011eh, f011fh (scr03), after reset: 0087h r/w f015ch, f015dh (scr12), f015eh, f015fh (scr13) symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 scrmn txe mn rxe mn dap mn ckp mn 0 eoc mn ptc mn1 ptc mn0 dir mn 0 slc mn1 slc mn0 0 dls mn2 dls mn1 dls mn0 dls mn2 dls mn1 dls mn0 setting of data length in csi and uart modes 1 0 0 5-bit data length (stored in bits 0 to 4 of sdrmn register) (settable in uart mode only) 1 1 0 7-bit data length (stored in bits 0 to 6 of sdrmn register) 1 1 1 8-bit data length (stored in bits 0 to 7 of sdrmn register) other than above setting prohibited be sure to set dlsmn0 = 1 in the simplified i 2 c mode. caution be sure to clear bits 3, 6, and 11 to ?0?. be sure to set bit 2 to ?1?. remark m: unit number (m = 0, 1), n: channel number (n = 0 to 3), mn = 00 to 03, 12, 13 chapter 11 serial array unit user?s manual u17854ej6v0ud 322 (5) higher 7 bits of the seria l data register mn (sdrmn) sdrmn is the transmit/receive data regist er (16 bits) of channel n. bits 7 to 0 function as a transmit/receive buffer register, and bits 15 to 9 are used as a register that sets the division ratio of the operation clock (mck). if the ccsmn bit of serial mode register mn (smrmn) is cleared to 0, the clock set by dividing the operating clock by the higher 7 bits of sdrmn is used as the transfer clock. for the function of the lower 8 bits of sdrmn, see 11.2 configuration of serial array unit . sdrmn can be read or written in 16-bit units. however, the higher 7 bits can be written or read on ly when the operation is st opped (semn = 0). during operation (semn = 1), a value is written only to the lower 8 bits of sdrmn. when sdrmn is read during operation, 0 is always read. reset signal generation clears this register to 0000h. figure 11-8. format of serial data register mn (sdrmn) address: fff10h, fff11h (sdr00), fff12h, fff13h (sdr01), after reset: 0000h r/w fff44h, fff45h (sdr02), fff46h, fff47h (sdr03), fff14h, fff15h (sdr12), fff16h, fff17h (sdr13) symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sdrmn 0 sdrmn[15:9] setting of division ratio of operation clock (mck) 0 0 0 0 0 0 0 mck/2 0 0 0 0 0 0 1 mck/4 0 0 0 0 0 1 0 mck/6 0 0 0 0 0 1 1 mck/8 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 1 1 1 1 1 0 mck/254 1 1 1 1 1 1 1 mck/256 cautions 1. be sure to clear bit 8 to ?0?. 2. setting sdrmn[15:9] = (0000000b, 0000001 b) is prohibited when uart is used. remarks 1. for the function of the lower 8 bits of sdrmn, see 11.2 configuration of serial array unit . 2. m: unit number (m = 0, 1) n: channel number (n = 0 to 3) mn = 00 to 03, 12, 13 fff11h (sdr00) fff10h (sdr00) chapter 11 serial array unit user?s manual u17854ej6v0ud 323 (6) serial status register mn (ssrmn) ssrmn is a register that indicates the communication status and error occurrence status of channel n. the errors indicated by this register are a fr aming error, parity error, and overrun error. ssrmn can be read by a 16-bit memory manipulation instruction. the lower 8 bits of ssrmn can be set with an 8-bit memory manipulation instruction with ssrmnl. reset signal generation clears this register to 0000h. figure 11-9. format of serial st atus register mn (ssrmn) (1/2) address: f0100h, f0101h (ssr00) to f0106h, f0107h (ssr03), after reset: 0000h r f0144h, f0145h (ssr12), f0146h, f0147h (ssr13) symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ssrmn 0 0 0 0 0 0 0 0 0 tsf mn bff mn 0 0 fef mn pef mn ovf mn tsf mn communication status indica tion flag of channel n 0 communication is not under execution. 1 communication is under execution. because this flag is an updating flag, it is automatically cleared when the communication operation is completed. this flag is cleared also when the stmn/ssmn bit is set to 1. bff mn buffer register status indication flag of channel n 0 valid data is not stored in the sdrmn register. 1 valid data is stored in the sdrmn register. this is an updating flag. it is automatic ally cleared when transfer from the sdrm n register to the shift register is completed. during reception, it is automatically clear ed when data has been read from the sdrmn register. this flag is cleared also when the stmn/ssmn bit is set to 1. this flag is automatically set if transmit data is written to the sdrmn register when the txemn bit of the scrmn register = 1 (transmission or reception mode in each communi cation mode). it is automatically set if receive data is stored in the sdrmn register when the rxemn bit of t he scrmn register = 1 (trans mission or reception mode in each communication mode). it is also set in case of a reception error. if data is written to the sdrmn register when bffmn = 1, the transmit/receive data stored in the register is discarded and an overrun error (ovfmn = 1) is detected. remark m: unit number (m = 0, 1), n: channel number (n = 0 to 3), mn = 00 to 03, 12, 13 chapter 11 serial array unit user?s manual u17854ej6v0ud 324 figure 11-9. format of serial st atus register mn (ssrmn) (2/2) address: f0100h, f0101h (ssr00) to f0106h, f0107h (ssr03), after reset: 0000h r f0144h, f0145h (ssr12), f0146h, f0147h (ssr13) symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ssrmn 0 0 0 0 0 0 0 0 0 tsf mn bff mn 0 0 fef mn pef mn ovf mn fef mn framing error detecti on flag of channel n 0 no error occurs. 1 a framing error occurs during uart reception. chapter 11 serial array unit user?s manual u17854ej6v0ud 325 (7) serial flag clear trigger register mn (sirmn) sirmn is a trigger register that is used to clear each error flag of channel n. when each bit (fectmn, pectmn, ovctmn) of this regi ster is set to 1, the corresponding bit (fefmn, pefmn, ovfmn) of serial status register mn is cleared to 0. because sirmn is a trigger register, it is cleared immediately when the corresponding bit of ssrmn is cleared. sirmn can be set by a 16-bit memory manipulation instruction. the lower 8 bits of sirmn can be set with an 8-bi t memory manipulation instruction with sirmnl. reset signal generation clears this register to 0000h. figure 11-10. format of serial flag clear trigger register mn (sirmn) address: f0108h, f0109h (sir00) to f010eh, f010fh (sir03), after reset: 0000h r/w f014ch, f014dh (sir12), f014eh, f014fh (sir13) symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sirmn 0 0 0 0 0 0 0 0 0 0 0 0 0 fec tmn pec tmn ovc tmn fec tmn clear trigger of fram ing error of channel n 0 no trigger operation 1 clears the fefmn bit of the ssrmn register to 0. pec tmn clear trigger of parity error flag of channel n 0 no trigger operation 1 clears the pefmn bit of the ssrmn register to 0. ovc tmn clear trigger of overrun error flag of channel n 0 no trigger operation 1 clears the ovfmn bit of the ssrmn register to 0. caution be sure to clear bits 15 to 3 to ?0?. remarks 1. m: unit number (m = 0, 1), n: channel number (n = 0 to 3), mn = 00 to 03, 12, 13 2. when the sirmn register is read, 0000h is always read. chapter 11 serial array unit user?s manual u17854ej6v0ud 326 (8) serial channel enable status register m (sem) sem indicates whether data transmission/reception ope ration of each channel is enabled or stopped. when 1 is written a bit of serial channel start register 0 ( ssm), the corresponding bit of this register is set to 1. when 1 is written a bit of serial channel stop regi ster 0 (stm), the corresponding bit is cleared to 0. channel n that is enabled to operate cannot rewrite by software the value of ckomn of the serial output register m (som) to be described below, and a value reflec ted by a communication oper ation is output from the serial clock pin. channel n that stops operation can se t the value of ckomn of the som r egister by software and output its value from the serial clock pin. in this way, any wavefo rm, such as that of a start condition/stop condition, can be created by software. sem can be read by a 16-bit memory manipulation instruction. the lower 8 bits of sem can be set with an 1-bit or 8-bit memory manipulation instruction with seml. reset signal generation clears this register to 0000h. figure 11-11. format of serial channe l enable status register m (sem) address: f0120h, f0121h after reset: 0000h r symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 se0 0 0 0 0 0 0 0 0 0 0 0 0 se0 3 se0 2 se0 1 se0 0 address: f0160h, f0161h after reset: 0000h r symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 se1 0 0 0 0 0 0 0 0 0 0 0 0 se1 3 se1 2 0 0 sem n indication of operation enable/stop status of channel n 0 operation stops (stops with the values of the control r egister and shift register, and the statuses of the serial clock i/o pin, serial data output pin, and the fef, pef, and ovf error flags retained note ). 1 operation is enabled. note bits 6 and 5 (tsfmn, bffmn) of the ssrmn register are cleared. remark m: unit number (m = 0, 1), n: channel number (n = 0 to 3), mn = 00 to 03, 12, 13 chapter 11 serial array unit user?s manual u17854ej6v0ud 327 (9) serial channel start register m (ssm) ssm is a trigger register that is used to enab le starting communication/count by each channel. when 1 is written a bit of this register (ssmn), the co rresponding bit (semn) of serial channel enable status register m (sem) is set to 1. because ssmn is a trigger bit, it is cleared immediately when semn = 1. ssm can be set by a 16-bit memory manipulation instruction. the lower 8 bits of ssm can be set with an 1-bit or 8-bit memory manipulation instruction with ssml. reset signal generation clears this register to 0000h. figure 11-12. format of serial channel start register m (ssm) address: f0122h, f0123h after reset: 0000h r/w symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ss0 0 0 0 0 0 0 0 0 0 0 0 0 ss03 ss02 ss01 ss00 address: f0162h, f0163h after reset: 0000h r/w symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ss1 0 0 0 0 0 0 0 0 0 0 0 0 ss13 ss12 0 0 ssmn operation start trigger of channel n 0 no trigger operation 1 sets semn to 1 and enters the communication wait st atus (if a communication operation is already under execution, the operation is stopped and the start condition is awaited). caution be sure to clear bits 15 to 4 of ss0 , and bits 15 to 4, 1 and 0 of ss1 to ?0?. remarks 1. m: unit number (m = 0, 1), n: channel number (n = 0 to 3), mn = 00 to 03, 12, 13 2. when the ssm register is read, 0000h is always read. chapter 11 serial array unit user?s manual u17854ej6v0ud 328 (10) serial channel stop register m (stm) stm is a trigger register that is used to en able stopping communication/count by each channel. when 1 is written a bit of this register (stmn), the corresponding bit (semn) of serial channel enable status register m (sem) is cleared to 0. because stmn is a trigger bit, it is cleared immediately when semn = 0. stm can set written by a 16-bit me mory manipulation instruction. the lower 8 bits of stm can be set with an 1-bit or 8-bit memory manipulation instruction with stml. reset signal generation clears this register to 0000h. figure 11-13. format of serial channel stop register m (stm) address: f0124h, f0125h after reset: 0000h r/w symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 st0 0 0 0 0 0 0 0 0 0 0 0 0 st0 3 st0 2 st0 1 st0 0 address: f0164h, f0165h after reset: 0000h r/w symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 st1 0 0 0 0 0 0 0 0 0 0 0 0 st1 3 st1 2 0 0 stm n operation stop trigger of channel n 0 no trigger operation 1 clears semn to 0 and stops the communication operation. (stops with the values of the contro l register and shift register, and the st atuses of the serial clock i/o pin, serial data output pin, and the fef, pef, and ovf error flags retained note .) note bits 6 and 5 (tsfmn, bffmn) of the ssrmn register are cleared. caution be sure to clear bits 15 to 4 of st0, and bits 15 to 4, 1 and 0 of st1 to ?0?. remarks 1. m: unit number (m = 0, 1), n: channel number (n = 0 to 3), mn = 00 to 03, 12, 13 2. when the stm register is read, 0000h is always read. chapter 11 serial array unit user?s manual u17854ej6v0ud 329 (11) serial output enable register m (soem) soem is a register that is used to enable or stop output of the serial communication operation of each channel. channel n that enables serial output ca nnot rewrite by software the value of somn of the serial output register m (som) to be described below, and a value reflected by a communication operation is output from the serial data output pin. for channel n, whose serial output is stopped, the somn valu e of the som register can be set by software, and that value can be output from the se rial data output pin. in this way, any waveform of the start condition and stop condition can be created by software. soem can be set by a 16-bit memory manipulation instruction. the lower 8 bits of soem can be set with an 1-bit or 8-bit memory manipulation instruction with soeml. reset signal generation clears this register to 0000h. figure 11-14. format of serial output enable register m (soem) address: f012ah, f012bh after reset: 0000h r/w symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 soe0 0 0 0 0 0 0 0 0 0 0 0 0 0 soe 02 0 soe 00 address: f016ah, f016bh after reset: 0000h r/w symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 soe1 0 0 0 0 0 0 0 0 0 0 0 0 0 soe 12 0 0 soe mn serial output enable/disable of channel n 0 stops output by serial communication operation. 1 enables output by serial communication operation. caution be sure to clear bits 15 to 3 and 1 of so e0, and bits 15 to 3, 1 and 0 of soe1 to ?0?. remark m: unit number (m = 0, 1), n: channel number (n = 0, 2), mn = 00, 02, 12 chapter 11 serial array unit user?s manual u17854ej6v0ud 330 (12) serial output register m (som) som is a buffer register for serial output of each channel. the value of bit n of this regi ster is output from the serial data output pin of channel n. the value of bit (n + 8) of this register is outp ut from the serial clock output pin of channel n. somn of this register can be rewritten by software only when serial output is disabled (soemn = 0). when serial output is enabled (soemn = 1), rewriting by softw are is ignored, and the value of the register can be changed only by a serial communication operation. ckomn of this register can be rewritten by softwar e only when the channel operation is stopped (semn = 0). while channel operation is enabled (semn = 1), rewrit ing by software is ignored, and the value of ckomn can be changed only by a serial communication operation. to use the p02/so10/txd1, p03/si 10/sda10/rxd1, p04/sck10/scl10, p10/sck00, p12/so00/txd0, or p13/txd3 pin as a port function pin, set the corresponding ckomn and somn bits to ?1?. som can be set by a 16-bit memory manipulation instruction. reset signal generation clears this register to 0f0fh. figure 11-15. format of serial output register m (som) address: f0128h, f0129h after reset: 0f0fh r/w symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 so0 0 0 0 0 1 cko 02 1 cko 00 0 0 0 0 1 so 02 1 so 00 address: f0168h, f0169h after reset: 0f0fh r/w symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 so1 0 0 0 0 1 1 1 1 0 0 0 0 1 so 12 1 1 cko mn serial clock output of channel n 0 serial clock output value is ?0?. 1 serial clock output value is ?1?. so mn serial data output of channel n 0 serial data output value is ?0?. 1 serial data output value is ?1?. caution be sure to set bits 11, 9, 3 and 1 of so0, a nd bits 11 to 8, 3, 1 and 0 of so1 to ?1?. and be sure to clear bits 15 to 12, and 7 to 4 of som to ?0?. remark m: unit number (m = 0, 1), n: channel number (n = 0, 2), mn = 00, 02, 12 chapter 11 serial array unit user?s manual u17854ej6v0ud 331 (13) serial output level register m (solm) solm is a register that is used to set inve rsion of the data output level of each channel. this register can be set only in the uart mode. be sure to set 0000h in the csi mode and simplifies i 2 c mode. inverting channel n by using this register is reflect ed on pin output only when serial output is enabled (soemn = 1). when serial output is disabled (soemn = 0), the value of the somn bit is output as is. rewriting solm is prohibited when the regi ster is in operation (when semn = 1). solm can be set by a 16-bit memory manipulation instruction. the lower 8 bits of solm can be set with an 8-bi t memory manipulation instruction with solml. reset signal generation clears this register to 0000h. figure 11-16. format of serial output level register m (solm) address: f0134h, f0135h after reset: 0000h r/w symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sol0 0 0 0 0 0 0 0 0 0 0 0 0 0 sol 02 0 sol 00 address: f0174h, f0175h after reset: 0000h r/w symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sol1 0 0 0 0 0 0 0 0 0 0 0 0 0 sol 12 0 0 sol mn selects inversion of the level of the transmit data of channel n in uart mode 0 communication data is output as is. 1 communication data is inverted and output. caution be sure to clear bits 15 to 3 and 1 of so l0, and bits 15 to 3, 1 and 0 of sol1 to ?0?. remark m: unit number (m = 0, 1), n: channel number (n = 0, 2), mn = 00, 02, 12 chapter 11 serial array unit user?s manual u17854ej6v0ud 332 (14) input switch control register (isc) isc is used to realize a lin-bus communication operatio n by uart3 in coordination with an external interrupt and the timer array unit. when bit 0 is set to 1, the input signal of the serial data input (r x d3) pin is selected as an external interrupt (intp0) that can be used to detect a wakeup signal. when bit 1 is set to 1, the input signal of the serial data input (r x d3) pin is selected as a timer input, so that the pulse widths of a sync break field and a sync field can be measured by the timer. isc can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clea rs this register to 00h. figure 11-17. format of input switch control register (isc) address: fff3ch after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 isc 0 0 0 0 0 0 isc1 isc0 isc1 switching channel 7 input of timer array unit 0 not uses the input signal (normal operation). 1 input signal of r x d3 pin is used as timer input (wakeup signal detection). isc0 switching external interrupt (intp0) input 0 uses the input signal of the intp0 pin as an external interrupt (normal operation). 1 uses the input signal of the r x d3 pin as an external interrupt (to measure the pulse widths of t he sync break field and sync field). caution be sure to clear bits 7 to 2 to ?0?. remark since the 78k0r/ke3 does not have the timer input pin on channel 7, normally the timer input on channel 7 cannot be used. when the lin-bus comm unication function is used, select the input signal of the rxd3 pin by setting isc1 to 1. chapter 11 serial array unit user?s manual u17854ej6v0ud 333 (15) noise filter enable register 0 (nfen0) nfen0 is used to set whether the noise filter can be used for the input sig nal from the serial data input pin to each channel. disable the noise filter of the pin used for csi or simplified i 2 c communication, by clearing the corresponding bit of this register to 0. enable the noise filter of the pin used for uart communication, by setting the corresponding bit of this register to 1. when the noise filter is enabled, cpu/peripheral operating clock (f clk ) is synchronized with 2-clock match detection. nfen0 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clea rs this register to 00h. figure 11-18. format of noise filter enable register 0 (nfen0) address: f0060h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 nfen0 0 snfen30 0 0 0 snfen10 0 snfen00 snfen30 use of noise filter of r x d3/p14 pin 0 noise filter off 1 noise filter on set snfen30 to 1 to use the r x d3 pin. clear snfen30 to 0 to use the p14 pin. snfen10 use of noise filter of r x d1/sda10/si10/p03 pin 0 noise filter off 1 noise filter on set snfen10 to 1 to use the r x d1 pin. clear snfen10 to 0 to use the sda10, si10, and p03 pins. snfen00 use of noise filter of r x d0/si00/p11 pin 0 noise filter off 1 noise filter on set snfen00 to 1 to use the r x d0 pin. clear snfen00 to 0 to use the si00 and p11 pins. caution be sure to clear bits 7, 5 to 3, and 1 to ?0?. chapter 11 serial array unit user?s manual u17854ej6v0ud 334 (16) port input mode registers 0 (pim0) this register set the input buffer of ports 0 in 1-bit units. pim0 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears these registers to 00h. figure 11-19. format of port in put mode registers 0 (pim0) address f0040h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 pim0 0 0 0 pim04 pim03 0 0 0 pim0n p0n pin input buffer selection (n = 3, 4) 0 normal input buffer 1 ttl input buffer (17) port output mode registers 0 (pom0) this register set the output mode of ports 0 in 1-bit units. pom0 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears these registers to 00h. figure 11-20. format of port output mode registers 0 (pom0) address f0050h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 pom0 0 0 0 pom04 pom03 pom02 0 0 pom0n p0n pin output buffer selection (n = 2 to 4) 0 normal output mode 1 n-ch open-drain output (v dd tolerance) mode chapter 11 serial array unit user?s manual u17854ej6v0ud 335 (18) port mode registers 0, 1 (pm0, pm1) these registers set input/output of ports 0 and 1 in 1-bit units. when using the p02/so10/t x d1, p03/si10/r x d1/sda10, p04/sck10/scl10, p10/sck00, p12/so00/t x d0, p13/t x d3 pins for serial data output or serial clock output, clear the pm02, pm03, pm04, pm10, pm12, and pm13 bits to 0, and set the output latches of p02, p03, p04, p10, p12, and p13 to 1. when using the p03/si10/r x d1/sda10, p04/sck10/scl10, p10/sck00, p11/si00/r x d0, and p14/r x d3 pins for serial data input or serial clock input, set t he pm03, pm04, pm10, pm11, and pm 14 bits to 1. at this time, the output latches of p03, p04, p10, p11, and p14 may be 0 or 1. pm0 and pm1 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation se ts these registers to ffh. figure 11-21. format of port mode registers 0 and 1 (pm0, pm1) address: fff20h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm0 1 pm06 pm05 pm04 pm03 pm02 pm01 pm00 address: fff21h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm1 pm17 pm16 pm15 pm14 pm13 pm12 pm11 pm10 pmmn pmn pin i/o mode selection (m = 0, 1; n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) chapter 11 serial array unit user?s manual u17854ej6v0ud 336 11.4 operation stop mode each serial interface of serial array unit has the operation stop mode. in this mode, serial communication cannot be exec uted, thus reducing the power consumption. in addition, the p02/so10/txd1, p03/si10/sda10/rxd1, p04/sck10/sc l10, p10/sck00, p11/si00/rxd0, p12/so00/txd0, p13/txd3, or p14/rxd3 pin can be used as ordinary port pins in this mode. 11.4.1 stopping the operation by units the stopping of the operation by units is set by using peripheral enable register 0 (per0). per0 is used to enable or disable use of each peripheral ha rdware macro. clock supply to a hardware macro that is not used is stopped in order to r educe the power consumption and noise. to stop the operation of serial array unit 0, set bit 2 (sau0en) to 0. to stop the operation of serial array unit 1, set bit 3 (sau1en) to 0. figure 11-22. peripheral enable register 0 (per 0) setting when stopping the operation by units cautions 1. if saumen = 0, writing to a control register of serial ar ray unit m is ignored, and, even if the register is read, only the default value is read (except for input switch control register (isc), noise filter enable register (nfen0), port input mode register (pim0), port output mode register (pom0), port mode register s (pm0, pm1), and port registers (p0, p1)). 2. be sure to clear bits 1 and 6 of per0 register to 0. remark m: unit number (m = 0, 1), : setting disabled (fixed by hardware) : bits not used with serial array units (dependi ng on the settings of other peripheral functions) 0/1: set to 0 or 1 depending on the usage of the user (a) peripheral enable register 0 (per0) ? set only the bit of saum to be stopped to 0. 7 6 5 4 3 2 1 0 per0 rtcen 0 adcen iic0en sau1en 0/1 sau0en 0/1 0 tau 0 e n control of saum input clock 0: stops supply of input clock 1: su pp lies in p ut cloc k chapter 11 serial array unit user?s manual u17854ej6v0ud 337 11.4.2 stopping the operation by channels the stopping of the operation by channels is se t using each of the following registers. figure 11-23. each register setting when stopping the operation by channels (1/2) (a) serial channel enable status register m ( sem) ? this register indicates whether data transmission/reception operation of eac h channel is enabled or stopped. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 se0 0 0 0 0 0 0 0 0 0 0 0 0 se03 0/1 se02 0/1 se01 0/1 se00 0/1 0: operation stops * the se0 register is a read-only status register, w hose operation is stopped by using the st0 register. with a channel whose operation is stopped, the value of cko0n of the so0 register can be set by software. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 se1 0 0 0 0 0 0 0 0 0 0 0 0 se13 0/1 se12 0/1 0 0 0: operation stops * the se1 register is a read-only status register, w hose operation is stopped by using the st1 register. (b) serial channel stop register m (stm) ? this register is a trigger register th at is used to enable stopping communication/count by each channel. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 st0 0 0 0 0 0 0 0 0 0 0 0 0 st03 0/1 st02 0/1 st01 0/1 st00 0/1 1: clears se0n to 0 and stops the communication operation * because st0n is a trigger bit, it is cleared immediately when se0n = 0. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 st1 0 0 0 0 0 0 0 0 0 0 0 0 st13 0/1 st12 0/1 0 0 1: clears se1n to 0 and stops the communication operation * because st1n is a trigger bit, it is cleared immediately when se1n = 0. remark m: unit number (m = 0, 1), n: channel number (n = 0 to 3) : setting disabled (fixed by hardware), 0/1: set to 0 or 1 depending on the usage of the user chapter 11 serial array unit user?s manual u17854ej6v0ud 338 figure 11-23. each register setting when stopping the operation by channels (2/2) (c) serial output enable register m (soem) ? this regi ster is a register that is used to enable or stop output of the serial communication operation of each channel. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 soe0 0 0 0 0 0 0 0 0 0 0 0 0 0 soe02 0/1 0 soe00 0/1 0: stops output by serial communication operation * for channel n, whose serial output is stopped, the so0n value of the so0 register can be set by software. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 soe1 0 0 0 0 0 0 0 0 0 0 0 0 0 soe12 0/1 0 0 0: stops output by serial communication operation * for channel n, whose serial output is stopped, the so12 value of the so1 register can be set by software. (d) serial output register m (som) ?thi s register is a buffer register for serial output of each channel. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 so0 0 0 0 0 1 cko02 0/1 1 cko00 0/1 0 0 0 0 1 so02 0/1 1 so00 0/1 1: serial clock output value is ?1? 1: serial data output value is ?1? * when using pins corresponding to each c hannel as port function pins, set the corresponding cko0n and so0n bits to ?1?. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 so1 0 0 0 0 1 1 1 1 0 0 0 0 1 so12 0/1 1 1 1: serial data output value is ?1? * when using pins corresponding to each channel as port function pins, set the corresponding so12 bit to ?1?. remark m: unit number (m = 0, 1), n: channel number (n = 0, 2) : setting disabled (fixed by hardware), 0/1: set to 0 or 1 depending on the usage of the user chapter 11 serial array unit user?s manual u17854ej6v0ud 339 11.5 operation of 3-wire serial i/o (csi00, csi10) communication this is a clocked communication function that uses thr ee lines: serial clock (sck) and serial data (si and so) lines. [data transmission/reception] ? data length of 7 or 8 bits ? phase control of transmit/receive data ? msb/lsb first selectable ? level setting of transmit/receive data [clock control] ? master/slave selection ? phase control of i/o clock ? setting of transfer period by prescaler and internal counter of each channel [interrupt function] ? transfer end interrupt/buffer empty interrupt [error detection flag] ? overrun error the channels s upporting 3-wire serial i/o (csi00, csi10) are channels 0, 2 of sau0. unit channel used as csi used as uart used as simplified i 2 c 0 csi00 uart0 ? 1 ? ? 2 csi10 uart1 iic10 0 3 ? ? 0 ? ? ? 1 ? ? ? 2 ? uart3 (supporting lin-bus) ? 1 3 ? ? 3-wire serial i/o (csi00, cis10) performs the fo llowing six types of comm unication operations. ? master transmission (see 11.5.1 .) ? master reception (see 11.5.2 .) ? master transmission/reception (see 11.5.3 .) ? slave transmission (see 11.5.4 .) ? slave reception (see 11.5.5 .) ? slave transmission/reception (see 11.5.6 .) chapter 11 serial array unit user?s manual u17854ej6v0ud 340 11.5.1 master transmission master transmission is that the 78k0r/ke3 outputs a tr ansfer clock and transmits data to another device. 3-wire serial i/o csi00 csi10 target channel channel 0 of sau0 channel 2 of sau0 pins used sck00, so00 sck10, so10 intcsi00 intcsi10 interrupt transfer end interrupt (in single-transfer mode) or buff er empty interrupt (in continuous transfer mode) can be selected. error detection flag none transfer data length 7 or 8 bits transfer rate max. f clk /4 [mhz], min. f clk /(2 2 11 128) [mhz] note f clk : system clock frequency data phase selectable by dap0n bit ? dap0n = 0: data output starts from the start of the operation of the serial clock. ? dap0n = 1: data output starts half a clock before the start of the serial clock operation. clock phase selectable by ckp0n bit ? ckp0n = 0: forward ? ckp0n = 1: reverse data direction msb or lsb first note use this operation within a range that satisfies the co nditions above and the ac characteristics in the electrical specifications (see chapter 27 electrical specifications ). chapter 11 serial array unit user?s manual u17854ej6v0ud 341 (1) register setting figure 11-24. example of contents of register s for master transmission of 3-wire serial i/o (csi00, csi10) (a) serial output register 0 (so0) ? sets only the bits of the target channel. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 so0 0 0 0 0 1 cko02 0/1 1 cko00 0/1 0 0 0 0 1 so02 0/1 1 so00 0/1 communication starts when these bits are 1 if the data phase is forward (ckp0n = 0). if the phase is reversed (ckp0n = 1), communication starts when these bits are 0. (b) serial output enable register 0 (soe0) ? se ts only the bits of the target channel to 1. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 soe0 0 0 0 0 0 0 0 0 0 0 0 0 0 soe02 0/1 0 soe00 0/1 (c) serial channel start register 0 (ss0) ? sets only the bits of the target channel to 1. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ss0 0 0 0 0 0 0 0 0 0 0 0 0 ss03 ss02 0/1 ss01 ss00 0/1 (d) serial mode register 0n (smr0n) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 smr0n cks0n 0/1 ccs0n 0 0 0 0 0 0 sts0n 0 0 sis00 0 1 0 0 md0n2 0 md0n1 0 md0n0 0/1 operation mode of channel n 0: transfer end interrupt 1: buffer empty interrupt (e) serial communication operati on setting register 0n (scr0n) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 scr0n txe0n 1 rxe0n 0 dap0n 0/1 ckp0n 0/1 0 eoc0n 0 ptc0n1 0 ptc0n0 0 dir0n 0/1 0 slc0n1 0 slc0n0 0 0 dls0n2 1 dls0n1 1 dls0n0 0/1 (f) serial data register 0n (sdr0n) (lower 8 bits: siop) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sdr0n baud rate setting 0 transmit data setting remark n: channel number (n = 0, 2), p: csi number (p = 00, 10) : setting is fixed in the csi master transmission mode, : setting disabled (set to the initial value) : bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: set to 0 or 1 depending on the usage of the user siop chapter 11 serial array unit user?s manual u17854ej6v0ud 342 (2) operation procedure figure 11-25. initial setting pr ocedure for master transmission caution after setting the per0 register to 1, be sure to set the sps0 register after 4 or more clocks have elapsed. starting initial setting setting per0 register setting sps0 register setting smr0n register setting scr0n register setting sdr0n register setting so0 register changing setting of soe0 register setting port writing to ss0 register starting communication release the serial array unit from the reset status and start clock supply. set the prescaler. set an operation mode, etc. set a communication format. set a transfer baud rate. manipulate the so0n and cko0n bits and set an initial output level. set the soe0n bit to 1 and enable data output of the target channel. enable data output and cloc k output of the target channel by setting a port register and a port mode register. set transmit data to the siop register (bits 7 to 0 of the sdr0n register) and start communication. se0n = 1 when the ss0n bit of the tar g et channel is set to 1. chapter 11 serial array unit user?s manual u17854ej6v0ud 343 figure 11-26. procedure for stopping master transmission remarks 1. even after communication is stopped, the pin level is retained. to resume the operation, re-set the so0 register (see figure 11-27 procedure for resuming master transmission ). 2. p: csi number (p = 00, 10) starting setting to stop setting st0 register stopping communication write 1 to the st0n bit of the target channel. stop communication in midway. chapter 11 serial array unit user?s manual u17854ej6v0ud 344 figure 11-27. procedure for resuming master transmission starting setting for resumption port manipulation changing setting of sps0 register changing setting of sdr0n register changing setting of smr0n register changing setting of so0 register port manipulation writing to ss0 register starting communication disable data output and clock output of the target channel by setting a port register and a port mode register. change the setting if an incorrect division ratio of the operation clock is set. change the setting if an incorrect transfer baud rate is set. change the setting if the setting of the smr0n register is incorrect. manipulate the so0n and cko0n bits and set an initial output level. enable data output and clock output of the target channel by setting a port register and a port mode register. se0n = 1 when the ss0n bit of the target channel is set to 1. sets transmit data to the siop register (bits 7 to 0 of the sdr0n register) and start communication. (essential) (selective) (selective) (selective) ( selective ) ( essential ) (essential) (essential) change the setting if the setting of the scr0n register is incorrect. (selective) changing setting of scr0n register cleared by using sir0 registe r if fef, pef, or ovf flag remains set. (selective) clearing error flag set the soe0 register and enable data output of the target channel. (selective) changing setting of soe0 register set the soe0 register and stop data output of the target channel. (selective) changing setting of soe0 register chapter 11 serial array unit user?s manual u17854ej6v0ud 345 (3) processing flow (in si ngle-transmission mode) figure 11-28. timing chart of master transmission (in single-transmission mode) ss0n se0n sdr0n sckp pin sop pin shift register 0n intcsip tsf0n data transmission (8-bit length) data transmission (8-bit length) data transmission (8-bit length) transmit data 3 transmit data 2 transmit data 1 transmit data 1 transmit data 2 transmit data 3 shift operation shift operation shift operation remark n: channel number (n = 0, 2), p: csi number (p = 00, 10) chapter 11 serial array unit user?s manual u17854ej6v0ud 346 figure 11-29. flowchart of master tr ansmission (in single-transmission mode) caution after setting the per0 register to 1, be sure to set the sps0 register after 4 or more clocks have elapsed. transfer end interrupt g enerated? transmission completed? starting csi communication writing 1 to ss0n bit writing transmit data to siop (=sdr0n[7:0]) writing 1 to st0n bit perform initial setting when se0n = 0. smr0n, scr0n: setting communication sdr0n[15:9]: setting transfer rate so0, soe0: setting output no no yes yes setting sau1en and sau0en bits of per0 register to 1 setting transfer rate by sps0 register port manipulation clearing sau1en and sau0en bits of per0 register to 0 end of communication chapter 11 serial array unit user?s manual u17854ej6v0ud 347 (4) processing flow (in continuous transmission mode) figure 11-30. timing chart of master transmission (in continuous transmission mode) ss0n se0n sdr0n sckp pin sop pin shift register 0n intcsip tsf0n data transmission (8-bit length) data transmission (8-bit length) transmit data 2 transmit data 1 transmit data1 transmit data 3 bff0n md0n0 transmit data 2 <1> <2> <2> <2> <3> <3> <3> <5> <4> ( note ) shift operation shift operation shift operation transmit data 3 data transmission (8-bit length) note when transmit data is written to the sdr0n register while bff0n = 1, the transmit data is overwritten. caution the md0n0 bit can be re written even during operation. however, rewrite it before transfer of the last bi t is started, so that it will be rewritten before the transfer end interrupt of the last transmit data. remark n: channel number (n = 0, 2), p: csi number (p = 00, 10) chapter 11 serial array unit user?s manual u17854ej6v0ud 348 figure 11-31. flowchart of master transmission (in continuous transmission mode) starting csi communication writing 1 to ss0n bit writing transmit data to siop (=sdr0n[7:0]) writing 1 to st0n bit perform initial setting when se0n = 0. <1> select the buffer empty interrupt. smr0n, scr0n: setting communication sdr0n[15:9]: setting transfer rate so0, soe0; setting output n o n o n o y es setting sau1en and sau0en bits of per0 register to 1 setting transfer rate by sps0 register port manipulation end of communication clearing 0 to md0n0 bit y es n o y es n o communication continued? y es y es clearing sau1en and sau0en bits of per0 register to 0 <2> <3> <4> <5> transmitting next data? buffer empty interrupt generated? transfer end interrupt generated? tsf0n = 1? writing 1 to md0n0 bit caution after setting the per0 register to 1, be sure to set the sps0 register after 4 or more clocks have elapsed. remark <1> to <5> in the figure correspond to <1> to <5> in figure 11-30 timing chart of master transmission (in continuous transmission mode) . chapter 11 serial array unit user?s manual u17854ej6v0ud 349 11.5.2 master reception master reception is that the 78k0 r/ke3 outputs a transfer clock and receives data from other device. 3-wire serial i/o csi00 csi10 target channel channel 0 of sau0 channel 2 of sau0 pins used sck00, si00 sck10, si10 intcsi00 intcsi10 interrupt transfer end interrupt only (setting the buffer empty interrupt is prohibited.) error detection flag overrun error detection flag (ovf0n) only transfer data length 7 or 8 bits transfer rate max. f clk /4 [mhz], min. f clk /(2 2 11 128) [mhz] note f clk : system clock frequency data phase selectable by dap0n bit ? dap0n = 0: data input starts from the start of the operation of the serial clock. ? dap0n = 1: data input starts half a clock be fore the start of the serial clock operation. clock phase selectable by ckp0n bit ? ckp0n = 0: forward ? ckp0n = 1: reverse data direction msb or lsb first note use this operation within a range that satisfies the co nditions above and the ac characteristics in the electrical specifications (see chapter 27 electrical specifications ). chapter 11 serial array unit user?s manual u17854ej6v0ud 350 (1) register setting figure 11-32. example of contents of regist ers for master reception of 3-wire serial i/o (csi00, csi10) (a) serial output register 0 (so0) ? sets only the bits of the target channel. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 so0 0 0 0 0 1 cko02 0/1 1 cko00 0/1 0 0 0 0 1 so02 1 so00 communication starts when these bits are 1 if the data phase is forward (ckp0n = 0). if the phase is reversed (ckp0n = 1), communication starts when these bits are 0. (b) serial output enable register 0 (soe0) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 soe0 0 0 0 0 0 0 0 0 0 0 0 0 0 soe02 0/1 0 soe00 0/1 set these bits to 0 when using them for csi master reception (c) serial channel start register 0 (ss0) ? sets only the bits of the target channel to 1. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ss0 0 0 0 0 0 0 0 0 0 0 0 0 ss03 ss02 0/1 ss01 ss00 0/1 (d) serial mode register 0n (smr0n) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 smr0n cks0n 0/1 ccs0n 0 0 0 0 0 0 sts0n 0 0 sis0n0 0 1 0 0 md0n2 0 md0n1 0 md0n0 0 operation mode of channel n 0: transfer end interrupt (e) serial communication operati on setting register 0n (scr0n) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 scr0n txe0n 0 rxe0n 1 dap0n 0/1 ckp0n 0/1 0 eoc0n 0 ptc0n1 0 ptc0n0 0 dir0n 0/1 0 slc0n1 0 slc0n0 0 0 dls0n2 1 dls0n1 1 dls0n0 0/1 (f) serial data register 0n (sdr0n) (lower 8 bits: siop) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sdr0n baud rate setting 0 receive data register (write ffh as dummy data.) remark n: channel number (n = 0, 2), p: csi number (p = 00, 10) : setting is fixed in the csi master reception mode , : setting disabled (s et to the initial value) : bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: set to 0 or 1 depending on the usage of the user siop chapter 11 serial array unit user?s manual u17854ej6v0ud 351 (2) operation procedure figure 11-33. initial setting procedure for master reception caution after setting the per0 register to 1, be sure to set the sps0 register after 4 or more clocks have elapsed. figure 11-34. procedure for stopping master reception remark even after communication is stopped, the pin level is retained. to resume the operation, re-set the so0 register (see figure 11-35 procedure for resuming master reception ). starting initial setting setting per0 register setting sps0 register setting smr0n register setting scr0n register setting sdr0n register setting so0 register setting port writing to ss0 register starting communication release the serial array unit from the reset status and start clock supply. set the prescaler. set an operation mode, etc. set a communication format. set a transfer baud rate. manipulate the cko0n bit and set an initial output level. enable clock output of the target channel by setting a port register and a port mode register. se0n = 1 when the ss0n bit of the ta r get channel is set to 1. set dummy data to the siop register (bits 7 to 0 of the sdr0n register) and start communication. starting setting to stop setting st0 register stopping communication write 1 to the st0n bit of the target channel. stop communication in midway. chapter 11 serial array unit user?s manual u17854ej6v0ud 352 figure 11-35. procedure for resuming master reception starting setting for resumption port manipulation changing setting of sps0 register changing setting of sdr0n register changing setting of smr0n register changing setting of so0 register port manipulation writing to ss0 register starting communication disable clock output of the target channel by setting a port register and a port mode register. change the setting if an incorrect division ratio of the operation clock is set. change the setting if an incorrect transfer baud rate is set. change the setting if the setting of the smr0n register is incorrect. manipulate the cko0n bit and set a clock output level. enable clock output of the target channel by setting a port register and a port mode register. se0n = 1 when the ss0n bit of the target channel is set to 1. sets dummy data to the siop register (bits 7 to 0 of the sdr0n register) and start communication. (essential) (selective) (selective) ( selective ) (selective) ( essential ) (essential) (essential) change the setting if the setting of the scr0n register is incorrect. (selective) changing setting of scr0n register cleared by using sir0 register if fef, pef, or ovf flag remains set. (selective) clearing error flag clear the soe0 register to 0 and stop data output of the target channel. (essential) changing setting of soe0 register chapter 11 serial array unit user?s manual u17854ej6v0ud 353 (3) processing flow (in single-reception mode) figure 11-36. timing chart of master reception (in single-reception mode) ss0n se0n sdr0n sckp pin sip pin shift register 0n intcsip tsf0n receive data 3 receive data 2 receive data 1 dummy data for reception dummy data dummy data receive data 1 receive data 2 receive data 3 write read write read read write reception & shift operation reception & shift operation reception & shift operation data transmission/reception (8-bit length) data transmission/reception (8-bit length) data transmission/reception (8-bit length) remark n: channel number (n = 0, 2), p: csi number (p = 00, 10) chapter 11 serial array unit user?s manual u17854ej6v0ud 354 figure 11-37. flowchart of master reception (in single-reception mode) starting csi communication writing 1 to ss0n bit writing dummy data to siop (=sdr0n[7:0]) writing 1 to st0n bit perform initial setting when se0n = 0. smr0n, scr0n: setting communication sdr0n[15:9]: setting transfer rate so0, soe0: setting sckp output transfer end interrupt generated? reception completed? no no yes yes setting sau1en and sau0en bits of per0 register to 1 setting transfer rate by sps0 register port manipulation clearing sau1en and sau0en bits of per0 register to 0 end of communication reading siop (= sdr0n[7:0]) register starting reception caution after setting the per0 register to 1, be sure to set the sps0 register after 4 or more clocks have elapsed. chapter 11 serial array unit user?s manual u17854ej6v0ud 355 11.5.3 master transmission/reception master transmission/reception is that the 78k0r/ke3 outputs a transfer clock and transmits/receives data to/from other device. 3-wire serial i/o csi00 csi10 target channel channel 0 of sau0 channel 2 of sau0 pins used sck00, si00, so00 sck10, si10, so10 intcsi00 intcsi10 interrupt transfer end interrupt (in single-transfer mode) or buff er empty interrupt (in continuous transfer mode) can be selected. error detection flag overrun error detection flag (ovf0n) only transfer data length 7 or 8 bits transfer rate max. f clk /4 [mhz], min. f clk /(2 2 11 128) [mhz] note f clk : system clock frequency data phase selectable by dap0n bit ? dap0n = 0: data output starts at the start of the operation of the serial clock. ? dap0n = 1: data output starts half a clock before the start of the serial clock operation. clock phase selectable by ckp0n bit ? ckp0n = 0: forward ? ckp0n = 1: reverse data direction msb or lsb first note use this operation within a range that satisfies the co nditions above and the ac characteristics in the electrical specifications (see chapter 27 electrical specifications ). chapter 11 serial array unit user?s manual u17854ej6v0ud 356 (1) register setting figure 11-38. example of contents of registers for master transmission/reception of 3-wire serial i/o (csi00, csi10) (a) serial output register 0 (so0) ? sets only the bits of the target channel. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 so0 0 0 0 0 1 cko02 0/1 1 cko00 0/1 0 0 0 0 1 so02 0/1 1 so00 0/1 communication starts when these bits are 1 if the data phase is forward (ckp0n = 0). if the phase is reversed (ckp0n = 1), communication starts when these bits are 0. (b) serial output enable register 0 (soe0) ? se ts only the bits of the target channel to 1. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 soe0 0 0 0 0 0 0 0 0 0 0 0 0 0 soe02 0/1 0 soe00 0/1 (c) serial channel start register 0 (ss0) ? sets only the bits of the target channel to 1. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ss0 0 0 0 0 0 0 0 0 0 0 0 0 ss03 ss02 0/1 ss01 ss00 0/1 (d) serial mode register 0n (smr0n) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 smr0n cks0n 0/1 ccs0n 0 0 0 0 0 0 sts0n 0 0 sis0n0 0 1 0 0 md0n2 0 md0n1 0 md0n0 0/1 operation mode of channel n 0: transfer end interrupt 1: buffer empty interrupt (e) serial communication operati on setting register 0n (scr0n) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 scr0n txe0n 1 rxe0n 1 dap0n 0/1 ckp0n 0/1 0 eoc0n 0 ptc0n1 0 ptc0n0 0 dir0n 0/1 0 slc0n1 0 slc0n0 0 0 dls0n2 1 dls0n1 1 dls0n0 0/1 (f) serial data register 0n (sdr0n) (lower 8 bits: siop) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sdr0n baud rate setting 0 transmit data setting/receive data register remark n: channel number (n = 0, 2), p: csi number (p = 00, 10) : setting is fixed in the csi mast er transmission/reception mode, : setting disabled (set to the initial value) : bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: set to 0 or 1 depending on the usage of the user siop chapter 11 serial array unit user?s manual u17854ej6v0ud 357 (2) operation procedure figure 11-39. initial setting proce dure for master transmission/reception caution after setting the per0 register to 1, be sure to set the sps0 register after 4 or more clocks have elapsed. figure 11-40. procedure for stoppi ng master transmission/reception remark even after communication is stopped, the pin level is retained. to resume the operation, re-set the so0 register (see figure 11-41 procedure for resumi ng master transmission/reception ). starting initial setting setting per0 register setting sps0 register setting smr0n register setting scr0n register setting sdr0n register setting so0 register changing setting of soe0 register setting port writing to ss0 register starting communication release the serial array unit from the reset status and start clock supply. set the prescaler. set an operation mode, etc. set a communication format. set a transfer baud rate. manipulate the so0n and cko0n bits and set an initial output level. set the soe0n bit to 1 and enable data output of the target channel. enable data output and clock output of the target channel by setting a port register and a port mode register. se0n = 1 when the ss0n bit of the target channel is set to 1. set transmit data to the siop register (bits 7 to 0 of the sdr0n register) and start communication. starting setting to stop setting st0 register stopping communication write 1 to the st0n bit of the target channel. stop communication in midway. chapter 11 serial array unit user?s manual u17854ej6v0ud 358 figure 11-41. procedure for resu ming master transmission/reception starting setting for resumption port manipulation changing setting of sps0 register changing setting of sdr0n register changing setting of smr0n register changing setting of so0 register port manipulation writing to ss0 register starting communication disable data output and clock output of the target channel by setting a port register and a port mode register. change the setting if an incorrect division ratio of the operation clock is set. change the setting if an incorrect transfer baud rate is set. change the setting if the setting of the smr0n register is incorrect. manipulate the so0n and cko0n bits and set an initial output level. enable data output and clock output of the target channel by setting a port register and a port mode register. se0n = 1 when the ss0n bit of the target channel is set to 1. sets transmit data to the siop register (bits 7 to 0 of the sdr0n register) and start communication. (essential) (selective) (selective) (selective) (selective) ( essential ) (essential) (essential) change the setting if the setting of the scr0n register is incorrect. (selective) changing setting of scr0n register cleared by using sir0 registe r if fef, pef, or ovf flag remains set. (selective) clearing error flag set the soe0 register and stop data output of the target channel. ( selective ) changing setting of soe0 register set the soe0 register and enable data output of the target channel. (selective) changing setting of soe0 register chapter 11 serial array unit user?s manual u17854ej6v0ud 359 (3) processing flow (in single -transmission/reception mode) figure 11-42. timing chart of master transmission/ reception (in single-trans mission/reception mode) ss0n se0n sdr0n sckp pin sip pin shift register 0n intcsip tsf0n receive data 3 receive data 2 receive data 1 transmit data 1 transmit data 2 transmit data 3 receive data 1 receive data 2 receive data 3 write read write read read write sop pin transmit data 3 transmit data 2 transmit data 1 reception & shift operation reception & shift operation reception & shift operation data transmission/reception (8-bit length) data transmission/reception (8-bit length) data transmission/reception (8-bit length) remark n: channel number (n = 0, 2), p: csi number (p = 00, 10) chapter 11 serial array unit user?s manual u17854ej6v0ud 360 figure 11-43. flowchart of master transmission/ reception (in single- tr ansmission/reception mode) starting csi communication writing 1 to ss0n bit writing transmit data to siop (=sdr0n[7:0]) writing 1 to st0n bit perform initial setting when se0n = 0. smr0n, scr0n: setting communication sdr0n[15:9]: setting transfer rate so0, soe0: setting output and sckp output transfer end interrupt generated? transmission/reception completed? no no yes yes setting sau1en and sau0en bits of per0 register to 1 setting transfer rate by sps0 register port manipulation clearing sau1en and sau0en bits of per0 register to 0 end of communication reading siop (=sdr0n[7:0]) register starting transmission/reception caution after setting the per0 register to 1, be sure to set the sps0 register after 4 or more clocks have elapsed. chapter 11 serial array unit user?s manual u17854ej6v0ud 361 (4) processing flow (in continu ous transmission/reception mode) figure 11-44. timing chart of master transmission/ reception (in continuous tr ansmission/reception mode) <4> <5> ss0n se0n sdr0n sckp pin sip pin shift register 0n intcsip tsf0n transmit data 1 transmit data 3 receive data 3 write read read read write sop pin bff0n <1> <2> <3> <2> <3> <4> <2> <7> <8> ( note 1 ) transmit data 2 write <6> <3> ( note 2 ) ( note 2 ) reception & shift operation md0n0 receive data 2 receive data 1 receive data 1 receive data 2 receive data 3 transmit data 3 transmit data 2 transmit data 1 reception & shift operation reception & shift operation data transmission/reception (8-bit length) data transmission/reception (8-bit length) data transmission/reception (8-bit length) notes 1. when transmit data is written to the sdr0n re gister while bff0n = 1, the transmit data is overwritten. 2. the transmit data can be read by reading the sdr0n register during this period. at this time, the transfer operation is not affected. caution the md0n0 bit can be re written even during operation. however, rewrite it before transfer of the last bit is started, so that it has been rewritten before the transfer end interrupt of the last transmit data. remarks 1. <1> to <8> in the figure correspond to <1> to <8> in figure 11-45 flowchart of master transmission/reception (in contin uous transmission/reception mode ). 2. n: channel number (n = 0, 2), p: csi number (p = 00, 10) chapter 11 serial array unit user?s manual u17854ej6v0ud 362 figure 11-45. flowchart of master transmission/ reception (in continuous tr ansmission/reception mode) starting csi communication writing 1 to ss0n bit reading receive data to siop (=sdr0n[7:0]) writing 1 to st0n bit perform initial setting when se0n = 0. <1> select the buffer empty interrupt. smr0n, scr0n: setting communication sdr0n[15:9]: setting transfer rate so0, soe0: setting output and sckp output y es y es n o n o setting sau1en and sau0en bits of per0 register to 1 setting transfer rate by sps0 register port manipulation end of communication clearing 0 to md0n0 bit n o transfer end interrupt generated? y es n o communication continued? y es y es clearing sau1en and sau0en bits of per0 register to 0 communication data exists? writing transmit data to siop (=sdr0n[7:0]) tsf0n = 1? reading receive data to siop (=sdr0n[7:0]) writing 1 to md0n0 bit buffer empty interrupt generated? <2> <3> <5> <6> <7> <4> <8> n o caution after setting the per0 register to 1, be sure to set the sps0 register after 4 or more clocks have elapsed. remark <1> to <8> in the figure correspond to <1> to <8> in figure 11-44 timing chart of master transmission/reception (in continuo us transmission/reception mode) . chapter 11 serial array unit user?s manual u17854ej6v0ud 363 11.5.4 slave transmission slave transmission is that the 78k0r/ ke3 transmits data to another device in the state of a transfer clock being input from another device. 3-wire serial i/o csi00 csi10 target channel channel 0 of sau0 channel 2 of sau0 pins used sck00, so00 sck10, so10 intcsi00 intcsi10 interrupt transfer end interrupt (in single-transfer mode) or buff er empty interrupt (in continuous transfer mode) can be selected. error detection flag overrun error detection flag (ovf0n) only transfer data length 7 or 8 bits transfer rate the smaller of f clk /6 [mhz] and f mck /2 [mhz] is the maximum transfer rate notes 1, 2 . data phase selectable by dap0n bit ? dap0n = 0: data output starts from the start of the operation of the serial clock. ? dap0n = 1: data output starts half a clock before the start of the serial clock operation. clock phase selectable by ckp0n bit ? ckp0n = 0: forward ? ckp0n = 1: reverse data direction msb or lsb first notes 1. because the external serial clock input to pins sck00, sck01, sck10, and sck20 is sampled internally and used, the fastest baud rate is the smaller of f clk /6 [mhz] and f mck /2 [mhz]. 2. use this operation within a range that satisfies the conditions above and the ac characteristics in the electrical specifications (see chapter 27 electrical specifications ). remark f mck : operation clock (mck) frequency of target channel f clk : system clock frequency chapter 11 serial array unit user?s manual u17854ej6v0ud 364 (1) register setting figure 11-46. example of contents of register s for slave transmission of 3-wire serial i/o (csi00, csi10) (a) serial output register 0 (so0) ? sets only the bits of the target channel. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 so0 0 0 0 0 1 cko02 1 cko00 0 0 0 0 1 so02 0/1 1 so00 0/1 (b) serial output enable register 0 (soe0) ? se ts only the bits of the target channel to 1. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 soe0 0 0 0 0 0 0 0 0 0 0 0 0 0 soe02 0/1 0 soe00 0/1 (c) serial channel start register 0 (ss0) ? sets only the bits of the target channel to 1. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ss0 0 0 0 0 0 0 0 0 0 0 0 0 ss03 ss02 0/1 ss01 ss00 0/1 (d) serial mode register 0n (smr0n) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 smr0n cks0n 0/1 ccs0n 1 0 0 0 0 0 sts0n 0 0 sis0n0 0 1 0 0 md0n2 0 md0n1 0 md0n0 0/1 operation mode of channel n 0: transfer end interrupt 1: buffer empty interrupt (e) serial communication operati on setting register 0n (scr0n) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 scr0n txe0n 1 rxe0n 0 dap0n 0/1 ckp0n 0/1 0 eoc0n 0 ptc0n1 0 ptc0n0 0 dir0n 0/1 0 slc0n1 0 slc0n0 0 0 dls0n2 1 dls0n1 1 dls0n0 0/1 (f) serial data register 0n (sdr0n) (lower 8 bits: siop) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sdr0n baud rate setting 0 transmit data setting remark n: channel number (n = 0, 2), p: csi number (p = 00, 10) : setting is fixed in the csi slave transmission mode , : setting disabled (set to the initial value) : bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: set to 0 or 1 depending on the usage of the user siop chapter 11 serial array unit user?s manual u17854ej6v0ud 365 (2) operation procedure figure 11-47. initial setting procedure for slave transmission caution after setting the per0 register to 1, be sure to set the sps0 register after 4 or more clocks have elapsed. starting initial setting setting per0 register setting sps0 register setting smr0n register setting scr0n register setting sdr0n register setting so0 register changing setting of soe0 register setting port writing to ss0 register starting communication release the serial array unit from the reset status and start clock supply. set the prescaler. set an operation mode, etc. set a communication format. set bits 15 to 9 to 0000000b for baud rate setting. manipulate the so0n bit and set an initial output level. set the soe0n bit to 1 and enable data output of the target channel. enable data output of the target channel by setting a port register and a port mode register. se0n = 1 when the ss0n bit of the target channel is set to 1. set transmit data to the siop register (bits 7 to 0 of the sdr0n register) and wait for a clock from the master. chapter 11 serial array unit user?s manual u17854ej6v0ud 366 figure 11-48. procedure for stopping slave transmission remark even after communication is stopped, the pin level is retained. to resume the operation, re-set the so0 register (see figure 11-49 procedure for resuming slave transmission ). starting setting to stop setting st0 register stopping communication write 1 to the st0n bit of the target channel. stop communication in midway. chapter 11 serial array unit user?s manual u17854ej6v0ud 367 figure 11-49. procedure for resuming slave transmission starting setting for resumption port manipulation changing setting of sps0 register changing setting of smr0n register changing setting of so0 register port manipulation writing to ss0 register disable data output of the target channel by setting a port register and a port mode register. change the setting if an incorrect division ratio of the operation clock is set. change the setting if the setting of the smr0n register is incorrect. manipulate the so0n and cko0n bits and set an initial output level. enable data output of the target channel by setting a port register and a port mode register. se0n = 1 when the ss0n bit of the target channel is set to 1. sets transmit data to the siop register (bits 7 to 0 of the sdr0n register) and wait for a clock from the master. (selective) (selective) (selective) (selective) (essential) (essential) (essential) change the setting if the setting of the scr0n register is incorrect. (selective) changing setting of scr0n register cleared by using sir0 registe r if fef, pef, or ovf flag remains set. (selective) clearing error flag set the soe0 register and enable data output of the target channel. (selective) changing setting of soe0 register stop the target fo r communication or wait until the target completes its operation. (essential) manipulating target for communication starting target for communication starts the target for communication. (essential) starting communication set the soe0 register and stop data output of the target channel. (selective) changing setting of soe0 register chapter 11 serial array unit user?s manual u17854ej6v0ud 368 (3) processing flow (in si ngle-transmission mode) figure 11-50. timing chart of slave tr ansmission (in single-transmission mode) ss0n se0n sdr0n sckp pin sop pin shift register 0n intcsip tsf0n data transmission (8-bit length) data transmission (8-bit length) data transmission (8-bit length) transmit data 3 transmit data 2 transmit data 1 transmit data 1 transmit data 2 transmit data 3 shift operation shift operation shift operation remark n: channel number (n = 0, 2), p: csi number (p = 00, 10) chapter 11 serial array unit user?s manual u17854ej6v0ud 369 figure 11-51. flowchart of slave tr ansmission (in single-transmission mode) caution after setting the per0 register to 1, be sure to set the sps0 register after 4 or more clocks have elapsed. starting csi communication writing 1 to ss0n bit writing transmit data to siop (=sdr0n[7:0]) writing 1 to st0n bit perform initial setting when se0n = 0. smr0n, scr0n: setting communication sdr0n[15:9]: setting transfer rate so0, soe0: setting output transfer end interrupt g enerated? transmission completed? no no yes yes setting sau1en and sau0en bits of per0 register to 1 setting transfer rate by sps0 register port manipulation clearing sau1en and sau0en bits of per0 register to 0 end of communication chapter 11 serial array unit user?s manual u17854ej6v0ud 370 (4) processing flow (in continuous transmission mode) figure 11-52. timing chart of slave transmission (in continuous transmission mode) ss0n se0n sdr0n sckp pin sop pin shift register 0n intcsip tsf0n data transmission (8-bit length) data transmission (8-bit length) transmit data 2 transmit data 1 transmit data 3 bff0n md0n0 transmit data 2 <1> <2> <2> <2> <3> <3> <3> <5> <4> ( note ) shift operation shift operation shift operation transmit data 3 data transmission (8-bit length) transmit data 1 note when transmit data is written to the sdr0n register while bff0n = 1, the transmit data is overwritten. caution the md0n0 bit can be rewritten even during ope ration. however, rewrite it before transfer of the last bit is started. chapter 11 serial array unit user?s manual u17854ej6v0ud 371 figure 11-53. flowchart of slave transmission (in continuous transmission mode) starting csi communication writing 1 to ss0n bit writing transmit data to siop (=sdr0n[7:0]) writing 1 to st0n bit perform initial setting when se0n = 0. <1> select the buffer empty interrupt. smr0n, scr0n: setting communication sdr0n[15:9]: setting transfer rate so0, soe0: setting output n o n o n o y es setting sau1en and sau0en bits of per0 register to 1 setting transfer rate by sps0 register port manipulation end of communication clearing 0 to md0n0 bit y es n o y es n o communication continued? y es y es clearing sau1en and sau0en bits of per0 register to 0 <2> <3> <4> <5> transmitting next data? buffer empty interrupt generated? buffer empty interrupt generated? tsf0n = 1? writing 1 to md0n0 bit caution after setting the per0 register to 1, be sure to set the sps0 register after 4 or more clocks have elapsed. remark <1> to <5> in the figure correspond to <1> to <5> in figure 11-52 timing chart of slave transmission (in continuous transmission mode) . chapter 11 serial array unit user?s manual u17854ej6v0ud 372 11.5.5 slave reception slave reception is that the 78k0r/ke3 receives data from another device in t he state of a transfer clock being input from another device. 3-wire serial i/o csi00 csi10 target channel channel 0 of sau0 channel 2 of sau0 pins used sck00, si00 sck10, si10 intcsi00 intcsi10 interrupt transfer end interrupt only (setting the buffer empty interrupt is prohibited.) error detection flag overrun error detection flag (ovf0n) only transfer data length 7 or 8 bits transfer rate the smaller of f clk /6 [mhz] and f mck /2 [mhz] is the maximum transfer rate notes 1, 2 . data phase selectable by dap0n bit ? dap0n = 0: data input starts from the start of the operation of the serial clock. ? dap0n = 1: data input starts half a clock be fore the start of the serial clock operation. clock phase selectable by ckp0n bit ? ckp0n = 0: forward ? ckp0n = 1: reverse data direction msb or lsb first notes 1. because the external serial clock input to pins sck00, sck01, sck10, and sck20 is sampled internally and used, the fastest baud rate is the smaller of f clk /6 [mhz] and f mck /2 [mhz]. 2. use this operation within a range t hat satisfies the conditions above and the ac characteristics in the electrical specifications (see chapter 27 electrical specifications ). remark f mck : operation clock (mck) frequency of target channel f clk : system clock frequency chapter 11 serial array unit user?s manual u17854ej6v0ud 373 (1) register setting figure 11-54. example of contents of regist ers for slave reception of 3-wire serial i/o (csi00, csi10) (a) serial output register 0 (so0) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 so0 0 0 0 0 1 cko02 1 cko00 0 0 0 0 1 so02 1 so00 (b) serial output enable register 0 (soe0) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 soe0 0 0 0 0 0 0 0 0 0 0 0 0 0 soe02 0/1 0 soe00 0/1 set these bits to 0 when using them for csi slave reception (c) serial channel start register 0 (ss0) ? sets only the bits of the target channel to 1. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ss0 0 0 0 0 0 0 0 0 0 0 0 0 ss03 ss02 0/1 ss01 ss00 0/1 (d) serial mode register 0n (smr0n) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 smr0n cks0n 0/1 ccs0n 1 0 0 0 0 0 sts0n 0 0 sis0n0 0 1 0 0 md0n2 0 md0n1 0 md0n0 0 operation mode of channel n 0: transfer end interrupt (e) serial communication operati on setting register 0n (scr0n) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 scr0n txe0n 0 rxe0n 1 dap0n 0/1 ckp0n 0/1 0 eoc0n 0 ptc0n1 0 ptc0n0 0 dir0n 0/1 0 slc0n1 0 slc0n0 0 0 dls0n2 1 dls0n1 1 dls0n0 0/1 (f) serial data register 0n (sdr0n) (lower 8 bits: siop) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sdr0n 0000000 (baud rate setting) 0 receive data register remark n: channel number (n = 0, 2), p: csi number (p = 00, 10) : setting is fixed in the csi slave reception mode, : setting disabled (set to the initial value) : bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: set to 0 or 1 depending on the usage of the user siop chapter 11 serial array unit user?s manual u17854ej6v0ud 374 (2) operation procedure figure 11-55. initial setting procedure for slave reception caution after setting the per0 register to 1, be sure to set the sps0 register after 4 or more clocks have elapsed. figure 11-56. procedure for stopping slave reception starting initial settings setting per0 register setting sps0 register setting smr0n register setting scr0n register setting sdr0n register setting port writing to ss0 register starting communication release the serial array unit from the reset status and start clock supply. set the prescaler. set an operation mode, etc. set a communication format. set bits 15 to 9 to 0000000b for baud rate setting. enable data input and clock input of the target channel by setting a port register and a port mode register. se0n = 1 when the ss0n bit of the target channel is set to 1. wait for a clock from the master. starting setting to stop setting st0 register stopping communication write 1 to the st0n bit of the target channel. stop communication in midway. chapter 11 serial array unit user?s manual u17854ej6v0ud 375 figure 11-57. procedure for resuming slave reception starting setting for resumption port manipulation changing setting of sps0 register changing setting of smr0n register changing setting of so0 register port manipulation writing to ss0 register starting communication disable clock output of the target channel by setting a port register and a port mode register. change the setting if an incorrect division ratio of the operation clock is set. change the setting if the setting of the smr0n register is incorrect. manipulate the cko0n bit and enable reception. enable clock output of the target channel by setting a port register and a port mode register. se0n = 1 when the ss0n bit of the target channel is set to 1. wait for a clock from the master. (essential) (selective) (selective) (selective) (essential) (essential) (essential) change the setting if the setting of the scr0n register is incorrect. (selective) changing setting of scr0n register cleared by using sir0 register if fef, pef, or ovf flag remains set. (selective) clearing error flag clear the soe0 register to 0 and stop data output of the target channel. (essential) changing setting of soe0 register manipulating target for communication stop the target for communication or wait until the target completes its operation. change the setting if the setting of the sdr0n register is incorrect. (selective) changing setting of sdr0n register (essential) chapter 11 serial array unit user?s manual u17854ej6v0ud 376 (3) processing flow (in single-reception mode) figure 11-58. timing chart of slave reception (in sing le-reception mode) ss0n se0n sdr0n sckp pin sip pin shift register 0n intcsip tsf0n data reception (8-bit length) data reception (8-bit length) data reception (8-bit length) receive data 3 receive data 2 receive data 1 receive data 1 receive data 2 receive data 3 read read read reception & shift operation reception & shift operation reception & shift operation remark n: channel number (n = 0, 2), p: csi number (p = 00, 10) chapter 11 serial array unit user?s manual u17854ej6v0ud 377 figure 11-59. flowchart of slave reception (in singl e-reception mode) starting csi communication writing 1 to ss0n bit writing 1 to st0n bit perform initial setting when se0n = 0. smr0n, scr0n: setting communication sdr0n[15:9]: setting transfer rate so0, soe0: setting sckp output transfer end interrupt generated? reception completed? no no yes yes setting sau1en and sau0en bits of per0 register to 1 setting transfer rate by sps0 register port manipulation clearing sau1en and sau0en bits of per0 register to 0 end of communication reading siop (=sdr0n[7:0]) register starting reception caution after setting the per0 register to 1, be sure to set the sps0 register after 4 or more clocks have elapsed. chapter 11 serial array unit user?s manual u17854ej6v0ud 378 11.5.6 slave transmission/reception slave transmission/reception is that t he 78k0r/ke3 transmits/receives data to/fr om another device in the state of a transfer clock being input from another device. 3-wire serial i/o csi00 csi10 target channel channel 0 of sau0 channel 2 of sau0 pins used sck00, si00, so00 sck10, si10, so10 intcsi00 intcsi10 interrupt transfer end interrupt (in single-transfer mode) or buff er empty interrupt (in continuous transfer mode) can be selected. error detection flag overrun error detection flag (ovf0n) only transfer data length 7 or 8 bits transfer rate the smaller of f clk /6 [mhz] and f mck /2 [mhz] is the maximum transfer rate notes 1, 2 . data phase selectable by dap0n bit ? dap0n = 0: data output starts from the start of the operation of the serial clock. ? dap0n = 1: data output starts half a clock before the start of the serial clock operation. clock phase selectable by ckp0n bit ? ckp0n = 0: forward ? ckp0n = 1: reverse data direction msb or lsb first notes 1. because the external serial clock input to pins sck00, sck01, sck10, and sck20 is sampled internally and used, the fastest baud rate is the smaller of f clk /6 [mhz] and f mck /2 [mhz]. 2. use this operation within a range t hat satisfies the conditions above and the ac characteristics in the electrical specifications (see chapter 27 electrical specifications ). remark f mck : operation clock (mck) frequency of target channel f clk : system clock frequency chapter 11 serial array unit user?s manual u17854ej6v0ud 379 (1) register setting figure 11-60. example of contents of registers fo r slave transmission/recepti on of 3-wire serial i/o (csi00, csi10) (a) serial output register 0 (so0) ? sets only the bits of the target channel. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 so0 0 0 0 0 1 cko02 1 cko00 0 0 0 0 1 so02 0/1 1 so00 0/1 (b) serial output enable register 0 (soe0) ? se ts only the bits of the target channel to 1. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 soe0 0 0 0 0 0 0 0 0 0 0 0 0 0 soe02 0/1 0 soe00 0/1 (c) serial channel start register 0 (ss0) ? sets only the bits of the target channel to 1. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ss0 0 0 0 0 0 0 0 0 0 0 0 0 ss03 ss02 0/1 ss01 ss00 0/1 (d) serial mode register 0n (smr0n) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 smr0n cks0n 0/1 ccs0n 1 0 0 0 0 0 sts0n 0 0 sis0n0 0 1 0 0 md0n2 0 md0n1 0 md0n0 0/1 operation mode of channel n 0: transfer end interrupt 1: buffer empty interrupt (e) serial communication operati on setting register 0n (scr0n) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 scr0n txe0n 1 rxe0n 1 dap0n 0/1 ckp0n 0/1 0 eoc0n 0 ptc0n1 0 ptc0n0 0 dir0n 0/1 0 slc0n1 0 slc0n0 0 0 dls0n2 1 dls0n1 1 dls0n0 0/1 (f) serial data register 0n (sdr0n) (lower 8 bits: siop) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sdr0n 0000000 (baud rate setting) 0 transmit data setting/receive data register remark n: channel number (n = 0, 2), p: csi number (p = 00, 10) : setting is fixed in the csi slave transmission/receptio n mode, : setting disabled (set to the initial value) : bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: set to 0 or 1 depending on the usage of the user siop chapter 11 serial array unit user?s manual u17854ej6v0ud 380 (2) operation procedure figure 11-61. initial setting pro cedure for slave transmission/reception cautions after setting the per0 register to 1, be sure to set the sps0 register after 4 or more clocks have elapsed. starting initial setting setting per0 register setting sps0 register setting smr0n register setting scr0n register setting sdr0n register setting so0 register changing setting of soe0 register setting port writing to ss0 register starting communication release the serial array unit from the reset status and start clock supply. set the prescaler. set an operation mode, etc. set a communication format. set bits 15 to 9 to 0000000b for baud rate setting. manipulate the so0n bit and set an initial output level. set the soe0n bit to 1 and enable data output of the target channel. enable data output of the target channel by setting a port register and a port mode register. se0n = 1 when the ss0n bit of the target channel is set to 1. set transmit data to the siop register (bits 7 to 0 of the sdr0n register) and wait for a clock from the master. chapter 11 serial array unit user?s manual u17854ej6v0ud 381 figure 11-62. procedure for stopping slave transmission/reception remark even after communication is stopped, the pin level is retained. to resume the operation, re-set the so0 register (see figure 11-63 procedure for resu ming slave transmission/reception ). starting setting to stop setting st0 register stopping communication write 1 to the st0n bit of the target channel. stop communication in midway. chapter 11 serial array unit user?s manual u17854ej6v0ud 382 figure 11-63. procedure for resu ming slave transmission/reception starting setting for resumption manipulating target for communication port manipulation changing setting of sps0 register changing setting of smr0n register changing setting of so0 register port manipulation writing to ss0 register stop the target fo r communication or wait until the target completes its operation. disable data output of the target channel by setting a port register and a port mode register. change the setting if an incorrect division ratio of the operation clock is set. change the setting if the setting of the smr0n register is incorrect. manipulate the so0n and cko0n bits and set an initial output level. enable data output and clock output of the target channel by setting a port register and a port mode register. se0n = 1 when the ss0n bit of the target channel is set to 1. (essential) (essential) ( selective ) (selective) (selective) (essential) (essential) clearing error flag (selective) cleared by using sir0 registe r if fef, pef, or ovf flag remains set. starting communication starting target for communication sets transmit data to the siop register (bits 7 to 0 of the sdr0n register) and wait for a clock from the master. starts the target for communication. (essential) (essential) changing setting of sdr0 register change the setting if an incorrect division ratio of the operation clock is set. ( selective ) changing setting of scr0n register change the setting if the setting of the scr0n register is incorrect. (selective) changing setting of soe0 register set the soe0 register and stop data output of the target channel. (selective) changing setting of soe0 register set the soe0 register and enable data output of the target channel. (selective) chapter 11 serial array unit user?s manual u17854ej6v0ud 383 (3) processing flow (in single -transmission/reception mode) figure 11-64. timing chart of slave transmission/ reception (in single-tra nsmission/reception mode) ss0n se0n sdr0n sckp pin sip pin shift register 0n intcsip tsf0n receive data 3 receive data 2 receive data 1 transmit data 1 transmit data 2 transmit data 3 receive data 2 receive data 3 write read write read read write sop pin transmit data 3 transmit data 2 transmit data 1 reception & shift operation reception & shift operation reception & shift operation receive data 1 data transmission/reception (8-bit length) data transmission/reception (8-bit length) data transmission/reception (8-bit length) remark n: channel number (n = 0, 2), p: csi number (p = 00, 10) chapter 11 serial array unit user?s manual u17854ej6v0ud 384 figure 11-65. flowchart of slave transmission/ reception (in single- tran smission/reception mode) starting csi communication writing 1 to ss0n bit writing transmit data to siop (=sdr0n[7:0]) writing 1 to st0n bit perform initial setting when se0n = 0. smr0n, scr0n: setting communication sdr0n[15:9] : setting transfer rate so0, soe0 : setting output transfer end interrupt generated? transmission/reception completed? no no yes yes setting sau1en and sau0en bits of per0 register to 1 setting transfer rate by sps0 register port manipulation clearing sau1en and sau0en bits of per0 register to 0 end of communication reading siop (=sdr0n[7:0]) register starting transmission/reception caution after setting the per0 register to 1, be sure to set the sps0 register after 4 or more clocks have elapsed. chapter 11 serial array unit user?s manual u17854ej6v0ud 385 (4) processing flow (in continu ous transmission/reception mode) figure 11-66. timing chart of slave transmission/ reception (in continuous tr ansmission/reception mode) <4> <5> ss0n se0n sdr0n sckp pin sip pin shift register 0n intcsip tsf0n transmit data 1 transmit data 3 receive data 3 write read read read write sop pin bff0n <1> <2> <3> <2> <3> <4> <2> <7> <8> ( note 1 ) transmit data 2 write <6> <3> ( note 2 ) ( note 2 ) reception & shift operation md0n0 receive data 2 receive data 1 receive data 1 receive data 2 receive data 3 transmit data 3 transmit data 2 transmit data 1 reception & shift operation reception & shift operation data transmission/reception (8-bit length) data transmission/reception (8-bit length) data transmission/reception (8-bit length) notes 1. when transmit data is written to the sdr0n re gister while bff0n = 1, the transmit data is overwritten. 2. the transmit data can be read by reading the sdr0n register during this period. at this time, the transfer operation is not affected. caution the md0n0 bit can be re written even during operation. however, rewrite it before transfer of the last bi t is started, so that it will be rewritten before the transfer end interrupt of the last transmit data. remarks 1. <1> to <8> in the figure correspond to <1> to <8> in figure 11-67 flowchart of slave transmission/reception (in contin uous transmission/reception mode ). 2. n: channel number (n = 0, 2), p: csi number (p = 00, 10) chapter 11 serial array unit user?s manual u17854ej6v0ud 386 figure 11-67. flowchart of slave transmission/r eception (in continuous tran smission/reception mode) starting csi communication writing 1 to ss0n bit reading receive data to siop (=sdr0n[7:0]) writing 1 to st0n bit perform initial setting when se0n = 0. <1> select the buffer empty interrupt. smr0n, scr0n: setting communication sdr0n[15:9]: setting transfer rate so0, soe0: setting output y es y es n o n o setting sau1en and sau0en bits of per0 register to 1 setting transfer rate by sps0 register port manipulation end of communication clearing 0 to md0n0 bit n o transfer end interrupt generated? y es n o communication continued? y es y es clearing sau1en and sau0en bits of per0 register to 0 communication data exists? writing transmit data to siop (=sdr0n[7:0]) tsf0n = 1? reading receive data to siop (=sdr0n[7:0]) writing 1 to md0n0 bit buffer empty interrupt generated? <2> <3> <5> <6> <7> <4> <8> n o cautions after setting the per0 register to 1, be sure to set the sps0 register after 4 or more clocks have elapsed. remark <1> to <8> in the figure correspond to <1> to <8> in figure 11-66 timing chart of slave transmission/reception (in continuo us transmission/reception mode) . chapter 11 serial array unit user?s manual u17854ej6v0ud 387 11.5.7 calculating transfer clock frequency the transfer clock frequency fo r 3-wire serial i/o (csi00, cs i10) communication can be ca lculated by the following expressions. (1) master (transfer clock frequency) = {operation clock (mck) frequency of target channel} (sdr0n[15:9] + 1) 2 [hz] (2) slave (transfer clock frequency) = {frequency of serial clock (sck) supplied by master} note [hz] note the permissible maximum frequency is the smaller of f clk /6 [mhz] and f mck /2 [mhz]. remarks 1. the value of sdr0n[15:9] is t he value of bits 15 to 9 of t he sdr0n register (0000000b to 1111111b) and therefore is 0 to 127. 2. n: channel number (n = 0, 2) the operation clock (mck) is determined by serial clock select register 0 (sps0) and bit 15 (cks0n) of serial mode register 0n (smr0n). chapter 11 serial array unit user?s manual u17854ej6v0ud 388 table 11-2 operating clock selection smr0n register sps0 register operation clock (mck) note 1 cks0n prs 013 prs 012 prs 011 prs 010 prs 003 prs 002 prs 001 prs 000 f clk = 20 mhz x x x x 0 0 0 0 f clk 20 mhz x x x x 0 0 0 1 f clk /2 10 mhz x x x x 0 0 1 0 f clk /2 2 5 mhz x x x x 0 0 1 1 f clk /2 3 2.5 mhz x x x x 0 1 0 0 f clk /2 4 1.25 mhz x x x x 0 1 0 1 f clk /2 5 625 khz x x x x 0 1 1 0 f clk /2 6 313 khz x x x x 0 1 1 1 f clk /2 7 156 khz x x x x 1 0 0 0 f clk /2 8 78.1 khz x x x x 1 0 0 1 f clk /2 9 39.1 khz x x x x 1 0 1 0 f clk /2 10 19.5 khz x x x x 1 0 1 1 f clk /2 11 9.77 khz 0 x x x x 1 1 1 1 inttm02 note 2 0 0 0 0 x x x x f clk 20 mhz 0 0 0 1 x x x x f clk /2 10 mhz 0 0 1 0 x x x x f clk /2 2 5 mhz 0 0 1 1 x x x x f clk /2 3 2.5 mhz 0 1 0 0 x x x x f clk /2 4 1.25 mhz 0 1 0 1 x x x x f clk /2 5 625 khz 0 1 1 0 x x x x f clk /2 6 313 khz 0 1 1 1 x x x x f clk /2 7 156 khz 1 0 0 0 x x x x f clk /2 8 78.1 khz 1 0 0 1 x x x x f clk /2 9 39.1 khz 1 0 1 0 x x x x f clk /2 10 19.5 khz 1 0 1 1 x x x x f clk /2 11 9.77 khz 1 1 1 1 1 x x x x inttm02 note 2 other than above setting prohibited notes 1. when changing the clock selected for f clk (by changing the system clock control register (ckc) value), do so after having stopped (st0 = 000fh) the operation of the serial array unit (sau). when selecting inttm02 for the operation clock, also stop the timer array unit (tau) (tt0 = 00ffh). 2. sau can be operated at a fixed division ratio of the subsystem clock, regardless of the f clk frequency (main system clock, subsystem cloc k), by setting the tis02 bit of the tis0 register of tau to 1, selecting f sub /4 for the input clock, and selecting inttm02 using the sps0 register. when changing f clk , however, sau and tau must be stopped as described in note 1 above. remarks 1. x: don?t care 2. n: channel number (n = 0, 2) chapter 11 serial array unit user?s manual u17854ej6v0ud 389 11.6 operation of uart (uart0, uart1, uart3) communication this is a start-stop synchronization function using two lines: serial data transmission (txd) and serial data reception (rxd) lines. it transmits or receives data in asyn chronization with the party of communication (by using an internal baud rate). full-duplex uart communication can be realized by using two channels, one dedicated to transmission (even channel) and the other to reception (odd channel). [data transmission/reception] ? data length of 5, 7, or 8 bits ? select the msb/lsb first ? level setting of transmit/recei ve data and select of reverse ? parity bit appending and parity check functions ? stop bit appending [interrupt function] ? transfer end interrupt/buffer empty interrupt ? error interrupt in case of framing error, parity error, or overrun error [error detection flag] ? framing error, parity error, or overrun error the lin-bus is supported in uart3 (2, 3 channels of unit 1) [lin-bus functions] ? wakeup signal detection ? sync break field (sbf) detection ? sync field measurement, baud rate calculation uart0 uses channels 0 and 1 of sau0. uart1 uses channels 2 and 3 of sau0. uart3 uses channels 2 and 3 of sau1. unit channel used as csi used as uart used as simplified i 2 c 0 csi00 uart0 ? 1 ? ? 2 csi10 uart1 iic10 0 3 ? ? 0 ? ? ? 1 ? ? ? 2 ? uart3 (supporting lin-bus) ? 1 3 ? ? uart performs the following four types of communication operations. ? uart transmission (see 11.6.1 .) ? uart reception (see 11.6.2 .) ? lin transmission (uart3 only) (see 11.6.3 .) ? lin reception (uart3 only) (see 11.6.4 .) external interrupt (intp0) or timer array unit (tau) is used. chapter 11 serial array unit user?s manual u17854ej6v0ud 390 11.6.1 uart transmission uart transmission is an operation to transmit data from the 78k0r/ke3 to another device asynchronously (start- stop synchronization). of two channels used for uart, the even channel is used for uart transmission. uart uart0 uart1 uart3 target channel channel 0 of sau0 channel 2 of sau0 channel 2 of sau1 pins used txd0 txd1 txd3 intst0 intst1 intst3 interrupt transfer end interrupt (in single-transfer mode) or buff er empty interrupt (in continuous transfer mode) can be selected. error detection flag none transfer data length 5, 7, or 8 bits transfer rate max. f mck /6 [bps] (sdrmn [15:9] = 2 or more), min. f clk /(2 2 11 128) [bps] note data phase forward output (default: high level) reverse output (default: low level) parity bit the following selectable ? no parity bit ? appending 0 parity ? appending even parity ? appending odd parity stop bit the following selectable ? appending 1 bit ? appending 2 bits data direction msb or lsb first note use this operation within a range that satisfies the co nditions above and the ac characteristics in the electrical specifications (see chapter 27 electrical specifications ). remark f mck : operation clock (mck) frequency of target channel f clk : system clock frequency chapter 11 serial array unit user?s manual u17854ej6v0ud 391 (1) register setting figure 11-68. example of contents of re gisters for uart transmission of uart (uart0, uart1, uart3) (1/2) (a) serial output register m (som) ? sets onl y the bit of the target channel to 1. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 so0 0 0 0 0 1 cko02 1 cko00 0 0 0 0 1 so02 0/1 note 1 so00 0/1 note 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 so1 0 0 0 0 1 1 1 1 0 0 0 0 1 so12 0/1 note 1 1 (b) serial output enable register m (soem) ? se ts only the bit of the target channel to 1. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 soe0 0 0 0 0 0 0 0 0 0 0 0 0 0 soe02 0/1 0 soe00 0/1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 soe1 0 0 0 0 0 0 0 0 0 0 0 0 0 soe12 0/1 0 0 (c) serial channel start register m (ssm) ? sets only the bits of the target channel to 1. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ss0 0 0 0 0 0 0 0 0 0 0 0 0 ss03 ss02 0/1 ss01 ss00 0/1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ss1 0 0 0 0 0 0 0 0 0 0 0 0 ss13 ss12 0/1 0 0 note before transmission is started, be sure to set to 1 when the solmn bit of the target channel is set to 0, and set to 0 when the solmn bit of the target channel is set to 1. the value varies depending on the communication data during communication operation. remark m: unit number (m = 0, 1), n: channel number (n = 0, 2), mn = 00, 02, 12 : setting disabled (set to the initial value) : bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: set to 0 or 1 depending on the usage of the user chapter 11 serial array unit user?s manual u17854ej6v0ud 392 figure 11-68. example of contents of re gisters for uart transmission of uart (uart0, uart1, uart3) (2/2) (d) serial output level register m (solm) ? sets only the bits of the target channel. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sol0 0 0 0 0 0 0 0 0 0 0 0 0 0 sol02 0/1 0 sol00 0/1 0: forward (normal) transmission 1: reverse transmission 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sol1 0 0 0 0 0 0 0 0 0 0 0 0 0 sol12 0/1 0 0 0: forward (normal) transmission 1: reverse transmission (e) serial mode register mn (smrmn) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 smrmn cksmn 0/1 ccsmn 0 0 0 0 0 0 stsmn 0 0 sismn0 0 1 0 0 mdmn2 0 mdmn1 1 mdmn0 0/1 operation mode of channel n 0: transfer end interrupt 1: buffer empty interrupt (f) serial communication operation setting register mn (scrmn) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 scrmn txemn 1 rxemn 0 dapmn 0 ckpmn 0 0 eocmn 0 ptcmn1 0/1 ptcmn0 0/1 dirmn 0/1 0 slcmn1 0/1 slcmn0 0/1 0 dlsmn2 1 dlsmn1 0/1 dlsmn0 0/1 setting of stop bit 01b: appending 1 bit 10b: appending 2 bits setting of parity bit 00b: no parity 01b: 0 parity 10b: even parity 11b: odd parity (g) serial data register mn (sdrmn) (lower 8 bits: txdq) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sdrmn baud rate setting 0 transmit data setting remark m: unit number (m = 0, 1), n: channel number (n = 0, 2), mn = 00, 02, 12, q: uart number (q = 0, 1, 3) : setting is fixed in the uart transmission mode, : setting disabled (set to the initial value) 0/1: set to 0 or 1 depending on the usage of the user txdq chapter 11 serial array unit user?s manual u17854ej6v0ud 393 (2) operation procedure figure 11-69. initial setting procedure for uart transmission caution after setting the per0 register to 1, be sure to set the spsm register after 4 or more clocks have elapsed. starting initial setting setting perm register setting spsm register setting smrmn register setting scrmn register setting sdrmn register setting som register setting port changing setting of soem register writing to ssm register starting communication release the serial array unit from the reset status and start clock supply. set the prescaler. set an operation mode, etc. set a communication format. set a transfer baud rate. manipulate the somn bit and set an initial output level. enable data output of the target channel by setting a port register and a port mode register. set the soemn bit to 1 and enable data output of the target channel. semn = 1 when the ssmn bit of the target channel is set to 1. set transmit data to the txdq register (bits 7 to 0 of the sdrmn register) and start communication. changing setting of solm register set an output data level. chapter 11 serial array unit user?s manual u17854ej6v0ud 394 figure 11-70. procedure for stopping uart transmission remark even after communication is stopped, the pin level is retained. to resume the operation, re-set the som register (see figure 11-71 procedure for resuming uart transmission ). starting setting to stop setting stm register stopping communication write 1 to the stmn bit of the target channel. stop communication in midway. chapter 11 serial array unit user?s manual u17854ej6v0ud 395 figure 11-71. procedure for resuming uart transmission port manipulation changing setting of spsm register changing setting of sdrm register changing setting of smrmn register changing setting of som register port manipulation writing to ssm register starting communication disable data output of the target channel by setting a port register and a port mode register. change the setting if an incorrect division ratio of the operation clock is set. change the setting if an incorrect transfer baud rate is set. change the setting if the setting of the smrmn register is incorrect. manipulate the somn bit and set an initial output level. enable data output of the target channel by setting a port register and a port mode register. semn = 1 when the ssmn bit of the target channel is set to 1. sets transmit data to the txdq register (bits 7 to 0 of the sdrmn register) and start communication. (essential) (selective) (essential) changing setting of soem register set the soemn bit to 1 and enable output. changing setting of soem register clear the soemn bit to 0 and stop output. (essential) changing setting of scrmn register change the setting if the setting of the scrmn register is incorrect. changing setting of solmn register change the setting if the setting of the solmn register is incorrect. starting setting for resumption (essential) (essential) (essential) (essential) (selective) (selective) (selective) (selective) chapter 11 serial array unit user?s manual u17854ej6v0ud 396 (3) processing flow (in si ngle-transmission mode) figure 11-72. timing chart of uart tr ansmission (in single-transmission mode) ssmn semn sdrmn txdq pin shift register mn intstq tsfmn data transmission (7-bit length) data transmission (7-bit length) data transmission (7-bit length) p transmit data 1 transmit data 2 transmit data 3 transmit data 3 transmit data 2 transmit data 1 shift operation shift operation shift operation sp st st p sp st p sp remark m: unit number (m = 0, 1), n: channel number (n = 0, 2), mn = 00, 02, 12, q: uart number (q = 0, 1, 3) chapter 11 serial array unit user?s manual u17854ej6v0ud 397 figure 11-73. flowchart of uart tr ansmission (in single-transmission mode) caution after setting the per0 register to 1, be sure to set the spsm register after 4 or more clocks have elapsed. starting uart communication writing 1 to ssmn bit writing transmit data to txdq (=sdrmn[7:0]) writing 1 to stmn bit perform initial setting when semn = 0. smrmn, scrmn: setting communication sdrmn[15:9]: setting transfer rate solmn: setting output data level som, soem: setting output transfer end interrupt g enerated? transmission completed? no no yes yes setting sau1en and sau0en bits of per0 register to 1 setting transfer rate by spsm register port manipulation end of communication clearing sau1en and sau0en bits of per0 register to 0 chapter 11 serial array unit user?s manual u17854ej6v0ud 398 (4) processing flow (in continuous transmission mode) figure 11-74. timing chart of uart transmission (in continuous transmission mode) ssmn semn sdrmn t x dq pin shift register mn intstq tsfmn data transmission (7-bit length) data transmission (7-bit length) p transmit data 1 transmit data 2 transmit data 3 transmit data 3 transmit data 2 transmit data 1 shift operation shift operation shift operation sp st st p sp st p sp bffmn <1> <2> <2> <3> ( note ) <2> <3> <5> <3> <4> mdmn0 data transmission (7-bit length) note when transmit data is written to the sdrmn register while bffmn = 1, the transmit data is overwritten. caution the mdmn0 bit can be rewr itten even during operation. however, rewrite it before transfer of the last bit is started, so that it has been rewritten before the transfer end interrupt of the last transmit data. remark m: unit number (m = 0, 1), n: channel number (n = 0, 2), mn = 00, 02, 12, q: uart number (q = 0, 1, 3) chapter 11 serial array unit user?s manual u17854ej6v0ud 399 figure 11-75. flowchart of uart transmission (in continuous transmission mode) starting uart communication writing 1 to ssmn bit writing transmit data to txdq (=sdrmn[7:0]) writing 1 to stmn bit perform initial setting when semn = 0. <1> select the buffer empty interrupt. smrmn, scrmn: setting communication sdrmn[15:9]: setting transfer rate solmn: setting output data level som, soem: setting output n o n o n o y es setting sau1en and sau0en bits of per0 register to 1 setting transfer rate by spsm register port manipulation end of communication clearing 0 to mdmn0 bit y es tsfmn = 1? transfer end interrupt g enerated? n o y es n o communication continued? y es y es clearing sau1en and sau0en bits of per0 register to 0 transmitting next data? <2> <3> buffer empty interrupt generated? writing 1 to mdmn0 bit <4> <5> caution after setting the per0 register to 1, be sure to set the spsm register after 4 or more clocks have elapsed. remark <1> to <5> in the figure correspond to <1> to <5> in figure 11-74 timing chart of uart transmission (in continuous transmission mode) . chapter 11 serial array unit user?s manual u17854ej6v0ud 400 11.6.2 uart reception uart reception is an operation wherei n the 78k0r/ke3 asynchronously receives data from another device (start- stop synchronization). for uart reception, the odd channel of the two channels used for uart is used. uart uart0 uart1 uart3 target channel channel 1 of sau0 channel 3 of sau0 channel 3 of sau1 pins used rxd0 rxd1 rxd3 intsr0 intsr1 intsr3 interrupt transfer end interrupt only (setting the buffer empty interrupt is prohibited.) error interrupt intsre0 intsre1 intsre3 error detection flag ? framing error detection flag (fefmn) ? parity error detection flag (pefmn) ? overrun error detection flag (ovfmn) transfer data length 5, 7 or 8 bits transfer rate max. f mck /6 [bps] (sdrmn [15:9] = 2 or more), min. f clk /(2 2 11 128) [bps] note data phase forward output (default: high level) reverse output (default: low level) parity bit the following selectable ? no parity bit (no parity check) ? appending 0 parity (no parity check) ? appending even parity ? appending odd parity stop bit appending 1 bit data direction msb or lsb first note use this operation within a range that satisfies the co nditions above and the ac characteristics in the electrical specifications (see chapter 27 electrical specifications ). remark f mck : operation clock (mck) frequency of target channel f clk : system clock frequency chapter 11 serial array unit user?s manual u17854ej6v0ud 401 (1) register setting figure 11-76. example of contents of registers for uart reception of uart (uart0, uart1, uart3) (1/2) (a) serial output register m (som) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 so0 0 0 0 0 1 cko02 1 cko00 0 0 0 0 1 so02 1 so00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 so1 0 0 0 0 1 1 1 1 0 0 0 0 1 so12 1 1 (b) serial output enable register m (soem) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 soe0 0 0 0 0 0 0 0 0 0 0 0 0 0 soe02 0 soe00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 soe1 0 0 0 0 0 0 0 0 0 0 0 0 0 soe12 0 0 (c) serial channel start register m (ssm) ? sets only the bits of the target channel is 1. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ss0 0 0 0 0 0 0 0 0 0 0 0 0 ss03 0/1 ss02 ss01 0/1 ss00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ss1 0 0 0 0 0 0 0 0 0 0 0 0 ss13 0/1 ss12 0 0 (d) serial mode register mn (smrmn) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 smrmn cksmn 0/1 ccsmn 0 0 0 0 0 0 stsmn 1 0 sismn0 0/1 1 0 0 mdmn2 0 mdmn1 1 mdmn0 0 0: forward (normal) reception 1: reverse reception operation mode of channel n 0: transfer end interrupt caution for the uart reception, be sure to set smr mr of channel r that is to be paired with channel n. remark m: unit number (m = 0, 1), n: channel number (n = 1, 3), mn = 01, 03, 13 r: channel number (r = n ? 1), : setting is fixed in the uart reception mode, : setting disabled (set to the initial value) : bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: set to 0 or 1 depending on the usage of the user chapter 11 serial array unit user?s manual u17854ej6v0ud 402 figure 11-76. example of contents of registers for uart reception of uart (uart0, uart1, uart3) (2/2) (e) serial mode register mr (smrmr) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 smrmr cksmr 0/1 ccsmr 0 0 0 0 0 0 stsmr 0 0 sismr0 0 1 0 0 mdmr2 0 mdmr1 1 mdmr0 0/1 same setting value as cksmn operation mode of channel r 0: transfer end interrupt 1: buffer empty interrupt (f) serial communication operation setting register mn (scrmn) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 scrmn txemn 0 rxemn 1 dapmn 0 ckpmn 0 0 eocmn 1 ptcmn1 0/1 ptcmn0 0/1 dirmn 0/1 0 slcmn1 0 slcmn0 1 0 dlsmn2 1 dlsmn1 0/1 dlsmn0 0/1 (g) serial data register mn (sdrmn) (lower 8 bits: rxdq) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sdrmn baud rate setting 0 receive data register caution for the uart reception, be sure to set smr mr of channel r that is to be paired with channel n. remark m: unit number (m = 0, 1), n: channel number (n = 1, 3), mn = 01, 03, 13, r: channel number (r = n ? 1), q: uart number (q = 0, 1, 3) : setting is fixed in the uart reception mode, : setting disabled (set to the initial value) : bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: set to 0 or 1 depending on the usage of the user rxdq chapter 11 serial array unit user?s manual u17854ej6v0ud 403 (2) operation procedure figure 11-77. initial setting procedure for uart reception cautions after setting the per0 register to 1, be sure to set the spsm register after 4 or more clocks have elapsed. figure 11-78. procedure for stopping uart reception starting initial setting setting per0 register setting spsm register setting smrmn and smrmr registers setting scrmn register setting sdrmn register writing to ssm register starting communication release the serial array unit from the reset status and start clock supply. set the prescaler. set an operation mode, etc. set a communication format. set a transfer baud rate. set the ssmn bit of the target channel to 1 and sets semn = 1. the start bit is detected. starting setting to stop setting stm register stopping communication write 1 to the stmn bit of the target channel. stop communication in midway. chapter 11 serial array unit user?s manual u17854ej6v0ud 404 figure 11-79. procedure for resuming uart reception starting setting for resumption manipulating target for communication changing setting of spsm register changing setting of sdrmn register writing to ssm register starting communication stop the target for communication or wait until the target completes its operation. change the setting if an incorrect division ratio of the operation clock is set. change the setting if an incorrect transfer baud rate is set. change the setting if the setting of the smrmn and smrmr registers is incorrect. semn = 1 when the ssmn bit of the target channel is set to 1. the start bit is detected. (essential) (selective) change the setting if the setting of the scrmn register is incorrect. changing setting of scrmn register cleared by using sirm register if fef, pef, or ovf flag remains set. clearing error flag clear the soem register to 0 and stop data output of the target channel. changing setting of soem register changing setting of smrmn and smrmr registers (essential) (essential) (essential) (selective) (selective) (selective) (selective) chapter 11 serial array unit user?s manual u17854ej6v0ud 405 (3) processing flow figure 11-80. timing chart of uart reception ssmn semn sdrmn rxdq pin shift register mn intsrq tsfmn data reception (7-bit length) data reception (7-bit length) data reception (7-bit length) p receive data 1 receive data 2 receive data 3 receive data 2 receive data 1 shift operation shift operation shift operation sp st st p sp st p sp receive data 3 remark m: unit number (m = 0, 1), n: channel number (n = 1, 3), mn = 01, 03, 13, q: uart number (q = 0, 1, 3) chapter 11 serial array unit user?s manual u17854ej6v0ud 406 figure 11-81. flowchart of uart reception caution after setting the per0 register to 1, be sure to set the spsm register after 4 or more clocks have elapsed. starting uart communication writing 1 to ssmn bit writing 1 to stmn bit end of uart communication perform initial setting when semn = 0. smrmn, smrmr, scrmn: setting communication sdrmn[15:9]: setting transfer rate som: set ckomn and somn bits to 1 transfer end interrupt g enerated? reception completed? no no yes yes starting reception reading rxdq register (sdrmn[7:0]) detecting start bit error interrupt generated? error processing no yes port manipulation clearing sau1en and sau0en bits of per0 register to 0 setting sau1en and sau0en bits of per0 register to 1 setting transfer rate by spsm register chapter 11 serial array unit user?s manual u17854ej6v0ud 407 11.6.3 lin transmission of uart transmission, uart3 supports lin communication. for lin transmission, channel 2 of unit 1 (sau1) is used. uart uart0 uart1 uart3 support of lin communication not supported not supported supported target channel ? ? channel 2 of sau1 pins used ? ? txd3 ? ? intst3 interrupt transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer mode) can be selected. error detection flag none transfer data length 8 bits transfer rate max. f mck /6 [bps] (sdrmn [15:9] = 2 or more), min. f clk /(2 2 11 128) [bps] note data phase forward output (default: high level) reverse output (default: low level) parity bit the following selectable ? no parity bit ? appending 0 parity ? appending even parity ? appending odd parity stop bit the following selectable ? appending 1 bit ? appending 2 bits data direction msb or lsb first note use this operation within a range that satisfies the co nditions above and the ac characteristics in the electrical specifications (see chapter 27 electrical specifications ). remark f mck : operation clock (mck) frequency of target channel f clk : system clock frequency lin stands for local interconnect network and is a low-s peed (1 to 20 kbps) serial communication protocol designed to reduce the cost of an automobile network. communication of lin is single-master communicatio n and up to 15 slaves can be connected to one master. the slaves are used to control switches, actuators, and sensors, which are connect ed to the master via lin. usually, the master is connected to a network such as can (controller area network). a lin bus is a single-wire bus to which nodes are connected via transceiver conforming to iso9141. according to the protocol of lin, the master transmits a frame by attaching baud rate information to it. a slave receives this frame and corrects a baud rate error from t he master. if the baud rate error of a slave is within 15%, communication can be established. figure 11-82 outlines a trans mission operation of lin. chapter 11 serial array unit user?s manual u17854ej6v0ud 408 figure 11-82. transmission operation of lin lin bus wakeup signal frame 8 bits note 1 55h transmission data transmission data transmission data transmission data transmission 13-bit sbf transmission note 2 sync break field sync field identification field data field data field checksum field t x d3 (output) intst3 note 3 notes 1. the baud rate is set so as to satisfy the standard of the wakeup signal and data of 00h is transmitted. 2. a sync break field is defined to have a width of 13 bits and output a low level. where the baud rate for main transfer is n [bps], therefore, the baud rate of the sync break field is calculated as follows. (baud rate of sync break field) = 8/13 n by transmitting data of 00h at this baud rate, a sync break field is generated. 3. intst3 is output upon completion of transmission. intst3 is also output when sbf transmission is executed. remark the interval between fields is controlled by software. chapter 11 serial array unit user?s manual u17854ej6v0ud 409 figure 11-83. flowchart for lin transmission starting lin communication writing 1 to ss12 transmitting wakeup signal frame transmitting sync break field writing 1 to st12 end of lin communication sync break field identification field data field checksum field sync field transfer end interrupt g enerated? transfer end interrupt g enerated? writing 1 to ss12 transmitting 55h wakeup signal frame setting baud rate setting transfer data 00h setting transfer data 00h setting baud rate receiving data chapter 11 serial array unit user?s manual u17854ej6v0ud 410 11.6.4 lin reception of uart reception, uart3 supports lin communication. for lin reception, channel 3 of unit 1 (sau1) is used. uart uart0 uart1 uart3 support of lin communication not supported not supported supported target channel ? ? channel 0 of sau1 pins used ? ? rxd3 ? ? intsr3 interrupt transfer end interrupt only (setting the buffer empty interrupt is prohibited.) error interrupt ? ? intsre3 error detection flag ? framing error detection flag (fefmn) ? parity error detection flag (pefmn) ? overrun error detection flag (ovfmn) transfer data length 8 bits transfer rate max. f mck /6 [bps] (sdrmn [15:9] = 2 or more), min. f clk /(2 2 11 128) [bps] note data phase forward output (default: high level) reverse output (default: low level) parity bit the following selectable ? no parity bit ? appending 0 parity ? appending even parity ? appending odd parity stop bit the following selectable ? appending 1 bit ? appending 2 bits data direction msb or lsb first note use this operation within a range that satisfies the co nditions above and the ac characteristics in the electrical specifications (see chapter 27 electrical specifications ). remark f mck : operation clock (mck) frequency of target channel f clk : system clock frequency figure 11-84 outlines a rec eption operation of lin. chapter 11 serial array unit user?s manual u17854ej6v0ud 411 figure 11-84. reception operation of lin lin bus 13-bit sbf reception sf reception id reception data reception data reception data reception wakeup signal frame sync break field sync field identification field data filed data filed checksum field r x d3 (input) reception interrupt (intsr3) edge detection (intp0) capture timer disable enable disable enable <1> <2> <3> <4> <5> here is the flow of signal processing. <1> the wakeup signal is detected by detecting an interr upt edge (intp0) on a pin. when the wakeup signal is detected, enable reception of uart3 (r xe13 = 1) and wait for sbf reception. <2> when the start bit of sbf is detect ed, reception is started and serial da ta is sequentially stored in the rxd3 register (= bits 7 to 0 of the serial data register 13 (sdr13)) at the set baud rate. when the stop bit is detected, the recepti on end interrupt request (intsr3) is generated. when data of low levels of 11 bits or more is detected as sbf, it is judged that sbf receptio n has been correctly completed. if data of low levels of less than 11 bits is detected as sbf, it is judged t hat an sbf reception error has occurred, and the system returns to the sbf reception wait status. <3> when sbf reception has been correctly completed, st art channel 7 of the timer array unit and measure the bit interval (pulse width) of the sync field (see 6.7.5 operation as input si gnal high-/low-level width measurement ). <4> calculate a baud rate error from the bit interval of sync field (sf). stop uart3 once and adjust (re-set) the baud rate. <5> the checksum field should be distinguished by software. in addition, processing to initialize uart3 after the checksum field is received and to wait for reception of sbf should also be performed by software. chapter 11 serial array unit user?s manual u17854ej6v0ud 412 figure 11-85 shows the configuration of a port that manipulates reception of lin. the wakeup signal transmitted from the master of lin is received by detecting an edge of an external interrupt (intp0). the length of the sync fi eld transmitted from the master can be measured by using the external event capture operation of the timer array unit (tau) to calculate a baud-rate error. by controlling switch of port input (i sc0/isc1), the input source of port input (rxd3) for reception can be input to the external interrupt pin (intp0) and timer array unit (tau). figure 11-85. port configuration for manipulating reception of lin rxd3 input intp0 input channel 7 input of tau p14/rxd3 p120/intp0/ exlvi port input switch control (isc0) chapter 11 serial array unit user?s manual u17854ej6v0ud 413 the peripheral functions used for the lin communication operation are as follows. chapter 11 serial array unit user?s manual u17854ej6v0ud 414 figure 11-86. flowchart of lin reception starting lin communication detecting low-level width detecting low-level width stopping operation detecting high-level width end of lin communication sync break field identification field data field checksum field sync field sbf detected? writing 1 to st13 writing 1 to ss13 wakeup signal frame setting tau in capture mode (to measure low-level width) detecting low-level width receiving data wakeup detected? setting tau in capture mode (to measure low-/high-level width) detecting low-level width setting uart reception mode calculating baud rate detecting high-level width intp0, tau sau for details, see figure 11-81 chapter 11 serial array unit user?s manual u17854ej6v0ud 415 11.6.5 calculating baud rate (1) baud rate calculation expression the baud rate for uart (uart0, uart1, uart3) communication can be calculated by the following expressions. (baud rate) = {operation clock (mck) frequency of ta rget channel} (sdrmn[15:9] + 1) 2 [bps] caution setting sdrmn [15:9] = (0000000b, 0000001b) is prohibited. remarks 1. when uart is used, the value of sdrmn[15:9] is the value of bits 15 to 9 of the sdrmn register (0000010b to 1111111b) and therefore is 2 to 127. 2. m: unit number (m = 0, 1), n: channel number (n = 0 to 3), mn = 00-03, 12, 13 the operation clock (mck) is determined by serial cloc k select register m (spsm) and bit 15 (cksmn) of serial mode register mn (smrmn). chapter 11 serial array unit user?s manual u17854ej6v0ud 416 table 11-3 operating clock selection smrmn register spsm register operation clock (mck) note 1 cksmn prs m13 prs m12 prs m11 prs m10 prs m03 prs m02 prs m01 prs m00 f clk = 20 mhz x x x x 0 0 0 0 f clk 20 mhz x x x x 0 0 0 1 f clk /2 10 mhz x x x x 0 0 1 0 f clk /2 2 5 mhz x x x x 0 0 1 1 f clk /2 3 2.5 mhz x x x x 0 1 0 0 f clk /2 4 1.25 mhz x x x x 0 1 0 1 f clk /2 5 625 khz x x x x 0 1 1 0 f clk /2 6 313 khz x x x x 0 1 1 1 f clk /2 7 156 khz x x x x 1 0 0 0 f clk /2 8 78.1 khz x x x x 1 0 0 1 f clk /2 9 39.1 khz x x x x 1 0 1 0 f clk /2 10 19.5 khz x x x x 1 0 1 1 f clk /2 11 9.77 khz 0 x x x x 1 1 1 1 if m = 0: inttm02, if m = 1: inttm03 note 2 0 0 0 0 x x x x f clk 20 mhz 0 0 0 1 x x x x f clk /2 10 mhz 0 0 1 0 x x x x f clk /2 2 5 mhz 0 0 1 1 x x x x f clk /2 3 2.5 mhz 0 1 0 0 x x x x f clk /2 4 1.25 mhz 0 1 0 1 x x x x f clk /2 5 625 khz 0 1 1 0 x x x x f clk /2 6 313 khz 0 1 1 1 x x x x f clk /2 7 156 khz 1 0 0 0 x x x x f clk /2 8 78.1 khz 1 0 0 1 x x x x f clk /2 9 39.1 khz 1 0 1 0 x x x x f clk /2 10 19.5 khz 1 0 1 1 x x x x f clk /2 11 9.77 khz 1 1 1 1 1 x x x x if m = 0: inttm02, if m = 1: inttm03 note 2 other than above setting prohibited notes 1. when changing the clock selected for f clk (by changing the system clock control register (ckc) value), do so after having stopped (stm = 000fh) the operation of the serial array unit (sau). when selecting inttm02 and inttm03 for the operation clock, also stop the timer array unit (tau) (tt0 = 00ffh). 2. sau can be operated at a fixed division ratio of the subsystem clock, regardless of the f clk frequency (main system clock, subsystem clock), by setting the tis02 (if m = 0) and tis03 (if m = 1) bits of the tis0 regi ster of tau to 1, selecting f sub /4 for the input clock, and selecting inttm02 and inttm03 using t he spsm register. when changing f clk , however, sau and tau must be stopped as described in note 1 above. remarks 1. x: don?t care 2. m: unit number (m = 0, 1), n: channel number (n = 0 to 3), mn = 00 to 03, 12, 13 chapter 11 serial array unit user?s manual u17854ej6v0ud 417 (2) baud rate error during transmission the baud rate error of uart (uart0, uart1, uart3) communication during transmission can be calculated by the following expression. make sure that the baud rate at the transmission side is within the permissible baud rate range at the reception side. (baud rate error) = (calculated baud rate value) (target baud rate) 100 ? 100 [%] here is an example of setting a uart baud rate at f clk = 20 mhz. f clk = 20 mhz uart baud rate (target baud rate) operation clock (mck) sdrmn[15:9] calculat ed baud rate error from target baud rate 300 bps f clk /2 9 64 300.48 bps +0.16 % 600 bps f clk /2 8 64 600.96 bps +0.16 % 1200 bps f clk /2 7 64 1201.92 bps +0.16 % 2400 bps f clk /2 6 64 2403.85 bps +0.16 % 4800 bps f clk /2 5 64 4807.69 bps +0.16 % 9600 bps f clk /2 4 64 9615.38 bps +0.16 % 19200 bps f clk /2 3 64 19230.8 bps +0.16 % 31250 bps f clk /2 3 39 31250.0 bps 0.0 % 38400 bps f clk /2 2 64 38461.5 bps +0.16 % 76800 bps f clk /2 64 76923.1 bps +0.16 % 153600 bps f clk 64 153846 bps +0.16 % 312500 bps f clk 31 312500 bps 0.0 % chapter 11 serial array unit user?s manual u17854ej6v0ud 418 (3) permissible baud rate range for reception the permissible baud rate range for reception during uart (uart0, uart1, uart3) communication can be calculated by the following expression. make sure that the baud rate at the transmission side is within the permissible baud rate range at the reception side. 2 k nfr (maximum receivable baud rate) = 2 k nfr ? k + 2 brate 2 k (nfr ? 1) (minimum receivable baud rate) = 2 k nfr ? k ? 2 brate brate: calculated baud rate value at the reception side (see 11.6.5 (1) baud rate calculation expression .) k: sdrmn[15:9] + 1 nfr: 1 data frame length [bits] = (start bit) + (data length) + (parity bit) + (stop bit) remark m: unit number (m = 0, 1), n: channel number (n = 1, 3) figure 11-87. permissible baud rate range fo r reception (1 data frame length = 11 bits) fl 1 data frame (11 fl) (11 fl) min. (11 fl) max. data frame length of sau start bit bit 0 bit 1 bit 7 parity bit permissible minimum data frame length permissible maximum data frame length stop bit start bit bit 0 bit 1 bit 7 parity bit latch timing stop bit start bit bit 0 bit 1 bit 7 parity bit stop bit as shown in figure 11-87, the timing of latching receive dat a is determined by the division ratio set by bits 15 to 9 of the serial data register mn (s drmn) after the start bit is detected. if the last data (stop bit) is received before this latch timing, the data can be correctly received. chapter 11 serial array unit user?s manual u17854ej6v0ud 419 11.7 operation of simplified i 2 c (iic10) communication this is a clocked communication function to communicate with two or more devices by using two lines: serial clock (scl) and serial data (sda). this communication functi on is designed to execute single communication with devices such as eeprom, flash memory, and a/d converter, and ther efore, can be used only by the master and does not have a wait detection function. make sure by using software, as well as operating the c ontrol registers, that the ac specifications of the start and stop conditions are observed. [data transmission/reception] ? master transmission, master reception (onl y master function with a single master) ? ack output and ack detection functions ? data length of 8 bits (when an address is transmitted, the address is specified by the higher 7 bits, and the least significant bit is used for r/w control.) ? manual generation of start condition and stop condition [interrupt function] ? transfer end interrupt [error detection flag] ? parity error (ack error) * [functions not supported by simplified i 2 c] ? slave transmission, slave reception ? arbitration loss detection function ? wait detection function remark to use an i 2 c bus of full function, see chapter 12 serial interface iic0 . the channels supporting simplified i 2 c (iic10) are channel 2 of sau0. unit channel used as csi used as uart used as simplified i 2 c 0 csi00 ? 1 ? uart0 ? 2 csi10 uart1 iic10 0 3 ? ? 0 ? ? ? 1 ? ? ? 2 ? ? 1 3 ? uart3 (supporting lin-bus) ? simplified i 2 c (iic10) performs the following four types of communication operations. ? address field transmission (see 11.7.1 .) ? data transmission (see 11.7.2 .) ? data reception (see 11.7.3 .) ? stop condition generation (see 11.7.4 .) chapter 11 serial array unit user?s manual u17854ej6v0ud 420 11.7.1 address field transmission address field transmission is a transmission operation that first executes in i 2 c communication to identify the target for transfer (slave). after a start condition is generated, an address (7 bits) and a transfer direction (1 bit) are transmitted in one frame. simplified i 2 c iic10 target channel channel 2 of sau0 pins used scl10, sda10 intiic10 interrupt transfer end interrupt only (setting the buffer empty interrupt is prohibited.) error detection flag parity error detection flag (pef02) transfer data length 8 bits (transmitted with specifying the higher 7 bits as address and the least significant bit as r/w control) transfer rate max. f clk /4 mhz f clk : system clock frequency however, the following condition must be satisfied in each mode of i 2 c. ? max. 400 khz (first mode) ? max. 100 khz (standard mode) data level forward output (default: high level) parity bit no parity bit stop bit appending 1 bit (for ack reception timing) data direction msb first chapter 11 serial array unit user?s manual u17854ej6v0ud 421 (1) register setting figure 11-88. example of contents of regist ers for address field transmission of simplified i 2 c (iic10) (a) serial output register 0 (so0) ? sets only the bits of the target channel. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 so0 0 0 0 0 1 cko02 0/1 1 cko00 0 0 0 0 1 so02 0/1 1 so00 start condition is generated by manipulating the so02 bit. (b) serial output enable register 0 (soe0) ? sets only the bits of the target channel. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 soe0 0 0 0 0 0 0 0 0 0 0 0 0 0 soe02 0/1 0 soe00 soe02 = 0 until the start condition is generated, and soe02 = 1 after generation. (c) serial channel start register 0 (ss0) ? sets only the bits of the target channel is 1. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ss0 0 0 0 0 0 0 0 0 0 0 0 0 ss03 ss02 0/1 ss01 ss00 (d) serial mode register 02 (smr02) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 smr02 cks02 0/1 ccs02 0 0 0 0 0 0 sts02 0 0 sis020 0 1 0 0 md022 1 md021 0 md020 0 operation mode of channel 2 0: transfer end interrupt (e) serial communication operati on setting register 02 (scr02) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 scr02 txe02 1 rxe02 0 dap02 0 ckp02 0 0 eoc02 0 ptc021 0 ptc020 0 dir02 0 0 slc021 0 slc020 1 0 dls022 1 dls021 1 dls020 1 setting of parity bit 00b: no parity setting of stop bit 01b: appending 1 bit (ack) (f) serial data register 02 (sdr02) (lower 8 bits: sio10) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sdr02 baud rate setting 0 transmit data setting (address + r/w) remark : setting is fixed in the iic mode, : setting disabled (set to the initial value) : bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: set to 0 or 1 depending on the usage of the user sio10 chapter 11 serial array unit user?s manual u17854ej6v0ud 422 (2) operation procedure figure 11-89. initial setting pro cedure for address field transmission caution after setting the per0 register to 1, be sure to set the sps0 register after 4 or more clocks have elapsed. starting initial setting setting per0 register setting sps0 register setting smr02 register setting scr02 register setting sdr02 register setting so0 register setting port setting so0 register starting communication release the serial array unit from the reset status and start clock supply. set the prescaler. set an operation mode, etc. set a communication format. set a transfer baud rate. manipulate the so02 and cko02 bit and set an initial out p ut level. enable data output and clock output of the target channel by setting a port register and a port mode register. clear the so02 bit to 0 to generate the start condition. set address and r/w to the sio10 register (bits 7 to 0 of the sdr02 re g iste r ) and start communication. setting so0 register writing to ss0 register clear the cko02 bit to 0 to lower the clock output level. se02 = 1 when the ss02 bit of the target channel is set to 1. secure a wait time so that the specifications of i 2 c on the slave side are satisfied. wait changing setting of soe0 register set the soe02 bit to 1 and enable data output of the target channel. chapter 11 serial array unit user?s manual u17854ej6v0ud 423 (3) processing flow figure 11-90. timing chart of address field transmission d7 d6 d5 d4 address d3 shift operation d2 d1 d0 r/w d7 d6 address field transmission ss02 se02 soe02 sdr02 scl10 output sda10 output sda10 input shift register 02 intiicr tsf02 transmit data 1 d5 d4 d3 d2 d1 d0 ack so02 bit manipulation cko02 bit manipulation chapter 11 serial array unit user?s manual u17854ej6v0ud 424 figure 11-91. flowchart of address field transmission starting iic communication writing 0 to so02 bit address field transmission completed perform initial setting when se02 = 0. smr02, scr02: setting communication sps0, sdr02[15:9]: setting transfer rate transfer end interrupt g enerated? no yes writing address and r/w data to sio10 (sdr02[7:0]) writing 1 to ss02 bit parity error (ack error) flag pef02 = 1 ? no yes ack reception error writing 1 to soe02 bit writing 0 to cko02 bit to data transmission flow and data reception flow chapter 11 serial array unit user?s manual u17854ej6v0ud 425 11.7.2 data transmission data transmission is an operation to transmit data to the ta rget for transfer (slave) after transmission of an address field. after all data are transmitted to the slave, a stop condition is generated and the bus is released. simplified i 2 c iic10 target channel channel 2 of sau0 pins used scl10, sda10 intiic10 interrupt transfer end interrupt only (setting the buffer empty interrupt is prohibited.) error detection flag parity error detection flag (pef02) transfer data length 8 bits transfer rate max. f clk /4 mhz f clk : system clock frequency however, the following condition must be satisfied in each mode of i 2 c. ? max. 400 khz (first mode) ? max. 100 khz (standard mode) data level forward output (default: high level) parity bit no parity bit stop bit appending 1 bit (for ack reception timing) data direction msb first chapter 11 serial array unit user?s manual u17854ej6v0ud 426 (1) register setting figure 11-92. example of contents of regi sters for data transmission of simplified i 2 c (iic10) (a) serial output register 0 (so0) ? do not manipulate this regi ster during data transmission/reception. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 so0 0 0 0 0 1 cko02 0/1 note 1 cko00 0 0 0 0 1 so02 0/1 note 1 so00 (b) serial output enable register 0 (soe0) ? do not manipulate this register during data transmission/reception. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 soe0 0 0 0 0 0 0 0 0 0 0 0 0 0 soe02 1 0 soe00 (c) serial channel start register 0 (ss0) ? do not manipulate this register during data transmission/reception. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ss0 0 0 0 0 0 0 0 0 0 0 0 0 ss03 ss02 0/1 ss01 ss00 (d) serial mode register 02 (smr02) ? do not manipulate this re gister during data transmission/reception. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 smr02 cks02 0/1 ccs02 0 0 0 0 0 0 sts02 0 0 sis020 0 1 0 0 md022 1 md021 0 md020 0 (e) serial communication operation se tting register 02 (scr02) ? do not manipulate the bits of this register, except the txe02 and rxe02 bits, during data transmission/reception. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 scr02 txe02 1 rxe02 0 dap02 0 ckp02 0 0 eoc02 0 ptc021 0 ptc020 0 dir02 0 0 slc021 0 slc020 1 0 dls022 1 dls021 1 dls020 1 (f) serial data register 02 (sdr02) (lower 8 bits: sio10) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sdr02 baud rate setting 0 transmit data setting note the value varies depending on the communication data during communication operation. remark : setting is fixed in the iic mode, : setting disabled (set to the initial value) : bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: set to 0 or 1 depending on the usage of the user sio10 chapter 11 serial array unit user?s manual u17854ej6v0ud 427 (2) processing flow figure 11-93. timing chart of data transmission d7 d6 d5 d4 d3 shift operation d2 d1 d0 d7 ?l? ?h? ?h? d6 transmit data 1 ss02 se02 soe02 sdr02 scl10 output sda10 output sda10 input shift register 02 intiic10 tsf02 transmit data1 d5 d4 d3 d2 d1 d0 ack figure 11-94. flowchart of data transmission starting data transmission data transmission completed transfer end interrupt g enerated? no yes writing data to sio10 (sdr02[7:0]) no yes ack reception error s top con di t i on generat i on data transfer completed? yes no address field transmission completed parity error (ack error) flag pef02 = 1 ? chapter 11 serial array unit user?s manual u17854ej6v0ud 428 11.7.3 data reception data reception is an operation to receive data to the target for transfer (slave) after transmission of an address field. after all data are received to the slave, a stop condition is generated and the bus is released. simplified i 2 c iic10 target channel channel 2 of sau0 pins used scl10, sda10 intiic10 interrupt transfer end interrupt only (setting the buffer empty interrupt is prohibited.) error detection flag none transfer data length 8 bits transfer rate max. f clk /4 mhz f clk : system clock frequency however, the following condition must be satisfied in each mode of i 2 c. ? max. 400 khz (first mode) ? max. 100 khz (standard mode) data level forward output (default: high level) parity bit no parity bit stop bit appending 1 bit (ack transmission) data direction msb first chapter 11 serial array unit user?s manual u17854ej6v0ud 429 (1) register setting figure 11-95. example of contents of re gisters for data reception of simplified i 2 c (iic10) (a) serial output register 0 (so0) ? do not manipulate this regi ster during data transmission/reception. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 so0 0 0 0 0 1 cko02 0/1 note 1 cko00 0 0 0 0 1 so02 0/1 note 1 so00 (b) serial output enable register 0 (soe0) ? do not manipulate this register during data transmission/reception. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 soe0 0 0 0 0 0 0 0 0 0 0 0 0 0 soe02 1 0 soe00 (c) serial channel start register 0 (ss0) ? do not manipulate this register during data transmission/reception. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ss0 0 0 0 0 0 0 0 0 0 0 0 0 ss03 ss02 0/1 ss01 ss00 (d) serial mode register 02 (smr02) ? do not manipulate this re gister during data transmission/reception. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 smr02 cks02 0/1 ccs02 0 0 0 0 0 0 sts02 0 0 sis020 0 1 0 0 md022 1 md021 0 md020 0 (e) serial communication operation se tting register 02 (scr02) ? do not manipulate the bits of this register, except the txe02 and rxe02 bits, during data transmission/reception. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 scr02 txe02 0 rxe02 1 dap02 0 ckp02 0 0 eoc02 0 ptc021 0 ptc020 0 dir02 0 0 slc021 0 slc020 1 0 dls022 1 dls021 1 dls020 1 (f) serial data register 02 (sdr02) (lower 8 bits: sio10) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sdr02 baud rate setting 0 dummy transmit data setting (ffh) note the value varies depending on the communication data during communication operation. remark : setting is fixed in the iic mode, : setting disabled (set to the initial value) : bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: set to 0 or 1 depending on the usage of the user sio10 chapter 11 serial array unit user?s manual u17854ej6v0ud 430 (2) processing flow figure 11-96. timing chart of data reception d7 d6 d5 d4 d3 d2 d1 d0 soe02 sdr02 intiic10 tsf02 ack txe02 = 0 / rxe02 = 1 txe02, rxe02 txe02 = 1 / rxe02 = 0 shift operation ?h? dummy data (ffh) scl10 output sda10 output sda10 input shift register 02 receive data ss02 se02 st02 figure 11-97. flowchart of data reception caution ack is also output when the last data is received. co mmunication is then completed by setting ?1? to the stmn bit to stop ope ration and generating a stop condition. starting data reception data reception completed transfer end interrupt g enerated? no yes writing dummy data (ffh) to sio10 (sdr02[7:0]) s to p con di t i on g enerat i on data transfer completed? yes no reading sio10 (sdr02[7:0]) address field tran smission completed writing 1 to st02 bit writing 0 to txe02 bit, and 1 to rxe02 bit writing 1 to ss02 bit chapter 11 serial array unit user?s manual u17854ej6v0ud 431 11.7.4 stop condition generation after all data are transmitted to or received from the ta rget slave, a stop condition is generated and the bus is released. (1) processing flow figure 11-98. timing chart of stop condition generation stop condition st02 se02 soe02 scl10 output sda10 output operation stop so02 bit manipulation cko02 bit manipulation so02 bit manipulation figure 11-99. flowchart of stop condition generation starting generation of stop condition. end of iic communication writing 1 to st02 bit to clear (se02 is cleared to 0) writing 0 to soe02 bit writing 1 to so02 bit writing 1 to cko02 bit writing 0 to so02 bit completion of data transmission/data reception wait secure a wait time so that the specifications of i 2 c on the slave side are satisfied. chapter 11 serial array unit user?s manual u17854ej6v0ud 432 11.7.5 calculating transfer rate the transfer rate for simplified i 2 c (iic10) communication can be calculated by the following expressions. (transfer rate) = {operation clock (mck) frequency of target channel} (sdr02[15:9] + 1) 2 remark the value of sdr02[15:9] is the value of bits 15 to 9 of the sdr02 register (0000000b to 1 111111b) and therefore is 0 to 127. the operation clock (mck) is determined by serial clock select register 0 (sps0) and bit 15 (cks02) of serial mode register 02 (smr02). chapter 11 serial array unit user?s manual u17854ej6v0ud 433 table 11-4 operating clock selection smr02 register sps0 register operation clock (mck) note 1 cks02 prs 013 prs 012 prs 011 prs 010 prs 003 prs 002 prs 001 prs 000 f clk = 20 mhz x x x x 0 0 0 0 f clk 20 mhz x x x x 0 0 0 1 f clk /2 10 mhz x x x x 0 0 1 0 f clk /2 2 5 mhz x x x x 0 0 1 1 f clk /2 3 2.5 mhz x x x x 0 1 0 0 f clk /2 4 1.25 mhz x x x x 0 1 0 1 f clk /2 5 625 khz x x x x 0 1 1 0 f clk /2 6 313 khz x x x x 0 1 1 1 f clk /2 7 156 khz x x x x 1 0 0 0 f clk /2 8 78.1 khz x x x x 1 0 0 1 f clk /2 9 39.1 khz x x x x 1 0 1 0 f clk /2 10 19.5 khz x x x x 1 0 1 1 f clk /2 11 9.77 khz 0 x x x x 1 1 1 1 inttm02 note 2 0 0 0 0 x x x x f clk 20 mhz 0 0 0 1 x x x x f clk /2 10 mhz 0 0 1 0 x x x x f clk /2 2 5 mhz 0 0 1 1 x x x x f clk /2 3 2.5 mhz 0 1 0 0 x x x x f clk /2 4 1.25 mhz 0 1 0 1 x x x x f clk /2 5 625 khz 0 1 1 0 x x x x f clk /2 6 313 khz 0 1 1 1 x x x x f clk /2 7 156 khz 1 0 0 0 x x x x f clk /2 8 78.1 khz 1 0 0 1 x x x x f clk /2 9 39.1 khz 1 0 1 0 x x x x f clk /2 10 19.5 khz 1 0 1 1 x x x x f clk /2 11 9.77 khz 1 1 1 1 1 x x x x inttm02 note 2 other than above setting prohibited notes 1. when changing the clock selected for f clk (by changing the system clock control register (ckc) value), do so after having stopped (st0 = 000fh) the operation of the serial array unit (sau). when selecting inttm02 for the operation clock, also stop the timer array unit (tau) (tt0 = 00ffh). 2. sau can be operated at a fixed division ratio of the subsystem clock, regardless of the f clk frequency (main system clock, subsystem cloc k), by setting the tis02 bit of the tis0 register of tau to 1, selecting f sub /4 for the input clock, and selecting inttm02 using the sps0 register. when changing f clk , however, sau and tau must be stopped as described in note 1 above. remark x: don?t care chapter 11 serial array unit user?s manual u17854ej6v0ud 434 here is an example of setting an iic transfer rate where mck = f clk = 20 mhz. f clk = 20 mhz iic transfer mode (desired transfer rate) operation clock (mck) sdr02[15:9] calculated transfer rate error from desired transfer rate 100 khz f clk 99 100 khz 0.0% 400 khz f clk 24 400 khz 0.0% chapter 11 serial array unit user?s manual u17854ej6v0ud 435 11.8 processing procedure in case of error the processing procedure to be followed if an error of each type occurs is described in figures 11-100 to 11-102. figure 11-100. processing procedure in case of parity error or overrun error software manipulation hardware status remark reads sdrmn register. bff = 0, and channel n is enabled to receive data. this is to prevent an overrun error if the next reception is completed during error processing. reads ssrmn register. error type is identified and the read value is used to clear error flag. writes sirmn register. error flag is cl eared. error can be cleared only during reading, by writing the value read from the ssrmn register to the sirmn register without modification. figure 11-101. processing procedure in case of framing error software manipulation hardware status remark reads sdrmn register. bff = 0, and channel n is enabled to receive data. this is to prevent an overrun error if the next reception is completed during error processing. reads ssrmn register. error type is identified and the read value is used to clear error flag. writes sirmn register. error flag is cl eared. error can be cleared only during reading, by writing the value read from the ssrmn register to the sirmn register without modification. sets stmn bit to 1. semn = 0, and channel n stops operation. synchronization with other party of communication synchronization with the other party of communication is re-established and communication is resumed because it is considered that a framing error has occurred because the start bit has been shifted. sets ssmn bit to 1. semn = 1, and channel n is enabled to operate. remark m: unit number (m = 0, 1), n: channel number (n = 0 to 3), 00 to 03, 12, 13 chapter 11 serial array unit user?s manual u17854ej6v0ud 436 figure 11-102. processing procedure in case of parity error (ack error) in simplified i 2 c mode software manipulation hardware status remark reads sdr02 register. bff = 0, and channel 2 is enabled to receive data. this is to prevent an overrun error if the next reception is completed during error processing. reads ssr02 register. error type is identified and the read value is used to clear error flag. writes sir02 register. error flag is cl eared. error can be cleared only during reading, by writing the value read from the ssr02 register to the sir02 register without modification. sets st02 bit to 1. se02 = 0, and channel 2 stops operation. creates stop condition. creates start condition. slave is not ready for reception because ack is not returned. therefore, a stop condition is created, the bus is released, and communication is started again from the start condition. or, a restart condition is generated and transmission can be redone from address transmission. sets ss02 bit to 1. se02 = 1, and channel 2 is enabled to operate. chapter 11 serial array unit user?s manual u17854ej6v0ud 437 11.9 relationship between register settings and pins tables 11-5 to 11-10 show the relationship between register settings and pins for each channel of serial array units 0 and 1. table 11-5. relationship between regi ster settings and pins (c hannel 0 of unit 0: csi00, uart0 transmission) pin function se 00 note1 md 002 md 001 soe 00 so 00 cko 00 txe 00 rxe 00 pm 10 p10 pm 11 note2 p11 note2 pm 12 p12 operation mode sck00/ p10 si00/rxd0/ p11 note2 so00/txd0/ p12 0 0 p11 0 0 1 0 1 1 0 0 note3 note3 note3 note3 note3 note3 operation stop mode p10 p11/rxd0 p12 0 1 1 0 1 1 1 note3 note3 slave csi00 reception sck00 (input) si00 p12 1 0/1 note4 1 1 0 1 note3 note3 0 1 slave csi00 transmission sck00 (input) p11 so00 1 0/1 note4 1 1 1 1 1 0 1 slave csi00 transmission/ reception sck00 (input) si00 so00 0 1 0/1 note4 0 1 0 1 1 note3 note3 master csi00 reception sck00 (output) si00 p12 1 0/1 note4 0/1 note4 1 0 0 1 note3 note3 0 1 master csi00 transmission sck00 (output) p11 so00 0 0 1 0/1 note4 0/1 note4 1 1 0 1 1 0 1 master csi00 transmission/ reception sck00 (output) si00 so00 1 0 1 1 0/1 note4 1 1 0 note3 note3 note3 note3 0 1 uart0 transmission note5 p10 p11/rxd0 txd0 notes 1. the se0 register is a read-only status register which is set using the ss0 and st0 registers. 2. when channel 1 of unit 0 is set to uart0 reception, this pin becomes an rxd0 function pin (refer to table 11-6 ). in this case, operation stop mode or uart0 transmission must be selected for channel 0 of unit 0. 3. this pin can be set as a port function pin. 4. this is 0 or 1, depending on the communication operation. for details, refer to 11.3 (12) serial output register m (som) . 5. when using uart0 transmission and reception in a pair, set channel 1 of unit 0 to uart0 reception (refer to table 11-6 ). remark x: don?t care chapter 11 serial array unit user?s manual u17854ej6v0ud 438 table 11-6. relationship between register settings and pins (channel 1 of un it 0: uart0 reception) pin function se01 note1 md012 md011 txe01 rxe01 pm11 note2 p11 note2 operation mode si00/rxd0/p11 note2 0 0 1 0 0 note3 note3 operation stop mode si00/p11 1 0 1 0 1 1 uart0 reception note4, 5 rxd0 notes 1. the se0 register is a read-only status register which is set using the ss0 and st0 registers. 2. when channel 1 of unit 0 is set to uart0 reception, th is pin becomes an rxd0 function pin. in this case, set channel 0 of unit 0 to operation stop mode or uart0 transmission (refer to table 11-5 ). when channel 0 of unit 0 is set to csi00, this pin cannot be used as an rxd0 function pin. in this case, set channel 1 of unit 0 to operation stop mode. 3. this pin can be set as a port function pin. 4. when using uart0 transmission and reception in a pair, set channel 0 of unit 0 to uart0 transmission (refer to table 11-5 ). 5. the smr00 register of chan nel 0 of unit 0 must also be set during uart0 reception. for details, refer to 11.5.2 (1) register setting . remark x: don?t care chapter 11 serial array unit user?s manual u17854ej6v0ud 439 table 11-7. relationship between register settings and pins (channel 2 of unit 0: csi10, uart1 transmission, iic10) pin function se 02 note1 md 022 md 021 soe 02 so 02 cko 02 txe 02 rxe 02 pm 04 p04 pm03 note2 p03 note2 pm02 p02 operation mode sck10/ scl10/p04 si10/sda10/ rxd1/p03 note2 so10/ txd1/p02 0 0 p03 0 1 p03/rxd1 0 1 0 0 1 1 0 0 note3 note3 note3 note3 note3 note3 operation stop mode p04 p03 p02 0 1 1 0 1 1 1 note3 note3 slave csi10 reception sck10 (input) si10 p02 1 0/1 note4 1 1 0 1 note3 note3 0 1 slave csi10 transmission sck10 (input) p03 so10 1 0/1 note4 1 1 1 1 1 0 1 slave csi10 transmission /reception sck10 (input) si10 so10 0 1 0/1 note4 0 1 0 1 1 note3 note3 master csi10 reception sck10 (output) si10 p02 1 0/1 note4 0/1 note4 1 0 0 1 note3 note3 0 1 master csi10 transmission sck10 (output) p03 so10 0 0 1 0/1 note4 0/1 note4 1 1 0 1 1 0 1 master csi10 transmission /reception sck10 (output) si10 so10 1 0 1 1 0/1 note4 1 1 0 note3 note3 note3 note3 0 1 uart1 transmission note5 p04 p03/rxd1 txd1 0 0 1 0 0 0 0/1 note6 0/1 note6 0 1 0 1 0 1 note3 note3 iic10 start condition scl10 sda10 p02 1 0/1 note4 0/1 note4 1 0 0 1 0 1 note3 note3 iic10 address field transmission scl10 sda10 p02 1 0/1 note4 0/1 note4 1 0 0 1 0 1 note3 note3 iic10 data transmission scl10 sda10 p02 1 1 0/1 note4 0/1 note4 0 1 0 1 0 1 note3 note3 iic10 data reception scl10 sda10 p02 0 0 1 0 0 1 0 0 0/1 note7 0/1 note7 0 1 0 1 0 1 note3 note3 iic10 stop condition scl10 sda10 p02 notes 1. the se0 register is a read-only status register which is set using the ss0 and st0 registers. 2. when channel 3 of unit 0 is set to uart1 reception, this pin becomes an rxd1 function pin (refer to table 11-8 ). in this case, operation stop mode or uart1 transmission must be selected for channel 2 of unit 0. 3. this pin can be set as a port function pin. 4. this is 0 or 1, depending on the communication operation. for details, refer to 11.3 (12) serial output register m (som) . 5. when using uart1 transmission and reception in a pair, set channel 3 of unit 0 to uart1 reception (refer to table 11-8 ). 6. set the cko02 bit to 1 before a start condition is genera ted. clear the so02 bit fr om 1 to 0 when the start condition is generated. 7. set the cko02 bit to 1 before a stop condition is gene rated. clear the so02 bit from 0 to 1 when the stop condition is generated. remark x: don?t care chapter 11 serial array unit user?s manual u17854ej6v0ud 440 table 11-8. relationship between register settings and pins (channel 3 of un it 0: uart1 reception) pin function se03 note1 md032 md031 txe03 rxe03 pm03 note2 p03 note2 operation mode si10/sda10/rxd1/p03 note2 0 0 1 0 0 note3 note3 operation stop mode si10/sda10/p03 note2 1 0 1 0 1 1 uart1 reception note4, 5 rxd1 notes 1. the se0 register is a read-only status register which is set using the ss0 and st0 registers. 2. when channel 3 of unit 0 is set to uart1 reception, th is pin becomes an rxd1 function pin. in this case, set channel 2 of unit 0 to operation stop mode or uart1 transmission (refer to table 11-7 ). when channel 2 of unit 0 is set to csi10 or iic10, this pi n cannot be used as an rxd1 function pin. in this case, set channel 3 of unit 0 to operation stop mode. 3. this pin can be set as a port function pin. 4. when using uart1 transmission and reception in a pair, set channel 2 of unit 0 to uart1 transmission (refer to table 11-7 ). 5. the smr02 register of chan nel 2 of unit 0 must also be set during uart1 reception. for details, refer to 11.5.2 (1) register setting . remark x: don?t care chapter 11 serial array unit user?s manual u17854ej6v0ud 441 table 11-9. relationship between register settings a nd pins (channel 2 of unit 1: uart3 transmission) pin function se12 note1 md122 md121 soe12 so12 txe12 rxe12 pm13 p13 operation mode txd3/p13 0 0 1 0 1 0 0 note2 note2 operation stop mode p13 1 0 1 1 0/1 note3 1 0 0 1 uart3 transmission note4 txd3 notes 1. the se1 register is a read-only status register which is set using the ss1 and st1 registers. 2. this pin can be set as a port function pin. 3. this is 0 or 1, depending on the communication operation. for details, refer to 11.3 (12) serial output register m (som) . 4. when using uart3 transmission and reception in a pair, set channel 3 of unit 1 to uart3 reception (refer to table 11-10 ). remark x: don?t care table 11-10. relationship between register settings and pins (channel 3 of un it 1: uart3 reception) pin function se13 note1 md132 md131 txe13 rxe13 pm14 p14 operation mode rxd3/p14 0 0 1 0 0 note2 note2 operation stop mode p14 1 0 1 0 1 1 uart3 reception note3, 4 rxd3 notes 1. the se1 register is a read-only status register which is set using the ss1 and st1 registers. 2. this pin can be set as a port function pin. 3. when using uart3 transmission and reception in a pair, set channel 2 of unit 1 to uart3 transmission (refer to table 11-9 ). 4. the smr12 register of chan nel 2 of unit 1 must also be set during uart3 reception. for details, refer to 11.5.2 (1) register setting . remark x: don?t care user?s manual u17854ej6v0ud 442 chapter 12 serial interface iic0 12.1 functions of serial interface iic0 serial interface iic0 has the following two modes. (1) operation stop mode this mode is used when serial transfers are not performed. it can therefore be used to reduce power consumption. (2) i 2 c bus mode (multimaster supported) this mode is used for 8-bit data transfers with several devices via two lines: a serial clock (scl0) line and a serial data bus (sda0) line. this mode complies with the i 2 c bus format and the master device can generated ?start condition?, ?address?, ?transfer direction specification?, ?dat a?, and ?stop condition? data to the slave device, via the serial data bus. the slave device automatically detects these received status and data by har dware. this function can simplify the part of application prog ram that controls the i 2 c bus. since the scl0 and sda0 pins are used for open drain ou tputs, iic0 requires pull-up resistors for the serial clock line and the serial data bus line. figure 12-1 shows a block diagram of serial interface iic0. chapter 12 serial interface iic0 user?s manual u17854ej6v0ud 443 figure 12-1. block diagram of serial interface iic0 internal bus iic status register 0 (iics0) iic control register 0 (iicc0) slave address register 0 (sva0) noise eliminator noise eliminator bus status detector match signal iic shift register 0 (iic0) so latch iice0 dq set clear cl01, cl00 trc0 dfc0 dfc0 sda0/ p61 scl0/ p60 data hold time correction circuit start condition generator stop condition generator ack generator wakeup controller ack detector output control stop condition detector serial clock counter interrupt request signal generator serial clock controller serial clock wait controller prescaler intiic0 iic shift register 0 (iic0) iicc0.stt0, spt0 iics0.msts0, exc0, coi0 iics0.msts0, exc0, coi0 f clk lrel0 wrel0 spie0 wtim0 acke0 stt0 spt0 msts0 ald0 exc0 coi0 trc0 ackd0 std0 spd0 start condition detector internal bus cld0 dad0 smc0 dfc0 cl01 cl00 clx0 iic clock select register 0 (iiccl0) stcf iicbsy stcen iicrsv iic flag register 0 (iicf0) iic function expansion register 0 (iicx0) n-ch open- drain output pm61 output latch (p61) n-ch open- drain output pm60 output latch (p60) chapter 12 serial interface iic0 user?s manual u17854ej6v0ud 444 figure 12-2 shows a serial bus configuration example. figure 12-2. serial bus c onfiguration example using i 2 c bus master cpu1 slave cpu1 address 0 sda0 scl0 serial data bus serial clock + v dd + v dd sda0 scl0 sda0 scl0 sda0 scl0 sda0 scl0 master cpu2 slave cpu2 address 1 slave cpu3 address 2 slave ic address 3 slave ic address n chapter 12 serial interface iic0 user?s manual u17854ej6v0ud 445 12.2 configuration of serial interface iic0 serial interface iic0 includes the following hardware. table 12-1. configuration of serial interface iic0 item configuration registers iic shift register 0 (iic0) slave address register 0 (sva0) control registers peripheral enable register 0 (per0) iic control register 0 (iicc0) iic status register 0 (iics0) iic flag register 0 (iicf0) iic clock select register 0 (iiccl0) iic function expansion register 0 (iicx0) port mode register 6 (pm6) port register 6 (p6) (1) iic shift register 0 (iic0) iic0 is used to convert 8-bit serial data to 8-bit paralle l data and vice versa in synchronization with the serial clock. iic0 can be used for both transmission and reception. the actual transmit and receive operations can be contro lled by writing and reading operations to iic0. cancel the wait state and start data transfer by writing data to iic0 during the wait period. iic0 can be set by an 8-bit memory manipulation instruction. reset signal generation clears iic0 to 00h. figure 12-3. format of iic shift register 0 (iic0) symbol iic0 address: fff50h after reset: 00h r/w 76543210 cautions 1. do not write data to iic0 during data transfer. 2. write or read iic0 only during the wait pe riod. accessing iic0 in a communication state other than during the wait period is prohibit ed. when the device serves as the master, however, iic0 can be written only once after the communication trigger bit (stt0) is set to 1. (2) slave address register 0 (sva0) this register stores local addresses when in slave mode. sva0 can be set by an 8-bit memory manipulation instruction. however, rewriting to this register is prohibited wh ile std0 = 1 (while the start condition is detected). reset signal generation clears sva0 to 00h. figure 12-4. format of slave address register 0 (sva0) symbol sva0 address: fff53h after reset: 00h r/w 76543210 0 note note bit 0 is fixed to 0. chapter 12 serial interface iic0 user?s manual u17854ej6v0ud 446 (3) so latch the so latch is used to retain the sda0 pin?s output level. (4) wakeup controller this circuit generates an interrupt request (intiic0) w hen the address received by this register matches the address value set to slave address register 0 (sva0) or when an extension code is received. (5) prescaler this selects the sampling clock to be used. (6) serial clock counter this counter counts the serial clocks that are output or input during transmi t/receive operations and is used to verify that 8-bit data was transmitted or received. (7) interrupt request signal generator this circuit controls the generation of interrupt request signals (intiic0). an i 2 c interrupt request is generated by the following two triggers. ? falling edge of eighth or ninth clock of the serial clock (set by wtim0 bit) ? interrupt request generated when a stop cond ition is detected (set by spie0 bit) remark wtim0 bit: bit 3 of iic control register 0 (iicc0) spie0 bit: bit 4 of iic control register 0 (iicc0) (8) serial clock controller in master mode, this circuit generates the clock output via the scl0 pin from a sampling clock. (9) serial clock wait controller this circuit controls the wait timing. (10) ack generator, stop condition detector, start condition detector, and ack detector these circuits generate and detect each status. (11) data hold time correction circuit this circuit generates the hold time for data corre sponding to the falling edge of the serial clock. (12) start condition generator this circuit generates a start conditi on when the stt0 bit is set to 1. however, in the communication reservation disabled stat us (iicrsv bit = 1), when the bus is not released (iicbsy bit = 1), start condition requests are ignored and the stcf bit is set to 1. (13) stop condition generator this circuit generates a stop condition when the spt0 bit is set to 1. chapter 12 serial interface iic0 user?s manual u17854ej6v0ud 447 (14) bus status detector this circuit detects whether or not the bus is releas ed by detecting start conditions and stop conditions. however, as the bus status cannot be detected immediately following operation, the initial status is set by the stcen bit. remark stt0 bit: bit 1 of iic control register 0 (iicc0) spt0 bit: bit 0 of iic control register 0 (iicc0) iicrsv bit: bit 0 of iic flag register 0 (iicf0) iicbsy bit: bit 6 of iic flag register 0 (iicf0) stcf bit: bit 7 of iic flag register 0 (iicf0) stcen bit: bit 1 of iic flag register 0 (iicf0) chapter 12 serial interface iic0 user?s manual u17854ej6v0ud 448 12.3 registers to controlling serial interface iic0 serial interface iic0 is controlled by the following eight registers. ? peripheral enable register 0 (per0) ? iic control register 0 (iicc0) ? iic flag register 0 (iicf0) ? iic status register 0 (iics0) ? iic clock select register 0 (iiccl0) ? iic function expansion register 0 (iicx0) ? port mode register 6 (pm6) ? port register 6 (p6) (1) peripheral enable register 0 (per0) per0 is used to enable or disable use of each peripheral hardware macro. clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise. when serial interface iic0 is used, be sure to set bit 4 (iic0en) of this register to 1. per0 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clea rs this register to 00h. cautions 1. when setting serial interfac e iic0, be sure to set iic0en to 1 first. if iic0en = 0, writing to a control register of serial interface iic0 is ignored , and, even if the register is read, only the default value is read. 2. be sure to clear bits 1 and 6 of per0 register to 0. figure 12-5. format of peripheral enable register 0 (per0) address: f00f0h after reset: 00h r/w symbol <7> 6 <5> <4> <3> <2> 1 <0> per0 rtcen 0 adcen iic0en sau1en sau0en 0 tau0en iic0en control of serial interface iic0 input clock 0 stops supply of input clock. ? sfr used by serial interface iic0 cannot be written. ? serial interface iic0 is in the reset status. 1 supplies input clock. ? sfr used by serial interface iic0 can be read/written. (2) iic control register 0 (iicc0) this register is used to enable/stop i 2 c operations, set wait timing, and set other i 2 c operations. iicc0 can be set by a 1-bit or 8-bit memory manipulation instruction. however, set the spie0, wtim0, and acke0 bits while iice0 bit = 0 or during the wait period. these bits can be set at the same time when the iice0 bit is set from ?0? to ?1?. reset signal generation clea rs this register to 00h. chapter 12 serial interface iic0 user?s manual u17854ej6v0ud 449 figure 12-6. format of iic control register 0 (iicc0) (1/4) address: fff52h after reset: 00h r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> iicc0 iice0 lrel0 wrel0 spie0 wtim0 acke0 stt0 spt0 iice0 i 2 c operation enable 0 stop operation. reset iic status register 0 (iics0) note 1 . stop internal operation. 1 enable operation. be sure to set this bit (1) while the scl0 and sda0 lines are at high level. condition for clearing (iice0 = 0) condition for setting (iice0 = 1) ? cleared by instruction ? reset ? set by instruction lrel0 note 2 exit from communications 0 normal operation 1 this exits from the current communications and sets standby mode. this setting is automatically cleared to 0 after being executed. its uses include cases in which a locally irrelevant extension code has been received. the scl0 and sda0 lines are set to high impedance. the following flags of iic control register 0 (iicc0) and iic status register 0 (iics0) are cleared to 0. ? stt0 ? spt0 ? msts0 ? exc0 ? coi0 ? trc0 ? ackd0 ? std0 the standby mode following exit from communications rema ins in effect until the following communications entry conditions are met. ? after a stop condition is detected, restart is in master mode. ? an address match or extension code rece ption occurs after the start condition. condition for clearing (lrel0 = 0) condition for setting (lrel0 = 1) ? automatically cleared after execution ? reset ? set by instruction wrel0 note 2 wait cancellation 0 do not cancel wait 1 cancel wait. this setting is automatic ally cleared after wait is canceled. when wrel0 is set (wait canceled) during the wait period at the ninth clock pulse in the transmission status (trc0 = 1), the sda0 line goes into the high impedance state (trc0 = 0). condition for clearing (wrel0 = 0) condition for setting (wrel0 = 1) ? automatically cleared after execution ? reset ? set by instruction notes 1. the iics0 register, the stcf0 and iicbsy bits of the iicf0 register, and the cld0 and dad0 bits of the iiccl0 register are reset. 2. this flag?s signal is invalid when iice0 = 0. caution the start condition is detected immediately after i 2 c is enabled to operate (iice0 = 1) while the scl0 line is at high level and the sda0 line is at low level. immediately after enabling i 2 c to operate (iice0 = 1), set lrel0 (1 ) by using a 1-bit memory manipulation instruction. chapter 12 serial interface iic0 user?s manual u17854ej6v0ud 450 figure 12-6. format of iic control register 0 (iicc0) (2/4) spie0 note 1 enable/disable generation of interrupt request when stop condition is detected 0 disable 1 enable condition for clearing (spie0 = 0) condition for setting (spie0 = 1) ? cleared by instruction ? reset ? set by instruction wtim0 note 1 control of wait and interrupt request generation 0 interrupt request is generated at the eighth clock?s falling edge. master mode: after output of eight clocks, cloc k output is set to low level and wait is set. slave mode: after input of eight clo cks, the clock is set to low level and wait is set for master device. 1 interrupt request is generated at the ninth clock?s falling edge. master mode: after output of nine clocks, clock output is set to low level and wait is set. slave mode: after input of nine clo cks, the clock is set to low level and wait is set for master device. an interrupt is generated at the falling edge of the ninth clock during address transfer independently of the setting of this bit. the setting of this bit is valid when the address transfer is completed. when in master mode, a wait is inserted at the falling edge of the ninth clock during address tr ansfers. for a slave device that has received a local address, a wait is inserted at the falling edge of the ninth clock after an acknowledge (ack) is issued. however, when the slave device has received an extension code, a wait is inserted at the falling edge of the eighth clock. condition for clearing (wtim0 = 0) condition for setting (wtim0 = 1) ? cleared by instruction ? reset ? set by instruction a cke 0 notes 1, 2 acknowledgment control 0 disable acknowledgment. 1 enable acknowledgment. during t he ninth clock period, the sda0 line is set to low level. condition for clearing (acke0 = 0) condition for setting (acke0 = 1) ? cleared by instruction ? reset ? set by instruction notes 1. this flag?s signal is invalid when iice0 = 0. 2. the set value is invalid during address transfer and if the code is not an extension code. when the device serves as a slave and the addresses match, an acknowledgment is generated regardless of the set value. chapter 12 serial interface iic0 user?s manual u17854ej6v0ud 451 figure 12-6. format of iic control register 0 (iicc0) (3/4) stt0 note start condition trigger 0 do not generate a start condition. 1 when bus is released (in stop mode): generate a start condition (for starting as master). when the scl0 line is high level, the sda0 line is changed from high level to low level and then the st art condition is generated. next, after the rated amount of time has elapsed, scl0 is changed to low level (wait state). when a third party is communicating: ? when communication reservation function is enabled (iicrsv = 0) functions as the start condition reservation flag. when set to 1, automatically generates a start condition after the bus is released. ? when communication reservation function is disabled (iicrsv = 1) stcf is set to 1 and information that is set (1) to stt0 is cleared. no start condition is generated. in the wait state (when master device): generates a restart condition after releasing the wait. cautions concerning set timing ? for master reception: cannot be set to 1 during transfer. can be set to 1 only in the waiting period when acke0 has been cleared to 0 and slave has been notified of final reception. ? for master transmission: a start condition cannot be generated normally during the acknowledge period. set to 1 during the wait period that follows output of the ninth clock. ? cannot be set to 1 at the same time as spt0. ? setting stt0 to 1 and then setting it again bef ore it is cleared to 0 is prohibited. condition for clearing (stt0 = 0) condition for setting (stt0 = 1) ? cleared by setting sst0 to 1 while communication reservation is prohibited. ? cleared by loss in arbitration ? cleared after start condition is generated by master device ? cleared by lrel0 = 1 (exit from communications) ? when iice0 = 0 (operation stop) ? reset ? set by instruction note this flag?s signal is invalid when iice0 = 0. remarks 1. bit 1 (stt0) becomes 0 when it is read after data setting. 2. iicrsv: bit 0 of iic flag register (iicf0) stcf: bit 7 of iic flag register (iicf0) chapter 12 serial interface iic0 user?s manual u17854ej6v0ud 452 figure 12-6. format of iic control register 0 (iicc0) (4/4) spt0 stop condition trigger 0 stop condition is not generated. 1 stop condition is generated (terminati on of master device?s transfer). after the sda0 line goes to low level, either set the scl0 line to high level or wait until it goes to high level. next, after the rated amount of time has elaps ed, the sda0 line changes from low level to high level and a stop condition is generated. cautions concerning set timing ? for master reception: cannot be set to 1 during transfer. can be set to 1 only in the waiting period when acke0 has been cleared to 0 and slave has been notified of final reception. ? for master transmission: a stop condition cannot be gene rated normally during the acknowledge period. therefore, set it during the wait period that follows output of the ninth clock. ? cannot be set to 1 at the same time as stt0. ? spt0 can be set to 1 only when in master mode note . ? when wtim0 has been cleared to 0, if spt0 is set to 1 dur ing the wait period that follows output of eight clocks, note that a stop condition will be generated during the high-le vel period of the ninth clock. wtim0 should be changed from 0 to 1 during the wait period following the out put of eight clocks, and spt0 should be set to 1 during the wait period that follows the output of the ninth clock. ? setting spt0 to 1 and then setting it again bef ore it is cleared to 0 is prohibited. condition for clearing (spt0 = 0) condition for setting (spt0 = 1) ? cleared by loss in arbitration ? automatically cleared after stop condition is detected ? cleared by lrel0 = 1 (exit from communications) ? when iice0 = 0 (operation stop) ? reset ? set by instruction note set spt0 to 1 only in master mode. however, spt0 must be set to 1 and a stop condition generated before the first stop condition is detect ed following the switch to the operation enabled status. caution when bit 3 (trc0) of iic status register 0 (iics0) is set to 1, wrel0 is set to 1 during the ninth clock and wait is cancele d, after which trc0 is cleared and the sda0 line is set to high impedance. remark bit 0 (spt0) becomes 0 when it is read after data setting. chapter 12 serial interface iic0 user?s manual u17854ej6v0ud 453 (3) iic status register 0 (iics0) this register indicates the status of i 2 c. iics0 is read by a 1-bit or 8-bit memory manipulation instruction only when stt0 = 1 and during the wait period. reset signal generation clea rs this register to 00h. figure 12-7. format of iic status register 0 (iics0) (1/3) address: fff56h after reset: 00h r symbol <7> <6> <5> <4> <3> <2> <1> <0> iics0 msts0 ald0 exc0 coi0 trc0 ackd0 std0 spd0 msts0 master device status 0 slave device status or communication standby status 1 master device communication status condition for clearing (msts0 = 0) condition for setting (msts0 = 1) ? when a stop condition is detected ? when ald0 = 1 (arbitration loss) ? cleared by lrel0 = 1 (exit from communications) ? when iice0 changes from 1 to 0 (operation stop) ? reset ? when a start condition is generated ald0 detection of arbitration loss 0 this status means either that there was no arbitr ation or that the arbitration result was a ?win?. 1 this status indicates the arbitration result was a ?loss?. msts0 is cleared. condition for clearing (ald0 = 0) condition for setting (ald0 = 1) ? automatically cleared after iics0 is read note ? when iice0 changes from 1 to 0 (operation stop) ? reset ? when the arbitration result is a ?loss?. exc0 detection of extension code reception 0 extension code was not received. 1 extension code was received. condition for clearing (exc0 = 0) condition for setting (exc0 = 1) ? when a start condition is detected ? when a stop condition is detected ? cleared by lrel0 = 1 (exit from communications) ? when iice0 changes from 1 to 0 (operation stop) ? reset ? when the higher four bits of the received address data is either ?0000? or ?1111? (set at the rising edge of the eighth clock). note this register is also cleared when a 1-bit memo ry manipulation instruction is executed for bits other than iics0. therefore, when using the ald0 bit, read the data of this bit before the data of the other bits. remark lrel0: bit 6 of iic control register 0 (iicc0) iice0: bit 7 of iic control register 0 (iicc0) chapter 12 serial interface iic0 user?s manual u17854ej6v0ud 454 figure 12-7. format of iic status register 0 (iics0) (2/3) coi0 detection of matching addresses 0 addresses do not match. 1 addresses match. condition for clearing (coi0 = 0) condition for setting (coi0 = 1) ? when a start condition is detected ? when a stop condition is detected ? cleared by lrel0 = 1 (exit from communications) ? when iice0 changes from 1 to 0 (operation stop) ? reset ? when the received address matches the local address (slave address register 0 (sva0)) (set at the rising edge of the eighth clock). trc0 detection of transmit/receive status 0 receive status (other than transmit status). the sda0 line is set for high impedance. 1 transmit status. the value in the so0 latch is enabled for output to the sda0 line (valid starting at the falling edge of the first byte?s ninth clock). condition for clearing (trc0 = 0) condition for setting (trc0 = 1) chapter 12 serial interface iic0 user?s manual u17854ej6v0ud 455 figure 12-7. format of iic status register 0 (iics0) (3/3) ackd0 detection of acknowledge (ack) 0 acknowledge was not detected. 1 acknowledge was detected. condition for clearing (ackd0 = 0) condition for setting (ackd0 = 1) ? when a stop condition is detected ? at the rising edge of the next byte?s first clock ? cleared by lrel0 = 1 (exit from communications) ? when iice0 changes from 1 to 0 (operation stop) ? reset ? after the sda0 line is set to low level at the rising edge of scl0?s ninth clock std0 detection of start condition 0 start condition was not detected. 1 start condition was detected. this indicates that the address transfer period is in effect. condition for clearing (std0 = 0) condition for setting (std0 = 1) ? when a stop condition is detected ? at the rising edge of the next byte?s first clock following address transfer ? cleared by lrel0 = 1 (exit from communications) ? when iice0 changes from 1 to 0 (operation stop) ? reset ? when a start condition is detected spd0 detection of stop condition 0 stop condition was not detected. 1 stop condition was detected. the master device ?s communication is terminated and the bus is released. condition for clearing (spd0 = 0) condition for setting (spd0 = 1) ? at the rising edge of the address transfer byte?s first clock following setting of th is bit and detection of a start condition ? when iice0 changes from 1 to 0 (operation stop) ? reset ? when a stop condition is detected remark lrel0: bit 6 of iic control register 0 (iicc0) iice0: bit 7 of iic control register 0 (iicc0) (4) iic flag register 0 (iicf0) this register sets the operation mode of i 2 c and indicates the status of the i 2 c bus. iicf0 can be set by a 1-bit or 8-bit memory manipulati on instruction. however, the stcf and iicbsy bits are read-only. the iicrsv bit can be used to enable/disabl e the communication reservation function. stcen can be used to set the initial value of the iicbsy bit. iicrsv and stcen can be written only when the operation of i 2 c is disabled (bit 7 (iice0) of iic control register 0 (iicc0) = 0). when operation is enabled, the iicf0 register can be read. reset signal generation clea rs this register to 00h. chapter 12 serial interface iic0 user?s manual u17854ej6v0ud 456 figure 12-8. format of iic flag register 0 (iicf0) <7> stcf condition for clearing (stcf = 0) ? cleared by stt0 = 1 ? when iice0 = 0 (operation stop) ? reset condition for setting (stcf = 1) ? generating start condition unsuccessful and stt0 cleared to 0 when communication reservation is disabled (iicrsv = 1). stcf 0 1 generate start condition start condition generation unsuccessful: clear stt0 flag stt0 clear flag iicf0 symbol <6> iicbsy 5 0 4 0 3 0 2 0 <1> stcen <0> iicrsv address: fff51h after reset: 00h r/w note condition for clearing (iicbsy = 0) ? detection of stop condition ? when iice0 = 0 (operation stop) ? reset condition for setting (iicbsy = 1) ? detection of start condition ? setting of iice0 when stcen = 0 iicbsy 0 1 bus release status (communication initial status when stcen = 1) bus communication status (communication initial status when stcen = 0) i 2 c bus status flag condition for clearing (stcen = 0) ? detection of start condition ? reset condition for setting (stcen = 1) ? set by instruction stcen 0 1 after operation is enabled (iice0 = 1), enable generation of a start condition upon detection of a stop condition. after operation is enabled (iice0 = 1), enable generation of a start condition without detecting a stop condition. initial start enable trigger condition for clearing (iicrsv = 0) ? cleared by instruction ? reset condition for setting (iicrsv = 1) ? set by instruction iicrsv 0 1 enable communication reservation disable communication reservation communication reservation function disable bit note bits 6 and 7 are read-only. cautions 1. write to stcen only when the operation is stopped (iice0 = 0). 2. as the bus release status (iicbsy = 0) is recognized regardless of the actual bus status when stcen = 1, when generating th e first start condition (stt0 = 1), it is necessary to verify that no third party comm unications are in progress in order to prevent such communications from being destroyed. 3. write to iicrsv only when th e operation is stopped (iice0 = 0). remark stt0: bit 1 of iic control register 0 (iicc0) iice0: bit 7 of iic control register 0 (iicc0) chapter 12 serial interface iic0 user?s manual u17854ej6v0ud 457 (5) iic clock select register 0 (iiccl0) this register is used to set the transfer clock for the i 2 c bus. iiccl0 can be set by a 1-bit or 8-bit memory manipulation instruction. however, the cld0 and dad0 bits are read-only. the smc0, cl01, and cl00 bits are set in comb ination with bit 0 (clx0) of iic function expansion register 0 (iicx0) (see 12.5.4 transfer clock setting method ). set iiccl0 while bit 7 (iice0) of iic control register 0 (iicc0) is 0. reset signal generation clea rs this register to 00h. figure 12-9. format of iic clock select register 0 (iiccl0) address: fff54h after reset: 00h r/w note symbol 7 6 <5> <4> <3> <2> 1 0 iiccl0 0 0 cld0 dad0 smc0 dfc0 cl01 cl00 cld0 detection of scl0 pin level (valid only when iice0 = 1) 0 the scl0 pin was detected at low level. 1 the scl0 pin was detected at high level. condition for clearing (cld0 = 0) condition for setting (cld0 = 1) ? when the scl0 pin is at low level ? when iice0 = 0 (operation stop) ? reset ? when the scl0 pin is at high level dad0 detection of sda0 pin level (valid only when iice0 = 1) 0 the sda0 pin was detected at low level. 1 the sda0 pin was detected at high level. condition for clearing (dad0 = 0) condition for setting (dad0 = 1) ? when the sda0 pin is at low level ? when iice0 = 0 (operation stop) ? reset ? when the sda0 pin is at high level smc0 operation mode switching 0 operates in standard mode. 1 operates in fast mode. dfc0 digital filter operation control 0 digital filter off. 1 digital filter on. digital filter can be used only in fast mode. in fast mode, the transfer clock does not vary regardless of dfc0 bit set (1)/clear (0). the digital filter is used for noise elimination in fast mode. note bits 4 and 5 are read-only. remark iice0: bit 7 of iic control register 0 (iicc0) chapter 12 serial interface iic0 user?s manual u17854ej6v0ud 458 (6) iic function expansi on register 0 (iicx0) this register sets the function expansion of i 2 c. iicx0 can be set by a 1-bit or 8-bit memory manipulation instruction. the clx0 bit is set in combination with bits 3, 1, and 0 (smc0, cl01, and cl00) of iic clock select register 0 (iiccl0) (see 12.5.4 transfer clock setting method ). set iicx0 while bit 7 (iice0) of iic control register 0 (iicc0) is 0. reset signal generation clears this register to 00h. figure 12-10. format of iic function expansion register 0 (iicx0) address: fff55h after reset: 00h r/w symbol 7 6 5 4 3 2 1 <0> iicx0 0 0 0 0 0 0 0 clx0 table 12-2. selection clock setting iicx0 iiccl0 bit 0 bit 3 bit 1 bit 0 clx0 smc0 cl01 cl00 transfer clock (f clk /m) settable selection clock (f clk ) range operation mode 0 0 0 0 f clk /88 4.00 mhz to 8.38 mhz 0 0 0 1 f clk /172 8.38 mhz to 16.76 mhz 0 0 1 0 f clk /344 16.76 mhz to 20 mhz 0 0 1 1 f clk /44 2.00 mhz to 4.19 mhz normal mode (smc0 bit = 0) 0 1 0 f clk /48 8.00 mhz to 16.76 mhz 0 1 1 0 f clk /96 16.00 mhz to 20 mhz 0 1 1 1 f clk /24 4.00 mhz to 8.38 mhz fast mode (smc0 bit = 1) 1 0 setting prohibited 1 1 0 f clk /48 8.00 mhz to 8.38 mhz 1 1 1 0 setting prohibited 16.00 mhz to 16.76 mhz 1 1 1 1 f clk /24 4.00 mhz to 4.19 mhz fast mode (smc0 bit = 1) caution determine the transf er clock frequency of i 2 c by using clx0, smc0, cl01, and cl00 before enabling the operation (by setting bit 7 (iice0) of iic control register 0 (iicc0) to 1). to change the transfer clock frequency, clear iice0 once to 0. remarks 1. : don?t care 2 . f clk : cpu/peripheral hardware clock frequency chapter 12 serial interface iic0 user?s manual u17854ej6v0ud 459 (7) port mode register 6 (pm6) this register sets the input/output of port 6 in 1-bit units. when using the p60/scl0 pin as clock i/o and the p61/ sda0 pin as serial data i/o, clear pm60 and pm61, and the output latches of p60 and p61 to 0. set iice0 (bit 7 of iic control register 0 (iicc0)) to 1 before setting the output mode because the p60/scl0 and p61/sda0 pins output a low level (fixed) when iice0 is 0. pm6 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation se ts this register to ffh. figure 12-11. format of port mode register 6 (pm6) pm60 pm61 pm62 pm63 1 1 1 1 p6n pin i/o mode selection (n = 0 to 3) output mode (output buffer on) input mode (output buffer off) pm6n 0 1 0 1 2 3 4 5 6 7 pm6 address: fff26h after reset: ffh r/w symbol chapter 12 serial interface iic0 user?s manual u17854ej6v0ud 460 12.4 i 2 c bus mode functions 12.4.1 pin configuration the serial clock pin (scl0) and serial data bus pin (sda0) are configured as follows. (1) scl0....... this pin is used for serial clock input and output. this pin is an n-ch open-drain output for both master and slave devices. input is schmitt input. (2) sda0 ...... this pin is used fo r serial data input and output. this pin is an n-ch open-drain output for both master and slave devices. input is schmitt input. since outputs from the serial clock line and the serial data bus line are n-ch open-drai n outputs, an external pull-up resistor is required. figure 12-12. pin configuration diagram master device clock output (clock input) data output data input v ss v ss scl0 sda0 v dd v dd (clock output) clock input data output data input v ss v ss slave device scl0 sda0 chapter 12 serial interface iic0 user?s manual u17854ej6v0ud 461 12.5 i 2 c bus definitions and control methods the following section describes the i 2 c bus?s serial data communication format and the signals used by the i 2 c bus. figure 12-13 shows the transfer timing for the ?start conditi on?, ?address?, ?data?, and ?st op condition? output via the i 2 c bus?s serial data bus. figure 12-13. i 2 c bus serial data transfer timing scl0 sda0 start condition address r/w ack data 1-7 8 9 1-8 ack data ack stop condition 9 1-8 9 the master device generates the start c ondition, slave address, and stop condition. the acknowledge (ack) can be generated by either the master or slave device (normally, it is output by the device that receives 8-bit data). the serial clock (scl0) is continuously output by the master device. howeve r, in the slave device, the scl0?s low level period can be extended and a wait can be inserted. 12.5.1 start conditions a start condition is met when the scl0 pin is at high level and the sda0 pin changes from high level to low level. the start conditions for the scl0 pin and sda0 pin are signal s that the master device gener ates to the slave device when starting a serial transfer. when the device is us ed as a slave, start conditions can be detected. figure 12-14. start conditions scl0 sda0 h a start condition is output when bit 1 (stt0) of iic control r egister 0 (iicc0) is set (to 1) after a stop condition has been detected (spd0: bit 0 = 1 in iic status register 0 (iic s0)). when a start condition is detected, bit 1 (std0) of iics0 is set (to 1). chapter 12 serial interface iic0 user?s manual u17854ej6v0ud 462 12.5.2 addresses the address is defined by the 7 bits of data that follow the start condition. an address is a 7-bit data segment that is output in order to select one of t he slave devices that are connected to the master device via the bus lines. therefore, each slave device connected via the bus lines must have a unique address. the slave devices include hardware t hat detects the start condition and c hecks whether or not the 7-bit address data matches the data values stored in slave address register 0 (sva0). if the address data matches the sva0 values, the slave device is selected and communicates with the master device until th e master device generates a start condition or stop condition. figure 12-15. address scl0 sda0 intiic0 123456789 a6 a5 a4 a3 a2 a1 a0 r/w address note note intiic0 is not issued if data other than a local address or extension code is received during slave device operation. the slave address and the eighth bit, which spec ifies the transfer direction as described in 12.5.3 transfer direction specification below, are together written to iic shift r egister 0 (iic0) and are then output. received addresses are written to iic0. the slave address is assigned to the higher 7 bits of iic0. 12.5.3 transfer di rection specification in addition to the 7-bit address data, the master device s ends 1 bit that specifies t he transfer direction. when this transfer direction specificati on bit has a value of ?0?, it indicates that the master device is transmitting data to a slave device. when the transfer direction specification bit has a value of ?1?, it indicates that the master device is receiving data from a slave device. figure 12-16. transfer direction specification scl0 sda0 intiic0 123456789 a6 a5 a4 a3 a2 a1 a0 r/w transfer direction specification note note intiic0 is not issued if data other than a local address or extension code is received during slave device operation. chapter 12 serial interface iic0 user?s manual u17854ej6v0ud 463 12.5.4 transfer clock setting method (1) selection clock setting method on the master side the i 2 c transfer clock frequency (f scl ) is calculated using the following expression. f scl = 1/(m t + t r + t f ) m = 24, 44, 48, 88, 96, 172, 344 (see table 12-3 selection clock setting ) t: 1/f clk t r : scl0 rise time t f : scl0 fall time for example, the i 2 c transfer clock frequency (f scl ) when f clk = 4.19 mhz, m = 88, t r = 200 ns, and t f = 50 ns is calculated using following expression. f scl = 1/(88 238.7 ns + 200 ns + 50 ns) ? 47.0 khz m t + t r + t f m/2 t m/2 t t f t r scl0 scl0 inversion scl0 inversion scl0 inversion the selection clock is set using a combination of bits 3, 1, and 0 (smc0, cl01, and cl00) of iic clock select register 0 (iiccl0) and bit 0 (clx0) of iic function expansion register 0 (iicx0). (2) selection clock setting method on the slave side to use as slave, set the bits 3, 1, and 0 (smc0, cl01, cl00) of the iic clock selection register (iicl0) and the bit 0 (clx0) of the iic function expansion register 0 (iicx0) according to the f clk (selectable selection clock range) and iic operation mode (normal or fast ) as defined in table 12-3. selection clock setting . chapter 12 serial interface iic0 user?s manual u17854ej6v0ud 464 table 12-3. selection clock setting iicx0 iiccl0 bit 0 bit 3 bit 1 bit 0 clx0 smc0 cl01 cl00 transfer clock (f clk /m) settable selection clock (f clk ) range operation mode 0 0 0 0 f clk /88 4.00 mhz to 8.38 mhz 0 0 0 1 f clk /172 8.38 mhz to 16.76 mhz 0 0 1 0 f clk /344 16.76 mhz to 20 mhz 0 0 1 1 f clk /44 2.00 mhz to 4.19 mhz normal mode (smc0 bit = 0) 0 1 0 f clk /48 8.00 mhz to 16.76 mhz 0 1 1 0 f clk /96 16.00 mhz to 20 mhz 0 1 1 1 f clk /24 4.00 mhz to 8.38 mhz fast mode (smc0 bit = 1) 1 0 setting prohibited 1 1 0 f clk /48 8.00 mhz to 8.38 mhz 1 1 1 0 setting prohibited 16.00 mhz to 16.76 mhz 1 1 1 1 f clk /24 4.00 mhz to 4.19 mhz fast mode (smc0 bit = 1) caution determine the transf er clock frequency of i 2 c by using clx0, smc0, cl01, and cl00 before enabling the operation (by setting bit 7 (iice0) of iic control register 0 (iicc0) to 1). to change the transfer clock frequency, clear iice0 once to 0. remarks 1. : don?t care 2 . f clk : cpu/peripheral hardware clock frequency 12.5.5 acknowledge (ack) ack is used to check the status of serial data at the transmission and reception sides. the reception side returns ack each time it has received 8-bit data. the transmission side usually receives ack after transmitting 8-bit data. when ack is returned from the reception side, it is assumed that reception has been correctly performed and processi ng is continued. whether ack has been detected can be checked by using bit 2 (ack d0) of iic status register 0 (iics0). when the master receives the last dat a item, it does not return ack and instead generates a stop condition. if a slave does not return ack after receiving data, the ma ster outputs a stop condition or restart condition and stops transmission. if ack is not returned, the possible causes are as follows. <1> reception was not performed normally. <2> the final data item was received. <3> the reception side specified by the address does not exist. to generate ack, the reception side makes the sda0 line low at the ninth clock (indicating normal reception). automatic generation of ack is enabled by setting bit 2 (ac ke0) of iic control register 0 (iicc0) to 1. bit 3 (trc0) of the iics0 register is set by the data of the eighth bit that follows 7-bit addre ss information. usually, set acke0 to 1 for reception (trc0 = 0). if a slave can receive no more data during reception (trc 0 = 0) or does not require the next data item, then the slave must inform the master, by clearing acke0 to 0, that it will not receive any more data. when the master does not require the next data item during reception (trc0 = 0), it must clear acke0 to 0 so that ack is not generated. in this way, the master informs a slave at the transmission side that it does not require any more data (transmission will be stopped). chapter 12 serial interface iic0 user?s manual u17854ej6v0ud 465 figure 12-17. ack scl0 sda0 123456789 a6 a5 a4 a3 a2 a1 a0 r/w ack when the local address is received, ac k is automatically generated, regardl ess of the value of acke0. when an address other than that of t he local address is received, ack is not generated (nack). when an extension code is received, ack is gen erated if acke0 is set to 1 in advance. how ack is generated when data is received differs as follows depending on the setting of the wait timing. ? when 8-clock wait state is selected (b it 3 (wtim0) of iicc0 register = 0): by setting acke0 to 1 before releasing the wait state, ack is generated at the falling edge of the eighth clock of the scl0 pin. ? when 9-clock wait state is selected (b it 3 (wtim0) of iicc0 register = 1): ack is generated by setting acke0 to 1 in advance. chapter 12 serial interface iic0 user?s manual u17854ej6v0ud 466 12.5.6 stop condition when the scl0 pin is at high level, changing the sda0 pin from low level to high level generates a stop condition. a stop condition is a signal that the master device generates to the slave device when serial transfer has been completed. when the device is used as a slave, stop conditions can be detected. figure 12-18. stop condition scl0 sda0 h a stop condition is generated when bit 0 (spt0) of iic c ontrol register 0 (iicc0) is set to 1. when the stop condition is detected, bit 0 (spd0) of iic status register 0 (iics0) is se t to 1 and intiic0 is generated when bit 4 (spie0) of iicc0 is set to 1. chapter 12 serial interface iic0 user?s manual u17854ej6v0ud 467 12.5.7 wait the wait is used to notify the communication partner that a device (master or slave) is preparing to transmit or receive data (i.e., is in a wait state). setting the scl0 pin to low level notifi es the communication partner of the wait state. when wait state has been canceled for both the master and slave devices, the next data transfer can begin. figure 12-19. wait (1/2) (1) when master device has a nine-clock wait and slave device has an eight-clock wait (master transmits, slave receives, and acke0 = 1) master iic0 scl0 slave iic0 scl0 acke0 transfer lines scl0 sda0 6789 123 master returns to high impedance but slave is in wait state (low level). wait after output of ninth clock iic0 data write (cancel wait) wait after output of eighth clock wait from slave wait from master ffh is written to iic0 or wrel0 is set to 1 678 9 123 d2 d1 d0 d7 d6 d5 ack h chapter 12 serial interface iic0 user?s manual u17854ej6v0ud 468 figure 12-19. wait (2/2) (2) when master and slave devices both have a nine-clock wait (master transmits, slave receives, and acke0 = 1) master iic0 scl0 slave iic0 scl0 acke0 transfer lines scl0 sda0 h 6789 1 23 master and slave both wait after output of ninth clock wait from master and slave wait from slave iic0 data write (cancel wait) ffh is written to iic0 or wrel0 is set to 1 6789 123 d2 d1 d0 ack d7 d6 d5 generate according to previously set acke0 value remark acke0: bit 2 of iic control register 0 (iicc0) wrel0: bit 5 of iic control register 0 (iicc0) a wait may be automatically generated depending on the setting of bit 3 (wtim0) of iic control register 0 (iicc0). normally, the receiving side cancels the wait state when bit 5 (wrel0) of iicc0 is set to 1 or when ffh is written to iic shift register 0 (iic0), and the transmitting side cancels the wait state when data is written to iic0. the master device can also cancel the wait state via either of the following methods. ? by setting bit 1 (stt0) of iicc0 to 1 ? by setting bit 0 (spt0) of iicc0 to 1 chapter 12 serial interface iic0 user?s manual u17854ej6v0ud 469 12.5.8 canceling wait the i 2 c usually cancels a wait stat e by the following processing. ? writing data to iic shift register 0 (iic0) ? setting bit 5 (wrel0) of iic control register 0 (iicc0) (canceling wait) ? setting bit 1 (stt0) of iic0 register (generating start condition) note ? setting bit 0 (spt0) of iic0 regi ster (generating stop condition) note note master only when the above wait canceling pr ocessing is executed, the i 2 c cancels the wait state and communication is resumed. to cancel a wait state and transmit data (incl uding addresses), write the data to iic0. to receive data after canceling a wait state, or to comple te data transmission, set bit 5 (wrel0) of the iic0 control register 0 (iicc0) to 1. to generate a restart condition after canceling a wait state, set bit 1 (stt0) of iicc0 to 1. to generate a stop condition after canceling a wait state, set bit 0 (spt0) of iicc0 to 1. execute the canceling processing only once for one wait state. if, for example, data is written to iic0 after canceling a wa it state by setting wrel0 to 1, an incorrect value may be output to sda0 because the timing for changing the sd a0 line conflicts with the timing for writing iic0. in addition to the above, communication is stopped if iic e0 is cleared to 0 when communication has been aborted, so that the wait st ate can be canceled. if the i 2 c bus has deadlocked due to noise, processing is saved from communication by setting bit 6 (lrel0) of iicc0, so that the wait state can be canceled. chapter 12 serial interface iic0 user?s manual u17854ej6v0ud 470 12.5.9 interrupt request (intiic0) generation timing and wait control the setting of bit 3 (wtim0) of iic c ontrol register 0 (iicc0) determines t he timing by which intiic0 is generated and the corresponding wait control, as shown in table 12-4. table 12-4. intiic0 generation timing and wait control during slave device operation during master device operation wtim0 address data reception data transmission address data reception data transmission 0 9 notes 1, 2 8 note 2 8 note 2 9 8 8 1 9 notes 1, 2 9 note 2 9 note 2 9 9 9 notes 1. the slave device?s intiic0 signal and wait period occu rs at the falling edge of the ninth clock only when there is a match with the address set to slave address register 0 (sva0). at this point, ack is generated regardless of the val ue set to iicc0?s bit 2 (acke0). for a slave device that has received an extension code, intiic0 occu rs at the falling edge of the eighth clock. however, if the address does not match after rest art, intiic0 is generated at the falling edge of the 9th clock, but wait does not occur. 2. if the received address does not match the contents of slave address register 0 (sva0) and extension code is not received, neither intiic0 nor a wait occurs. remark the numbers in the table indicate the number of t he serial clock?s clock signals. interrupt requests and wait control are both synchronized with t he falling edge of these clock signals. (1) during address transmission/reception ? slave device operation: interrupt and wait timi ng are determined depending on the conditions described in notes 1 and 2 above, regardless of the wtim0 bit. ? master device operation: interrupt and wait timing oc cur at the falling edge of the ninth clock regardless of the wtim0 bit. (2) during data reception ? master/slave device operation: interrupt and wait timing are determined according to the wtim0 bit. (3) during data transmission ? master/slave device operation: interrupt and wait timing are determined according to the wtim0 bit. (4) wait cancellation method the four wait cancellation methods are as follows. ? writing data to iic shift register 0 (iic0) ? setting bit 5 (wrel0) of iic control register 0 (iicc0) (canceling wait) ? setting bit 1 (stt0) of iic0 register (generating start condition) note ? setting bit 0 (spt0) of iic0 regi ster (generating stop condition) note note master only. when an 8-clock wait has been selected (wtim0 = 0) , the presence/absence of ack generation must be determined prior to wait cancellation. (5) stop condition detection intiic0 is generated when a stop condit ion is detected (only when spie0 = 1). chapter 12 serial interface iic0 user?s manual u17854ej6v0ud 471 12.5.10 address match detection method in i 2 c bus mode, the master device can se lect a particular slave device by transmitting the corresponding slave address. address match can be detected automatical ly by hardware. an interrupt r equest (intiic0) occurs when a local address has been set to slave address register 0 (sva0) and when the address set to sva0 matches the slave address sent by the master device, or when an extension code has been received. 12.5.11 error detection in i 2 c bus mode, the status of t he serial data bus (sda0) during data transmi ssion is captured by iic shift register 0 (iic0) of the transmitting device, so the iic0 data prior to transmission can be compared with the transmitted iic0 data to enable detection of transmission errors. a transmission error is judged as having occurred when the compared data values do not match. 12.5.12 extension code (1) when the higher 4 bits of the receive address are ei ther ?0000? or ?1111?, the extension code reception flag (exc0) is set to 1 for extension code reception and an interrupt request (intiic0) is issued at the falling edge of the eighth clock. the local address stored in slave address register 0 (sva0) is not affected. (2) if ?11110 0? is set to sva0 by a 10-bit address transfer and ?11110 0? is transferred from the master device, the results are as follows. note that intiic0 occurs at the falling edge of the eighth clock. ? higher four bits of data match: exc0 = 1 ? seven bits of data match: coi0 = 1 remark exc0: bit 5 of iic status register 0 (iics0) coi0: bit 4 of iic status register 0 (iics0) (3) since the processing after the interrupt request occurs differs according to the data that follows the extension code, such processing is performed by software. if the extension code is received while a slave device is operating, then the slave device is participating in communication even if its address does not match. for example, after the extension code is received, if you do not wish to operate the target device as a slave device, set bit 6 (lrel0) of the iic control register 0 (iicc0) to 1 to set the standby mode for the next communication operation. table 12-5. extension code bit definitions slave address r/w bit description 0 0 0 0 0 0 0 0 general call address 0 0 0 0 0 0 0 1 start byte 0 0 0 0 0 0 1 c-bus address 0 0 0 0 0 1 0 address that is reserved for different bus format 1 1 1 1 0 x x 10-bit slave address specification chapter 12 serial interface iic0 user?s manual u17854ej6v0ud 472 12.5.13 arbitration when several master devices simultaneously generate a star t condition (when stt0 is set to 1 before std0 is set to 1), communication among the master devices is perform ed as the number of clocks are adjusted until the data differs. this kind of operation is called arbitration. when one of the master devices loses in arbitration, an arbitration loss flag (ald 0) in iic status register 0 (iics0) is set (1) via the timing by which the arbitration loss oc curred, and the scl0 and sda0 lines are both set to high impedance, which releases the bus. the arbitration loss is detected based on the timing of the next interrupt reques t (the eighth or ninth clock, when a stop condition is detected, et c.) and the ald0 = 1 setting that has been made by software. for details of interrupt request timing, see 12.5.9 interrupt request (intiic 0) generation timing and wait control . remark std0: bit 1 of iic status register 0 (iics0) stt0: bit 1 of iic control register 0 (iicc0) figure 12-20. arbitration timing example scl0 sda0 scl0 sda0 scl0 sda0 hi-z hi-z master 1 loses arbitration master 1 master 2 transfer lines chapter 12 serial interface iic0 user?s manual u17854ej6v0ud 473 table 12-6. status during arbitration and interrupt request generation timing status during arbitration interrupt request generation timing during address transmission read/write data after address transmission during extension code transmission read/write data after extension code transmission during data transmission during ack transfer period after data transmission when restart condition is detected during data transfer at falling edge of eighth or ninth clock following byte transfer note 1 when stop condition is detected during data transf er when stop condition is generated (when spie0 = 1) note 2 when data is at low level while attempting to generate a restart condition at falling edge of eighth or ninth clock following byte transfer note 1 when stop condition is detected while attempting to generate a restart condition when stop condition is generated (when spie0 = 1) note 2 when data is at low level while attempting to generate a stop condition when scl0 is at low level while attempting to generate a restart condition at falling edge of eighth or ninth clock following byte transfer note 1 notes 1. when wtim0 (bit 3 of iic control register 0 (iicc0 )) = 1, an interrupt request occurs at the falling edge of the ninth clock. when wtim0 = 0 and the extension code?s slave address is received, an interrupt request occurs at the falling edge of the eighth clock. 2. when there is a chance that ar bitration will occur, set spie0 = 1 for master device operation. remark spie0: bit 4 of iic control register 0 (iicc0) 12.5.14 wakeup function the i 2 c bus slave function is a function that generates an interrupt request si gnal (intiic0) when a local address and extension code have been received. this function makes processing more efficient by pr eventing unnecessary intiic0 signal from occurring when addresses do not match. when a start condition is detected, wake up standby mode is set. this wakeup standby mode is in effect while addresses are transmitted due to the possibility that an ar bitration loss may change the master device (which has generated a start condition) to a slave device. however, when a stop condition is detecte d, bit 4 (spie0) of iic control register 0 (iicc0) is set regardless of the wakeup function, and this determines whether interrupt requests are enabled or disabled. chapter 12 serial interface iic0 user?s manual u17854ej6v0ud 474 12.5.15 communication reservation (1) when communication reservation func tion is enabled (bit 0 (iicrsv) of iic flag register 0 (iicf0) = 0) to start master device communications when not curr ently using a bus, a communication reservation can be made to enable transmission of a start condition when the bus is released. there are two modes under which the bus is not used. ? when arbitration results in neither master nor slave operation ? when an extension code is received and slave operation is disabled (ack is not returned and the bus was released when bit 6 (lrel0) of iic control register 0 (iicc0) was set to 1). if bit 1 (stt0) of iicc0 is set to 1 while the bus is not used (after a stop condition is detected), a start condition is automatically generated and wait state is set. if an address is written to iic shift register 0 (iic0) afte r bit 4 (spie0) of iicc0 was set to 1, and it was detected by generation of an interrupt request signal (intiic0) that the bus was released (detection of the stop condition), then the device automatically starts communi cation as the master. data written to iic0 before the stop condition is det ected is invalid. when stt0 has been set to 1, the operation mode (as st art condition or as communication reservation) is determined according to the bus status. ? if the bus has been released ........................................ a start c ondition is generated ? if the bus has not been released (stand by mode)......... communication reservation check whether the communication reservation operates or not by using msts0 (bit 7 of iic status register 0 (iics0)) after stt0 is set to 1 and the wait time elapses. the wait periods, which should be set via software, are listed in table 12-6. table 12-7. wait periods clx0 smc0 cl01 cl00 wait period 0 0 0 0 43 clocks 0 0 0 1 85 clocks 0 0 1 0 101 clocks 0 0 1 1 23 clocks 0 1 0 0 0 1 0 1 27 clocks 0 1 1 0 51 clocks 0 1 1 1 1 1 0 0 1 1 0 1 15 clocks 1 1 1 0 27 clocks 1 1 1 1 9 clocks figure 12-21 shows the communication reservation timing. chapter 12 serial interface iic0 user?s manual u17854ej6v0ud 475 figure 12-21. communication reservation timing 2 13456 2 1 3456 789 scl0 sda0 program processing hardware processing write to iic0 set spd0 and intiic0 stt0 = 1 communi- cation reservation set std0 generate by master device with bus mastership remark iic0: iic shift register 0 stt0: bit 1 of iic control register 0 (iicc0) std0: bit 1 of iic status register 0 (iics0) spd0: bit 0 of iic status register 0 (iics0) communication reservations are accepted via the following timing. after bit 1 (std0) of iic status register 0 (iics0) is set to 1, a communication reservation can be made by setting bit 1 (stt0) of iic control register 0 (iicc0) to 1 before a stop condition is detected. figure 12-22. timing for accep ting communication reservations scl0 sda0 std0 spd0 standby mode figure 12-23 shows the communication reservation protocol. chapter 12 serial interface iic0 user?s manual u17854ej6v0ud 476 figure 12-23. communication reservation protocol di set1 stt0 define communication reservation wait msts0 = 0? (communication reservation) note yes no (generate start condition) cancel communication reservation mov iic0, # h ei sets stt0 flag (communication reservation) defines that communication reservation is in effect (defines and sets user flag to any part of ram) secures wait period set by software (see table 12-7 ). confirmation of communication reservation clear user flag iic0 write operation note the communication reservation operation executes a write to iic shift register 0 (iic0) when a stop condition interrupt request occurs. remark stt0: bit 1 of iic control register 0 (iicc0) msts0: bit 7 of iic status register 0 (iics0) iic0: iic shift register 0 chapter 12 serial interface iic0 user?s manual u17854ej6v0ud 477 (2) when communication reservation function is disabled (b it 0 (iicrsv) of iic flag register 0 (iicf0) = 1) when bit 1 (stt0) of iic control register 0 (iicc0) is se t to 1 when the bus is not used in a communication during bus communication, this request is rejected and a start condition is not generated. the following two statuses are included in the st atus where bus is not used. ? when arbitration results in neither master nor slave operation ? when an extension code is received and slave operation is disabled (ack is not returned and the bus was released when bit 6 (lrel0) of iicc0 was set to 1) to confirm whether the start condition was generated or request was rejected, check stcf (bit 7 of iicf0). it takes up to 5 clocks until stcf is set to 1 after setting s tt0 = 1. therefore, secure the time by software. chapter 12 serial interface iic0 user?s manual u17854ej6v0ud 478 12.5.16 cautions (1) when stcen (bit 1 of iic flag register 0 (iicf0)) = 0 immediately after i 2 c operation is enabled (iice0 = 1), the bus comm unication status (iicbsy (bit 6 of iicf0) = 1) is recognized regardless of the actual bus status. when changing from a mode in which no stop condition has been detected to a master device communication mo de, first generate a stop condition to release the bus, then perform master device communication. when using multiple masters, it is not possible to per form master device communication when the bus has not been released (when a stop condition has not been detected). use the following sequence for generating a stop condition. <1> set iic clock select register 0 (iiccl0). <2> set bit 7 (iice0) of iic c ontrol register 0 (iicc0) to 1. <3> set bit 0 (spt0) of iicc0 to 1. (2) when stcen = 1 immediately after i 2 c operation is enabled (iice0 = 1), the bus released status (iicbsy = 0) is recognized regardless of the actual bus status. to generate the first start condition (stt0 (bit 1 of iic control register 0 (iicc0)) = 1), it is necessary to confirm that the bus has been releas ed, so as to not disturb other communications. (3) if other i 2 c communications are already in progress if i 2 c operation is enabled and the device participates in communication already in progress when the sda0 pin is low and the scl0 pin is high, the macro of i 2 c recognizes that the sda0 pin has gone low (detects a start condition). if the value on the bus at this time ca n be recognized as an extension code, ack is returned, but this interferes with other i 2 c communications. to avoid this, start i 2 c in the following sequence. <1> clear bit 4 (spie0) of iicc0 to 0 to disable gener ation of an interrupt request signal (intiic0) when the stop condition is detected. <2> set bit 7 (iice0) of iicc0 to 1 to enable the operation of i 2 c. <3> wait for detection of the start condition. <4> set bit 6 (lrel0) of iicc0 to 1 before ack is returned (4 to 80 clocks after setting iice0 to 1), to forcibly disable detection. (4) determine the transfer clock frequency by using smc0, cl 01, cl00 (bits 3, 1, and 0 of iicl0), and clx0 (bit 0 of iicx0) before enabling the operation (iice0 = 1). to change the transfer clock frequency, clear iice0 to 0 once. (5) setting stt0 and spt0 (bits 1 and 0 of iicc0) again after they are set and before they are cleared to 0 is prohibited. (6) when transmission is reserved, set spie0 (bit 4 of iic l0) to 1 so that an interrupt request is generated when the stop condition is detected. transfe r is started when communication data is written to iic0 after the interrupt request is generated. unless the interrupt is generat ed when the stop condition is detected, the device stops in the wait state because the interrupt request is not generated when communicati on is started. however, it is not necessary to set spie0 to 1 when msts0 (bit 7 of iics0) is detected by software. chapter 12 serial interface iic0 user?s manual u17854ej6v0ud 479 12.5.17 communication operations the following shows three operatio n procedures with the flowchart. (1) master operation in single master system the flowchart when using the 78k0r/ke3 as the ma ster in a single master system is shown below. this flowchart is broadly divided into the initial setti ngs and communication processing. execute the initial settings at startup. if communication with the slave is required, prepare the communication and then execute communication processing. (2) master operation in multimaster system in the i 2 c bus multimaster system, whethe r the bus is released or us ed cannot be ju dged by the i 2 c bus specifications when the bus takes part in a communication. here, when data and clock are at a high level for a certain period (1 frame), the 78k0r/ke3 takes part in a communication with bus released state. this flowchart is broadly divided into the initial setti ngs, communication waiting, and communication processing. the processing when the 78k0r/ke3 looses in arbitratio n and is specified as the slave is omitted here, and only the processing as the master is shown. execute the initial settings at startup to take part in a communication. then, wait for the communication request as the master or wait fo r the specification as the slave. the actual communication is performed in the communication processing, and it supports the transmission/reception with the slave and the arbitration with other masters. (3) slave operation an example of when the 78k0r/ke3 is used as the i 2 c bus slave is shown below. when used as the slave, operation is st arted by an interrupt. execute the in itial settings at startup, then wait for the intiic0 interrupt occurrence (communication waiting). when an intiic0 interrupt occurs, the communication status is judged and its result is passed as a flag over to the main processing. by checking the flags, necessary communication processing is performed. chapter 12 serial interface iic0 user?s manual u17854ej6v0ud 480 (1) master operation in single-master system figure 12-24. master operation in single-master system spt0 = 1 spt0 = 1 wrel0 = 1 start end acke0 = 0 wtim0 = wrel0 = 1 no no yes no no no yes yes yes yes stcen = 1? acke0 = 1 wtim0 = 0 trc0 = 1? ackd0 = 1? ackd0 = 1? no yes no yes yes no yes no yes no yes no yes no stt0 = 1 iicx0 0xh iiccl0 xxh iicf0 0xh setting stcen, iicrsv = 0 iicc0 xxh acke0 = wtim0 = spie0 = 1 iice0 = 1 setting port initializing i 2 c bus note sva0 xxh writing iic0 writing iic0 reading iic0 intiic0 interrupt occurs? end of transfer? end of transfer? restart? sets each pin in the i 2 c mode (see 12.3 (7) port mode register 6 (pm6) ). selects a transfer clock. sets a local address. sets a start condition. prepares for starting communication (generates a start condition). starts communication (specifies an address and transfer direction). waits for detection of acknowledge. waits for data transmission. starts transmission. communication processing initial setting starts reception. waits for data reception. intiic0 interrupt occurs? waits for detection of acknowledge. prepares for starting communication (generates a stop condition). waits for detection of the stop condition. intiic0 interrupt occurs? intiic0 interrupt occurs? intiic0 interrupt occurs? note release (scl0 and sda0 pins = high level) the i 2 c bus in conformance with t he specifications of the product that is communicating. if eeprom is outputting a low level to the sda0 pin, for example, set the scl0 pin in the output port mode, and output a clock pulse from the output port until the sda0 pin is constantly at high level. remark conform to the specifications of the product that is communicating, with respect to the transmission and reception formats. chapter 12 serial interface iic0 user?s manual u17854ej6v0ud 481 (2) master operation in multi-master system figure 12-25. master operation in multi-master system (1/3) iicx0 0xh iiccl0 xxh iicf0 0xh setting stcen and iicrsv iicc0 xxh acke0 = wtim0 = spie0 = 1 iice0 = 1 setting port spt0 = 1 sva0 xxh spie0 = 1 start slave operation slave operation releases the bus for a specific period. bus status is being checked. yes checking bus status note master operation starts? enables reserving communication. disables reserving communication. spd0 = 1? stcen = 1? iicrsv = 0? a sets each pin in the i 2 c mode (see 12.3 (7) port mode register 6 (pm6) ). selects a transfer clock. sets a local address. sets a start condition. (communication start request) (no communication start request) ? waiting to be specified as a slave by other master ? waiting for a communication start request (depends on user program) prepares for starting communication (generates a stop condition). waits for detection of the stop condition. no yes yes no intiic0 interrupt occurs? intiic0 interrupt occurs? yes no yes no spd0 = 1? yes no slave operation no intiic0 interrupt occurs? yes no 1 b spie0 = 0 yes no waits for a communication request. waits for a communication initial setting note confirm that the bus is released (cld0 bit = 1, dad0 bi t = 1) for a specific period (for example, for a period of one frame). if the sda0 pin is constantly at low level, decide whether to release the i 2 c bus (scl0 and sda0 pins = high level) in conformance with the s pecifications of the produc t that is communicating. chapter 12 serial interface iic0 user?s manual u17854ej6v0ud 482 figure 12-25. master operation in multi-master system (2/3) stt0 = 1 wait slave operation yes msts0 = 1? exc0 = 1 or coi0 =1? prepares for starting communication (generates a start condition). secure wait time by software (see table 12-7 ). waits for bus release (communication being reserved). wait state after stop condition was detected and start condition was generated by the communication reservation function. no intiic0 interrupt occurs? yes yes no no a c stt0 = 1 wait slave operation yes iicbsy = 0? exc0 = 1 or coi0 =1? prepares for starting communication (generates a start condition). disables reserving communication. enables reserving communication. secure wait time by software (see table 12-7 ). waits for bus release detects a stop condition. no no intiic0 interrupt occurs? yes yes no yes stcf = 0? no b d c d communication processing communication processing chapter 12 serial interface iic0 user?s manual u17854ej6v0ud 483 figure 12-25. master operation in multi-master system (3/3) writing iic0 wtim0 = 1 wrel0 = 1 reading iic0 acke0 = 1 wtim0 = 0 wtim0 = wrel0 = 1 acke0 = 0 writing iic0 yes trc0 = 1? restart? msts0 = 1? starts communication (specifies an address and transfer direction). starts transmission. no yes waits for data reception. starts reception. yes no intiic0 i nterrupt occurs? yes no transfer end? waits for detection of ack. yes no intiic0 i nterrupt occurs? waits for data transmission. does not participate in communication. yes no intiic0 i nterrupt occurs? no yes ackd0 = 1? no yes no c 2 yes msts0 = 1? no yes transfer end? no yes ackd0 = 1? no 2 yes msts0 = 1? no 2 waits for detection of ack. yes no intiic0 i nterrupt occurs? yes msts0 = 1? no c 2 yes exc0 = 1 or coi0 = 1? no 1 2 spt0 = 1 stt0 = 1 slave operation end communication processing communication processing remarks 1. conform to the specifications of the product that is communicatin g, with respect to the transmission and reception formats. 2. to use the device as a master in a multi-master system, read the msts0 bit each time interrupt intiic0 has occurred to check the arbitration result. 3. to use the device as a slave in a multi-master system, check the status by using the iics0 and iicf0 registers each time interrupt intiic0 has occurr ed, and determine the processing to be performed next. chapter 12 serial interface iic0 user?s manual u17854ej6v0ud 484 (3) slave operation the processing procedure of the slave operation is as follows. basically, the slave operation is event-driven. therefor e, processing by the intiic0 interrupt (processing that must substantially change the operation status such as de tection of a stop condition during communication) is necessary. in the following explanation, it is assumed that the extension code is not supported for data communication. it is also assumed that the intiic0 interrupt servicing only performs status transition pr ocessing, and that actual data communication is performed by the main processing. iic0 interrupt servicing main processing intiic0 flag setting data setting therefore, data communication processing is perfo rmed by preparing the following three flags and passing them to the main processing instead of intiic0. <1> communication mode flag this flag indicates the following two communication statuses. ? clear mode: status in which data communication is not performed ? communication mode: status in which data comm unication is performed (from valid address detection to stop condition detection, no detec tion of ack from master, address mismatch) <2> ready flag this flag indicates that data communication is enabled. its function is the same as the intiic0 interrupt for ordinary data communication. this flag is set by interrupt servicing and cleared by the main processing. clear this flag by interrupt servicing when communication is started. however, the ready flag is not set by interrupt servicing when the first data is transmitted. therefore, the first data is transmitted without the flag being cleared (an address match is interpreted as a request for the next data). <3> communication direction flag this flag indicates the direction of communic ation. its value is the same as trc0. chapter 12 serial interface iic0 user?s manual u17854ej6v0ud 485 the main processing of the slave operation is explained next. start serial interface iic0 and wait until communication is enabled. when communication is enabled, execute communication by using the communication mode flag an d ready flag (processing of the stop condition and start condition is performed by an interrupt. here, check the status by using the flags). the transmission operation is repeated until the master no longer returns ack. if ack is not returned from the master, communication is completed. for reception, the necessary amount of data is received. when communication is completed, ack is not returned as the next data. after that, the master generat es a stop condition or restart condition. exit from the communication status occurs in this way. figure 12-26. slave operation flowchart (1) yes yes yes yes yes yes yes no no no no no no wrel0 = 1 ackd0 = 1? no yes no yes no start communication mode flag = 1? communication mode flag = 1? communication direction flag = 1? ready flag = 1? communication direction flag = 1? reading iic0 clearing ready flag clearing ready flag communication direction flag = 1? clearing communication mode flag wrel0 = 1 writing iic0 iicc0 xxh acke0 = wtim0 = 1 spie0 = 0, iice0 = 1 sva0 xxh sets a local address. iicx0 0xh iiccl0 xxh selects a transfer clock. iicf0 0xh setting iicrsv sets a start condition. starts transmission. starts reception. communication mode flag = 1? ready flag = 1? setting port sets each pin to the i 2 c mode (see 12.3 (7) port mode register 6 (pm6) ). communication processing initial setting remark conform to the specifications of the product that is in communication, regarding the transmission and reception formats. chapter 12 serial interface iic0 user?s manual u17854ej6v0ud 486 an example of the processing procedur e of the slave with the intiic0 inte rrupt is explained below (processing is performed assuming that no extension code is used). the intiic0 interrupt c hecks the status, and the following operations are performed. <1> communication is stopped if the stop condition is issued. <2> if the start condition is issued, the address is c hecked and communication is completed if the address does not match. if the address matches, the communi cation mode is set, wait is cancelled, and processing returns from the interrupt (the ready flag is cleared). <3> for data transmit/receive, only the ready flag is set. processing returns from the interrupt with the i 2 c bus remaining in the wait state. remark <1> to <3> above correspond to <1> to <3> in figure 12-27 slave operation flowchart (2) . figure 12-27. slave operation flowchart (2) yes yes yes no no no intiic0 generated set ready flag interrupt servicing completed spd0 = 1? std0 = 1? coi0 = 1? communication direction flag trc0 set communication mode flag clear ready flag clear c ommunication direction flag, ready flag, and communication mode flag <1> <2> <3> chapter 12 serial interface iic0 user?s manual u17854ej6v0ud 487 12.5.18 timing of i 2 c interrupt request (intiic0) occurrence the timing of transmitting or receiving data and generation of interrupt request signal in tiic0, and the value of the iics0 register when the intiic0 signal is generated are shown below. remark st: start condition ad6 to ad0: address r/w: transfer direction specification ack: acknowledge d7 to d0: data sp: stop condition chapter 12 serial interface iic0 user?s manual u17854ej6v0ud 488 (1) master device operation (a) start ~ address ~ data ~ data ~ stop (transmission/reception) (i) when wtim0 = 0 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp spt0 = 1 3 4 5 2 1 1: iics0 = 1000110b 2: iics0 = 1000000b 3: iics0 = 1000000b (sets wtim0 to 1) note 4: iics0 = 100000b (sets spt0 to 1) note 5: iics0 = 00000001b note to generate a stop condition, set wtim0 to 1 and chan ge the timing for generating the intiic0 interrupt request signal. remark : always generated : generated only when spie0 = 1 : don?t care (ii) when wtim0 = 1 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp spt0 = 1 3 4 2 1 1: iics0 = 1000110b 2: iics0 = 1000100b 3: iics0 = 100000b (sets spt0 to 1) 4: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care chapter 12 serial interface iic0 user?s manual u17854ej6v0ud 489 (b) start ~ address ~ data ~ start ~ address ~ data ~ stop (restart) (i) when wtim0 = 0 st ad6 to ad0 r/w ack d7 to d0 ad6 to ad0 ack ack sp st r/w d7 to d0 ack stt0 = 1 spt0 = 1 3 4 7 2 1 5 6 1: iics0 = 1000110b 2: iics0 = 1000000b (sets wtim0 to 1) note 1 3: iics0 = 100000b (clears wtim0 to 0 note 2 , sets stt0 to 1) 4: iics0 = 1000110b 5: iics0 = 1000000b (sets wtim0 to 1) note 3 6: iics0 = 100000b (sets spt0 to 1) 7: iics0 = 00000001b notes 1. to generate a start condition, set wtim0 to 1 and change the timing for generating the intiic0 interrupt request signal. 2. clear wtim0 to 0 to restore the original setting. 3. to generate a stop condition, set wtim0 to 1 and change the timing for generating the intiic0 interrupt request signal. remark : always generated : generated only when spie0 = 1 : don?t care (ii) when wtim0 = 1 st ad6 to ad0 r/w ack d7 to d0 ad6 to ad0 ack ack sp st r/w d7 to d0 ack stt0 = 1 spt0 = 1 3 4 5 2 1 1: iics0 = 1000110b 2: iics0 = 100000b (sets stt0 to 1) 3: iics0 = 1000110b 4: iics0 = 100000b (sets spt0 to 1) 5: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care chapter 12 serial interface iic0 user?s manual u17854ej6v0ud 490 (c) start ~ code ~ data ~ data ~ stop (extension code transmission) (i) when wtim0 = 0 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp spt0 = 1 3 4 5 2 1 1: iics0 = 1010110b 2: iics0 = 1010000b 3: iics0 = 1010000b (sets wtim0 to 1) note 4: iics0 = 101000b (sets spt0 to 1) 5: iics0 = 00000001b note to generate a stop condition, set wtim0 to 1 and chan ge the timing for generating the intiic0 interrupt request signal. remark : always generated : generated only when spie0 = 1 : don?t care (ii) when wtim0 = 1 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp spt0 = 1 3 4 2 1 1: iics0 = 1010110b 2: iics0 = 1010100b 3: iics0 = 101000b (sets spt0 to 1) 4: iics0 = 00001001b remark : always generated : generated only when spie0 = 1 : don?t care chapter 12 serial interface iic0 user?s manual u17854ej6v0ud 491 (2) slave device operation (slave address data reception) (a) start ~ address ~ data ~ data ~ stop (i) when wtim0 = 0 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp 3 4 2 1 1: iics0 = 0001110b 2: iics0 = 0001000b 3: iics0 = 0001000b 4: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care (ii) when wtim0 = 1 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp 3 4 2 1 1: iics0 = 0001110b 2: iics0 = 0001100b 3: iics0 = 000100b 4: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care chapter 12 serial interface iic0 user?s manual u17854ej6v0ud 492 (b) start ~ address ~ data ~ start ~ address ~ data ~ stop (i) when wtim0 = 0 (after restart, matches with sva0) st ad6 to ad0 r/w ack d7 to d0 ad6 to ad0 ack ack sp st r/w d7 to d0 ack 3 4 5 2 1 1: iics0 = 0001110b 2: iics0 = 0001000b 3: iics0 = 0001110b 4: iics0 = 0001000b 5: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care (ii) when wtim0 = 1 (after restart, matches with sva0) st ad6 to ad0 r/w ack d7 to d0 ad6 to ad0 ack ack sp st r/w d7 to d0 ack 3 4 5 2 1 1: iics0 = 0001110b 2: iics0 = 000100b 3: iics0 = 0001110b 4: iics0 = 000100b 5: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care chapter 12 serial interface iic0 user?s manual u17854ej6v0ud 493 (c) start ~ address ~ data ~ start ~ code ~ data ~ stop (i) when wtim0 = 0 (after restart, does not match address (= extension code)) st ad6 to ad0 r/w ack d7 to d0 ad6 to ad0 ack ack sp st r/w d7 to d0 ack 3 4 5 2 1 1: iics0 = 0001110b 2: iics0 = 0001000b 3: iics0 = 0010010b 4: iics0 = 0010000b 5: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care (ii) when wtim0 = 1 (after restart, does not match address (= extension code)) st ad6 to ad0 r/w ack d7 to d0 ad6 to ad0 ack ack sp st r/w d7 to d0 ack 3 5 6 2 1 4 1: iics0 = 0001110b 2: iics0 = 000100b 3: iics0 = 0010010b 4: iics0 = 0010110b 5: iics0 = 001000b 6: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care chapter 12 serial interface iic0 user?s manual u17854ej6v0ud 494 (d) start ~ address ~ data ~ start ~ address ~ data ~ stop (i) when wtim0 = 0 (after restart, does not match address (= not extension code)) st ad6 to ad0 r/w ack d7 to d0 ad6 to ad0 ack ack sp st r/w d7 to d0 ack 3 4 2 1 1: iics0 = 0001110b 2: iics0 = 0001000b 3: iics0 = 00000110b 4: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care (ii) when wtim0 = 1 (after restart, does not match address (= not extension code)) st ad6 to ad0 r/w ack d7 to d0 ad6 to ad0 ack ack sp st r/w d7 to d0 ack 3 4 2 1 1: iics0 = 0001110b 2: iics0 = 000100b 3: iics0 = 00000110b 4: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care chapter 12 serial interface iic0 user?s manual u17854ej6v0ud 495 (3) slave device operation (w hen receiving extension code) the device is always participating in communication when it receives an extension code. (a) start ~ code ~ data ~ data ~ stop (i) when wtim0 = 0 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp 3 4 2 1 1: iics0 = 0010010b 2: iics0 = 0010000b 3: iics0 = 0010000b 4: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care (ii) when wtim0 = 1 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp 3 4 5 2 1 1: iics0 = 0010010b 2: iics0 = 0010110b 3: iics0 = 0010100b 4: iics0 = 001000b 5: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care chapter 12 serial interface iic0 user?s manual u17854ej6v0ud 496 (b) start ~ code ~ data ~ start ~ address ~ data ~ stop (i) when wtim0 = 0 (after restart, matches sva0) st ad6 to ad0 r/w ack d7 to d0 ad6 to ad0 ack ack sp st r/w d7 to d0 ack 3 4 5 2 1 1: iics0 = 0010010b 2: iics0 = 0010000b 3: iics0 = 0001110b 4: iics0 = 0001000b 5: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care (ii) when wtim0 = 1 (after restart, matches sva0) st ad6 to ad0 r/w ack d7 to d0 ad6 to ad0 ack ack sp st r/w d7 to d0 ack 3 4 6 2 1 5 1: iics0 = 0010010b 2: iics0 = 0010110b 3: iics0 = 001000b 4: iics0 = 0001110b 5: iics0 = 000100b 6: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care chapter 12 serial interface iic0 user?s manual u17854ej6v0ud 497 (c) start ~ code ~ data ~ start ~ code ~ data ~ stop (i) when wtim0 = 0 (after restart, extension code reception) st ad6 to ad0 r/w ack d7 to d0 ad6 to ad0 ack ack sp st r/w d7 to d0 ack 3 4 5 2 1 1: iics0 = 0010010b 2: iics0 = 0010000b 3: iics0 = 0010010b 4: iics0 = 0010000b 5: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care (ii) when wtim0 = 1 (after restart, extension code reception) st ad6 to ad0 r/w ack d7 to d0 ad6 to ad0 ack ack sp st r/w d7 to d0 ack 3 4 7 2 1 5 6 1: iics0 = 0010010b 2: iics0 = 0010110b 3: iics0 = 001000b 4: iics0 = 0010010b 5: iics0 = 0010110b 6: iics0 = 001000b 7: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care chapter 12 serial interface iic0 user?s manual u17854ej6v0ud 498 (d) start ~ code ~ data ~ start ~ address ~ data ~ stop (i) when wtim0 = 0 (after restart, does not match address (= not extension code)) st ad6 to ad0 r/w ack d7 to d0 ad6 to ad0 ack ack sp st r/w d7 to d0 ack 3 4 2 1 1: iics0 = 00100010b 2: iics0 = 00100000b 3: iics0 = 00000110b 4: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care (ii) when wtim0 = 1 (after restart, does not match address (= not extension code)) st ad6 to ad0 r/w ack d7 to d0 ad6 to ad0 ack ack sp st r/w d7 to d0 ack 3 4 5 2 1 1: iics0 = 00100010b 2: iics0 = 00100110b 3: iics0 = 0010000b 4: iics0 = 00000110b 5: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care chapter 12 serial interface iic0 user?s manual u17854ej6v0ud 499 (4) operation without communication (a) start ~ code ~ data ~ data ~ stop st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp 1 1: iics0 = 00000001b remark : generated only when spie0 = 1 (5) arbitration loss operation (opera tion as slave after arbitration loss) when the device is used as a master in a multi-master system, read the ms ts0 bit each time interrupt request signal intiic0 has occurred to check the arbitration result. (a) when arbitration loss occurs durin g transmission of slave address data (i) when wtim0 = 0 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp 3 4 2 1 1: iics0 = 0101110b 2: iics0 = 0001000b 3: iics0 = 0001000b 4: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care chapter 12 serial interface iic0 user?s manual u17854ej6v0ud 500 (ii) when wtim0 = 1 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp 3 4 2 1 1: iics0 = 0101110b 2: iics0 = 0001100b 3: iics0 = 000100b 4: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care (b) when arbitration loss occurs dur ing transmission of extension code (i) when wtim0 = 0 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp 3 4 2 1 1: iics0 = 0110010b 2: iics0 = 0010000b 3: iics0 = 0010000b 4: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care chapter 12 serial interface iic0 user?s manual u17854ej6v0ud 501 (ii) when wtim0 = 1 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp 3 4 5 2 1 1: iics0 = 0110010b 2: iics0 = 0010110b 3: iics0 = 0010100b 4: iics0 = 001000b 5: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care (6) operation when arbitration loss occurs (no communication after arbitration loss) when the device is used as a master in a multi-master system, read the ms ts0 bit each time interrupt request signal intiic0 has occurred to check the arbitration result. (a) when arbitration loss occu rs during transmission of slave address data (when wtim0 = 1) st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp 2 1 1: iics0 = 01000110b 2: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 chapter 12 serial interface iic0 user?s manual u17854ej6v0ud 502 (b) when arbitration loss occurs dur ing transmission of extension code st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp 2 1 1: iics0 = 0110010b sets lrel0 = 1 by software 2: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care (c) when arbitration loss occu rs during transmission of data (i) when wtim0 = 0 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp 3 2 1 1: iics0 = 10001110b 2: iics0 = 01000000b 3: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 chapter 12 serial interface iic0 user?s manual u17854ej6v0ud 503 (ii) when wtim0 = 1 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp 3 2 1 1: iics0 = 10001110b 2: iics0 = 01000100b 3: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 (d) when loss occurs due to rest art condition during data transfer (i) not extension code (example: unmatches with sva0) st ad6 to ad0 r/w ack d7 to dn ad6 to ad0 ack sp st r/w d7 to d0 ack 3 2 1 1: iics0 = 1000110b 2: iics0 = 01000110b 3: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care n = 6 to 0 chapter 12 serial interface iic0 user?s manual u17854ej6v0ud 504 (ii) extension code st ad6 to ad0 r/w ack d7 to dn ad6 to ad0 ack sp st r/w d7 to d0 ack 3 2 1 1: iics0 = 1000110b 2: iics0 = 01100010b sets lrel0 = 1 by software 3: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care n = 6 to 0 (e) when loss occurs due to st op condition during data transfer st ad6 to ad0 r/w ack d7 to dn sp 2 1 1: iics0 = 10000110b 2: iics0 = 01000001b remark : always generated : generated only when spie0 = 1 : don?t care n = 6 to 0 chapter 12 serial interface iic0 user?s manual u17854ej6v0ud 505 (f) when arbitration loss occurs due to low-level da ta when attempting to generate a restart condition (i) when wtim0 = 0 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack sp ack d7 to d0 ack stt0 = 1 3 4 5 2 1 1: iics0 = 1000110b 2: iics0 = 1000000b (sets wtim0 to 1) 3: iics0 = 1000100b (clears wtim0 to 0) 4: iics0 = 01000000b 5: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care (ii) when wtim0 = 1 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack sp ack d7 to d0 ack stt0 = 1 3 4 2 1 1: iics0 = 1000110b 2: iics0 = 1000100b (sets stt0 to 1) 3: iics0 = 01000100b 4: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care chapter 12 serial interface iic0 user?s manual u17854ej6v0ud 506 (g) when arbitration loss occurs due to a stop condition when attempting to generate a restart condition (i) when wtim0 = 0 st ad6 to ad0 r/w ack d7 to d0 ack sp stt0 = 1 3 4 2 1 1: iics0 = 1000110b 2: iics0 = 1000000b (sets wtim0 to 1) 3: iics0 = 100000b (sets stt0 to 1) 4: iics0 = 01000001b remark : always generated : generated only when spie0 = 1 : don?t care (ii) when wtim0 = 1 st ad6 to ad0 r/w ack d7 to d0 ack sp stt0 = 1 2 3 1 1: iics0 = 1000110b 2: iics0 = 100000b (sets stt0 to 1) 3: iics0 = 01000001b remark : always generated : generated only when spie0 = 1 : don?t care chapter 12 serial interface iic0 user?s manual u17854ej6v0ud 507 (h) when arbitration loss occurs due to low-level data when attemp ting to generate a stop condition (i) when wtim0 = 0 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack sp ack d7 to d0 ack spt0 = 1 3 4 5 2 1 1: iics0 = 1000110b 2: iics0 = 1000000b (sets wtim0 to 1) 3: iics0 = 1000100b (clears wtim0 to 0) 4: iics0 = 01000100b 5: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care (ii) when wtim0 = 1 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack sp ack d7 to d0 ack spt0 = 1 3 4 2 1 1: iics0 = 1000110b 2: iics0 = 1000100b (sets spt0 to 1) 3: iics0 = 01000100b 4: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don?t care chapter 12 serial interface iic0 user?s manual u17854ej6v0ud 508 12.6 timing charts when using the i 2 c bus mode, the master device outputs an address via the serial bus to select one of several slave devices as its communication partner. after outputting the slave address, the mast er device transmits the trc0 bit (bit 3 of iic status register 0 (iics0)), which specifies the data transfer di rection, and then starts serial communication with the slave device. figures 12-28 and 12-29 show timing charts of the data communication. iic shift register 0 (iic0)?s shift operation is synchronized with the falling edge of the serial clock (scl0). the transmit data is transferred to the so0 latch a nd is output (msb first) via the sda0 pin. data input via the sda0 pin is captured into iic0 at the rising edge of scl0. chapter 12 serial interface iic0 user?s manual u17854ej6v0ud 509 figure 12-28. example of master to slave communication (when 9-clock wait is selected fo r both master and slave) (1/3) (1) start condition ~ address iic0 ackd0 std0 spd0 wtim0 h h l l l l h h h l l acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 scl0 sda0 processing by master device transfer lines processing by slave device 123456789 4 3 2 1 ad6 ad5 ad4 ad3 ad2 ad1 ad0 w ack d4 d5 d6 d7 iic0 address iic0 data iic0 ffh transmit start condition receive (when exc0 = 1) note note note to cancel slave wait, write ?ffh? to iic0 or set wrel0. chapter 12 serial interface iic0 user?s manual u17854ej6v0ud 510 figure 12-28. example of master to slave communication (when 9-clock wait is selected fo r both master and slave) (2/3) (2) data iic0 ackd0 std0 spd0 wtim0 h h l l l l l l h h h h l l l l l acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 scl0 sda0 processing by master device transfer lines processing by slave device 1 9 8 23456789 3 2 1 d7 d0 d6 d5 d4 d3 d2 d1 d0 d5 d6 d7 iic0 data iic0 ffh iic0 ffh iic0 data transmit receive note note ack ack note note note to cancel slave wait, write ?ffh? to iic0 or set wrel0. chapter 12 serial interface iic0 user?s manual u17854ej6v0ud 511 figure 12-28. example of master to slave communication (when 9-clock wait is selected fo r both master and slave) (3/3) (3) stop condition iic0 ackd0 std0 spd0 wtim0 h h l l l l h h h l acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 scl0 sda0 processing by master device transfer lines processing by slave device 123456789 2 1 d7 d6 d5 d4 d3 d2 d1 d0 ad5 ad6 iic0 data iic0 address iic0 ffh note iic0 ffh note stop condition start condition transmit note note (when spie0 = 1) receive (when spie0 = 1) ack note to cancel slave wait, write ?ffh? to iic0 or set wrel0. chapter 12 serial interface iic0 user?s manual u17854ej6v0ud 512 figure 12-29. example of slave to master communication (when 8-clock wait is selected for master, 9-clock wait is selected for slave) (1/3) (1) start condition ~ address iic0 ackd0 std0 spd0 wtim0 h h l l l h l acke0 msts0 stt0 l l spt0 wrel0 intiic0 trc0 iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 scl0 sda0 processing by master device transfer lines processing by slave device 123456789 4 56 3 2 1 ad6 ad5 ad4 ad3 ad2 ad1 ad0 r d4 d3 d2 d5 d6 d7 iic0 address iic0 ffh note note iic0 data start condition ack note to cancel master wait, write ?ffh? to iic0 or set wrel0. chapter 12 serial interface iic0 user?s manual u17854ej6v0ud 513 figure 12-29. example of slave to master communication (when 8-clock wait is selected for master, 9-clock wait is selected for slave) (2/3) (2) data iic0 ackd0 std0 spd0 wtim0 h h h l l l l l l l h h l l l l l acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 scl0 sda0 processing by master device transfer lines processing by slave device 1 89 23456789 3 2 1 d7 d0 ack d6 d5 d4 d3 d2 d1 d0 ack d5 d6 d7 note note receive transmit iic0 data iic0 data iic0 ffh note iic0 ffh note note to cancel master wait, write ?ffh? to iic0 or set wrel0. chapter 12 serial interface iic0 user?s manual u17854ej6v0ud 514 figure 12-29. example of slave to master communication (when 8-clock and 9-clock wait is selected for m aster, 9-clock wait is selected for slave) (3/3) (3) stop condition iic0 ackd0 std0 spd0 wtim0 h h l l l acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 scl0 sda0 processing by master device transfer lines processing by slave device 12345678 9 1 d7 d6 d5 d4 d3 d2 d1 d0 ad6 iic0 address iic0 ffh note note iic0 data stop condition start condition (when spie0 = 1) nack (when spie0 = 1) note to cancel master wait, write ?ffh? to iic0 or set wrel0. user?s manual u17854ej6v0ud 515 chapter 13 multiplier 13.1 functions of multiplier the multiplier has the following functions. ? can execute calculation of 16 bits 16 bits = 32 bits. figure 13-1 shows the block diagram of the multiplier. figure 13-1. block di agram of multiplier internal bus internal bus multiplication input data register a (mula) multiplication input data register b (mulb) 32-bit multiplier 16-bit higher multiplication result storage register (muloh) 16-bit lower multiplication result storage register (mulol) chapter 13 multiplier user?s manual u17854ej6v0ud 516 13.2 configuration of multiplier (1) 16-bit higher multiplication resu lt storage register and 16-bit lo wer multiplication result storage register (muloh, mulol) these two registers, muloh and mulol, are used to store a 32-bit multip lication result. the higher 16 bits of the multiplication result are stored in muloh and the lower 16 bits, in mulol, so that a total of 32 bits of the multiplication resu lt can be stored. these registers hold the result of multip lication after the lapse of one cpu clock. muloh and mulol can be read by a 16-b it memory manipulation instruction. reset signal generation clears these registers to 0000h. figure 13-2. format of 16-bit higher multiplication result storage regi ster and 16-bit lower multiplication result storage register (muloh, mulol) symbol address: ffff4h, ffff5h after reset: 0000h r ffff5h ffff4h muloh symbol address: ffff6h, ffff7h after reset: 0000h r ffff7h ffff6h mulol (2) multiplication input data registers a, b (mula, mulb) these are 16-bit registers that store data for multiplication. the multiplie r multiplies the values of mula and mulb. mula and mulb can be set by a 16-bit memory manipulation instruction. reset signal generation clears these registers to 0000h. figure 13-3. format of multiplication in put data registers a, b (mula, mulb) symbol address: ffff0h, ffff1h after reset: 0000h r/w ffff1h ffff0h mula symbol address: ffff2h, ffff3h after reset: 0000h r/w ffff3h ffff2h mulb chapter 13 multiplier user?s manual u17854ej6v0ud 517 13.3 operation of multiplier the result of the multiplic ation can be obtained by stori ng the values in the mula and mulb registers and then reading the muloh and mulol registers after waiting for 1 cl ock. the result can also be obtained after 1 clock or more has elapsed, even when fixing either of mula or mu lb and rewrite the other of t hese. the result can be read without problem, regardless of whether muloh or mulol is read in first. a source example is shown below. example movw mula, #1234h movw mulb, #5678h nop ; 1 clock wait. doesn?t have to be nop movw ax, muloh ; the result obtained on upper side push ax movw ax, mulol ; the result obtained on lower side user?s manual u17854ej6v0ud 518 chapter 14 dma controller the 78k0r/ke3 has an internal dma (direct memory access) controller. data can be automatically transferred between the peri pheral hardware supporting dma, sfrs, and internal ram without via cpu. as a result, the normal internal operation of the cpu and data transfer can be execut ed in parallel with transfer between the sfr and internal ram, and therefore, a large c apacity of data can be processed. in addition, real-time control using communication, timer, and a/d can also be realized. 14.1 functions of dma controller { number of dma channels: 2 { transfer unit: 8 or 16 bits { maximum transfer unit: 1024 times { transfer type: 2-cycle transfer (one transfer is proc essed in 2 clocks and the cpu stops during that processing.) { transfer mode: single-transfer mode { transfer request: selectable from the following peripheral hardware interrupts ? a/d converter ? serial interface (cis00, csi10, uart0, uart1, uart3, or iic10) ? timer (channel 0, 1, 4, or 5) { transfer target: between sfr and internal ram here are examples of functions using dma. ? successive transfer of serial interface ? batch transfer of analog data ? capturing a/d conversion result at fixed interval ? capturing port value at fixed interval chapter 14 dma controller user?s manual u17854ej6v0ud 519 14.2 configuration of dma controller the dma controller includes the following hardware. table 14-1. configuration of dma controller item configuration address registers ? dma sfr address registers 0, 1 (dsa0, dsa1) ? dma ram address regist ers 0, 1 (dra0, dra1) count register ? dma byte count registers 0, 1 (dbc0, dbc1) control registers ? dma mode control registers 0, 1 (dmc0, dmc1) ? dma operation control register 0, 1 (drc0, drc1) (1) dma sfr address register n (dsan) this is an 8-bit register that is us ed to set an sfr address that is the tr ansfer source or destination of dma channel n. set the lower 8 bits of t he sfr addresses fff00h to fffffh note . this register is not automatically incr emented but fixed to a specific value. in the 16-bit transfer mode, the least significant bit is ignored and is treated as an even address. dsan can be read or written in 8-bit units. however, it cannot be written during dma transfer. reset signal generation clears this register to 00h. note except for address ffffeh because the pmc register is allocated there. figure 14-1. format of dma sfr address register n (dsan) address: fffb0h (dsa0), fffb1h (dsa1) after reset: 00h r/w 7 6 5 4 3 2 1 0 dsan remark n: dma channel number (n = 0, 1) chapter 14 dma controller user?s manual u17854ej6v0ud 520 (2) dma ram address register n (dran) this is a 16-bit register that is used to set a ram address that is the transfer source or destination of dma channel n. addresses of the internal ram area other than the general-purpose registers (f ef00h to ffedfh in the case of the pd78f1142) can be set to this register. set the lower 16 bits of the ram address. this register is automatically in cremented when dma transfer has been start ed. it is incremented by +1 in the 8-bit transfer mode and by +2 in the 16-bit transfer mo de. dma transfer is started from the address set to this dran register. when the data of the last address has been transferred, dran st ops with the value of the last address +1 in the 8-bit transfer mode, and t he last address +2 in the 16-bit transfer mode. in the 16-bit transfer mode, the least significant bit is ignored and is treated as an even address. dran can be read or written in 8-bit or 16-bit units. however, it cannot be written during dma transfer. reset signal generation clears this register to 0000h. figure 14-2. format of dma ram address register n (dran) address: fffb2h, fffb3h (dra0), fffb4h, fffb5h (dra1) after reset: 0000h r/w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dran (n = 0, 1) remark n: dma channel number (n = 0, 1) dra0h: fffb3h dra1h: fffb5h dra0l: fffb2h dra1l: fffb4h chapter 14 dma controller user?s manual u17854ej6v0ud 521 (3) dma byte count register n (dbcn) this is a 10-bit register that is us ed to set the number of times dma channel n executes transfer. be sure to set the number of times of transfer to this dbcn regi ster before executing dma transfer (up to 1024 times). each time dma transfer has been executed, this regist er is automatically decremented. by reading this dbcn register during dma transfer, the remain ing number of times of transfer can be learned. dbcn can be read or written in 8-bit or 16-bit units. however, it cannot be written during dma transfer. reset signal generation clears this register to 0000h. figure 14-3. format of dma byte count register n (dbcn) address: fffb6h, fffb7h (dbc0), fffb8h, fffb9h (dbc1) after reset: 0000h r/w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dbcn 0 0 0 0 0 0 (n = 0, 1) dbcn[9:0] number of times of transfer (when dbcn is written) remaining number of times of transfer (when dbcn is read) 000h 1024 completion of transfer or waiting for 1024 times of dma transfer 001h 1 waiting for remaining one time of dma transfer 002h 2 waiting for remaining two times of dma transfer 003h 3 waiting for remaining three times of dma transfer ? ? ? ? ? ? ? ? ? 3feh 1022 waiting for remaining 1022 times of dma transfer 3ffh 1023 waiting for remaining 1023 times of dma transfer cautions 1. be sure to cl ear bits 15 to 10 to ?0?. 2. if the general-purpose register is specifie d or the internal ram sp ace is exceeded as a result of continuous transfer , the general-purpose register or sfr space are written or read, resulting in loss of data in these spaces. be sure to set the number of times of transfer that is within the internal ram space. remark n: dma channel number (n = 0, 1) dbc0h: fffb7h dbc1h: fffb9h dbc0l: fffb6h dbc1l: fffb8h chapter 14 dma controller user?s manual u17854ej6v0ud 522 14.3 registers to controlling dma controller dma controller is controlle d by the following registers. ? dma mode control register n (dmcn) ? dma operation control register n (drcn) remark n: dma channel number (n = 0, 1) (1) dma mode control register n (dmcn) dmcn is a register that is used to set a transfer mode of dma channel n. it is used to select a transfer direction, data size, setting of pending, and start source. bit 7 (stgn) is a software trigger that starts dma. rewriting bits 6, 5, and 3 to 0 of dmcn is prohibited during operation (when dstn = 1). dmcn can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. figure 14-4. format of dma mode control register n (dmcn) (1/2) address: fffbah (dmc0), fffbbh (dmc1) after reset: 00h r/w symbol <7> <6> <5> <4> 3 2 1 0 dmcn stgn drsn dsn dwaitn ifcn3 ifcn2 ifcn1 ifcn0 stgn note dma transfer start software trigger 0 no trigger operation 1 dma transfer is started when dma operation is enabled (denn = 1). dma transfer is started by writing 1 to stgn when dma operation is enabled (denn = 1). when this bit is read, 0 is always read. drsn selection of dma transfer direction 0 sfr to internal ram 1 internal ram to sfr dsn specification of transfer data size for dma transfer 0 8 bits 1 16 bits dwaitn pending of dma transfer 0 executes dma transfer upon dma start request (not held pending). 1 holds dma start request pending if any. dma transfer that has been held pending can be star ted by clearing the value of dwaitn to 0. it takes 2 clocks to actually hold dma transfer pending when the value of dwaitn is set to 1. note the software trigger (stgn) can be used r egardless of the ifcn0 to ifcn3 values. remark n: dma channel number (n = 0, 1) chapter 14 dma controller user?s manual u17854ej6v0ud 523 figure 14-4. format of dma mode control register n (dmcn) (2/2) address: fffbah (dmc0), fffbbh (dmc1) after reset: 00h r/w symbol <7> <6> <5> <4> 3 2 1 0 dmcn stgn drsn dsn dwaitn ifcn3 ifcn2 ifcn1 ifcn0 selection of dma stat source note ifcn 3 ifcn 2 ifcn 1 ifcn 0 trigger signal trigger contents 0 0 0 0 ? disables dma transfer by interrupt. (only software trigger is enabled.) 0 0 1 0 inttm00 timer channel 0 interrupt 0 0 1 1 inttm01 timer channel 1 interrupt 0 1 0 0 inttm04 timer channel 4 interrupt 0 1 0 1 inttm05 timer channel 5 interrupt 0 1 1 0 intst0/intcsi00 uart0 transmission end interrupt/ csi00 transfer end interrupt 0 1 1 1 intsr0 uart0 reception end interrupt 1 0 0 0 intst1/intcsi10/intiic10 uart1 transmission end interrupt/ csi10 transfer end interrupt/ iic10 transfer end interrupt 1 0 0 1 intsr1 uart1 reception end interrupt 1 0 1 0 intst3 uart3 transmission end interrupt 1 0 1 1 intsr3 uart3 reception end interrupt 1 1 0 0 intad a/d conversion end interrupt other than above setting prohibited note the software trigger (stgn) can be used regardless of the ifcn0 to ifcn3 values. remark n: dma channel number (n = 0, 1) chapter 14 dma controller user?s manual u17854ej6v0ud 524 (2) dma operation control register n (drcn) drcn is a register that is used to enable or disable transfer of dma channel n. rewriting bit 7 (denn) of this register is prohibited during operation (when dstn = 1). drcn can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. figure 14-5. format of dma oper ation control register n (drcn) address: fffbch (drc0), fffbdh (drc1) after reset: 00h r/w symbol <7> 6 5 4 3 2 1 0 drcn denn 0 0 0 0 0 0 dstn denn dma operation enable flag 0 disables operation of dma channel n (stops operating cock of dma). 1 enables operation of dma channel n. dmac waits for a dma trigger when dstn = 1 after dma operation is enabled (denn = 1). dstn dma transfer mode flag 0 dma transfer of dma channel n is completed. 1 dma transfer of dma channel n is not completed (still under execution). dmac waits for a dma trigger when dstn = 1 after dma operation is enabled (denn = 1). when a software trigger (stgn) or the start source trigger set by ifcn3 to ifcn0 is input, dma transfer is started. when dma transfer is completed after that, this bit is automatic ally cleared to 0. write 0 to this bit to forcibly te rminate dma transfer under execution. caution the dstn flag is automatically cleared to 0 when a dma transfer is completed. writing the denn flag is enabled only when dstn = 0. when a dma transfer is terminated without waiting for generation of the interrupt (intdman) of dman, therefore, set dstn to 0 and then denn to 0 (for details, refer to 14.5.5 forced termination by software). remark n: dma channel number (n = 0, 1) chapter 14 dma controller user?s manual u17854ej6v0ud 525 no no dstn = 1 dstn = 0 intdman = 1 dma trigger = 1? dbcn = 0000h ? yes yes denn = 1 setting dsan, dran, dbcn, and dmcn transmitting dma request receiving dma acknowledge dma transfer dran = dran + 1 (or + 2) dbcn = dbcn ? 1 denn = 0 set by software program operation by dma controller (hardware) set by software program 14.4 operation of dma controller 14.4.1 operation procedure <1> the dma controller is enabled to operate when denn = 1. before writing the other registers, be sure to set denn to 1. use 80h to write wit h an 8-bit manipulation instruction. <2> set an sfr address, a ram address, the number of times of transfer, and a transfer mode of dma transfer to the dsan, dran, cbcn, and dmcn registers. <3> the dma controller waits for a dma trigger when dstn = 1. use 81h to write with an 8-bit manipulation instruction. <4> when a software trigger (stgn) or a start source tri gger specified by ifcn3 to ifcn0 is input, a dma transfer is started. <5> transfer is completed when the number of times of trans fer set by the dbcn register reaches 0, and transfer is automatically terminated by occu rrence of an interrupt (intdman). <6> stop the operation of the dma c ontroller by clearing denn to 0 w hen the dma controller is not used. figure 14-6. operation procedure remark n: dma channel number (n = 0, 1) chapter 14 dma controller user?s manual u17854ej6v0ud 526 14.4.2 transfer mode the following four modes can be selected for dma transfe r by using bits 6 and 5 (drsn and dsn) of the dmcn register. drsn dsn dma transfer mode 0 0 transfer from sfr of 1-byte data (fixed add ress) to ram (address is incremented by +1) 0 1 transfer from sfr of 2-byte data (fixed add ress) to ram (address is incremented by +2) 1 0 transfer from ram of 1-byte data (address is incremented by +1) to sfr (fixed address) 1 1 transfer from ram of 2-byte data (address is incremented by +2) to sfr (fixed address) by using these transfer modes, up to 1024 bytes of data can be consecutively transferred by using the serial interface, data resulting from a/d c onversion can be consecutively transferred, and port data can be scanned at fixed time intervals by using a timer. 14.4.3 termination of dma transfer when dbcn = 00h and dma transfer is completed, the dstn bit is automatically cleared to 0. an interrupt request (intdman) is generated and transfer is terminated. when the dstn bit is cleared to 0 to forcibly terminate dm a transfer, the dbcn and dra n registers hold the value when transfer is terminated. the interrupt request (intdman) is not ge nerated if transfer is forcibly terminated. remark n: dma channel number (n = 0, 1) chapter 14 dma controller user?s manual u17854ej6v0ud 527 14.5 example of setting of dma controller 14.5.1 csi consecutive transmission a flowchart showing an example of setting for csi consecutive transmission is shown below. ? consecutive transmission of csi00 ? dma channel 0 is used for dma transfer. ? dma start source: intcsi00 (software trigger (stg0) only for the first start source) ? interrupt of csi00 is specified by ifc03 to if c00 (bits 3 to 0 of the dmc0 register) = 0110b. ? transfers ff100h to ff1ffh (256 bytes) of ram to fff10h of the transmit buffer (sio00) of csi. chapter 14 dma controller user?s manual u17854ej6v0ud 528 figure 14-7. example of setting for csi consecuti ve transmission note the dst0 flag is automatically cleared to 0 when a dma transfer is completed. writing the den0 flag is enabled only when dst0 = 0. to terminate a dma transfer without waiting for occurrence of the interrupt of dma0 (intdma0), set dst0 to 0 and then den0 to 0 (for details, refer to 14.5.5 forced termination by software ). the fist trigger for consecutive transmi ssion is not started by the interrupt of csi. start it by a software trigger. csi transmission of the second time and onward is automatically executed. the dma interrupt (intdma0) is generated as soon as the last data has been writte n to the transmit buffer. at this point, the last data of csi is being transmitted. to start dma transfer again, therefore, wait until transfer of csi is completed. setting for csi transfer den0 = 1 dsa0 = 10h dra0 = f100h dbc0 = 0100h dmc0 = 46h den0 = 0 dst0 = 1 stg0 = 1 start dma is started. intcsi00 occurs. reti end user program processing occurrence of intdma0 dst0 = 0 note dma0 transfer csi transmission hardware operation chapter 14 dma controller user?s manual u17854ej6v0ud 529 14.5.2 consecutive capturing of a/d conversion results a flowchart of an example of setting for consecutivel y capturing a/d conversion results is shown below. ? consecutive capturing of a/d conversion results. ? dma channel 1 is used for dma transfer. ? dma start source: intad ? interrupt of a/d is specified by ifc13 to if c10 (bits 3 to 0 of the dmc1 register) = 1100b. ? transfers fff1eh and fff1fh (2 bytes) of the 10-bit a/d conversion result register to 2048 bytes of ff380h to ffb7fh of ram. chapter 14 dma controller user?s manual u17854ej6v0ud 530 figure 14-8. example of setting of cons ecutively capturing a/d conversion results note the dst1 flag is automatically cleared to 0 when a dma transfer is completed. writing the den1 flag is enabled only when dst1 = 0. to terminate a dma transfer without waiting for occurrence of the interrupt of dma1 (intdma1), set dst1 to 0 and then den1 to 0 (for details, refer to 14.5.5 forced termination by software ). hardware operation den1 = 1 dsa1 = 1eh dra1 = f380h dbc1 = 0000h dmc1 = 2ch dst1 = 1 starting a/d conversion den1 = 0 reti end intdma1 occurs. dst1 = 0 note intad occurs. dma1 transfer start user program processing chapter 14 dma controller user?s manual u17854ej6v0ud 531 14.5.3 uart consecutive r eception + ack transmission a flowchart illustrating an example of setting for uart consecutive reception + ack transmission is shown below. ? consecutively receives data fr om uart0 and outputs ack to p10 on completion of reception. ? dma channel 0 is used for dma transfer. ? dma start source: software trigger (dma transfer on occurrence of an interrupt is disabled.) ? transfers fff12h of uart receive data register 0 (rxd0) to 64 bytes of ffe00h to ffe3fh of ram. chapter 14 dma controller user?s manual u17854ej6v0ud 532 den0 = 1 dsa0 = 12h dra0 = fe00h dbc0 = 0040h dmc0 = 00h den0 = 0 note setting for uart reception dst0 = 1 user program processing stg0 = 1 p10 = 1 p10 = 0 intsr0 occurs. intdma0 occurs. dst0 = 0 dma0 transfer reti hardware operation start end reti intsr0 interrupt routine figure 14-9. example of setting for uar t consecutive reception + ack transmission note the dst0 flag is automatically cleared to 0 when a dma transfer is completed. writing the den0 flag is enabled only when dst0 = 0. to terminate a dma transfer without waiting for occurrence of the interrupt of dma0 (intdma0), set dst0 to 0 and then den0 to 0 (for details, refer to 14.5.5 forced termination by software ). remark this is an example where a software trigger is used as a dma start source. if ack is not transmitted and if only data is consec utively received from uart, the uart reception end interrupt (intsr0) can be used to start dma for data reception. chapter 14 dma controller user?s manual u17854ej6v0ud 533 starting dma transfer dwaitn = 0 dwaitn = 1 wait for 2 clocks p00 = 1 wait for 9 clocks p00 = 0 main program 14.5.4 holding dma transfer pending by dwaitn when dma transfer is started, transfer is performed while an in struction is executed. at this time, the operation of the cpu is stopped and delayed for the duration of 2 clo cks. if this poses a problem to the operation of the set system, a dma transfer can be held pen ding by setting dwaitn to 1. to output a pulse with a width of 10 cl ocks of the operating frequency from t he p00 pin, for example, the clock width increases to 12 if a dma transfer is started midway. in this case, the dma transfer can be held pending by setting dwaitn to 1. after setting dwaitn to 1, it takes two cl ocks until a dma transfer is held pending. figure 14-10. example of setting for ho lding dma transfer pending by dwaitn remarks 1. n: dma channel number (n = 0, 1) 2. 1 clock: 1/f clk (f clk : cpu clock) chapter 14 dma controller user?s manual u17854ej6v0ud 534 dstn = 0 denn = 0 dstn = 0 ? no 2 clock wait yes dstn = 0 denn = 0 14.5.5 forced termination by software after dstn is set to 0 by software, it takes up to 2 clocks until a dma transfe r is actually stopped and dstn is set to 0. to forcibly terminate a dma transfer by software wit hout waiting for occurrence of the interrupt (intdman) of dman, therefore, perform either of the following processes. ? set dstn to 0 (use drcn = 80h to write with an 8-bit manipulation instruction) by software, confirm by polling that dstn has actually been cleared to 0, and then set denn to 0 (use drcn = 00h to write with an 8-bit manipulation instruction). ? set dstn to 0 (use drcn = 80h to write with an 8-bit manipulation instruction) by software and then set denn to 0 (use drcn = 00h to write with an 8-bit manipu lation instruction) two or more clocks after. figure 14-11. forced termination of dma transfer example 1 example 2 remarks 1. n: dma channel number (n = 0, 1) 2. 1 clock: 1/f clk (f clk : cpu clock) chapter 14 dma controller user?s manual u17854ej6v0ud 535 14.6 cautions on using dma controller (1) priority of dma during dma transfer, a request from the other dma channel is held pend ing even if generated. the pending dma transfer is started after the ongoing dma transfer is completed. when the requests from either of the dma channels are successively generated in a short period note , they are successively transferred, and on completion of that, the requests from the other dm a channel are executed. in this case, one or tow instructions are executed between the fi rst dma transfer and next dma transfer. if two dma requests are generated at the same time, however, dma channel 0 takes priority over dma channel 1. if a dma request and an interrupt request are gener ated at the same time, the dma transfer takes precedence, and then interrupt servicing is executed. note the short period refers to a period of eight or fewe r cpu clocks. the relationship between the lengths of clock period and dma operations is as follows. 1 clock period: setting disabled dma request cannot be accepted. 2 to 4 clock period: dma transfer of the channel where requests are successively generated is executed. 5 to 8 clock period: whether dma transfer of the c hannel where requests are successively generated is executed or dma requests from the ot her channel are executed depends on the number of times cpu instructions are executed. (2) dma response time the response time of dma transfer is as follows. table 14-2. response time of dma transfer minimum time maximum time response time 4 clocks 10 clocks remark 1 clock: 1/f clk (f clk : cpu clock) in the following cases, however, dma transfer may be delayed further. the number of clocks by which dma transfer is delayed differs depending on the condition. ? instruction execution by ram ? instruction execution by external memory ? if wait cycle is inserted when external memory is accessed ? execution of dma pending instruction chapter 14 dma controller user?s manual u17854ej6v0ud 536 (3) operation in standby mode the dma controller operates as follows in the standby mode. table 14-3. dma operation in standby mode status dma operation halt mode normal operation stop mode stops operation. if dma transfer and stop instruction execution contend, dma transfer may be damaged. therefore, stop dma before executing the stop instruction. (4) dma pending instruction even if a dma request is generated, dm a transfer is held pending immediately after the following instructions. ? call !addr16 ? call &!addr16 ? call !!addr20 ? call rp ? callt [addr5] ? brk ? bit manipulation instructions for registers if0l, if0h, if1l, if1h, if2l, if2h, mk0l, mk0h, mk1l, mk1h, mk2l, mk2h, pr00l, pr00h, pr01l, pr01h, pr02l, pr02h, pr10l, pr10h, pr11l, pr11h, pr12l, pr12h and psw each, and 8-bit manipulation instru ctions with operands including es registers (5) operation if address in general- purpose register area or other than those of internal ram area is specified the address indicated by dra0n is incremented during dma transfer. if the address is incremented to an address in the general-purpose register area or exceed s the area of the internal ram, the following operation is performed. z in mode of transfer from sfr to ram the data of that address is lost. z in mode of transfer from ram to sfr undefined data is transferred to sfr. in either case, malfunctioning may occur or damage may be done to the system. therefore, make sure that the address is within the internal ram area ot her than the general-purpose register area. internal ram general-purpose registers dma transfer enabled area fff00h ffeffh ffee0h ffedfh user?s manual u17854ej6v0ud 537 chapter 15 interrupt functions 15.1 interrupt function types the following two types of inte rrupt functions are used. (1) maskable interrupts these interrupts undergo mask control. maskable interrupts can be divided into four priority groups by setting the priority specification flag regist ers (pr00l, pr00h, pr01l, pr01h, pr02l, pr02h, pr10l, pr10h, pr11l, pr11h, pr12l, pr12h). multiple interrupt servicing can be applied to low-priority interrupts when high-priority interrupts are generated. if two or more interrupt requests, each having the same priority, are simultaneously generated, then they are processed according to the priority of vectored in terrupt servicing. for the priority order, see table 15-1 . a standby release signal is generated a nd stop and halt modes are released. external interrupt requests and internal interrupt requests are provided as maskable interrupts. external: 13, internal: 25 (2) software interrupt this is a vectored interrupt generated by executing the brk instruction. it is acknowledged even when interrupts are disabled. the software interrupt does not undergo interrupt priority control. chapter 15 interrupt functions user?s manual u17854ej6v0ud 538 15.2 interrupt sources and configuration the 78k0r/ke3 has a total of 39 interrupt sources incl uding maskable interrupts and software interrupts. in addition, they also have up to five reset sources (see table 15-1 ). table 15-1. interrupt source list (1/2) interrupt source interrupt type default priority note 1 name trigger internal/ external vector table address basic configuration type note 2 0 intwdti watchdog timer interval note 3 (75% of overflow time) 0004h 1 intlvi low-voltage detection note 4 internal 0006h (a) 2 intp0 0008h 3 intp1 000ah 4 intp2 000ch 5 intp3 000eh 6 intp4 0010h 7 intp5 pin input edge detection external 0012h (b) 8 intst3 end of uart3 transmission 0014h 9 intsr3 end of uart3 reception 0016h 10 intsre3 uart3 reception error occurrence 0018h 11 intdma0 end of dma0 transfer 001ah 12 intdma1 end of dma1 transfer 001ch 13 intst0 /intcsi00 end of uart0 transmission/ end of csi00 communication 001eh 14 intsr0 end of uart0 reception 0020h 15 intsre0 uart0 reception error occurrence 0022h 16 intst1 /intcsi10 /intiic10 end of uart1 transmission/ end of csi10 communication/ end of iic10 communication 0024h 17 intsr1 end of uart1 reception 0026h 18 intsre1 uart1 reception error occurrence 0028h 19 intiic0 end of iic0 communication 002ah 20 inttm00 end of timer channel 0 count or capture 002ch 21 inttm01 end of timer channel 1 count or capture 002eh 22 inttm02 end of timer channel 2 count or capture 0030h maskable 23 inttm03 end of timer channel 3 count or capture internal 0032h (a) notes 1. the default priority determines t he sequence of interrupts if two or more maskable interrupts occur simultaneously. zero indicates the highest priority and 37 indicates the lowest priority. 2. basic configuration types (a) to (c) co rrespond to (a) to (c) in figure 15-1. 3. when bit 7 (wdtint) of the option byte (000c0h) is set to 1. 4. when bit 1 (lvimd) of the low-voltage detec tion register (lvim) is cleared to 0. chapter 15 interrupt functions user?s manual u17854ej6v0ud 539 table 15-1. interrupt source list (2/2) interrupt source interrupt type default priority note 1 name trigger internal/ external vector table address basic configuration type note 2 24 intad end of a/d conversion 0034h 25 intrtc fixed-cycle sign al of real-time counter/alarm match detection 0036h 26 intrtci interval signal dete ction of real-time counter internal 0038h (a) 27 intkr key return signal detection external 003ah (b) 28 inttm04 end of timer channel 4 count or capture 0042h 29 inttm05 end of timer channel 5 count or capture 0044h 30 inttm06 end of timer channel 6 count or capture 0046h 31 inttm07 end of timer channel 7 count or capture internal 0048h (a) 32 intp6 004ah 33 intp7 004ch 34 intp8 004eh 35 intp9 0050h 36 intp10 0052h maskable 37 intp11 pin input edge detection external 0054h (b) software ? brk execution of brk instruction ? 007eh (c) reset reset pin input poc power-on-clear lvi low-voltage detection note 3 wdt overflow of watchdog timer reset ? trap execution of illegal instruction note 4 ? 0000h ? notes 1. the default priority determines t he sequence of interrupts if two or more maskable interrupts occur simultaneously. zero indicates the highest priority and 37 indicates the lowest priority. 2. basic configuration types (a) to (c) co rrespond to (a) to (c) in figure 15-1. 3. when bit 1 (lvimd) of the low-voltage detection register (lvim) is set to 1. 4. when the instruction code in ffh is executed. reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip debug emulator. chapter 15 interrupt functions user?s manual u17854ej6v0ud 540 figure 15-1. basic configuration of interrupt function (a) internal maskable interrupt if mk ie pr1 isp1 pr0 isp0 internal bus interrupt request priority controller vector table address generator standby release signal (b) external maskable interrupt if mk ie pr1 isp1 pr0 isp0 internal bus external interrupt edge enable register (egp, egn) interrupt request edge detector priority controller vector table address generator standby release signal (c) software interrupt vector table address generator internal bus interrupt request if: interrupt request flag ie: interrupt enable flag isp0: in-service priority flag 0 isp1: in-service priority flag 1 mk: interrupt mask flag pr0: priority specification flag 0 pr1: priority specification flag 1 chapter 15 interrupt functions user?s manual u17854ej6v0ud 541 15.3 registers controlling interrupt functions the following 6 types of registers are used to control the interrupt functions. ? interrupt request flag registers (i f0l, if0h, if1l, if1h, if2l, if2h) ? interrupt mask flag registers (mk0l, mk0h, mk1l, mk1h, mk2l, mk2h) ? priority specification flag registers (pr00l, pr 00h, pr01l, pr01h, pr02l, pr02h, pr10l, pr10h, pr11l, pr11h, pr12l, pr12h) ? external interrupt rising edge enable registers (egp0, egp1) ? external interrupt falling edge enable registers (egn0, egn1) ? program status word (psw) table 15-2 shows a list of interrupt request flags, interrupt mask flags, and priority specification flags corresponding to interrupt request sources. table 15-2. flags corresponding to interrupt request sources (1/2) interrupt request flag interrupt mask flag priority specification flag interrupt source register register register intwdti wdtiif wdtimk wdtipr0, wdtipr1 intlvi lviif lvimk lvipr0, lvipr1 intp0 pif0 pmk0 ppr00, ppr10 intp1 pif1 pmk1 ppr01, ppr11 intp2 pif2 pmk2 ppr02, ppr12 intp3 pif3 pmk3 ppr03, ppr13 intp4 pif4 pmk4 ppr04, ppr14 intp5 pif5 if0l pmk5 mk0l ppr05, ppr15 pr00l, pr10l intst3 stif3 stmk3 stpr03, stpr13 intsr3 srif3 srmk3 srpr03, srpr13 intsre3 sreif3 sremk3 srepr03, srepr13 intdma0 dmaif0 dmamk0 dmapr00, dmapr10 intdma1 dmaif1 dmamk1 dmapr01, dmapr11 intst0 note stif0 note stmk0 note stpr00, stpr10 note intcsi00 note csiif00 note csimk00 note csipr000, csipr100 note intsr0 srif0 srmk0 srpr00, srpr10 intsre0 sreif0 if0h sremk0 mk0h srepr00, srepr10 pr00h, pr10h note do not use uart0 and csi00 at the same time because they share flags for the interrupt request sources. if one of the interrupt sources intst0 and intcsi00 is gener ated, bit 5 of if1h is set to 1. bit 5 of mk0h, pr00h, and pr10h supports these three interrupt sources. chapter 15 interrupt functions user?s manual u17854ej6v0ud 542 table 15-2. flags corresponding to interrupt request sources (2/2) interrupt request flag interrupt mask flag priority specification flag interrupt source register register register intst1 note stif1 note stmk1 note stpr01, stpr11 note intcsi10 note csiif10 note csimk10 note csipr010, csipr110 note intiic10 note iicif10 note iicmk10 note iicpr010, iicpr110 note intsr1 srif1 srmk1 srpr01, srpr11 intsre1 sreif1 sremk1 srepr01, srepr11 intiic0 iicif0 iicmk0 iicpr00, iicpr10 inttm00 tmif00 tmmk00 tmpr000, tmpr100 inttm01 tmif01 tmmk01 tmpr001, tmpr101 inttm02 tmif02 tmmk02 tmpr002, tmpr102 inttm03 tmif03 if1l tmmk03 mk1l tmpr003, tmpr103 pr01l, pr11l intad adif admk adpr0, adpr1 intrtc rtcif rtcmk rtcpr0, rtcpr1 intrtci rtciif rtcimk rtcipr0, rtcipr1 intkr krif krmk krpr0, krpr1 inttm04 tmif04 if1h tmmk04 mk1h tmpr004, tmpr104 pr01h, pr11h inttm05 tmif05 tmmk05 tmpr005, tmpr105 inttm06 tmif06 tmmk06 tmpr006, tmpr106 inttm07 tmif07 tmmk07 tmpr007, tmpr107 intp6 pif6 pmk6 ppr06, ppr16 intp7 pif7 pmk7 ppr07, ppr17 intp8 pif8 pmk8 ppr08, ppr18 intp9 pif9 pmk9 ppr09, ppr19 intp10 pif10 if2l pmk10 mk2l ppr010, ppr110 pr02l, pr12l intp11 pif11 if2h pmk11 mk2h ppr011, ppr111 pr02h, pr12h note do not use uart1, csi10, and iic10 at the same time because they share flags for the interrupt request sources. if one of the interrupt sources intst1, intcsi 10, and intiic10 is generated, bit 0 of if1l is set to 1. bit 0 of mk1l, pr01l, and pr11l s upports these three interrupt sources. chapter 15 interrupt functions user?s manual u17854ej6v0ud 543 (1) interrupt request flag registers (i f0l, if0h, if1l, if1h, if2l, if2h) the interrupt request flags are set to 1 when the correspo nding interrupt request is g enerated or an instruction is executed. they are cleared to 0 when an instruction is executed upon acknow ledgment of an interrupt request or upon reset signal generation. when an interrupt is acknowledged, the interrupt req uest flag is automatically cleared and then the interrupt routine is entered. if0l, if0h, if1l, if1h, if2l, and if2h can be set by a 1-bit or 8-bit memory manipulation instruction. when if0l and if0h, if1l and if1h, and if2l and if 2h are combined to form 16-bit r egisters if0, if1, and if2, they can be set by a 16-bit memory manipulation instruction. reset signal generation clears these registers to 00h. remark if an instruction that writes data to this register is execut ed, the number of instru ction execution clocks increases by 2 clocks. figure 15-2. format of interrupt request flag registers (if0l, if0h, if1l, if1h, if2l, if2h) address: fffe0h after reset: 00h r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> if0l pif5 pif4 pif3 pif2 pif1 pif0 lviif wdtiif address: fffe1h after reset: 00h r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> if0h sreif0 srif0 csiif00 stif0 dmaif1 dmaif0 sreif3 srif3 stif3 address: fffe2h after reset: 00h r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> if1l tmif03 tmif02 tmif01 tmif00 iicif0 sreif1 srif1 csiif10 iicif10 stif1 address: fffe3h after reset: 00h r/w symbol <7> 6 5 4 <3> <2> <1> <0> if1h tmif04 0 0 0 krif rtciif rtcif adif address: fffd0h after reset: 00h r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> if2l pif10 pif9 pif8 pif7 pif6 tmif07 tmif06 tmif05 address: fffd1h after reset: 00h r/w symbol 7 6 5 4 3 2 1 <0> if2h 0 0 0 0 0 0 0 pif11 xxifx interrupt request flag 0 no interrupt request signal is generated 1 interrupt request is generated, interrupt request status chapter 15 interrupt functions user?s manual u17854ej6v0ud 544 cautions 1. be sure to clear bits 4 to 6 of if1h and bits 1 to 7 of if2h to 0. 2. when operating a timer, seri al interface, or a/d c onverter after standby release, operate it once after clearing the interrupt request flag. an interrupt request flag may be set by noise. 3. when manipulating a flag of the interrupt request flag register, use a 1-bit memory manipulation instruction (clr1) . when describing in c langua ge, use a bit manipulation instruction such as ?if0l.0 = 0;? or ?_asm(?clr1 if0l, 0?);? because the comp iled assembler must be a 1-bit memory manipulation instruction (clr1). if a program is described in c language us ing an 8-bit memory manipulation instruction such as ?if0l &= 0xfe;? and compiled, it b ecomes the assembler of three instructions. mov a, if0l and a, #0feh mov if0l, a in this case, even if th e request flag of another bit of the same interrupt request flag register (if0l) is set to 1 at the timi ng between ?mov a, if0l? and ?mov if0l, a?, the flag is cleared to 0 at ?mov if0l, a?. therefore, care mu st be exercised when using an 8-bit memory manipulation instruction in c language. (2) interrupt mask flag registers (mk 0l, mk0h, mk1l, mk1h, mk2l, mk2h) the interrupt mask flags are used to enable/disable the corresponding maskable interrupt servicing. mk0l, mk0h, mk1l, mk1h, mk2l, and mk2h can be set by a 1-bit or 8-bit memory manipulation instruction. when mk0l and mk0h, mk1l and mk1h, and mk2l and mk2h are combined to form 16-bit registers mk0, mk1, and mk2, they can be set by a 16-bi t memory manipulation instruction. reset signal generation sets these registers to ffh. remark if an instruction that writes data to this register is execut ed, the number of instru ction execution clocks increases by 2 clocks. chapter 15 interrupt functions user?s manual u17854ej6v0ud 545 figure 15-3. format of interrupt mask flag re gisters (mk0l, mk0h, mk1l, mk1h, mk2l, mk2h) address: fffe4h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> mk0l pmk5 pmk4 pmk3 pmk2 pmk1 pmk0 lvimk wdtimk address: fffe5h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> mk0h sremk0 srmk0 csimk00 stmk0 dmamk1 dmamk0 sremk3 srmk3 stmk3 address: fffe6h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> mk1l tmmk03 tmmk02 tmmk01 tmmk00 iicmk0 sremk1 srmk1 csimk10 iicmk10 stmk1 address: fffe7h after reset: ffh r/w symbol <7> 6 5 4 <3> <2> <1> <0> mk1h tmmk04 1 1 1 krmk rtcimk rtcmk admk address: fffd4h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> mk2l pmk10 pmk9 pmk8 pmk7 pmk6 tmmk07 tmmk06 tmmk05 address: fffd5h after reset: ffh r/w symbol 7 6 5 4 3 2 1 <0> mk2h 1 1 1 1 1 1 1 pmk11 xxmkx interrupt servicing control 0 interrupt servicing enabled 1 interrupt servicing disabled caution be sure to set bits 4 to 6 of mk1h and bits 1 to 7 of mk2h to 1. chapter 15 interrupt functions user?s manual u17854ej6v0ud 546 (3) priority specification flag registers (pr00l, pr 00h, pr01l, pr01h, pr02l, pr02h, pr10l, pr10h, pr11l, pr11h, pr12l, pr12h) the priority specification flag regist ers are used to set the corresponding maskable interrupt priority level. a priority level is set by using the pr0xy and pr1xy regi sters in combination (xy = 0l, 0h, 1l, 1h, 2l, or 2h). pr00l, pr00h, pr01l, pr01h, pr02l, pr02h, pr10 l, pr10h, pr11l, pr11h, pr12l, and pr12h can be set by a 1-bit or 8-bit memory manipulation instruction. if pr00l and pr00h, pr01l and pr01h, pr02l and pr02h, pr10l and pr10h, pr11l and pr11h, and pr12l and pr12h are combined to form 16-bit registers pr00, pr01, pr02, pr10, pr11, and pr12, they can be se t by a 16-bit memory manipulation instruction. reset signal generation sets these registers to ffh. remark if an instruction that writes data to this register is execut ed, the number of instru ction execution clocks increases by 2 clocks. figure 15-4. format of priority specification flag registers (pr00l, pr00h, pr01l, pr01h, pr02l, pr02h, pr 10l, pr10h, pr11l, pr11h, pr12l, pr12h) (1/2) address: fffe8h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> pr00l ppr05 ppr04 ppr03 ppr02 ppr01 ppr00 lvipr0 wdtipr0 address: fffech after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> pr10l ppr15 ppr14 ppr13 ppr12 ppr11 ppr10 lvipr1 wdtipr1 address: fffe9h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> pr00h srepr00 srpr00 csipr000 stpr00 dmapr01 dmapr00 srepr03 srpr03 stpr03 address: fffedh after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> pr10h srepr10 srpr10 csipr100 stpr10 dmapr11 dmapr10 srepr13 srpr13 stpr13 address: fffeah after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> pr01l tmpr003 tmpr002 tmpr001 tmpr000 iicpr00 srepr01 srpr01 csipr010 iicpr010 stpr01 address: fffeeh after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> pr11l tmpr103 tmpr102 tmpr101 tmpr100 iicpr10 srepr11 srpr11 csipr110 iicpr110 stpr11 chapter 15 interrupt functions user?s manual u17854ej6v0ud 547 figure 15-4. format of priority specification flag registers (pr00l, pr00h, pr01l, pr01h, pr02l, pr02h, pr 10l, pr10h, pr11l, pr11h, pr12l, pr12h) (2/2) address: fffebh after reset: ffh r/w symbol <7> 6 5 4 <3> <2> <1> <0> pr01h tmpr004 1 1 1 krpr0 rtcipr0 rtcpr0 adpr0 address: fffefh after reset: ffh r/w symbol <7> 6 5 4 <3> <2> <1> <0> pr11h tmpr104 1 1 1 krpr1 rtcipr1 rtcpr1 adpr1 address: fffd8h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> pr02l ppr010 ppr09 ppr08 ppr07 ppr06 tmpr007 tmpr006 tmpr005 address: fffdch after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> pr12l ppr110 ppr19 ppr18 ppr17 ppr16 tmpr107 tmpr106 tmpr105 address: fffd9h after reset: ffh r/w symbol 7 6 5 4 3 2 1 <0> pr02h 1 1 1 1 1 1 1 ppr011 address: fffddh after reset: ffh r/w symbol 7 6 5 4 3 2 1 <0> pr12h 1 1 1 1 1 1 1 ppr111 xxpr1x xxpr0x priority level selection 0 0 specify level 0 (high priority level) 0 1 specify level 1 1 0 specify level 2 1 1 specify level 3 (low priority level) caution be sure to set bits 4 to 6 of pr01h and pr11h to 1. be sure to set bits 1 to 7 of pr02h and pr12h to 1. chapter 15 interrupt functions user?s manual u17854ej6v0ud 548 (4) external interrupt rising edge enable registers (egp0, egp1), ext ernal interrupt falling edge enable registers (egn0, egn1) these registers specify the valid edge for intp0 to intp11. egp0, egp1, egn0, and egn1 can be set by a 1-bi t or 8-bit memory manipulation instruction. reset signal generation clears these registers to 00h. figure 15-5. format of external interrupt ri sing edge enable registers (egp0, egp1) and external interrupt falling e dge enable registers (egn0, egn1) address: fff38h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 egp0 egp7 egp6 egp5 egp4 egp3 egp2 egp1 egp0 address: fff39h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 egn0 egn7 egn6 egn5 egn4 egn3 egn2 egn1 egn0 address: fff3ah after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 egp1 0 0 0 0 egp11 egp10 egp9 egp8 address: fff3bh after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 egn1 0 0 0 0 egn11 egn10 egn9 egn8 egpn egnn intpn pin valid edge selection (n = 0 to 11) 0 0 edge detection disabled 0 1 falling edge 1 0 rising edge 1 1 both rising and falling edges table 15-3 shows the ports corresponding to egpn and egnn. chapter 15 interrupt functions user?s manual u17854ej6v0ud 549 table 15-3. ports correspo nding to egpn and egnn detection enable register edge detection port interrupt request signal egp0 egn0 p120 intp0 egp1 egn1 p50 intp1 egp2 egn2 p51 intp2 egp3 egn3 p30 intp3 egp4 egn4 p31 intp4 egp5 egn5 p16 intp5 egp6 egn6 p140 intp6 egp7 egn7 p141 intp7 egp8 egn8 p74 intp8 egp9 egn9 p75 intp9 egp10 egn10 p76 intp10 egp11 egn11 p77 intp11 caution select the port mode by clearing eg pn and egnn to 0 because an edge may be detected when the external interrupt func tion is switched to the port function. remark n = 0 to 11 chapter 15 interrupt functions user?s manual u17854ej6v0ud 550 (5) program status word (psw) the program status word is a register used to hold the instruction exec ution result and the current status for an interrupt request. the ie flag that sets maskable in terrupt enable/disable and the isp0 and isp1 flags that controls multiple interrupt servicing are mapped to the psw. besides 8-bit read/write, this register can carry out op erations using bit manipulation instructions and dedicated instructions (ei and di). when a vect ored interrupt request is acknowledged, if the brk instruction is executed, the contents of the psw are aut omatically saved into a stack and the ie flag is reset to 0. if a maskable interrupt request is acknowledged, the contents of the priority specification flag of t he acknowledged interrupt are transferred to the isp0 and isp1 flags. the psw content s are also saved into the stack with the push psw instruction. they are restored from the stack with the reti, re tb, and pop psw instructions. reset signal generation sets psw to 06h. figure 15-6. configuration of program status word <7> ie <6> z <5> rbs1 <4> ac <3> rbs0 <2> isp1 <1> isp0 0 cy psw after reset 06h isp1 0 0 1 1 enables interrupt of level 0 (while interrupt of level 1 or 0 is being serviced). enables interrupt of level 0 and 1 (while interrupt of level 2 is being serviced). enables interrupt of level 0 to 2 (while interrupt of level 3 is being serviced). enables all interrupts (waits for acknowledgment of an interrupt). ie 0 1 disabled enabled priority of interrupt currently being serviced interrupt request acknowledgment enable/disable used when normal instruction is executed isp0 0 1 0 1 chapter 15 interrupt functions user?s manual u17854ej6v0ud 551 15.4 interrupt servicing operations 15.4.1 maskable interrupt acknowledgment a maskable interrupt becomes acknowledgeable when the in terrupt request flag is set to 1 and the mask (mk) flag corresponding to that interrupt request is cleared to 0. a vectored interrupt request is acknowledged if interrupts are in the interrupt enabled state (when the ie flag is set to 1). however, a low-priority interrupt request is not acknowledged during servicing of a higher priority interrupt request. the times from generation of a maskable interrupt request until vectored interr upt servicing is performed are listed in table 15-4 below. for the interrupt request acknowledgment timing, see figures 15-8 and 15-9 . table 15-4. time from generation of maskable inte rrupt until servicing minimum time maximum time note servicing time 9 clocks 14 clocks note if an interrupt request is generated just before the ret instruction, the wait time becomes longer. remark 1 clock: 1/f clk (f clk : cpu clock) if two or more maskable interrupt requests are generated simultaneously, the request with a higher priority level specified in the priority specification flag is acknowledge d first. if two or more interrupts requests have the same priority level, the request with the highest default priority is acknowledged first. an interrupt request that is held pending is a cknowledged when it becomes acknowledgeable. figure 15-7 shows the interrupt request acknowledgment algorithm. if a maskable interrupt request is acknowledged, the content s are saved into the stacks in the order of psw, then pc, the ie flag is reset (0), and the contents of the pr iority specification flag corresponding to the acknowledged interrupt are transferred to the isp1 and isp0 flags. the ve ctor table data determined for each interrupt request is the loaded into the pc and branched. restoring from an interrupt is possible by using the reti instruction. chapter 15 interrupt functions user?s manual u17854ej6v0ud 552 figure 15-7. interrupt request acknowledgment processing algorithm yes no yes no yes no no yes no ie = 1? vectored interrupt servicing start if = 1? mk = 0? ( pr 1, pr 0) (isp1, isp0) yes (interrupt request generation) no (low priority) interrupt request held pending interrupt request held pending interrupt request held pending interrupt request held pending interrupt request held pending higher priority than other interrupt requests simultaneously generated? higher default priority note than other interrupt requests simultaneously generated? if: interrupt request flag mk: interrupt mask flag pr0: priority specification flag 0 pr1: priority specification flag 1 ie: flag that controls acknowledgment of mask able interrupt request (1 = enable, 0 = disable) isp0, isp1: flag that indicates the priority leve l of the interrupt currently being serviced (see figure 15-6 ) note for the default priority, refer to table 15-1 interrupt source list . chapter 15 interrupt functions user?s manual u17854ej6v0ud 553 figure 15-8. interrupt request ac knowledgment timing (minimum time) 9 clocks instruction instruction cpu processing if 6 clocks psw and pc saved, jump to interrupt servicing interrupt servicing program remark 1 clock: 1/f clk (f clk : cpu clock) figure 15-9. interrupt request ac knowledgment timing (maximum time) 14 clocks instruction ret instruction cpu processing if 6 clocks 6 clocks psw and pc saved, jump to interrupt servicing interrupt servicing program remark 1 clock: 1/f clk (f clk : cpu clock) 15.4.2 software interrupt request acknowledgment a software interrupt acknowledge is acknowledged by brk instruction execution. so ftware interrupts cannot be disabled. if a software interrupt request is ackno wledged, the cont ents are saved into the stacks in the order of the program status word (psw), then program counter (pc), the ie flag is reset (0), and the contents of the vect or table (0007eh, 0007fh) are loaded into the pc and branched. restoring from a software interrupt is possi ble by using the retb instruction. caution do not use the reti instruction fo r restoring from the software interrupt. chapter 15 interrupt functions user?s manual u17854ej6v0ud 554 15.4.3 multiple interrupt servicing multiple interrupt servicing occurs when another interrupt re quest is acknowledged during execution of an interrupt. multiple interrupt servicing does not occur unless the inte rrupt request acknowledgment enabled state is selected (ie = 1). when an interrupt request is acknowledged, inte rrupt request acknowledgment becomes disabled (ie = 0). therefore, to enable multiple interrupt servicing, it is necessary to set (1) the ie flag with the ei instruction during interrupt servicing to enable interrupt acknowledgment. moreover, even if interrupts are enabled, multiple interr upt servicing may not be enabled, this being subject to interrupt priority control. two types of priority control are available: default priority control and programmable priority control. programmable priority control is used for multiple interrupt servicing. in the interrupt enabled state, if an in terrupt request with a priority equal to or higher than that of the interrupt currently being serviced is generated, it is acknowledged for mu ltiple interrupt servicing. if an interrupt with a priority lower than that of the interrupt currently being serviced is generated during interrupt servicing, it is not acknowledged for multiple interrupt servicing. inte rrupt requests that are not enabled because interrupts are in the interrupt disabled state or because they have a lower prio rity are held pending. when servicing of the current interrupt ends, the pending interrupt request is acknowledged following execution of at least one main processing instruction execution. table 15-5 shows relationship between interrupt requests enabled for multiple interrupt servicing and figure 15-10 shows multiple interrupt servicing examples. table 15-5. relationship between interrupt requests enabled for multiple interrupt servicing during interrupt servicing maskable interrupt request priority level 0 (pr = 00) priority level 1 (pr = 01) priority level 2 (pr = 10) priority level 3 (pr = 11) multiple interrupt request interrupt being serviced ie = 1 ie = 0 ie = 1 ie = 0 ie = 1 ie = 0 ie = 1 ie = 0 software interrupt request isp1 = 0 isp0 = 0 { { isp1 = 0 isp0 = 1 { { { isp1 = 1 isp0 = 0 { { { { maskable interrupt isp1 = 1 isp0 = 1 { { { { { software interrupt { { { { { remarks 1. { : multiple interrupt servicing enabled 2. : multiple interrupt servicing disabled 3. isp0, isp1, and ie are flags contained in the psw. isp1 = 0, isp0 = 0: an interrupt of level 1 or level 0 is being serviced. isp1 = 0, isp0 = 1: an interrupt of level 2 is being serviced. isp1 = 1, isp0 = 0: an interrupt of level 3 is being serviced. isp1 = 1, isp0 = 1: wait for an interrupt acknowledgment. ie = 0: interrupt request acknowledgment is disabled. ie = 1: interrupt request acknowledgment is enabled. 4. pr is a flag contained in pr00l, pr00h, pr 01l, pr01h, pr02l, pr02h, pr10l, pr10h, pr11l, pr11h, pr12l, and pr12h. pr = 00: specify level 0 with pr1 = 0, pr0 = 0 (higher priority level) pr = 01: specify level 1 with pr1 = 0, pr0 = 1 pr = 10: specify level 2 with pr1 = 1, pr0 = 0 pr = 11: specify level 1 with pr1 = 1, pr0 = 1 (lower priority level) chapter 15 interrupt functions user?s manual u17854ej6v0ud 555 figure 15-10. examples of multip le interrupt se rvicing (1/2) example 1. multiple inte rrupt servicing occurs twice main processing intxx servicing intyy servicing intzz servicing ei ei ei reti reti reti intxx (pr = 11) intyy (pr = 10) intzz (pr = 01) ie = 0 ie = 0 ie = 0 ie = 1 ie = 1 ie = 1 during servicing of interrupt intxx, two interrupt re quests, intyy and intzz, are acknowledged, and multiple interrupt servicing takes place. before each interrupt re quest is acknowledged, the ei instruction must always be issued to enable interrupt request acknowledgment. example 2. multiple interrupt servicing does not occur due to priority control main processing intxx servicing intyy servicing intxx (pr = 10) intyy (pr = 11) ei reti ie = 0 ie = 0 ei 1 instruction execution reti ie = 1 ie = 1 interrupt request intyy issued during servicing of interrupt intxx is not acknowledged because its priority is lower than that of intxx, and mu ltiple interrupt servicing does not take place. the intyy interrupt request is held pending, and is acknowledged following execution of one main processing instruction. pr = 00: specify level 0 with pr1 = 0, pr0 = 0 (higher priority level) pr = 01: specify level 1 with pr1 = 0, pr0 = 1 pr = 10: specify level 2 with pr1 = 1, pr0 = 0 pr = 11: specify level 1 with pr1 = 1, pr0 = 1 (lower priority level) ie = 0: interrupt request acknowledgment is disabled ie = 1: interrupt request acknowledgment is enabled. chapter 15 interrupt functions user?s manual u17854ej6v0ud 556 figure 15-10. examples of multip le interrupt se rvicing (2/2) example 3. multiple interrupt servicing do es not occur because inte rrupts are not enabled main processing intxx servicing intyy servicing ei 1 instruction execution reti reti intxx (pr = 11) intyy (pr = 00) ie = 0 ie = 0 ie = 1 ie = 1 interrupts are not enabled during servicing of interrupt int xx (ei instruction is not issued), therefore, interrupt request intyy is not acknowledged and multiple interrupt serv icing does not take place. the intyy interrupt request is held pending, and is acknowledged following ex ecution of one main processing instruction. pr = 00: specify level 0 with pr1 = 0, pr0 = 0 (higher priority level) pr = 01: specify level 1 with pr1 = 0, pr0 = 1 pr = 10: specify level 2 with pr1 = 1, pr0 = 0 pr = 11: specify level 1 with pr1 = 1, pr0 = 1 (lower priority level) ie = 0: interrupt request acknowledgment is disabled ie = 1: interrupt request acknowledgment is enabled. chapter 15 interrupt functions user?s manual u17854ej6v0ud 557 15.4.4 interrupt request hold there are instructions where, even if an interrupt request is issued for them while another instruction is being executed, request acknowledgment is held pending until the end of execution of the ne xt instruction. these instructions (interrupt request hol d instructions) are listed below. ? mov psw, #byte ? mov psw, a ? mov1 psw. bit, cy ? set1 psw. bit ? clr1 psw. bit ? retb ? reti ? pop psw ? btclr psw. bit, $addr8 ? ei ? di ? skc ? sknc ? skz ? sknz ? manipulation instructions for the if0l, if0h, if1l, if1h, if2l, if2h, mk0l, mk0h, mk1l, mk1h, mk2l, mk2h, pr00l, pr00h, pr01l, pr01h, pr02l, pr02h, pr 10l, pr10h, pr11l, pr11h, pr12l, and pr12h registers. caution the brk instruction is not one of the above-listed interrupt re quest hold instructions. however, the software interrupt activated by executing the brk instruction causes the ie flag to be cleared. therefore, even if a maskable interrupt re quest is generated during execution of the brk instruction, the interrupt re quest is not acknowledged. figure 15-11 shows the timing at which interrupt requests are held pending. figure 15-11. interrupt request hold instruction n instruction m psw and pc saved, jump to interrupt servicing interrupt servicing program cpu processing if remarks 1. instruction n: interrupt request hold instruction 2. instruction m: instruction other t han interrupt request hold instruction 3. the pr (priority level) values do not affect the operation of if (interrupt request). user?s manual u17854ej6v0ud 558 chapter 16 key interrupt function 16.1 functions of key interrupt a key interrupt (intkr) can be generated by setting t he key return mode register (krm) and inputting a falling edge to the key interrupt input pins (kr0 to kr7). table 16-1. assignment of k ey interrupt detection pins flag description krm0 controls kr0 signal in 1-bit units. krm1 controls kr1 signal in 1-bit units. krm2 controls kr2 signal in 1-bit units. krm3 controls kr3 signal in 1-bit units. krm4 controls kr4 signal in 1-bit units. krm5 controls kr5 signal in 1-bit units. krm6 controls kr6 signal in 1-bit units. krm7 controls kr7 signal in 1-bit units. 16.2 configuration of key interrupt the key interrupt includes the following hardware. table 16-2. configuration of key interrupt item configuration control register key return mode register (krm) figure 16-1. block diag ram of key interrupt intkr key return mode register (krm) krm7 krm6 krm5 krm4 krm3 krm2 krm1 krm0 kr7 kr6 kr5 kr4 kr3 kr2 kr1 kr0 chapter 16 key interrupt function user?s manual u17854ej6v0ud 559 16.3 register controlling key interrupt (1) key return mode register (krm) this register controls the krm0 to krm7 bits using the kr0 to kr7 signals, respectively. krm can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. figure 16-2. format of key return mode register (krm) krm7 does not detect key interrupt signal detects key interrupt signal krmn 0 1 key interrupt mode control krm krm6 krm5 krm4 krm3 krm2 krm1 krm0 address: fff37h after reset: 00h r/w symbol 765432 0 cautions 1. if any of the krm0 to krm7 bits used is set to 1, set bits 0 to 7 (pu70 to pu77) of the corresponding pull-up resistor register 7 (pu7) to 1. 2. if krm is changed, the interrupt request flag may be set. therefore, disable interrupts and then change the krm register. clear the in terrupt request flag and enable interrupts. 3. the bits not used in the key inte rrupt mode can be used as normal ports. remark n = 0 to 7 user?s manual u17854ej6v0ud 560 chapter 17 standby function 17.1 standby function and configuration 17.1.1 standby function the standby function reduces the operat ing current of the system, and the fo llowing two modes are available. (1) halt mode halt instruction execution se ts the halt mode. in the halt mode, the cpu operation clock is stopped. if the high-speed system clock oscillator, internal high-speed oscillator, or subsystem clock oscillator is operating before the halt mode is set, oscillation of each clock c ontinues. in this mode, the operating current is not decreased as much as in the stop m ode, but the halt mode is effective fo r restarting operation immediately upon interrupt request generation and carry ing out intermittent operations frequently. (2) stop mode stop instruction execution sets the stop mode. in the stop mode, the high-speed system clock oscillator and internal high-speed oscillator stop, stopping the whole system, thereby considerably reducing the cpu operating current. because this mode can be cleared by an interrupt reques t, it enables intermittent operations to be carried out. however, because a wait time is required to secure th e oscillation stabilization time after the stop mode is released when the x1 clock is selected, select the halt mode if it is necessary to start processing immediately upon interrupt request generation. in either of these two modes, all the contents of registers, flags and data me mory just before the standby mode is set are held. the i/o port output latches an d output buffer statuses are also held. cautions 1. the stop mode can be used only when the cpu is operating on the main system clock. the stop mode cannot be set while the cpu ope rates with the subsystem clock. the halt mode can be used when the cpu is operating on either the main system clock or the subsystem clock. 2. when shifting to the stop mode, be su re to stop the peripher al hardware operation operating with main system clock be fore executing stop instruction. 3. the following sequence is r ecommended for operating current reduction of the a/d converter when the standby function is used: first cl ear bit 7 (adcs) and bit 0 (adce) of the a/d converter mode register (adm) to 0 to stop the a/d conversion opera tion, and then execute the stop instruction. 4. it can be selected by the option byte whet her the internal low-sp eed oscillator continues oscillating or stops in the ha lt or stop mode. for details , see chapter 22 option byte. 17.1.2 registers controlling standby function the standby function is controlled by the following two registers. ? oscillation stabilization time c ounter status register (ostc) ? oscillation stabilization time select register (osts) remark for the registers that start, st op, or select the clock, see chapter 5 clock generator . chapter 17 standby function user?s manual u17854ej6v0ud 561 (1) oscillation stabilization time c ounter status register (ostc) this is the register that indicates the count status of the x1 clock osci llation stabilization time counter. the x1 clock oscillation stabilization time can be checked in the following case, ? if the x1 clock starts oscillation while the internal high -speed oscillation clock or s ubsystem clock is being used as the cpu clock. ? if the stop mode is entered and then re leased while the internal high-speed oscillation clock is being used as the cpu clock with the x1 clock oscillating. ostc can be read by a 1-bit or 8-bit memory manipulation instruction. when reset is released (reset by reset input, poc, lv i, wdt, and executing an illegal instruction), the stop instruction and mstop (bit 7 of csc regist er) = 1 clear this register to 00h. figure 17-1. format of oscillation stabilizati on time counter status register (ostc) address: fffa2h after reset: 00h r symbol 7 6 5 4 3 2 1 0 ostc most 8 most 9 most 10 most 11 most 13 most 15 most 17 most 18 oscillation stabilization time status most 8 most 9 most 10 most 11 most 13 most 15 most 17 most 18 f x = 10 mhz f x = 20 mhz 0 0 0 0 0 0 0 0 2 8 /f x max. 25.6 s max. 12.8 s max. 1 0 0 0 0 0 0 0 2 8 /f x min. 25.6 s min. 12.8 s min. 1 1 0 0 0 0 0 0 2 9 /f x min. 51.2 s min. 25.6 s min. 1 1 1 0 0 0 0 0 2 10 /f x min. 102.4 s min. 51.2 s min. 1 1 1 1 0 0 0 0 2 11 /f x min. 204.8 s min. 102.4 s min. 1 1 1 1 1 0 0 0 2 13 /f x min. 819.2 s min. 409.6 s min. 1 1 1 1 1 1 0 0 2 15 /f x min. 3.27 ms min. 1.64 ms min. 1 1 1 1 1 1 1 0 2 17 /f x min. 13.11 ms min. 6.55 ms min. 1 1 1 1 1 1 1 1 2 18 /f x min. 26.21 ms min. 13.11 ms min. cautions 1. after the above time has elapsed, the bits are set to 1 in order from most8 and remain 1. 2. the oscillation stabilization time counter counts up to the oscillation stabilization time set by osts. if the st op mode is entered and then released while the internal high-speed oscillation clock is being used as the cpu clock, set the oscillation stabilization time as follows. ? desired ostc oscillation stabilization time oscillation stabilization time set by osts note, therefore, that only the status up to the oscillation stabilization time set by osts is set to ostc afte r stop mode is released. 3. the x1 clock oscillation stabilization wa it time does not include the time until clock oscillation starts (?a? below). stop mode release x1 pin voltage waveform a remark f x : x1 clock oscillation frequency chapter 17 standby function user?s manual u17854ej6v0ud 562 (2) oscillation stabilization time select register (osts) this register is used to select the x1 clock oscillation stabilization wait time when the stop mode is released. when the x1 clock is selected as the cpu clock, the operation waits for the time set using osts after the stop mode is released. when the internal high-speed oscillation clock is selected as the cpu clock, confirm with ostc that the desired oscillation stabilization time has elaps ed after the stop mode is released. the oscillation stabilization time can be checked up to the time set using ostc. osts can be set by an 8-bit memory manipulation instruction. reset signal generation sets this register to 07h. figure 17-2. format of oscillation stabiliz ation time select register (osts) address: fffa3h after reset: 07h r/w symbol 7 6 5 4 3 2 1 0 osts 0 0 0 0 0 osts2 osts1 osts0 oscillation stabilization time selection osts2 osts1 osts0 f x = 10 mhz f x = 20 mhz 0 0 0 2 8 /f x 25.6 s setting prohibited 0 0 1 2 9 /f x 51.2 s 25.6 s 0 1 0 2 10 /f x 102.4 s 51.2 s 0 1 1 2 11 /f x 204.8 s 102.4 s 1 0 0 2 13 /f x 819.2 s 409.6 s 1 0 1 2 15 /f x 3.27 ms 1.64 ms 1 1 0 2 17 /f x 13.11 ms 6.55 ms 1 1 1 2 18 /f x 26.21 ms 13.11 ms cautions 1. to set the stop mode when the x1 cl ock is used as the cpu cl ock, set osts before executing the stop instruction. 2. setting the oscillation stabilization time to 20 s or less is prohibited. 3. before changing the setting of the osts regi ster, confirm that the count operation of the ostc register is completed. 4. do not change the value of the osts regi ster during the x1 clock oscillation stabilization time. 5. the oscillation stabilization time counter c ounts up to the oscillation stabilization time set by osts. if the stop mode is entered and then released while th e internal high-speed oscillation clock is being used as the cpu clo ck, set the oscillation stabilization time as follows. ? desired ostc oscillation stabilization time oscillation stabilization time set by osts note, therefore, that only the status up to the oscillation stabilization time set by osts is set to ostc after stop mode is released. 6. the x1 clock oscillation stabilization wait time does not include the time until clock oscillation starts (?a? below). stop mode release x1 pin voltage waveform a remark f x : x1 clock oscillation frequency chapter 17 standby function user?s manual u17854ej6v0ud 563 17.2 standby function operation 17.2.1 halt mode (1) halt mode the halt mode is set by executing t he halt instruction. halt mode can be set regardless of whether the cpu clock before the setting was the high-spe ed system clock, internal high-spee d oscillation clock, or subsystem clock. the operating statuses in t he halt mode are shown below. chapter 17 standby function user?s manual u17854ej6v0ud 564 table 17-1. operating statuses in halt mode (1/2) when halt instruction is executed while cpu is operating on main system clock halt mode setting item when cpu is operating on internal high-speed oscillation clock (f ih ) when cpu is operating on x1 clock (f x ) when cpu is operating on external main system clock (f ex ) system clock clock supply to the cpu is stopped f ih operation continues (cannot be stopped) status before halt mode was set is retained f x operation continues (cannot be stopped) cannot operate main system clock f ex status before halt mode was set is retained cannot operate operation continues (cannot be stopped) subsystem clock f xt status before halt mode was set is retained f il set by bits 0 (wdstbyon) and 4 (wton) of option byte (000c0h) ? wton = 0: stops ? wton = 1 and wdstbyon = 1: oscillates ? wton = 1 and wdstbyon = 0: stops cpu operation stopped flash memory operable in lo w-current consumption mode ram operation stopped. however, status before halt mode was set is retained at voltage higher than poc detection voltage. port (latch) status before halt mode was set is retained timer array unit (tau) real-time counter (rtc) operable watchdog timer set by bits 0 (wdstbyon) and 4 (wton) of option byte (000c0h) ? wton = 0: stops ? wton = 1 and wdstbyon = 1: operates ? wton = 1 and wdstbyon = 0: stops clock output/buzzer output a/d converter serial array unit (sau) serial interface (iic0) operable multiplier operation stopped dma controller power-on-clear function low-voltage detection function external interrupt operable remark f ih : internal high-speed oscillation clock f x : x1 clock f ex : external main system clock f xt : xt1 clock f il : internal low-speed oscillation clock chapter 17 standby function user?s manual u17854ej6v0ud 565 table 17-1. operating statuses in halt mode (2/2) remark f ih : internal high-speed oscillation clock f x : x1 clock f ex : external main system clock f xt : xt1 clock f il : internal low-speed oscillation clock when halt instruction is executed while cpu is operating on subsystem clock halt mode setting item when cpu is operating on xt1 clock (f xt ) system clock clock supply to the cpu is stopped f ih f x status before halt mode was set is retained main system clock f ex operates or stops by external clock input subsystem clock f xt operation continues (cannot be stopped) f il set by bits 0 (wdstbyon) and 4 (wton) of option byte (000c0h) ? wton = 0: stops ? wton = 1 and wdstbyon = 1: oscillates ? wton = 1 and wdstbyon = 0: stops cpu operation stopped flash memory operable in lo w-current consumption mode ram operation stopped. however, status before halt mode was set is retained at voltage higher than poc detection voltage. port (latch) status before halt mode was set is retained timer array unit (tau) real-time counter (rtc) operable watchdog timer set by bits 0 (wdstbyon) and 4 (wton) of option byte (000c0h) ? wton = 0: stops ? wton = 1 and wdstbyon = 1: operates ? wton = 1 and wdstbyon = 0: stops clock output/buzzer output operable a/d converter cannot operate serial array uni t (sau) operable serial interface (iic0) cannot operate multiplier operation stopped dma controller power-on-clear function low-voltage detection function external interrupt operable chapter 17 standby function user?s manual u17854ej6v0ud 566 (2) halt mode release the halt mode can be released by the following two sources. (a) release by unmasked interrupt request when an unmasked interrupt request is generated, the halt mode is released. if interrupt acknowledgment is enabled, vectored interrupt servicing is carried out. if interrupt acknowledgment is disabled, the next address instruction is executed. figure 17-3. halt mode release by interrupt request generation halt instruction wait note operating mode halt mode operating mode oscillation high-speed system clock, internal high-speed oscillation clock, or subsystem clock status of cpu standby release signal interrupt request note the wait time is as follows: ? when vectored interrupt servicing is carried out: 10 to 12 clocks ? when vectored interrupt servicing is not carried out: 5 or 6 clocks remark the broken lines indicate the case when the interrupt request which has released the standby mode is acknowledged. chapter 17 standby function user?s manual u17854ej6v0ud 567 (b) release by reset signal generation when the reset signal is generated, halt mode is re leased, and then, as in the case with a normal reset operation, the program is executed after br anching to the reset vector address. figure 17-4. halt mode release by reset (1) when high-speed system clock is used as cpu clock halt instruction reset signal high-speed system clock (x1 oscillation) halt mode reset period oscillates oscillation stopped oscillates status of cpu normal operation (high-speed system clock) oscillation stabilization time (2 8 /f x to 2 11 /f x , 2 13 /f x , 2 15 /f x , 2 17 /f x , 2 18 /f x ) normal operation (internal high-speed oscillation clock) oscillation stopped starting x1 oscillation is specified by software. reset processing (1.92 to 6.17 ms) (2) when internal high-speed osc illation clock is used as cpu clock halt instruction reset signal internal high-speed oscillation clock normal operation (internal high-speed oscillation clock) halt mode reset period normal operation (internal high-speed oscillation clock) oscillates oscillation stopped oscillates status of cpu wait for oscillation accuracy stabilization reset processing (1.92 to 6.17 ms) (3) when subsystem clo ck is used as cpu clock halt instruction reset signal subsystem clock (xt1 oscillation) normal operation (subsystem clock) halt mode reset period normal operation mode (internal high-speed oscillation clock) oscillates oscillation stopped oscillates status of cpu oscillation stopped starting xt1 oscillation is specified by software. reset processing (1.92 to 6.17 ms) remark f x : x1 clock oscillation frequency chapter 17 standby function user?s manual u17854ej6v0ud 568 17.2.2 stop mode (1) stop mode setting and operating statuses the stop mode is set by executing t he stop instruction, and it can be se t only when the cpu clock before the setting was the main system clock. caution because the interrupt request signal is used to clear the standby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is immediately cleared if set. thus, the stop mode is reset to the halt mode immediately after execution of the stop instruction and the system returns to the operating mode as soon as the wait time set using the oscillation stabilizat ion time select register (osts) has elapsed. the operating statuses in t he stop mode are shown below. chapter 17 standby function user?s manual u17854ej6v0ud 569 table 17-2. operating statuses in stop mode when stop instruction is executed while cpu is operating on main system clock stop mode setting item when cpu is operating on internal high-speed oscillation clock (f ih ) when cpu is operating on x1 clock (f x ) when cpu is operating on external main system clock (f ex ) system clock clock supply to the cpu is stopped f ih f x main system clock f ex stopped subsystem clock f xt status before stop mode was set is retained f il set by bits 0 (wdstbyon) and 4 (wton) of option byte (000c0h) ? wton = 0: stops ? wton = 1 and wdstbyon = 1: oscillates ? wton = 1 and wdstbyon = 0: stops cpu operation stopped flash memory operation stopped ram operation stopped. however, status before st op mode was set is retained at voltage higher than poc detection voltage. port (latch) status before stop mode was set is retained timer array unit (tau ) operation stopped real-time counter (rtc) operable watchdog timer set by bits 0 (wdstbyon) and 4 (wton) of option byte (000c0h) ? wton = 0: stops ? wton = 1 and wdstbyon = 1: operates ? wton = 1 and wdstbyon = 0: stops clock output/buzzer output oper able only when subsystem clock is selected as the count clock a/d converter serial array unit (sau) serial interface (iic0) multiplier dma controller operation stopped power-on-clear function low-voltage detection function external interrupt operable remark f ih : internal high-speed oscillation clock f x : x1 clock f ex : external main system clock f xt : xt1 clock f il : internal low-speed oscillation clock chapter 17 standby function user?s manual u17854ej6v0ud 570 cautions 1. to use the peripheral ha rdware that stops operation in the stop mode, and the peripheral hardware for which the clock that stops oscillati ng in the stop mode after the stop mode is released, restart the peripheral hardware. 2. to stop the internal low-speed oscillation clo ck in the stop mode, use an option byte to stop the watchdog timer operation in the halt/stop m ode (bit 0 (wdstbyon) of 000c0h = 0), and then execute the stop instruction. 3. to shorten oscillation stabiliz ation time after the stop mode is released when the cpu operates with the high-speed system clock (x1 oscillation) , temporarily switch the cpu clock to the internal high-speed oscillation cl ock before the next execution of the stop instruction. before changing the cpu clock from the internal high-speed oscillation clock to the hi gh-speed system clock (x1 oscillation) after the stop mode is released, check the oscilla tion stabilization time with the oscillation stabilization time counter status register (ostc). (2) stop mode release figure 17-5. operation timing wh en stop mode is released stop mode stop mode release high-speed system clock (x1 oscillation) high-speed system clock (external clock input) internal high-speed oscillation clock high-speed system clock (x1 oscillation) is selected as cpu clock when stop instruction is executed high-speed system clock (external clock input) is selected as cpu clock when stop instruction is executed internal high-speed oscillation clock is selected as cpu clock when stop instruction is executed wait for oscillation accuracy stabilization halt status (oscillation stabilization time set by osts) note 1 clock switched by software clock switched by software high-speed system clock high-speed system clock wait note 2 wait note 2 supply of the cpu clock is stopped (23 to 61 s) high-speed system clock supply of the cpu clock is stopped (23 to 61 s) internal high-speed oscillation clock notes 1. when the oscillation stabilization time set by osts is equal to or shorter than 61 s, the halt status is retained to a maximum of "61 s + wait time." 2. the wait time is as follows: ? when vectored interrupt servicing is carried out: 10 to 12 clocks ? when vectored interrupt servicing is not carried out: 5 or 6 clocks the stop mode can be released by the following two sources. chapter 17 standby function user?s manual u17854ej6v0ud 571 (a) release by unmasked interrupt request when an unmasked interrupt request is generated, the stop mode is released. after the oscillation stabilization time has elapsed, if interrupt acknowledg ment is enabled, vectored interrupt servicing is carried out. if interrupt acknowledgment is disabled, the next address instruction is executed. figure 17-6. stop mode release by interrupt request generation (1/2) (1) when high-speed system clock (x 1 oscillation) is used as cpu clock normal operation (high-speed system clock) normal operation (high-speed system clock) oscillates oscillates stop instruction stop mode wait note (set by osts) standby release signal oscillation stabilization wait (halt mode status) oscillation stopped high-speed system clock (x1 oscillation) status of cpu oscillation stabilization time (set by osts) interrupt request (2) when high-speed system clock (external clock in put) is used as cpu clock interrupt request stop instruction standby release signal status of cpu high-speed system clock (external clock input) oscillates normal operation (high-speed system clock) stop mode oscillation stopped oscillates normal operation (high-speed system clock) wait note supply of the cpu clock is stopped (23 to 61 s) note the wait time is as follows: ? when vectored interrupt servicing is carried out: 10 to 12 clocks ? when vectored interrupt servicing is not carried out: 5 or 6 clocks remark the broken lines indicate the case when the inte rrupt request that has re leased the standby mode is acknowledged. chapter 17 standby function user?s manual u17854ej6v0ud 572 figure 17-6. stop mode release by interrupt request generation (2/2) (3) when internal high-speed osc illation clock is used as cpu clock standby release signal status of cpu internal high-speed oscillation clock normal operation (internal high-speed oscillation clock) oscillates stop mode oscillation stopped wait for oscillation accuracy stabilization interrupt request stop instruction wait note normal operation (internal high-speed oscillation clock) supply of the cpu clock is stopped (23 to 61 s) oscillates note the wait time is as follows: ? when vectored interrupt servicing is carried out: 10 to 12 clocks ? when vectored interrupt servicing is not carried out: 5 or 6 clocks remark the broken lines indicate the case when the inte rrupt request that has re leased the standby mode is acknowledged. chapter 17 standby function user?s manual u17854ej6v0ud 573 (b) release by reset signal generation when the reset signal is generated, stop mode is released, and then, as in the case with a normal reset operation, the program is executed after br anching to the reset vector address. figure 17-7. stop mode release by reset (1) when high-speed system clock is used as cpu clock stop instruction reset signal high-speed system clock (x1 oscillation) normal operation (high-speed system clock) stop mode reset period normal operation (internal high-speed oscillation clock) oscillates oscillation stopped oscillates status of cpu oscillation stabilization time (2 8 /f x to 2 11 /f x , 2 13 /f x , 2 15 /f x , 2 17 /f x , 2 18 /f x ) oscillation stopped starting x1 oscillation is specified by software. oscillation stopped reset processing (1.92 to 6.17 ms) (2) when internal high-speed osc illation clock is used as cpu clock stop instruction reset signal internal high-speed oscillation clock normal operation (internal high-speed oscillation clock) stop mode reset period normal operation (internal high-speed oscillation clock) oscillates oscillation stopped status of cpu oscillates oscillation stopped wait for oscillation accuracy stabilization reset processing (1.92 to 6.17 ms) remark f x : x1 clock oscillation frequency user?s manual u17854ej6v0ud 574 chapter 18 reset function the following five operations are available to generate a reset signal. (1) external reset input via reset pin (2) internal reset by watchdog timer program loop detection (3) internal reset by comparison of supply voltage and detection voltage of power-on-clear (poc) circuit (4) internal reset by comparison of supply voltage of the low-voltage detector (lvi) or input voltage (exlvi) from external input pin, and detection voltage (5) internal reset by execution of illegal instruction note external and internal resets start program execution from the address at 0000h and 0001h when the reset signal is generated. a reset is effected when a low level is input to the r eset pin, the watchdog timer overflows, or by poc and lvi circuit voltage detection or ex ecution of illegal instruction note , and each item of hardware is set to the status shown in tables 18-1 and 18-2. each pin is hi gh impedance during reset signal generation or during the oscillation stabilization time just after a reset release, exc ept for p130, which is low-level output. when a low level is input to the reset pin, the device is reset. it is released from the reset status when a high level is input to the reset pin and program execution is started with the internal high- speed oscillation clock after reset processing. a reset by the watchdog timer is autom atically released, and program execution starts using the internal high-speed oscillation clock (see figures 18-2 to 18-4 ) after reset processing. reset by poc and lvi circuit power supply detection is automatically released when v dd v poc or v dd v lvi after the reset, and program execution starts using the internal high-speed oscillation clock (see chapter 19 power-on-clear circuit and chapter 20 low-voltage detector ) after reset processing. note the illegal instruction is generated wh en instruction code ffh is executed. reset by the illegal instruction execution not issued by emulation with the in-circu it emulator or on-chip debug emulator. cautions 1. for an external reset, input a low level for 10 s or more to the reset pin. (if an external reset is effected upon power application, the period during which the supply voltage is outside th e operating range (v dd < 1.8 v) is not counted in the 10 s. however, the low-level input may be conti nued before poc is released.) 2. during reset input, the x1 clo ck, xt1 clock, internal high-speed oscillati on clock, and internal low-speed oscillation clock stop oscillating. external main system clock input becomes invalid. 3. when the stop mode is released by a rese t, the ram contents in the stop mode are held during reset input. however, because sfr and 2 nd sfr are initialized, the port pins become high-impedance, except for p130, wh ich is set to low-level output. chapter 18 reset function user?s manual u17854ej6v0ud 575 figure 18-1. block di agram of reset function lvirf wdrf reset control flag register (resf) internal bus watchdog timer reset signal reset power-on clear circuit reset signal low-voltage detector reset signal reset signal reset signal to lvim/lvis register clear set clear set trap reset signal by execution of illegal instruction set clear resf register read signal caution an lvi circuit internal r eset does not reset the lvi circuit. remarks 1. lvim: low-voltage detection register 2. lvis: low-voltage detection level select register chapter 18 reset function user?s manual u17854ej6v0ud 576 figure 18-2. timing of reset by reset input delay hi-z normal operation cpu clock reset period (oscillation stop) normal operation (internal high-speed oscillation clock) reset internal reset signal port pin (except p130) port pin (p130) note high-speed system clock (when x1 oscillation is selected) internal high-speed oscillation clock starting x1 oscillation is specified by software. reset processing (1.92 to 6.17 ms) wait for oscillation accuracy stabilization delay (5 s (max.)) note set p130 to high-level output by software. remark when reset is effected, p130 outputs a low level. if p130 is set to output a high level before reset is effected, the output signal of p130 ca n be dummy-output as the cpu reset signal. figure 18-3. timing of reset du e to watchdog timer overflow normal operation reset period (oscillation stop) (100 ns (typ.)) cpu clock watchdog timer overflow internal reset signal hi-z port pin (except p130) port pin (p130) note high-speed system clock (when x1 oscillation is selected) internal high-speed oscillation clock starting x1 oscillation is specified by software. normal operation (internal high-speed oscillation clock) wait for oscillation accuracy stabilization reset processing ( 61 to 162 s ) note set p130 to high-level output by software. caution a watchdog timer internal reset resets the watchdog timer. remark when reset is effected, p130 outputs a low level. if p130 is set to output a high level before reset is effected, the output signal of p130 ca n be dummy-output as the cpu reset signal. chapter 18 reset function user?s manual u17854ej6v0ud 577 figure 18-4. timing of reset in stop mode by reset input delay normal operation cpu clock reset period (oscillation stop) reset internal reset signal stop instruction execution stop status (oscillation stop) high-speed system clock (when x1 oscillation is selected) internal high-speed oscillation clock hi-z port pin (except p130) port pin (p130) note starting x1 oscillation is specified by software. normal operation (internal high-speed oscillation clock) wait for oscillation accuracy stabilization reset processing (1.92 to 6.17 ms) delay (5 s (max.)) note set p130 to high-level output by software. remarks 1. when reset is effected, p130 outputs a low level. if p 130 is set to output a high level before reset is effected, the output signal of p130 ca n be dummy-output as the cpu reset signal. 2. for the reset timing of the power-on-cl ear circuit and low-voltage detector, see chapter 19 power-on-clear circuit and chapter 20 low-voltage detector . chapter 18 reset function user?s manual u17854ej6v0ud 578 table 18-1. operation st atuses during reset period item during reset period system clock clock supply to the cpu is stopped. f ih operation stopped f x operation stopped (x1 and x2 pins are input port mode) main system clock f ex clock input invalid (pin is input port mode) subsystem clock f xt operation stopped (xt1 and xt2 pins are input port mode) f il cpu operation stopped flash memory operable in lo w-current consumption mode ram operation stopped port (latch) timer array unit (tau) real-time counter (rtc) watch timer watchdog timer clock output/buzzer output a/d converter serial array unit (sau) multiplier dma controller operation stopped power-on-clear f unction operable low-voltage detection function operation stopped (however, operation continues at lvi reset) external interrupt operation stopped remark f ih : internal high-speed oscillation clock f x : x1 oscillation clock f ex : external main system clock f xt : xt1 oscillation clock f il : internal low-speed oscillation clock chapter 18 reset function user?s manual u17854ej6v0ud 579 table 18-2. hardware statuses after reset acknowledgment (1/3) hardware after reset acknowledgment note 1 program counter (pc) the contents of the reset vector table (0000h, 0001h) are set. stack pointer (sp) undefined program status word (psw) 06h data memory undefined note 2 ram general-purpose registers undefined note 2 port registers (p0 to p7, p12 to p14) (output latches) 00h port mode registers (pm0 to pm7, pm12, pm14) ffh port input mode regi sters 0 (pim0) 00h port output mode registers 0 (pom0) 00h pull-up resistor option registers (pu0, pu1, pu3 to pu5, pu7, pu12, pu14) 00h clock operation mode control register (cmc) 00h clock operation status control register (csc) c0h processor mode control register (pmc) 00h system clock control register (ckc) 09h oscillation stabilization time counter status register (ostc) 00h oscillation stabilization time select register (osts) 07h noise filter enable registers 0, 1 (nfen0, nfen1) 00h peripheral enable registers 0 (per0) 00h internal high-speed oscillator tr imming register (hiotrm) 10h operation speed mode control register (osmc) 00h timer data registers 00, 01, 02, 03, 04, 05, 06, 07 (tdr00, tdr01, tdr02, tdr03, tdr04, tdr05, tdr06, tdr07) 0000h timer mode registers 00, 01, 02, 03, 04, 05, 06, 07 (tmr00, tmr01, tmr02, tmr03, tmr04, tmr05, tmr06, tmr07) 0000h timer status registers 00, 01, 02, 03, 04, 05, 06, 07 (tsr00, tsr01, tsr02, tsr03, tsr04, tsr05, tsr06, tsr07) 0000h timer input select register 0 (tis0) 00h timer channel counter regist ers 00, 01, 02, 03, 04, 05, 06, 07 (tcr00, tcr01, tcr02, tcr03, tcr04, tcr05, tcr06, tcr07) ffffh timer channel enable status register 0 (te0) 0000h timer channel start trigger register 0 (ts0) 0000h timer channel stop trigger register 0 (tt0) 0000h timer clock select register 0 (tps0) 0000h timer channel output register 0 (to0) 0000h timer channel output enable register 0 (toe0) 0000h timer channel output level register 0 (tol0) 0000h timer array unit (tau) timer channel output mode register 0 (tom0) 0000h notes 1. during reset signal generation or oscillation st abilization time wait, only the pc contents among the hardware statuses become undefined. all other hardware statuses remain unchanged after reset. 2. when a reset is executed in the standby mode, the pre-reset status is held even after reset. chapter 18 reset function user?s manual u17854ej6v0ud 580 table 18-2. hardware statuses after reset acknowledgment (2/3) hardware status after reset acknowledgment note 1 sub-count register (rsubc) 0000h second count register (sec) 00h minute count register (min) 00h hour count register (hour) 12h week count register (week) 00h day count register (day) 01h month count register (month) 01h year count register (year) 00h watch error correction register (subcud) 00h alarm minute register (alarmwm) 00h alarm hour register (alarmwh) 12h alarm week register alarmww) 00h real-time counter control register 0 (rtcc0) 00h real-time counter control register 1 (rtcc1) 00h real-time counter real-time counter control register 2 (rtcc2) 00h clock output/buzzer output controller clock output select registers 0, 1 (cks0, cks1) 00h watchdog timer enable register (wdte) 1ah/9ah note 2 10-bit a/d conversion result register (adcr) 0000h 8-bit a/d conversion result register (adcrh) 00h mode register (adm) 00h analog input channel specification register (ads) 00h a/d converter a/d port configuration register (adpc) 10h serial data registers 00, 01, 02, 03, 12, 13 (sdr00, sdr01, sdr02, sdr03, sdr12, sdr13) 0000h serial status registers 00, 01, 02, 03, 12, 13 (ssr00, ssr01, ssr02, ssr03, ssr12, ssr13) 0000h serial flag clear trigger registers 00, 01, 02, 03, 12, 13 (sir00, sir01, sir02, sir03, sir12, sir13) 0000h serial mode registers 00, 01, 02, 03, 12, 13 (smr00, smr01, smr02, smr03, smr12, smr13) 0020h serial communication operation setting registers 00, 01, 02, 03, 12, 13 (scr00, scr01, scr02, scr03, scr12, scr13) 0087h serial channel enable status re gisters 0, 1 (se0, se1) 0000h serial channel start trigger r egisters 0, 1 (ss0, ss1) 0000h serial channel stop trigger registers 0, 1 (st0, st1) 0000h serial clock select registers 0, 1 (sps0, sps1) 0000h serial output registers 0, 1 (so0, so1) 0f0fh serial output enable register s 0, 1 (soe0, soe1) 0000h serial array unit (sau) input switch control register (isc) 00h notes 1. during reset signal generation or oscillation st abilization time wait, only the pc contents among the hardware statuses become undefined. all other hardware statuses remain unchanged after reset. 2. the reset value of wdte is dete rmined by the option byte setting. chapter 18 reset function user?s manual u17854ej6v0ud 581 table 18-2. hardware statuses after reset acknowledgment (3/3) hardware status after reset acknowledgment note 1 shift register 0 (iic0) 00h control register 0 (iicc0) 00h slave address register 0 (sva0) 00h clock select register 0 (iiccl0) 00h function expansion register 0 (iicx0) 00h status register 0 (iics0) 00h serial interface iic0 flag register 0 (iicf0) 00h multiplication input data register a (mula) 0000h multiplication input data register b (mulb) 0000h higher multiplication result storage register (muloh) 0000h multiplier lower multiplication result storage register (mulol) 0000h key interrupt key return mode register (krm) 00h reset function reset control flag register (resf) 00h note 2 low-voltage detection register (lvim) 00h note 3 low-voltage detector low-voltage detection level select register (lvis) 0eh note 2 sfr address registers 0, 1 (dsa0, dsa1) 00h ram address registers 0l, 0h, 1l, 1h (dra0l, dra0h, dra1l, dra1h) 00h byte count registers 0l, 0h, 1l, 1h (dbc0l, dbc0h, dbc1l, dbc1h) 00h mode control registers 0, 1 (dmc0, dmc1) 00h dma controller operation control registers 0, 1 (drc0, drc1) 00h request flag registers 0l, 0h, 1l, 1h, 2l, 2h (if0l, if0h, if1l, if1h, if2l, if2h) 00h mask flag registers 0l, 0h, 1l, 1h, 2l, 2h (mk0l, mk0h, mk1l, mk1h, mk2l, mk2h) ffh priority specification flag registers 00l, 00h, 01l, 01h, 02l, 02h, 10l, 10h, 11l, 11h, 12l, 12h (pr00l, pr00h, pr01l, pr01h, pr10l, pr10h, pr11l, pr11h, pr02l, pr02h, pr12l, pr12h) ffh external interrupt rising edge enab le registers (egp0, egp1) 00h interrupt external interrupt falling edge enable registers (egn0, egn1) 00h notes 1. during reset signal generation or oscillation st abilization time wait, only the pc contents among the hardware statuses become undefined. all other hardware statuses remain unchanged after reset. 2. these values vary depending on the reset source. reset source register reset input reset by poc reset by execution of illegal instruction reset by wdt reset by lvi trap bit set (1) held held wdrf bit held set (1) held resf lvirf bit cleared (0) cleared (0) held held set (1) lvis cleared (0eh) cleared (0eh) cleared (0eh) cleared (0eh) held 3. this value varies depending on the reset source and the option byte. chapter 18 reset function user?s manual u17854ej6v0ud 582 18.1 register for confirming reset source many internal reset generation sources exist in the 78k0r /ke3. the reset control flag register (resf) is used to store which source has generated the reset request. resf can be read by an 8-bit memory manipulation instruction. reset input, reset by power-on-clear (poc) circuit, and reading resf set resf to 00h. figure 18-5. format of reset control flag register (resf) address: fffa8h after reset: 00h note 1 r symbol 7 6 5 4 3 2 1 0 resf trap 0 0 wdrf 0 0 0 lvirf trap internal reset request by execution of illegal instruction note 2 0 internal reset request is not generated, or resf is cleared. 1 internal reset request is generated. wdrf internal reset request by watchdog timer (wdt) 0 internal reset request is not generated, or resf is cleared. 1 internal reset request is generated. lvirf internal reset request by low-voltage detector (lvi) 0 internal reset request is not generated, or resf is cleared. 1 internal reset request is generated. notes 1. the value after reset varies depending on the reset source. 2. the illegal instruction is generated wh en instruction code ffh is executed. reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip debug emulator. cautions 1. do not read data by a 1-bit memory manipulation instruction. 2. when the lvi default start function (bit 0 (lv ioff) of 000c1h = 0) is used, lvirf flag may become 1 from the beginning de pending on the power-on waveform. the status of resf when a reset request is generated is shown in table 18-3. table 18-3. resf status when reset request is generated reset source flag reset input reset by poc reset by execution of illegal instruction reset by wdt reset by lvi trap set (1) held held wdrf held set (1) held lvirf cleared (0) cleared (0) held held set (1) user?s manual u17854ej6v0ud 583 chapter 19 power-on-clear circuit 19.1 functions of power-on-clear circuit the power-on-clear circuit (poc) has the following functions. ? generates internal reset signal at power on. the reset signal is released when the supply voltage (v dd ) exceeds 1.59 v 0.09 v note . caution if the low-voltage detector (l vi) is set to on by an option byte by default, the reset signal is not released until the supply voltage (v dd ) exceeds 2.07 v 0.2 v note . ? compares supply voltage (v dd ) and detection voltage (v poc = 1.59 v 0.09 v note ), generates internal reset signal when v dd < v poc . note these are preliminary values and subject to change. caution if an internal reset signal is generated in the poc circuit, th e reset control flag register (resf) is cleared to 00h. remark this product incorporates multiple hardware functi ons that generate an internal reset signal. a flag that indicates the reset source is located in the reset control flag register (resf) for when an internal reset signal is generated by the watchdog timer (wdt), low-voltage-detector (lvi), or illegal instruction execution. resf is not cleared to 00h and the flag is set to 1 when an internal reset signal is generated by wdt or lvi. for details of resf, see chapter 18 reset function . chapter 19 power-on-clear circuit user?s manual u17854ej6v0ud 584 19.2 configuration of power-on-clear circuit the block diagram of the power-on-clear circuit is shown in figure 19-1. figure 19-1. block diagram of power-on-clear circuit ? + reference voltage source internal reset signal v dd v dd 19.3 operation of power-on-clear circuit ? an internal reset signal is generated on pow er application. when the supply voltage (v dd ) exceeds the detection voltage (v poc = 1.59 v 0.09 v note ), the reset status is released. caution if the low-voltage detector (l vi) is set to on by an option byte by default, the reset signal is not released until the supply voltage (v dd ) exceeds 2.07 v 0.2 v note . ? the supply voltage (v dd ) and detection voltage (v poc = 1.59 v 0.09 v note ) are compared. when v dd < v poc , the internal reset signal is generated. note these are preliminary values and subject to change. the timing of generation of the internal reset signal by t he power-on-clear circuit and low-voltage detector is shown below. chapter 19 power-on-clear circuit user?s manual u17854ej6v0ud 585 figure 19-2. timing of generation of intern al reset signal by power-on-clear circuit and low-voltage detector (1/2) (1) when lvi is off upon power a pplication (option byte: lvioff = 1) internal high-speed oscillation clock (f ih ) high-speed system clock (f mx ) (when x1 oscillation is selected) starting oscillation is specified by software. v poc = 1.59 v (typ.) note 6 v lvi operation stops wait for voltage stabilization normal operation (internal high-speed oscillation clock) note 5 operation stops reset period (oscillation stop) reset period (oscillation stop) wait for oscillation accuracy stabilization note 4 normal operation (internal high-speed oscillation clock) note 5 starting oscillation is specified by software. starting oscillation is specified by software. cpu 0 v supply voltage (v dd ) 1.8 v note 1 wait for voltage stabilization normal operation (internal high-speed oscillation clock ) note 5 0.5 v/ms (min.) note 2 set lvi to be used for reset set lvi to be used for reset set lvi to be used for interrupt internal reset signal reset processing reset processing (43 to 160 s) reset processing wait for oscillation accuracy stabilization note 3 wait for oscillation accuracy stabilization note 3 1.92 to 6.17 ms 1.92 to 6.17 ms notes 1. the operation guaranteed range is 1.8 v v dd 5.5 v. to make the state at lower than 1.8 v reset state when the supply voltage falls, us e the reset function of the low-vo ltage detector, or input the low level to the reset pin. 2. if the rate at which the voltage rises to 1.8 v afte r power application is slower than 0.5 v/ms (min.), input a low level to the reset pin before the voltage r eaches to 1.8 v, or set lvi to on by default by using an option byte (option byte: lvioff = 0). 3. the internal voltage stabilization time includes the o scillation accuracy stabilization time of the internal high-speed oscillation clock. 4. the internal reset processing time includes the o scillation accuracy stabilization time of the internal high-speed oscillation clock. 5. the internal high-speed oscillation clock and a hi gh-speed system clock or subsystem clock can be selected as the cpu clock. to us e the x1 clock, use the ostc regi ster to confirm the lapse of the oscillation stabilization time. to use the xt1 clock, use the timer function for confirmation of the lapse of the stabilization time. 6. this is a preliminary value and subject to change. caution set the low-voltage detector by software after the reset status is released (see chapter 20 low-voltage detector). remark v lvi : lvi detection voltage v poc : poc detection voltage chapter 19 power-on-clear circuit user?s manual u17854ej6v0ud 586 figure 19-2. timing of generation of intern al reset signal by power-on-clear circuit and low-voltage detector (2/2) (2) when lvi is on upon power app lication (option byte: lvioff = 0) internal high-speed oscillation clock (f ih ) high-speed system clock (f mx ) (when x1 oscillation is selected) starting oscillation is specified by software. internal reset signal v lvi = 2.07 v (typ.) note 3 v poc = 1.59 v (typ.) note 3 v lvi operation stops note 5 normal operation (internal high-speed oscillation clock) note 2 normal operation (internal high-speed oscillation clock) note 2 operation stops reset period (oscillation stop) normal operation (internal high-speed oscillation clock) note 2 starting oscillation is specified by software. starting oscillation is specified by software. cpu 0 v supply voltage (v dd ) 1.8 v note 1 reset processing (43 to 160 s) poc processing reset processing (43 to 160 s) set lvi (v lvi = 2.07) to be used for reset (default) set lvi (v lvi = 2.07) to be used for reset (default) change lvi detection voltage (v lvi ) set lvi to be used for interrupt wait for oscillation accuracy stabilization note 4 wait for oscillation accuracy stabilization note 4 wait for oscillation accuracy stabilization note 4 reset period (oscillation stop) reset processing (43 to 160 s) poc processing note 5 notes 1. the operation guaranteed range is 1.8 v v dd 5.5 v. to make the state at lower than 1.8 v reset state when the supply voltage falls, us e the reset function of the low-vo ltage detector, or input the low level to the reset pin. 2. the internal high-speed oscillation clock and a hi gh-speed system clock or subsystem clock can be selected as the cpu clock. to us e the x1 clock, use the ostc regi ster to confirm the lapse of the oscillation stabilization time. to use the xt1 clock, use the timer function for confirmation of the lapse of the stabilization time. 3. these are preliminary values and subject to change. 4. the internal reset processing time includes the o scillation accuracy stabilization time of the internal high-speed oscillation clock. 5. the following times are required between reachi ng the poc detection voltag e (1.59 v (typ.)) and starting normal operation. ? when the time to reach 2.07 v (typ.) fr om 1.59 v (typ.) is less than 6.17 ms: a poc processing time of 1.92 to 6.33 ms is required between reaching 1.59 v (typ.) and starting normal operation. ? when the time to reach 2.07 v (typ.) from 1.59 v (typ.) is greater than 6.17 ms: a reset processing time of 43 to 160 s is required between reaching 2.07 v (typ.) and starting normal operation. caution set the low-voltage detector by software after the reset status is released (see chapter 20 low-voltage detector). remark v lvi : lvi detection voltage v poc : poc detection voltage chapter 19 power-on-clear circuit user?s manual u17854ej6v0ud 587 19.4 cautions for power-on-clear circuit in a system where the supply voltage (v dd ) fluctuates for a certain period in the vicinity of the poc detection voltage (v poc ), the system may be repeatedly reset and released from the reset status. in this case, the time from release of reset to the start of the oper ation of the microcontroller can be arbitrarily set by taking the following action. chapter 19 power-on-clear circuit user?s manual u17854ej6v0ud 588 figure 19-3. example of software processing after reset release (2/2) ? checking reset source yes no check reset source power-on-clear/external reset generated reset processing by watchdog timer reset processing by low-voltage detector no wdrf of resf register = 1? lvirf of resf register = 1? yes no reset processing by illegal instruction execution note trap of resf register = 1? yes note the illegal instruction is generated wh en instruction code ffh is executed. reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip debug emulator. user?s manual u17854ej6v0ud 589 chapter 20 low-voltage detector 20.1 functions of low-voltage detector the low-voltage detector (lvi ) has the following functions. ? the lvi circuit compares the supply voltage (v dd ) with the detection voltage (v lvi ) or the input voltage from an external input pin (exlvi) with the detection voltage (v exlvi = 1.21 v 0.1 v note ), and generates an internal reset or internal interrupt signal. ? the low-voltage detector (lvi) can be set to on by an option byte by default. if it is se t to on to raise the power supply from the poc detection voltage or lower, the inte rnal reset signal is generated when the supply voltage (v dd ) < detection voltage (v lvi = 2.07 v 0.2 v note ). after that, the internal reset signal is generated when the supply voltage (v dd ) < detection voltage (v lvi = 2.07 v 0.1 v note ). ? the supply voltage (v dd ) or the input voltage from the external in put pin (exlvi) can be selected to be detected by software. ? a reset or an interrupt can be selected to be generated after detection by software. ? detection levels (v lvi ,16 levels) of supply voltage can be changed by software. ? operable in stop mode. note this is a preliminary value and subject to change. the reset and interrupt signals are generated as follows depending on selection by software. selection of level detection of supply voltage (v dd ) (lvisel = 0) selection level detection of input voltage from external input pin (exlvi) (lvisel = 1) selects reset (lvimd = 1). selects interrupt (lvimd = 0). selects reset (lvimd = 1). selects interrupt (lvimd = 0). generates an internal reset signal when v dd < v lvi and releases the reset signal when v dd v lvi . generates an internal interrupt signal when v dd drops lower than v lvi (v dd < v lvi ) or when v dd becomes v lvi or higher (v dd v lvi ). generates an internal reset signal when exlvi < v exlvi and releases the reset signal when exlvi v exlvi . generates an internal interrupt signal when exlvi drops lower than v exlvi (exlvi < v exlvi ) or when exlvi becomes v exlvi or higher (exlvi v exlvi ). remark lvisel: bit 2 of low-voltage detection register (lvim) lvimd: bit 1 of lvim while the low-voltage detector is operat ing, whether the supply voltage or t he input voltage from an external input pin is more than or less than the detection level can be che cked by reading the low-voltage detection flag (lvif: bit 0 of lvim). when the low-voltage detector is used to reset, bit 0 (lvirf) of the reset control flag regi ster (resf) is set to 1 if reset occurs. for details of resf, see chapter 18 reset function . chapter 20 low-voltage detector user?s manual u17854ej6v0ud 590 20.2 configuration of low-voltage detector the block diagram of the low-voltage detector is shown in figure 20-1. figure 20-1. block diagram of low-voltage detector lvis1 lvis0 lvion ? + reference voltage source v dd internal bus n-ch low-voltage detection level select register (lvis) low-voltage detection register (lvim) lvis2 lvis3 lvif intlvi internal reset signal 4 lvisel exlvi/p120/ intp0 lvimd v dd low-voltage detection level selector selector selector 20.3 registers controlli ng low-voltage detector the low-voltage detector is contro lled by the following registers. ? low-voltage detection register (lvim) ? low-voltage detection level select register (lvis) ? port mode register 12 (pm12) (1) low-voltage detection register (lvim) this register sets low-voltag e detection and the operation mode. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. chapter 20 low-voltage detector user?s manual u17854ej6v0ud 591 figure 20-2. format of low-volta ge detection register (lvim) <0> lvif <1> lvimd <2> lvisel 3 0 4 0 5 0 6 0 <7> lvion symbol lvim address: fffa9h after reset: 00h note 1 r/w note 2 lvion notes 3, 4 enables low-voltage detection operation 0 disables operation 1 enables operation lvisel note 3 voltage detection selection 0 detects level of supply voltage (v dd ) 1 detects level of input voltage from external input pin (exlvi) lvimd note 3 low-voltage detection operation m ode (interrupt/reset) selection 0 ? lvisel = 0: generates an internal interrupt signal when the supply voltage (v dd ) drops lower than the detection voltage (v lvi ) (v dd < v lvi ) or when v dd becomes v lvi or higher (v dd v lvi ). ? lvisel = 1: generates an interrupt signal when the input voltage from an external input pin (exlvi) drops lower than the detection voltage (v exlvi ) (exlvi < v exlvi ) or when exlvi becomes v exlvi or higher (exlvi v exlvi ). 1 ? lvisel = 0: generates an internal reset signal when the supply voltage (v dd ) < detection voltage (v lvi ) and releases the reset signal when v dd v lvi . ? lvisel = 1: generates an internal reset signal when the input voltage from an external input pin (exlvi) < detection voltage (v exlvi ) and releases the reset signal when exlvi v exlvi . lvif low-voltage detection flag 0 ? lvisel = 0: supply voltage (v dd ) detection voltage (v lvi ), or when lvi operation is disabled ? lvisel = 1: input voltage from external input pin (exlvi) detection voltage (v exlvi ), or when lvi operation is disabled 1 ? lvisel = 0: supply voltage (v dd ) < detection voltage (v lvi ) ? lvisel = 1: input voltage from external input pin (exlvi) < detection voltage (v exlvi ) notes 1. the reset value changes depending on the rese t source and the setting of the option byte. this register is not cleared (00h) by lvi reset. it is set to ?82h? when a reset signal other than lv i is applied if option byte lvioff = 0, and to ?00h? if option byte lvioff = 1. 2. bit 0 is read-only. 3. lvion, lvimd, and lvisel are cleared to 0 in t he case of a reset other than an lvi reset. these are not cleared to 0 in the case of an lvi reset. chapter 20 low-voltage detector user?s manual u17854ej6v0ud 592 notes 4. when lvion is set to 1, operation of the comparator in the lvi circuit is started. use software to wait for the following periods of time, between when lv ion is set to 1 and when the voltage is confirmed with lvif. ? operation stabilization time (10 s (max.)) ? minimum pulse width (200 s (min.)) ? detection delay time (200 s (max.)) the lvif value for these periods may be set/cl eared regardless of the voltage level, and can therefore not be used. also, the lviif interrupt request flag may be set to 1 in these periods. cautions 1. to stop lvi, follow either of the procedures below. ? when using 8-bit memory manipulation instruction: write 00h to lvim. ? when using 1-bit memory manipulatio n instruction: clear lvion to 0. 2. input voltage from external input pin (exlvi) must be exlvi < v dd . 3. when lvi is used in interrupt mode (lvimd = 0) and lvisel is set to 0, an interrupt request signal (intlvi) that disables lvi operation (clears lvion) when the supply voltage (v dd ) is less than or equal to the detection voltage (v lvi ) (if lvisel = 1, input voltage of external input pin (exlvi) is less than or equal to the detection voltage (v exlvi )) is generated and lviif may be set to 1. chapter 20 low-voltage detector user?s manual u17854ej6v0ud 593 (2) low-voltage detection l evel select register (lvis) this register selects the low-voltage detection level. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation input sets this register to 0eh. figure 20-3. format of low-voltage dete ction level select register (lvis) 0 lvis0 1 lvis1 2 lvis2 3 lvis3 4 0 5 0 6 0 7 0 symbol lvis address: fffaah after reset: 0eh note 1 r/w lvis3 lvis2 lvis1 lvis0 detection level 0 0 0 0 v lvi0 (4.22 0.1 v) note 2 0 0 0 1 v lvi1 (4.07 0.1 v) note 2 0 0 1 0 v lvi2 (3.92 0.1 v) note 2 0 0 1 1 v lvi3 (3.76 0.1 v) note 2 0 1 0 0 v lvi4 (3.61 0.1 v) note 2 0 1 0 1 v lvi5 (3.45 0.1 v) note 2 0 1 1 0 v lvi6 (3.30 0.1 v) note 2 0 1 1 1 v lvi7 (3.15 0.1 v) note 2 1 0 0 0 v lvi8 (2.99 0.1 v) note 2 1 0 0 1 v lvi9 (2.84 0.1 v) note 2 1 0 1 0 v lvi10 (2.68 0.1 v) note 2 1 0 1 1 v lvi11 (2.53 0.1 v) note 2 1 1 0 0 v lvi12 (2.38 0.1 v) note 2 1 1 0 1 v lvi13 (2.22 0.1 v) note 2 1 1 1 0 v lvi14 (2.07 0.1 v) note 2 1 1 1 1 v lvi15 (1.91 0.1 v) note 2 notes 1. the reset value changes depending on the reset source. if the lvis register is reset by lvi, it is not reset but holds the current value. the value of this register is reset to ?0eh? if a reset other than by lvi is effected. 2. these are preliminary values and subject to change. cautions 1. be sure to cl ear bits 4 to 7 to ?0?. chapter 20 low-voltage detector user?s manual u17854ej6v0ud 594 cautions 2. change the lvis value with either of the following methods. ? when changing the value after stopping lvi <1> stop lvi (lvion = 0). <2> change the lvis register. <3> set to the mode used as an interrupt (lvimd = 0). <4> mask lvi interrupts (lvimk = 1). <5> enable lvi operation (lvion = 1). <6> before cancelling the lvi interrupt mask (lvimk = 0), clear it with software because an lviif flag may be set when lvi operation is enabled. ? when changing the value after setting to the mode used as an interrupt (lvimd = 0) <1> mask lvi interrupts (lvimk = 1). <2> set to the mode used as an interrupt (lvimd = 0). <3> change the lvis register. <4> before cancelling the lvi interrupt mask (lvimk = 0), clear it with software because an lviif flag may be set when the lvis register is changed. 3. when an input voltage from the externa l input pin (exlvi) is detected, the detection voltage (v exlvi ) is fixed. therefore, setting of lvis is not necessary. (3) port mode register 12 (pm12) when using the p120/exlvi/intp0 pin for external low-volt age detection potential input, set pm120 to 1. at this time, the output latch of p120 may be 0 or 1. pm12 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to ffh. figure 20-4. format of port mode register 12 (pm12) 0 pm120 1 1 2 1 3 1 4 1 5 1 6 1 7 1 symbol pm12 address: fff2ch after reset: ffh r/w pm120 p120 pin i/o mode selection 0 output mode (output buffer on) 1 input mode (output buffer off) chapter 20 low-voltage detector user?s manual u17854ej6v0ud 595 20.4 operation of low-voltage detector the low-voltage detector can be us ed in the following two modes. (1) used as reset (lvimd = 1) ? if lvisel = 0, compares the supply voltage (v dd ) and detection voltage (v lvi ), generates an internal reset signal when v dd < v lvi , and releases internal reset when v dd v lvi . ? if lvisel = 1, compares the input voltage from external input pin (exlvi) and detection voltage (v exlvi ), generates an internal reset signal when exlvi < v exlvi , and releases internal reset when exlvi v exlvi . remark the low-voltage detector (lvi) can be set to on by an option byte by default. if it is set to on to raise the power supply from the poc detection vo ltage or lower, the internal reset signal is generated when the supply voltage (v dd ) < detection voltage (v lvi = 2.07 v 0.2 v note ). after that, the internal reset signal is generated when the supply voltage (v dd ) < detection voltage (v lvi = 2.07 v 0.1 v note ). (2) used as interrupt (lvimd = 0) ? if lvisel = 0, compares the supply voltage (v dd ) and detection voltage (v lvi ). when v dd drops lower than v lvi (v dd < v lvi ) or when v dd becomes v lvi or higher (v dd v lvi ), generates an interrupt signal (intlvi). ? if lvisel = 1, compares the input voltage from external input pin (exlvi) and detection voltage (v exlvi = 1.21 v 0.1 v note ). when exlvi drops lower than v exlvi (exlvi < v exlvi ) or when exlvi becomes v exlvi or higher (exlvi v exlvi ), generates an interrupt signal (intlvi). note this is a preliminary value and subject to change. while the low-voltage detector is operat ing, whether the supply voltage or t he input voltage from an external input pin is more than or less than the detection level can be che cked by reading the low-voltage detection flag (lvif: bit 0 of lvim). remark lvimd: bit 1 of low-voltage detection register (lvim) lvisel: bit 2 of lvim chapter 20 low-voltage detector user?s manual u17854ej6v0ud 596 20.4.1 when used as reset (1) when detecting level of supply voltage (v dd ) (a) when lvi default start function st opped is set (option byte: lvioff = 1) ? when starting operation <1> mask the lvi interrupt (lvimk = 1). <2> clear bit 2 (lvisel) of the low-voltage detection re gister (lvim) to 0 (detects level of supply voltage (v dd )) (default value). <3> set the detection voltage using bits 3 to 0 (lvis3 to lvis0) of the low-voltage detection level selection register (lvis). <4> set bit 7 (lvion) of lvim to 1 (enables lvi operation). <5> use software to wait for the following periods of time (total 410 s). ? operation stabilization time (10 s (max.)) ? minimum pulse width (200 s (min.)) ? detection delay time (200 s (max.)) <6> wait until it is checked that (supply voltage (v dd ) detection voltage (v lvi )) by bit 0 (lvif) of lvim. <7> set bit 1 (lvimd) of lvim to 1 (generates reset when the level is detected). figure 20-5 shows the timing of the internal reset signal generated by the low-voltage detector. the numbers in this timing chart correspond to <1> to <7> above. cautions 1. <1> must always be executed. when lvimk = 0, an interrupt may occur immediately after the processing in <4>. 2. if supply voltage (v dd ) detection voltage (v lvi ) when lvimd is set to 1, an internal reset signal is not generated. ? when stopping operation either of the following pr ocedures must be executed. ? when using 8-bit memory manipulation instruction: write 00h to lvim. ? when using 1-bit memory manipulation instruction: clear lvimd to 0 and then lvion to 0. chapter 20 low-voltage detector user?s manual u17854ej6v0ud 597 figure 20-5. timing of low-voltage dete ctor internal reset signal generation (bit: lvisel = 0, option byte: lvioff = 1) l set lvi to be used for reset time supply voltage (v dd ) v lvi v poc = 1.59 v (typ.) lvimk flag (set by software) lvif flag lvirf flag note 3 lvi reset signal poc reset signal internal reset signal lvion flag (set by software) lvimd flag (set by software) lvisel flag (set by software) h note 1 <1> <3> <2> <4> <5> wait time <6> note 2 <7> cleared by software cleared by software not cleared not cleared not cleared not cleared clear clear clear notes 1. the lvimk flag is set to ?1? by reset signal generation. 2. the lviif flag of the interrupt request flag registers and the lvif flag may be set (1). 3. lvirf is bit 0 of the reset control flag re gister (resf). for details of resf, see chapter 18 reset function . remark <1> to <7> in figure 20-5 above correspond to <1> to <7> in the description of ?when starting operation? in 20.4.1 (1) (a) when lvi default start function stopped is set (option byte: lvioff = 1). chapter 20 low-voltage detector user?s manual u17854ej6v0ud 598 (b) when lvi default start function enabled is set (option byte: lvioff = 0) ? when starting operation start in the following initial setting state. ? set bit 7 (lvion) of lvim to 1 (enables lvi operation) ? clear bit 2 (lvisel) of the low-voltage detection regi ster (lvim) to 0 (detects level of supply voltage (v dd )) ? set the low-voltage detection level selectio n register (lvis) to 0eh (default value: v lvi = 2.07 v 0.1 v ). ? set bit 1 (lvimd) of lvim to 1 (generat es reset when the level is detected) ? set bit 0 (lvif) of lvim to 0 (?supply voltage (v dd ) detection voltage (v lvi )?) figure 20-6 shows the timing of the internal rese t signal generated by the low-voltage detector. ? when stopping operation either of the following pr ocedures must be executed. ? when using 8-bit memory manipulation instruction: write 00h to lvim. ? when using 1-bit memory manipulation instruction: clear lvimd to 0 and then lvion to 0. caution even when the lvi default start function is used, if it is set to lvi operation prohibition by the software, it operates as follows: ? does not perform low-voltage detection during lvion = 0. ? if a reset is generated while lvion = 0, lvion will be re-set to 1 when the cpu starts after reset release. there is a pe riod when low-voltage detecti on cannot be performed normally, however, when a reset occurs due to wd t and illegal instruction execution. this is due to the fact that while the pulse width detected by lvi must be 200 s max., lvion = 1 is set upon reset occurrence, and th e cpu starts operating without waiting for the lvi stabilization time. chapter 20 low-voltage detector user?s manual u17854ej6v0ud 599 figure 20-6. timing of low-voltage dete ctor internal reset signal generation (bit: lvisel = 0, option byte: lvioff = 0) v lvi value after a change l h supply voltage (v dd ) lvimk flag (set by software) lvif flag lvirf flag lvi reset signal poc reset signal internal reset signal lvion flag (set by software) lvimd flag (set by software) lvisel flag (set by software) v lvi = 2.07 v (typ.) v poc = 1.59 v (typ.) h note 1 time not cleared not cleared not cleared clear clear cleared by software cleared by software cleared by software not cleared note 2 interrupt operation mode is set by setting lvimd to 0 (lvi interrupt is masked) change lvi detection voltage (vlvi) reset mode is set by setting lvimd to 1 h notes 1. the lvimk flag is set to ?1? by reset signal generation. 2. lvirf is bit 0 of the reset control flag register (resf). when the lvi default start function (bit 0 (lvio ff) of 000c1h = 0) is used, the lvirf flag may become 1 from the beginning due to the power-on waveform. for details of resf, see chapter 18 reset function . chapter 20 low-voltage detector user?s manual u17854ej6v0ud 600 (2) when detecting level of input vo ltage from external input pin (exlvi) ? when starting operation <1> mask the lvi interrupt (lvimk = 1). <2> set bit 2 (lvisel) of the low-voltage detection regist er (lvim) to 1 (detects level of input voltage from external input pin (exlvi)). <3> set bit 7 (lvion) of lvim to 1 (enables lvi operation). <4> use software to wait for the following periods of time (total 410 s). ? operation stabilization time (10 s (max.)) ? minimum pulse width (200 s (min.)) ? detection delay time (200 s (max.)) <5> wait until it is checked that (input voltage from external input pin (exlvi) detection voltage (v exlvi = 1.21 v (typ.))) by bit 0 (lvif) of lvim. <6> set bit 1 (lvimd) of lvim to 1 (generates reset signal when the level is detected). figure 20-7 shows the timing of the internal reset signal generated by the low-volt age detector. the numbers in this timing chart correspond to <1> to <6> above. cautions 1. <1> must always be executed. when lvimk = 0, an interrupt may occur immediately after the processing in <3>. 2. if input voltage from external input pin (exlvi) detection voltage (v exlvi = 1.21 v (typ.)) when lvimd is set to 1, an intern al reset signal is not generated. 3. input voltage from external input pin (exlvi) must be exlvi < v dd . ? when stopping operation either of the following pr ocedures must be executed. ? when using 8-bit memory manipulation instruction: write 00h to lvim. ? when using 1-bit memory manipulation instruction: clear lvimd to 0 and then lvion to 0. chapter 20 low-voltage detector user?s manual u17854ej6v0ud 601 figure 20-7. timing of low-voltage dete ctor internal reset signal generation (bit: lvisel = 1) v exlvi set lvi to be used for reset lvimk flag (set by software) lvif flag lvirf flag note 3 lvi reset signal internal reset signal lvion flag (set by software) lvimd flag (set by software) lvisel flag (set by software) <1> <2> <3> <4> wait time <5> <6> note 2 not cleared not cleared not cleared not cleared not cleared not cleared not cleared not cleared not cleared cleared by software cleared by software time h note 1 input voltage from external input pin (exlvi) notes 1. the lvimk flag is set to ?1? by reset signal generation. 2. the lviif flag of the interrupt request flag registers and the lvif flag may be set (1). 3. lvirf is bit 0 of the reset control flag re gister (resf). for details of resf, see chapter 18 reset function . remark <1> to <6> in figure 20-7 above correspond to <1> to <6> in the description of ? when starting operation? in 20.4.1 (2) when detecting level of input voltage from external input pin (exlvi) . chapter 20 low-voltage detector user?s manual u17854ej6v0ud 602 20.4.2 when used as interrupt (1) when detecting level of supply voltage (v dd ) (a) when lvi default start function st opped is set (option byte: lvioff = 1) ? when starting operation <1> mask the lvi interrupt (lvimk = 1). <2> clear bit 2 (lvisel) of the low-voltage detection re gister (lvim) to 0 (detects level of supply voltage (v dd )) (default value). clear bit 1 (lvimd) of lvim to 0 (generates interrupt signal when the level is detected) (default value). <3> set the detection voltage using bits 3 to 0 (lvis3 to lvis0) of the low-voltag e detection level selection register (lvis). <4> set bit 7 (lvion) of lvim to 1 (enables lvi operation). <5> use software to wait for the following periods of time (total 410 s). ? operation stabilization time (10 s (max.)) ? minimum pulse width (200 s (min.)) ? detection delay time (200 s (max.)) <6> confirm that ?supply voltage (v dd ) detection voltage (v lvi )? when detecting the falling edge of v dd , or ?supply voltage (v dd ) < detection voltage (v lvi )? when detecting the rising edge of v dd , at bit 0 (lvif) of lvim. <7> clear the interrupt request flag of lvi (lviif) to 0. <8> release the interrupt mask flag of lvi (lvimk). <9> execute the ei instruction (w hen vector interrupts are used). figure 20-8 shows the timing of the interrupt signal ge nerated by the low-voltage detector. the numbers in this timing chart correspond to <1> to <8> above. ? when stopping operation either of the following pr ocedures must be executed. ? when using 8-bit memory manipulation instruction: write 00h to lvim. ? when using 1-bit memory manipulation instruction: clear lvion to 0. chapter 20 low-voltage detector user?s manual u17854ej6v0ud 603 figure 20-8. timing of low-voltage de tector interrupt signal generation (bit: lvisel = 0, option byte: lvioff = 1) l l supply voltage (v dd ) lvimk flag (set by software) lvif flag intlvi lviif flag internal reset signal lvion flag (set by software) lvisel flag (set by software) lvimd flag (set by software) v lvi v poc = 1.59 v (typ.) time <1> note 1 <2> <8> cleared by software note 3 note 3 <5> wait time <4> <6> note 2 note 2 note 2 <7> cleared by software <3> notes 1. the lvimk flag is set to ?1? by reset signal generation. 2. the interrupt request signal (intlvi) is generat ed and the lvif and lviif flags may be set (1). 3. if lvi operation is disabled when the supply voltage (v dd ) is less than or equal to the detection voltage (v lvi ), an interrupt request signal (intlvi) is generated and lviif may be set to 1. remark <1> to <8> in figure 20-8 above correspond to <1> to <8> in the description of ?when starting operation? in 20.4.2 (1) (a) when lvi default start function stopped is set (option byte: lvioff = 1). chapter 20 low-voltage detector user?s manual u17854ej6v0ud 604 (b) when lvi default start function enabled is set (option byte: lvioff = 0) ? when starting operation <1> start in the following initial setting state. ? set bit 7 (lvion) of lvim to 1 (enables lvi operation) ? clear bit 2 (lvisel) of the low-voltage detection re gister (lvim) to 0 (detects level of supply voltage (v dd )) ? set the low-voltage detection level selectio n register (lvis) to 0eh (default value: v lvi = 2.07 v 0.1 v ). ? set bit 1 (lvimd) of lvim to 1 (generat es reset when the level is detected) ? set bit 0 (lvif) of lvim to 0 (detects falling edge ?supply voltage (v dd ) detection voltage (v lvi )?) <2> clear bit 1 (lvimd) of lvim to 0 (generates inte rrupt signal when the level is detected) (default value). <3> release the interrupt mask flag of lvi (lvimk). <4> execute the ei instruction (w hen vector interrupts are used). figure 20-9 shows the timing of the interrupt signal ge nerated by the low-voltage detector. the numbers in this timing chart correspond to <1> to <3> above. ? when stopping operation either of the following pr ocedures must be executed. ? when using 8-bit memory manipulation instruction: write 00h to lvim. ? when using 1-bit memory manipulation instruction: clear lvion to 0. cautions 1. even when the lvi default start function is used, if it is set to lvi operation prohibition by the software, it operates as follows: ? does not perform low-voltage detection during lvion = 0. ? if a reset is generated whil e lvion = 0, lvion will be re-set to 1 when the cpu starts after reset release. there is a period when low-voltage detection cannot be performed normally, however, when a reset occurs due to wdt and illegal instruction execution. this is due to the fact that while the pulse width detected by lvi must be 200 s max., lvion = 1 is set upon reset occurrence, and the cpu starts operating without waiting for the lvi stabilization time. 2. when the lvi default start function (bit 0 (l vioff) of 000c1h = 0) is used, the lvirf flag may become 1 from the beginning due to the power-on waveform. for details of resf, see chapter 18 reset function. chapter 20 low-voltage detector user?s manual u17854ej6v0ud 605 figure 20-9. timing of low-voltage de tector interrupt signal generation (bit: lvisel = 0, option byte: lvioff = 0) l supply voltage (v dd ) lvimk flag (set by software) lvif flag intlvi lviif flag internal reset signal lvion flag (set by software) lvisel flag (set by software) lvimd flag (set by software) v lvi = 2.07 v (typ.) mask lvi interrupts (lvimk = 1) v poc = 1.59 v (typ.) <1> note 1 <3> cleared by software cleared by software note 2 note 2 note 3 <2> time change lvi detection voltage (v lvi ) cancelling the lvi interrupt mask (lvimk = 0) v lvi value after a change notes 1. the lvimk flag is set to ?1? by reset signal generation. 2. if lvi operation is disabled when the supply voltage (v dd ) is less than or equal to the detection voltage (v lvi ), an interrupt request signal (intlvi) is generated and lviif may be set to 1. 3. the lviif flag may be set when the lvi detection voltage is changed. remark <1> to <3> in figure 20-9 above correspond to <1> to <3> in the description of ?when starting operation? in 20.4.2 (1) (b) when lvi de fault start function enabled is set (option byte: lvioff = 0). chapter 20 low-voltage detector user?s manual u17854ej6v0ud 606 (2) when detecting level of input vo ltage from external input pin (exlvi) ? when starting operation <1> mask the lvi interrupt (lvimk = 1). <2> set bit 2 (lvisel) of the low-voltage detection regist er (lvim) to 1 (detects level of input voltage from external input pin (exlvi)). clear bit 1 (lvimd) of lvim to 0 (generates interrupt signal when the level is detected) (default value). <3> set bit 7 (lvion) of lvim to 1 (enables lvi operation). <4> use software to wait for the following periods of time (total 410 s). ? operation stabilization time (10 s (max.)) ? minimum pulse width (200 s (min.)) ? detection delay time (200 s (max.)) <5> confirm that ?input voltage fr om external input pin (exlvi) detection voltage (v exlvi = 1.21 v (typ.))? when detecting the falling edge of exlvi, or ?input vo ltage from external input pin (exlvi) < detection voltage (v exlvi = 1.21 v (typ.))? when detecting the rising e dge of exlvi, at bit 0 (lvif) of lvim. <6> clear the interrupt request flag of lvi (lviif) to 0. <7> release the interrupt mask flag of lvi (lvimk). <8> execute the ei instruction (w hen vector interrupts are used). figure 20-10 shows the timing of the interrupt signal ge nerated by the low-voltage detector. the numbers in this timing chart correspond to <1> to <7> above. caution input voltage from external i nput pin (exlvi) must be exlvi < v dd . ? when stopping operation either of the following pr ocedures must be executed. ? when using 8-bit memory manipulation instruction: write 00h to lvim. ? when using 1-bit memory manipulation instruction: clear lvion to 0. chapter 20 low-voltage detector user?s manual u17854ej6v0ud 607 figure 20-10. timing of low-voltage detector interrupt signal generation (bit: lvisel = 1) v exlvi l lvimk flag (set by software) lvif flag intlvi lviif flag lvion flag (set by software) lvisel flag (set by software) lvimd flag (set by software) input voltage from external input pin (exlvi) time <1> note 1 <7> cleared by software <2> <3> <5> note 2 note 2 note 2 <6> cleared by software <4> wait time note 3 note 3 notes 1. the lvimk flag is set to ?1? by reset signal generation. 2. the interrupt request signal (intlvi) is generat ed and the lvif and lviif flags may be set (1). 3. if lvi operation is disabled when the input voltage of ex ternal input pin (exlvi) is less than or equal to the detection voltage (v exlvi ), an interrupt request signal (intlv i) is generated and lviif may be set to 1. remark <1> to <7> in figure 20-10 above correspond to <1> to <7> in the description of ?when starting operation? in 20.4.2 (2) when detecting level of in put voltage from external input pin (exlvi) . chapter 20 low-voltage detector user?s manual u17854ej6v0ud 608 20.5 cautions for low-voltage detector (1) measures method wh en supply voltage (v dd ) frequently fluctuates in the vicinity of the lvi detection voltage (v lvi ) in a system where the supply voltage (v dd ) fluctuates for a certain period in the vicinity of the lvi detection voltage (v lvi ), the operation is as follows depending on how the low-voltage detector is used. operation example 1: when used as reset the system may be repeatedly reset and released from the reset status. the time from reset release through microcontroller operation start can be set arbitrarily by the following action. chapter 20 low-voltage detector user?s manual u17854ej6v0ud 609 figure 20-11. example of software processing after reset release (1/2) ? if supply voltage fluctuation is 50 ms or less in vicinity of lvi detection voltage ; check the reset source, etc. note ; setting of detection level by lvis. the low-voltage detector operates (lvion = 1). reset initialization processing <1> 50 ms has passed? (tmif00 = 1?) initialization processing <2> setting timer array unit (to measure 50 ms) ; initial setting for port. setting of division ratio of system clock, such as setting of timer or a/d converter. yes no setting lvi clearing wdt detection voltage or higher (lvif = 0?) yes restarting timer array unit (tt0n = 1 ts0n = 1) no ; the timer counter is cleared and the timer is started. lvi reset ;f clk = internal high-speed oscillation clock (8.4 mhz (max.)) (default) source: f clk (8.4 mhz (max.))/2 12 , where comparison value = 102: ? 50 ms timer starts (ts0n = 1). note a flowchart is shown on the next page. remarks 1. n: channel number (n = 0 to 7) 2. if bit 2 (lvisel) of the low voltage detection register (lvim) is set to ?1?, the meanings of the above words change as follows. ? supply voltage (v dd ) input voltage from external input pin (exlvi) ? detection voltage (v lvi ) detection voltage (v exlvi = 1.21 v) chapter 20 low-voltage detector user?s manual u17854ej6v0ud 610 figure 20-11. example of software processing after reset release (2/2) ? checking reset source yes no check reset source power-on-clear/external reset generated reset processing by watchdog timer reset processing by low-voltage detector yes wdrf of resf register = 1? lvirf of resf register = 1? yes no reset processing by illegal instruction execution note trap of resf register = 1? no note when instruction code ffh is executed. reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip debug emulator. remark if bit 2 (lvisel) of the low voltage detection regist er (lvim) is set to ?1?, the meanings of the above words change as follows. ? supply voltage (v dd ) input voltage from external input pin (exlvi) ? detection voltage (v lvi ) detection voltage (v exlvi = 1.21 v) chapter 20 low-voltage detector user?s manual u17854ej6v0ud 611 operation example 2: when used as interrupt interrupt requests may be generated frequently. take the following action. user?s manual u17854ej6v0ud 612 chapter 21 regulator 21.1 regulator overview the 78k0r/ke3 contains a circuit for operating the device with a constant voltage. at this time, in order to stabilize the regulator output voltage, connect the regc pin to v ss via a capacitor (0.47 to 1 f). however, when using the stop mode that has been entered since ope ration of the internal high-speed oscillation clock and external main system clock, 0.47 f is recommended. also, use a capacitor with good characteristics, since it is used to stabilize internal voltage. the regulator output voltage is norma lly 2.5 v (typ.), and in the low consum ption current mode, 1.8 v (typ.). 21.2 registers controlling regulator (1) regulator mode c ontrol register (rmc) this register sets the output voltage of the regulator. rmc is set with an 8-bit memory manipulation instruction. reset input sets this register to 00h. figure 21-1. format of regulator mode control register (rmc) address: f00f4h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 rmc rmc[7:0] control of output voltage of regulator 5ah fixed to low consumption current mode (1.8 v) 00h switches normal current mode (2.5 v) and low consumption current mode (1.8 v) according to the condition (refer to table 21-1 ) other than above setting prohibited cautions 1. the rmc register can be rewritten only in the low cons umption current mode (refer to table 21-1). in other words, rewrite this re gister during cpu operation with the subsystem clock (f xt ) while the high-speed system clock (f mx ) and high-speed internal oscillation clock (f ih ) are both stopped. 2. when using the setting fixed to the low c onsumption current mode, the rmc register can be used in the following cases. chapter 21 regulator user?s manual u17854ej6v0ud 613 table 21-1. regulator output voltage conditions mode output voltage condition during system reset in stop mode (except during ocd mode) when both the high-speed system clock (f mx ) and the high-speed internal oscillation clock (f ih ) are stopped during cpu operati on with the subsystem clock (f xt ) low consumption current mode 1.8 v when both the high-speed system clock (f mx ) and the high-speed internal oscillation clock (f ih ) are stopped during the halt mode when the cpu operation with the subsystem clock (f xt ) has been set normal current mode 2.5 v other than above user?s manual u17854ej6v0ud 614 chapter 22 option byte 22.1 functions of option bytes addresses 000c0h to 000c3h of the flash memory of the 78k0r/ke3 form an option byte area. option bytes consist of user option byte (000c0h to 000c2h) and on-chip debug option byte (000c3h). upon power application or resetting and starting, an opti on byte is automatically referenced and a specified function is set. when using the product, be sure to se t the following functions by using the option bytes. to use the boot swap operation during self programming, 000c0h to 000c3h are replaced by 010c0h to 010c3h. therefore, set the same values as 000c0h to 000c3h to 010c0h to 010c3h. caution be sure to set ffh to 000c2h (000c2h/ 010c2h when the boot swap operation is used). 22.1.1 user option byte (000c0h to 000c2h/010c0h to 010c2h) (1) 000c0h/010c0h { operation of watchdog timer ? operation is stopped or enabl ed in the halt or stop mode. { setting of interval time of watchdog timer { operation of watchdog timer ? operation is stopped or enabled. { setting of window open period of watchdog timer { setting of interval interrupt of watchdog timer ? used or not used caution set the same value as 000c0h to 010c0h when the boot swap operation is used because 000c0h is replaced by 010c0h. (2) 000c1h/010c1h { setting of lvi upon reset release (upon power application) ? lvi is on or off by default upon reset release (re set by reset pin excluding lvi, poc, wdt, or illegal instructions). caution set the same value as 000c1h to 010c1h when the boot swap operation is used because 000c1h is replaced by 010c1h. (3) 000c2h/010c2h { be sure to set ffh, as these addresses are reserved areas. caution set ffh to 010c2h when the boot swap operation is used because 000c2h is replaced by 010c2h. chapter 22 option byte user?s manual u17854ej6v0ud 615 22.1.2 on-chip debug option byte (000c3h/ 010c3h) { control of on-chip debug operation ? on-chip debug operation is disabled or enabled. { handling of data of flash memory in case of failure in on-chip debug security id authentication ? data of flash memory is erased or not erased in case of failure in on-chip debug security id authentication. caution set the same value as 000c3h to 010c3h when the boot swap operation is used because 000c3h is replaced by 010c3h. 22.2 format of user option byte the format of user option byte is shown below. figure 22-1. format of user option byte (000c0h/010c0h) (1/2) address: 000c0h/010c0h note 1 7 6 5 4 3 2 1 0 wdtinit window1 window0 wdton wdcs2 wdcs1 wdcs0 wdstbyon wdtinit use of interval interrupt of watchdog timer 0 interval interrupt is not used. 1 interval interrupt is generated when 75% of the overflow time is reached. window1 window0 watchdog timer window open period note 2 0 0 25% 0 1 50% 1 0 75% 1 1 100% wdton operation control of watchdog timer counter 0 counter operation disabled (counting stopped after reset) 1 counter operation enabled (counting started after reset) wdcs2 wdcs1 wdcs0 watc hdog timer overflow time 0 0 0 2 10 /f il (3.88 ms) 0 0 1 2 11 /f il (7.76 ms) 0 1 0 2 12 /f il (15.52 ms) 0 1 1 2 13 /f il (31.03 ms) 1 0 0 2 15 /f il (124.12 ms) 1 0 1 2 17 /f il (496.48 ms) 1 1 0 2 18 /f il (992.97 ms) 1 1 1 2 20 /f il (3971.88 ms) chapter 22 option byte user?s manual u17854ej6v0ud 616 figure 22-1. format of user option byte (000c0h/010c0h) (2/2) address: 000c0h/010c0h note 1 7 6 5 4 3 2 1 0 wdtinit window1 window0 wdton wdcs2 wdcs1 wdcs0 wdstbyon wdstbyon operation control of watc hdog timer counter (halt/stop mode) 0 counter operation stopped in halt/stop mode note 2 1 counter operation enabled in halt/stop mode notes 1. set the same value as 000c0h to 010c0h when t he boot swap operation is used because 000c0h is replaced by 010c0h. 2. the window open period is 100% when wdstbyo n = 0, regardless the value of window1 and window0. caution the watchdog timer conti nues its operation during self-program ming of the flash memory and eeprom emulation. during processing, the inte rrupt acknowledge time is delayed. set the overflow time and window size taki ng this delay into consideration. remarks 1. f il : internal low-speed oscillation clock frequency 2. ( ): f il = 264 khz (max.) figure 22-2. format of option byte (000c1h/010c1h) address: 000c1h/010c1h note 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 lvioff lvioff setting of lvi on power application 0 lvi is on by default (lvi default start function enabled) upon reset release (upon power application) 1 lvi is off by default (lvi default start function stopped) upon reset release (upon power application) note set the same value as 000c1h to 010c1h when the boot swap operation is used because 000c1h is replaced by 010c1h. cautions 1. be sure to set bits 7 to 1 to ?1?. 2. even when the lvi default start function is u sed, if it is set to lvi operation prohibition by the software, it operates as follows: ? does not perform low-voltage detection during lvion = 0. ? if a reset is generated while lvion = 0, lvion will be re-set to 1 when the cpu starts after reset release. there is a period when low-vo ltage detection cannot be performed normally, however, when a reset occurs due to wd t and illegal instruction execution. this is due to the fact that while the pulse width detected by lvi must be 200 s max., lvion = 1 is set upon reset occurrence, and the cpu starts operating without waiting for the lvi stabilization time. chapter 22 option byte user?s manual u17854ej6v0ud 617 figure 22-3. format of option byte (000c2h/010c2h) address: 000c2h/010c2h note 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 note be sure to set ffh to 000c2h, as these addresses ar e reserved areas. also set ffh to 010c2h when the boot swap operation is used because 000c2h is replaced by 010c2h. 22.3 format of on-chip debug option byte the format of on-chip debug option byte is shown below. figure 22-4. format of on-chip de bug option byte (000c3h/010c3h) address: 000c3h/010c3h note 7 6 5 4 3 2 1 0 ocdenset 0 0 0 0 1 0 ocdersd ocdenset ocdersd control of on-chip debug operation 0 0 disables on-chip debug operation. 0 1 setting prohibited 1 0 erases data of flash memory in case of failures in enabling on-chip debugging and authenticating on-chip debug security id. 1 1 does not erases data of flash memory in case of failures in enabling on-chip debugging and authenticating on-chip debug security id. note set the same value as 000c3h to 010c3h when the boot swap operation is used because 000c3h is replaced by 010c3h. caution bits 7 and 0 (ocdenset and ocdersd) can only be specified a value. be sure to set 000010b to bits 6 to 1. remark the value on bits 3 to 1 will be written over when the on-chip debug function is in use and thus it will become unstable after the setting. however, be sure to set the default values (0, 1, and 0) to bits 3 to 1 at setting. 22.4 setting of option byte set the user option byte and on-chip debug option byte using a linker option of assembler package ra78k0r. for how to set the option byte, refer to ra78k0r assembler package user?s manual . remark the option byte is referenced during reset proce ssing. for the timing of reset processing, see chapter 18 reset function . user?s manual u17854ej6v0ud 618 chapter 23 flash memory the 78k0r/ke3 incorporates the flash memory to which a program can be written, er ased, and overwritten while mounted on the board. 23.1 writing with flash memory programmer data can be written to the flash memory on-board or o ff-board, by using a dedicated flash memory programmer. (1) on-board programming the contents of the flash memory can be rewritten afte r the 78k0r/ke3 has been mounted on the target system. the connectors that connect the dedicated flash memo ry programmer must be mounted on the target system. (2) off-board programming data can be written to the flash memory with a dedicat ed program adapter (fa seri es) before the 78k0r/ke3 is mounted on the target system. remark the fa series is a product of na ito densei machida mfg. co., ltd. table 23-1. wiring between 78k0r/ke3 and dedicated flash memory programmer pin configuration of dedicated flash memory programmer pin no. signal name i/o pin function pin name lqfp (12x12), lqfp (10x10), tqfp (7x7) note fbga (5x5) note si/rxd input receive signal tool0/p40 5 d6 so/txd output transmit signal sck output transfer clock ? ? ? clk output clock output ? ? ? /reset output reset signal reset 6 e7 flmd0 output mode signal flmd0 9 e8 v dd 15 b7 ev dd 16 a8 v dd i/o v dd voltage generation/ power monitoring av ref 47 g1 v ss 13 c7 ev ss 14 b8 gnd ? ground av ss 48 h1 note under development chapter 23 flash memory user?s manual u17854ej6v0ud 619 examples of the recommended connection when using the adapter for flash memory writing are shown below. figure 23-1. example of wiring adapter for flash memory writing (gf package) gnd vdd vdd2 writer interface gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 si so sck clk /reset flmd0 v dd (2.7 to 5.5 v) chapter 23 flash memory user?s manual u17854ej6v0ud 620 23.2 programming environment the environment required for writing a program to the fl ash memory of the 78k0r/ke3 is illustrated below. figure 23-2. environment for wr iting program to flash memory rs-232c usb 78k0r/ke3 flmd0 v dd v ss reset tool0 (dedicated single-line uart) host machine dedicated flash memory programmer pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx x x x y yy xxxxx xxxxxx xxxx x x x x y y y y s tat v e a host machine that controls the dedicated flash memory programmer is necessary. to interface between the dedicated flash memory pr ogrammer and the 78k0r/ke3, the tool0 pin is used for manipulation such as writing and erasing via a dedicated si ngle-line uart. to write the flash memory off-board, a dedicated program adapter (fa series) is necessary. 23.3 communication mode communication between the dedicated flash memory progra mmer and the 78k0r/ke3 is established by serial communication using the tool0 pin via a dedic ated single-line uart of the 78k0r/ke3. transfer rate: 115,200 bps to 1,000,000 bps figure 23-3. communication with de dicated flash memory programmer v dd /ev dd v ss /ev ss reset tool0 flmd0 flmd0 v dd gnd /reset si/rxd so/txd dedicated flash memory programmer pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx x x x y y y xxxxx xxxxxx xxxx x x x x y yy y statve 78k0r/ke3 chapter 23 flash memory user?s manual u17854ej6v0ud 621 when using the flashpro4 as the dedicated flash memory programmer, the flashpro4 generates the following signals for the 78k0r/ke3. for details, refer to the user?s manual for the flashpro4. table 23-2. pin connection flashpro4 78k0r/ke3 connection signal name i/o pin function pin name flmd0 output mode signal flmd0 v dd i/o v dd voltage generation/power monitoring v dd , ev dd , av ref gnd ? ground v ss , ev ss , av ss clk output clock output ? /reset output reset signal reset si/rxd input receive signal tool0 so/txd output transmit signal sck output transfer clock ? remark : be sure to connect the pin. : the pin does not have to be connected. 23.4 connection of pins on board to write the flash memory on-board, connectors that connect the dedicat ed flash memory programmer must be provided on the target system. first provide a function that selects the no rmal operation mode or flash memory programming mode on the board. when the flash memory programming mode is set, all the pins not used for programming the flash memory are in the same status as immediately after re set. therefore, if the external device does not recognize t he state immediately after reset, the pins must be handled as described below. 23.4.1 flmd0 pin (1) in flash memory programming mode directly connect this pin to a flash memory programmer w hen data is written by the flash memory programmer. this supplies a writing voltage of the v dd level to the flmd0 pin. the flmd0 pin does not have to be pulled down externally because it is internally pulled down by reset. to pull it down externally, use a resistor of 1 k to 200 k . (2) in normal operation mode it is recommended to leave this pin open during normal operation. the flmd0 pin must always be kept at the v ss level before reset release but does not have to be pulled down externally because it is internally pulled down by rese t. however, pulling it down must be kept selected (i.e., flmdpup = ?0?, default value) by using bit 7 (flmdpup ) of the background event control register (bectl) (see 23.5 (1) back ground event control register ). to pull it down externally, use a resistor of 200 k or smaller. self programming and the rewriting of flash memory with the programmer c an be prohibited using hardware, by directly connecting this pin to the v ss pin. chapter 23 flash memory user?s manual u17854ej6v0ud 622 (3) in self programming mode it is recommended to leave this pin open when using the se lf programming function. to pull it down externally, use a resistor of 100 k to 200 k . in the self programming mode, the setting is swit ched to pull up in the self programming library. figure 23-4. flmd0 pin connection example 78k0r/ke3 flmd0 dedicated flash memory programmer connection pin 23.4.2 tool0 pin in the flash memory programming mode, connect this pin directly to the dedicated flash memory programmer or pull it up by connecting it to ev dd via an external resistor. when on-chip debugging is enabled in the normal operat ion mode, pull this pin up by connecting it to ev dd via an external resistor, and be sure to keep inputting the v dd level to the tool0 pin before reset is released (pulling down this pin is prohibited). remark the sau and iic0 pins are not used for communica tion between the 78k0r/ke3 and dedicated flash memory programmer, because single-line uart is used. 23.4.3 reset pin signal conflict will occur if the reset signal of the ded icated flash memory programmer is connected to the reset pin that is connected to the reset sign al generator on the board. to prevent this conflict, isolate the connection with the reset signal generator. the flash memory will not be correctly prog rammed if the reset signal is input from the user system while the flash memory programming mode is set . do not input any signal ot her than the reset signal of the dedicated flash memory programmer. figure 23-5. signal conflict (reset pin) input pin dedicated flash memory programmer connection pin another device signal conflict output pin in the flash memory programming mode, a signal output by another device will conflict with the signal output by the dedicated flash memory programmer. therefore, isolate the signal of another device. 78k0r/ke3 chapter 23 flash memory user?s manual u17854ej6v0ud 623 23.4.4 port pins when the flash memory programming mode is set, all the pins not used for flash memory programming enter the same status as that immediately afte r reset. if external devices connected to the ports do not recognize the port status immediately after reset, the port pin must be connected to v dd or v ss via a resistor. 23.4.5 regc pin connect the regc pin to gnd via a capacitor (0.47 to 1 f) in the same manner as during normal operation. however, when using the stop mode t hat has been entered since operation of the internal high-speed oscillation clock and external main system clock, 0.47 f is recommended. also, use a capacitor with good characteristics, since it is used to stabilize internal voltage. 23.4.6 x1 and x2 pins connect x1 and x2 in the same status as in the normal operation mode. remark in the flash memory programming mode, the internal high-speed oscillation clock (f ih ) is used. 23.4.7 power supply to use the supply voltage output of the flash memory programmer, connect the v dd pin to v dd of the flash memory programmer, and the v ss pin to gnd of the flash memory programmer. to use the on-board supply voltage, connect in compliance with the normal operation mode. however, when using the on-board supp ly voltage, be sure to connect the v dd and v ss pins to v dd and gnd of the flash memory programmer to use the power moni tor function with the flash memory programmer. supply the same other power supplies (ev dd , ev ss , av ref , and av ss ) as those in the normal operation mode. 23.5 registers that control flash memory (1) background event control register (bectl) even if the flmd0 pin is not controlled externally, it can be controlled by so ftware with the bectl register to set the self-programming mode. however, depending on the processing of the flmd0 pin, it may not be possible to set the self-programming mode by software. when using bectl, leaving the flmd0 pin open is recommended. when pulling it down externally, use a resistor with a resistance of 100 k or more. in addition, in the normal operation mode, use bectl with the pull down selection. in the self-progra mming mode, the setting is switched to pull up in the self- programming library. the bectl register is set by a 1-bit or 8-bit memory manipula tion instruction. reset input sets this register to 00h. figure 23-6. format of background event control register (bectl) address: fffbeh after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 bectl flmdpup 0 0 0 0 0 0 0 flmdpup software control of flmd0 pin 0 selects pull-down 1 selects pull-up chapter 23 flash memory user?s manual u17854ej6v0ud 624 23.6 programming method 23.6.1 controlling flash memory the following figure illustrates the proc edure to manipulate the flash memory. figure 23-7. flash memory manipulation procedure start manipulate flash memory end? yes controlling flmd0 pin and reset pin no end flash memory programming mode is set 23.6.2 flash memory programming mode to rewrite the contents of the flash memory by using the dedicated flash memory programmer, set the 78k0r/ke3 in the flash memory programming mode. to set the mode, set the flmd0 pin and tool0 pin to v dd and clear the reset signal. change the mode by using a jumper when writing the flash memory on-board. figure 23-8. flash memory programming mode v dd reset 5.5 v 0 v v dd 0 v flmd0 v dd 0 v tool0 v dd 0 v flash memory programming mode chapter 23 flash memory user?s manual u17854ej6v0ud 625 table 23-3. relationship between flmd0 pi n and operation mode after reset release flmd0 operation mode 0 normal operation mode v dd flash memory programming mode 23.6.3 selecting communication mode communication mode of the 78k0r/ke3 as follows. table 23-4. communication modes standard setting note 1 communication mode port speed frequency multiply rate pins used 1-line mode (dedicated single-line uart) uart-ch0 1 mbps note 2 ? ? tool0 notes 1. selection items for standard settings on gu i of the flash memory programmer. 2. because factors other than the baud rate error, such as the signal waveform slew, also affect uart communication, thoroughly evaluate the slew as well as the baud rate error. 23.6.4 communication commands the 78k0r/ke3 communicates with the dedicated flash memory programmer by using commands. the signals sent from the flash memory programmer to the 78k0r/ ke3 are called commands, and the signals sent from the 78k0r/ke3 to the dedicated flash memory programmer are called response. figure 23-9. communication commands command response 78k0r/ke3 dedicated flash memory programmer pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx x x x y y y x x x x x x x x x x x x x x x x x x x y y y y statve the flash memory control commands of the 78k0r/ke3 are listed in the t able below. all these commands are issued from the programmer and the 78k0r/ke3 perform processing corresponding to the respective commands. chapter 23 flash memory user?s manual u17854ej6v0ud 626 table 23-5. flash memory control commands classification command name function verify verify compares the contents of a specified area of the flash memory with data transmitted from the programmer. chip erase erases the entire flash memory. erase block erase erases a specified area in the flash memory. blank check block blank check checks if a specified block in the flash memory has been correctly erased. write programming writes data to a sp ecified area in the flash memory. silicon signature gets 78k0r/ke3 information (such as the part number and flash memory configuration). version get gets the 78k0r/ke3 firmware version. getting information checksum gets the checksum data for a specified area. security security set sets security information. reset used to detect synchronization status of communication. others baud rate set sets baud rate when uart communication mode is selected. the 78k0r/ke3 return a response for the command issued by the dedicated flash memory programmer. the response names sent from the 78k0r/ke3 are listed below. table 23-6. response names response name function ack acknowledges command/data. nak acknowledges illegal command/data. chapter 23 flash memory user?s manual u17854ej6v0ud 627 23.7 security settings the 78k0r/ke3 supports a security functi on that prohibits rewritin g the user program writt en to the internal flash memory, so that the program cannot be changed by an unauthorized person. the operations shown below can be performed using the se curity set command. the security setting is valid when the programming mode is set next. ? disabling batch erase (chip erase) execution of the block erase and batch erase (chip eras e) commands for entire blocks in the flash memory is prohibited by this setting during on-board/off-board prog ramming. once execution of the batch erase (chip erase) command is prohibited, all of the prohibition settings (including prohibition of batch erase (chip erase)) can no longer be cancelled. caution after the security setting for the batch erase is set, erasure ca nnot be performed for the device. in addition, even if a write command is executed, data different from that which has already been written to the flash memory cannot be wr itten, because th e erase command is disabled. ? disabling block erase execution of the block erase command fo r a specific block in the flash memo ry is prohibited during on-board/off- board programming. however, blocks can be erased by means of self programming. ? disabling write execution of the write and block erase commands for entire blocks in the flash memory is prohibited during on- board/off-board programming. however, blocks can be written by means of self programming. ? disabling rewriting boot cluster 0 execution of the batch erase (chi p erase) command, block erase command, and write command on boot cluster 0 in the flash memory is prohibited by this setting. the batch erase (chip erase), block eras e, write commands, and rewriting boot cluster 0 are enabled by the default setting when the flash memory is shipped. security can be set by on-board/off-board programming and self programming. each security setting can be used in combination. all the security settings are cleared by exec uting the batch erase (chip erase) command. table 23-7 shows the relationship between the erase a nd write commands when the 78k0r/ke3 security function is enabled. remark to prohibit writing and erasing during self-programming, use the flash sealed window function (see 23.8.2 for detail). chapter 23 flash memory user?s manual u17854ej6v0ud 628 table 23-7. relationship between en abling security function and command (1) during on-board/off-board programming executed command valid security batch erase (chip erase) block erase write prohibition of batch erase (c hip erase) cannot be erased in batch can be performed note . prohibition of block erase can be performed. prohibition of writing can be erased in batch. blocks cannot be erased. cannot be performed. prohibition of rewriting boot cluster 0 cannot be erased in batch boot cluster 0 cannot be erased. boot cluster 0 cannot be written. note confirm that no data has been wri tten to the write area. because data cannot be erased after batch erase (chip erase) is prohibited, do not wr ite data if the data has not been erased. (2) during self programming executed command valid security block erase write prohibition of batch erase (chip erase) prohibition of block erase prohibition of writing blocks can be erased. can be performed. prohibition of rewriting boot cluster 0 boot cluster 0 cannot be erased. boot cluster 0 cannot be written. remark to prohibit writing and erasing during self-programming, use the flash sealed window function (see 23.8.2 for detail). table 23-8. setting security in each programming mode (1) on-board/off-board programming security security setting how to disable security setting prohibition of batch erase (chip er ase) cannot be disabled after set. prohibition of block erase prohibition of writing execute batch erase (chip erase) command prohibition of rewriting boot cluster 0 set via gui of dedicated flash memory programmer, etc. cannot be disabled after set. (2) self programming security security setting how to disable security setting prohibition of batch erase (chip er ase) cannot be disabled after set. prohibition of block erase prohibition of writing prohibition of rewriting boot cluster 0 set by using information library. execute batch erase (chip erase) command during on-board/off-board programming (cannot be disabled during self programming) chapter 23 flash memory user?s manual u17854ej6v0ud 629 23.8 flash memory programming by self-programming the 78k0r/ke3 supports a self-programming function that can be used to rewrite the flash memory via a user program. because this function allows a user application to rewrite the flash memory by using the 78k0r/ke3 self- programming library, it can be used to upgrade the program in the field. if an interrupt occurs during self-programming, self -programming can be temporarily stopped and interrupt servicing can be executed. if an unma sked interrupt request is generated in the ei state, t he request branches directly from the self-programming library to the interrupt routine. after the self-programming mode is later restored, self-programming can be resumed. however, the interrupt response time is differ ent from that of the normal operation mode. remark for details of the self-programming function and the 78k0r/ke3 self-programming library, refer to 78k0r microcontroller self programming library type01 user?s manual (u18706e) . cautions 1. the self-programmi ng function cannot be used when th e cpu operates with the subsystem clock. 2. in the self-programming mode, call the self-programming start library (flashstart). 3. to prohibit an interrupt during self-progra mming, in the same way as in the normal operation mode, execute the self-programming lib rary in the state where the ie flag is cleared (0) by the di instruction. to enable an interrupt, clear (0 ) the interrupt mask flag to accept in the state where the ie flag is set (1) by the ei instruction, and then execute the self-programming library. 4. the self-programming function is disabled in the low consumption curre nt mode. for details of the low consumption current mode, see chapter 21 regulator. chapter 23 flash memory user?s manual u17854ej6v0ud 630 the following figure illustrates a flow of rewriting t he flash memory by using a self programming library. figure 23-10. flow of self programming (rewriting flash memory) flashstart flashenv checkflmd flashblockblankcheck yes no flashblockerase flashwordwrite flashblockverify flashend yes no no flashblockerase flashwordwrite flashblockverify yes start of self programming normal completion setting operating environment normal completion? end of self programming normal completion? normal completion? error remark for details of the self programming library, refer to 78k0r microcontroller se lf programming library type01 user?s manual (u18706e) . chapter 23 flash memory user?s manual u17854ej6v0ud 631 23.8.1 boot swap function if rewriting the boot area failed by temporary power failure or other reasons, restarti ng a program by resetting or overwriting is disabled due to dat a destruction in the boot area. the boot swap function is used to avoid this problem. before erasing boot cluster 0 note , which is a boot program area, by self-p rogramming, write a new boot program to boot cluster 1 in advance. when the program has been correctly written to boot cluster 1, swap this boot cluster 1 and boot cluster 0 by using the set information function of the firmw are of the 78k0r/ke3, so that boot cluster 1 is used as a boot area. after that, erase or write the or iginal boot program area, boot cluster 0. as a result, even if a power failure occurs while the bo ot programming area is being rewritten, the program is executed correctly because it is booted from boot cluster 1 to be swapped when the program is reset and started next. note a boot cluster is a 4 kb area and boot clusters 0 and 1 are swapped by the boot swap function. figure 23-11. boot swap function boot program (boot cluster 0) new boot program (boot cluster 1) user program self-programming to boot cluster 1 self-programming to boot cluster 0 execution of boot swap by firmware user program boot program (boot cluster 0) user program new user program (boot cluster 0) new boot program (boot cluster 1) user program new boot program (boot cluster 1) boot program (boot cluster 0) user program xxxxxh 02000h 00000h 01000h boot boot boot boot in an example of above figure, it is as follows. boot cluster 0: boot program area before boot swap boot cluster 1: boot program area after boot swap chapter 23 flash memory user?s manual u17854ej6v0ud 632 figure 23-12. example of executing boot swapping boot cluster 1 booted by boot cluster 0 booted by boot cluster 1 block number erasing block 2 boot cluster 0 program program 01000h 00000h 01000h 00000h erasing block 3 writing blocks 2 and 3 boot swap 3 2 1 0 boot program boot program program boot program boot program boot program boot program boot program boot program new boot program new boot program boot program boot program new boot program new boot program erasing block 2 erasing block 3 boot program new boot program new boot program new boot program new boot program writing blocks 2 and 3 new program new program new boot program new boot program 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 chapter 23 flash memory user?s manual u17854ej6v0ud 633 23.8.2 flash shield window function the flash shield window function is provided as one of the security functions for self-programming. writing and erasing to the flash memory within the range specified as a window are enabled during self- programming, and writing and erasing to the flash memory outside the specified range are prohibited. the window range can be expanded or reduced by setting and change during on-board/off-board programming and self-programming. however, the shield function be comes effective only during self-programming. in on- board/off-board programming, writing and erasing to the flash memory outside the window range are enabled. caution if the rewrite-prohibited area of the boot cl uster 0 overlaps with the fl ash shield window range, prohibition to rewrite the bo ot cluster 0 takes priority. table 23-9. relationship between flash shield wi ndow function setting/change methods and commands execution commands programming conditions window range setting/change methods block erase write self-programming specify the starting and ending blocks by the set information library. block erasing is enabled only within the window range. writing is enabled only within the range of window range. on-board/off-board programming specify the starting and ending blocks on gui of dedicated flash memory programmer, etc. block erasing is enabled also outside the window range. writing is enabled also outside the window range. remark see 23.7 security settings to prohibit writing/erasing during on-board/off-board programming. user?s manual u17854ej6v0ud 634 chapter 24 on-chip debug function 24.1 connecting qb-mini2 to 78k0r/ke3 the 78k0r/ke3 uses the v dd , flmd0, reset, tool0, tool1 note , and v ss pins to communicate with the host machine via an on-chip debug emulator (qb-mini2). caution the 78k0r/ke3 has an on-chip debug functi on. do not use this product for mass production because its reliability cannot be guaranteed after the on-chip de bug function has been used, given the issue of the number of times the flash memory can be rewritten. nec electronics does not accept complaints c oncerning this product. figure 24-1. connection exampl e of qb-mini2 and 78k0r/ke3 v dd flmd0 tool0 reset_in clk_in rxd flmd0 reset v dd reset_out qb-mini2 target connector gnd tool1 v ss ev dd txd 78k0r/ke3 target reset note 1 note 2 note 2 notes 1. connection is not required for communication in 1-line mode but required for communication in 2-line mode. at this time, perform necessary connections according to table 2-2 connection of unused pins since tool1 is an unused pin when qb-mini2 is unconnected. 2. connecting the dotted line is not necessary si nce rxd and txd are shorted within qb-min2. when using the other flash memory programmer, rxd and txd may not be shorted within the programmer. in this case, they must be sh orted on the target system. remark the flmd0 pin is recommended to be open for self-programming in on-chip debugging. to pull down externally, use a resistor of 100 k or more. 1-line mode (single line uart) using the tool0 pin or 2- line mode using the tool0 and tool1 pins is used for serial communication for flash memory programming, 1-line mode is used. 1-line mode or 2-line mode is used for on- chip debugging. table 24-1 lists the differences between 1-line mode and 2-line mode. chapter 24 on-chip debug function user?s manual u17854ej6v0ud 635 table 24-1. lists the differences be tween 1-line mode and 2-line mode. communicat ion mode flash memory programming function debugging function 1-line mode available ? pseudo real-time ram monitor (rrm) function not supported. ? dmm function (rewriting memory in run) not supported. ? the debugger speed is two to four times slower than 2-line mode. 2-line mode none ? pseudo real-time ram monitor (rrm) function supported ? dmm function (rewriting memory in run) supported remark 2-line mode is not used for flash programming, howeve r, even if tool1 pin is connected with clk_in of qb-mini2, writing is perform ed normally with no problem. 24.2 on-chip debug security id the 78k0r/ke3 has an on-chip debug operation c ontrol bit in the flash memory at 000c3h (see chapter 22 option byte ) and an on-chip debug security id setting area at 000c4h to 000cdh, to prevent third parties from reading memory content. when the boot swap function is used, also set a value t hat is the same as that of 010c3h and 010c4h to 010cdh in advance, because 000c3h, 000c4h to 000cdh and 010c3h, and 010c4h to 010cdh are switched. for details on the on-chip debug security id, refer to the qb-mini2 on-chip debug emulator with programming function user?s manual (u18371e) . table 24-2. on-chip debug security id address on-chip debug security id 000c4h to 000cdh 010c4h to 010cdh any id code of 10 bytes 24.3 securing of user resources to perform communication between the 78k0r/ke3 and qb-mi ni2, as well as each d ebug function, the securing of memory space must be done beforehand. if nec electronics assembler ra78k0r or compiler cc78k0r is used, the items can be set by using linker options. (1) securement of memory space the shaded portions in figure 24-2 are the areas reserv ed for placing the debug monitor program, so user programs or data cannot be allocated in these spaces . when using the on-chip deb ug function, these spaces must be secured so as not to be used by the user progra m. moreover, this area must not be rewritten by the user program. chapter 24 on-chip debug function user?s manual u17854ej6v0ud 636 figure 24-2. memory spaces where de bug monitor programs are allocated (1 kb) : area used for on-chip debugging note 1 note 2 internal rom use prohibited internal ram internal rom area boot cruster 1 debug monitor area (10 bytes) debug monitor area (2 bytes) debug monitor area (2 bytes) security id area (10 bytes) debug monitor area (10 bytes) security id area (10 bytes) on-chip debug option byte area (1 byte) on-chip debug option byte area (1 byte) note 2 stack area for debugging (6 bytes) note 3 02000h 010d8h 010ceh 010c4h 010c3h 01002h 01000h 000d8h 000ceh 000c4h 000c3h 00002h 00000h internal ram area boot cruster 0 notes 1. address differs depending on products as follows. products internal rom address pd78f1142 64 kb 0fc00h-0ffffh pd78f1143 96 kb 17c00h-17fffh pd78f1144 128 kb 1fc00h-1ffffh pd78f1145 192 kb 2fc00h-2ffffh pd78f1146 256 kb 3fc00h-3ffffh 2. in debugging, reset vector is rewritten to address allocated to a monitor program. 3. since this area is allocated immediately before the stack area, the address of this area varies depending on the stack increase and decrease. that is, 6 ex tra bytes are consumed for the stack area used. for details of the way to secure of the memory space, refer to the qb-mini2 on-chip debug emulator with programming function u ser?s manual (u18371e) . user?s manual u17854ej6v0ud 637 chapter 25 bcd correction circuit 25.1 bcd correction circuit function the result of addition/subtraction of the bcd (binary-coded decimal) code and bcd code can be obtained as bcd code with this circuit. the decimal correction operation result is obtained by perf orming addition/subtraction having the a register as the operand and then adding/ subtracting the bcdadj register. 25.2 registers used by bcd correction circuit the bcd correction circuit uses the following registers. ? bcd correction result register (bcdadj) (1) bcd correction result register (bcdadj) the bcdadj register stores correct ion values for obtaini ng the add/subtract resu lt as bcd code through add/subtract instructions using t he a register as the operand. the value read from the bcdadj regist er varies depending on the value of the a register when it is read and those of the cy and ac flags. bcdadj is read by an 8-bit memory manipulation instruction. reset input sets this register to undefined. figure 25-1. format of bcd correct ion result register (bcdadj) address: f00feh after reset: undefined r symbol 7 6 5 4 3 2 1 0 bcdadj chapter 25 bcd correction circuit user?s manual u17854ej6v0ud 638 25.3 bcd correction circuit operation the basic operation of the bcd correction circuit is as follows. (1) addition: calculating the result of adding a bcd code value and another bcd code value by using a bcd code value <1> the bcd code value to which addition is performed is stored in the a register. <2> by adding the value of the a register and the second operand (value of one more bcd code to be added) as are in binary, the binary operation result is stored in the a register and the correction value is stored in the bcdadj register. <3> decimal correction is performed by adding in binary t he value of the a register (addition result in binary) and the bcdadj register (correction value), and the correction result is stored in the a register and cy register. caution the value read from the bcdadj regist er varies depending on the value of the a register when it is read and those of th e cy and ac flags. therefore, execute the instruction <3> after the instru ction <2> instead of executing any other instructions. to perform bcd correction in the interrupt en abled state, saving and restoring the a register is required within the interrupt func tion. psw (cy flag and ac flag) is restored by the reti instruction. an example is shown below. examples 1: 99 + 89 = 188 instruction a register cy register ac flag bcdadj register mov a, #99h ; <1> 99h ? ? ? add a, #89h ; <2> 22h 1 1 66h add a, !bcdadj ; <3> 88h 1 0 ? examples 2: 85 + 15 = 100 instruction a register cy register ac flag bcdadj register mov a, #85h ; <1> 85h ? ? ? add a, #15h ; <2> 9ah 0 0 06h add a, !bcdadj ; <3> 00h 1 1 ? examples 3: 80 + 80 = 160 instruction a register cy register ac flag bcdadj register mov a, #80h ; <1> 80h ? ? ? add a, #80h ; <2> 00h 1 0 60h add a, !bcdadj ; <3> 60h 1 0 ? chapter 25 bcd correction circuit user?s manual u17854ej6v0ud 639 (2) subtraction: calculating the r esult of subtracting a bcd code valu e from another bcd code value by using a bcd code value <1> the bcd code value from which subtracti on is performed is stored in the a register. <2> by subtracting the value of the second operand (value of bcd code to be subtracted) from the a register as is in binary, the calculation result in binary is st ored in the a register, and the correction value is stored in the bcdadj register. <3> decimal correction is performed by subtracting the va lue of the bcdadj register (correction value) from the a register (subtraction result in binary) in binary, and the correction result is stored in the a register and cy register. caution the value read from the bcdadj regist er varies depending on the value of the a register when it is read and those of th e cy and ac flags. therefore, execute the instruction <3> after the instru ction <2> instead of executing any other instructions. to perform bcd correction in the interrupt en abled state, saving and restoring the a register is required within the interrupt func tion. psw (cy flag and ac flag) is restored by the reti instruction. an example is shown below. example: 91 ? 52 = 39 instruction a register cy register ac flag bcdadj register mov a, #91h ; <1> 91h ? ? ? sub a, #52h ; <2> 3fh 0 1 06h sub a, !bcdadj ; <3> 39h 0 0 ? user?s manual u17854ej6v0ud 640 chapter 26 instruction set this chapter lists the instructions in the 78k0r microcont roller instruction set. for details of each operation and operation code, refer to the separate document 78k0r microcontrollers instru ctions user?s manual (u17792e) . remark the shaded parts of the tables in table 26-5 operation list indicate the operation or instruction format that is newly added for the 78k0r microcontrollers. 26.1 conventions used in operation list 26.1.1 operand identifier s and specification methods operands are described in the ?operand? column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler s pecifications for details). when there are two or more description methods, select one of them. al phabetic letters in capitals and the sym bols, #, !, !!, $, $!, [ ], and es: are keywords and are described as they are. each symbol has the following meaning. ? #: immediate data specification ? !: 16-bit absolute address specification ? !!: 20-bit absolute address specification ? $: 8-bit relative address specification ? $!: 16-bit relative address specification ? [ ]: indirect address specification ? es:: extension address specification in the case of immediate data, describe an appropriate nu meric value or a label. when using a label, be sure to describe the #, !, !!, $, $!, [ ], and es: symbols. for operand register identifiers, r and rp, either function names (x, a, c, etc.) or absolute names (names in parentheses in the table below, r0, r1 , r2, etc.) can be used for description. table 26-1. operand identifi ers and specification methods identifier description method r rp sfr sfrp x (r0), a (r1), c (r2), b (r3), e (r4), d (r5), l (r6), h (r7) ax (rp0), bc (rp1), de (rp2), hl (rp3) special-function register symbol (sfr symbol) special-function register sy mbols (16-bit manipulatable sf r symbol. even addresses only note ) saddr saddrp ffe20h to fff1fh immediate data or labels ffe20h to ff1fh immediate data or labels (even addresses only note ) addr20 addr16 addr5 00000h to fffffh immediate data or labels 0000h to ffffh immediate data or labels (only ev en addresses for 16-bit data transfer instructions note ) 0080h to 00bfh immediate data or labels (even addresses only) word byte bit 16-bit immediate data or label 8-bit immediate data or label 3-bit immediate data or label rbn rb0 to rb3 note bit 0 = 0 when an odd address is specified. remark for special-function register symbol, see table 3-5 sfr list and table 3-6 extended sfr (2nd sfr) list . chapter 26 instruction set user?s manual u17854ej6v0ud 641 26.1.2 description of operation column the operation when the instruction is exec uted is shown in the ?operation? colu mn using the following symbols. table 26-2. symbols in ?operation? column symbol function a a register; 8-bit accumulator x x register b b register c c register d d register e e register h h register l l register es es register cs cs register ax ax register pair; 16-bit accumulator bc bc register pair de de register pair hl hl register pair pc program counter sp stack pointer psw program status word cy carry flag ac auxiliary carry flag z zero flag rbs register bank select flag ie interrupt request enable flag () memory contents indicated by address or register contents in parentheses x h , x l x s , x h , x l 16-bit registers: x h = higher 8 bits, x l = lower 8 bits 20-bit registers: x s = (bits 19 to 16), x h = (bits 15 to 8), x l = (bits 7 to 0) logical product (and) logical sum (or) exclusive logical sum (exclusive or) ? inverted data addr5 16-bit immediate data (even addresses only in 0080h to 00bfh) addr16 16-bit immediate data addr20 20-bit immediate data jdisp8 signed 8-bit data (displacement value) jdisp16 signed 16-bit data (displacement value) chapter 26 instruction set user?s manual u17854ej6v0ud 642 26.1.3 description of flag operation column the change of the flag value when the in struction is executed is shown in t he ?flag? column using the following symbols. table 26-3. symbols in ?flag? column symbol change of flag value (blank) 0 1 r unchanged cleared to 0 set to 1 set/cleared according to the result previously saved value is restored 26.1.4 prefix instruction instructions with ?es:? have a prefix operation code as a prefix to extend t he accessible data area to the 1 mb space (00000h to fffffh), by adding the es register va lue to the 64 kb space from f0000h to fffffh. when a prefix operation code is attached as a pr efix to the target instruction, only one instruction immediately after the prefix operation code is executed as the addr esses with the es register value added. table 26-4. use example of prefix operation code opcode instruction 1 2 3 4 5 mov !addr16, #byte cfh !addr16 #byte ? mov es:!addr16, #byte 11h cfh !addr16 #byte mov a, [hl] 8bh ? ? ? ? mov a, es:[hl] 11h 8bh ? ? ? caution set the es register value with mov es, a, etc., before executing th e prefix instruction. chapter 26 instruction set user?s manual u17854ej6v0ud 643 26.2 operation list table 26-5. operation list (1/17) clocks flag instruction group mnemonic operands bytes note 1 note 2 operation z ac cy r, #byte 2 1 ? r byte saddr, #byte 3 1 ? (saddr) byte sfr, #byte 3 1 ? sfr byte !addr16, #byte 4 1 ? (addr16) byte a, r note 3 1 1 ? a r r, a note 3 1 1 ? r a a, saddr 2 1 ? a (saddr) saddr, a 2 1 ? (saddr) a a, sfr 2 1 ? a sfr sfr, a 2 1 ? sfr a a, !addr16 3 1 4 a (addr16) !addr16, a 3 1 ? (addr16) a psw, #byte 3 3 ? psw byte a, psw 2 1 ? a psw psw, a 2 3 ? psw a es, #byte 2 1 ? es byte es, saddr 3 1 ? es (saddr) a, es 2 1 ? a es es, a 2 1 ? es a cs, #byte 3 1 ? cs byte a, cs 2 1 ? a cs cs, a 2 1 ? cs a a, [de] 1 1 4 a (de) [de], a 1 1 ? (de) a [de + byte], #byte 3 1 ? (de + byte) byte a, [de + byte] 2 1 4 a (de + byte) [de + byte], a 2 1 ? (de + byte) a a, [hl] 1 1 4 a (hl) [hl], a 1 1 ? (hl) a 8-bit data transfer mov [hl + byte], #byte 3 1 ? (hl + byte) byte notes 1. when the internal ram area or sfr area is a ccessed, or for an instruction with no data access. 2. when the program memory area is accessed. 3. except r = a remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the system clock control register (ckc). 2. this number of clocks is for when the program is in the internal rom (flash memory) area. chapter 26 instruction set user?s manual u17854ej6v0ud 644 table 26-5. operation list (2/17) clocks flag instruction group mnemonic operands bytes note 1 note 2 operation z ac cy a, [hl + byte] 2 1 4 a (hl + byte) [hl + byte], a 2 1 ? (hl + byte) a a, [hl + b] 2 1 4 a (hl + b) [hl + b], a 2 1 ? (hl + b) a a, [hl + c] 2 1 4 a (hl + c) [hl + c], a 2 1 ? (hl + c) a word[b], #byte 4 1 ? (b + word) byte a, word[b] 3 1 4 a (b + word) word[b], a 3 1 ? (b + word) a word[c], #byte 4 1 ? (c + word) byte a, word[c] 3 1 4 a (c + word) word[c], a 3 1 ? (c + word) a word[bc], #byte 4 1 ? (bc + word) byte a, word[bc] 3 1 4 a (bc + word) word[bc], a 3 1 ? (bc + word) a [sp + byte], #byte 3 1 ? (sp + byte) byte a, [sp + byte] 2 1 ? a (sp + byte) [sp + byte], a 2 1 ? (sp + byte) a b, saddr 2 1 ? b (saddr) b, !addr16 3 1 4 b (addr16) c, saddr 2 1 ? c (saddr) c, !addr16 3 1 4 c (addr16) x, saddr 2 1 ? x (saddr) x, !addr16 3 1 4 x (addr16) es:!addr16, #byte 5 2 ? (es, addr16) byte a, es:!addr16 4 2 5 a (es, addr16) es:!addr16, a 4 2 ? (es, addr16) a a, es:[de] 2 2 5 a (es, de) es:[de], a 2 2 ? (es, de) a es:[de + byte],#byte 4 2 ? ((es, de) + byte) byte a, es:[de + byte] 3 2 5 a ((es, de) + byte) 8-bit data transfer mov es:[de + byte], a 3 2 ? ((es, de) + byte) a notes 1. when the internal ram area or sfr area is a ccessed, or for an instruction with no data access. 2. when the program memory area is accessed. remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the system clock control register (ckc). 2. this number of clocks is for when the program is in the internal rom (flash memory) area. chapter 26 instruction set user?s manual u17854ej6v0ud 645 table 26-5. operation list (3/17) clocks flag instruction group mnemonic operands bytes note 1 note 2 operation z ac cy a, es:[hl] 2 2 5 a (es, hl) es:[hl], a 2 2 ? (es, hl) a es:[hl + byte],#byte 4 2 ? ((es, hl) + byte) byte a, es:[hl + byte] 3 2 5 a ((es, hl) + byte) es:[hl + byte], a 3 2 ? ((es, hl) + byte) a a, es:[hl + b] 3 2 5 a ((es, hl) + b) es:[hl + b], a 3 2 ? ((es, hl) + b) a a, es:[hl + c] 3 2 5 a ((es, hl) + c) es:[hl + c], a 3 2 ? ((es, hl) + c) a es:word[b], #byte 5 2 ? ((es, b) + word) byte a, es:word[b] 4 2 5 a ((es, b) + word) es:word[b], a 4 2 ? ((es, b) + word) a es:word[c], #byte 5 2 ? ((es, c) + word) byte a, es:word[c] 4 2 5 a ((es, c) + word) es:word[c], a 4 2 ? ((es, c) + word) a es:word[bc], #byte 5 2 ? ((es, bc) + word) byte a, es:word[bc] 4 2 5 a ((es, bc) + word) es:word[bc], a 4 2 ? ((es, bc) + word) a b, es:!addr16 4 2 5 b (es, addr16) c, es:!addr16 4 2 5 c (es, addr16) mov x, es:!addr16 4 2 5 x (es, addr16) a, r note 3 1 (r = x) 2 (other than r = x) 1 ? a r a, saddr 3 2 ? a (saddr) a, sfr 3 2 ? a sfr a, !addr16 4 2 ? a (addr16) a, [de] 2 2 ? a (de) a, [de + byte] 3 2 ? a (de + byte) a, [hl] 2 2 ? a (hl) a, [hl + byte] 3 2 ? a (hl + byte) a, [hl + b] 2 2 ? a (hl + b) 8-bit data transfer xch a, [hl + c] 2 2 ? a (hl + c) notes 1. when the internal ram area or sfr area is a ccessed, or for an instruction with no data access. 2. when the program memory area is accessed. 3. except r = a remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the system clock control register (ckc). 2. this number of clocks is for when the program is in the internal rom (flash memory) area. chapter 26 instruction set user?s manual u17854ej6v0ud 646 table 26-5. operation list (4/17) clocks flag instruction group mnemonic operands bytes note 1 note 2 operation z ac cy a, es:!addr16 5 3 ? a (es, addr16) a, es:[de] 3 3 ? a (es, de) a, es:[de + byte] 4 3 ? a ((es, de) + byte) a, es:[hl] 3 3 ? a (es, hl) a, es:[hl + byte] 4 3 ? a ((es, hl) + byte) a, es:[hl + b] 3 3 ? a ((es, hl) + b) xch a, es:[hl + c] 3 3 ? a ((es, hl) + c) a 1 1 ? a 01h x 1 1 ? x 01h b 1 1 ? b 01h c 1 1 ? c 01h saddr 2 1 ? (saddr) 01h !addr16 3 1 ? (addr16) 01h oneb es:!addr16 4 2 ? (es, addr16) 01h a 1 1 ? a 00h x 1 1 ? x 00h b 1 1 ? b 00h c 1 1 ? c 00h saddr 2 1 ? (saddr) 00h !addr16 3 1 ? (addr16) 00h clrb es:!addr16 4 2 ? (es,addr16) 00h [hl + byte], x 3 1 ? (hl + byte) x 8-bit data transfer movs es:[hl + byte], x 4 2 ? (es, hl + byte) x rp, #word 3 1 ? rp word saddrp, #word 4 1 ? (saddrp) word sfrp, #word 4 1 ? sfrp word ax, saddrp 2 1 ? ax (saddrp) saddrp, ax 2 1 ? (saddrp) ax ax, sfrp 2 1 ? ax sfrp sfrp, ax 2 1 ? sfrp ax ax, rp note 3 1 1 ? ax rp 16-bit data transfer movw rp, ax note 3 1 1 ? rp ax notes 1. when the internal ram area or sfr area is a ccessed, or for an instruction with no data access. 2. when the program memory area is accessed. 3. except rp = ax remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the system clock control register (ckc). 2. this number of clocks is for when the program is in the internal rom (flash memory) area. chapter 26 instruction set user?s manual u17854ej6v0ud 647 table 26-5. operation list (5/17) clocks flag instruction group mnemonic operands bytes note 1 note 2 operation z ac cy ax, !addr16 3 1 4 ax (addr16) !addr16, ax 3 1 ? (addr16) ax ax, [de] 1 1 4 ax (de) [de], ax 1 1 ? (de) ax ax, [de + byte] 2 1 4 ax (de + byte) [de + byte], ax 2 1 ? (de + byte) ax ax, [hl] 1 1 4 ax (hl) [hl], ax 1 1 ? (hl) ax ax, [hl + byte] 2 1 4 ax (hl + byte) [hl + byte], ax 2 1 ? (hl + byte) ax ax, word[b] 3 1 4 ax (b + word) word[b], ax 3 1 ? (b + word) ax ax, word[c] 3 1 4 ax (c + word) word[c], ax 3 1 ? (c + word) ax ax, word[bc] 3 1 4 ax (bc + word) word[bc], ax 3 1 ? (bc + word) ax ax, [sp + byte] 2 1 ? ax (sp + byte) [sp + byte], ax 2 1 ? (sp + byte) ax bc, saddrp 2 1 ? bc (saddrp) bc, !addr16 3 1 4 bc (addr16) de, saddrp 2 1 ? de (saddrp) de, !addr16 3 1 4 de (addr16) hl, saddrp 2 1 ? hl (saddrp) hl, !addr16 3 1 4 hl (addr16) ax, es:!addr16 4 2 5 ax (es, addr16) es:!addr16, ax 4 2 ? (es, addr16) ax ax, es:[de] 2 2 5 ax (es, de) es:[de], ax 2 2 ? (es, de) ax ax, es:[de + byte] 3 2 5 ax ((es, de) + byte) es:[de + byte], ax 3 2 ? ((es, de) + byte) ax ax, es:[hl] 2 2 5 ax (es, hl) 16-bit data transfer movw es:[hl], ax 2 2 ? (es, hl) ax notes 1. when the internal ram area or sfr area is a ccessed, or for an instruction with no data access. 2. when the program memory area is accessed. remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the system clock control register (ckc). 2. this number of clocks is for when the program is in the internal rom (flash memory) area. chapter 26 instruction set user?s manual u17854ej6v0ud 648 table 26-5. operation list (6/17) clocks flag instruction group mnemonic operands bytes note 1 note 2 operation z ac cy ax, es:[hl + byte] 3 2 5 ax ((es, hl) + byte) es:[hl + byte], ax 3 2 ? ((es, hl) + byte) ax ax, es:word[b] 4 2 5 ax ((es, b) + word) es:word[b], ax 4 2 ? ((es, b) + word) ax ax, es:word[c] 4 2 5 ax ((es, c) + word) es:word[c], ax 4 2 ? ((es, c) + word) ax ax, es:word[bc] 4 2 5 ax ((es, bc) + word) es:word[bc], ax 4 2 ? ((es, bc) + word) ax bc, es:!addr16 4 2 5 bc (es, addr16) de, es:!addr16 4 2 5 de (es, addr16) movw hl, es:!addr16 4 2 5 hl (es, addr16) xchw ax, rp note 3 1 1 ? ax rp ax 1 1 ? ax 0001h onew bc 1 1 ? bc 0001h ax 1 1 ? ax 0000h 16-bit data transfer clrw bc 1 1 ? bc 0000h a, #byte 2 1 ? a, cy a + byte saddr, #byte 3 2 ? (saddr), cy (saddr) + byte a, r note 4 2 1 ? a, cy a + r r, a 2 1 ? r, cy r + a a, saddr 2 1 ? a, cy a + (saddr) a, !addr16 3 1 4 a, cy a + (addr16) a, [hl] 1 1 4 a, cy a + (hl) a, [hl + byte] 2 1 4 a, cy a + (hl + byte) a, [hl + b] 2 1 4 a, cy a + (hl + b) a, [hl + c] 2 1 4 a, cy a + (hl + c) a, es:!addr16 4 2 5 a, cy a + (es, addr16) a, es:[hl] 2 2 5 a,cy a + (es, hl) a, es:[hl + byte] 3 2 5 a,cy a + ((es, hl) + byte) a, es:[hl + b] 3 2 5 a,cy a + ((es, hl) + b) 8-bit operation add a, es:[hl + c] 3 2 5 a,cy a + ((es, hl) + c) notes 1. when the internal ram area or sfr area is a ccessed, or for an instruction with no data access. 2. when the program memory area is accessed. 3. except rp = ax 4. except r = a remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the system clock control register (ckc). 2. this number of clocks is for when the program is in the internal rom (flash memory) area. chapter 26 instruction set user?s manual u17854ej6v0ud 649 table 26-5. operation list (7/17) clocks flag instruction group mnemonic operands bytes note 1 note 2 operation z ac cy a, #byte 2 1 ? a, cy a + byte + cy saddr, #byte 3 2 ? (saddr), cy (saddr) + byte + cy a, r note 3 2 1 ? a, cy a + r + cy r, a 2 1 ? r, cy r + a + cy a, saddr 2 1 ? a, cy a + (saddr) + cy a, !addr16 3 1 4 a, cy a + (addr16) + cy a, [hl] 1 1 4 a, cy a + (hl) + cy a, [hl + byte] 2 1 4 a, cy a + (hl + byte) + cy a, [hl + b] 2 1 4 a, cy a + (hl + b) + cy a, [hl + c] 2 1 4 a, cy a + (hl + c) + cy a, es:!addr16 4 2 5 a, cy a + (es, addr16) + cy a, es:[hl] 2 2 5 a, cy a + (es, hl) + cy a, es:[hl + byte] 3 2 5 a, cy a + ((es, hl) + byte) + cy a, es:[hl + b] 3 2 5 a, cy a + ((es, hl) + b) + cy addc a, es:[hl + c] 3 2 5 a, cy a + ((es, hl) + c) + cy a, #byte 2 1 ? a, cy a ? byte saddr, #byte 3 2 ? (saddr), cy (saddr) ? byte a, r note 3 2 1 ? a, cy a ? r r, a 2 1 ? r, cy r ? a a, saddr 2 1 ? a, cy a ? (saddr) a, !addr16 3 1 4 a, cy a ? (addr16) a, [hl] 1 1 4 a, cy a ? (hl) a, [hl + byte] 2 1 4 a, cy a ? (hl + byte) a, [hl + b] 2 1 4 a, cy a ? (hl + b) a, [hl + c] 2 1 4 a, cy a ? (hl + c) a, es:!addr16 4 2 5 a, cy a ? (es:addr16) a, es:[hl] 2 2 5 a, cy a ? (es:hl) a, es:[hl + byte] 3 2 5 a, cy a ? ((es:hl) + byte) a, es:[hl + b] 3 2 5 a, cy a ? ((es:hl) + b) 8-bit operation sub a, es:[hl + c] 3 2 5 a, cy a ? ((es:hl) + c) notes 1. when the internal ram area or sfr area is a ccessed, or for an instruction with no data access. 2. when the program memory area is accessed. 3. except r = a remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the system clock control register (ckc). 2. this number of clocks is for when the program is in the internal rom (flash memory) area. chapter 26 instruction set user?s manual u17854ej6v0ud 650 table 26-5. operation list (8/17) clocks flag instruction group mnemonic operands bytes note 1 note 2 operation z ac cy a, #byte 2 1 ? a, cy a ? byte ? cy saddr, #byte 3 2 ? (saddr), cy (saddr) ? byte ? cy a, r note 3 2 1 ? a, cy a ? r ? cy r, a 2 1 ? r, cy r ? a ? cy a, saddr 2 1 ? a, cy a ? (saddr) ? cy a, !addr16 3 1 4 a, cy a ? (addr16) ? cy a, [hl] 1 1 4 a, cy a ? (hl) ? cy a, [hl + byte] 2 1 4 a, cy a ? (hl + byte) ? cy a, [hl + b] 2 1 4 a, cy a ? (hl + b) ? cy a, [hl + c] 2 1 4 a, cy a ? (hl + c) ? cy a, es:!addr16 4 2 5 a, cy a ? (es:addr16) ? cy a, es:[hl] 2 2 5 a, cy a ? (es:hl) ? cy a, es:[hl + byte] 3 2 5 a, cy a ? ((es:hl) + byte) ? cy a, es:[hl + b] 3 2 5 a, cy a ? ((es:hl) + b) ? cy subc a, es:[hl + c] 3 2 5 a, cy a ? ((es:hl) + c) ? cy a, #byte 2 1 ? a a byte saddr, #byte 3 2 ? (saddr) (saddr) byte a, r note 3 2 1 ? a a r r, a 2 1 ? r r a a, saddr 2 1 ? a a (saddr) a, !addr16 3 1 4 a a (addr16) a, [hl] 1 1 4 a a (hl) a, [hl + byte] 2 1 4 a a (hl + byte) a, [hl + b] 2 1 4 a a (hl + b) a, [hl + c] 2 1 4 a a (hl + c) a, es:!addr16 4 2 5 a a (es:addr16) a, es:[hl] 2 2 5 a a (es:hl) a, es:[hl + byte] 3 2 5 a a ((es:hl) + byte) a, es:[hl + b] 3 2 5 a a ((es:hl) + b) 8-bit operation and a, es:[hl + c] 3 2 5 a a ((es:hl) + c) notes 1. when the internal ram area or sfr area is a ccessed, or for an instruction with no data access. 2. when the program memory area is accessed. 3. except r = a remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the system clock control register (ckc). 2. this number of clocks is for when the program is in the internal rom (flash memory) area. chapter 26 instruction set user?s manual u17854ej6v0ud 651 table 26-5. operation list (9/17) clocks flag instruction group mnemonic operands bytes note 1 note 2 operation z ac cy a, #byte 2 1 ? a a byte saddr, #byte 3 2 ? (saddr) (saddr) byte a, r note 3 2 1 ? a a r r, a 2 1 ? r r a a, saddr 2 1 ? a a (saddr) a, !addr16 3 1 4 a a (addr16) a, [hl] 1 1 4 a a (hl) a, [hl + byte] 2 1 4 a a (hl + byte) a, [hl + b] 2 1 4 a a (hl + b) a, [hl + c] 2 1 4 a a (hl + c) a, es:!addr16 4 2 5 a a (es:addr16) a, es:[hl] 2 2 5 a a (es:hl) a, es:[hl + byte] 3 2 5 a a ((es:hl) + byte) a, es:[hl + b] 3 2 5 a a ((es:hl) + b) or a, es:[hl + c] 3 2 5 a a ((es:hl) + c) a, #byte 2 1 ? a a byte saddr, #byte 3 2 ? (saddr) (saddr) byte a, r note 3 2 1 ? a a r r, a 2 1 ? r r a a, saddr 2 1 ? a a (saddr) a, !addr16 3 1 4 a a (addr16) a, [hl] 1 1 4 a a (hl) a, [hl + byte] 2 1 4 a a (hl + byte) a, [hl + b] 2 1 4 a a (hl + b) a, [hl + c] 2 1 4 a a (hl + c) a, es:!addr16 4 2 5 a a (es:addr16) a, es:[hl] 2 2 5 a a (es:hl) a, es:[hl + byte] 3 2 5 a a ((es:hl) + byte) a, es:[hl + b] 3 2 5 a a ((es:hl) + b) 8-bit operation xor a, es:[hl + c] 3 2 5 a a ((es:hl) + c) notes 1. when the internal ram area or sfr area is a ccessed, or for an instruction with no data access. 2. when the program memory area is accessed. 3. except r = a remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the system clock control register (ckc). 2. this number of clocks is for when the program is in the internal rom (flash memory) area. chapter 26 instruction set user?s manual u17854ej6v0ud 652 table 26-5. operation list (10/17) clocks flag instruction group mnemonic operands bytes note 1 note 2 operation z ac cy a, #byte 2 1 ? a ? byte saddr, #byte 3 1 ? (saddr) ? byte a, r note 3 2 1 ? a ? r r, a 2 1 ? r ? a a, saddr 2 1 ? a ? (saddr) a, !addr16 3 1 4 a ? (addr16) a, [hl] 1 1 4 a ? (hl) a, [hl + byte] 2 1 4 a ? (hl + byte) a, [hl + b] 2 1 4 a ? (hl + b) a, [hl + c] 2 1 4 a ? (hl + c) !addr16, #byte 4 1 4 (addr16) ? byte a, es:!addr16 4 2 5 a ? (es:addr16) a, es:[hl] 2 2 5 a ? (es:hl) a, es:[hl + byte] 3 2 5 a ? ((es:hl) + byte) a, es:[hl + b] 3 2 5 a ? ((es:hl) + b) a, es:[hl + c] 3 2 5 a ? ((es:hl) + c) cmp es:!addr16, #byte 5 2 5 (es:addr16) ? byte a 1 1 ? a ? 00h x 1 1 ? x ? 00h b 1 1 ? b ? 00h c 1 1 ? c ? 00h saddr 2 1 ? (saddr) ? 00h !addr16 3 1 4 (addr16) ? 00h cmp0 es:!addr16 4 2 5 (es:addr16) ? 00h x, [hl + byte] 3 1 4 x ? (hl + byte) 8-bit operation cmps x, es:[hl + byte] 4 2 5 x ? ((es:hl) + byte) notes 1. when the internal ram area or sfr area is a ccessed, or for an instruction with no data access. 2. when the program memory area is accessed. 3. except r = a remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the system clock control register (ckc). 2. this number of clocks is for when the program is in the internal rom (flash memory) area. chapter 26 instruction set user?s manual u17854ej6v0ud 653 table 26-5. operation list (11/17) clocks flag instruction group mnemonic operands bytes note 1 note 2 operation z ac cy ax, #word 3 1 ? ax, cy ax + word ax, ax 1 1 ? ax, cy ax + ax ax, bc 1 1 ? ax, cy ax + bc ax, de 1 1 ? ax, cy ax + de ax, hl 1 1 ? ax, cy ax + hl ax, saddrp 2 1 ? ax, cy ax + (saddrp) ax, !addr16 3 1 4 ax, cy ax + (addr16) ax, [hl+byte] 3 1 4 ax, cy ax + (hl + byte) ax, es:!addr16 4 2 5 ax, cy ax + (es:addr16) addw ax, es: [hl+byte] 4 2 5 ax, cy ax + ((es:hl) + byte) ax, #word 3 1 ? ax, cy ax ? word ax, bc 1 1 ? ax, cy ax ? bc ax, de 1 1 ? ax, cy ax ? de ax, hl 1 1 ? ax, cy ax ? hl ax, saddrp 2 1 ? ax, cy ax ? (saddrp) ax, !addr16 3 1 4 ax, cy ax ? (addr16) ax, [hl+byte] 3 1 4 ax, cy ax ? (hl + byte) ax, es:!addr16 4 2 5 ax, cy ax ? (es:addr16) subw ax, es: [hl+byte] 4 2 5 ax, cy ax ? ((es:hl) + byte) ax, #word 3 1 ? ax ? word ax, bc 1 1 ? ax ? bc ax, de 1 1 ? ax ? de ax, hl 1 1 ? ax ? hl ax, saddrp 2 1 ? ax ? (saddrp) ax, !addr16 3 1 4 ax ? (addr16) ax, [hl+byte] 3 1 4 ax ? (hl + byte) ax, es:!addr16 4 2 5 ax ? (es:addr16) 16-bit operation cmpw ax, es: [hl+byte] 4 2 5 ax ? ((es:hl) + byte) multiply mulu x 1 1 ? ax a x notes 1. when the internal ram area or sfr area is a ccessed, or for an instruction with no data access. 2. when the program memory area is accessed. remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the system clock control register (ckc). 2. this number of clocks is for when the program is in the internal rom (flash memory) area. chapter 26 instruction set user?s manual u17854ej6v0ud 654 table 26-5. operation list (12/17) clocks flag instruction group mnemonic operands bytes note 1 note 2 operation z ac cy r 1 1 ? r r + 1 saddr 2 2 ? (saddr) (saddr) + 1 !addr16 3 2 ? (addr16) (addr16) + 1 [hl+byte] 3 2 ? (hl+byte) (hl+byte) + 1 es:!addr16 4 3 ? (es, addr16) (es, addr16) + 1 inc es: [hl+byte] 4 3 ? ((es:hl) + byte) ((es:hl) + byte) + 1 r 1 1 ? r r ? 1 saddr 2 2 ? (saddr) (saddr) ? 1 !addr16 3 2 ? (addr16) (addr16) ? 1 [hl+byte] 3 2 ? (hl+byte) (hl+byte) ? 1 es:!addr16 4 3 ? (es, addr16) (es, addr16) ? 1 dec es: [hl+byte] 4 3 ? ((es:hl) + byte) ((es:hl) + byte) ? 1 rp 1 1 ? rp rp + 1 saddrp 2 2 ? (saddrp) (saddrp) + 1 !addr16 3 2 ? (addr16) (addr16) + 1 [hl+byte] 3 2 ? (hl+byte) (hl+byte) + 1 es:!addr16 4 3 ? (es, addr16) (es, addr16) + 1 incw es: [hl+byte] 4 3 ? ((es:hl) + byte) ((es:hl) + byte) + 1 rp 1 1 ? rp rp ? 1 saddrp 2 2 ? (saddrp) (saddrp) ? 1 !addr16 3 2 ? (addr16) (addr16) ? 1 [hl+byte] 3 2 ? (hl+byte) (hl+byte) ? 1 es:!addr16 4 3 ? (es, addr16) (es, addr16) ? 1 increment/ decrement decw es: [hl+byte] 4 3 ? ((es:hl) + byte) ((es:hl) + byte) ? 1 shr a, cnt 2 1 ? (cy a 0 , a m ? 1 a m , a 7 0) cnt shrw ax, cnt 2 1 ? (cy ax 0 , ax m ? 1 ax m , ax 15 0) cnt a, cnt 2 1 ? (cy a 7 , a m a m ? 1 , a 0 0) cnt b, cnt 2 1 ? (cy b 7 , b m b m ? 1 , b 0 0) cnt shl c, cnt 2 1 ? (cy c 7 , c m c m ? 1 , c 0 0) cnt ax, cnt 2 1 ? (cy ax 15 , ax m ax m ? 1 , ax 0 0) cnt shlw bc, cnt 2 1 ? (cy bc 15 , bc m bc m ? 1 , bc 0 0) cnt sar a, cnt 2 1 ? (cy a 0 , a m ? 1 a m , a 7 a 7 ) cnt shift sarw ax, cnt 2 1 ? (cy ax 0 , ax m ? 1 ax m , ax 15 ax 15 ) cnt notes 1. when the internal ram area or sfr area is a ccessed, or for an instruction with no data access. 2. when the program memory area is accessed. remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the system clock control register (ckc). 2. this number of clocks is for when the program is in the internal rom (flash memory) area. 3. cnt indicates the bit shift count. chapter 26 instruction set user?s manual u17854ej6v0ud 655 table 26-5. operation list (13/17) clocks flag instruction group mnemonic operands bytes note 1 note 2 operation z ac cy ror a, 1 2 1 ? (cy, a 7 a 0 , a m ? 1 a m ) 1 rol a, 1 2 1 ? (cy, a 0 a 7 , a m + 1 a m ) 1 rorc a, 1 2 1 ? (cy a 0 , a 7 cy, a m ? 1 a m ) 1 rolc a, 1 2 1 ? (cy a 7 , a 0 cy, a m + 1 a m ) 1 ax,1 2 1 ? (cy ax 15 , ax 0 cy, ax m + 1 ax m ) 1 rotate rolwc bc,1 2 1 ? (cy bc 15 , bc 0 cy, bc m + 1 bc m ) 1 cy, saddr.bit 3 1 ? cy (saddr).bit cy, sfr.bit 3 1 ? cy sfr.bit cy, a.bit 2 1 ? cy a.bit cy, psw.bit 3 1 ? cy psw.bit cy,[hl].bit 2 1 4 cy (hl).bit saddr.bit, cy 3 2 ? (saddr).bit cy sfr.bit, cy 3 2 ? sfr.bit cy a.bit, cy 2 1 ? a.bit cy psw.bit, cy 3 4 ? psw.bit cy [hl].bit, cy 2 2 ? (hl).bit cy cy, es:[hl].bit 3 2 5 cy (es, hl).bit mov1 es:[hl].bit, cy 3 3 ? (es, hl).bit cy cy, saddr.bit 3 1 ? cy cy (saddr).bit cy, sfr.bit 3 1 ? cy cy sfr.bit cy, a.bit 2 1 ? cy cy a.bit cy, psw.bit 3 1 ? cy cy psw.bit cy,[hl].bit 2 1 4 cy cy (hl).bit and1 cy, es:[hl].bit 3 2 5 cy cy (es, hl).bit cy, saddr.bit 3 1 ? cy cy (saddr).bit cy, sfr.bit 3 1 ? cy cy sfr.bit cy, a.bit 2 1 ? cy cy a.bit cy, psw.bit 3 1 ? cy cy psw.bit cy, [hl].bit 2 1 4 cy cy (hl).bit bit manipulate or1 cy, es:[hl].bit 3 2 5 cy cy (es, hl).bit notes 1. when the internal ram area or sfr area is a ccessed, or for an instruction with no data access. 2. when the program memory area is accessed. remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the system clock control register (ckc). 2. this number of clocks is for when the program is in the internal rom (flash memory) area. chapter 26 instruction set user?s manual u17854ej6v0ud 656 table 26-5. operation list (14/17) clocks flag instruction group mnemonic operands bytes note 1 note 2 operation z ac cy cy, saddr.bit 3 1 ? cy cy (saddr).bit cy, sfr.bit 3 1 ? cy cy sfr.bit cy, a.bit 2 1 ? cy cy a.bit cy, psw.bit 3 1 ? cy cy psw.bit cy, [hl].bit 2 1 4 cy cy (hl).bit xor1 cy, es:[hl].bit 3 2 5 cy cy (es, hl).bit saddr.bit 3 2 ? (saddr).bit 1 sfr.bit 3 2 ? sfr.bit 1 a.bit 2 1 ? a.bit 1 !addr16.bit 4 2 ? (addr16).bit 1 psw.bit 3 4 ? psw.bit 1 [hl].bit 2 2 ? (hl).bit 1 es:!addr16.bit 5 3 ? (es, addr16).bit 1 set1 es:[hl].bit 3 3 ? (es, hl).bit 1 saddr.bit 3 2 ? (saddr.bit) 0 sfr.bit 3 2 ? sfr.bit 0 a.bit 2 1 ? a.bit 0 !addr16.bit 4 2 ? (addr16).bit 0 psw.bit 3 4 ? psw.bit 0 [hl].bit 2 2 ? (hl).bit 0 es:!addr16.bit 5 3 ? (es, addr16).bit 0 clr1 es:[hl].bit 3 3 ? (es, hl).bit 0 set1 cy 2 1 ? cy 1 1 clr1 cy 2 1 ? cy 0 0 bit manipulate not1 cy 2 1 ? cy cy notes 1. when the internal ram area or sfr area is a ccessed, or for an instruction with no data access. 2. when the program memory area is accessed. remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the system clock control register (ckc). 2. this number of clocks is for when the program is in the internal rom (flash memory) area. chapter 26 instruction set user?s manual u17854ej6v0ud 657 table 26-5. operation list (15/17) clocks flag instruction group mnemonic operands bytes note 1 note 2 operation z ac cy rp 2 3 ? (sp ? 2) (pc + 2) s , (sp ? 3) (pc + 2) h , (sp ? 4) (pc + 2) l , pc cs, rp, sp sp ? 4 $!addr20 3 3 ? (sp ? 2) (pc + 3) s , (sp ? 3) (pc + 3) h , (sp ? 4) (pc + 3) l , pc pc + 3 + jdisp16, sp sp ? 4 !addr16 3 3 ? (sp ? 2) (pc + 3) s , (sp ? 3) (pc + 3) h , (sp ? 4) (pc + 3) l , pc 0000, addr16, sp sp ? 4 call !!addr20 4 3 ? (sp ? 2) (pc + 4) s , (sp ? 3) (pc + 4) h , (sp ? 4) (pc + 4) l , pc addr20, sp sp ? 4 callt [addr5] 2 5 ? (sp ? 2) (pc + 2) s , (sp ? 3) (pc + 2) h , (sp ? 4) (pc + 2) l , pc s 0000, pc h (0000, addr5 + 1), pc l (0000, addr5), sp sp ? 4 brk ? 2 5 ? (sp ? 1) psw, (sp ? 2) (pc + 2) s , (sp ? 3) (pc + 2) h , (sp ? 4) (pc + 2) l , pc s 0000, pc h (0007fh), pc l (0007eh), sp sp ? 4, ie 0 ret ? 1 6 ? pc l (sp), pc h (sp + 1), pc s (sp + 2), sp sp + 4 reti ? 2 6 ? pc l (sp), pc h (sp + 1), pc s (sp + 2), psw (sp + 3), sp sp + 4 r r r call/ return retb ? 2 6 ? pc l (sp), pc h (sp + 1), pc s (sp + 2), psw (sp + 3), sp sp + 4 r r r notes 1. when the internal ram area or sfr area is a ccessed, or for an instruction with no data access. 2. when the program memory area is accessed. remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the system clock control register (ckc). 2. this number of clocks is for when the program is in the internal rom (flash memory) area. chapter 26 instruction set user?s manual u17854ej6v0ud 658 table 26-5. operation list (16/17) clocks flag instruction group mnemonic operands bytes note 1 note 2 operation z ac cy psw 2 1 ? (sp ? 1) psw, (sp ? 2) 00h, sp sp ? 2 push rp 1 1 ? (sp ? 1) rp h , (sp ? 2) rp l , sp sp ? 2 psw 2 3 ? psw (sp + 1), sp sp + 2 r r r pop rp 1 1 ? rp l (sp), rp h (sp + 1), sp sp + 2 sp, #word 4 1 ? sp word sp, ax 2 1 ? sp ax ax, sp 2 1 ? ax sp hl, sp 3 1 ? hl sp bc, sp 3 1 ? bc sp movw de, sp 3 1 ? de sp addw sp, #byte 2 1 ? sp sp + byte stack manipulate subw sp, #byte 2 1 ? sp sp ? byte ax 2 3 ? pc cs, ax $addr20 2 3 ? pc pc + 2 + jdisp8 $!addr20 3 3 ? pc pc + 3 + jdisp16 !addr16 3 3 ? pc 0000, addr16 unconditio nal branch br !!addr20 4 3 ? pc addr20 bc $addr20 2 2/4 note 3 ? pc pc + 2 + jdisp8 if cy = 1 bnc $addr20 2 2/4 note 3 ? pc pc + 2 + jdisp8 if cy = 0 bz $addr20 2 2/4 note 3 ? pc pc + 2 + jdisp8 if z = 1 bnz $addr20 2 2/4 note 3 ? pc pc + 2 + jdisp8 if z = 0 bh $addr20 3 2/4 note 3 ? pc pc+3+jdisp8 if (z cy)=0 bnh $addr20 3 2/4 note 3 ? pc pc+3+jdisp8 if (z cy)=1 saddr.bit, $addr20 4 3/5 note 3 ? pc pc + 4 + jdisp8 if (saddr).bit = 1 sfr.bit, $addr20 4 3/5 note 3 ? pc pc + 4 + jdisp8 if sfr.bit = 1 a.bit, $addr20 3 3/5 note 3 ? pc pc + 3 + jdisp8 if a.bit = 1 psw.bit, $addr20 4 3/5 note 3 ? pc pc + 4 + jdisp8 if psw.bit = 1 [hl].bit, $addr20 3 3/5 note 3 6/8 pc pc + 3 + jdisp8 if (hl).bit = 1 conditional branch bt es:[hl].bit, $addr20 4 4/6 note 3 7/9 pc pc + 4 + jdisp8 if (es, hl).bit = 1 notes 1. when the internal ram area or sfr area is a ccessed, or for an instruction with no data access. 2. when the program memory area is accessed. 3. this indicates the number of clocks ?when condition is not met/when condition is met?. remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the system clock control register (ckc). 2. this number of clocks is for when the program is in the internal rom (flash memory) area. chapter 26 instruction set user?s manual u17854ej6v0ud 659 table 26-5. operation list (17/17) clocks flag instruction group mnemonic operands bytes note 1 note 2 operation z ac cy saddr.bit, $addr20 4 3/5 note 3 ? pc pc + 4 + jdisp8 if (saddr).bit = 0 sfr.bit, $addr20 4 3/5 note 3 ? pc pc + 4 + jdisp8 if sfr.bit = 0 a.bit, $addr20 3 3/5 note 3 ? pc pc + 3 + jdisp8 if a.bit = 0 psw.bit, $addr20 4 3/5 note 3 ? pc pc + 4 + jdisp8 if psw.bit = 0 [hl].bit, $addr20 3 3/5 note 3 6/8 pc pc + 3 + jdisp8 if (hl).bit = 0 bf es:[hl].bit, $addr20 4 4/6 note 3 7/9 pc pc + 4 + jdisp8 if (es, hl).bit = 0 saddr.bit, $addr20 4 3/5 note 3 ? pc pc + 4 + jdisp8 if (saddr).bit = 1 then reset (saddr).bit sfr.bit, $addr20 4 3/5 note 3 ? pc pc + 4 + jdisp8 if sfr.bit = 1 then reset sfr.bit a.bit, $addr20 3 3/5 note 3 ? pc pc + 3 + jdisp8 if a.bit = 1 then reset a.bit psw.bit, $addr20 4 5/7 note 3 ? pc pc + 4 + jdisp8 if psw.bit = 1 then reset psw.bit [hl].bit, $addr20 3 3/5 note 3 ? pc pc + 3 + jdisp8 if (hl).bit = 1 then reset (hl).bit condition al branch btclr es:[hl].bit, $addr20 4 4/6 note 3 ? pc pc + 4 + jdisp8 if (es, hl).bit = 1 then reset (es, hl).bit skc ? 2 1 ? next instruction skip if cy = 1 sknc ? 2 1 ? next instruction skip if cy = 0 skz ? 2 1 ? next instruction skip if z = 1 sknz ? 2 1 ? next instruction skip if z = 0 skh ? 2 1 ? next instruction skip if (z cy) = 0 conditional skip sknh ? 2 1 ? next instruction skip if (z cy) = 1 sel rbn 2 1 ? rbs[1:0] n nop ? 1 1 ? no operation ei ? 3 4 ? ie 1(enable interrupt) di ? 3 4 ? ie 0(disable interrupt) halt ? 2 3 ? set halt mode cpu control stop ? 2 3 ? set stop mode notes 1. when the internal ram area or sfr area is a ccessed, or for an instruction with no data access. 2. when the program memory area is accessed. 3. this indicates the number of clocks ?when condition is not met/when condition is met?. remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the system clock control register (ckc). 2. this number of clocks is for when the program is in the internal rom (flash memory) area. 3. n indicates the number of register banks (n = 0 to 3) user?s manual u17854ej6v0ud 660 chapter 27 electrical specifications caution the 78k0r/ke3 is provided with an on-chip debug function. after using the on-chip debug function, do not use the product for mass production becau se its reliability cannot be guaranteed from the viewpoint of the limit of the number of times the flash memory can be rewritten. after the on-chip debug function is used, complaints will not be accepted. absolute maximum ratings (t a = 25 c) (1/2) parameter symbols conditions ratings unit v dd ? 0.5 to +6.5 v ev dd ? 0.5 to +6.5 v v ss ? 0.5 to +0.3 v ev ss ? 0.5 to +0.3 v av ref ? 0.5 to v dd +0.3 note 1 v supply voltage av ss ? 0.5 to +0.3 v regc pin input voltage v iregc regc ? 0.3 to +3.6 and ? 0.3 to v dd +0.3 note 2 v v i1 p00 to p06, p10 to p17, p30, p31, p40 to p43, p50 to p55, p70 to p77, p120 to p124, p140, p141, exclk, reset, flmd0 ? 0.3 to ev dd +0.3 and ? 0.3 to v dd +0.3 note 1 v v i2 p60 to p63 (n-ch open-drain) ? 0.3 to +6.5 v input voltage v i3 p20 to p27 ? 0.3 to av ref +0.3 and ? 0.3 to v dd +0.3 note 1 v v o1 p00 to p06, p10 to p17, p30, p31, p40 to p43, p50 to p55, p60 to p63, p70 to p77, p120, p130, p140, p141 ? 0.3 to ev dd +0.3 note 1 v output voltage v o2 p20 to p27 ? 0.3 to av ref +0.3 v analog input voltage v an ani0 to ani7 ? 0.3 to av ref +0.3 note 1 and ? 0.3 to v dd +0.3 note 1 v notes 1. must be 6.5 v or lower. 2. connect the regc pin to v ss via a capacitor (0.47 to 1 f). this value regulates the absolute maximum rating of the regc pin. do not use this pin with voltage applied to it. caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical dama ge, and therefore the product mu st be used under conditions that ensure that the absolute maximum rati ngs are not exceeded. remark unless specified otherwise, the charac teristics of alternate-function pi ns are the same as those of port pins. chapter 27 electrical specifications user?s manual u17854ej6v0ud 661 absolute maximum ratings (t a = 25 c) (2/2) parameter symbols conditions ratings unit per pin p00 to p06, p10 to p17, p30, p31, p40 to p43, p50 to p55, p70 to p77, p120, p130, p140, p141 ? 10 ma p00 to p04, p40 to p43, p120, p130, p140, p141 ? 25 ma i oh1 total of all pins ? 80 ma p05, p06, p10 to p17, p30, p31, p50 to p55, p70 to p77 ? 55 ma per pin ? 0.5 ma output current, high i oh2 total of all pins p20 to p27 ? 2 ma per pin p00 to p06, p10 to p17, p30, p31, p40 to p43, p50 to p55, p60 to p63, p70 to p77, p120, p130, p140, p141 30 ma p00 to p04, p40 to p43, p120, p130, p140, p141 60 ma i ol1 total of all pins 200 ma p05, p06, p10 to p17, p30, p31, p50 to p55, p60 to p63, p70 to p77 140 ma per pin 1 ma output current, low i ol2 total of all pins p20 to p27 5 ma in normal operation mode operating ambient temperature t a in flash memory programming mode ? 40 to +85 c storage temperature t stg ? 65 to +150 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical dama ge, and therefore the product mu st be used under conditions that ensure that the absolute maximum rati ngs are not exceeded. remark unless specified otherwise, the charac teristics of alternate-function pi ns are the same as those of port pins. chapter 27 electrical specifications user?s manual u17854ej6v0ud 662 x1 oscillator characteristics (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, v ss = ev ss = av ss = 0 v) resonator recommended circuit parameter conditions min. typ. max. unit 2.7 v v dd 5.5 v 2.0 20.0 ceramic resonator c1 x2 x1 c2 v ss x1 clock oscillation frequency (f x ) note 1.8 v v dd < 2.7 v 2.0 5.0 mhz 2.7 v v dd 5.5 v 2.0 20.0 crystal resonator c1 x2 x1 c2 v ss x1 clock oscillation frequency (f x ) note 1.8 v v dd < 2.7 v 2.0 5.0 mhz note indicates only oscillator characteri stics. refer to ac characterist ics for instruction execution time. cautions 1. when using the x1 osc illator, wire as follows in the area encl osed by the bro ken lines in the above figures to avoid an adverse effect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. ? do not route the wiring near a signal line th rough which a high fluctuating current flows. ? always make the ground point of the o scillator capacitor the same potential as v ss . ? do not ground the capacitor to a ground pattern through which a high current flows. ? do not fetch signals from the oscillator. 2. since the cpu is started by the internal hi gh-speed oscillation clo ck after a reset release, check the x1 clock oscillation stab ilization time using the oscilla tion stabilization time counter status register (ostc) by the user. determine the oscillation stabilization time of the ostc register and oscillation stabilizat ion time select register (ost s) after sufficiently evaluating the oscillation stabilization time with the resonator to be used. remark for the resonator selection and oscillator constan t, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. chapter 27 electrical specifications user?s manual u17854ej6v0ud 663 internal oscillator characteristics (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, v ss = ev ss = av ss = 0 v) oscillators parameters conditions min. typ. max. unit 2.7 v v dd 5.5 v 7.6 8.0 8.4 mhz 8 mhz internal oscillator internal high- speed oscillation clock frequency (f ih ) note 1 1.8 v v dd < 2.7 v 5.0 8.0 8.4 mhz 2.7 v v dd 5.5 v 216 240 264 khz normal current mode 1.8 v v dd < 2.7 v 192 240 264 khz 240 khz internal oscillator internal low-speed oscillation clock frequency (f il ) low consumption current mode note 2 192 240 264 khz notes 1. this only indicates the oscillator characteristi cs of when hiotrm is set to 10h. refer to ac characteristics for instruction execution time. 2. regulator output is set to low consumption current mode in the following cases: ? when the rmc register is set to 5ah. ? during system reset ? in stop mode (except during ocd mode) ? when both the high-speed system clock (f mx ) and the high-speed internal oscillation clock (f ih ) are stopped during cpu operation wit h the subsystem clock (f xt ) ? when both the high-speed system clock (f mx ) and the high-speed internal oscillation clock (f ih ) are stopped during the halt mode when the cp u operation with the subsystem clock (f xt ) has been set. remark for details on the normal current mode and low cons umption current mode according to the regulator output voltage, refer to chapter 21 regulator . chapter 27 electrical specifications user?s manual u17854ej6v0ud 664 xt1 oscillator characteristics (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, v ss = ev ss = av ss = 0 v) resonator recommended circuit items conditions min. typ. max. unit crystal resonator xt1 xt2 c4 c3 rd v ss xt1 clock oscillation frequency (f xt ) note 32 32.768 35 khz note indicates only oscillator characteri stics. refer to ac characterist ics for instruction execution time. cautions 1. when using the xt1 oscillator, wire as follo ws in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. ? do not route the wiring near a signal line th rough which a high fluctuating current flows. ? always make the ground point of the o scillator capacitor the same potential as v ss . ? do not ground the capacitor to a ground pattern through which a high current flows. ? do not fetch signals from the oscillator. 2. the xt1 oscillator is desi gned as a low-amplitude circuit for reducing power consumption, and is more prone to malfunction due to noi se than the x1 oscillato r. particular care is therefore required with the wiring meth od when the xt1 clock is used. remark for the resonator selection and oscillator constan t, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. chapter 27 electrical specifications user?s manual u17854ej6v0ud 665 dc characteristics (1/10) (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, 1.8 v av ref v dd , v ss = ev ss = av ss = 0 v) items symbol conditions min. typ. max. unit 4.0 v v dd 5.5 v ? 3.0 ma 2.7 v v dd < 4.0 v ? 1.0 ma per pin for p00 to p06, p10 to p17, p30, p31, p40 to p43, p50 to p55, p70 to p77, p120, p130, p140, p141 1.8 v v dd < 2.7 v ? 1.0 ma 4.0 v v dd 5.5 v ? 20.0 ma 2.7 v v dd < 4.0 v ? 10.0 ma total of p00 to p04, p40 to p43, p120, p130, p140, p141 (when duty = 70% note 2 ) 1.8 v v dd < 2.7 v ? 5.0 ma 4.0 v v dd 5.5 v ? 30.0 ma 2.7 v v dd < 4.0 v ? 19.0 ma total of p05, p06, p10 to p17, p30, p31, p50 to p55, p70 to p77 (when duty = 70% note 2 ) 1.8 v v dd < 2.7 v ? 10.0 ma 4.0 v v dd 5.5 v ? 50.0 ma 2.7 v v dd < 4.0 v ? 29.0 ma i oh1 total of all pins (when duty = 60% note 2 ) 1.8 v v dd < 2.7 v ? 15.0 ma output current, high note 1 i oh2 per pin for p20 to p27 av ref v dd ? 0.1 ma notes 1. value of current at which t he device operation is guaranteed even if the current flows from ev dd pin to an output pin. 2. specification under conditions where the duty factor is 60% or 70%. the output current value that has changed t he duty ratio can be calculated with the following expression (when changing the duty factor from 70% to n%). ? total output current of pins = (i oh 0.7)/(n 0.01) chapter 27 electrical specifications user?s manual u17854ej6v0ud 666 dc characteristics (2/10) (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, 1.8 v av ref v dd , v ss = ev ss = av ss = 0 v) items symbol conditions min. typ. max. unit 4.0 v v dd 5.5 v 8.5 ma 2.7 v v dd < 4.0 v 1.0 ma per pin for p00 to p06, p10 to p17, p30, p31, p40 to p43, p50 to p55, p70 to p77, p120, p130, p140, p141 1.8 v v dd < 2.7 v 0.5 ma 4.0 v v dd 5.5 v 15.0 ma 2.7 v v dd < 4.0 v 3.0 ma per pin for p60 to p63 1.8 v v dd < 2.7 v 2.0 ma 4.0 v v dd 5.5 v 20.0 ma 2.7 v v dd < 4.0 v 15.0 ma total of p00 to p04, p40 to p43, p120, p130, p140, p141 (when duty = 70% note 2 ) 1.8 v v dd < 2.7 v 9.0 ma 4.0 v v dd 5.5 v 45.0 ma 2.7 v v dd < 4.0 v 35.0 ma total of p05, p06, p10 to p17, p30, p31, p50 to p55, p60 to p63, p70 to p77 (when duty = 70% note 2 ) 1.8 v v dd < 2.7 v 20.0 ma 4.0 v v dd 5.5 v 65.0 ma 2.7 v v dd < 4.0 v 50.0 ma i ol1 total of all pins (when duty = 60% note 2 ) 1.8 v v dd < 2.7 v 29.0 ma output current, low note 1 i ol2 per pin for p20 to p27 av ref v dd 0.4 ma notes 1 . value of current at which the device operation is guaranteed even if the cu rrent flows from an output pin to ev ss , v ss , and av ss pin. 2. specification under conditions where the duty factor is 60% or 70%. the output current value that has changed t he duty ratio can be calculated with the following expression (when changing the duty factor from 70% to n%). ? total output current of pins = (i ol 0.7)/(n 0.01) chapter 27 electrical specifications user?s manual u17854ej6v0ud 667 dc characteristics (3/10) (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, 1.8 v av ref v dd , v ss = ev ss = av ss = 0 v) items symbol conditions min. typ. max. unit v ih1 p01, p02, p12, p13, p15, p41, p52 to p55, p121 to p124 0.7v dd v dd v v ih2 p00, p03 to p06, p10, p11, p14, p16, p17, p30, p31, p40, p42, p43, p50, p51, p70 to p77, p120, p140, p141, exclk, reset normal input buffer 0.8v dd v dd v ttl input buffer 4.0 v v dd 5.5 v 2.2 v dd v ttl input buffer 2.7 v v dd < 4.0 v 2.0 v dd v v ih3 p03, p04 ttl input buffer 1.8 v v dd < 2.7 v 1.6 v dd v 2.7 v av ref v dd v ih4 p20 to p27 av ref = v dd < 2.7 v 0.7av ref av ref v v ih5 p60 to p63 0.7v dd 6.0 v input voltage, high v ih6 flmd0 0.9v dd note 1 v dd v v il1 p01, p02, p12, p13, p15, p41, p52 to p55, p121 to p124 0 0.3v dd v v il2 p00, p03 to p06, p10, p11, p14, p16, p17, p30, p31, p40, p42, p43, p50, p51, p70 to p77, p120, p140, p141, exclk, reset normal input buffer 0 0.2v dd v ttl input buffer 4.0 v v dd 5.5 v 0 0.8 v ttl input buffer 2.7 v v dd < 4.0 v 0 0.5 v v il3 p03, p04 ttl input buffer 1.8 v v dd < 2.7 v 0 0.2 v 2.7 v av ref v dd v il4 p20 to p27 av ref = v dd < 2.7 v 0 0.3av ref v v il5 p60 to p63 0 0.3v dd v input voltage, low v il6 flmd0 note 2 0 0.1v dd v notes 1. the high-level input voltage (v ih6 ) must be greater than 0.9v dd when using it in the flash memory programming mode. 2. when disabling writing of the flash memory, c onnect the flmd0 pin processing directly to v ss , and maintain a voltage less than 0.1v dd . cautions 1. the maximum value of v ih of pins p02 to p04 is v dd , even in the n-ch open-drain mode. 2. for p122/exclk, the value of v ih and v il differs according to the input port mode or external clock mode. make sure to satisfy the dc characteristics of exclk in external clock input mode. remark unless specified otherwise, the charac teristics of alternate-function pi ns are the same as those of port pins. chapter 27 electrical specifications user?s manual u17854ej6v0ud 668 dc characteristics (4/10) (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, 1.8 v av ref v dd , v ss = ev ss = av ss = 0 v) items symbol conditions min. typ. max. unit 4.0 v v dd 5.5 v, i oh1 = ? 3.0 ma v dd ? 0.7 v v oh1 p00 to p06, p10 to p17, p30, p31, p40 to p43, p50 to p55, p70 to p77, p120, p130, p140, p141 1.8 v v dd 5.5 v, i oh1 = ? 1.0 ma v dd ? 0.5 v output voltage, high v oh2 p20 to p27 av ref v dd , i oh2 = ? 0.1 ma av ref ? 0.5 v 4.0 v v dd 5.5 v, i ol1 = 8.5 ma 0.7 v 2.7 v v dd 5.5 v, i ol1 = 1.0 ma 0.5 v v ol1 p00 to p06, p10 to p17, p30, p31, p40 to p43, p50 to p55, p70 to p77, p120, p130, p140, p141 1.8 v v dd 5.5 v, i ol1 = 0.5 ma 0.4 v v ol2 p20 to p27 av ref v dd , i ol2 = 0.4 ma 0.4 v 4.0 v v dd 5.5 v, i ol1 = 15.0 ma 2.0 v 4.0 v v dd 5.5 v, i ol1 = 5.0 ma 0.4 v 2.7 v v dd 5.5 v, i ol1 = 3.0 ma 0.4 v output voltage, low v ol3 p60 to p63 1.8 v v dd 5.5 v, i ol1 = 2.0 ma 0.4 v remark unless specified otherwise, the charac teristics of alternate-function pi ns are the same as those of port pins. chapter 27 electrical specifications user?s manual u17854ej6v0ud 669 dc characteristics (5/10) (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, 1.8 v av ref v dd , v ss = ev ss = av ss = 0 v) items symbol conditions min. typ. max. unit i lih1 p00 to p06, p10 to p17, p30, p31, p40 to p43, p50 to p55, p60 to p63, p70 to p77, p120, p140, p141, flmd0, reset v i = v dd 1 a v i = av ref , 2.7 v av ref v dd i lih2 p20 to p27 v i = av ref , av ref = v dd < 2.7 v 1 a in input port 1 a input leakage current, high i lih3 p121 to p124 (x1, x2, xt1, xt2) v i = v dd in resonator connection 10 a i lil1 p00 to p06, p10 to p17, p30, p31, p40 to p43, p50 to p55, p60 to p63, p70 to p77, p120, p140, p141, flmd0, reset v i = v ss ? 1 a v i = v ss , 2.7 v av ref v dd i lil2 p20 to p27 v i = v ss , av ref = v dd < 2.7 v ? 1 a in input port ? 1 a input leakage current, low i lil3 p121 to p124 (x1, x2, xt1, xt2) v i = v ss in resonator connection ? 10 a remark unless specified otherwise, the charac teristics of alternate-function pi ns are the same as those of port pins. chapter 27 electrical specifications user?s manual u17854ej6v0ud 670 dc characteristics (6/10) (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, 1.8 v av ref v dd , v ss = ev ss = av ss = 0 v) items symbol conditions min. typ. max. unit on-chip pll-up resistance r u p00 to p06, p10 to p17, p30, p31, p40 to p43, p50 to p55, p70 to p77, p120, p140, p141 v i = v ss , in input port 10 20 100 k flmd0 pin external pull-down resistance note r flmd0 when enabling the self-programming mode setting with software 100 k note it is recommended to leave the flmd0 pin open. if the pin is required to be pulled down externally, set r fldm0 to 100 k or more. 78k0r/ke3 flmd0 pin r flmd0 remark unless specified otherwise, the charac teristics of alternate-function pi ns are the same as those of port pins. chapter 27 electrical specifications user?s manual u17854ej6v0ud 671 dc characteristics (7/10) (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, 1.8 v av ref v dd , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit square wave input 8.2 12.2 ma f mx = 20 mhz note 2 , v dd = 5.0 v resonator connection 8.5 12.5 ma square wave input 8.2 12.2 ma f mx = 20 mhz note 2 , v dd = 3.0 v resonator connection 8.5 12.5 ma square wave input 3.9 6.2 ma f mx = 10 mhz notes 2, 3 , v dd = 5.0 v resonator connection 4.0 6.3 ma square wave input 3.9 6.2 ma f mx = 10 mhz notes 2, 3 , v dd = 3.0 v resonator connection 4.0 6.3 ma square wave input 2.1 3.0 ma normal current mode resonator connection 2.2 3.1 ma square wave input 1.5 2.1 ma f mx = 5 mhz notes 2, 3 , v dd = 3.0 v low consumption current mode note 4 resonator connection 1.5 2.1 ma square wave input 1.5 2.1 ma normal current mode resonator connection 1.5 2.1 ma square wave input 1.4 2.0 ma f mx = 5 mhz notes 2, 3 , v dd = 2.0 v low consumption current mode note 4 resonator connection 1.4 2.0 ma v dd = 5.0 v 3.5 5.0 ma f ih = 8 mhz note 5 v dd = 3.0 v 3.5 5.0 ma v dd = 5.0 v 8.0 24.0 a v dd = 3.0 v 8.0 24.0 a f sub = 32.768 khz note 6 , t a = ? 40 to +70 c v dd = 2.0 v 7.0 21.0 a v dd = 5.0 v 8.0 31.0 a v dd = 3.0 v 8.0 31.0 a supply current i dd1 note 1 operating mode f sub = 32.768 khz note 6 , t a = ? 40 to +85 c v dd = 2.0 v 7.0 28.0 a notes 1. total current flowing into v dd , ev dd , and av ref , including the input leakage current flowing when the level of the input pin is fixed to v dd or v ss . the values below the max. column include the peripheral operation current. however, not incl uding the current flowing in to the a/d converter, lvi circuit, i/o port, and on-chip pull-up/pull-down resistors. 2. when internal high-speed oscillator and subsystem clock are stopped. 3. when amph (bit 0 of clock operation mode control re gister (cmc)) = 0 and fsel (bit 0 of operation speed mode control register (osmc)) = 0. 4. when the rmc register is set to 5ah. 5. when high-speed system clock and subsystem clock are stopped. 6. when internal high-speed oscillator and high-speed system clock are stopped. when watchdog timer is stopped. remarks 1. f mx : high-speed system clock frequency (x1 clock oscill ation frequency or exte rnal main system clock frequency) 2. f ih : internal high-speed oscillation clock frequency 3. f sub : subsystem clock frequency (xt1 clock oscillation frequency) 4. for details on the normal current mode and low co nsumption current mode according to the regulator output voltage, refer to chapter 21 regulator . chapter 27 electrical specifications user?s manual u17854ej6v0ud 672 dc characteristics (8/10) (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, 1.8 v av ref v dd , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit square wave input 1.1 2.7 ma f mx = 20 mhz note 2 , v dd = 5.0 v resonator connection 1.4 3.0 ma square wave input 1.1 2.7 ma f mx = 20 mhz note 2 , v dd = 3.0 v resonator connection 1.4 3.0 ma square wave input 0.65 1.4 ma f mx = 10 mhz notes 2, 3 , v dd = 5.0 v resonator connection 0.75 1.5 ma square wave input 0.65 1.4 ma f mx = 10 mhz notes 2, 3 , v dd = 3.0 v resonator connection 0.75 1.5 ma square wave input 0.39 0.75 ma normal current mode resonator connection 0.44 0.8 ma square wave input 0.3 0.5 ma f mx = 5 mhz notes 2, 3 , v dd = 3.0 v low consumption current mode note 4 resonator connection 0.35 0.55 ma square wave input 0.3 0.5 ma normal current mode resonator connection 0.35 0.55 ma square wave input 0.3 0.5 ma f mx = 5 mhz notes 2, 3 , v dd = 2.0 v low consumption current mode note 4 resonator connection 0.35 0.55 ma v dd = 5.0 v 0.45 0.6 ma supply current i dd2 note 1 halt mode f ih = 8 mhz note 5 v dd = 3.0 v 0.45 0.6 ma notes 1. total current flowing into v dd , ev dd , and av ref , including the input leakage current flowing when the level of the input pin is fixed to v dd or v ss . the maximum value include the peripheral operation current. however, not including t he current flowing into t he a/d converter, lvi circuit, i/o port, and on-chip pull- up/pull-down resistors. during halt instruction execution by flash memory. 2. when internal high-speed oscillator and subsystem clock are stopped. 3. when amph (bit 0 of clock operation mode control re gister (cmc)) = 0 and fsel (bit 0 of operation speed mode control register (osmc)) = 0. 4. when the rmc register is set to 5ah. 5. when high-speed system clock and subsystem clock are stopped. remarks 1. f mx : high-speed system clock frequency (x1 clock oscill ation frequency or exte rnal main system clock frequency) 2. f ih : internal high-speed oscillation clock frequency 3. for details on the normal current mode and low co nsumption current mode according to the regulator output voltage, refer to chapter 21 regulator . chapter 27 electrical specifications user?s manual u17854ej6v0ud 673 dc characteristics (9/10) (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, 1.8 v av ref v dd , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit v dd = 5.0 v 2.2 14.0 a v dd = 3.0 v 2.2 14.0 a f sub = 32.768 khz note 2 , t a = ? 40 to +70 c v dd = 2.0 v 2.1 13.8 a v dd = 5.0 v 2.2 21.0 a v dd = 3.0 v 2.2 21.0 a i dd2 note 1 halt mode f sub = 32.768 khz note 2 , t a = ? 40 to +85 c v dd = 2.0 v 2.1 20.8 a t a = ? 40 to +70 c 1.1 9.0 a supply current i dd3 note 3 stop mode t a = ? 40 to +85 c 1.1 16.0 a notes 1. total current flowing into v dd , ev dd , and av ref , including the input leakage current flowing when the level of the input pin is fixed to v dd or v ss . the maximum value include the peripheral operation current. however, not including t he current flowing into t he a/d converter, lvi circuit, i/o port, and on-chip pull- up/pull-down resistors. during halt instruction execution by flash memory. 2. when internal high-speed oscillator and high-speed system clock are stopped. when watchdog timer is stopped. 3. total current flowing into v dd , ev dd , and av ref , including the input leakage current flowing when the level of the input pin is fixed to v dd or v ss . when subsystem clock is stopped. when watchdog timer is stopped. remark f sub : subsystem clock frequency (xt1 clock oscillation frequency) chapter 27 electrical specifications user?s manual u17854ej6v0ud 674 dc characteristics (10/10) (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, 1.8 v av ref v dd , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit v dd = 3.0 v 0.2 1.0 rtc operating current i rtc notes 1, 2 f sub = 32.768 khz v dd = 2.0 v 0.2 1.0 a watchdog timer operating current i wdt notes 2, 3 f il = 240 khz 5 10 a a/d converter operating current i adc note 4 during conversion at maximum speed, 2.3 v av ref 0.86 1.9 ma lvi operating current i lvi note 5 9 18 a notes 1. current flowing only to the real-time counter (excludi ng the operating current of the xt1 oscillator). the current value of the 78k0r/ke3 is the typ. val ue, the sum of the typ. values of either i dd1 or i dd2 , and i rtc , when the real-time counter operates in operation mode or halt mode. the i dd1 and i dd2 max. values also include the real-time counter operating current. 2. when internal high-speed oscillator and high-speed system clock are stopped. 3. current flowing only to the watchdog timer (including the operating current of the 240 khz internal oscillator). the current value of the 78k 0r/ke3 is the sum of i dd1 , i dd2 or i dd3 and i wdt when f clk = f sub /2 or when the watchdog timer operates in stop mode. 4. current flowing only to the a/d converter (av ref pin). the current value of the 78k0r/ke3 is the sum of i dd1 or i dd2 and i adc when the a/d converter operates in an operation mode or the halt mode. 5. current flowing only to the lvi circuit. the cu rrent value of the 78k0r/ke3 is the sum of i dd1 , i dd2 or i dd3 and i lvi when the lvi circuit operates in t he operating, halt or stop mode. remarks 1. f il : internal low-speed oscillation clock frequency 2. f sub : subsystem clock frequency (xt1 clock oscillation frequency) 3. f clk : cpu/peripheral hardware clock frequency chapter 27 electrical specifications user?s manual u17854ej6v0ud 675 ac characteristics (1) basic operation (1/6) (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, 1.8 v av ref v dd , v ss = ev ss = av ss = 0 v) items symbol conditions min. typ. max. unit 2.7 v v dd 5.5 v 0.05 8 s normal current mode 1.8 v v dd < 2.7 v 0.2 8 s main system clock (f xp ) operation low consumption current mode 0.2 8 s subsystem clock (f sub ) operation 57.2 61 62.5 s instruction cycle (minimum instruction execution time) t cy in the self programming mode normal current mode 2.7 v v dd 5.5 v 0.05 0.5 s 2.7 v v dd 5.5 v 2.0 20.0 mhz external main system clock frequency f ex 1.8 v v dd < 2.7 v 2.0 5.0 mhz 2.7 v v dd 5.5 v 24 ns external main system clock input high-level width, low-level width t exh , t exl 1.8 v v dd < 2.7 v 96 ns ti00 to ti06 input high-level width, low-level width t tih , t til 1/f mck + 10 ns 2.7 v v dd 5.5 v 10 mhz to00 to to06 output frequency f to 1.8 v v dd < 2.7 v 5 mhz 2.7 v v dd 5.5 v 10 mhz pclbuz0, pclbuz1 output frequency f pcl 1.8 v v dd < 2.7 v 5 mhz interrupt input high-level width, low-level width t inth , t intl 1 s key interrupt input low-level width t kr 250 ns reset low-level width t rsl 10 s remarks 1. f mck : timer array unit operation clock frequency (operation clock to be set by the cks0n bit of the tm r0n register. n: channel number (n = 0 to 6)) 2. for details on the normal current mode and low consumption current mode according to the regulator output voltage, refer to chapter 21 regulator . chapter 27 electrical specifications user?s manual u17854ej6v0ud 676 (1) basic operation (2/6) minimum instruction execution time during main system clock operation (fsel = 0, rmc = 00h) 8.0 1.0 0.2 0.1 0 10 1.0 2.0 3.0 4.0 5.0 6.0 5.5 2.7 0.01 1.8 guaranteed range of main system clock operation (fsel = 0, rmc = 00h) 2.1 the range enclosed in dotted lines applies when the internal high-speed oscillator is selected. supply voltage v dd [v] cycle time t cy [ s] remark fsel: bit 0 of the operation sp eed mode control register (osmc) chapter 27 electrical specifications user?s manual u17854ej6v0ud 677 (1) basic operation (3/6) minimum instruction execution time during main system clock operation (fsel = 1, rmc = 00h) 8.0 1.0 0.2 0.1 0.05 0 10 1.0 2.0 3.0 4.0 5.0 6.0 5.5 2.7 0.01 1.8 guaranteed range of main system clock operation (fsel = 1, rmc = 00h) the range enclosed in dotted lines applies when the internal high-speed oscillator is selected. supply voltage v dd [v] cycle time t cy [ s] caution the following operations are prohibited when v dd is less than 2.25 v. ? operation rewriting fsel from 0 to 1 ? releasing stop mode during f ex operation and f ih operation, when fsel is set to 1 (this must not be performed even if the fre quency is divided. the stop mode may be released during f x operation.) ? operation to switch f clk from f sub to f main , while fsel = 1 (this must not be performed even if the frequency is divided.) remarks 1. fsel: bit 0 of the operation sp eed mode control register (osmc) 2. f x : x1 clock oscillation frequency f ih : internal high-speed oscillation clock frequency f ex : external main system clock frequency f main : main system clock frequency f sub : subsystem clock frequency f clk : cpu/peripheral hardware clock frequency chapter 27 electrical specifications user?s manual u17854ej6v0ud 678 (1) basic operation (4/6) minimum instruction execution time during main sy stem clock operation (fsel = 0, rmc = 5ah) 8.0 1.0 0.2 0.1 0.05 0 10 1.0 2.0 3.0 4.0 5.0 6.0 5.5 0.01 1.8 supply voltage v dd [v] cycle time t cy [ s] guaranteed range of main system clock operation (fsel = 0, rmc = 5ah) the range enclosed in dotted lines applies when the internal high-speed oscillator is selected. remarks 1. fsel: bit 0 of the operation sp eed mode control register (osmc) 2. the entire voltage range is 5 mhz (max.) when rmc is set to 5ah. chapter 27 electrical specifications user?s manual u17854ej6v0ud 679 (1) basic operation (5/6) minimum instruction execution time duri ng self programming mode (rmc = 00h) 8.0 1.0 0.5 0.1 0.05 0 10 1.0 2.0 3.0 4.0 5.0 6.0 5.5 0.01 2.7 cycle time t cy [ s] supply voltage v dd [v] guaranteed range of self programming mode (rmc = 00h) the range enclosed in dotted lines applies when the internal high-speed oscillator is selected. remarks 1. fsel: bit 0 of the operation sp eed mode control register (osmc) 2. the self programming function cannot be used wh en rmc is set to 5ah or the cpu operates with the subsystem clock. chapter 27 electrical specifications user?s manual u17854ej6v0ud 680 (1) basic operation (6/6) ac timing test points v ih v il test points v ih v il external main system clock timing exclk 0.8v dd (min.) 0.2v dd (max.) 1/f ex t exl t exh ti timing ti00 to ti06 t til t tih interrupt request input timing intp0 to intp11 t intil t inth key interrupt input timing kr0 to kr7 t kr reset input timing reset t rsl chapter 27 electrical specifications user?s manual u17854ej6v0ud 681 (2) serial interface: se rial array unit (1/17) (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, v ss = ev ss = av ss = 0 v) (a) during communication at same potential (uart mode) (dedicat ed baud rate ge nerator output) parameter symbol conditions min. typ. max. unit f mck /6 bps transfer rate f clk = 20 mhz, f mck = f clk 3.3 mbps uart mode connection diagram (duri ng communication at same potential) 78k0r/ke3 user's device txdq rxdq rx tx uart mode bit width (dur ing communication at same potential) (reference) baud rate error tolerance high-/low-bit width 1/transfer rate txdq rxdq caution when using uart1, select the normal input bu ffer for rxd1 and the normal output mode for txd1 by using the pim0 and pom0 registers. remarks 1. q: uart number (q = 0, 1, 3) 2. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of t he smrmn register. m: un it number (m = 0, 1), n: channel number (n = 0 to 3)) chapter 27 electrical specifications user?s manual u17854ej6v0ud 682 (2) serial interface: se rial array unit (2/17) (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, v ss = ev ss = av ss = 0 v) (b) during communication at same pot ential (csi mode) (master mode, sckp... internal clock output) parameter symbol conditions min. typ. max. unit 4.0 v v dd 5.5 v 200 ns 2.7 v v dd < 4.0 v 400 ns sckp cycle time t kcy1 1.8 v v dd < 2.7 v 800 ns 4.0 v v dd 5.5 v t kcy1 /2 ? 20 ns 2.7 v v dd < 4.0 v t kcy1 /2 ? 35 ns sckp high-/low-level width t kh1 , t kl1 1.8 v v dd < 2.7 v t kcy1 /2 ? 80 ns 4.0 v v dd 5.5 v 70 ns 2.7 v v dd < 4.0 v 100 ns sip setup time (to sckp ) note 1 t sik1 1.8 v v dd < 2.7 v 190 ns sip hold time (from sckp ) note 2 t ksi1 30 ns delay time from sckp to sop output note 3 t kso1 c = 50 pf note 4 40 ns notes 1. when dap0n = 0 and ckp0n = 0, or dap0n = 1 and ckp0n = 1. the sip setup time becomes ?to sckp ? when dap0n = 0 and ckp0n = 1, or dap0n = 1 and ckp0n = 0. 2. when dap0n = 0 and ckp0n = 0, or dap0n = 1 and ckp0n = 1. the sip hold time becomes ?from sckp ? when dap0n = 0 and ckp0n = 1, or dap0n = 1 and ckp0n = 0. 3. when dap0n = 0 and ckp0n = 0, or dap0n = 1 and ck p0n = 1. the delay time to sop output becomes ?from sckp ? when dap0n = 0 and ckp0n = 1, or dap0n = 1 and ckp0n = 0. 4. c is the load capacitance of the sckp and sop output lines. caution when using csi10, select the normal input bu ffer for si10 and the normal output mode for so10 and sck10 by using the pim0 and pom0 registers. remark p: csi number (p = 00, 10), n: channel number (n = 0, 2) chapter 27 electrical specifications user?s manual u17854ej6v0ud 683 (2) serial interface: se rial array unit (3/17) (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, v ss = ev ss = av ss = 0 v) (c) during communication at same potential (csi mode) (slave m ode, sckp... external clock input) parameter symbol conditions min. typ. max. unit 16 mhz < f mck 8/f mck ns sckp cycle time t kcy2 f mck 16 mhz 6/f mck ns sckp high-/low-level width t kh2 , t kl2 f kcy2 /2 ns sip setup time (to sckp ) note 1 t sik2 1/f mck +80 ns sip hold time (from sckp ) note 2 t ksi2 50 ns 4.0 v v dd 5.5 v 1/f mck + 120 ns 2.7 v v dd < 4.0 v 1/f mck + 120 ns delay time from sckp to sop output note 3 t kso2 c = 50 pf note 4 1.8 v v dd < 2.7 v 1/f mck + 180 ns notes 1. when dap0n = 0 and ckp0n = 0, or dap0n = 1 and ckp0n = 1. the sip setup time becomes ?to sckp ? when dap0n = 0 and ckp0n = 1, or dap0n = 1 and ckp0n = 0. 2. when dap0n = 0 and ckp0n = 0, or dap0n = 1 and ckp0n = 1. the sip hold time becomes ?from sckp ? when dap0n = 0 and ckp0n = 1, or dap0n = 1 and ckp0n = 0. 3. when dap0n = 0 and ckp0n = 0, or dap0n = 1 and ck p0n = 1. the delay time to sop output becomes ?from sckp ? when dap0n = 0 and ckp0n = 1, or dap0n = 1 and ckp0n = 0. 4. c is the load capacitance of the sckp and sop output lines. caution when using csi10, select the normal input buffer for si10 and sck10 and the normal output mode for so10 by using the pim0 and pom0 registers. remarks 1. p: csi number (p = 00, 10) 2. f mck : serial array unit operation clock frequency (operation clock to be set by the cks0n bit of the smr0n register. n: channel number (n = 0, 2)) chapter 27 electrical specifications user?s manual u17854ej6v0ud 684 (2) serial interface: se rial array unit (4/17) csi mode connection diagram (duri ng communication at same potential) 78k0r/ke3 user's device sckp sop sck si sip so csi mode serial transfer timing (during communication at same potential) (when dap0n = 0 and ckp0n = 0, or dap0n = 1 and ckp0n = 1.) sip input data output data sop t kcy1, 2 t kl1, 2 t kh1, 2 t sik1, 2 t ksi1, 2 t kso1, 2 sckp csi mode serial transfer timing (during communication at same potential) (when dap0n = 0 and ckp0n = 1, or dap0n = 1 and ckp0n = 0.) sip input data output data sop t kcy1, 2 t kh1, 2 t kl1, 2 t sik1, 2 t ksi1, 2 t kso1, 2 sckp remarks 1. p: csi number (p = 00, 10) 2. n: channel number (n = 0, 2) chapter 27 electrical specifications user?s manual u17854ej6v0ud 685 (2) serial interface: se rial array unit (5/17) (t a = ? 40 to +85 c, 2.7 v v dd = ev dd 5.5 v, v ss = ev ss = av ss = 0 v) (d) during communication at same potentia (simplified i 2 c mode) parameter symbol conditions min. max. unit scl10 clock frequency f scl 2.7 v v dd 5.5 v, c b = 100 pf, r b = 3 k 400 khz hold time when scl10 = ?l? t low 2.7 v v dd 5.5 v, c b = 100 pf, r b = 3 k 995 ns hold time when scl10 = ?h? t high 2.7 v v dd 5.5 v, c b = 100 pf, r b = 3 k 995 ns data setup time (reception) t su:dat 2.7 v v dd 5.5 v, c b = 100 pf, r b = 3 k 1/f mck + 120 ns data hold time (transmission) t hd:dat 2.7 v v dd 5.5 v, c b = 100 pf, r b = 3 k 0 160 ns simplified i 2 c mode mode connection diagram (dur ing communication at same potential) 78k0r/ke3 user's device sda10 scl10 sda scl v dd r b simplified i 2 c mode serial transfer timing (dur ing communication at same potential) sda10 t low t high t hd:dat scl10 t su:dat caution select the normal input buff er and the n-ch open drain output (v dd tolerance) mode for sda10 and the normal output mode for scl10 by using the pim0 and pom0 registers. remarks 1. r b [ ]:communication line (sda10) pull-up resistance, c b [f]: communication line (scl10, sda10) load capacitance 2. f mck : serial array unit operation clock frequency (operation clock to be set by the c ks02 bit of the smr02 register.) chapter 27 electrical specifications user?s manual u17854ej6v0ud 686 (2) serial interface: se rial array unit (6/17) (t a = ? 40 to +85 c, 2.7 v v dd = ev dd 5.5 v, v ss = ev ss = av ss = 0 v) (e) communication at different potential (2.5 v, 3 v) ( uart mode) (dedicated baud rate generator output) (1/2) parameter symbol conditions min. typ. max. unit f mck /6 bps 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v f clk = 20 mhz, f mck = f clk 3.3 mbps f mck /6 bps transfer rate reception 2.7 v v dd 4.0 v, 2.3 v v b 2.7 v f clk = 20 mhz, f mck = f clk 3.3 mbps caution select the ttl input buffer for rxd1 and the n-ch open drain output (v dd tolerance) mode for txd1 by using the pim0 and pom0 registers. remarks 1. f mck : serial array unit operation clock frequency (operation clock to be set by the cks0n bit of the smr0n register. n: channel number (n = 2, 3)) 2. v ih and v il below are observation points for the ac char acteristics of the serial array unit when communicating at different potentials in uart mode. 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v: v ih = 2.2 v, v il = 0.8 v 2.7 v v dd 4.0 v, 2.3 v v b 2.7 v: v ih = 2.0 v, v il = 0.5 v 3. uart0 and uart3 cannot communicate at differ ent potential. use uart1 for communication at different potential. chapter 27 electrical specifications user?s manual u17854ej6v0ud 687 (2) serial interface: se rial array unit (7/17) (t a = ? 40 to +85 c, 2.7 v v dd = ev dd 5.5 v, v ss = ev ss = av ss = 0 v) (e) communication at different potential (2.5 v, 3 v) ( uart mode) (dedicated baud rate generator output) (2/2) parameter symbol conditions min. typ. max. unit note 1 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v f clk = 16.8 mhz, f mck = f clk , c b = 50 pf, r b = 1.4 k , v b = 2.7 v 2.8 note 2 mbps note 3 transfer rate transmission 2.7 v v dd 4.0 v, 2.3 v v b 2.7 v f clk = 19.2 mhz, f mck = f clk , c b = 50 pf, r b = 2.7 k , v b = 2.3 v 1.2 note 4 mbps notes 1. the smaller maximum transfer rate derived by using f mck /6 or the following expression is the valid maximum transfer rate. expression for calculating the transfer rate when 4.0 v v dd = ev dd 5.5 v and 2.7 v v b 4.0 v 1 maximum transfer rate = 2.2 { ? c b r b ln (1 ? v b )} 3 [bps] 1 2.2 transfer rate 2 ? { ? c b r b ln (1 ? v b )} baud rate error (theoretical value) = 1 100 [%] ( transfer rate ) number of transferred bits * this value is the theoretical va lue of the relative difference between the transmission and reception sides. 2. this value as an example is calculated when the cond itions described in the ?conditions? column are met. refer to note 1 above to calculate the maximum tr ansfer rate under conditions of the customer. 3. the smaller maximum transfer rate derived by using f mck /6 or the following expression is the valid maximum transfer rate. expression for calculating the transfer rate when 2.7 v v dd = ev dd 4.0 v and 2.3 v v b 2.7 v 1 maximum transfer rate = 2.0 { ? c b r b ln (1 ? v b )} 3 [bps] 1 2.0 transfer rate 2 ? { ? c b r b ln (1 ? v b )} baud rate error (theoretical value) = 1 100 [%] ( transfer rate ) number of transferred bits * this value is the theoretical va lue of the relative difference between the transmission and reception sides. 4. this value as an example is calculated when the cond itions described in the ?conditions? column are met. refer to note 3 above to calculate the maximum tr ansfer rate under conditions of the customer. caution select the ttl input buffer for rxd1 and the n-ch open drain output (v dd tolerance) mode for txd1 by using the pim0 and pom0 registers. (remark are given on the next page.) chapter 27 electrical specifications user?s manual u17854ej6v0ud 688 (2) serial interface: se rial array unit (8/17) remarks 1. r b [ ]:communication line (txd1) pull-up resistance, c b [f]: communication line (txd1) load capacitance, v b [v]: communication line voltage 2. f mck : serial array unit operation clock frequency (operation clock to be set by the cks0n bit of the smr0n register. n: channel number (n = 2, 3)) 3. v ih and v il below are observation points for the ac char acteristics of the serial array unit when communicating at different potentials in uart mode. 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v: v ih = 2.2 v, v il = 0.8 v 2.7 v v dd 4.0 v, 2.3 v v b 2.7 v: v ih = 2.0 v, v il = 0.5 v 4. uart0 and uart3 cannot communicate at differ ent potential. use uart1 for communication at different potential. chapter 27 electrical specifications user?s manual u17854ej6v0ud 689 (2) serial interface: se rial array unit (9/17) uart mode connection diagram (communication at different potential) 78k0r/ke3 user's device txd1 rxd1 rx tx v b r b uart mode bit width (communication at different potential) (reference) txd1 rxd1 baud rate error tolerance baud rate error tolerance low-bit width high-/low-bit width high-bit width 1/transfer rate 1/transfer rate caution select the ttl input buffer for rxd1 and the n-ch open drain output (v dd tolerance) mode for txd1 by using the pim0 and pom0 registers. remarks 1. r b [ ]:communication line (txd1) pull-up resistance, v b [v]: communication line voltage 2. uart0 and uart3 cannot communicate at differ ent potential. use uart1 for communication at different potential. chapter 27 electrical specifications user?s manual u17854ej6v0ud 690 (2) serial interface: se rial array unit (10/17) (t a = ? 40 to +85 c, 2.7 v v dd = ev dd 5.5 v, v ss = ev ss = av ss = 0 v) (f) communication at different potential (2.5 v, 3 v) (csi mode) (master mode , sck10... internal clock output) (1/2) parameter symbol conditions min. typ. max. unit 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 50 pf, r b = 1.4 k 500 ns sck10 cycle time t kcy1 2.7 v v dd 4.0 v, 2.3 v v b < 2.7 v, c b = 50 pf, r b = 2.7 k 1000 ns 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 50 pf, r b = 1.4 k t kcy1 /2 ? 120 ns sck10 high-level width t kh1 2.7 v v dd 4.0 v, 2.3 v v b < 2.7 v, c b = 50 pf, r b = 2.7 k t kcy1 /2 ? 275 ns 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 50 pf, r b = 1.4 k t kcy1 /2 ? 20 ns sck10 low-level width t kl1 2.7 v v dd 4.0 v, 2.3 v v b < 2.7 v, c b = 50 pf, r b = 2.7 k t kcy1 /2 ? 35 ns 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 50 pf, r b = 1.4 k 195 ns si10 setup time (to sck10 ) note t sik1 2.7 v v dd 4.0 v, 2.3 v v b < 2.7 v, c b = 50 pf, r b = 2.7 k 380 ns 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 50 pf, r b = 1.4 k 30 ns si10 hold time (from sck10 ) note t ksi1 2.7 v v dd 4.0 v, 2.3 v v b < 2.7 v, c b = 50 pf, r b = 2.7 k 30 ns 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 50 pf, r b = 1.4 k 165 ns delay time from sck10 to so10 output note t kso1 2.7 v v dd 4.0 v, 2.3 v v b < 2.7 v, c b = 50 pf, r b = 2.7 k 320 ns note when dap02 = 0 and ckp02 = 0, or dap02 = 1 and ckp02 = 1. caution select the ttl input buffer for si10 and the n-ch open drain output (v dd tolerance) mode for so10 and sck10 by using the pim0 and pom0 registers. remarks 1. r b [ ]:communication line (sck10, so10) pull-up resistance, c b [f]: communication line (si10, so10, sck10) load capacitance, v b [v]: communication line voltage 2. v ih and v il below are observation points for the ac c haracteristics of the serial array unit when communicating at different potentials in csi mode. 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v: v ih = 2.2 v, v il = 0.8 v 2.7 v v dd 4.0 v, 2.3 v v b 2.7 v: v ih = 2.0 v, v il = 0.5 v 3. csi00 cannot communicate at different potential. use csi10 for communication at different potential. chapter 27 electrical specifications user?s manual u17854ej6v0ud 691 (2) serial interface: se rial array unit (11/17) (t a = ? 40 to +85 c, 2.7 v v dd = ev dd 5.5 v, v ss = ev ss = av ss = 0 v) (f) communication at different potential (2.5 v, 3 v) (csi mode) (master mode , sck10... internal clock output) (2/2) parameter symbol conditions min. typ. max. unit 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 50 pf, r b = 1.4 k 70 ns si10 setup time (to sck10 ) note t sik1 2.7 v v dd 4.0 v, 2.3 v v b < 2.7 v, c b = 50 pf, r b = 2.7 k 100 ns 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 50 pf, r b = 1.4 k 30 ns si10 hold time (from sck10 ) note t ksi1 2.7 v v dd 4.0 v, 2.3 v v b < 2.7 v, c b = 50 pf, r b = 2.7 k 30 ns 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 50 pf, r b = 1.4 k 40 ns delay time from sck10 to so10 output note t kso1 2.7 v v dd 4.0 v, 2.3 v v b < 2.7 v, c b = 50 pf, r b = 2.7 k 40 ns note when dap02 = 0 and ckp02 = 1, or dap02 = 1 and ckp02 = 0. csi mode connection diagram (communication at different potential) v b r b 78k0r/ke3 user's device chapter 27 electrical specifications user?s manual u17854ej6v0ud 692 (2) serial interface: se rial array unit (12/17) csi mode serial transfer timing (communication at different potential) (when dap02 = 0 and ckp02 = 0, or dap02 = 1 and ckp02 = 1.) si10 input data output data so10 t kcy1 t kl1 t kh1 t sik1 t ksi1 t kso1 sck10 csi mode serial transfer timing (communication at different potential) (when dap02 = 0 and ckp02 = 1, or dap02 = 1 and ckp02 = 0.) si10 input data output data so10 t kcy1 t kl1 t kh1 t sik1 t ksi1 t kso1 sck10 caution select the ttl input buffer for si10 and the n-ch open drain output (v dd tolerance) mode for so10 and sck10 by using the pim0 and pom0 registers. remark csi00 cannot communicate at different potential. use csi10 for communication at different potential. chapter 27 electrical specifications user?s manual u17854ej6v0ud 693 (2) serial interface: se rial array unit (13/17) (t a = ? 40 to +85 c, 2.7 v v dd = ev dd 5.5 v, v ss = ev ss = av ss = 0 v) (g) communication at different potential (2.5 v, 3 v) (csi mode) (slave mode, s ck10... external clock input) parameter symbol conditions min. typ. max. unit 16.6 mhz < f mck 12/f mck ns 12.5 mhz < f mck 16.6 mhz 10/f mck ns 8.3 mhz < f mck 12.5 mhz 8/f mck ns 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v f mck 8.3 mhz 6/f mck ns 17.5 mhz < f mck 18/f mck ns 15 mhz < f mck 17.5 mhz 16/f mck ns 12.5 mhz < f mck 15 mhz 14/f mck ns 10 mhz < f mck 12.5 mhz 12/f mck ns 7.5 mhz < f mck 10 mhz 10/f mck ns 5 mhz < f mck 7.5 mhz 8/f mck ns sck10 cycle time t kcy2 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v f mck 5 mhz 6/f mck ns 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v f kcy2 /2 ? 20 ns sck10 high-/low-level width t kh2 , t kl2 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v f kcy2 /2 ? 35 ns si10 setup time (to sck10 ) note 1 t sik2 1/f mck + 90 ns si10 hold time (from sck10 ) note 2 t ksi2 50 ns 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v c b = 50 pf, r b = 1.4 k 1/f mck + 245 ns delay time from sck10 to so10 output note 3 t kso2 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v c b = 50 pf, r b = 2.7 k 1/f mck + 400 ns notes 1. when dap02 = 0 and ckp02 = 0, or dap02 = 1 and ckp02 = 1. the si10 setup time becomes ?to sck10 ? when dap02 = 0 and ckp02 = 1, or dap02 = 1 and ckp02 = 0. 2. when dap02 = 0 and ckp02 = 0, or dap02 = 1 and ckp02 = 1. the si10 hold time becomes ?from sck10 ? when dap02 = 0 and ckp02 = 1, or dap02 = 1 and ckp02 = 0. 3. when dap02 = 0 and ckp02 = 0, or dap02 = 1 a nd ckp02 = 1. the delay time to so10 output becomes ?from sck10 ? when dap02 = 0 and ckp02 = 1, or dap02 = 1 and ckp02 = 0. csi mode connection diagram (communication at different potential) 78k0r/ke3 user's device chapter 27 electrical specifications user?s manual u17854ej6v0ud 694 (2) serial interface: se rial array unit (14/17) caution select the ttl input buffer for si10 and sck10 and the n-ch open drain output (v dd tolerance) mode for so10 by using the pim0 and pom0 registers. remarks 1. r b [ ]:communication line (so10) pull-up resistance, c b [f]: communication line (so10, sck10) load capacitance, v b [v]: communication line voltage 2. f mck : serial array unit operation clock frequency (operation clock to be set by the c ks02 bit of the smr02 register.) 3. v ih and v il below are observation points for the ac c haracteristics of the serial array unit when communicating at different potentials in csi mode. 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v: v ih = 2.2 v, v il = 0.8 v 2.7 v v dd 4.0 v, 2.3 v v b 2.7 v: v ih = 2.0 v, v il = 0.5 v 4. csi00 cannot communicate at different potential. use csi10 for communication at different potential. chapter 27 electrical specifications user?s manual u17854ej6v0ud 695 (2) serial interface: se rial array unit (15/17) csi mode serial transfer timing (communication at different potential) (when dap02 = 0 and ckp02 = 0, or dap02 = 1 and ckp02 = 1.) si10 input data output data so10 t kcy2 t kl2 t kh2 t sik2 t ksi2 t kso2 sck10 csi mode serial transfer timing (communication at different potential) (when dap02 = 0 and ckp02 = 1, or dap02 = 1 and ckp02 = 0.) si10 input data output data so10 t kcy2 t kl2 t kh2 t sik2 t ksi2 t kso2 sck10 caution select the ttl input buffer for si10 and sck10 and the n-ch open drain output (v dd tolerance) mode for so10 by using the pim0 and pom0 registers. remark csi00 cannot communicate at different potential. use csi10 for communication at different potential. chapter 27 electrical specifications user?s manual u17854ej6v0ud 696 (2) serial interface: se rial array unit (16/17) (t a = ? 40 to +85 c, 2.7 v v dd = ev dd 5.5 v, v ss = ev ss = av ss = 0 v) (h) communication at different potential (2.5 v, 3 v) (simplified i 2 c mode) parameter symbol conditions min. max. unit 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 100 pf, r b = 1.4 k 400 khz scl10 clock frequency f scl 2.7 v v dd 4.0 v, 2.3 v v b 2.7 v, c b = 100 pf, r b = 2.7 k 400 khz 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 100 pf, r b = 1.4 k 1065 ns hold time when scl10 = ?l? t low 2.7 v v dd 4.0 v, 2.3 v v b 2.7 v, c b = 100 pf, r b = 2.7 k 1065 ns 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 100 pf, r b = 1.4 k 445 ns hold time when scl10 = ?h? t high 2.7 v v dd 4.0 v, 2.3 v v b 2.7 v, c b = 100 pf, r b = 2.7 k 445 ns 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 100 pf, r b = 1.4 k 1/f mck +190 ns data setup time (reception) t su:dat 2.7 v v dd 4.0 v, 2.3 v v b 2.7 v, c b = 100 pf, r b = 2.7 k 1/f mck +190 ns 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 100 pf, r b = 1.4 k 0 160 ns data hold time (transmission) t hd:dat 2.7 v v dd 4.0 v, 2.3 v v b 2.7 v, c b = 100 pf, r b = 2.7 k 0 160 ns caution select the ttl input buffer and the n-ch open drain output (v dd tolerance) mode for sda10 and the n-ch open drain output (v dd tolerance) mode for scl10 by us ing the pim0 and pom0 registers. remarks 1. r b [ ]:communication line (sda10, scl10) pull-up resistance, c b [f]: communication line (sda10, scl10) load capacitance, v b [v]: communication line voltage 2. f mck : serial array unit operation clock frequency (operation clock to be set by the c ks02 bit of the smr02 register.) 3. v ih and v il below are observation points for the ac c haracteristics of the serial array unit when communicating at different potentials in simplified i 2 c mode mode. 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v: v ih = 2.2 v, v il = 0.8 v 2.7 v v dd 4.0 v, 2.3 v v b 2.7 v: v ih = 2.0 v, v il = 0.5 v chapter 27 electrical specifications user?s manual u17854ej6v0ud 697 (2) serial interface: se rial array unit (17/17) simplified i 2 c mode connection diagram (communication at different potential) 78k0r/ke3 user's device sda10 scl10 sda scl v b r b v b r b simplified i 2 c mode serial transfer timing (communication at different potential) sda10 t low t high t hd:dat scl10 t su:dat 1/f scl caution select the ttl input buffer and the n-ch open drain output (v dd tolerance) mode for sda10 and the n-ch open drain output (v dd tolerance) mode for scl10 by us ing the pim0 and pom0 registers. remark r b [ ]:communication line (sda10, scl10) pull-up resistance, v b [v]: communication line voltage chapter 27 electrical specifications user?s manual u17854ej6v0ud 698 (3) serial interface: iic0 (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, v ss = ev ss = av ss = 0 v) (a) iic0 standard mode high-speed mode parameter symbol conditions min. max. min. max. unit 6.7 mhz f clk 0 100 0 400 khz 4.0 mhz f clk < 6.7 mhz 0 100 0 340 khz 3.2 mhz f clk < 4.0 mhz 0 100 ? ? khz scl0 clock frequency f scl 2.0 mhz f clk < 3.2 mhz 0 85 ? ? khz setup time of restart condition note 1 t su:sta 4.7 0.6 s hold time t hd:sta 4.0 0.6 s hold time when scl0 = ?l? t low 4.7 1.3 s hold time when scl0 = ?h? t high 4.0 0.6 s data setup time (reception) t su:dat 250 100 ns 3.45 note 3 0.9 note 4 s cl00 = 1 and cl01 = 1 0 5.50 note 5 0 1.5 note 6 s 0.9 note 7 s cl00 = 0 and cl01 = 0, or cl00 = 1 and cl01 = 0 0 3.45 0 0.95 note 8 s data hold time (transmission) note 2 t hd:dat cl00 = 0 and cl01 = 1 0 3.45 0 0.9 s setup time of stop condition t su:sto 4.0 0.6 s bus-free time t buf 4.7 1.3 s notes 1. the first clock pulse is generated after this per iod when the start/restart condition is detected. 2. the maximum value (max.) of t hd:dat is during normal transfer and a wa it state is inserted in the ack (acknowledge) timing. 3. when 3.2 mhz f clk 4.19 mhz. 4. when 6.7 mhz f clk 8.38 mhz. 5. when 2.0 mhz f clk < 3.2 mhz. at this time, use the scl0 clock within 85 khz. 6. when 4.0 mhz f clk < 6.7 mhz. at this time, use the scl0 clock within 340 khz. 7. when 8.0 mhz f clk 16.76 mhz. 8. when 7.6 mhz f clk < 8.0 mhz. remark cl00, cl01, dfc0: bits 0, 1, and 2 of t he iic clock select register 0 (iiccl0) iic0 serial transfer timing t low t low t high t hd:sta stop condition start condition restart condition stop condition t su:dat t su:sta t su:sto t hd:sta t hd:dat scl0 sda0 chapter 27 electrical specifications user?s manual u17854ej6v0ud 699 (4) serial interface: on-chip debug (uart) (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, v ss = ev ss = av ss = 0 v) (a) on-chip debug (uart) parameter symbol conditions min. typ. max. unit f clk /2 12 f clk /6 bps transfer rate flash memory programming mode 2.66 mbps 2.7 v v dd 5.5 v 10 mhz tool1 output frequency f tool1 1.8 v v dd < 2.7 v 2.5 mhz chapter 27 electrical specifications user?s manual u17854ej6v0ud 700 a/d converter characteristics (t a = ? 40 to +85 c, 2.3 v v dd = ev dd 5.5 v, 2.3 v av ref v dd , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit resolution r es 10 bit 4.0 v av ref 5.5 v 0.4 %fsr 2.7 v av ref < 4.0 v 0.6 %fsr overall error notes 1, 2 ainl 2.3 v av ref < 2.7 v 1.2 %fsr 4.0 v av ref 5.5 v 6.1 66.6 s 2.7 v av ref < 4.0 v 12.2 66.6 s conversion time t conv 2.3 v av ref < 2.7 v 27 66.6 s 4.0 v av ref 5.5 v 0.4 %fsr 2.7 v av ref < 4.0 v 0.6 %fsr zero-scale error notes 1, 2 ezs 2.3 v av ref < 2.7 v 0.6 %fsr 4.0 v av ref 5.5 v 0.4 %fsr 2.7 v av ref < 4.0 v 0.6 %fsr full-scale error notes 1, 2 efs 2.3 v av ref < 2.7 v 0.6 %fsr 4.0 v av ref 5.5 v 2.5 lsb 2.7 v av ref < 4.0 v 4.5 lsb integral non-linearity error note 1 ile 2.3 v av ref < 2.7 v 6.5 lsb 4.0 v av ref 5.5 v 1.5 lsb 2.7 v av ref < 4.0 v 2.0 lsb differential non-linearity error note 1 dle 2.3 v av ref < 2.7 v 2.0 lsb analog input voltage v ain 2.3 v av ref 5.5 v av ss av ref v notes 1. excludes quantization error ( 1/2 lsb). 2. this value is indicated as a ratio (%fsr) to the full-scale value. chapter 27 electrical specifications user?s manual u17854ej6v0ud 701 poc circuit characteristics (t a = ? 40 to +85 c, v ss = 0 v) parameter symbol conditions min. typ. max. unit detection voltage v poc0 1.5 1.59 1.68 v power supply voltage rise inclination t pth change inclination of v dd : 0 v v poc0 0.5 v/ms minimum pulse width t pw when the voltage drops 200 s detection delay time 200 s poc circuit timing supply voltage (v dd ) time detection voltage (min.) detection voltage (typ.) detection voltage (max.) t pth t pw supply voltage rise time (t a = ? 40 to +85 c, v ss = 0 v) parameter symbol conditions min. typ. max. unit maximum time to rise to 1.8 v (v dd (min.)) note (v dd : 0 v 1.8 v) t pup1 lvi default start function stopped is set (lvioff (option byte) = 1), when reset input is not used 3.6 ms maximum time to rise to 1.8 v (v dd (min.)) note (releasing reset input v dd : 1.8 v) t pup2 lvi default start function stopped is set (lvioff (option byte) = 1), when reset input is used 1.88 ms note make sure to raise the power supply in a shorter time than this. supply voltage rise time timing ? when reset pin input is not used ? when reset pin input is used (when external reset is released by the reset pin, after poc has been released) 1.8 v 0 v poc i nternal signal t pup1 supply voltage (v dd ) time 1.8 v t pup2 0 v poc i nternal signal reset pin internal reset signal supply voltage (v dd ) time chapter 27 electrical specifications user?s manual u17854ej6v0ud 702 lvi circuit characteristics (t a = ? 40 to +85 c, v poc v dd = ev dd 5.5 v, v ss = ev ss =0 v) parameter symbol conditions min. typ. max. unit v lvi0 4.12 4.22 4.32 v v lvi1 3.97 4.07 4.17 v v lvi2 3.82 3.92 4.02 v v lvi3 3.66 3.76 3.86 v v lvi4 3.51 3.61 3.71 v v lvi5 3.35 3.45 3.55 v v lvi6 3.20 3.30 3.40 v v lvi7 3.05 3.15 3.25 v v lvi8 2.89 2.99 3.09 v v lvi9 2.74 2.84 2.94 v v lvi10 2.58 2.68 2.78 v v lvi11 2.43 2.53 2.63 v v lvi12 2.28 2.38 2.48 v v lvi13 2.12 2.22 2.32 v v lvi14 1.97 2.07 2.17 v supply voltage level v lvi15 1.81 1.91 2.01 v external input pin note 1 v exlvi exlvi < v dd , 1.8 v v dd 5.5 v 1.11 1.21 1.31 v detection voltage power supply voltage on power application v puplvi when lvi default start function enabled is set 1.87 2.07 2.27 v minimum pulse width t lw 200 s detection delay time 200 s operation stabilization wait time note 2 t lwait 10 s notes 1. the exlvi/p120/intp0 pin is used. 2. time required from setting bit 7 (lvion) of the lo w-voltage detection register (lvim) to 1 to operation stabilization remark v lvi(n ? 1) > v lvin : n = 1 to 15 lvi circuit timing supply voltage (v dd ) time detection voltage (min.) detection voltage (typ.) detection voltage (max.) t lw t lwait lvion 1 chapter 27 electrical specifications user?s manual u17854ej6v0ud 703 data memory stop mode low supply vo ltage data retention characteristics (t a = ? 40 to +85 c) parameter symbol conditions min. typ. max. unit data retention supply voltage v dddr 1.5 note 5.5 v note the value depends on the poc detecti on voltage. when the voltage drop s, the data is retained until a poc reset is effected, but data is not re tained when a poc reset is effected. v dd stop instruction execution standby release signal (interrupt request) stop mode data retention mode v dddr operation mode flash memory programming characteristics (t a = ? 40 to +85 c, 2.7 v v dd = ev dd 5.5 v, v ss = ev ss = 0 v) parameter symbol conditions min. typ. max. unit v dd supply current i dd typ. = 10 mhz, max. = 20 mhz 6 20 ma cpu/peripheral hardware clock frequency f clk 2 20 mhz number of rewrites per chip c erwr retention: 15 years 1 erase + 1 write after erase = 1 rewrite note 100 times note when a product is first written after shipment, ?erase write? and ?write only? are both taken as one rewrite. user?s manual u17854ej6v0ud 704 chapter 28 package drawings l c lp hd he zd ze l1 a1 a2 a d e 0.125 + 0.75 ? 0.25 (unit:mm) item dimensions d e hd he a a1 a2 a3 12.00 0.20 12.00 0.20 14.00 0.20 14.00 0.20 1.60 max. 0.10 0.05 1.40 0.05 0.25 c e x y zd ze 0.65 0.13 0.10 1.125 1.125 l lp l1 0.50 0.60 0.15 1.00 0.20 p64gk-65-gaj 3 + 5 ? 3 note each lead centerline is located within 0.13 mm of its true position at maximum material condition. detail of lead end 64-pin plastic lqfp (12x12) 0.30 + 0.08 ? 0.04 b 16 32 1 64 17 33 49 48 s y e s x b m a3 s chapter 28 package drawings user?s manual u17854ej6v0ud 705 s y e s x b m l c lp hd he zd ze l1 a1 a2 a d e a3 s 0.125 + 0.075 ? 0.025 (unit:mm) item dimensions d e hd he a a1 a2 a3 10.00 0.20 10.00 0.20 12.00 0.20 12.00 0.20 1.60 max. 0.10 0.05 1.40 0.05 0.25 c e x y zd ze 0.50 0.08 0.08 1.25 1.25 l lp l1 0.50 0.60 0.15 1.00 0.20 p64gb-50-gah 3 + 5 ? 3 note each lead centerline is located within 0.08 mm of its true position at maximum material condition. detail of lead end 0.20 b 16 32 1 64 17 33 49 48 64-pin plastic lqfp(fine pitch)(10x10) + 0.07 ? 0.03 chapter 28 package drawings user?s manual u17854ej6v0ud 706 s y e s x b m l c lp hd he zd ze l1 a1 a2 a d e a3 s note each lead centerline is located within 0.07mm of its true position at maximum material condition. detail of lead end 16 32 1 64 17 33 49 48 0.125 + 0.075 ? 0.025 (unit:mm) item dimensions d e hd he a a1 a2 a3 7.00 0.20 7.00 0.20 9.00 0.20 9.00 0.20 1.20 max. 0.10 0.05 1.00 0.05 0.25 c e x y zd ze 0.40 0.07 0.08 0.50 0.50 l lp l1 0.50 0.60 0.15 1.00 0.20 p64ga-40-hab 3 + 5 ? 3 0.16 b 64-pin plastic tqfp (fine pitch) (7x7) + 0.07 ? 0.03 chapter 28 package drawings user?s manual u17854ej6v0ud 707 64-pin plastic fbga (5x5) p64f1-50-an1 item dimensions d e w a a1 a2 e b x y y1 zd ze 5.00 0.10 5.00 0.10 0.50 0.20 0.21 0.05 0.32 0.05 0.90 0.10 0.69 (unit:mm) 0.05 0.08 0.20 0.75 0.75 s y1 s a a1 1 hgfedcba 2 3 4 5 6 7 8 a2 s y s e x bab m s wb s wa ze zd index mark b a d e user?s manual u17854ej6v0ud 708 appendix a development tools the following development t ools are available for the development of systems that employ the 78k0r/ke3. figure a-1 shows the developm ent tool configuration. ? support for pc98-nx series unless otherwise specified, pr oducts supported by ibm pc/at tm compatibles are compatible with pc98-nx series computers. when using pc98-nx series computer s, refer to the explanation for ibm pc/at compatibles. ? windows tm unless otherwise specified, ?windows? means the following oss. ? windows 98 ? windows nt tm ? windows 2000 ? windows xp appendix a development tools user?s manual u17854ej6v0ud 709 figure a-1. development tool configuration (1/2) (1) when using the in-circuit emulator qb-78k0rkx3 language processing software ? assembler package ? c compiler package ? device file note 1 debugging software ? integrated debugger note 3 ? system simulator host machine (pc or ews) qb-78k0rkx3 note 3 emulation probe target system flash memory programmer note 3 flash memory write adapter flash memory ? software package ? project manager software package flash memory write environment control software (windows only) note 2 power supply unit note 3 usb interface cable note 3 notes 1. download the device file for 78k0r/ke3 (df781188) from the download site for development tools (http://www.necel.com/micro/ods/eng/index.html). 2. the project manager pm+ is in cluded in the assembler package. the pm+ is only used for windows. 3. in-circuit emulator qb-78k0rkx3 is supplied with integrated debugger id78k0r-qb, on-chip debug emulator with programming function qb-mini2, power supply unit, and usb interface cable. any other products are sold separately. appendix a development tools user?s manual u17854ej6v0ud 710 figure a-1. developmen t tool configuration (2/2) (2) when using the on-chip debug emulat or with programming function qb-mini2 language processing software ? assembler package ? c compiler package ? device file note 1 debugging software ? integrated debugger note 1 ? system simulator host machine (pc or ews) usb interface cable note 3 qb-mini2 note 3 78k0-ocd board note 3 target connector target system ? software package ? project manager software package appendix a development tools user?s manual u17854ej6v0ud 711 a.1 software package development tools (software) common to t he 78k0r microcontrollers are combined in this package. sp78k0r 78k0r series software package part number: s sp78k0r remark in the part number differs depending on the host machine and os used. s sp78k0r host machine os supply medium ab17 windows (japanese version) bb17 pc-9800 series, ibm pc/at compatibles windows (english version) cd-rom a.2 language processing software this assembler converts programs written in mnemonics into object codes executable with a microcontroller. this assembler is also provided with functi ons capable of automatically creating symbol tables and branch instruction optimization. this assembler should be used in combi nation with a device file (df781188) (sold separately). appendix a development tools user?s manual u17854ej6v0ud 712 remark in the part number differs depending on the host machine and os used. s ra78k0r s cc78k0r host machine os supply medium ab17 windows (japanese version) bb17 pc-9800 series, ibm pc/at compatibles windows (english version) cd-rom s df781188 host machine os supply medium ab13 windows (japanese version) bb13 pc-9800 series, ibm pc/at compatibles windows (english version) 3.5-inch 2hd fd a.3 control software pm+ project manager this is control software designed to enable e fficient user program development in the windows environment. all operations used in development of a user program, such as starting the editor, building, and starting the debugger, can be performed from the project manager. appendix a development tools user?s manual u17854ej6v0ud 713 a.4.2 when using on-chip debug emul ator with programming function qb-mini2 qb-mini2 on-chip debug emulator with programming function this is a flash memory programmer dedicat ed to microcontrollers with on-chip flash memory. it is available also as on-chip debug emulator which serves to debug hardware and software when developing application systems using the 78k0r. the qb-mini2 is supplied with a usb inte rface cable and connection cables (10-pin cable and 16-pin cable), and the 78k0-ocd board. to use 78k0r/ke3, use usb interface cable and 16-pin connection cable. remark download the software for operating the qb-mi ni2 from the download site for minicube2 (http://www.necel.com/micro/en/developmen t/asia/minicube2/minicube2.html). a.5 debugging tools (hardware) a.5.1 when using in-circu it emulator qb-78k0rkx3 qb-78k0kx3 in-circuit emulator this in-circuit emulator serves to debug har dware and software when developing application systems using the 78k0r/kx3. it supports to the integrated debugger (id78k0r-qb). this emulator should be used in combination with a power supply unit and emulation probe, and the usb is used to connect this em ulator to the host machine. qb-144-ca-01 check pin adapter this check pin adapter is used in waveform monitoring using the oscilloscope, etc. qb-144-ep-02s emulation probe this emulation probe is flexible type and used to connect the in-circuit emulator and target system. qb-64gk-ea-06t, qb-64gb-ea-08t, qb-64ga-ea-02t note 1 , qb-64f1-ea-01t note 1 exchange adapter this exchange adapter is used to perform pin conver sion from the in-circuit emulator to target connector. ? qb-64gk-ea-06t: 64-pin pl astic lqfp (gk-gaj type) ? qb-64gb-ea-08t: 64-pin pl astic lqfp (gb-gah type) ? qb-64ga-ea-02t: 64-pin pl astic tqfp (ga-hab type) note 1 ? qb-64f1-ea-01t: 64-pin pl astic fbga (f1-an1 type) note 1 qb-64gk-ys-01t, qb-64gb-ys-01t, qb-64ga-ys-01t note 1 space adapter note 2 this space adapter is used to adjust the height bet ween the target system and in-circuit emulator. ? qb-64gk-ys-01t: 64-pin pl astic lqfp (gk-gaj type) ? qb-64gb-ys-01t: 64-pin pl astic lqfp (gb-gah type) ? qb-64ga-ys-01t: 64-pin pl astic tqfp (ga-hab type) note 1 qb-64gk-yq-01t, qb-64gb-yq-01t, qb-64ga-yq-01t note 1 yq connector note 2 this yq connector is used to connect the target connector and exchange adapter. ? qb-64gk-yq-01t: 64-pin pl astic lqfp (gk-gaj type) ? qb-64gb-yq-01t: 64-pin pl astic lqfp (gb-gah type) ? qb-64ga-yq-01t: 64-pin plastic tqfp (ga-hab type) note 1 qb-64gk-hq-01t, qb-64gb-hq-01t, qb-64ga-hq-01t note 1 mount adapter note 2 this mount adapter is used to mount the target device with socket. ? qb-64gk-hq-01t: 64-pin pl astic lqfp (gk-gaj type) ? qb-64gb-hq-01t: 64-pin pl astic lqfp (gb-gah type) ? qb-64ga-hq-01t: 64-pin plastic tqfp (ga-gab type) note 1 qb-64gk-nq-01t, qb-64gb-nq-01t, qb-64ga-nq-01t note 1 , qb-64fc-nq-01t note 1 target connector this target connector is used to mount on the target system. ? qb-64gk-nq-01t: 64-pin pl astic lqfp (gk-gaj type) ? qb-64gb-nq-01t: 64-pin pl astic lqfp (gb-gah type) ? qb-64ga-nq-01t: 64-pin plastic tqfp (ga-hab type) note 1 ? qb-64fc-nq-01t: 64-pin plastic fbga (f1-an1 type) note 1 notes 1. under development 2. these adapter are not necessary in 64-pin plastic fbga (f1-an1 type). appendix a development tools user?s manual u17854ej6v0ud 714 remarks 1. the qb-78k0rkx3 is supplied with a power suppl y unit and usb interface cable. as control software, integrated debugger id78k0r-qb and on-ch ip debug emulator with programming function qb-mini2 are supplied. 2. the packed contents differ depending on the part number, as follows. packed contents part number in-circuit emulator emulation probe exchange adapter yq connector target connector qb-78k0rkx3-zzz none qb-78k0rkx3-t64gk qb-64gk-ea-06t qb-64gk-yq-01t qb-64gk-nq-01t qb-78k0rkx3-t64gb qb-64gb-ea-08t qb-64gb-yq-01t qb-64gb-nq-01t qb-78k0rkx3-t64ga note qb-64ga-ea-02t note qb-64ga-yq-01t note qb-64ga-nq-01t note qb-78k0rkx3-t64f1 note qb-78k0rkx3 qb-144-ep-02s qb-64f1-ea-01t note none qb-64fc-nq-01t note note under development a.5.2 when using on-chip debug emul ator with programming function qb-mini2 qb-mini2 on-chip debug emulator with programming function this on-chip debug emulator serves to debug hardware and software when developing application systems using the 78k0r. it is av ailable also as flash memory programmer dedicated to microcontrollers with on-chip flash memory. the qb-mini2 is supplied with a usb inte rface cable and connection cables (10-pin cable and 16-pin cable), and the 78k0-ocd board. to use 78k0r/ke3, use usb interface cable and 16-pin connection cable. remark download the software for operating the qb-mi ni2 from the download site for minicube2 (http://www.necel.com/micro/en/developmen t/asia/minicube2/minicube2.html). appendix a development tools user?s manual u17854ej6v0ud 715 a.6 debugging tools (software) sm+ for 78k0r is windows-based software. it is used to perform debugging at the c source level or assembler level while simulating the operation of the target system on a host machine. use of sm+ for 78k0r allows the exec ution of application logical testing and performance testing on an independent basis from hardware development, thereby providing higher development e fficiency and software quality. sm+ for 78k0r should be used in combinati on with the device file (df781188) (sold separately). sm+ for 78k0r system simulator part number: s sm781000 this debugger supports the in-circuit emulat ors for the 78k0r microcontrollers. the id78k0r-qb is windows-based software. it has improved c-compatible debugging functions and can display the results of tracing with the source program using an integrating window function that associates the source program, disassemble display, and memory di splay with the trace result. it should be used in combination with the device file (sold separately). id78k0r-qb integrated debugger part number: s id78k0r-qb remark in the part number differs depending on the host machine and os used. s sm781000 s id78k0r-qb host machine os supply medium ab17 windows (japanese version) bb17 pc-9800 series, ibm pc/at compatibles windows (english version) cd-rom user?s manual u17854ej6v0ud 716 appendix b revision history b.1 major revisions in this edition (1/4) page description classification throughout change of status of pd78f1142, 78f1143, 78f1144, 78f1145, and 78f1146 from under development to mass production (d) chapter 1 outline p.17 addition of package and note to 1.3 ordering information (d) pp.18, 19 addition of package and note to 1.4 pin configuration (top view) (d) p.24 change of 1.7 outline of functions (d) chapter 2 pin functions p.25 change of corresponding pins of ev dd and v dd in table 2-1. pin i/o buffer power supplies (c) p.37 change of description in 2.2.15 regc (b) p.37 change of description in 2.2.18 flmd0 (c) p.39 modification of 37-a to 37-b and 39 to 2-w in table 2-2. connection of unused pins (c) pp.40, 41 modification of 37-a to 37-b and 39 to 2-w in figure 2-1. pin i/o circuit list (c) chapter 3 cpu architecture p.62 change of address in figure 3-16. configuration of general-purpose registers (a) pp.67, 68 addition of register and note in table 3-5. sfr list (c) chapter 4 port functions throughout addition of pim register and pom register in block diagram (c) p.88 change of corresponding pins of ev dd and v dd in table 4-1. pin i/o buffer power supplies (c) p.92 change of cautions 1 and cautions 2 in 4.2.1 port 0 (c) p.98 change of cautions 1, cautions 2, and cautions 3 in 4.2.2 port 1 (c) p.106 change of cautions 1 and addition of cautions 2 in 4.2.4 port 3 (c) p.107 change of cautions 2 in 4.2.5 port 4 (c) p.114 addition of caution to 4.2.7 port 6 (c) p.121 addition of caution to 4.2.11 port 14 (c) p.128 addition description to (4) port input mode registers (pim0) and (5) port output mode registers (pom0) in 4.3 (c) p.128 change of figure 4-32. format of port input mode register (a) chapter 5 clock generator p.146 addition of notes 3 to figure 5-6 format of system clock control register (ckc) (c) p.150 addition of cautions 5 to figure 5-8. format of operation speed mode control register (osmc) (b) chapter 6 timer array unit p.180 change of table 6-1. configuration of timer array unit (a) pp.180, 201, 217, 218, 220, 224, 225, 228, 232 deletion of bit 7 (tom07) of tom0 register (a) remark ?classification? in the above table classifies revisions as follows. (a): error correction, (b): additi on/change of specifications, (c): a ddition/change of description or note, (d): addition/change of package, part number, or ma nagement division, (e): addition/change of related documents appendix b revision history user?s manual u17854ej6v0ud 717 (2/4) page description classification chapter 6 timer array unit (continuation) p.187 change of description of master0n bit in figure 6-6. format of timer mode register 0n (tmr0n) (1/3) (c) p.197 change of figure 6-16. format of timer input select register 0 (tis0) and caution (c) p.199 addition of description to 6.3 (10) timer output register 0 (to0) (c) p.201 addition of description to 6.3 (12) timer output mode register 0 (tom0) (c) p.201 change of remark in figure 6-20. format of timer output mode register 0 (tom0) (c) p.202 change of remark in figure 6-21. format of input switch control register (isc) (c) chapter 7 real-time counter p.257 change of cautions 1 in figure 7-2. format of peripheral enable register 0 (per0) (c) p.267 addition of description to 7.3 (15) alarm hour register (alarmwh) (c) p.269 addition of note to figure 7-18. procedure for starti ng operation of real-time counter (c) chapter 8 watchdog timer p.275 change of cautions 1 and cautions 2 in 8.3 (1) watchdog timer enable register (wdte) (a) chapter 11 serial array unit throughout change of som register (a) p.310 change of figure 11-1. block diagram of serial array unit 0 (a) p.311 change of figure 11-2. block diagram of serial array unit 1 (a) p.330 change of description in 11.3 (12) serial output register m (som) (c) pp.336 to 338 addition of 11.4 operation stop mode (c) p.344 change of figure 11-27. procedure for resuming master transmission (c) p.353 change of figure 11-36. timing chart of master reception (in single-reception mode) (a) p.358 change of figure 11-41. procedure for resuming master transmission/reception (a) p.359 change of figure 11-42. timing chart of master transmission/reception (in single- transmission/reception mode) (a) p.361 change of figure 11-44. timing chart of master transmission/reception (in continuous transmission/reception mode) (a) p.362 change of figure 11-45. flowchart of master transmission/reception (in continuous transmission/reception mode) (a) p.367 change of figure 11-49. procedure for resuming slave transmission (a) p.368 change of figure 11-50. timing chart of slave transmission (in single-transmission mode) (c) p.375 change of figure 11-57. procedure for resuming slave reception (a) p.376 change of figure 11-58. timing chart of slave reception (in single-reception mode) (a) p.382 change of figure 11-63. procedure for resuming slave transmission/reception (a) p.383 change of figure 11-64. timing chart of slave transmission/reception (in single- transmission/reception mode) (a) p.385 change of figure 11-66. timing chart of slave transmission/reception (in continuous transmission/reception mode) (a) p.386 change of figure 11-67. flowchart of slave transmission/reception (in continuous transmission/reception mode) (a) p.400 change of transfer data length in 11.6.2 uart reception (a) p.405 change of figure 11-80. timing chart of uart reception (a) remark ?classification? in the above table classifies revisions as follows. (a): error correction, (b): additi on/change of specifications, (c): a ddition/change of description or note, (d): addition/change of package, part number, or ma nagement division, (e): addition/change of related documents appendix b revision history user?s manual u17854ej6v0ud 718 (3/4) page description classification chapter 11 serial array unit (continuation) p.407 change of transfer data length in 11.6.3 lin transmission (a) p.410 change of transfer data length in 11.6.4 lin reception (a) p.422 change of figure 11-89. initial setting procedure for address field transmission (a) p.423 change of figure 11-90. timing chart of address field transmission (a) p.424 change of figure 11-91. flowchart of address field transmission (a) p.426 change of figure 11-92. example of contents of registers for data transmission of simplified i 2 c (iic10) and addition of note (a) p.427 change of figure 11-94. flowchart of data transmission (a) p.429 change of figure 11-95. example of contents of registers for data reception of simplified i 2 c (iic10) and addition of note (a) p.430 change of figure 11-96. timing chart of data reception (c) p.430 change of figure 11-97. flowchart of data reception and addition of caution (c) p.431 change of figure 11-99. flowchart of stop condition generation (c) pp.437 to 441 addition of 11.9 relationship between register settings and pins (c) chapter 15 interrupt functions p.538 change of table 15-1. interrupt source list (a) chapter 17 standby function p.566 addition of note to figure 17-3. halt mode release by interrupt request generation (b) p.570 addition of note to figure 17-5. operation timing when stop mode is released (when unmasked interrupt request is generated) (b) pp.571, 572 addition of note to figure 17-6. stop mode release by interrupt request generation (b) chapter 18 reset function p.574 change of description in (4) (c) p.576 change of figure 18-2. timing of reset by reset input (b) p.577 change of figure 18-4. timing of reset in stop mode by reset input (b) chapter 23 flash memory p.612 change of pin no. in table 23-1. wiring between 78k0r/ke3 and dedicated flash memory programmer and addition of note (b) p.621 change of 23.4.1 flmd0 pin (c) p.629 change of remark in 23.8 flash memory programming by self-programming (e) p.630 change of figure 23-10. flow of self programming (rewriting flash memory) , and addition of remark (b, e) chapter 25 bcd correction circuit pp.638, 639 change of 25.3 bcd correction circuit operation (b) chapter 26 instruction set p.641 addition of addr5 to table 26-2. symbols in ?operation? column (c) p.657 change of operation of callt in table 26-5. operation list (15/17) (b) remark ?classification? in the above table classifies revisions as follows. (a): error correction, (b): additi on/change of specifications, (c): a ddition/change of description or note, (d): addition/change of package, part number, or ma nagement division, (e): addition/change of related documents appendix b revision history user?s manual u17854ej6v0ud 719 (4/4) page description classification chapter 27 electrical specifications throughout change of specifications of pd78f1142, 78f1143, 78f1144, 78f1145, and 78f1146 from target specifications to formal specifications (b) p.660 absolute maximum ratings ? change of input voltage ? change of condition of output voltage (b) p.663 change of notes 1 in internal oscillator characteristics (c) pp.665 to 669, 671, 672 dc characteristics ? change of condition of output current, high (i oh2 ) ? change of condition of output current, low (i ol2 ) ? change of condition of input voltage, high (v ih4 ) ? change of condition of input voltage, low (v il4 ) ? change of cautions 2 ? change of output voltage, high (v oh2 ) ? change of output voltage, low (v ol2 ) ? change of condition of input leakage current, high (i lih2 ) ? change of condition of input leakage current, low (i lil2 ) ? change of supply current (i dd1 ) and addition of low consumption current mode, notes 4 , and remarks 4. ? change of supply current (i dd2 ) and addition of low consumption current mode, notes 4 , and remarks 3. (b) pp.676 to 680 ac characteristics (1) basic operation ? addition of figures of minimum instruction execution time during main system clock operation and minimum instruction execution time during self programming mode in (1) basic operation ? change of title in ac timing test points (b) p.701 change of figures and figure title in supply voltage rise time timing (c) chapter 28 package drawings pp.706, 707 addition of package drawing (d) appendix a development tools p.712 change of a.4.1 when using flash memory programmer fg-fp4 and fl-pr4 (b) p.713 change of a.4.2 when using on-chip debug emulator with programming function qb-mini2 (c) pp.713, 714 change of a.5.1 when using in-circuit emulator qb-78k0rkx3 (d) p.714 change of a.5.2 when using on-chip debug emulator with programming function qb-mini2 (c) remark ?classification? in the above table classifies revisions as follows. (a): error correction, (b): additi on/change of specifications, (c): a ddition/change of description or note, (d): addition/change of package, part number, or ma nagement division, (e): addition/change of related documents appendix b revision history user?s manual u17854ej6v0ud 720 b.2 revision history of preceding editions here is the revision history of the preceding editi ons. chapter indicates the chapter of each edition. (1/6) edition description chapter change of status indication of pd78f1142 and pd78f1143 to ?under development? 1.1 feature ? addition of single-power supply flash memory security function ? addition of flash shield window f unction to self-programming function chapter 1 outline changes of figure 3-1 memory map ( pd78f1142) through figure 3-5 memory map ( pd78f1146) addition of 3.1.1(4) on-chip debug security id setting area addition of caution to 3.1.3 internal data memory space addition of caution to 3.2.4 special function registers (sfrs) change of note 1 in table 3-5 sfr list change of bcd adjust result register in table 3-5 sfr list addition of caution to 3.2.5 extended special function registers (2nd sfrs: 2nd special function registers) chapter 3 cpu architecture addition of caution to figure 5-7 format of peripheral enable register 0 (per0) addition of note 4 to 5.3 (7) operation speed mode control register (osmc) change of description of 5.3 (8) internal high-speed oscillator trimming register (hiotrm) addition of time until cpu operation start in figure 5-13 clock generator operation when power supply voltage is turned on (when lvi default start function stopped is set (option byte: lvioff = 1)) change of figure 5-14 clock generator operation when power supply voltage is turned on (when lvi default start function enabled is set (option byte: lvioff = 0)) addition of caution to 5.6.1 (3) <3> chapter 5 clock generator addition of caution 2 to 6.3 (1) peripheral enable register 0 (per0) change of figure 6-6 format of timer mode register 0n (tmr0n) addition of description to 6.3 (4) timer status register 0n (tsr0n) addition of table 6-3 ovf bit operation and set/clear conditions in each operation mode addition of table 6-4 operations from count operation enabled state to tcr0n count start , and (a) through (e) addition of description to 6.3 (11) timer output level register 0 (tol0) change of description of 6.3 (12) timer output mode register 0 (tom0) change of figure 6-20 format of timer output mode register 0 (tom0) and remark change of description to figure 6-21 format of input switch control register (isc) addition of 6.4 channel output (to0n pin) control 4th edition addition of 6.5 channel input (ti0n pin) control chapter 6 clock generator appendix b revision history user?s manual u17854ej6v0ud 721 (2/6) edition description chapter addition of md0n0 bit condition to titles in the following figures ? figure 6-37 example of basic timing of operation as interval timer/square wave output (md0n0 = 1) ? figure 6-45 example of basic timing of operation as frequency divider (md0n0 = 1) ? figure 6-49 example of block diagram of operation as input pulse interval measurement (md0n0 = 0) change of description of 6.7.3 operation as frequency divider change of description of 6.8.3 operation as multiple pwm output function chapter 6 clock generator change of clear conditions of real-time counter change of description and caution 1 in figure 7-2 format of peripheral enable register 0 (per0) addition of caution 2 to figure 7-2 format of peripheral enable register 0 (per0) addition of caution to figure 7-4 format of real-time counter control register 1 (rtcc1) addition of caution to figure 7-5 format of real-time counter control register 2 (rtcc2) change of note 2 in 7.3 (5) sub-count register (rsubc) change of description of 7.3 (8) hour count register (hour) change of bit name in figure 7-17 format of alarm week register (alarmww) chapter 7 real- time counter addition of caution 2 to 10.3 (1) peripheral enable register 0 (per0) change of table 10-2 a/d conversion time selection chapter 10 a/d converter addition of caution 3 to 11.3 (1) peripheral enable register 0 (per0) change of figure 11-7 format of serial communication operation setting register mn (scrmn) addition of description to 11.3 (13) serial output level register m (solm) changes of bits 1 and 3 in figure 11-16 format of serial output level register m (solm) changes of setting of (a) serial output register m (som) and note in figure 11-66 example of contents of registers for uart transmission of uart (uart0, uart1, uart2, uart3) change of figure 11-89 flowchart of address field transmission change of figure 11-92 flowchart of data transmission chapter 11 serial array unit addition of caution 2 to 12.3 (1) peripheral enable register 0 (per0) change of description of 12.5.4 (2) selection clock setting method on the slave side chapter 12 serial interface iic0 addition of description to <1> and <3> in 14.4.1 operation procedure addition of description to 14.5.5 forced termination by software additions of description and note to 14.6 (1) priority of dma chapter 14 dma controller a dditions of reset processing time and clock supply stop time to the following figures ? figure 17-4 halt mode release by reset ? figure 17-6 stop mode release by interrupt request generation ? figure 17-7 stop mode release by reset 4th edition change of figure 17-5 operation timing when stop mode is released (when unmasked interrupt request is generated) chapter 17 standby function appendix b revision history user?s manual u17854ej6v0ud 722 (3/6) edition description chapter change of figure 18-2 timing of reset by reset input change of figure 18-3 timing of reset due to watchdog timer overflow change of figure 18-4 timing of reset in stop mode by reset input chapter 18 reset function addition of reset processing time to figure 19-2 timing of generation of internal reset signal by power-on-clear circuit and low-voltage detector addition of 19.4 caution for power-on-clear circuit chapter 19 power- on-clear circuit addition of operation stabilization time change of caution 2 in figure 20-3 format of low-voltage detection level select register (lvis) addition of 20.5 caution for low voltage detector chapter 20 low- voltage detector change of description of 22.1.1 (2) 000c1h/010c1h change of figure 22-2 format of user option byte(000c1h/010c1h) change of figure 22-4 format of on-chip debug option byte(000c3h/010c3h) chapter 22 option byte addition of description to 23. 4.1 (3) during writing by self programming addition of description to 23.5 (1) background event control register (bectl) addition of 23.6 programming method addition of 23.7 security settings addition of 23.8 flash memory programming by self-programming chapter 23 flash memory addition of chapter chapter 24 on-chip debugging deletion of description of bcd correcti on carry register (bcdcy bit), etc. chapter 25 bcd correction circuit absolute maximum ratings ? addition of regulator voltage (regc) ? change of input voltage and output voltage addition of min. value and max. val ue in xt1 oscillator characteristics dc characteristics ? change of note 1 in output current, high (i oh1 ) ? change of note 2 in output current, low (i ol1 ) ? addition of supply current ? addition of watchdog timer operating current (i wdt ) ? addition of a/d converter operating current (i adc ) ? addition of dma controller operating current (i dma ) ? addition of lvi operating current (i lvi ) change of min. value of conversion time (t conv ) of a/d converter characteristics addition of poc circuit characteristics addition of supply voltage rise time addition of lvi circuit characteristics addition of data memory stop mode low supply voltage data retention characteristics chapter 27 electrical specifications (target) 4th edition revision of chapter appendix a development tools appendix b revision history user?s manual u17854ej6v0ud 723 (4/6) edition description chapter 4th edition (modification version) deletion of description of temperature co rrection function of internal high-speed oscillation clock and temperature correction t ables h, l from the following chapters. ? chapter 3 cpu architecture ? chapter 5 clock generator ? chapter 10 a/d converter ? chapter 12 serial interface iic0 ? chapter 18 reset function ? chapter 27 electrical specifications (target) throughout deletion of target from the capacitance value of the capacitor connected to the regc pin throughout change of description in 2.2.15 regc modification of p60 to p64 in table 2-2 connection of unused pins chapter 2 pin functions addition (address change) of the bcdadj register to table 3-6 extended sfr (2nd sfr) list (1/4) chapter 3 cpu architecture change of figure 4-34 bit manipulation instruction (p10) chapter 4 port functions change of caution 2 in figure 5-6 format of system clock control register (ckc) change of description in 5.3 (8) internal high-speed oscillator trimming register (hiotrm) and addition of caution change of figure 5-9 format of internal high-speed oscillator trimming register (hiotrm) and addition of caution change of figure 5-13 clock generator operation when power supply voltage is turned on (when lvi default start function stopped is set (option byte: lvioff = 1)) chapter 5 clock generator addition of note to figure 6-5 format of timer clock select register 0 (tps0) change of table 6-3 ovf bit operation and set/clear conditions in each operation mode and addition of remark addition of caution 2 to figure 6-18. format of timer output register 0 (to0) change of description in 6.3 (14) noise filter enable register 1 (nfen1) change of 6.5.1 ti0n edge detection circuit chapter 6 timer array unit change of figure 7-1 block diagram of real-time counter chapter 7 real- time counter addition of caution 3 to table 8-4 setting window open period of watchdog timer chapter 8 watchdog timer fixing of the soe01 and soem3 bit settings to ?0?. fixing of the so10, som1, som3, cko10, ckom1, cko12, and ckom3 bit settings to ?1?. change of ?setting disabled (set to the initial value)? in remark change of figure 11-1 block diagram of serial array unit 0 change of figure 11-2 block diagram of serial array unit 1 addition of settings and note to figure 11-5 format of serial clock select register m (spsm) change of figure 11-11 format of serial channel enable status register m (sem) change of figure 11-14 format of serial output enable register m (soem) 5th edition addition of description to 11.3 (12) serial output register m (som) chapter 11 serial array unit appendix b revision history user?s manual u17854ej6v0ud 724 (5/6) edition description chapter change of figure 11-15 format of serial output register m (som) addition of note to transfer rate change of transfer rate and note in 11.4.4 slave transmission change of transfer rate in 11.4.5 slave reception change of transfer rate in 11.4.6 slave transmission/reception change of note in 11.4.7 (2) addition of setting and note to table 11-2 operating clock selection change of transfer rate and addition of note change of figure 11-66 example of contents of registers for uart transmission of uart (uart0, uart1, uart3) change of figure 11-74 example of contents of registers for uart reception of uart (uart0, uart1, uart3) change of figure 11-77 procedure for resuming uart reception addition of setting and note to table 11-3 operating clock selection change of figure 11-92 flowchart of data transmission addition of setting and note to table 11-4 operating clock selection chapter 11 serial array unit change of figure 14-9 example of setting for uart consecutive reception + ack transmission additions of description to 14.6 (4) dma pending instruction chapter 14 dma controller change of figure 17-4 halt mode release by reset change of figure 17-7 stop mode release by reset chapter 17 standby function change of reset processing in figure 18-2 timing of reset by reset input change of reset processing in figure 18-4 timing of reset in stop mode by reset input change of caution 2 in figure 18-5 format of reset control flag register (resf) chapter 18 reset function change of figure 19-2 timing of generation of internal reset signal by power- on-clear circuit and low-voltage detector (1/2) change of figure 19-2 timing of generation of internal reset signal by power- on-clear circuit and low-voltage detector (2/2) and addition of note change of figure 19-3 example of software processing after reset release chapter 19 power- on-clear circuit change of note 4 in figure 20-2 format of low-voltage detection register (lvim) and addition of caution 3 change of caution 2 in figure 20-3 format of low-voltage detection level select register (lvis) change of <5> in 20.4.1 (1) (a) change of note 2 in figure 20-5 timing of low-volt age detector internal reset signal generation (bit: lvisel = 0, option byte: lvioff = 1) change of description and caution in 20.4.1 (1) (b) change of figure 20-6 timing of low-voltage detector internal reset signal generation (bit: lvisel = 0, option byte: lvioff = 0) and note change of <4> in 20.4.1 (2) change of figure 20-7 timing of low-voltage detector internal reset signal generation (bit: lvisel = 1) and note 2 5th edition change of <5> in 20.4.2 (1) chapter 20 low- voltage detector appendix b revision history user?s manual u17854ej6v0ud 725 (6/6) edition description chapter additions of note 3 to figure 20-8 timing of low-voltage detector interrupt signal generation (bit: lvisel = 0, option byte: lvioff = 1) change of description and caution in 20.4.2 (1) (b) change of figure 20-9 timing of low-voltage detector interrupt signal generation (bit: lvisel = 0, option byte: lvioff = 0) and addition of note change of <4> in 20.4.2 (2) change of figure 20-10 timing of low-voltage detector interrupt signal generation (bit: lvisel = 1) and addition of note 3 change of figure 20-11 example of software processing after reset release chapter 20 low- voltage detector change of 21.1 regulator overview addition of note 3 to figure 21-1 format of regulator mode control register (rmc) chapter 21 regulator change of description in 22.1.1 (2) 000c1h/010c1h change of figure 22-2 format of user option byte (000c1h/010c1h) and caution 2 chapter 22 option byte change of description in 23.4.5 regc pin addition of caution 4 to 23.8 flash memory programming by self-programming chapter 23 flash memory addition of 24.3 securing of user resources chapter 24 on-chip debugging 5th edition modification of throughout chapter 27 electrical specifications (target) nec electronics corporation 1753, shimonumabe, nakahara-ku, kawasaki, kanagawa 211-8668, japan tel: 044-435-5111 http://www.necel.com/ [america] nec electronics america, inc. 2880 scott blvd. santa clara, ca 95050-2554, u.s.a. tel: 408-588-6000 800-366-9782 http://www.am.necel.com/ [asia & oceania] nec electronics (china) co., ltd 7th floor, quantum plaza, no. 27 zhichunlu haidian district, beijing 100083, p.r.china tel: 010-8235-1155 http://www.cn.necel.com/ shanghai branch room 2509-2510, bank of china tower, 200 yincheng road central, pudong new area, shanghai, p.r.china p.c:200120 tel:021-5888-5400 http://www.cn.necel.com/ shenzhen branch unit 01, 39/f, excellence times square building, no. 4068 yi tian road, futian district, shenzhen, p.r.china p.c:518048 tel:0755-8282-9800 http://www.cn.necel.com/ nec electronics hong kong ltd. unit 1601-1613, 16/f., tower 2, grand century place, 193 prince edward road west, mongkok, kowloon, hong kong tel: 2886-9318 http://www.hk.necel.com/ nec electronics taiwan ltd. 7f, no. 363 fu shing north road taipei, taiwan, r. o. c. tel: 02-8175-9600 http://www.tw.necel.com/ nec electronics singapore pte. ltd. 238a thomson road, #12-08 novena square, singapore 307684 tel: 6253-8311 http://www.sg.necel.com/ nec electronics korea ltd. 11f., samik lavied?or bldg., 720-2, yeoksam-dong, kangnam-ku, seoul, 135-080, korea tel: 02-558-3737 http://www.kr.necel.com/ for further information, please contact: g0706 [europe] nec electronics (europe) gmbh arcadiastrasse 10 40472 dsseldorf, germany tel: 0211-65030 http://www.eu.necel.com/ hanover office podbielskistrasse 166 b 30177 hannover tel: 0 511 33 40 2-0 munich office werner-eckert-strasse 9 81829 mnchen tel: 0 89 92 10 03-0 stuttgart office industriestrasse 3 70565 stuttgart tel: 0 711 99 01 0-0 united kingdom branch cygnus house, sunrise parkway linford wood, milton keynes mk14 6np, u.k. tel: 01908-691-133 succursale fran?aise 9, rue paul dautier, b.p. 52 78142 velizy-villacoublay cdex france tel: 01-3067-5800 sucursal en espa?a juan esplandiu, 15 28007 madrid, spain tel: 091-504-2787 tyskland filial t?by centrum entrance s (7th floor) 18322 t?by, sweden tel: 08 638 72 00 filiale italiana via fabio filzi, 25/a 20124 milano, italy tel: 02-667541 branch the netherlands steijgerweg 6 5616 hs eindhoven the netherlands tel: 040 265 40 10 |
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