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1 radhard msi logic ut54acs00/ut54acts00 radiation-hardened quadruple 2-input nand gates features 1.2m radiation-hardened cmos - latchup immune high speed low power consumption single 5 volt supply available qml q or v processes flexible package - 14-pin dip - 14-lead flatpack description the ut54acs00 and the ut54acts00 are quadruple, two- input nand gates. the circuits perform the boolean functions y = a b or y = a + b in positive logic. the devices are characterized over full military temperature range of -55 c to +125 c. function table logic symbol pinouts 14-pin dip top view 14-lead flatpack top view logic diagram inputs output a b y h h l l x h x l h y1 (3) (6) y2 y3 (8) (11) y4 (1) a1 (2) b1 (4) a2 (5) b2 (9) a3 (10) b3 (12) a4 (13) b4 note: 1. logic symbol in accordance with ansi/ieee standard 91-1984 and iec publication 617-12. & 1 14 2 13 3 12 4 11 5 10 6 9 7 8 a1 b1 y1 a2 b2 y2 v ss v dd b4 a4 y4 b3 a3 y3 v dd b4 a4 y4 b3 a3 y3 a1 b1 y1 a2 b2 y2 v ss 1 14 2 13 3 12 4 11 5 10 6 9 7 8 b4 a4 y4 b3 a3 y3 a1 b1 y1 a2 b2 y2
radhard msi logic 2 ut54acs00/ut54acts00 radiation hardness specifications 1 notes: 1. logic will not latchup during radiation exposure within the limits defined in the table. 2. device storage elements are immune to seu affects. absolute maximum ratings note: 1.stresses outside the listed absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, f unctional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. exposure to absolute ma ximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter limit units total dose 1.0e6 rads(si) seu threshold 2 80 mev-cm 2 /mg sel threshold 120 mev-cm 2 /mg neutron fluence 1.0e14 n/cm 2 symbol parameter limit units v dd supply voltage -0.3 to 7.0 v v i/o voltage any pin -.3 to v dd +.3 v t stg storage temperature range -65 to +150 c t j maximum junction temperature +175 c t ls lead temperature (soldering 5 seconds) +300 c q jc thermal resistance junction to case 20 c/w i i dc input current 10 ma p d maximum power dissipation 1 w symbol parameter limit units v dd supply voltage 4.5 to 5.5 v v in input voltage any pin 0 to v dd v t c temperature range -55 to + 125 c
3 radhard msi logic ut54acs00/ut54acts00 dc electrical characteristics 7 (v dd = 5.0v 10%; v ss = 0v 6 , -55 c < t c < +125 c) symbol parameter condition min max unit v il low-level input voltage 1 acts acs 0.8 .3v dd v v ih high-level input voltage 1 acts acs .5v dd .7v dd v i in input leakage current acts/acs v in = v dd or v ss -1 1 m a v ol low-level output voltage 3 acts acs i ol = 8.0ma i ol = 100 m a 0.40 0.25 v v oh high-level output voltage 3 acts acs i oh = -8.0ma i oh = -100 m a .7v dd v dd - 0.25 v i os short-circuit output current 2 ,4 acts/acs v o = v dd and v ss -200 200 ma i ol output current 10 (sink) v in = v dd or v ss v ol = 0.4v 8 ma i oh output current 10 (source) v in = v dd or v ss v oh = v dd - 0.4v -8 ma p total power dissipation 2, 8, 9 c l = 50pf 1.8 mw/ mhz i ddq quiescent supply current v dd = 5.5v 10 m a d i ddq quiescent supply current delta acts for input under test v in = v dd - 2.1v for all other inputs v in = v dd or v ss v dd = 5.5v 1.6 ma c in input capacitance 5 | = 1mhz @ 0v 15 pf c out output capacitance 5 | = 1mhz @ 0v 15 pf
radhard msi logic 4 ut54acs00/ut54acts00 notes: 1. functional tests are conducted in accordance with mil-std-883 with the following input test conditions: v ih = v ih (min) + 20%, - 0%; v il = v il (max) + 0%, - 50%, as specified herein, for ttl, cmos, or schmitt compatible inputs. devices may be tested using any input voltage within th e above specified range, but are guaranteed to v ih (min) and v il (max). 2. supplied as a design limit but not guaranteed or tested. 3. per mil-prf-38535, for current density 5.0e5 amps/cm 2 , the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pf/mhz. 4. not more than one output may be shorted at a time for maximum duration of one second. 5. capacitance measured for initial qualification and when design changes may affect the value. capacitance is measured between the designated terminal and v ss at frequency of 1mhz and a signal amplitude of 50mv rms maximum. 6. maximum allowable relative shift equals 50mv. 7. all specifications valid for radiation dose 1e6 rads(si). 8. power does not include power contribution of any ttl output sink current. 9. power dissipation specified per switching output. 10. this value is guaranteed based on characterization data, but not tested. ac electrical characteristics 2 (v dd = 5.0v 10%; v ss = 0v 1 , -55 c < t c < +125 c) notes: 1. maximum allowable relative shift equals 50mv. 2. all specifications valid for radiation dose 1e6 rads(si). symbol parameter minimum maximum unit t phl input to yn 1 14 ns t plh input to yn 1 11 ns
5 radhard msi logic ut54acs02/ut54acts02 radiation-hardened quadruple 2-input nor gates features radiation-hardened cmos - latchup immune high speed low power consumption single 5 volt supply available qml q or v processes flexible package - 14-pin dip - 14-lead flatpack description the ut54acs02 and the ut54acts02 are quadruple, two- input nor gates. the circuits perform the boolean functions y = a + b or y = a b in positive logic. the devices are characterized over full military temperature range of -55 c to +125 c. function table logic symbol pinouts 14-pin dip top view 14-lead flatpack top view logic diagram inputs output a b y h x l x h l l l h y1 (1) (4) y2 y3 (10) (13) y4 (2) a1 (3) b1 (5) a2 (6) b2 (8) a3 (9) b3 (11) a4 (12) b4 note: 1. logic symbol in accordance with ansi/ieee standard 91-1984 and iec publication 617-12. 1 1 2 3 4 5 7 6 14 13 12 11 10 8 9 y1 a1 b1 y2 a2 b2 v ss v dd y4 b4 a4 y3 b3 a3 1 2 3 4 5 7 6 14 13 12 11 10 8 9 y1 a1 b1 y2 a2 b2 v ss v dd y4 b4 a4 y3 b3 a3 b4 a4 y4 b3 a3 y3 a1 b1 y1 a2 b2 y2
radhard msi logic 6 ut54acs02/ut54acts02 radiation hardness specifications 1 notes: 1. logic will not latchup during radiation exposure within the limits defined in the table. 2. device storage elements are immune to seu affects. absolute maximum ratings note: 1. stresses outside the listed absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. exposure to absolute ma ximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter limit units total dose 1.0e6 rads(si) seu threshold 2 80 mev-cm 2 /mg sel threshold 120 mev-cm 2 /mg neutron fluence 1.0e14 n/cm 2 symbol parameter limit units v dd supply voltage -0.3 to 7.0 v v i/o voltage any pin -.3 to v dd +.3 v t stg storage temperature range -65 to +150 c t j maximum junction temperature +175 c t ls lead temperature (soldering 5 seconds) +300 c jc thermal resistance junction to case 20 c/w i i dc input current ma p d maximum power dissipation 1 w symbol parameter limit units v dd supply voltage 4.5 to 5.5 v v in input voltage any pin 0 to v dd v t c temperature range -55 to + 125 c
7 radhard msi logic ut54acs02/ut54acts02 dc electrical characteristics 7 (v dd = 5.0v 10%; v ss = 0v 6 , -55 c < t c < +125 c) symbol parameter condition min max unit v il low-level input voltage 1 acts acs 0.8 .3v dd v v ih high-level input voltage 1 acts acs .5v dd .7v dd v i in input leakage current acts/acs v in = v dd or v ss -1 1 a v ol low-level output voltage 3 acts acs i ol = 8.0ma i ol = 100 a 0.40 0.25 v v oh high-level output voltage 3 acts acs i oh = -8.0ma i oh = -100 a .7v dd v dd - 0.25 v i os short-circuit output current 2 ,4 acts/acs v o = v dd and v ss -200 200 ma i ol output current 10 (sink) v in = v dd or v ss v ol = 0.4v 8 ma i oh output current 10 (source) v in = v dd or v ss v oh = v dd - 0.4v -8 ma p total power dissipation 2, 8, ,9 c l = 50pf 1.8 mw/ mhz i ddq quiescent supply current v dd = 5.5v 10 a i ddq quiescent supply current delta acts for input under test v in = v dd - 2.1v for all other inputs v in = v dd or v ss v dd = 5.5v 1.6 ma c in input capacitance 5 = 1mhz @ 0v 15 pf c out output capacitance 5 = 1mhz @ 0v 15 pf
radhard msi logic 8 ut54acs02/ut54acts02 notes: 1. functional tests are conducted in accordance with mil-std-883 with the following input test conditions: v ih = v ih (min) + 20%, - 0%; v il = v il (max) + 0%, - 50%, as specified herein, for ttl, cmos, or schmitt compatible inputs. devices may be tested using any input voltage within th e above specified range, but are guaranteed to v ih (min) and v il (max). 2. supplied as a design limit but not guaranteed or tested. 3. per mil-prf-38535, for current density 5.0e5 amps/cm 2 , the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pf/mhz. 4. not more than one output may be shorted at a time for maximum duration of one second. 5. capacitance measured for initial qualification and when design changes may affect the value. capacitance is measured between the designated terminal and v ss at frequency of 1mhz and a signal amplitude of 50mv rms maximum. 6. maximum allowable relative shift equals 50mv. 7. all specifications valid for radiation dose 1e6 rads(si). 8. power does not include power contribution of any ttl output sink current. 9. power dissipation specified per switching output. 10. this value is guaranteed based on characterization data, but not tested. ac electrical characteristics 2 (v dd = 5.0v 10%; v ss = 0v 1 , -55 c < t c < +125 c) notes: 1. maximum allowable relative shift equals 50mv. 2. all specifications valid for radiation dose 1e6 rads(si). symbol parameter minimum maximum unit t phl input to yn 1 13 ns t plh input to yn 1 11 ns
9 radhard msi logic ut54acs04/ut54acts04 radiation-hardened hex inverters features radiation-hardened cmos - latchup immune high speed low power consumption single 5 volt supply available qml q or v processes flexible package - 14-pin dip - 14-lead flatpack description the ut54acs04 and the ut54acts04 are hex inverters. the circuits perform the boolean function y = a . the devices are characterized over full military temperature range of -55 c to +125 c. function table logic symbol pinouts 14-pin dip top view 14-lead flatpack top view logic diagram input output a y h l l h y1 y2 y3 y4 (1) a1 (5) a3 (11) a5 (13) a6 note: 1. logic symbol in accordance with ansi/ieee standard 91-1984 and iec publication 617-12. 1 (3) a2 (9) a4 (2) (10) (12) (4) (8) y5 y6 (6) a1 y1 a2 y2 a3 y3 v ss v dd a6 y6 a5 y5 a4 y4 1 14 2 13 3 12 4 11 5 10 6 9 7 8 v dd a6 y6 a5 y5 a4 y4 a1 y1 a2 y2 a3 y3 v ss 1 14 2 13 3 12 4 11 5 10 6 9 7 8 y4 y3 y1 y2 y6 y5 a4 a3 a1 a2 a6 a5
radhard msi logic 10 ut54acs04/ut54acts04 radiation hardness specifications 1 notes: 1. logic will not latchup during radiation exposure within the limits defined in the table. 2. device storage elements are immune to seu affects. absolute maximum ratings note: 1. stresses outside the listed absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. exposure to absolute m aximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter limit units total dose 1.0e6 rads(si) seu threshold 2 80 mev-cm 2 /mg sel threshold 120 mev-cm 2 /mg neutron fluence 1.0e14 n/cm 2 symbol parameter limit units v dd supply voltage -0.3 to 7.0 v v i/o voltage any pin -.3 to v dd +.3 v t stg storage temperature range -65 to +150 c t j maximum junction temperature +175 c t ls lead temperature (soldering 5 seconds) +300 c jc thermal resistance junction to case 20 c/w i i dc input current 10 ma p d maximum power dissipation 1 w symbol parameter limit units v dd supply voltage 4.5 to 5.5 v v in input voltage any pin 0 to v dd v t c temperature range -55 to + 125 c
11 radhard msi logic ut54acs04/ut54acts04 dc electrical characteristics 7 (v dd = 5.0v 10%; v ss = 0v 6 , -55 c < t c < +125 c) symbol parameter condition min max unit v il low-level input voltage 1 acts acs 0.8 .3v dd v v ih high-level input voltage 1 acts acs .5v dd .7v dd v i in input leakage current acts/acs v in = v dd or v ss -1 1 a v ol low-level output voltage 3 acts acs i ol = 8ma i ol = 100 a 0.40 0.25 v v oh high-level output voltage 3 acts acs i oh = -8ma i oh = -100 a .7v dd v dd - 0.25 v i os short-circuit output current 2 ,4 acts/acs v o = v dd and v ss -200 200 ma i ol output current 10 (sink) v in = v dd or v ss v ol = 0.4v 8 ma i oh output current 10 (source) v in = v dd or v ss v oh = v dd - 0.4v -8 ma p total power dissipation 2, 8, 9 c l = 50pf 1.8 mw/ mhz i ddq quiescent supply current v dd = 5.5v 10 a i ddq quiescent supply current delta acts for input under test v in = v dd - 2.1v for all other inputs v in = v dd or v ss v dd = 5.5v 1.6 ma c in input capacitance 5 = 1mhz @ 0v 15 pf c out output capacitance 5 = 1mhz @ 0v 15 pf
radhard msi logic 12 ut54acs04/ut54acts04 notes: 1. functional tests are conducted in accordance with mil-std-883 with the following input test conditions: v ih = v ih (min) + 20%, - 0%; v il = v il (max) + 0%, - 50%, as specified herein, for ttl, cmos, or schmitt compatible inputs. devices may be tested using any input voltage within th e above specified range, but are guaranteed to v ih (min) and v il (max). 2. supplied as a design limit but not guaranteed or tested. 3. per mil-prf-38535, for current density 5.0e5 amps/cm 2 , the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pf/mhz. 4. not more than one output may be shorted at a time for maximum duration of one second. 5. capacitance measured for initial qualification and when design changes may affect the value. capacitance is measured between the designated terminal and v sss at frequency of 1mhz and a signal amplitude of 50mv rms maximum. 6. maximum allowable relative shift equals 50mv. 7. all specifications valid for radiation dose 1e6 rads(si). 8. power does not include power contribution of any ttl output sink current. 9. power dissipation specified per switching output. 10. this value is guaranteed based on characterization data, but not tested. ac electrical characteristics 2 (v dd = 5.0v 10%; v ss = 0v 1 , -55 c < t c < +125 c) notes: 1. maximum allowable relative shift equals 50mv. 2. all specifications valid for radiation dose 1e6 rads(si) symbol parameter minimum maximum unit t phl input to yn 1 19 ns t plh input to yn 1 11 ns
13 radhard msi logic ut54acs08/ut54acts08 radiation-hardened quadruple 2-input and gates features ? 1.2m radiation-hardened cmos - latchup immune ? high speed ? low power consumption ? single 5 volt supply ? available qml q or v processes ? flexible package - 14-pin dip - 14-lead flatpack description the ut54acs08 and the ut54acts08 are quadruple two- input and gates. the circuits perform the boolean functions y= a b or y =in positive logic. the devices are characterized over full military temperature range of -55 c to +125 c. function table logic symbol pinouts 14-pin dip top view 14-pin flatpack top view logic diagram input output a b y h h h l x l x l l a + b y1 (3) (6) y2 y3 (8) (11) y4 (1) a1 (2) b1 (4) a2 (5) b2 (9) a3 (10) b3 (12) a4 (13) b4 note: 1. logic symbol in accordance with ansi/ieee standard 91-1984 and iec publication 617-12. a1 b1 y1 a2 b2 y2 v ss v dd b4 a4 y4 b3 a3 y3 1 14 2 13 3 12 4 11 5 10 6 9 7 8 1 2 3 4 5 7 6 14 13 12 11 10 8 9 v dd b4 a4 y4 b3 a3 y3 a1 b1 y1 a2 b2 y2 v ss b4 a4 y4 b3 a3 y3 a1 b1 y1 a2 b2 y2
radhard msi logic 14 ut54acs08/ut54acts08 radiation hardness specifications 1 notes: 1. logic will not latchup during radiation exposure within the limits defined in the table. 2. device storage elements are immune to seu affects. absolute maximum ratings note: 1. stresses outside the listed absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. exposure to absolute ma ximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter limit units total dose 1.0e6 rads(si) seu threshold 2 80 mev-cm 2 /mg sel threshold 120 mev-cm 2 /mg neutron fluence 1.0e14 n/cm 2 symbol parameter limit units v dd supply voltage -0.3 to 7.0 v v i/o voltage any pin -.3 to v dd +.3 v t stg storage temperature range -65 to +150 c t j maximum junction temperature +175 c t ls lead temperature (soldering 5 seconds) +300 c jc thermal resistance junction to case 20 c/w i i dc input current 10 ma p d maximum power dissipation 1 w symbol parameter limit units v dd supply voltage 4.5 to 5.5 v v in input voltage any pin 0 to v dd v t c temperature range -55 to + 125 c
15 radhard msi logic ut54acs08/ut54acts08 dc electrical characteristics 7 (v dd = 5.0v 10%; v ss = 0v 6, -55 c < t c < +125 c) symbol parameter condition min max unit v il low-level input voltage 1 acts acs 0.8 .3v dd v v ih high-level input voltage 1 acts acs .5v dd .7v dd v i in input leakage current acts/acs v in = v dd or v ss -1 1 a v ol low-level output voltage 3 acts acs i ol = 8.0ma i ol = 100 a 0.40 0.25 v v oh high-level output voltage 3 acts acs i oh = -8.0ma i oh = -100 a .7v dd v dd - 0.25 v i os short-circuit output current 2 ,4 acts/acs v o = v dd and v ss -200 200 ma i ol output current 10 (sink) v in = v dd or v ss v ol = 0.4v 8 ma i oh output current 10 (source) v in = v dd or v ss v oh = v dd - 0.4v -8 ma p total power dissipation 2, 8, 9 c l = 50pf 1.8 mw/ mhz i ddq quiescent supply current v dd = 5.5v 10 a i ddq quiescent supply current delta acts for input under test v in = v dd - 2.1v for all other inputs v in = v dd or v ss v dd = 5.5v 1.6 ma c in input capacitance 5 = 1mhz @ 0v 15 pf c out output capacitance 5 = 1mhz @ 0v 15 pf
radhard msi logic 16 ut54acs08/ut54acts08 notes: 1. functional tests are conducted in accordance with mil-std-883 with the following input test conditions: v ih = v ih (min) + 20%, - 0%; v il = v il (max) + 0%, - 50%, as specified herein, for ttl, cmos, or schmitt compatible inputs. devices may be tested using any input voltage within th e above specified range, but are guaranteed to v ih (min) and v il (max). 2. supplied as a design limit but not guaranteed or tested. 3. per mil-prf-38535, for current density 5.0e5 amps/cm 2 , the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pf/mhz. 4. not more than one output may be shorted at a time for maximum duration of one second. 5. capacitance measured for initial qualification and when design changes may affect the value. capacitance is measured between the designated terminal and v ss at frequency of 1mhz and a signal amplitude of 50mv rms maximum. 6. maximum allowable relative shift equals 50mv. 7. all specifications valid for radiation dose 1e6 rads(si). 8. power does not include power contribution of any ttl output sink current. 9. power dissipation specified per switching output. 10. this value is guaranteed based on characterization data, but not tested. ac electrical characteristics 2 (v dd = 5.0v 10%; v ss = 0v 1 , -55 c < t c < +125 c) notes: 1. maximum allowable relative shift equals 50mv. 2. all specifications valid for radiation dose 1e6 rads(si). symbol parameter minimum maximum unit t phl input to yn 1 13 ns t plh input to yn 1 10 ns
17 radhard msi logic ut54acs10/ut54acts10 radiation-hardened triple 3-input nand gates features ? radiation-hardened cmos - latchup immune ? high speed ? low power consumption ? single 5 volt supply ? available qml q or v processes ? flexible package - 14-pin dip - 14-lead flatpack description the ut54acs10 and the ut54acts10 are triple three-input nand gates. the circuits perform the boolean functions y = a b c or y = a + b + c in positive logic. the devices are characterized over full military temperature range of -55 c to +125 c. function table logic symbol pinouts 14-pin dip top view 14-lead flatpack top view logic diagram inputs output a b c y h h h l l x x h x l x h x x l h y1 (12) (6) y2 y3 (8) (1) a1 (2) b1 (13) c1 (3) a2 (4) b2 (5) c2 (9) a3 (10) b3 note: . 1. logic symbol in accordance with ansi/ieee standard 91-1984 and iec publication 617-12. (11) c3 1 2 3 4 5 7 6 14 13 12 11 10 8 9 a1 b1 a2 b2 c2 y2 v ss v dd c1 y1 c3 b3 a3 y3 v dd c1 y1 c3 b3 a3 y3 a1 b1 a2 b2 c2 y2 v ss 1 2 3 4 5 7 6 14 13 12 11 10 8 9 y1 a1 b1 c1 y2 a2 b2 c2 y3 a3 b3 c3
radhard msi logic 18 ut54acs10/ut54acts10 radiation hardness specifications 1 notes: 1. logic will not latchup during radiation exposure within the limits defined in the table. 2. device storage elements are immune to seu affects. absolute maximum ratings note: 1. stresses outside the listed absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. exposure to absolute m aximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter limit units total dose 1.0e6 rads(si) seu threshold 2 80 mev-cm 2 /mg sel threshold 120 mev-cm 2 /mg neutron fluence 1.0e14 n/cm 2 symbol parameter limit units v dd supply voltage -0.3 to 7.0 v v i/o voltage any pin -.3 to v dd +.3 v t stg storage temperature range -65 to +150 c t j maximum junction temperature +175 c t ls lead temperature (soldering 5 seconds) +300 c jc thermal resistance junction to case 20 c/w i i dc input current 10 ma p d maximum power dissipation 1 w symbol parameter limit units v dd supply voltage 4.5 to 5.5 v v in input voltage any pin 0 to v dd v t c temperature range -55 to + 125 c
19 radhard msi logic ut54acs10/ut54acts10 dc electrical characteristics 7 (v dd = 5.0v 10%; v ss = 0v 6 , -55 c < t c < +125 c) symbol parameter condition min max unit v il low-level input voltage 1 acts acs 0.8 .3v dd v v ih high-level input voltage 1 acts acs .5v dd .7v dd v i in input leakage current acts/acs v in = v dd or v ss -1 1 a v ol low-level output voltage 3 acts acs i ol = 8.0ma i ol = 100 a 0.40 0.25 v v oh high-level output voltage 3 acts acs i oh = -8.0ma i oh = -100 a .7v dd v dd - 0.25 v i os short-circuit output current 2 ,4 acts/acs v o = v dd and v ss -200 200 ma i ol output current 10 (sink) v in = v dd or v ss v ol = 0.4v 8 ma i oh output current 10 (source) v in = v dd or v ss v oh = v dd - 0.4v -8 ma p total power dissipation 2, 8, 9 c l = 50pf 1.8 mw/ mhz i ddq quiescent supply current v dd = 5.5v 10 a i ddq quiescent supply current delta acts for input under test v in = v dd - 2.1v for all other inputs v in = v dd or v ss v dd = 5.5v 1.6 ma c in input capacitance 5 = 1mhz @ 0v 15 pf c out output capacitance 5 = 1mhz @ 0v 15 pf
radhard msi logic 20 ut54acs10/ut54acts10 notes: 1. functional tests are conducted in accordance with mil-std-883 with the following input test conditions: v ih = v ih (min) + 20%, - 0%; v il = v il (max) + 0%, - 50%, as specified herein, for ttl, cmos, or schmitt compatible inputs. devices may be tested using any input voltage within t he above specified range, but are guaranteed to v ih (min) and v il (max). 2. supplied as a design limit but not guaranteed or tested. 3. per mil-prf-38535, for current density 5.0e5 amps/cm 2 , the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pf/mhz. 4. not more than one output may be shorted at a time for maximum duration of one second. 5. capacitance measured for initial qualification and when design changes may affect the value. capacitance is measured between the designated terminal and v ss at frequency of 1mhz and a signal amplitude of 50mv rms maximum. 6. maximum allowable relative shift equals 50mv. 7. all specifications valid for radiation dose 1e6 rads(si). 8. power does not include power contribution of any ttl output sink current. 9. power dissipation specified per switching output. 10. this value is guaranteed based on characterization data, but not tested. ac electrical characteristics 2 (v dd = 5.0v 10%; v ss = 0v 1 , -55 c < t c < +125 c) notes: 1. maximum allowable relative shift equals 50mv. 2. all specifications valid for radiation dose 1e6 rads(si). symbol parameter minimum maximum unit t phl input to yn 1 16 ns t plh input to yn 1 12 ns
21 radhard msi logic ut54acs11/ut54acts11 radiation-hardened triple 3-input and gates features ? radiation-hardened cmos - latchup immune ? high speed ? low power consumption ? single 5 volt supply ? available qml q or v processes ? flexible package - 14-pin dip - 14-lead flatpack description the ut54acs11 and the ut54acts11 are triple three-input and gates. the circuits perform the boolean functions y = a b c or in positive logic. the devices are characterized over full military temperature range of -55 c to +125 c. function table logic symbol pinouts 14-pin dip top view 14-lead flatpack top view logic diagram inputs output a b c y h h h h l x x l x l x l x x l l y = a + b + c y1 (12) (6) y2 y3 (8) (1) a1 (2) b1 (13) c1 (3) a2 (4) b2 (5) c2 (9) a3 (10) b3 note: 1. logic symbol in accordance with ansi/ieee standard 91-1984 and iec publication 617-12. & (11) c3 1 2 3 4 5 7 6 14 13 12 11 10 8 9 a1 b1 a2 b2 c2 y2 v ss v dd c1 y1 c3 b3 a3 y3 1 2 3 4 5 7 6 14 13 12 11 10 8 9 v dd c1 y1 c3 b3 a3 y3 a1 b1 a2 b2 c2 y2 v ss y1 a1 b1 c1 y2 a2 b2 c2 y3 a3 b3 c3
radhard msi logic 22 ut54acs11/ut54acts11 radiation hardness specifications 1 notes: 1. logic will not latchup during radiation exposure within the limits defined in the table. 2. device storage elements are immune to seu affects. absolute maximum ratings note: 1. stresses outside the listed absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. exposure to absolute ma ximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter limit units total dose 1.0e6 rads(si) seu threshold 2 80 mev-cm 2 /mg sel threshold 120 mev-cm 2 /mg neutron fluence 1.0e14 n/cm 2 symbol parameter limit units v dd supply voltage -0.3 to 7.0 v v i/o voltage any pin -.3 to v dd +.3 v t stg storage temperature range -65 to +150 c t j maximum junction temperature +175 c t ls lead temperature (soldering 5 seconds) +300 c jc thermal resistance junction to case 20 c/w i i dc input current 10 ma p d maximum power dissipation 1 w symbol parameter limit units v dd supply voltage 4.5 to 5.5 v v in input voltage any pin 0 to v dd v t c temperature range -55 to + 125 c
23 radhard msi logic ut54acs11/ut54acts11 dc electrical characteristics 7 (v dd = 5.0v 10%; v ss = 0v 6 , -55 c < t c < +125 c) symbol parameter condition min max unit v il low-level input voltage 1 acts acs 0.8 .3v dd v v ih high-level input voltage 1 acts acs .5v dd .7v dd v i in input leakage current acts/acs v in = v dd or v ss -1 1 a v ol low-level output voltage 3 acts acs i ol = 8.0ma i ol = 100 a 0.40 0.25 v v oh high-level output voltage 3 acts acs i oh = -8.0ma i oh = -100 a .7v dd v dd - 0.25 v i os short-circuit output current 2 ,4 acts/acs v o = v dd and v ss -200 200 ma i ol output current 10 (sink) v in = v dd or v ss v ol = 0.4v 8 ma i oh output current 10 (source) v in = v dd or v ss v oh = v dd - 0.4v -8 ma p total power dissipation 2, 8, 9 c l = 50pf 1.8 mw/ mhz i ddq quiescent supply current v dd = 5.5v 10 a i ddq quiescent supply current delta acts for input under test v in = v dd - 2.1v for all other inputs v in = v dd or v ss v dd = 5.5v 1.6 ma c in input capacitance 5 = 1mhz @ 0v 15 pf c out output capacitance 5 = 1mhz @ 0v 15 pf
radhard msi logic 24 ut54acs11/ut54acts11 notes: 1. functional tests are conducted in accordance with mil-std-883 with the following input test conditions: v ih = v ih (min) + 20%, - 0%; v il = v il (max) + 0%, - 50%, as specified herein, for ttl, cmos, or schmitt compatible inputs. devices may be tested using any input voltage within th e above specified range, but are guaranteed to v ih (min) and v il (max). 2. supplied as a design limit but not guaranteed or tested. 3. per mil-prf-38535, for current density 5.0e5 amps/cm 2 , the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pf/mhz. 4. not more than one output may be shorted at a time for maximum duration of one second. 5. capacitance measured for initial qualification and when design changes may affect the value. capacitance is measured between the designated terminal and v ss at frequency of 1mhz and a signal amplitude of 50mv rms maximum. 6. maximum allowable relative shift equals 50mv. 7. all specifications valid for radiation dose 1e6 rads(si). 8. power does not include power contribution of any ttl output sink current. 9. power dissipation specified per switching output. 10. this value is guaranteed based on characterization data, but not tested. ac electrical characteristics 2 (v dd = 5.0v 10%; v ss = 0v 1 , -55 c < t c < +125 c) notes: 1. maximum allowable relative shift equals 50mv. 2. all specifications valid for radiation dose 1e6 rads(si). symbol parameter minimum maximum unit t phl input to yn 1 13 ns t plh input to yn 1 10 ns
25 radhard msi logic ut54acs14/ut54acts14 radiation-hardened hex inverting schmitt triggers dec. 1, 2003 features ? 1.2 radiation-hardened cm os (acts14) and 0.6 crh cmos process (acs14) - latchup immune ? high speed ? low power consumption ? single 5 volt supply ? available qml q or v processes ? flexible package - 14-pin dip (not available for the acs14) - 14-lead flatpack description the ut54acs14 and the ut54ac ts14 are hex inverters. the circuits perform the boolean function y = a . the devices are characterized over full military temperature range of -55 c to +125 c. function table logic symbol pinouts 14-pin dip top view 14-lead flatpack top view logic diagram input output a y h l l h y1 y2 y3 y4 (1) a1 (5) a3 (11) a5 (13) a6 note: 1. logic symbol in accordance with ansi/ieee standard 91-1984 and iec publication 617-12. 1 (3) a2 (9) a4 (2) (10) (12) (4) (8) y5 y6 (6) a1 y1 a2 y2 a3 y3 v ss v dd a6 y6 a5 y5 a4 y4 114 213 312 411 510 69 78 v dd a6 y6 a5 y5 a4 y4 a1 y1 a2 y2 a3 y3 v ss 114 213 312 411 510 69 78 y4 y3 y1 y2 y6 y5 a4 a3 a1 a2 a6 a5
radhard msi logic 26 ut54acs14/ut54acts14 radiation hardness specifications 1 notes: 1. logic will not latchup during radiation expo sure within the limits defined in the table. 2. device storage elements are immune to seu affects. absolute maximum ratings note: 1. stresses outside the listed absolute maximum ratings may cause permanent damage to the device . this is a stress rating only, functional operation of the device at these or any other cond itions beyond limits indicated in the operational sections is not reco mmended. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter limit units total dose 1.0e6 (acts14) 5.0e5 (acs14) rads(si) seu threshold 2 80 mev-cm 2 /mg sel threshold 120 mev-cm 2 /mg neutron fluence 1.0e14 n/cm 2 symbol parameter limit units v dd supply voltage -0.3 to 7.0 v v i/o voltage any pin -.3 to v dd +.3 v t stg storage temperature range -65 to +150 c t j maximum junction temperature +175 c t ls lead temperature (soldering 5 seconds) +300 c jc thermal resistance junction to case 20 c/w i i dc input current 10 ma p d maximum power dissipation 1 w symbol parameter limit units v dd supply voltage 4.5 to 5.5 v v in input voltage any pin 0 to v dd v t c temperature range -55 to + 125 c
27 radhard msi logic ut54acs14/ut54acts14 dc electrical characteristics 7 (v dd = 5.0v 10%; v ss = 0v 6 , -55 c < t c < +125 c) symbol parameter condition min max unit v t+ schmitt trigger, positive going 1 threshold acts acs 2.25 .7v dd v v t- schmitt trigger, negative going 1 threshold acts acs 0.5 .3v dd v v h schmitt trigger, typical range of hysteresis 2 acts acs 0.3 0.6 0.9 1.5 v i in input leakage current acts/acs v in = v dd or v ss -1 1 a v ol low-level output voltage 3 acts acs i ol = 8.0ma i ol = 100 a 0.40 0.25 v v oh high-level output voltage 3 acts acs i oh = -8.0ma i oh = -100 a .7v dd v dd -0.25 v i os short-circuit output current 2,4 acts/acs v o = v dd and v ss -200 200 ma i ol output current 10 (sink) v in = v dd or v ss v ol = 0.4v 8 ma i oh output current 10 (source) v in = v dd or v ss v oh = v dd - 0.4v -8 ma p total power dissipation 2, 8, 9 c l = 50pf 1.8 mw/ mhz i ddq quiescent supply current v dd = 5.5v 10 a ? i ddq quiescent supply current delta acts for input under test v in = v dd - 2.1v for all other inputs v in = v dd or v ss v dd = 5.5v 3.1 ma c in input capacitance 5 ? = 1mhz @ 0v 15 pf c out output capacitance 5 ? = 1mhz @ 0v 15 pf
radhard msi logic 28 ut54acs14/ut54acts14 notes: 1. functional tests are conducted in accordance with mi l-std-883 with the following input test conditions: v ih = v ih (min) + 20%, - 0%; v il = v il (max) + 0%, - 50%, as specified herein, for ttl, cmos, or schmitt compatible inputs. devices may be tested using any input voltage within t he above specified range, but are guaranteed to v ih (min) and v il (max). 2. supplied as a design limit bu t not guaranteed or tested. 3. per mil-prf-38535, for current density 5.0e5 amps/cm 2 , the maximum product of load capacitance (per ou tput buffer) times frequency should not exceed 3,765 pf/mhz. 4. not more than one output may be shorted at a time for maximum duration of one second. 5. capacitance measured fo r initial qualification and when design changes may affect the value. capacitance is measured between the designated terminal and v ss at frequency of 1mhz and a signal amplitude of 50mv rms maximum. 6. maximum allowable relative shift equals 50mv. 7. all acts specifications are valid for radiation dose < 1e6 rads(si), and all acs specifications are valid for radiation dose < 5e5 rads(si). 8. power does not include power contribution of any ttl output sink current. 9. power dissipation specified per switching output. 10. this value is guaranteed based on characterization data, but not tested. ac electrical characteristics 2 (v dd = 5.0v 10%; v ss = 0v 1, -55 c < t c < +125 c) notes: 1. maximum allowable relative shift equals 50mv. 2. for the acts version, all specifi cations are valid for radiation dose < 1e6 rads(si). for the acs version, all sp ecifications are valid for radiation dose < 5e5 rads(si). symbol parameter minimum maximum unit t phl input to yn 2 14 ns t plh input to yn 2 13 ns
29 radhard msi logic ut54acs20/ut54acts20 radiation-hardened dual 4-input nand gates features ? radiation-hardened cmos - latchup immune ? high speed ? low power consumption ? single 5 volt supply ? available qml q or v processes ? flexible package - 14-pin dip - 14-lead flatpack description the ut54acs20 and the ut54acts20 are dual 4-input nand gates. the circuits perform the boolean functions y = a b c d or y = a + b + c + d in positive logic. the devices are characterized over full military temperature range of -55 c to +125 c. function table logic symbol pinouts 14-pin dip top view 14-lead flatpack top view logic diagram inputs output a b c d y h h h h l l x x x h x l x x h x x l x h x x x l h y1 (6) (8) y2 (1) a1 (2) b1 (4) c1 (5) d1 (9) a2 (10) b2 (12) c2 (13) d2 note: 1. logic symbol in accordance with ansi/ieee standard 91-1984 and iec publication 617-12. & 1 2 3 4 5 7 6 14 13 12 11 10 8 9 a1 b1 nc c1 d1 y1 v ss v dd d2 c2 nc b2 a2 y2 1 2 3 4 5 7 6 14 13 12 11 10 8 9 v dd d2 c2 nc b2 a2 y2 a1 b1 nc c1 d1 y1 v ss y1 a1 b1 c1 d1 a2 b2 c2 d2 y2
radhard msi logic 30 ut54acs20/ut54acts20 radiation hardness specifications 1 notes: 1. logic will not latchup during radiation exposure within the limits defined in the table. 2. device storage elements are immune to seu affects. absolute maximum ratings note: 1. stresses outside the listed absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. exposure to absolute ma ximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter limit units total dose 1.0e6 rads(si) seu threshold 2 80 mev-cm 2 /mg sel threshold 120 mev-cm 2 /mg neutron fluence 1.0e14 n/cm 2 symbol parameter limit units v dd supply voltage -0.3 to 7.0 v v i/o voltage any pin -.3 to v dd +.3 v t stg storage temperature range -65 to +150 c t j maximum junction temperature +175 c t ls lead temperature (soldering 5 seconds) +300 c jc thermal resistance junction to case 20 c/w i i dc input current 10 ma p d maximum power dissipation 1 w symbol parameter limit units v dd supply voltage 4.5 to 5.5 v v in input voltage any pin 0 to v dd v t c temperature range -55 to + 125 c
31 radhard msi logic ut54acs20/ut54acts20 dc electrical characteristics 7 (v dd = 5.0v 10%; v ss = 0v 6 , -55 c < t c < +125 c) symbol parameter condition min max unit v il low-level input voltage 1 acts acs 0.8 .3v dd v v ih high-level input voltage 1 acts acs .5v dd .7v dd v i in input leakage current acts/acs v in = v dd or v ss -1 1 a v ol low-level output voltage 3 acts acs i ol = 8.0ma i ol = 100 a 0.40 0.25 v v oh high-level output voltage 3 acts acs i oh = -8.0ma i oh = -100 a .7v dd v dd - 0.25 v i os short-circuit output current 2 ,4 acts/acs v o = v dd and v ss -200 200 ma i ol output current 10 (sink) v in = v dd or v ss v ol = 0.4v 8 ma i oh output current 10 (source) v in = v dd or v ss v oh = v dd - 0.4v -8 ma p total power dissipation 2, 8, 9 c l = 50pf 1.9 mw/ mhz i ddq quiescent supply current v dd = 5.5v 10 a i ddq quiescent supply current delta acts for input under test v in = v dd - 2.1v for all other inputs v in = v dd or v ss v dd = 5.5v 1.6 ma c in input capacitance 5 = 1mhz @ 0v 15 pf c out output capacitance 5 = 1mhz @ 0v 15 pf
radhard msi logic 32 ut54acs20/ut54acts20 notes: 1. functional tests are conducted in accordance with mil-std-883 with the following input test conditions: v ih = v ih (min) + 20%, - 0%; v il = v il (max) + 0%, - 50%, as specified herein, for ttl, cmos, or schmitt compatible inputs. devices may be tested using any input voltage within th e above specified range, but are guaranteed to v ih (min) and v il (max). 2. supplied as a design limit but not guaranteed or tested. 3. per mil-prf-38535, for current density 5.0e5 amps/cm 2 , the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pf/mhz. 4. not more than one output may be shorted at a time for maximum duration of one second. 5. capacitance measured for initial qualification and when design changes may affect the value. capacitance is measured between the designated terminal and v ss at frequency of 1mhz and a signal amplitude of 50mv rms maximum. 6. maximum allowable relative shift equals 50mv. 7. all specifications valid for radiation dose 1e6 rads(si). 8. power does not include power contribution of any ttl output sink current. 9. power dissipation specified per switching output. 10. this value is guaranteed based on characterization data, but not tested. ac electrical characteristics 2 (v dd = 5.0v 10%; v ss = 0v 1 , -55 c < t c < +125 c) notes: 1. maximum allowable relative shift equals 50mv. 2. all specifications valid for radiation dose 1e6 rads(si). symbol parameter minimum maximum unit t phl input to yn 1 15 ns t plh input to yn 1 11 ns
33 radhard msi logic ut54acs27/ut54acts27 radiation-hardened triple 3-input nor gates features ? radiation-hardened cmos - latchup immune ? high speed ? low power consumption ? single 5 volt supply ? available qml q or v processes ? flexible package - 14-pin dip - 14-lead flatpack description the ut54acs27 and the ut54acts27 are triple, three-input nor gates. the circuits perform the boolean functions y = a + b + c or y = a b c in positive logic. the devices are characterized over full military temperature range of -55 c to +125 c. function table logic symbol pinouts 14-pin dip top view 14-lead flatpack top view logic diagram inputs output a b c y h x x l x h x l x x h l l l l h y1 (12) (6) y2 y3 (8) (1) a1 (2) b1 (13) c1 (3) a2 (4) b2 (5) c2 (9) a3 (10) b3 note: 1. logic symbol in accordance with ansi/ieee standard 91-1984 and iec publication 617-12. 1 (11) c3 1 2 3 4 5 7 6 14 13 12 11 10 8 9 a1 b1 a2 b2 c2 y2 v ss v dd c1 y1 c3 b3 a3 y3 1 2 3 4 5 7 6 14 13 12 11 10 8 9 v dd c1 y1 c3 b3 a3 y3 a1 b1 a2 b2 c2 y2 v ss y1 a1 b1 c1 y2 a2 b2 c2 y3 a3 b3 c3
radhard msi logic 34 ut54acs27/ut54acts27 radiation hardness specifications 1 notes: 1. logic will not latchup during radiation exposure within the limits defined in the table. 2. device storage elements are immune to seu affects. absolute maximum ratings note: 1. stresses outside the listed absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. exposure to absolute ma ximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter limit units total dose 1.0e6 rads(si) seu threshold 2 80 mev-cm 2 /mg sel threshold 120 mev-cm 2 /mg neutron fluence 1.0e14 n/cm 2 symbol parameter limit units v dd supply voltage -0.3 to 7.0 v v i/o voltage any pin -.3 to v dd +.3 v t stg storage temperature range -65 to +150 c t j maximum junction temperature +175 c t ls lead temperature (soldering 5 seconds) +300 c jc thermal resistance junction to case 20 c/w i i dc input current ma p d maximum power dissipation 1 w symbol parameter limit units v dd supply voltage 4.5 to 5.5 v v in input voltage any pin 0 to v dd v t c temperature range -55 to + 125 c
35 radhard msi logic ut54acs27/ut54acts27 dc electrical characteristics 7 (v dd = 5.0v 10%; v ss = 0v 6 , -55 c < t c < +125 c) symbol parameter condition min max unit v il low-level input voltage 1 acts acs 0.8 .3v dd v v ih high-level input voltage 1 acts acs .5v dd .7v dd v i in input leakage current acts/acs v in = v dd or v ss -1 1 a v ol low-level output voltage 3 acts acs i ol = 8.0ma i ol = 100 a 0.40 0.25 v v oh high-level output voltage 3 acts acs i oh = -8.0ma i oh = -100 a .7v dd v dd - 0.25 v i os short-circuit output current 2 ,4 acts/acs v o = v dd and v ss -200 200 ma p total power dissipation 2, 8, 9 c l = 50pf 1.8 mw/ mhz i ol output current 10 (sink) v in = v dd or v ss v ol = 0.4v 8 ma i oh output current 10 (source) v in = v dd or v ss v oh = v dd - 0.4v -8 ma i ddq quiescent supply current v dd = 5.5v 10 a i ddq quiescent supply current delta acts for input under test v in = v dd - 2.1v for all other inputs v in = v dd or v ss v dd = 5.5v 1.6 ma c in input capacitance 5 = 1mhz @ 0v 15 pf c out output capacitance 5 = 1mhz @ 0v 15 pf
radhard msi logic 36 ut54acs27/ut54acts27 notes: 1.functional tests are conducted in accordance with mil-std-883 with the following input test conditions: v ih = v ih (min) + 20%, - 0%; v il = v il (max) + 0%, - 50%, as specified herein, for ttl, cmos, or schmitt compatible inputs. devices may be tested using any input voltage within th e above specified range, but are guaranteed to v ih (min) and v il (max). 2. supplied as a design limit but not guaranteed or tested. 3. per mil-prf-38535, for current density 5.0e5 amps/cm 2 , the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pf/mhz. 4. not more than one output may be shorted at a time for maximum duration of one second. 5. capacitance measured for initial qualification and when design changes may affect the value. capacitance is measured between the designated terminal and v ss at frequency of 1mhz and a signal amplitude of 50mv rms maximum. 6. maximum allowable relative shift equals 50mv. 7. all specifications valid for radiation dose 1e6 rads(si). 8. power does not include power contribution of any ttl output sink current. 9. power dissipation specified per switching output. 10. this value is guaranteed based on characterization data, but not tested. ac electrical characteristics 2 (v dd = 5.0v 10%; v ss = 0v 1 , -55 c < t c < +125 c) notes: 1. maximum allowable relative shift equals 50mv. 2. all specifications valid for radiation dose 1e6 rads(si). symbol parameter minimum maximum unit t phl input to yn 1 15 ns t plh input to yn 1 13 ns
37 radhard msi logic ut54acs34/ut54acts34 radiation-hardened hex noninverting buffers features ? radiation-hardened cmos - latchup immune ? high speed ? low power consumption ? single 5 volt supply ? available qml q or v processes ? flexible package - 14-pin dip - 14-lead flatpack description the ut54acs34 and the ut54acts34 are hex noninvertering buffers. the circuits perform the boolean functions y = a. the devices are characterized over full military temperature range of -55 c to +125 c. function table logic symbol pinouts 14-pin dip top view 14-lead flatpack top view logic diagram input output a y h h l l y1 y2 y3 y4 (1) a1 (5) a3 (11) a5 (13) a6 note: 1. logic symbol in accordance with ansi/ieee standard 91-1984 and iec publication 617-12. 1 (3) a2 (9) a4 (2) (6) (10) (12) (4) (8) y5 y6 1 2 3 4 5 7 6 14 13 12 11 10 8 9 a1 y1 a2 y2 a3 y3 v ss v dd a6 y6 a5 y5 a4 y4 1 2 3 4 5 7 6 14 13 12 11 10 8 9 v dd a6 y6 a5 y5 a4 y4 a1 y1 a2 y2 a3 y3 v ss y4 y3 y1 y2 y6 y5 a4 a3 a1 a2 a6 a5
radhard msi logic 38 ut54acs34/ut54acts34 radiation hardness specifications 1 notes: 1. logic will not latchup during radiation exposure within the limits defined in the table. 2. device storage elements are immune to seu affects. absolute maximum ratings note: 1. stresses outside the listed absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. exposure to absolute ma ximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter limit units total dose 1.0e6 rads(si) seu threshold 2 80 mev-cm 2 /mg sel threshold 120 mev-cm 2 /mg neutron fluence 1.0e14 n/cm 2 symbol parameter limit units v dd supply voltage -0.3 to 7.0 v v i/o voltage any pin -.3 to v dd +.3 v t stg storage temperature range -65 to +150 c t j maximum junction temperature +175 c t ls lead temperature (soldering 5 seconds) +300 c jc thermal resistance junction to case 20 c/w i i dc input current 10 ma p d maximum power dissipation 1 w symbol parameter limit units v dd supply voltage 4.5 to 5.5 v v in input voltage any pin 0 to v dd v t c temperature range -55 to + 125 c
39 radhard msi logic ut54acs34/ut54acts34 dc electrical characteristics 7 (v dd = 5.0v 10%; v ss = 0v 6 , -55 c < t c < +125 c) symbol parameter condition min max unit v il low-level input voltage 1 acts acs 0.8 .3v dd v v ih high-level input voltage 1 acts acs .5v dd .7v dd v i in input leakage current acts/acs v in = v dd or v ss -1 1 a v ol low-level output voltage 3 acts acs i ol = 8.0ma i ol = 100 a 0.40 0.25 v v oh high-level output voltage 3 acts acs i oh = -8.0ma i oh = -100 a .7v dd v dd - 0.25 v i os short-circuit output current 2 ,4 acts/acs v o = v dd and v ss -200 200 ma i ol output current 10 (sink) v in = v dd or v ss v ol = 0.4v 8 ma i oh output current 10 (source) v in = v dd or v ss v oh = v dd - 0.4v -8 ma p total power dissipation 2, 8, 9 c l = 50pf 1.8 mw/ mhz i ddq quiescent supply current v dd = 5.5v 10 a i ddq quiescent supply current delta acts for input under test v in = v dd - 2.1v for all other inputs v in = v dd or v ss v dd = 5.5v 1.6 ma c in input capacitance 5 = 1mhz @ 0v 15 pf c out output capacitance 5 = 1mhz @ 0v 15 pf
radhard msi logic 40 ut54acs34/ut54acts34 notes: 1. functional tests are conducted in accordance with mil-std-883 with the following input test conditions: v ih = v ih (min) + 20%, - 0%; v il = v il (max) + 0%, - 50%, as specified herein, for ttl, cmos, or schmitt compatible inputs. devices may be tested using any input voltage within th e above specified range, but are guaranteed to v ih (min) and v il (max). 2. supplied as a design limit but not guaranteed or tested. 3. per mil-prf-38535, for current density 5.0e5 amps/cm 2 , the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pf/mhz. 4. not more than one output may be shorted at a time for maximum duration of one second. 5. capacitance measured for initial qualification and when design changes may affect the value. capacitance is measured between the designated terminal and v ss at frequency of 1mhz and a signal amplitude of 50mv rms maximum. 6. maximum allowable relative shift equals 50mv. 7. all specifications valid for radiation dose 1e6 rads(si). 8. power does not include power contribution of any ttl output sink current. 9. power dissipation specified per switching output. 10. this value is guaranteed based on characterization data, but not tested. ac electrical characteristics 2 (v dd = 5.0v 10%; v ss = 0v 1 , -55 c < t c < +125 c) notes: 1. maximum allowable relative shift equals 50mv. 2. all specifications valid for radiation dose 1e6 rads(si). symbol parameter minimum maximum unit t phl input to yn 1 11 ns t plh input to yn 1 11 ns
41 radhard msi logic ut54acs54/ut54acts54 radiation-hardened 4-wide and-or-invert gates features ? 1.2 radiation-hardened cmos - latchup immune ? high speed ? low power consumption ? single 5 volt supply ? available qml q or v processes ? flexible package - 14-pin dip - 14-lead flatpack description the ut54acs54 and the ut54acts54 are 4-wide and-or- invert gates. the devices perform the boolean function: y = ab+cd+ef+gh the devices are characterized over full military temperature range of -55 c to +125 c. function table logic symbol pinouts 14-pin dip top view 14-lead flatpack top view logic diagram input output a b c d e f g h y h h x x x x x x l x x h h x x x x l x x x x h h x x l x x x x x x h h l l x l x l x l x h x l x l x l x l h (8) y (1) a (13) b (2) c (3) d (4) e (5) f (9) g (10) h note: 1. logic symbol in accordance with ansi/ieee standard 91-1984 and iec publication 617-12. > 1 & & & & 1 2 3 4 5 7 6 14 13 12 11 10 8 9 a c d e f nc v ss v dd b nc nc h g y 1 2 3 4 5 7 6 14 13 12 11 10 8 9 v dd b nc nc h g y a c d e f nc v ss h g f e a b y c d
radhard msi logic 42 ut54acs54/ut54acts54 radiation hardness specifications 1 notes: 1. logic will not latchup during radiation ex posure within the limits defined in the table. 2. device storage elements are immune to seu affects. absolute maximum ratings note: 1. stresses outside the listed absolute maximum ratings may cause permanent damage to the device . this is a stress rating only, functional operation of the device at these or any other cond itions beyond limits indicated in the operational sections is not recomm ended. exposure to absolute m aximum rating conditions for extended periods may affect device reliability. 2. pd = ts-tc/ jc. recommended operating conditions parameter limit units total dose 1.0e6 rads(si) seu threshold 2 80 mev-cm 2 /mg sel threshold 120 mev-cm 2 /mg neutron fluence 1.0e14 n/cm 2 symbol parameter limit units v dd supply voltage -0.3 to 7.0 v v i/o voltage any pin -.3 to v dd +.3 v t stg storage temperature range -65 to +150 c t j maximum junction temperature +175 c t ls lead temperature (soldering 5 seconds) +300 c jc thermal resistance junction to case 15.5 c/w i i dc input current 10 ma p d maximum power dissipation 3.2 w symbol parameter limit units v dd supply voltage 4.5 to 5.5 v v in input voltage any pin 0 to v dd v t c temperature range -55 to + 125 c
43 radhard msi logic ut54acs54/ut54acts54 dc electrical characteristics 7 (v dd = 5.0v 10%; v ss = 0v 6 , -55 c < t c < +125 c) symbol parameter condition min max unit v il low-level input voltage 1 acts acs 0.8 .3v dd v v ih high-level input voltage 1 acts acs .5v dd .7v dd v i in input leakage current acts/acs v in = v dd or v ss -1 1 a v ol low-level output voltage 3 acts acs i ol = 8.0ma i ol = 100 a 0.40 0.25 v v oh high-level output voltage 3 acts acs i oh = -8.0ma i oh = -100 a .7v dd v dd - 0.25 v i os short-circuit output current 2 ,4 acts/acs v o = v dd and v ss -200 200 ma p total power dissipation 2, 8, 9 c l = 50pf 2.0 mw/ mhz i ol output current 10 (sink) v in = v dd or v ss v ol = 0.4v 8 ma i oh output current 10 (source) v in = v dd or v ss v oh = v dd - 0.4v -8 ma i ddq quiescent supply current v dd = 5.5v 10 a i ddq quiescent supply current delta acts for input under test v in = v dd - 2.1v for all other inputs v in = v dd or v ss v dd = 5.5v 1.6 ma c in input capacitance 5 ? = 1mhz @ 0v 15 pf c out output capacitance 5 ? = 1mhz @ 0v 15 pf
radhard msi logic 44 ut54acs54/ut54acts54 notes: 1. functional tests are conducted in accordance with mi l-std-883 with the following input test conditions: v ih = v ih (min) + 20%, - 0%; v il = v il (max) + 0%, - 50%, as specified herein, for ttl, cmos, or schmitt compatible inputs. devices may be tested using any input voltage within t he above specified range, but are guaranteed to v ih (min) and v il (max). 2. supplied as a design limit bu t not guaranteed or tested. 3. per mil-prf-38535, for current density 5.0e5 amps/cm 2 , the maximum product of load capacitance (per ou tput buffer) times frequency should not exceed 3,765 pf/mhz. 4. not more than one output may be shorted at a time for maximum duration of one second. 5. capacitance measured for initial qualifica tion and when design changes may affect th e value. capacitance is measured betwee n the designated terminal and v ss at frequency of 1mhz and a signal amplitude of 50mv rms maximum. 6. maximum allowable relative shift equals 50mv. 7. all specifications valid for radiation dose 1e6 rads(si). 8. power does not include power contribution of any ttl output sink current. 9. power dissipation specified per switching output 10. this value is guaranteed based on characterization data, but not tested. ac electrical characteristics 2 (v dd = 5.0v 10%; v ss = 0v 1 , -55 c < t c < +125 c) notes: 1. maximum allowable relative shift equals 50mv. 2. all specifications valid for radiation dose 1e6 rads(si). symbol parameter minimum maximum unit t phl from any input to y output 1 16 ns t plh from any input to y output 1 13 ns
45 radhard msi logic ut54acs74/ut54acts74 radiation-hardened dual d flip-flops with clear & preset features ? 1.2 radiation-hardened cmos (acs74) and 0.6 m crh cmos process (acts74) - latchup immune ? high speed ? low power consumption ? single 5 volt supply ? available qml q or v processes ? flexible package - 14-pin dip (not available for the acts74) - 14-lead flatpack description the ut54acs74 and the ut54acts74 contain two indepen- dent d-type positive triggered flip-flops. a low level at the preset or clear inputs sets or resets the outputs regardless of the levels of the other inputs. wh en preset and clear are inactive (high), data at the d input meeting the setup time requirement is transferred to the outputs on the positive-going edge of the clock pulse. following the hold time interval, data at the d input may be changed without affecting the levels at the outputs. the devices are characterized over full military temperature range of -55 c to +125 c. function table note: 1. the output levels in this configura tion are not guaranteed to meet the mini- mum levels for v oh if the lows at preset and clear are near v il maximum. in addition, this configur ation is nonstable; that is, it will not persist when either preset or clear return s to its inactive (high) level. pinouts 14-pin dip top view 14-lead flatpack top view logic symbol inputs output pre clr clk d q q l h x x h l h l x x l h l l x x h 1 h 1 h h h h l h h l l h h h l x q o q o 1 2 3 4 5 7 6 14 13 12 11 10 8 9 clr1 d1 clk1 pre1 q1 q1 v ss v dd clr2 d2 clk2 pre2 q2 q2 1 2 3 4 5 7 6 14 13 12 11 10 8 9 v dd clr2 d2 clk2 pre2 q2 q2 clr1 d1 clk1 pre1 q1 q1 v ss q1 (5) (6) q1 q2 (9) (8) q2 (4) pre1 (3) clk1 (2) d1 (1) clr1 (10) pre2 (11) clk2 (12) d2 (13) clr2 note: 1. logic symbol in accordance with ansi/ieee standard 91-1984 and iec publication 617-12. s c1 d1 r
radhard msi logic 46 ut54acs74/ut54acts74 logic diagram pre clr clk q q d
47 radhard msi logic ut54acs74/ut54acts74 radiation hardness specifications 1 notes: 1. logic will not latchup during radiation ex posure within the limits defined in the table. 2. device storage elements are immune to seu affects. absolute maximum ratings note: 1. stresses outside the listed absolute maximum ratings may cause permanent damage to the device . this is a stress rating only, functional operation of the device at these or any other cond itions beyond limits indicated in the operational sections is not recomm ended. exposure to absolute m aximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter limit units total dose 1.0e6 rads(si) seu threshold 2 80 mev-cm 2 /mg sel threshold 120 mev-cm 2 /mg neutron fluence 1.0e14 n/cm 2 symbol parameter limit units v dd supply voltage -0.3 to 7.0 v v i/o voltage any pin -0.3 to v dd +0.3 v t stg storage temperature range -65 to +150 c t j maximum junction temperature +175 c t ls lead temperature (soldering 5 seconds) +300 c jc thermal resistance junction to case 20 c/w i i dc input current 10 ma p d maximum power dissipation 1 w symbol parameter limit units v dd supply voltage 4.5 to 5.5 v v in input voltage any pin 0 to v dd v t c temperature range -55 to + 125 c
radhard msi logic 48 ut54acs74/ut54acts74 dc electrical characteristics 7 (v dd = 5.0v 10%; v ss = 0v 6 , -55 c < t c < +125 c) symbol parameter condition min max unit v il low-level input voltage 1 acts acs 0.8 0.3v dd v v ih high-level input voltage 1 acts acs 0.5v dd 0.7v dd v i in input leakage current acts/acs v in = v dd or v ss -1 1 a v ol low-level output voltage 3 acts acs i ol = 8.0ma i ol = 100 a 0.40 0.25 v v oh high-level output voltage 3 acts acs i oh = -8.0ma i oh = -100 a 0.7v dd v dd - 0.25 v i os short-circuit output current 2 ,4 acts/acs v o = v dd and v ss -200 200 ma i ol output current 10 (sink) v in = v dd or v ss v ol = 0.4v 8 ma i oh output current 10 (source) v in = v dd or v ss v oh = v dd - 0.4v -8 ma p total power dissipation 2, 8, 9 c l = 50pf 1.9 mw/mhz i ddq quiescent supply current v dd = 5.5v 10 a i ddq quiescent supply current delta acts for input under test v in = v dd - 2.1v for all other inputs v in = v dd or v ss v dd = 5.5v 1.6 ma c in input capacitance 5 ? = 1mhz @ 0v 15 pf c out output capacitance 5 ? = 1mhz @ 0v 15 pf
49 radhard msi logic ut54acs74/ut54acts74 notes: 1. functional tests are conducted in accordance with mi l-std-883 with the following input test conditions: v ih = v ih (min) + 20%, - 0%; v il = v il (max) + 0%, - 50%, as specified herein, for ttl, cmos, or schmitt compatible inputs. devices may be tested using any input voltage within t he above specified range, but are guaranteed to v ih (min) and v il (max). 2. supplied as a design limit bu t not guaranteed or tested. 3. per mil-prf-38535, for current density 5.0e5 amps/cm 2 , the maximum product of load capacitance (per ou tput buffer) times frequency should not exceed 3,765 pf/mhz. 4. not more than one output may be shorted at a time for maximum duration of one second. 5. capacitance measured for initial qualifi cation and when design changes may affect the value. capacitance is measured between the designated terminal and v ss at a frequency of 1mhz and a sign al amplitude of 50mv rms maximum. 6. maximum allowable relative shift equals 50mv. 7. all specifications valid for radiation dose 1e6 rads(si). 8. power does not include power contribution of any ttl output sink current. 9. power dissipation specified per switching output. 10. this value is guaranteed based on characterization data, but not tested.
radhard msi logic 50 ut54acs74/ut54acts74 ac electrical characteristics 2 (v dd = 5.0v 10%; v ss = 0v 1 , -55 c < t c < +125 c) notes: 1. maximum allowable relative shift equals 50mv. 2. all specifications valid for radiation dose 1e6 rads(si). 3. based on characterization, hold time (t h ) of 0ns can be assumed if data setup time (t su2 ) is > 10ns. this is guaranteed, but not tested. symbol parameter minimum maximum unit t phl clk to q, q 3 21 ns t plh clk to q, q 1 20 ns t plh pre to q 1 15 ns t phl pre to q 3 19 ns t phl clr to q 3 19 ns t plh clr to q 1 15 ns f max maximum clock frequency 71 mhz t su1 pre or clr inactive setup time before clk 5 ns t su2 data setup time before clk 5 ns t h 3 data hold time after clk 2 ns t w minimum pulse width pre or clr low clk high clk low 7 ns
51 radhard msi logic ut54acs85/ut54acts85 radiation-hardened 4-bit comparators features radiation-hardened cmos - latchup immune high speed low power consumption single 5 volt supply available qml q or v processes flexible package - 16-pin dip - 16-lead flatpack description the ut54acs85 and the ut54acts85 are 4-bit magnitude comparators that perform comparison of straight binary and straight bcd (8-4-2-1) codes. three fully decoded decisions about two 4-bit words (a, b) are made and are externally avail- able at three outputs. devices are fully expandable to any num- ber of bits without external gates. the cascading paths of the devices are implemented with only a two-gate-level delay to reduce overall comparison times for long words. an alternate method of cascading which further reduces the comparison time is shown in the typical application data. the devices are characterized over full military temperature range of -55 c to +125 c. logic symbol pinouts 16-pin dip top view 16-lead flatpack top view (5) (a>b)out (10) a0 (12) a1 (13) a2 0 (6) (a=b)out (7) (a a (15) a3 (2) (ab)in (9) b0 (11) b1 (14) b2 (1) b3 3 < = > 0 b 3 note: 1. logic symbol in accordance with ansi/ieee standard 91-1984 and iec publication 617-12. 1 2 3 4 5 7 6 16 15 14 13 12 10 11 b3 (ab)in (a>b)out (a=b)out (ab)in (a>b)out (a=b)out (a radhard msi logic 52 ut54acs85/ut54acts85 function table logic diagram comparing inputs cascading inputs outputs a3, b3 a2, b2 a1, b1 a0, b0 a>b ab ab3 x x x x x x h l l a3b2 x x x x x h l l a3=b3 a2b1 x x x x h l l a3=b3 a2=b2 a1b0 x x x h l l a3=b3 a2=b2 a1=b1 a0b a=b ab a1 b1 a0 b0 (6) (5) (15) (1) (13) (14) (2) (3) (4) (12) (11) (10) (9)
53 radhard msi logic ut54acs85/ut54acts85 radiation hardness specifications 1 notes: 1. logic will not latchup during radiation exposure within the limits defined in the table. 2. device storage elements are immune to seu affects. absolute maximum ratings note: 1. stresses outside the listed absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. exposure to absolute ma ximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter limit units total dose 1.0e6 rads(si) seu threshold 2 80 mev-cm 2 /mg sel threshold 120 mev-cm 2 /mg neutron fluence 1.0e14 n/cm 2 symbol parameter limit units v dd supply voltage -0.3 to 7.0 v v i/o voltage any pin -.3 to v dd +.3 v t stg storage temperature range -65 to +150 c t j maximum junction temperature +175 c t ls lead temperature (soldering 5 seconds) +300 c jc thermal resistance junction to case 20 c/w i i dc input current 10 ma p d maximum power dissipation 1 w symbol parameter limit units v dd supply voltage 4.5 to 5.5 v v in input voltage any pin 0 to v dd v t c temperature range -55 to + 125 c
radhard msi logic 54 ut54acs85/ut54acts85 dc electrical characteristics 7 (v dd = 5.0v 10%; v ss = 0v 6 , -55 c < t c < +125 c) symbol parameter condition min max unit v il low-level input voltage 1 acts acs 0.8 .3v dd v v ih high-level input voltage 1 acts acs .5v dd .7v dd v i in input leakage current acts/acs v in = v dd or v ss -1 1 a v ol low-level output voltage 3 acts acs i ol = 8.0ma i ol = 100 a 0.40 0.25 v v oh high-level output voltage 3 acts acs i oh = -8.0ma i oh = -100 a .7v dd v dd - 0.25 v i os short-circuit output current 2 ,4 acts/acs v o = v dd and v ss -200 200 ma i ol output current 10 (sink) v in = v dd or v ss v ol = 0.4v 8 ma i oh output current 10 (source) v in = v dd or v ss v oh = v dd - 0.4v -8 ma p total power dissipation 2, 8, 9 c l = 50pf 2.3 mw/ mhz i ddq quiescent supply current v dd = 5.5v 10 a i ddq quiescent supply current delta acts for input under test v in = v dd - 2.1v for all other inputs v in = v dd or v ss v dd = 5.5v 1.6 ma c in input capacitance 5 = 1mhz @ 0v 15 pf c out output capacitance 5 = 1mhz @ 0v 15 pf
55 radhard msi logic ut54acs85/ut54acts85 notes: 1. functional tests are conducted in accordance with mil-std-883 with the following input test conditions: v ih = v ih (min) + 20%, - 0%; v il = v il (max) + 0%, - 50%, as specified herein, for ttl, cmos, or schmitt compatible inputs. devices may be tested using any input voltage within th e above specified range, but are guaranteed to v ih (min) and v il (max). 2. supplied as a design limit but not guaranteed or tested. 3. per mil-prf-38535, for current density 5.0e5 amps/cm 2 , the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pf/mhz. 4. not more than one output may be shorted at a time for maximum duration of one second. 5. capacitance measured for initial qualification and when design changes may affect the value. capacitance is measured between the designated terminal and v ss at frequency of 1mhz and a signal amplitude of 50mv rms maximum 7. all specifications valid for radiation dose 1e6 rads(si). 6. maximum allowable relative shift equals 50mv. 8. power does not include power contribution of any ttl output sink current. 9. power dissipation specified per switching output. 10. this value is guaranteed based on characterization data, but not tested.
radhard msi logic 56 ut54acs85/ut54acts85 ac electrical characteristics 2 (v dd = 5.0v 10%; v ss = 0v 1 , -55 c < t c < +125 c) notes: 1. maximum allowable relative shift equals 50mv. 2. all specifications valid for radiation dose 1e6 rads(si) symbol parameter minimum maximum unit t phl an, bn to (ab) out 2 18 ns t plh an, bn to (a>b) out 2 16 ns t phl (ab) out 2 17 ns t plh (ab) out 2 15 ns t phl (a=b) in to (a=b) out 2 13 ns t plh (a=b) in to (a=b) out 1 15 ns t phl (a>b) in , (a=b) in to (ab) in , (a=b) in to (a 57 radhard msi logic ut54acs86/ut54acts86 radiation-hardened quadruple 2-input exclusive or gates features ? radiation-hardened cmos - latchup immune ? high speed ? low power consumption ? single 5 volt supply ? available qml q or v processes ? flexible package - 14-pin dip - 14-lead flatpack description the ut54acs86 and the ut54acts86 are quadruple 2-input exclusive or gates. the devices perform the boolean function y = a b = a b + a b in positive logic. an application is as a true/complement element. if one of the inputs is low, the other input will be reproduced in true form at the output. if one of the inputs is high, the signal on the other input will be reproduced inverted at the output. the devices are characterized over full military temperature range of -55 c to +125 c. function table logic symbol pinouts 14-pin dip top view 14-lead flatpack top view logic diagram inputs output a b y l l l l h h h l h h h l y1 (3) (6) y2 y3 (8) (11) y4 (1) a1 (2) b1 (4) a2 (5) b2 (9) a3 (10) b3 (12) a4 (13) b4 note: 1. logic symbol in accordance with ansi/ieee standard 91-1984 and iec publication 617-12. =1 a1 b1 y1 a2 b2 y2 v ss v dd b4 a4 y4 b3 a3 y3 1 14 2 13 3 12 4 11 5 10 6 9 7 8 v dd b4 a4 y4 b3 a3 y3 a1 b1 y1 a2 b2 y2 v ss 1 14 2 13 3 12 4 11 5 10 6 9 7 8 b4 a4 y4 b3 a3 y3 b2 a2 y2 b1 a1 y1
rad-ard msi logic 58 ut54acs86/ut54acts86 radiation hardness specifications 1 notes: 1. logic will not latchup during radiation exposure within the limits defined in the table. 2. device storage elements are immune to seu affects. absolute maximum ratings note: 1. stresses outside the listed absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. exposure to absolute ma ximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter limit units total dose 1.0e6 rads(si) seu threshold 2 80 mev-cm 2 /mg sel threshold 120 mev-cm 2 /mg neutron fluence 1.0e14 n/cm 2 symbol parameter limit units v dd supply voltage -0.3 to 7.0 v v i/o voltage any pin -.3 to v dd +.3 v t stg storage temperature range -65 to +150 c t j maximum junction temperature +175 c t ls lead temperature (soldering 5 seconds) +300 c jc thermal resistance junction to case 20 c/w i i dc input current 10 ma p d maximum power dissipation 1 w symbol parameter limit units v dd supply voltage 4.5 to 5.5 v v in input voltage any pin 0 to v dd v t c temperature range -55 to + 125 c
59 radhard msi logic ut54acs86/ut54acts86 dc electrical characteristics 7 (v dd = 5.0v 10%; v ss = 0v 6 , -55 c < t c < +125 c) symbol parameter condition min max unit v il low-level input voltage 1 acts acs 0.8 .3v dd v v ih high-level input voltage 1 acts acs .5v dd .7v dd v i in input leakage current acts/acs v in = v dd or v ss -1 1 a v ol low-level output voltage 3 acts acs i ol = 8.0ma i ol = 100 a 0.40 0.25 v v oh high-level output voltage 3 acts acs i oh = -8.0ma i oh = -100 a .7v dd v dd - 0.25 v i os short-circuit output current 2 ,4 acts/acs v o = v dd and v ss -200 200 ma i ol output current 10 (sink) v in = v dd or v ss v ol = 0.4v 8 ma i oh output current 10 (source) v in = v dd or v ss v oh = v dd - 0.4v -8 ma p total power dissipation 2, 8, 9 c l = 50pf 1.8 mw/ mhz i ddq quiescent supply current v dd = 5.5v 10 a i ddq quiescent supply current delta acts for input under test v in = v dd - 2.1v for all other inputs v in = v dd or v ss v dd = 5.5v 1.6 ma c in input capacitance 5 = 1mhz @ 0v 15 pf c out output capacitance 5 = 1mhz @ 0v 15 pf
rad-ard msi logic 60 ut54acs86/ut54acts86 notes: 1. functional tests are conducted in accordance with mil-std-883 with the following input test conditions: v ih = v ih (min) + 20%, - 0%; v il = v il (max) + 0%, - 50%, as specified herein, for ttl, cmos, or schmitt compatible inputs. devices may be tested using any input voltage within th e above specified range, but are guaranteed to v ih (min) and v il (max). 2. supplied as a design limit but not guaranteed or tested. 3. per mil-prf-38535, for current density 5.0e5 amps/cm 2 , the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pf/mhz. 4. not more than one output may be shorted at a time for maximum duration of one second. 5. capacitance measured for initial qualification and when design changes may affect the value. capacitance is measured between the designated terminal and v ss at frequency of 1mhz and a signal amplitude of 50mv rms maximum. 6. maximum allowable relative shift equals 50mv. 7. all specifications valid for radiation dose 1e6 rads(si). 8. power does not include power contribution of any ttl output sink current. 9. power dissipation specified per switching output. 10. this value is guaranteed based on characterization data, but not tested. ac electrical characteristics 2 (v dd = 5.0v 10%; v ss = 0v 1 , -55 c < t c < +125 c) notes: 1. maximum allowable relative shift equals 50mv. 2. all specifications valid for radiation dose 1e6 rads(si). symbol parameter minimum maximum unit t phl data to input 1 14 ns t plh data to input 1 13 ns
61 radhard msi logic ut54acs109/ut54acts109 radiation-hardened dual j-k flip-flops dec. 1, 2003 features ? 1.2 radiation-hardened cmos (acts109) and 0.6 crh cmos process (acs109) - latchup immune ? high speed ? low power consumption ? single 5 volt supply ? available qml q or v processes ? flexible package - 16-pin dip (not available for acs109) - 16-lead flatpack description the ut54acs109 and the ut54acts109 are dual j-k posi- tive triggered flip-flops. a low le vel at the preset or clear inputs sets or resets the outputs regardless of the other input levels. when preset and clear are inactiv e (high), data at the j and k input meeting the setup time requi rements are transferred to the outputs on the positive-going edge of the clock pulse. following the hold time interval, data at the j and k input can be changed without affecting the levels at the outputs. the flip-flops can perform as toggle flip-flops by grounding k and tying j high. they also can perform as d flip-flops if j and k are tied together. the devices are characterized over full military temperature range of -55 c to +125 c. function table note: 1. the output levels in this configura tion are not guaranteed to meet the mini- mum levels for v oh if the lows at preset and clear are near v il maximum. in addition, this configuration is nonstable; that is, it will not persist when either preset or clear returns to its inactive (high) level. pinouts 16-pin dip top view 16-lead flatpack top view logic symbol inputs output pre clr clk j k q q l h x x x h l h l x x x l h l l x x x h 1 h 1 h h l l l h h h h l toggle h h l h no change h h h h h l h h l x x no change 1 2 3 4 5 7 6 16 15 14 13 12 10 11 clr1 j k1 clk1 pre1 q1 v dd clr2 j2 k2 clk2 pre2 q2 8 9 v ss q2 q1 1 2 3 4 5 7 6 16 15 14 13 12 10 11 clr1 j1 k1 clk1 pre1 q1 v ss q1 89 v dd clr2 j2 k2 clk2 pre2 q2 q2 q1 (6) (7) q1 q2 (10) (9) q2 (5) pre1 (4) clk1 (1) clr1 (11) pre2 (14) j2 (12) clk2 (13) k2 note: 1. logic symbol in accordance with ansi/ieee standard 91-1984 and iec publication 617-12. s c1 r (2) j1 j1 (3) k1 k1 (15) clr2
radhard msi logic 62 ut54acs109/ut54acts109 logic diagram radiation hardness specifications 1 notes: 1. logic will not latchup during radiation ex posure within the limits defined in the table. 2. device storage elements are immune to seu affects. absolute maximum ratings note: 1. stresses outside the listed absolute maximum ratings may cause permanent damage to the device . this is a stress rating only, functional operation of the device at these or any other cond itions beyond limits indicated in the operational sections is not recomm ended. exposure to absolute m aximum rating conditions for extended periods may affect device reliability. parameter limit units total dose 1.0e6 (acts109) 5.0e5 (acs109) rads(si) seu threshold 2 80 mev-cm 2 /mg sel threshold 120 mev-cm 2 /mg neutron fluence 1.0e14 n/cm 2 pre q clr q k clk j symbol parameter limit units v dd supply voltage -0.3 to 7.0 v v i/o voltage any pin -.3 to v dd +.3 v t stg storage temperature range -65 to +150 c t j maximum junction temperature +175 c t ls lead temperature (soldering 5 seconds) +300 c jc thermal resistance junction to case 20 c/w i i dc input current 10 ma p d maximum power dissipation 1 w
63 radhard msi logic ut54acs109/ut54acts109 recommended operating conditions symbol parameter limit units v dd supply voltage 4.5 to 5.5 v v in input voltage any pin 0 to v dd v t c temperature range -55 to + 125 c
radhard msi logic 64 ut54acs109/ut54acts109 dc electrical characteristics 7 (v dd = 5.0v 10%; v ss = 0v 6 , -55 c < t c < +125 c) symbol parameter condition min max unit v il low-level input voltage 1 acts acs 0.8 .3v dd v v ih high-level input voltage 1 acts acs .5v dd .7v dd v i in input leakage current acts/acs v in = v dd or v ss -1 1 a v ol low-level output voltage 3 acts acs i ol = 8.0ma i ol = 100 a 0.40 0.25 v v oh high-level output voltage 3 acts acs i oh = -8.0ma i oh = -100 a .7v dd v dd - 0.25 v i os short-circuit output current 2 ,4 acts/acs v o = v dd and v ss -200 200 ma i ol output current 10 (sink) v in = v dd or v ss v ol = 0.4v 8 ma i oh output current 10 (source) v in = v dd or v ss v oh = v dd - 0.4v -8 ma p total power dissipation 2, 8 ,9 c l = 50pf 2.0 mw/ mhz i ddq quiescent supply current v dd = 5.5v 10 a ? i ddq quiescent supply current delta acts for input under test v in = v dd - 2.1v for all other inputs v in = v dd or v ss v dd = 5.5v 1.6 ma c in input capacitance 5 ? = 1mhz @ 0v 15 pf c out output capacitance 5 ? = 1mhz @ 0v 15 pf
65 radhard msi logic ut54acs109/ut54acts109 notes: 1. functional tests are conducted in accordance with mi l-std-883 with the following input test conditions: v ih = v ih (min) + 20%, - 0%; v il = v il (max) + 0%, - 50%, as specified herein, for ttl, cmos, or schmitt compatible inputs. devices may be tested using any input voltage within t he above specified range, but are guaranteed to v ih (min) and v il (max). 2. supplied as a design limit bu t not guaranteed or tested. 3. per mil-prf-38535, for current density 5.0e5 amps/cm 2 , the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pf/mhz. 4. not more than one output may be shorted at a time for maximum duration of one second. 5. capacitance measured for initial qualifi cation and when design changes may affect the value. capacitance is measured between the designated terminal and v ss at frequency of 1mhz and a signal amplitude of 50mv rms maximum. 6. maximum allowable relative shift equals 50mv. 7. all acts specifications are valid for radiation dose < 1e6 rads(si), and all acs specifications are valid for radiation dose < 5e5 rads(si). 8. power does not include power contribution of any ttl output sink current. 9. power dissipation specified per switching output. 10. this value is guaranteed based on characterization data, but not tested.
radhard msi logic 66 ut54acs109/ut54acts109 ac electrical characteristics 2 (v dd = 5.0v 10%; v ss = 0v 1 , -55 c < t c < +125 c) notes: 1. maximum allowable relative shift equals 50mv. 2. for the acts version, all specifi cations are valid for radiation dose < 1e6 rads(si). for the acs version, all sp ecifications are valid for radiation dose < 5e5 rads(si). 3. based on characterization, hold time (t h ) of 0ns can be assumed if data setup time (t su2 ) is > 10ns. this is guaranteed, but not tested. symbol parameter minimum maximum unit t phl clk to q, q 5 27 ns t plh clk to q, q 4 23 ns t plh pre to q 1 16 ns t phl pre to q 1 19 ns t phl clr to q 2 19 ns t plh clr to q 2 16 ns f max maximum clock frequency 62 mhz t su1 pre or clr inactive setup time before clk 5 ns t su2 data setup time before clk 5 ns t h 3 data hold time after clk 3 ns t w minimum pulse width pre or clr low clk high clk low 8 ns
67 radhard msi logic ut54acs132/ut54acts132 radiation-hardened quadruple 2-input nand schmitt triggers dec. 1, 2003 features ? 1.2 radiation-hardened cmos (acts 132) and 0.6 crh cmos process (acs132) - latchup immune ? high speed ? low power consumption ? single 5 volt supply ? available qml q or v processes ? flexible package - 14-pin dip (not available for the acs132) - 14-lead flatpack description the ut54acs132 and the ut54acts132 are 2-input nand gates with schmitt trigger input levels. a high applied on both the inputs forces the output to a low state. the devices are characterized over full military temperature range of -55 c to +125 c. function table logic symbol pinouts 14-pin dip top view 14-lead flatpack top view logic diagram inputs output an bn yn l l h l h h h l h h h l y1 (3) (6) y2 y3 (8) (11) y4 (1) a1 (2) b1 (4) a2 (5) b2 (9) a3 (10) b3 (12) a4 (13) b4 note: 1. logic symbol in accordance with ansi/ieee standard 91-1984 and iec publication 617-12. & a1 b1 y1 a2 b2 y2 v ss v dd b4 a4 y4 b3 a3 y3 114 213 312 411 510 69 78 v dd b4 a4 y4 b3 a3 y3 a1 b1 y1 a2 b2 y2 v ss 114 213 312 411 510 69 78 b4 a4 y4 b3 a3 y3 a1 b1 y1 a2 b2 y2
radhard msi logic 68 ut54acs132/ut54acts132 radiation hardness specifications 1 notes: 1. logic will not latchup during radiation ex posure within the limits defined in the table. 2. device storage elements are immune to seu affects. absolute maximum ratings note: 1. stresses outside the listed absolute maximum ratings may cause permanent damage to the device . this is a stress rating only, functional operation of the device at these or any other cond itions beyond limits indicated in the operational sections is not recomm ended. exposure to absolute m aximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter limit units total dose 1.0e6 (acts132) 5.0e5 (acs132) rads(si) seu threshold 2 80 mev-cm 2 /mg sel threshold 120 mev-cm 2 /mg neutron fluence 1.0e14 n/cm 2 symbol parameter limit units v dd supply voltage -0.3 to 7.0 v v i/o voltage any pin -.3 to v dd +.3 v t stg storage temperature range -65 to +150 c t j maximum junction temperature +175 c t ls lead temperature (soldering 5 seconds) +300 c jc thermal resistance junction to case 20 c/w i i dc input current 10 ma p d maximum power dissipation 1 w symbol parameter limit units v dd supply voltage 4.5 to 5.5 v v in input voltage any pin 0 to v dd v t c temperature range -55 to + 125 c
69 radhard msi logic ut54acs132/ut54acts132 dc electrical characteristics 7 (v dd = 5.0v 10%; v ss = 0v 6 , -55 c < t c < +125 c) symbol parameter condition min max unit v t + schmitt trigger, positive going 1 threshold acts acs 2.25 .7v dd v v t - schmitt trigger, negative going 1 threshold acts acs 0.5 .3v dd v v h schmitt trigger, typical range of hysteresis 2 acts acs 0.3 0.6 0.9 1.5 v i in input leakage current acts/acs v in = v dd or v ss -1 1 a v ol low-level output voltage 3 acts acs i ol = 8.0ma i ol = 100 a 0.40 0.25 v v oh high-level output voltage 3 acts acs i oh = -8.0ma i oh = -100 a .7v dd v dd - 0.25 v i os short-circuit output current 2 ,4 acts/acs v o = v dd and v ss -200 200 ma i ol output current 10 (sink) v in = v dd or v ss v ol = 0.4v 8 ma i oh output current 10 (source) v in = v dd or v ss v oh = v dd - 0.4v -8 ma p total power dissipation 2, 8, 9 c l = 50pf 1.9 mw/ mhz i ddq quiescent supply current v dd = 5.5v 10 a ? i ddq quiescent supply current delta acts for input under test v in = v dd - 2.1v for all other inputs v in = v dd or v ss v dd = 5.5v 3.1 ma c in input capacitance 5 ? = 1mhz @ 0v 15 pf c out output capacitance 5 ? = 1mhz @ 0v 15 pf
radhard msi logic 70 ut54acs132/ut54acts132 notes: 1. functional tests are conducted in accordance with mi l-std-883 with the following input test conditions: v ih = v ih (min) + 20%, - 0%; v il = v il (max) + 0%, - 50%, as specified herein, for ttl, cmos, or schmitt compatible inputs. devices may be tested using any input voltage within t he above specified range, but are guaranteed to v ih (min) and v il (max). 2. supplied as a design limit bu t not guaranteed or tested. 3. per mil-prf-38535, for current density 5.0e5 amps/cm 2 , the maximum product of load capacitance (per ou tput buffer) times frequency should not exceed 3,765 pf/mhz. 4. not more than one output may be shorted at a time for maximum duration of one second. 5. capacitance measured for initial qualifi cation and when design changes may affect the value. capacitance is measured between the designated terminal and v ss at frequency of 1mhz and a signal amplitude of 50mv rms maximum. 6. maximum allowable relative shift equals 50mv. 7. all acts specifications are valid for radiation dose < 1e6 rads(si), and all acs specifications are valid for radiation dose < 5e5 rads(si). 8. power does not include power contribution of any ttl output sink current. 9. power dissipation specified per switching output. 10. this value is guaranteed based on characterization data, but not tested. ac electrical characteristics 2 (v dd = 5.0v 10%; v ss = 0v 1 , -55 c < t c < +125 c) notes: 1. maximum allowable relative shift equals 50mv. 2. for the acts version, all specifi cations are valid for radiation dose < 1e6 rads(si). for the acs version, all sp ecifications are valid for radiation dose < 5e5 rads(si). symbol parameter minimum maximum unit t phl input to yn 2 15 ns t plh input to yn 2 12 ns
71 radhard msi logic ut54acs138/ut54acts138 radiation-hardened 3-line to 8-line decoders/demultiplexers features ? radiation-hardened cmos - latchup immune ? high speed ? low power consumption ? single 5 volt supply ? available qml q or v processes ? flexible package - 16-pin dip - 16-lead flatpack description the ut54acs138 and the ut54acts138 3-line to 8-line de- coders/demultiplexers are designed to be used in high-perfor- mance memory-decoding or data-routing applications requiring very short propagation delay times. the conditions at the binary select inputs and the three enable inputs select one of eight output lines. two active-low and one active-high enable inputs reduce the need for external gates of inverters when expanding. a 24-line decoder can be implement- ed without external inverters and a 32-line decoder requires only one inverter. an enable input can be used as a data input for demultiplexing applications. the devices are characterized over full military temperature range of -55 c to +125 c. pinouts 16-pin dip top view 16-lead flatpack top view function table 1 2 3 4 5 7 6 16 15 14 13 12 10 11 a b c g2a g2b g1 y7 v dd y0 y1 y2 y3 y4 y5 8 9 v ss y6 1 2 3 4 5 7 6 16 15 14 13 12 10 11 v dd a b c g2a g2b g1 y7 y0 y1 y2 y3 y4 y5 v ss y6 8 9 enable inputs select inputs output g1 g2a g2b c b a y0 y1 y2 y3 y4 y5 y6 y7 x x h x x x h h h h h h h h l x x x x x h h h h h h h h x h x x x x h h h h h h h h h l l l l l l h h h h h h h h l l l l h h l h h h h h h h l l l h l h h l h h h h h h l l l h h h h h l h h h h h l l h l l h h h h l h h h h l l h l h h h h h h l h h h l l h h l h h h h h h l h h l l h h h h h h h h h h l
radhard msi logic 72 ut54acs138/ut54acts138 logic symbol logic diagram (7) y7 (1) a (2) b (3) c (6) g1 (4) g2a (5) g2b 2 4 1 (9) y6 (10) y5 (11) y4 (12) y3 (13) y2 (14) y1 (15) y0 bin/oct en & 1 2 0 4 5 3 6 7 (7) y7 (1) a (2) b (3) c (6) g1 (4) g2a (5) g2b 2 4 1 (9) y6 (10) y5 (11) y4 (12) y3 (13) y2 (14) y1 (15) y0 dmux en & 1 2 0 4 5 3 6 7 note: 1. logic symbols in accordance with ansi/ieee standard 91-1984 and iec publication 617-12. g 0 7 --- y0 y1 y2 y3 y4 y5 y6 y7 data select enable (15) (14) (13) (12) (11) (10) (9) (7) (3) (2) (1) a b c (6) (4) (5) g1 g2a g2b
73 radhard msi logic ut54acs138/ut54acts138 radiation hardness specifications 1 notes: 1. logic will not latchup during radiation exposure within the limits defined in the table. 2. device storage elements are immune to seu affects. absolute maximum ratings note: 1. stresses outside the listed absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. exposure to absolute ma ximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter limit units total dose 1.0e6 rads(si) seu threshold 2 80 mev-cm 2 /mg sel threshold 120 mev-cm 2 /mg neutron fluence 1.0e14 n/cm 2 symbol parameter limit units v dd supply voltage -0.3 to 7.0 v v i/o voltage any pin -.3 to v dd +.3 v t stg storage temperature range -65 to +150 c t j maximum junction temperature +175 c t ls lead temperature (soldering 5 seconds) +300 c jc thermal resistance junction to case 20 c/w i i dc input current 10 ma p d maximum power dissipation 1 w symbol parameter limit units v dd supply voltage 4.5 to 5.5 v v in input voltage any pin 0 to v dd v t c temperature range -55 to + 125 c
radhard msi logic 74 ut54acs138/ut54acts138 dc electrical characteristics 7 (v dd = 5.0v 10%; v ss = 0v 6 , -55 c < t c < +125 c) symbol parameter condition min max unit v il low-level input voltage 1 acts acs 0.8 .3v dd v v ih high-level input voltage 1 acts acs .5v dd .7v dd v i in input leakage current acts/acs v in = v dd or v ss -1 1 a v ol low-level output voltage 3 acts acs i ol = 8.0ma i ol = 100 a 0.40 0.25 v v oh high-level output voltage 3 acts acs i oh = -8.0ma i oh = -100 a .7v dd v dd - 0.25 v i os short-circuit output current 2 ,4 acts/acs v o = v dd and v ss -200 200 ma i ol output current 10 (sink) v in = v dd or v ss v ol = 0.4v 8 ma i oh output current 10 (source) v in = v dd or v ss v oh = v dd - 0.4v -8 ma p total power dissipation 2, 8, 9 c l = 50pf 1.9 mw/ mhz i ddq quiescent supply current v dd = 5.5v 10 a i ddq quiescent supply current delta acts for input under test v in = v dd - 2.1v for all other inputs v in = v dd or v ss v dd = 5.5v 1.6 ma c in input capacitance 5 = 1mhz @ 0v 15 pf c out output capacitance 5 = 1mhz @ 0v 15 pf
75 radhard msi logic ut54acs138/ut54acts138 notes: 1. functional tests are conducted in accordance with mil-std-883 with the following input test conditions: v ih = v ih (min) + 20%, - 0%; v il = v il (max) + 0%, - 50%, as specified herein, for ttl, cmos, or schmitt compatible inputs. devices may be tested using any input voltage within th e above specified range, but are guaranteed to v ih (min) and v il (max). 2. supplied as a design limit but not guaranteed or tested. 3. per mil-prf-38535, for current density 5.0e5 amps/cm 2 , the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pf/mhz. 4. not more than one output may be shorted at a time for maximum duration of one second. 5. capacitance measured for initial qualification and when design changes may affect the value. capacitance is measured between the designated terminal and v ss at frequency of 1mhz and a signal amplitude of 50mv rms maximum. 6. maximum allowable relative shift equals 50mv. 7. all specifications valid for radiation dose 1e6 rads(si). 8. power does not include power contribution of any ttl output sink current. 9. power dissipation specified per switching output. 10. this value is guaranteed based on characterization data, but not tested.
radhard msi logic 76 ut54acs138/ut54acts138 ac electrical characteristics 2 (v dd = 5.0v 10%; v ss = 0v 1 , -55 c < t c < +125 c) notes: 1. maximum allowable relative shift equals 50mv. 2. all specifications valid for radiation dose 1e6 rads(si). symbol parameter minimum maximum unit t phl binary select to output yn 2 15 ns t plh binary select to output yn 2 15 ns t phl enable to output yn 2 17 ns t plh enable to output yn 2 14 ns
77 radhard msi logic ut54acs139/ut54acts139 radiation-hardened features radiation-hardened cmos - latchup immune ? high speed ? low power consumption ? single 5 volt supply ? available qml q or v processes ? flexible package - 16-pin dip - 16-lead flatpack description the ut54acs139 and the ut54acts139 are designed to be used in high-performance memory-decoding or data-routing ap- plications requiring very short propagation delay times. the devices consist of two individual two-line to four-line de- coders in a single package. the active-low enable input can be used as a data line in demultiplexing applications. the devices are characterized over full military temperature range of -55 c to +125 c. function table pinouts 16-pin dip top view 16-lead flatpack top view logic diagram enable inputs select inputs output g b a y0 y1 y2 y3 h x x h h h h l l l l h h h l l h h l h h l h l h h l h l h h h h h l 1 2 3 4 5 7 6 16 15 14 13 12 10 11 ig 1a 1b 1 y0 1 y1 1 y2 1 y3 v dd 2g 2a 2b 2 y0 2 y1 2 y2 8 9 v ss 2 y3 1 2 3 4 5 7 6 16 15 14 13 12 10 11 v dd 1g 1a 1b 1 y0 1 y1 1 y2 1 y3 2g 2a 2b 2 y0 2 y1 2 y2 v ss 2 y3 8 9 1 y0 1 y1 1 y2 1 y3 d a t a (4) (5) (6) (7) (1) (2) (3) 1g 1b select 2 y0 2 y1 2 y2 2 y3 (12) (11) (10) (9) (15) (14) (13) 2g 2b select 1a 2a
radhard msi logic 78 ut54acs139/ut54acts139 logic symbol radiation hardness specifications 1 notes: 1. logic will not latchup during radiation exposure within the limits defined in the table. 2. device storage elements are immune to seu affects. absolute maximum ratings note: 1. stresses outside the listed absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. exposure to absolute ma ximum rating conditions for extended periods may affect device reliability. parameter limit units total dose 1.0e6 rads(si) seu threshold 2 80 mev-cm 2 /mg sel threshold 120 mev-cm 2 /mg neutron fluence 1.0e14 n/cm 2 (9) 2 y3 (2) 1a (3) 1b (1) 1g (14) 2a (13) 2b (15) 2g 2 1 (10) 2 y2 (11) 2 y1 (12) 2 y0 (7) 1 y3 (6) 1 y2 (5) 1 y1 (4) 1 y0 x/y en 1 2 0 3 (2) 1a (3) 1b (1) 1g (14) 2a (13) 2b (15) 2g 1 0 dmux 1 2 0 3 (9) 2 y3 (10) 2 y2 (11) 2 y1 (12) 2 y0 (7) 1 y3 (6) 1 y2 (5) 1 y1 (4) 1 y0 note: 1. logic symbols in accordance with ansi/ieee std 91-1984 and iec publication 617-12. g 0 3 --- symbol parameter limit units v dd supply voltage -0.3 to 7.0 v v i/o voltage any pin -.3 to v dd +.3 v t stg storage temperature range -65 to +150 c t j maximum junction temperature +175 c t ls lead temperature (soldering 5 seconds) +300 c jc thermal resistance junction to case 20 c/w i i dc input current 10 ma p d maximum power dissipation 1 w
79 radhard msi logic ut54acs139/ut54acts139 recommended operating conditions symbol parameter limit units v dd supply voltage 4.5 to 5.5 v v in input voltage any pin 0 to v dd v t c temperature range -55 to + 125 c
radhard msi logic 80 ut54acs139/ut54acts139 dc electrical characteristics 7 (v dd = 5.0v 10%; v ss = 0v 6 , -55 c < t c < +125 c) symbol parameter condition min max unit v il low-level input voltage 1 acts acs 0.8 .3v dd v v ih high-level input voltage 1 acts acs .5v dd .7v dd v i in input leakage current acts/acs v in = v dd or v ss -1 1 a v ol low-level output voltage 3 acts acs i ol = 8.0ma i ol = 100 a 0.40 0.25 v v oh high-level output voltage 3 acts acs i oh = -8.0ma i oh = -100 a .7v dd v dd - 0.25 v i ol output current 10 (sink) v in = v dd or v ss v ol = 0.4v 8 ma i oh output current 10 (source) v in = v dd or v ss v oh = v dd - 0.4v -8 ma i os short-circuit output current 2 ,4 acts/acs v o = v dd and v ss -200 200 ma p total power dissipation 2, 8, ,9 c l = 50pf 1.8 mw/ mhz i ddq quiescent supply current v dd = 5.5v 10 a i ddq quiescent supply current delta acts for input under test v in = v dd - 2.1v for all other inputs v in = v dd or v ss v dd = 5.5v 1.6 ma c in input capacitance 5 = 1mhz @ 0v 15 pf c out output capacitance 5 = 1mhz @ 0v 15 pf
81 radhard msi logic ut54acs139/ut54acts139 notes: 1. functional tests are conducted in accordance with mil-std-883 with the following input test conditions: v ih = v ih (min) + 20%, - 0%; v il = v il (max) + 0%, - 50%, as specified herein, for ttl, cmos, or schmitt compatible inputs. devices may be tested using any input voltage within th e above specified range, but are guaranteed to v ih (min) and v il (max). 2. supplied as a design limit but not guaranteed or tested. 3. per mil-prf-38535, for current density 5.0e5 amps/cm 2 , the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pf/mhz. 4. not more than one output may be shorted at a time for maximum duration of one second. 5. capacitance measured for initial qualification and when design changes may affect the value. capacitance is measured between the designated terminal and v ss at frequency of 1mhz and a signal amplitude of 50mv rms maximum. 6. maximum allowable relative shift equals 50mv. 7. all specifications valid for radiation dose 1e6 rads(si). 8. power does not include power contribution of any ttl output sink current. 9. power dissipation specified per switching output. 10. this value is guaranteed based on characterization data, but not tested.
radhard msi logic 82 ut54acs139/ut54acts139 ac electrical characteristics 2 (v dd = 5.0v 10%; v ss = 0v 1 , -55 c < t c < +125 c) notes: 1. maximum allowable relative shift equals 50mv. 2. all specifications valid for radiation dose 1e6 rads(si). symbol parameter minimum maximum unit t phl select to output yn 2 14 ns t plh select to output yn 2 15 ns t phl enable to output yn 2 14 ns t plh enable to output yn 2 12 ns
83 radhard msi logic ut54acs151/ut54acts151 radiation-hardened 1 of 8 data selectors/multiplexers features ? 8-line to 1-line multiplexers can perform as boolean function generators, parallel-to-serial converters, and data source selectors ? radiation-hardened cmos - latchup immune ? high speed ? low power consumption ? single 5 volt supply ? available qml q or v processes ? flexible package - 16-pin dip - 16-lead flatpack description the ut54acs151 and the ut54acts151 are data multiplex- ers that provide full binary decoding to select one of eight data sources. the strobe input, g , must be at a low logic level to enable the inputs. a high level at the strobe terminal forces the y output high and the y output low. the devices are characterized over full military temperature range of -55 c to +125 c. function table h= high level, l = low level, x = irrelevant d0, d1... d7 = the level of the d respective input pinouts 16-pin dip top view 16-lead flatpack top view logic symbol inputs output select strobe c b a g y y x x x h l h l l l l d0 d0 l l h l d1 d1 l h l l d2 d2 l h h l d3 d3 h l l l d4 d4 h l h l d5 d5 h h l l d6 d6 h h h l d7 d7 d3 d2 d1 d0 y y g v ss v dd d4 d5 d6 d7 a b c 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 v dd d4 d5 d6 d7 a b c 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 d3 d2 d1 d0 y y g v ss (7) (11) (10) (9) (4) (3) (2) (1) (15) (14) (13) (12) g a b c d0 d1 d2 d3 d4 d5 d6 d7 e n 0 1 2 0 1 2 3 4 5 6 (6) y mux note: 1. logic symbol in accordance with ansi/ieee std 91-1984 and iec publication 617-12. (5) y g 0 3 ---
radhard msi logic 84 ut54acs151/ut54acts151 logic diagram (5) y d0 d1 d2 d3 d4 d5 d6 d7 (7) (4) (3) (2) (1) (15) (14) (13) (12) strobe g (6) y a b c data select data (9) (10) (11) outputs
85 radhard msi logic ut54acs151/ut54acts151 radiation hardness specifications 1 notes: 1. logic will not latchup during radiation exposure within the limits defined in the table. 2. device storage elements are immune to seu affects. absolute maximum ratings note: 1. stresses outside the listed absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. exposure to absolute ma ximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter limit units total dose 1.0e6 rads(si) seu threshold 2 80 mev-cm 2 /mg sel threshold 120 mev-cm 2 /mg neutron fluence 1.0e14 n/cm 2 symbol parameter limit units v dd supply voltage -0.3 to 7.0 v v i/o voltage any pin -.3 to v dd +.3 v t stg storage temperature range -65 to +150 c t j maximum junction temperature +175 c t ls lead temperature (soldering 5 seconds) +300 c jc thermal resistance junction to case 20 c/w i i dc input current 10 ma p d maximum power dissipation 1 w symbol parameter limit units v dd supply voltage 4.5 to 5.5 v v in input voltage any pin 0 to v dd v t c temperature range -55 to + 125 c
radhard msi logic 86 ut54acs151/ut54acts151 dc electrical characteristics 7 (v dd = 5.0v 10%; v ss = 0v 6 , -55 c < t c < +125 c) symbol parameter condition min max unit v il low-level input voltage 1 acts acs 0.8 .3v dd v v ih high-level input voltage 1 acts acs .5v dd .7v dd v i in input leakage current acts/acs v in = v dd or v ss -1 1 a v ol low-level output voltage 3 acts acs i ol = 8.0ma i ol = 100 a 0.40 0.25 v v oh high-level output voltage 3 acts acs i oh = -8.0ma i oh = -100 a .7v dd v dd - 0.25 v i os short-circuit output current 2 ,4 acts/acs v o = v dd and v ss -200 200 ma i ol output current 10 (sink) v in = v dd or v ss v ol = 0.4v 8 ma i oh output current 10 (source) v in = v dd or v ss v oh = v dd - 0.4v -8 ma p total power dissipation 2, 8, 9 c l = 50pf 2.3 mw/ mhz i ddq quiescent supply current v dd = 5.5v 10 a i ddq quiescent supply current delta acts for input under test v in = v dd - 2.1v for all other inputs v in = v dd or v ss v dd = 5.5v 1.6 ma c in input capacitance 5 = 1mhz @ 0v 15 pf c out output capacitance 5 = 1mhz @ 0v 15 pf
87 radhard msi logic ut54acs151/ut54acts151 notes: 1. functional tests are conducted in accordance with mil-std-883 with the following input test conditions: v ih = v ih (min) + 20%, - 0%; v il = v il (max) + 0%, - 50%, as specified herein, for ttl, cmos, or schmitt compatible inputs. devices may be tested using any input voltage within th e above specified range, but are guaranteed to v ih (min) and v il (max). 2. supplied as a design limit but not guaranteed or tested. 3. per mil-prf-38535, for current density 5.0e5 amps/cm 2 , the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pf/mhz. 4. not more than one output may be shorted at a time for maximum duration of one second. 5. capacitance measured for initial qualification and when design changes may affect the value. capacitance is measured between the designated terminal and v ss at frequency of 1mhz and a signal amplitude of 50mv rms maximum. 6. maximum allowable relative shift equals 50mv. 7. all specifications valid for radiation dose 1e6 rads(si). 8. power does not include power contribution of any ttl output sink current. 9. power dissipation specified per switching output. 10. this value is guaranteed based on characterization data, but not tested.
radhard msi logic 88 ut54acs151/ut54acts151 ac electrical characteristics 2 (v dd = 5.0v 10%; v ss = 0v 1 , -55 c < t c < +125 c) notes: 1. maximum allowable relative shift equals 50mv. 2. all specifications valid for radiation dose 1e6 rads(si). symbol parameter minimum maximum unit t phl input to y 1 22 ns t plh input to y 1 23 ns t phl input to y 1 25 ns t plh input to y 1 19 ns t phl select to y 1 21 ns t plh select to y 1 22 ns t phl select to y 1 24 ns t plh select to y 1 21 ns t phl g to y 1 14 ns t plh g to y 1 11 ns t phl g to y 1 14 ns t plh g to y 1 10 ns
89 radhard msi logic ut54acs153/ut54acts153 radiation-hardened dual 4 to 1 multiplexers features radiation-hardened cmos - latchup immune high speed low power consumption single 5 volt supply available qml q or v processes flexible package - 16-pin dip - 16-lead flatpack description the ut54acs153 and the ut54acts153 are dual four to one line selectors/multiplexers. common inputs a and b select a value from one of four sources for each section and routes the value from each section to their respective outputs. separate strobe inputs, g are provided for each of the two four-line sec- tions. the devices are characterized over full military temperature range of -55 c to +125 c. function table pinouts 16-pin dip top view 16-lead flatpack top view logic symbol select inputs data inputs output control output b a c0 c1 c2 c3 g y x x x x x x h l l l l x x x l l l l h x x x l h l h x l x x l l l h x h x x l h h l x x l x l l h l x x h x l h h h x x x l l l h h x x x h l h 1 2 3 4 5 7 6 16 15 14 13 12 10 11 1g b 1c3 1c2 1c1 1c0 1y v dd 2g a 2c3 2c2 2c1 2c0 8 9 v ss 2y 1 2 3 4 5 7 6 16 15 14 13 12 10 11 v dd 1g b 1c3 1c2 1c1 1c0 1y 2g a 2c3 2c2 2c1 2c0 v ss 2y 8 9 (14) a (2) b 1 0 mux note: 1. logic symbol in accordance with ansi/ieee std 91-1984 and iec publication 617-12. (1) 1g en (6) 1c0 0 (5) 1c1 (4) 1c2 (3) 1c3 (15) 2g (10) 2c0 (11) 2c1 (7) 1y 2c2 (13) 2c3 (9) 2y (12) 1 2 3 g 0 3 ---
radhard msi logic 90 ut54acs153/ut54acts153 logic diagram (7) 1y (9) 2y (1) (6) (5) (4) (3) (2) (14) (10) (11) (12) (13) 2c3 2c2 2c1 2c0 a b 1c3 1c2 1c1 1c0 1g (15) output control output control 2g data 1 data 2 select
91 radhard msi logic ut54acs153/ut54acts153 radiation hardness specifications 1 notes: 1. logic will not latchup during radiation exposure within the limits defined in the table. 2. device storage elements are immune to seu affects. absolute maximum ratings note: 1. stresses outside the listed absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. exposure to absolute ma ximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter limit units total dose 1.0e6 rads(si) seu threshold 2 80 mev-cm 2 /mg sel threshold 120 mev-cm 2 /mg neutron fluence 1.0e14 n/cm 2 symbol parameter limit units v dd supply voltage -0.3 to 7.0 v v i/o voltage any pin -.3 to v dd +.3 v t stg storage temperature range -65 to +150 c t j maximum junction temperature +175 c t ls lead temperature (soldering 5 seconds) +300 c jc thermal resistance junction to case 20 c/w i i dc input current 10 ma p d maximum power dissipation 1 w symbol parameter limit units v dd supply voltage 4.5 to 5.5 v v in input voltage any pin 0 to v dd v t c temperature range -55 to + 125 c
radhard msi logic 92 ut54acs153/ut54acts153 dc electrical characteristics 7 (v dd = 5.0v 10%; v ss = 0v 6 , -55 c < t c < +125 c) symbol parameter condition min max unit v il low-level input voltage 1 acts acs 0.8 .3v dd v v ih high-level input voltage 1 acts acs .5v dd .7v dd v i in input leakage current acts/acs v in = v dd or v ss -1 1 a v ol low-level output voltage 3 acts acs i ol = 8.0ma i ol = 100 a 0.40 0.25 v v oh high-level output voltage 3 acts acs i oh = -8.0ma i oh = -100 a .7v dd v dd - 0.25 v i os short-circuit output current 2 ,4 acts/acs v o = v dd and v ss -200 200 ma i ol output current 10 (sink) v in = v dd or v ss v ol = 0.4v 8 ma i oh output current 10 (source) v in = v dd or v ss v oh = v dd - 0.4v -8 ma p total power dissipation 2, 8, 9 c l = 50pf 2.1 mw/ mhz i ddq quiescent supply current delta acts for input under test v in = v dd - 2.1v for all other inputs v in = v dd or v ss v dd = 5.5v 1.6 ma i ddq quiescent supply current v dd = 5.5v 10 a c in input capacitance 5 = 1mhz @ 0v 15 pf c out output capacitance 5 = 1mhz @ 0v 15 pf
93 radhard msi logic ut54acs153/ut54acts153 notes: 1. functional tests are conducted in accordance with mil-std-883 with the following input test conditions: v ih = v ih (min) + 20%, - 0%; v il = v il (max) + 0%, - 50%, as specified herein, for ttl, cmos, or schmitt compatible inputs. devices may be tested using any input voltage within th e above specified range, but are guaranteed to v ih (min) and v il (max). 2. supplied as a design limit but not guaranteed or tested. 3. per mil-prf-38535, for current density 5.0e5 amps/cm 2 , the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pf/mhz. 4. not more than one output may be shorted at a time for maximum duration of one second. 5. capacitance measured for initial qualification and when design changes may affect the value. capacitance is measured between the designated terminal and v ss at frequency of 1mhz and a signal amplitude of 50mv rms maximum. 6. maximum allowable relative shift equals 50mv. 7. all specifications valid for radiation dose 1e6 rads(si). 8. power does not include power contribution of any ttl output sink current. 9. power dissipation specified per switching output. 10. this value is guaranteed based on characterization data, but not tested.
radhard msi logic 94 ut54acs153/ut54acts153 ac electrical characteristics 2 (v dd = 5.0v 10%; v ss = 0v 1 , -55 c < t c < +125 c) notes: 1. maximum allowable relative shift equals 50mv. 2. all specifications valid for radiation dose 1e6 rads(si). symbol parameter minimum maximum unit t phl data to output yn 2 16 ns t plh data to output yn 2 12 ns t phl strobe to output yn 1 15 ns t plh strobe to output yn 1 14 ns t phl select to output yn 2 16 ns t plh select to output yn 2 14 ns
95 radhard msi logic ut54acs157/ut54acts157 radiation-hardened quadruple 2 to 1 multiplexers features ? radiation-hardened cmos - latchup immune ? high speed ? low power consumption ? single 5 volt supply ? available qml q or v processes ? flexible package - 16-pin dip - 16-lead flatpack description the ut54acs157 and the ut54acts157 are monolithic data selectors/multiplexers. a 4-bit word is selected from one of two sources and is routed to the four outputs. a separate strobe input, g , is provided. the devices are characterized over full military temperature range of -55 c to +125 c. function table pinouts 16-pin dip top view 16-lead flatpack top view logic symbol inputs output strobe g select a /b data a b y h x x x l l l l x l l l h x h l h x l l l h x h h 1 2 3 4 5 7 6 16 15 14 13 12 10 11 a /b a1 b1 y1 a2 b2 y2 v dd g a4 b4 y4 a3 b3 8 9 v ss y3 1 2 3 4 5 7 6 16 15 14 13 12 10 11 v dd a /b a1 b1 y1 a2 b2 y2 g a4 b4 y4 a3 b3 v ss y3 8 9 (15) g (1) a /b g1 en mux note: 1. logic symbol in accordance with ansi/ieee std 91-1984 and iec publication 617-12. (2) a1 1 (3) b1 1 (5) a2 (6) b2 (11) a3 (10) b3 (14) a4 (13) b4 (4) y1 (7) y2 (9) y3 (12) y4
radhard msi logic 96 ut54acs157/ut54acts157 logic diagram (12) (9) (4) (7) 1a 1b 2a 2b 3a 3b 4a 4b strobe g select a /b (2) (3) (5) (6) (11) (10) (14) (13) (15) (1) 1y 2y 3y 4y
97 radhard msi logic ut54acs157/ut54acts157 radiation hardness specifications 1 notes: 1. logic will not latchup during radiation exposure within the limits defined in the table. 2. device storage elements are immune to seu affects. absolute maximum ratings note: 1. stresses outside the listed absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. exposure to absolute ma ximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter limit units total dose 1.0e6 rads(si) seu threshold 2 80 mev-cm 2 /mg sel threshold 120 mev-cm 2 /mg neutron fluence 1.0e14 n/cm 2 symbol parameter limit units v dd supply voltage -0.3 to 7.0 v v i/o voltage any pin -.3 to v dd +.3 v t stg storage temperature range -65 to +150 c t j maximum junction temperature +175 c t ls lead temperature (soldering 5 seconds) +300 c jc thermal resistance junction to case 20 c/w i i dc input current 10 ma p d maximum power dissipation 1 w symbol parameter limit units v dd supply voltage 4.5 to 5.5 v v in input voltage any pin 0 to v dd v t c temperature range -55 to + 125 c
radhard msi logic 98 ut54acs157/ut54acts157 dc electrical characteristics 7 (v dd = 5.0v 10%; v ss = 0v 6 , -55 c < t c < +125 c) symbol parameter condition min max unit v il low-level input voltage 1 acts acs 0.8 .3v dd v v ih high-level input voltage 1 acts acs .5v dd .7v dd v i in input leakage current acts/acs v in = v dd or v ss -1 1 a v ol low-level output voltage 3 acts acs i ol = 8.0ma i ol = 100 a 0.40 0.25 v v oh high-level output voltage 3 acts acs i oh = -8.0ma i oh = -100 a .7v dd v dd - 0.25 v i os short-circuit output current 2 ,4 acts/acs v o = v dd and v ss -200 200 ma i ol output current 10 (sink) v in = v dd or v ss v ol = 0.4v 8 ma i oh output current 10 (source) v in = v dd or v ss v oh = v dd - 0.4v -8 ma p total power dissipation 2, 8, 9 c l = 50pf 1.9 mw/ mhz i ddq quiescent supply current v dd = 5.5v 10 a i ddq quiescent supply current delta acts for input under test v in = v dd - 2.1v for all other inputs v in = v dd or v ss v dd = 5.5v 1.6 ma c in input capacitance 5 = 1mhz @ 0v 15 pf c out output capacitance 5 = 1mhz @ 0v 15 pf
99 radhard msi logic ut54acs157/ut54acts157 notes: 1.functional tests are conducted in accordance with mil-std-883 with the following input test conditions: v ih = v ih (min) + 20%, - 0%; v il = v il (max) + 0%, - 50%, as specified herein, for ttl, cmos, or schmitt compatible inputs. devices may be tested using any input voltag within the above specified range, but are guaranteed to v ih (min) and v il (max). 2. supplied as a design limit but not guaranteed or tested. 3. per mil-prf-38535, for current density 5.0e5 amps/cm 2 , the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pf/mhz. 4. not more than one output may be shorted at a time for maximum duration of one second. 5. capacitance measured for initial qualification and when design changes may affect the value. capacitance is measured between the designated terminal and v ss at frequency of 1mhz and a signal amplitude of 50mv rms maximum. 6. maximum allowable relative shift equals 50mv. 7. all specifications valid for radiation dose 1e6 rads(si). 8. power does not include power contribution of any ttl output sink current. 9. power dissipation specified per switching output. 10. this value is guaranteed based on characterization data, but not tested.
radhard msi logic 100 ut54acs157/ut54acts157 ac electrical characteristics 2 (v dd = 5.0v 10%; v ss = 0v 1 , -55 c < t c < +125 c) notes: 1. maximum allowable relative shift equals 50mv. 2. all specifications valid for radiation dose 1e6 rads(si). symbol parameter minimum maximum unit t phl data to output yn 2 15 ns t plh data to output yn 2 13 ns t phl strobe to output yn 2 15 ns t plh strobe to output yn 2 12 ns t phl select to output yn 2 16 ns t plh select to output yn 2 14 ns
101 radhard msi logic ut54acs163/ut54acts163 radiation-hardened 4-bit synchronous counters features internal look-ahead for fast counting carry output for n-bit cascading synchronous counting synchronously programmable radiation-hardened cmos - latchup immune high speed low power consumption single 5 volt supply available qml q or v processes flexible package - 16-pin dip - 16-lead flatpack description the ut54acs163 and the ut54acts163 are synchronous presettable 4-bit binary counters that feature internal carry look- ahead logic for high-speed counting designs. synchronous op- eration occurs by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when in- structed by the count-enable inputs and internal gating. a buff- ered clock input triggers the four flip-flops on the rising (posi- tive-going) edge of the clock input waveform. the counters are fully programmable (i.e., they may be preset to any number between 0 and 15). presetting is synchronous; applying a low level at the load input disables the counter and causes the outputs to agree with the load data after the next clock pulse. the clear function is synchronous and a low level at the clear input sets all four of the flip-flop outputs low after the next clock pulse. this synchronous clear allows the count length to be mod- ified by decoding the q outputs for the maximum count desired. the counters feature a fully independent clock circuit. changes at control inputs (enp, ent, or load ) that modify the oper- ating mode have no effect on the contents of the counter until clocking occurs. the function of the counter (whether enabled, disabled, loading, or counting) will be dictated solely by the conditions meeting the stable setup and hold times. the devices are characterized over full military temperature range of -55 c to +125 c. pinouts 16-pin dip top view 16-lead flatpack top view logic symbol 1 2 3 4 5 7 6 16 15 14 13 12 10 11 clr clk a b c d enp v dd rco q a q b q c q d ent 8 9 v ss load 1 2 3 4 5 7 6 16 15 14 13 12 10 11 v dd 8 9 clr clk a b c d enp rco q a q b q c q d ent v ss load (1) clr (9) load m1 5ct=0 ctrdiv 16 (10) ent g3 (7) enp g4 (2) clk (3) a (4) b (5) c (6) d (15) rco (14) q a (11) q d m2 c5/2,3,4+ (12) q c (13) q b 1,5d (1) (2) (4) (8) 3ct = 15 note: 1. logic symbol in accordance with ansi/ieee std 91-1984 and iec publi- cation 617-12.
radhard msi logic 102 ut54acs163/ut54acts163 function table h = high voltage level h = high voltage level one setup time prior to the low-to-high clock transition l = low voltage level l = low voltage level one setup time prior to the low-to-high clock transition notes: 1. the rco output is high when ent is high and the counter is at terminal count hhhh. 2. the high-to-low transition of enp or ent should only occur while clk is high for conventional operations. 3. the low-to-high transition of load or clr should only occur while clk is high for conventional operations. logic diagram operating mode clr clk enp ent load data a,b,c,d q n rco reset (clear) l x x x x l l parallel load h 3 h 3 x x x x l l l h l h l 1 count h 3 h h h x count 1 inhibit h 3 h 3 x x l 2 x x l 2 h 3 h 3 x x q n q n 1 l (2) (1) (9) (7) (10) (3) (4) (5) (6) (14) (12) (13) (11) (15) q a q b q c q d rco data d data c data b data a ent enp load clr clk c d q q c d q q c d q q c d q q
103 radhard msi logic ut54acs163/ut54acts163 radiation hardness specifications 1 notes: 1. logic will not latchup during radiation exposure within the limits defined in the table. 2. device storage elements are immune to seu affects. absolute maximum ratings note: 1. stresses outside the listed absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. exposure to abso lute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter limit units total dose 1.0e6 rads(si) seu threshold 2 80 mev-cm 2 /mg sel threshold 120 mev-cm 2 /mg neutron fluence 1.0e14 n/cm 2 symbol parameter limit units v dd supply voltage 0.3 to 7.0 v v i/o voltage any pin -.3 to v dd +.3 v t stg storage temperature range -65 to +150 c t j maximum junction temperature +175 c t ls lead temperature (soldering 5 seconds) +300 c jc thermal resistance junction to case 20 c/w i i dc input current 10 ma p d maximum power dissipation 1 w symbol parameter limit units v dd supply voltage 4.5 to 5.5 v v in input voltage any pin 0 to v dd v t c temperature range -55 to + 125 c
radhard msi logic 104 ut54acs163/ut54acts163 dc electrical characteristics 7 (v dd = 5.0v 10%; v ss = 0v 6 , -55 c < t c < +125 c) symbol parameter condition min max unit v il low-level input voltage 1 acts acs 0.8 .3v dd v v ih high-level input voltage 1 acts acs .5v dd .7v dd v i in input leakage current acts/acs v in = v dd or v ss -1 1 a v ol low-level output voltage 3 acts acs i ol = 8.0ma i ol = 100 a 0.40 0.25 v v oh high-level output voltage 3 acts acs i oh = -8.0ma i oh = -100 a .7v dd v dd - 0.25 v i os short-circuit output current 2 ,4 acts/acs v o = v dd and v ss -200 200 ma i ol output current 10 (sink) v in = v dd or v ss v ol = 0.4v 8 ma i oh output current 10 (source) v in = v dd or v ss v oh = v dd - 0.4v -8 ma p total power dissipation 2, 8, 9 c l = 50pf 1.9 mw/mhz i ddq quiescent supply current v dd = 5.5v 10 a i ddq quiescent supply current delta acts for input under test v in = v dd - 2.1v for all other inputs v in = v dd or v ss v dd = 5.5v 1.6 ma c in input capacitance 5 = 1mhz @ 0v 15 pf c out output capacitance 5 = 1mhz @ 0v 15 pf
105 radhard msi logic ut54acs163/ut54acts163 notes: 1. functional tests are conducted in accordance with mil-std-883 with the following input test conditions: v ih = v ih (min) + 20%, - 0%; v il = v il (max) + 0%, - 50%, as specified herein, for ttl, cmos, or schmitt compatible inputs. devices may be tested using any input voltage within th e above specified range, but are guaranteed to v ih (min) and v il (max). 2. supplied as a design limit but not guaranteed or tested. 3. per mil-prf-38535, for current density 5.0e5 amps/cm 2 , the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pf/mhz. 4. not more than one output may be shorted at a time for maximum duration of one second. 5. capacitance measured for initial qualification and when design changes may affect the value. capacitance is measured between the designated terminal and v ss at frequency of 1mhz and a signal amplitude of 50mv rms maximum. 6. maximum allowable relative shift equals 50mv. 7. all specifications valid for radiation dose 1e6 rads(si). 8. power does not include power contribution of any ttl output sink current. 9. power dissipation specified per switching output. 10. this value is guaranteed based on characterization data, but not tested.
radhard msi logic 106 ut54acs163/ut54acts163 ac electrical characteristics 2 (v dd = 5.0v 10%; v ss = 0v 1 , -55 c < t c < +125 c) notes: 1. maximum allowable relative shift equals 50mv. 2. all specifications valid for radiation dose 1e6 rads(si). 3. based on characterization, hold time (t h1 ) of 0ns can be assumed if data setup time (t su1 ) is > 10ns. this is guaranteed, but not tested. symbol parameter minimum maximum unit t phl clk to q n 4 24 ns t plh clk to q n 4 22 ns t phl clk to rco 4 22 ns t plh clk to rco 4 24 ns t phl ent to rco 1 13 ns t plh ent to rco 1 14 ns f max maximum clock frequency 77 mhz t su1 a, b, c, d setup time before clk 6 ns t su2 load , enp, ent, clr low or high setup time before clk 6 ns t h1 3 data hold time after clk 1 ns t h2 all synchronous inputs hold time after clk 1 ns t w minimum pulse width clr low clk high clk low 7 ns
107 radhard msi logic ut54acs164/ut54acts164 radiation-hardened 8-bit shift registers features and-gated (enable/disable) serial inputs fully buffered clock and serial inputs direct clear radiation-hardened cmos - latchup immune high speed low power consumption single 5 volt supply available qml q or v processes flexible package - 14-pin dip - 14-lead flatpack description the ut54acs164 and the ut54acts164 are 8-bit shift reg- isters which feature and-gated serial inputs and an asynchro- nous clear. the gated serial inputs (a and b) permit complete control over incoming data. a low at either input inhibits entry of new data and resets the first flip-flop to the low level at the next clock pulse. a high-level at both serial inputs sets the first flip-flop to the high level at the next clock pulse. data at the serial inputs may be changed while the clock is high or low, providing the minimum setup time requirements are met. clocking occurs on the low-to-high-level transition of the clock input. the devices are characterized over full military temperature range of -55 c to +125 c. function table notes: 1. q a0 , q b0 , q h0 = the level of q a , q b or q h , respectively, before the indicated steady-state input conditions were established. 2. q an and q gn = the level of q a or q g before the most recent transition of the clock; indicates a one-bit shift. pinouts 14-pin dip top view 14-lead flatpack top view logic symbol inputs outputs clr clk a b q a q b ... q h l x x x l l l h l x x q a0 q b0 q h0 h h h h q an q gn h l x l q an q gn h x l l q an q gn 1 2 3 4 5 7 6 14 13 12 11 10 8 9 a b q a q b q c q d v ss v dd q h q g q f q e clr clk 1 2 3 4 5 7 6 14 13 12 11 10 8 9 v dd q h q g q f q e clr clk a b q a q b q c q d v ss (9) clr (8) clk r 1d note: 1. logic symbol in accordance with ansi/ieee std 91-1984 and iec publication 617-12. (1) a (2) b (3) q a srg8 & (4) q b (5) q c (6) q d (10) q e (11) q f (12) q g (13) q h c1/
radhard msi logic 108 ut54acs164/ut54acts164 logic diagram radiation hardness specifications 1 notes: 1. logic will not latchup during radiation exposure within the limits defined in the table. 2. device storage elements are immune to seu affects. absolute maximum ratings note: 1. stresses outside the listed absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. exposure to absolute ma ximum rating conditions for extended periods may affect device reliability. parameter limit units total dose 1.0e6 rads(si) seu threshold 2 80 mev-cm 2 /mg sel threshold 120 mev-cm 2 /mg neutron fluence 1.0e14 n/cm 2 q a (8) clk k k r s k r s k r s k r s k r s k r s k r s q b q c q d q e q f q g q h clr (9) (2) (1) a b serial r s c c c c c c c c (3) (4) (5) (6) (10) (11) (12) (13) symbol parameter limit units v dd supply voltage -0.3 to 7.0 v v i/o voltage any pin -.3 to v dd +.3 v t stg storage temperature range -65 to +150 c t j maximum junction temperature +175 c t ls lead temperature (soldering 5 seconds) +300 c jc thermal resistance junction to case 20 c/w i i dc input current 10 ma p d maximum power dissipation 1 w
109 radhard msi logic ut54acs164/ut54acts164 recommended operating conditions symbol parameter limit units v dd supply voltage 4.5 to 5.5 v v in input voltage any pin 0 to v dd v t c temperature range -55 to + 125 c
radhard msi logic 110 ut54acs164/ut54acts164 dc electrical characteristics 7 (v dd = 5.0v 10%; v ss = 0v 6 , -55 c < t c < +125 c) symbol parameter condition min max unit v il low-level input voltage 1 acts acs 0.8 .3v dd v v ih high-level input voltage 1 acts acs .5v dd .7v dd v i in input leakage current acts/acs v in = v dd or v ss -1 1 a v ol low-level output voltage 3 acts acs i ol = 8.0ma i ol = 100 a 0.40 0.25 v v oh high-level output voltage 3 acts acs i oh = -8.0ma i oh = -100 a .7v dd v dd - 0.25 v i os short-circuit output current 2 ,4 acts/acs v o = v dd and v ss -200 200 ma i ol output current 10 (sink) v in = v dd or v ss v ol = 0.4v 8 ma i oh output current 10 (source) v in = v dd or v ss v oh = v dd - 0.4v -8 ma p total power dissipation 2, 8, 9 c l = 50pf 1.9 mw/ mhz i ddq quiescent supply current v dd = 5.5v 10 a i ddq quiescent supply current delta acts for input under test v in = v dd - 2.1v for all other inputs v in = v dd or v ss v dd = 5.5v 1.6 ma c in input capacitance 5 = 1mhz @ 0v 15 pf c out output capacitance 5 = 1mhz @ 0v 15 pf
111 radhard msi logic ut54acs164/ut54acts164 notes: 1. functional tests are conducted in accordance with mil-std-883 with the following input test conditions: v ih = v ih (min) + 20%, - 0%; v il = v il (max) + 0%, - 50%, as specified herein, for ttl, cmos, or schmitt compatible inputs. devices may be tested using any input voltage within th e above specified range, but are guaranteed to v ih (min) and v il (max). 2. supplied as a design limit but not guaranteed or tested. 3. per mil-prf-38535, for current density 5.0e5 amps/cm 2 , the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pf/mhz. 4. not more than one output may be shorted at a time for maximum duration of one second. 5. capacitance measured for initial qualification and when design changes may affect the value. capacitance is measured between the designated terminal and v ss at frequency of 1mhz and a signal amplitude of 50mv rms maximum. 6. maximum allowable relative shift equals 50mv. 7. all specifications valid for radiation dose 1e6 rads(si). 8. power does not include power contribution of any ttl output sink current 9. power dissipation specified per switching output. 10. this value is guaranteed based on characterization data, but not tested.
radhard msi logic 112 ut54acs164/ut54acts164 ac electrical characteristics 2 (v dd = 5.0v 10%; v ss = 0v 1 , -55 c < t c < +125 c) notes: 1. maximum allowable relative shift equals 50mv. 2. all specifications valid for radiation dose 1e6 rads(si). 3. based on characterization, hold time (t h ) of 0ns can be assumed if data setup time (t su2 ) is > 10ns. this is guaranteed, but not tested. symbol parameter minimum maximum unit t phl clk to qn 4 21 ns t plh clk to qn 2 18 ns t phl clr to qn 5 21 ns f max maximum clock frequency 83 mhz t su1 clr inactive setup time before clk 4 ns t su2 data setup time before clk 4 ns t h 3 data hold time after clk 2 ns t w minimum pulse width clr low clk high clk low 6 ns
113 radhard msi logic ut54acs165/ut54acts165 radiation-hardened 8-bit parallel shift registers features complementary outputs direct overriding load (data) inputs gated clock inputs parallel-to-serial data conversions radiation-hardened cmos - latchup immune high speed low power consumption single 5 volt supply available qml q or v processes flexible package - 16-pin dip - 16-lead flatpack description the ut54acs165 and the ut54acts165 are 8-bit serial shift regis- ters that, when clocked, shift the data toward serial output q h . parallel- in access to each stage is provided by eight individual data inputs that are enabled by a low level at the sh/ ld input. the devices feature a clock inhibit function and a complemented serial output q h . clocking is accomplished by a low-to-high transition of the clk input while sh/ ld is held high and clk inh is held low. the functions of the clk and clk inh (clock inhibit) inputs are interchangeable. since a low clk input and a low-to-high transition of clk inh will also accomplish clocking, clk inh should be changed to the high level only while the clk input is high. parallel loading is disabled when sh/ ld is held high. parallel inputs to the registers are enabled while sh/ ld is low independently of the levels of clk, clk inh or ser inputs. the devices are characterized over full military temperature range of -55 c to +125 c. function table note: 1. q n = the state of the referenced output one setup time prior to the low-to- high clock transition. pinouts 16-pin dip top view 16-lead flatpack top view logic symbol inputs internal outputs outputs sh/ ld clk inh clk ser parallel a . . . h q a q b q h q h l x x x a . . . h a b h h h l l x x q a q b q h q h h l h x h q a q g q g h l l x l q a q g q g h h x x x q a q b q h q h 1 2 3 4 5 7 6 16 15 14 13 12 10 11 sh/ ld clk e f g h q h v dd clk inh d c b a ser 8 9 v ss q h 1 2 3 4 5 7 6 16 15 14 13 12 10 11 v dd 8 9 sh /ld clk e f g h q h clk inh d c b a ser v ss q h (1) sh/ ld (15) clk inh c2/ c1 (load) note: 1. logic symbol in accordance with ansi/ieee std 91-1984 and iec publication 617-12. (10) ser (11) a srg8 (9) q h (7) q h 1 (2) clk 2d 1d (12) b (13) c (14) d (3) e (4) f (5) g (6) h 1d 1d
radhard msi logic 114 ut54acs165/ut54acts165 logic diagram radiation hardness specifications 1 notes: 1. logic will not latchup during radiation exposure within the limits defined in the table. 2. device storage elements are immune to seu affects. parameter limit units total dose 1.0e6 rads(si) seu threshold 2 80 mev-cm 2 /mg sel threshold 120 mev-cm 2 /mg neutron fluence 1.0e14 n/cm 2 a b c d e f g h (11 ) (12) (13) (14) (4) (5) (6) (3) s c d r (1) (15) (2) (10 ) clk inh clk ser q c q d q e q f q g sh/ ld (9) (7) q h q h s c d r s c d r s c d r s c d r s c d r s c d r q a s c d r q h q b
115 radhard msi logic ut54acs165/ut54acts165 absolute maximum ratings note: 1. stresses outside the listed absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. exposure to absolute ma ximum rating conditions for extended periods may affect device reliability. recommended operating conditions symbol parameter limit units v dd supply voltage -0.3 to 7.0 v v i/o voltage any pin -.3 to v dd +.3 v t stg storage temperature range -65 to +150 c t j maximum junction temperature +175 c t ls lead temperature (soldering 5 seconds) +300 c jc thermal resistance junction to case 20 c/w i i dc input current 10 ma p d maximum power dissipation 1 w symbol parameter limit units v dd supply voltage 4.5 to 5.5 v v in input voltage any pin 0 to v dd v t c temperature range -55 to + 125 c
radhard msi logic 116 ut54acs165/ut54acts165 dc electrical characteristics 7 (v dd = 5.0v 10%; v ss = 0v 6 , -55 c < t c < +125 c) symbol parameter condition min max unit v il low-level input voltage 1 acts acs 0.8 .3v dd v v ih high-level input voltage 1 acts acs .5v dd .7v dd v i in input leakage current acts/acs v in = v dd or v ss -1 1 a v ol low-level output voltage 3 acts acs i ol = 8.0ma i ol = 100 a 0.40 0.25 v v oh high-level output voltage 3 acts acs i oh = -8.0ma i oh = -100 a .7v dd v dd - 0.25 v i os short-circuit output current 2 ,4 acts/acs v o = v dd and v ss -200 200 ma i ol output current 10 (sink) v in = v dd or v ss v ol = 0.4v 8 ma i oh output current 10 (source) v in = v dd or v ss v oh = v dd - 0.4v -8 ma p total power dissipation 2, 8, 9 c l = 50pf 2.9 mw/mhz i ddq quiescent supply current v dd = 5.5v 10 a i ddq quiescent supply current delta acts for input under test v in = v dd - 2.1v for all other inputs v in = v dd or v ss v dd = 5.5v 1.6 ma c in input capacitance 5 = 1mhz @ 0v 15 pf c out output capacitance 5 = 1mhz @ 0v 15 pf
117 radhard msi logic ut54acs165/ut54acts165 notes: 1. functional tests are conducted in accordance with mil-std-883 with the following input test conditions: v ih = v ih (min) + 20%, - 0%; v il = v il (max) + 0%, - 50%, as specified herein, for ttl, cmos, or schmitt compatible inputs. devices may be tested using any input voltage within th e above specified range, but are guaranteed to v ih (min) and v il (max). 2. supplied as a design limit but not guaranteed or tested. 3. per mil-prf-38535, for current density 5.0e5 amps/cm 2 , the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pf/mhz. 4. not more than one output may be shorted at a time for maximum duration of one second. 5. capacitance measured for initial qualification and when design changes may affect the value. capacitance is measured between the designated terminal and v ss at frequency of 1mhz and a signal amplitude of 50mv rms maximum. 6. maximum allowable relative shift equals 50mv. 7. all specifications valid for radiation dose 1e6 rads(si). 8. power does not include power contribution of any ttl output sink current. 9. power dissipation specified per switching output. 10. this value is guaranteed based on characterization data, but not tested.
radhard msi logic 118 ut54acs165/ut54acts165 ac electrical characteristics 2 (v dd = 5.0v 10%; v ss = 0v 1 , -55 c < t c < +125 c) notes: 1. maximum allowable relative shift equals 50mv. 2. all specifications valid for radiation dose 1e6 rads(si). 3. based on characterization, hold time (t h3 ) of 0ns for data pins a-h, can be assumed if data setup time (t su2 ) is > 10ns. this is guaranteed, but not tested. symbol parameter minimum maximum unit t phl clk or clk inh to q h or q h 2 21 ns t plh clk or clk inh to q h or q h 2 18 ns t phl sh/ ld to q h or q h 2 21 ns t plh sh/ ld to q h or q h 2 18 ns t phl h to q h 2 21 ns t plh h to q h 2 17 ns t phl h to q h 2 20 ns t plh h to q h 2 18 ns f max maximum clock frequency 71 mhz t su1 ser, sh/ ld , clkinh or clk setup time before clk or clk inh 7 ns t su2 data setup time before sh/ ld 7 ns t h1 ser hold time after clk or clk inh 2 ns t h2 clk inh hold time after clk 2 ns t h3 3 hold time for any input after sh/ ld 2 ns t w minimum pulse width clk or clk inh high clk or clk inh low sh/ ld 7 ns
119 radhard msi logic ut54acs169/ut54acts169 radiation-hardened 4-bit up-down binary counters features fully synchronous operation for counting and programming internal look-ahead for fast counting carry output for n-bit cascading fully independent clock circuit radiation-hardened cmos - latchup immune high speed low power consumption single 5 volt supply available qml q or v processes flexible package - 16-pin dip - 16-lead flatpack description the ut54acs169 and the ut54acts169 are synchronous 4- bit binary counters that feature an internal carry look-ahead for cascading in high-speed counting applications. synchronous operation is provided by having all flip-flops clocked simulta- neously so that the outputs change coincident with each other when instructed by the count-enable inputs and internal gating. synchronous operation helps eliminate the output counting spikes that are normally associated with asynchronous (ripple clock) counters. the clock input triggers the four flip-flops on the rising (positive-going) edge of the clock. the counters are fully programmable (i.e., the outputs may each be preset high or low). the load input circuitry allows loading with the carry-enable output of cascaded counters. loading is synchronous; applying a low level at the load input disables the counter and causes the outputs to agree with the data inputs after the next clock pulse. the carry look-ahead circuitry provides for cascaded counters for n-bit synchronous application without additional gating. in- strumental in accomplishing this function are two count-enable inputs and a carry output. assert both count enable inputs ( enp and ent ) to count. the direction of the count is determined by the level of the u/ d input. when u/ d is high, the counter counts up; when low, it counts down. input ent is fed forward to enable the carry output. the ripple carry output rco enables a low-level pulse while the count is zero (all inputs low) counting down or maximum (15) counting up. the low- level overflow carry pulse can be used to enable successive cas- caded stages. pinouts 16-pin dip top view 16-lead flatpack top view transitions at enp or ent are allowed regardless of the level of the clock input. the counters feature a fully independent clock circuit. changes at control inputs ( enp , ent , load , u/ d ) that modify the op- erating mode have no effect on the contents of the counter until clocking occurs. the function of the counter (whether enabled, disabled, loading, or counting) will be dictated solely by the conditions meeting the stable setup and hold times. the devices are characterized over full military temperature range of -55 c to +125 c. 1 2 3 4 5 7 6 16 15 14 13 12 10 11 u/ d clk a b c d enp v dd rco q a q b q c ent 8 9 v ss load q d 1 2 3 4 5 7 6 16 15 14 13 12 10 11 v dd 8 9 u/ d clk a b c d enp rco q a q b q c q d ent v ss load
radhard msi logic 120 ut54acs169/ut54acts169 logic symbol function table (9) load (1) u/ d m3 (up) m1 (load) ctrdiv 16 (10) ent g5 (7) enp g6 (2) clk (3) a (4) b (5) c (6) d (15) rco (14) q a (11) q d m4 (down) 2,3,5,6+/c7 (12) q c (13) q b 1,7d (1) (2) (4) (8) 3,5ct = 15 m2 (count) 2,3,5,6- 4,5ct = 0 note: 1. logic symbol in accordance with ansi/ieee std 91-1984 and iec publication 617-12. output load enp ent u/ d clk count up h l l h count down h l l l load preset l x x x inhibit h h h x x h x x x x
121 radhard msi logic ut54acs169/ut54acts169 logic diagram c c c c d d d d (14) (13) (12) (11) q 0 q 1 q 2 q 3 (15) rco d c b a (10) (7) (9) (1) (3) (4) (5) (6) ent load u/ d enp clk q q q q q q q q (2)
radhard msi logic 122 ut54acs169/ut54acts169 radiation hardness specifications 1 notes: 1. logic will not latchup during radiation exposure within the limits defined in the table. 2. device storage elements are immune to seu affects. absolute maximum ratings note: 1. stresses outside the listed absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. exposure to absolute ma ximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter limit units total dose 1.0e6 rads(si) seu threshold 2 80 mev-cm 2 /mg sel threshold 120 mev-cm 2 /mg neutron fluence 1.0e14 n/cm 2 symbol parameter limit units v dd supply voltage -0.3 to 7.0 v v i/o voltage any pin -.3 to v dd +.3 v t stg storage temperature range -65 to +150 c t j maximum junction temperature +175 c t ls lead temperature (soldering 5 seconds) +300 c jc thermal resistance junction to case 20 c/w i i dc input current ma p d maximum power dissipation 1 w symbol parameter limit units v dd supply voltage 4.5 to 5.5 v v in input voltage any pin 0 to v dd v t c temperature range -55 to + 125 c
123 radhard msi logic ut54acs169/ut54acts169 7 (v = 5.0v 10%; v ss = 0v 6 , -55 c < t c c) symbol parameter condition min max unit v il low-level input voltage 1 acts acs 0.8 .3v dd v v ih high-level input voltage 1 acts acs .5v dd .7v dd v i in input leakage current acts/acs v in = v dd or v ss -1 1 v ol 3 acts i ol i ol a 0.40 0.25 v v oh high-level output voltage 3 acts acs i oh = -8.0ma i oh = -100 .7v dd dd -0.25 i os 2 ,4 v o dd and v -200 200 i ol 10 (sink) in = v or v ss ol = 0.4v ma i output current 10 v in dd or v v oh dd - 0.4v ma p power dissipation 2, 8, 9 l = 50pf mw/mhz i quiescent supply current v = 5.5v 10 a i ddq acts for input under test in = v - 2.1v for all other inputs in = v or v ss dd = 5.5v ma c input capacitance 5 = 1mhz @ 0v 15 pf c out output capacitance 5 = 1mhz @ 0v 15
radhard msi logic 124 ut54acs169/ut54acts169 notes: 1.functional tests are conducted in accordance with mil-std-883 with the following input test conditions: v ih = v ih (min) + 20%, - 0%; v il = v il (max) + 0%, - 50%, as specified herein, for ttl, cmos, or schmitt compatible inputs. devices may be tested using any input voltage within th e above specified range, but are guaranteed to v ih (min) and v il (max). 2. supplied as a design limit but not guaranteed or tested. 3. per mil-prf-38535, for current density 5.0e5 amps/cm 2 , the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pf/mhz. 4. not more than one output may be shorted at a time for maximum duration of one second. 5. capacitance measured for initial qualification and when design changes may affect the value. capacitance is measured between the designated terminal and v ss at frequency of 1mhz and a signal amplitude of 50mv rms maximum. 6. maximum allowable relative shift equals 50mv. 7. all specifications valid for radiation dose 1e6 rads(si). 8. power does not include power contribution of any ttl output sink current. 9. power dissipation specified per switching output. 10. this value is guaranteed based on characterization data, but not tested. ac electrical characteristics 2 (v dd = 5.0v 10%; v ss = 0v 1 , -55 c < t c < +125 c) notes: 1. maximum allowable relative shift equals 50mv. 2. all specifications valid for radiation dose 1e6 rads(si). 3. based on characterization, hold time (t h1 ) of 0ns can be assumed if data setup time (t su1 ) is > 10ns. this is guaranteed, but not tested. symbol parameter minimum maximum unit t plh clk to rco 2 23 ns t phl clk to rco 4 28 ns t plh clk to any q 4 24 ns t phl clk to any q 4 24 ns t plh ent to rco 1 15 ns t phl ent to rco 2 16 ns t plh u/ d to rco 2 16 ns t phl u/ d to rco 2 16 ns f max maximum clock frequency 71 mhz t su1 a, b, c, d setup time before clk 9 ns t su2 load , enp , ent , u/ d setup time before clk 9 ns t h1 data hold time after clk 2 ns t h2 all synchronous inputs hold time after clk 2 ns t w minimum pulse width clk high clk low 7 ns
125 radhard msi logic ut54acs190/ut54acts190 radiation-hardened synchronous 4-bit up-down bcd counters features single down/up count control line look-ahead circuitry enhances speed of cascaded counters fully synchronous in count modes asynchronously presettable with load control radiation-hardened cmos - latchup immune high speed low power consumption single 5 volt supply available qml q or v processes flexible package - 16-pin dip - 16-lead flatpack description the ut54acs190 and the ut54acts190 are synchronous 4- bit reversible up-down bcd decade counters. synchronous counting operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed. synchronous operation eliminates the output counting spikes associated with asynchronous counters. the outputs of the four flip-flops are triggered on a low-to-high- level transition of the clock input if the enable input ( cten ) is low. a logic one applied to cten inhibits counting. the di- rection of the count is determined by the level of the down/up (d/ u ) input. when d/ u is low, the counter counts up and when d/ u is high, it counts down. the counters feature a fully independent clock circuit. changes at control inputs ( cten and d/ u ) that will modify the operating mode have no effect on the contents of the counter until clocking occurs. the counters are fully programmable. the outputs may be pre- set to either logic level by placing a low on the load input and entering the desired data at the data inputs. the output will change to agree with the data inputs independently of the level of the clock input. the asynchronous load allows counters to be used as modulo-n dividers by simply modifying the count length with the preset inputs. if preset to an illegal state, the counter returns to a normal se- quence in one or two counts. pinouts 16-pin dip top view 16-lead flatpack top view two outputs have been made available to perform the cascading function: ripple clock and maximum/minimum (max/min) count. the max/min output produces a high-level output pulse with a duration approximately equal to one complete cycle of the clock while the count is zero (all outputs low) counting down or maximum (9) counting up. the ripple clock output ( rco ) produces a low-level output pulse under those same conditions but only while the clock input is low. the counters easily cascade by feeding the rco to the enable input of the succeeding counter if parallel clocking is used, or to the clock input if parallel enabling is used. use the max/min count output to accomplish look-ahead for high- speed operation. the devices are characterized over full military temperature range of -55 c to +125 c. 1 2 3 4 5 7 6 16 15 14 13 12 10 11 b q b q a cten d/ u q c q d v dd a clk rco max/min c 8 9 v ss d load 1 2 3 4 5 7 6 16 15 14 13 12 10 11 v dd 8 9 b q b q a cten d/ u q c q d a clk rco max/min load c v ss d
radhard msi logic 126 ut54acs190/ut54acts190 function table logic symbol logic diagram function load cten d/ u clk count up h l l count down h l h asynchronous l x x no change h x (4) cten d/ u g ctrdiv 10 clk (15) (1) b c (9) (12) max/min q a q d (6) q (2) q 5d (1) (4) (8) m2 (down) g4 (11) load (13) rco note: 1. logic symbol in accordance with ansi/ieee standard 91-1984 and iec publication 617-12. 7 (14) (5) (15) (4) (1) (10) (13) (12) (3) (2) (6) (7) rco q a q b q c q d (9) (11) load cten clk d/ u max/min a b c d r s j q c k q r j q c k q s r s j q c k q r s j q c k q
127 radhard msi logic ut54acs190/ut54acts190 radiation hardness specifications 1 notes: 1. logic will not latchup during radiation exposure within the limits defined in the table. 2. device storage elements are immune to seu affects. absolute maximum ratings note: 1. stresses outside the listed absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. exposure to absolute ma ximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter limit units total dose 1.0e6 rads(si) seu threshold 2 80 mev-cm 2 /mg sel threshold 120 mev-cm 2 /mg neutron fluence 1.0e14 n/cm 2 symbol parameter limit units v dd supply voltage -0.3 to 7.0 v v i/o voltage any pin -.3 to v dd +.3 v t stg storage temperature range -65 to +150 c t j maximum junction temperature +175 c t ls lead temperature (soldering 5 seconds) +300 c jc thermal resistance junction to case 20 c/w i i dc input current 10 ma p d maximum power dissipation 1 w symbol parameter limit units v dd supply voltage 4.5 to 5.5 v v in input voltage any pin 0 to v dd v t c temperature range -55 to + 125 c
radhard msi logic 128 ut54acs190/ut54acts190 dc electrical characteristics 7 (v dd = 5.0v 10%; v ss = 0v 6 , -55 c < t c < +125 c) symbol parameter condition min max unit v il low-level input voltage 1 acts acs 0.8 .3v dd v v ih high-level input voltage 1 acts acs .5v dd .7v dd v i in input leakage current acts/acs v in = v dd or v ss -1 1 a v ol low-level output voltage 3 acts acs i ol = 8.0ma i ol = 100 a 0.40 0.25 v v oh high-level output voltage 3 acts acs i oh = -8.0ma i oh = -100 a .7v dd v dd - 0.25 v i os short-circuit output current 2 ,4 acts/acs v o = v dd and v ss -200 200 ma i ol output current 10 (sink) v in = v dd or v ss v ol = 0.4v 8 ma i oh output current 10 (source) v in = v dd or v ss v oh = v dd - 0.4v -8 ma p total power dissipation 2, 8, 9 c l = 50pf 2.2 mw/mhz i ddq quiescent supply current v dd = 5.5v 10 a i ddq quiescent supply current delta acts for input under test v in = v dd - 2.1v for all other inputs v in = v dd or v ss v dd = 5.5v 1.6 ma c in input capacitance 5 = 1mhz @ 0v 15 pf c out output capacitance 5 = 1mhz @ 0v 15 pf
129 radhard msi logic ut54acs190/ut54acts190 notes: 1. functional tests are conducted in accordance with mil-std-883 with the following input test conditions: v ih = v ih (min) + 20%, - 0%; v il = v il (max) + 0%, - 50%, as specified herein, for ttl, cmos, or schmitt compatible inputs. devices may be tested using any input voltage within th e above specified range, but are guaranteed to v ih (min) and v il (max). 2. supplied as a design limit but not guaranteed or tested. 3. per mil-prf-38535, for current density 5.0e5 amps/cm 2 , the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pf/mhz. 4. not more than one output may be shorted at a time for maximum duration of one second. 5. capacitance measured for initial qualification and when design changes may affect the value. capacitance is measured between the designated terminal and v ss at frequency of 1mhz and a signal amplitude of 50mv rms maximum. 6. maximum allowable relative shift equals 50mv. 7. all specifications valid for radiation dose 1e6 rads(si). 8. power does not include power contribution of any ttl output sink current. 9. power dissipation specified per switching output. 10. this value is guaranteed based on characterization data, but not tested.
radhard msi logic 130 ut54acs190/ut54acts190 ac electrical characteristics 2 (v dd = 5.0v 10%; v ss = 0v 1 , -55 c < t c < +125 c) notes: 1. maximum allowable relative shift equals 50mv. 2. all specifications valid for radiation dose 1e6 rads(si). 3. based on characterization, hold time (t h2 ) of 0ns can be assumed if data setup time (t su3 ) is > 10ns. this is guaranteed, but not tested. symbol parameter minimum maximum unit t plh load to q n 2 19 ns t phl load to q n 2 22 ns t plh data in to q n 2 19 ns t phl data in to q n 2 21 ns t plh clk to q n 2 18 ns t phl clk to q n 2 20 ns t plh clk to rco 2 16 ns t phl clk to rco 2 16 ns t plh clk to max/min 2 18 ns t phl clk to max/min 2 23 ns t plh d/ u to rco 2 16 ns t phl d/ u to rco 2 18 ns t plh d/ u to max/min 1 14 ns t phl d/ u to max/min 2 18 ns t plh cten to rco 2 12 ns t phl cten to rco 2 16 ns f max maximum clock frequency 71 mhz t su1 cten , d/ u setup time before clk 13 ns t su2 load setup time before clk 2 ns t su3 a, b, c, d setup time before load 7 ns t h1 cten and d/ u hold time after clk 2 ns t h2 3 a, b, c, d hold time after load 2 ns t w minimum pulse width clk high clk low load low 7 ns
131 rad-hard msi logic ut54acs191/ut54acts191 radiation-hardened synchronous 4-bit up-down binary counters features ? single down/up count control line ? look-ahead circuitry enhances speed of cascade counters ? fully synchronous in count modes ? asynchronously presetable with load control ? 1.2 radiation-hardened cmos - latchup immune ? high speed ? low power consumption ? single 5 volt supply ? available qml q or v processes ? flexible package - 16-pin dip - 16-lead flatpack description the ut54acs191 and the ut54acts191 are synchronous 4- bit reversible up-down binary c ounters. synchronous counting operation is provided by having all flip-flops clocked simulta- neously so that the outputs cha nge coincident with each other when so instructed. synchronous operation eliminates the out- put counting spikes associated with asynchronous counters. the outputs of the four flip-fl ops are triggered on a low-to-high- level transition of the clock input if the enable input (cten ) is low. a logic one applied to cten inhibits counting. the di- rection of the count is determined by the level of the down/up (d/u ) input. when d/u is low, the counter counts up and when d/u is high, it counts down. the counters feature a fully independent clock circuit. changes at control inputs (cten and d/u ) that will modify the operating mode have no effect on the contents of the counter until clocking occurs. the counters are fully programmable. the outputs may be preset to either logic level by placing a low on the load input and entering the desired data at the data inputs. the output will change to agree with the data inputs independently of the level of the clock input. the asynchronous load allows counters to be used as modulo-n dividers by simply modifying the count length with the preset inputs. two outputs have been made available to perform the cascading function: ripple clock and maximum/minimum (max/min) count. the max/min output produces a high-level output pulse with a duration approximately equal to one complete cycle of the clock while the count is zero (all outputs low) counting down or maximum (15) counting up. pinouts 16-pin dip top view 16-lead flatpack top view the ripple clock output (rco ) produces a low-level output pulse under those same conditions but only while the clock input is low. the counters easily cascade by feeding the rco to the enable input of the succeeding c ounter if parallel clocking is used, or to the clock input if parallel enabling is used. use the max/min count output to acco mplish look-ahead for high- speed operation. the devices are characterized ov er full military temperature range of -55 c to +125 c. 1 2 3 4 5 7 6 16 15 14 13 12 10 11 b q b q a cten d/u q c q d v dd a clk rco max/min c 8 9 v ss d load 1 2 3 4 5 7 6 16 15 14 13 12 10 11 v dd 89 b q b q a cten d/u q c q d a clk rco max/min load c v ss d
rad-hard msi logic 132 ut54acs191/ut54acts191 function table logic symbol logic diagram function load cten d/u clk count up h l l count down h l h asynchronous reset l x x x no change h h x x (4) cten (5) d/u m3 (up) g1 ctrdiv 16 (14) clk (15) a (1) b (10) c (9) d (12) max/min (3) q a (7) q d 1,2 -/1,3+ (6) q c (2) q b 5d (1) (2) (4) (8) 2(ct=0)z6 m2 (dwn) g4 3(ct=9)z6 (11) load c5 (13) rco 6,1,4 7 note: 1. logic symbol in accordance with ansi/ieee standard 91-1984 and iec publication 617-12. clk d/u cten load (11) (9) (10) (1) (4) s r 1j c1 1k (7) (6) (2) (3) (13) (12) q d q c q b q a max/min rco a b c d (15) (5) (14) s r 1j c1 1k s r 1j c1 1k r 1j c1 1k s q q q q q q q q
133 rad-hard msi logic ut54acs191/ut54acts191 radiation hardness specifications 1 notes: 1. logic will not latchup during radiation ex posure within the limits defined in the table. 2. device storage elements are immune to seu affects. absolute maximum ratings note: 1. stresses outside the listed absolute maximum ratings may cause permanent damage to the device . this is a stress rating only, functional operation of the device at these or any other cond itions beyond limits indicated in the operational sections is not recomm ended. exposure to absolute m aximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter limit units total dose 1.0e6 rads(si) seu threshold 2 80 mev-cm 2 /mg sel threshold 120 mev-cm 2 /mg neutron fluence 1.0e14 n/cm 2 symbol parameter limit units v dd supply voltage -0.3 to 7.0 v v i/o voltage any pin -.3 to v dd +.3 v t stg storage temperature range -65 to +150 c t j maximum junction temperature +175 c t ls lead temperature (soldering 5 seconds) +300 c jc thermal resistance junction to case 20 c/w i i dc input current 10 ma p d maximum power dissipation 1 w symbol parameter limit units v dd supply voltage 4.5 to 5.5 v v in input voltage any pin 0 to v dd v t c temperature range -55 to + 125 c
rad-hard msi logic 134 ut54acs191/ut54acts191 dc electrical characteristics 7 (v dd = 5.0v 10%; v ss = 0v 6 , -55 c < t c < +125 c) symbol parameter condition min max unit v il low-level input voltage 1 acts acs 0.8 .3v dd v v ih high-level input voltage 1 acts acs .5v dd .7v dd v i in input leakage current acts/acs v in = v dd or v ss -1 1 a v ol low-level output voltage 3 acts acs i ol = 8.0ma i ol = 100 a 0.40 0.25 v v oh high-level output voltage 3 acts acs i oh = -8.0ma i oh = -100 a .7v dd v dd - 0.25 v i os short-circuit output current 2 ,4 acts/acs v o = v dd and v ss -200 200 ma i ol output current 10 (sink) v in = v dd or v ss v ol = 0.4v 8 ma i oh output current 10 (source) v in = v dd or v ss v oh = v dd - 0.4v -8 ma p total power dissipation 2, 8, 9 c l = 50pf 2.1 mw/ mhz i ddq quiescent supply current v dd = 5.5v 10 a i ddq quiescent supply current delta acts for input under test v in = v dd - 2.1v for all other inputs v in = v dd or v ss v dd = 5.5v 1.6 ma c in input capacitance 5 ? = 1mhz @ 0v 15 pf c out output capacitance 5 ? = 1mhz @ 0v 15 pf
135 rad-hard msi logic ut54acs191/ut54acts191 notes: 1. functional tests are conducted in accordance with mi l-std-883 with the following input test conditions: v ih = v ih (min) + 20%, - 0%; v il = v il (max) + 0%, - 50%, as specified herein, for ttl, cmos, or schmitt compatible inputs. devices may be tested using any input voltage within t he above specified range, but are guaranteed to v ih (min) and v il (max). 2. supplied as a design limit bu t not guaranteed or tested. 3. per mil-prf-38535, for current density 5.0e5 amps/cm 2 , the maximum product of load capacitance (per ou tput buffer) times frequency should not exceed 3,765 pf/mhz. 4. not more than one output may be shorted at a time for maximum duration of one second. 5. capacitance measured for initial qualifi cation and when design changes may affect the value. capacitance is measured between the designated terminal and v ss at frequency of 1mhz and a signal amplitude of 50mv rms maximum. 6. maximum allowable relative shift equals 50mv. 7. all specifications valid for radiation dose 1e6 rads(si). 8. power does not include power contribution of any ttl output sink current. 9. power dissipation specified per switching output. 10. this value is guaranteed based on characterization data, but not tested.
rad-hard msi logic 136 ut54acs191/ut54acts191 ac electrical characteristics 2 (v dd = 5.0v 10%; v ss = 0v 1 , -55 c < t c < +125 c) notes: 1. maximum allowable relative shift equals 50mv. 2. all specifications valid for radiation dose 1e6 rads(si). 3. based on characterization, hold time (t h2 ) of 0ns can be assumed if data setup time (t su2 ) is > 10ns. this is guaran teed, but not tested. symbol parameter minimum maximum unit t plh load to q n 2 20 ns t phl load to q n 2 22 ns t plh data in to q n 2 23 ns t phl data in to q n 2 19 ns t plh clk to q n 2 17 ns t phl clk to q n 2 22 ns t plh clk to rco 2 12 ns t phl clk to rco 2 15 ns t plh clk to max/min 2 22 ns t phl clk to max/min 2 23 ns t plh d/u to rco 2 16 ns t phl d/u to rco 2 18 ns t plh d/u to max/min 2 15 ns t phl d/u to max/min 2 17 ns t plh cten to rco 2 12 ns t phl cten to rco 2 16 ns f max maximum clock frequency 63 mhz t su1 load , cten , d/u setup time before clk 12 ns t su2 a, b, c, d setup time before load 5 ns t h1 cten and d/u hold time after clk 2 ns t h2 3 a, b, c, d hold time after load 2 ns t w minimum pulse width clk high clk low load low 8 ns
137 radhard msi logic ut54acs193/ut54acts193 radiation-hardened synchronous 4-bit up-down dual clock counters features ? look-ahead circuitry enhances cascaded counters ? fully synchronous in count modes ? parallel asynchronous load for modulo-n count lengths ? asynchronous clear ?1.2 m radiation-hardened cmos (acts193) and .6 m crh cmos process (acs193) - latchup immune ? high speed ? low power consumption ? single 5 volt supply ? available qml q or v processes ? flexible package - 16-pin dip - 16-lead flatpack description the ut54acs193 and the ut54acts193 are synchronous 4- bit, binary reversible up-down binary counters. synchronous operation is provided by having all flip-flops clocked simultaneously so that the output s change coincident with each other when instructed. synchronous operation eliminates the output counting spikes normally associated with asynchronous counters. the outputs of the four flip-fl ops are triggered on a low-to-high- level transition of either count input (up or down). the direc- tion of the counting is determined by which count input is pulsed while the other count input is high. the counters are fully programmable. the outputs may be pre- set to either level by placing a low on the load input and entering the desired data at the data inputs. the output will change to agree with the data inputs independently of the count pulses. asynchronous loading allows the counters to be used as modu- lo-n dividers by simply modifying the count length with the preset inputs. a clear input has been provided th at forces all outputs to the low level when a high level is applied. the clear function is inde- pendent of the count and the load inputs. the counter is designed for efficient cascading without the need for external circuitry. the borrow output (bo ) produces a low- level pulse while the count is zero and the down input is low. similarly, the carry output (co ) produces a low-level pulse while the count is maximum pinouts 16-pin dip top view 16-lead flatpack top view function table function clock up clock down clr load count up h l h count down h l h reset x x h x load preset input x x l l 1 2 3 4 5 7 6 16 15 14 13 12 10 11 b q b q a down up q c q d v dd a clr bo co c 8 9 v ss d load 1 2 3 4 5 7 6 16 15 14 13 12 10 11 v dd 89 b q b q a down up q c q d a clr bo co load c v ss d
radhard msi logic 138 ut54acs193/ut54acts193 logic symbol (14) clr (5) up g1 ct=0 ctrdiv 16 (4) down (15) a (1) b (10) c (9) d (12) (3) q a (7) q d (6) q c (2) q b 3d (1) (2) (4) (8) 2+ g2 (11) load c3 (13) bo 2 ct=0 1- co 1ct=15 note: 1. logic symbol in accordance with ansi/ieee std 91-1984 and iec publi- cation 617-12.
139 radhard msi logic ut54acs193/ut54acts193 logic diagram a down up clr load (15) (4) (5) (1) (10) (9) (14) (11) q (7) (6) (2) (3) (12) (13) b c d bo co d c b a q q q c q r s q c q r s q c q r s q c q r s q
radhard msi logic 140 ut54acs193/ut54acts193 radiation hardness specifications 1 notes: 1. logic will not latchup during radiation ex posure within the limits defined in the table. 2. device storage elements are immune to seu affects. absolute maximum ratings note: 1. stresses outside the listed absolute maximum ratings may cause permanent damage to the device . this is a stress rating only, functional operation of the device at these or any other cond itions beyond limits indicated in the operational sections is not recomm ended. exposure to absolute m aximum rating conditions for extended periods may affect device reliability. parameter limit units total dose 1.0e6 rads(si) seu threshold 2 80 mev-cm 2 /mg sel threshold 120 mev-cm 2 /mg neutron fluence 1.0e14 n/cm 2 symbol parameter limit units v dd supply voltage -0.3 to 7.0 v v i/o voltage any pin -.3 to v dd +.3 v t stg storage temperature range -65 to +150 c t j maximum junction temperature +175 c t ls lead temperature (soldering 5 seconds) +300 c jc thermal resistance junction to case 20 c/w i i dc input current 10 ma p d maximum power dissipation 1 w
141 radhard msi logic ut54acs193/ut54acts193 recommended operating conditions symbol parameter limit units v dd supply voltage 4.5 to 5.5 v v in input voltage any pin 0 to v dd v t c temperature range -55 to + 125 c
radhard msi logic 142 ut54acs193/ut54acts193 dc electrical characteristics 7 (v dd = 5.0v 10%; v ss = 0v 6 , -55 c < t c < +125 c) symbol parameter condition min max unit v il low-level input voltage 1 acts acs 0.8 .3v dd v v ih high-level input voltage 1 acts acs .5v dd .7v dd v i in input leakage current acts/acs v in = v dd or v ss -1 1 a v ol low-level output voltage 3 acts acs i ol = 8.0ma i ol = 100 a 0.40 0.25 v v oh high-level output voltage 3 acts acs i oh = -8.0ma i oh = -100 a .7v dd v dd - 0.25 v i os short-circuit output current 2 ,4 acts/acs v o = v dd and v ss -200 200 ma i ol output current 10 (sink) v in = v dd or v ss v ol = 0.4v 8 ma i oh output current 10 (source) v in = v dd or v ss v oh = v dd - 0.4v -8 ma p total power dissipation 2, 8, 9 c l = 50pf 2.1 mw/ mhz i ddq quiescent supply current v dd = 5.5v 10 a i ddq quiescent supply current delta acts for input under test v in = v dd - 2.1v for all other inputs v in = v dd or v ss v dd = 5.5v 1.6 ma c in input capacitance 5 ? = 1mhz @ 0v 15 pf c out output capacitance 5 ? = 1mhz @ 0v 15 pf
143 radhard msi logic ut54acs193/ut54acts193 notes: 1. functional tests are conducted in accordance with mi l-std-883 with the following input test conditions: v ih = v ih (min) + 20%, - 0%; v il = v il (max) + 0%, - 50%, as specified herein, for ttl, cmos, or schmitt compatible inputs. devices may be tested using any input voltage within t he above specified range, but are guaranteed to v ih (min) and v il (max). 2. supplied as a design limit bu t not guaranteed or tested. 3. per mil-prf-38535, for current density 5.0e5 amps/cm 2 , the maximum product of load capacitance (per ou tput buffer) times frequency should not exceed 3,765 pf/mhz. 4. not more than one output may be shorted at a time for maximum duration of one second. 5. capacitance measured for initial qualifi cation and when design changes may affect the value. capacitance is measured between the designated terminal and v ss at frequency of 1mhz and a signal amplitude of 50mv rms maximum. 6. maximum allowable relative shift equals 50mv. 7. all acts specifications are valid for radiation dose 1e6 rads(si) and all acs specifications are valid for radiation dose 5e5 rads(si). 8. power does not include power contribution of any ttl output sink current. 9. power dissipation specified per switching output. 10. this value is guaranteed based on characterization data, but not tested.
radhard msi logic 144 ut54acs193/ut54acts193 ac electrical characteristics 2 (v dd = 5.0v 10%; v ss = 0v 1 , -55 c < t c < +125 c) notes: 1. maximum allowable relative shift equals 50mv. 2. all acts specifications are valid for radiation dose 1e6 rads(si) and all acs specifications are valid for radiation dose 5e5 rads(si). 3. based on characterization, data hold time (t h3 ) of 0ns can be assumed if data setup time (t su3 ) is > 10ns. this is guaranteed, but not tested. symbol parameter minimum maximum unit t plh up to q n 2 20 ns t phl up to q n 2 24 ns t plh up to co 2 13 ns t phl up to co 2 16 ns t plh down to bo 2 13 ns t phl down to bo 2 16 ns t plh down to q n 2 20 ns t phl down to q n 2 24 ns t plh load to q n 2 22 ns t phl load to q n 2 23 ns t phl clr to q n 2 22 ns f max maximum clock frequency 56 mhz t su1 load inactive setup time before up or down 3 ns t su2 clr inactive setup time before up or down 3 ns t su3 a, b, c, d setup time before load 6 ns t h1 up high hold time after down 20 ns t h2 down high hold time after up 20 ns t h3 3 a, b, c, d hold time after load 2 ns t w minimum pulse width up high or low down high or low load low clr high 9 ns
145 radhard msi logic ut54acts220 clock and wait-state generation circuit features 1.2m radiation-hardened cmos - latchup immune high speed low power consumption single 5-volt supply available qml q or v processes flexible package - 14-pin dip - 14-lead flatpack description the ut54acts220 is designed to be a companion chip to utmc?s ut69151 s m mmit family for the purpose of gener- ating clock and wait-state signals. the device contains a divide by two circuit that accepts ttl input levels and drives cmos output buffers. the chip accepts a 48mhz clock and generates a 24mhz clock. the 48mhz clock can have a duty cycle that varies by 20%. the ut54act220 generates a 24mhz clock with a 5% duty cycle variation. the wait-state circuit generates a single wait-state by delaying the falling edge of dtack into the s m mmit. the clock/timing device generates dtack from the falling edge of input rcs which is synchronized by the falling edge of 24mhz. the s m mmit drives inputs rcs and dmack . the devices are characterized over full military temperature range of -55 c to +125 c. logic symbol pinouts 14-pin dip top view 14-lead flatpack top view 1 14 2 13 3 12 4 11 5 10 6 9 7 8 nc clkout clkout clkin nc 48mhz v ss v dd 24mhz dtack mrst rcs dmack test 1 14 2 13 3 12 4 11 5 10 6 9 7 8 nc clkout clkout clkin nc 48mhz v ss v dd 24mhz dtack mrst rcs dmack test (10) mrst (8) dmack (6) 48mhz (9) rcs (13) 24mhz (11) (12) dtack (4) clkin (2) clkout (3) clkout s ctr1 srg2 1d s test note: 1. logic symbol in accordance with ansi/ieee std 91-1984 and iec publication 617-12.
radhard msi logic 146 ut54acts220 pin description functional timing: single s m mmit wait-state for both read and write memory cycles, dtack is an input to the s m mmit e and s m mmit lxe/dxe. a non-wait state mem- ory requires two clock cycles, t 1 and t 2 of figure 1. for accessing slower memory devices, the ut54acts220 holds dtack to a logical ?1?. this results in the stretching of memory cycles by one clock to three clock cycles, t w of figure 1. the s m mmit e and s m mmit lxe/dxe samples the dtack on the rising edge of the 24 mhz clock. if dtack is not generated before the ris- ing edge of the clock, the s m mmit e and s m mmit lxe/dxe extends the memory cycle. pin number pin name description 2 clkout buffered version of clkin. 3 clkout inverted version of clkin. 4 clkin clock input. this signal can be any arbitrary signal that the user wishes to buffer. 6 48mhz 48mhz clock. the 24mhz clock is created by dividing this signal by two. 8 dmack dma acknowledge. this input is generated by the s m mmit. when high, this signal will cause dtack output to be forced high. 9 rcs ram chip select. this input is generated by the s m mmit. 10 mrst master reset. this input can be used to preset 24mhz, dtack and test. for normal operation tie mrst to v dd through a resistor. 11 test test output signal. 12 dtack data transfer acknowledge. this signal can be used to drive the dtack signal of the s m mmit if the user requires one wait state during the memory transfer. 13 24mhz 24mhz clock. this output runs at half the frequency of the 48mhz input. the falling edge of 24mhz is the signal that latches the dtack outputs. 24mhz is forced high whenever mrst is low. properly loaded, 24mhz will have a 50% duty cycle 5%. 48mhz 24mhz t 1 t 2 dmack rcs dtack t w figure 1. functional timing
147 radhard msi logic ut54acts220 logic diagram clkin clkout clkout dtack dmack rcs mrst 48mhz 24mhz ck d rst q ck d pre q q ck d pre q q q test
radhard msi logic 148 ut54acts220 radiation hardness specifications notes: 1. device storage elements are immune to seu affects. 2. not tested, inherent of cmos technology. absolute maximum ratings note: 1.stresses outside the listed absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, f unctional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. exposure to absolute ma ximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter limit units total dose 1.0e6 rad(si) seu threshold 1 80 mev-cm 2 /mg sel threshold >120 mev-cm 2 /mg neutron fluence 2 1.0e14 n/cm 2 symbol parameter limit units v dd supply voltage -0.3 to 7.0 v v i/o voltage any pin -0.3 to v dd +0.3 v t stg storage temperature range -65 to +150 c t j maximum junction temperature +175 c t ls lead temperature (soldering 5 seconds) +300 c q jc thermal resistance junction to case 20 c/w i i dc input current 10 ma p d maximum power dissipation 1 w symbol parameter limit units v dd supply voltage 4.5 to 5.5 v v in input voltage any pin 0 to v dd v t c temperature range -55 to + 125 c 48mhz duty cycle 50 20% mhz
149 radhard msi logic ut54acts220 dc electrical characteristics 7 (v dd = 5.0v 10%; v ss = 0v 6 , -55 c < t c < +125 c) symbol parameter condition min max unit v il low-level input voltage 1 ttl 0.8 v v ih high-level input voltage 1 ttl 2.25v dd v i in input leakage current ttl v dd = 5.5v v in = v dd or v ss -1 1 m a v ol1 low-level output voltage 3 except clkout/ clkout i ol = 8ma, v dd = 4.5v i ol = 100 m a 0.4 0.25 v v oh1 high-level output voltage 3 except clkout/ clkout i oh = -8ma, v dd = 4.5v 3.15v dd v v ol2 clkout/ clkout low-level output voltage 3 i ol = 100 m a 0.25 v v oh2 clkout/ clkout high-level output voltage 3 i oh = -100 m a v dd 4.25 v i os short-circuit output current 2 ,4 v o = v dd and v ss v dd = 5.5v +300 ma i ol1 output current 10 (sink), except clkout/ clkout v in = v dd or v ss v ol = 0.4v 8 ma i oh1 output current 10 (source), except clkout/ clkout v in = v dd or v ss v oh = v dd - 0.4v -8 ma i ol2 clkout/ clkout output current 10 (sink) v in = v dd or v ss v ol = 0.4v 12 ma i oh2 clkout/ clkout output current 10 (source) v in = v dd or v ss v oh = v dd - 0.4v -12 ma i ih input current high v in = v dd or v ss v in = 5.5v +1.0 m a i il input current low v in = v dd or v ss v in = v ss -1.0 m a p total power dissipation 2, 8, 9 c l = 50pf 1.0 mw/ mhz i ddq quiescent supply current v dd = 5.5v v in = v dd or v ss 10 m a
radhard msi logic 150 ut54acts220 notes: 1. functional tests are conducted in accordance with mil-std-883 with the following input test conditions: v ih = v ih (min) + 20%, - 0%; v il = v il (max) + 0%, - 50%, as specified herein, for ttl, cmos, or schmitt compatible inputs. devices may be tested using any input voltage within th e above specified range, but are guaranteed to v ih (min) and v il (max). 2. supplied as a design limit but not guaranteed or tested. 3. per mil-prf-38535, for current density 5.0e5 amps/cm 2 , the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pf/mhz. 4. not more than one output may be shorted at a time for maximum duration of one second. 5. capacitance measured for initial qualification and when design changes may affect the value. capacitance is measured between the designated terminal and v ss at frequency of 1mhz and a signal amplitude of 50mv rms maximum. 6. maximum allowable relative shift equals 50mv. 7. all specifications valid for radiation dose 1e6 rads(si). 8. power does not include power contribution of any ttl output sink current. 9. power dissipation specified per switching output. 10. this value is guaranteed based on characterization data, but not tested. d i ddq quiescent supply current delta for input under test v in = v dd - 2.1v for all other inputs v in = v dd or v ss v dd = 5.5v 1.6 ma c in input capacitance 5 | = 1mhz @ 0v 15 pf c out output capacitance 5 | = 1mhz @ 0v 15 pf
151 radhard msi logic ut54acts220 ac electrical diagram 24mhz t w t 2 rcs dtack t phl or t plh t su t h or clkout clkin clkout t sur t w t 1 48mhz
radhard msi logic 152 ut54acts220 ac electrical characteristics 2 (v dd = 5.0v 10%; v ss = 0v 1 , -55 c < t c < +125 c) notes: 1. maximum allowable relative shift equals 50mv. 2. all specifications valid for radiation dose 1e6 rads(si). 3. guaranteed by design but not tested. symbol parameter minimum maximum unit t phl 1 48mhz - to 24mhz 0 15 ns t plh 1 48mhz - to 24mhz - 0 15 ns t phl 2 24mhz to dtack 0 7 ns t plh 2 24mhz to dtack - 0 6 ns t plh 3 dmack - to dtack - 3 16 ns t plh 4 mrst to 24mhz - , dtack - 3 16 ns t phl 5 clkin to clkout 0 11 ns t plh 5 clkin - to clkout - 0 11 ns t phl 6 clkin - to clkout 0 11 ns t plh 6 clkin to clkout - 0 11 ns t su 3 dtack to 24mhz -, setup time 12 ns t h 3 24mhz - to dtack -, hold time 20 ns t sur setup time from rcs to 24mhz 7 ns t wm mrst pulse width low 5 ns t wc clkin pulse width 12 ns f max maximum clkin frequency 40 mhz
153 radhard msi logic ut54acs240/ut54acts240 radiation-hardened octal buffers & line drivers, inverted three-state outputs features three-state outputs drive bus lines or buffer memory address registers radiation-hardened cmos - latchup immune high speed low power consumption single 5 volt supply available qml q or v processes flexible package - 20-pin dip - 20-lead flatpack description the ut54acs240 and the ut54acts240 are inverting octal buffer and line drivers which improve the performance and den- sity of three-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. the devices are characterized over full military temperature range of -55 c to +125 c. function table logic symbol pinouts 20-pin dip top view 20-lead flatpack top view inputs output 1g , 2g a y l l h l h l h x z (1) 1 g en (2) 1a1 (4) 1a2 (6) 1a3 (8) 1a4 (18) 1y1 (12) 1y4 (14) (16) 1y2 (19) 2g en (11) 2a1 (13) 2a2 (15) 2a3 (17) 2a4 (9) 2y1 (3) 2y4 (5) 2y3 (7) 2y2 note: 1. logic symbol in accordance with ansi/ieee std 91-1984 and iec publication 617-12. 1y3 1g 1a1 2y4 1a2 2y3 1a3 2y2 v dd 2g 1y1 2a4 1y2 1y3 1a4 2a2 2a3 2y1 1y4 v ss 2a1 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 1g 1a1 2y4 1a2 2y3 1a3 2y2 v dd 2g 1y1 2a4 1y2 1y3 1a4 2a2 2a3 2y1 1y4 v ss 2a1 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11
radhard msi logic 154 ut54acs240/ut54acts240 logic diagram radiation hardness specifications 1 notes: 1. logic will not latchup during radiation exposure within the limits defined in the table 2. device storage elements are immune to seu affects. absolute maximum ratings note: 1. stresses outside the listed absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. exposure to absolute ma ximum rating conditions for extended periods may affect device reliability. parameter limit units total dose 1.0e6 rads(si) seu threshold 2 80 mev-cm 2 /mg sel threshold 120 mev-cm 2 /mg neutron fluence 1.0e14 n/cm 2 1a1 1a2 1a3 1a4 1 g (2) (4) (6) (8) (1) (16) (14) (12) (18) 1y1 1y2 1y3 1y4 2a1 2a2 2a3 2a4 2g (11) (13) (15) (17) (19) (7) (5) (3) (9) 2y1 2y2 2y3 2y4 symbol parameter limit units v dd supply voltage -0.3 to 7.0 v v i/o voltage any pin -.3 to v dd +.3 v t stg storage temperature range -65 to +150 c t j maximum junction temperature +175 c t ls lead temperature (soldering 5 seconds) +300 c jc thermal resistance junction to case 20 c/w i i dc input current 10 ma p d maximum power dissipation 1 w
155 radhard msi logic ut54acs240/ut54acts240 recommended operating conditions symbol parameter limit units v dd supply voltage 4.5 to 5.5 v v in input voltage any pin 0 to v dd v t c temperature range -55 to + 125 c
radhard msi logic 156 ut54acs240/ut54acts240 dc electrical characteristics 7 (v dd = 5.0v 10%; v ss = 0v 6 , -55 c < t c < +125 c) symbol parameter condition min max unit v il low-level input voltage 1 acts acs 0.8 .3v dd v v ih high-level input voltage 1 acts acs .5v dd .7v dd v i in input leakage current acts/acs v in = v dd or v ss -1 1 a v ol low-level output voltage 3 acts acs i ol = 12.0ma i ol = 100 a 0.40 0.25 v v oh high-level output voltage 3 acts acs i oh = -12.0ma i oh = -100 a .7v dd v dd - 0.25 v i oz three-state output leakage current v o = v dd and v ss -30 30 a i os short-circuit output current 2 ,4 acts/acs v o = v dd and v ss -300 300 ma i ol output current 10 (sink) v in = v dd or v ss v ol = 0.4v 12 ma i oh output current 10 (source) v in = v dd or v ss v oh = v dd - 0.4v -12 ma p total power dissipation 2, 8, 9 c l = 50pf 2.1 mw/ mhz i ddq quiescent supply current v dd = 5.5v 10 a i ddq quiescent supply current delta acts for input under test v in = v dd - 2.1v for all other inputs v in = v dd or v ss v dd = 5.5v 1.6 ma c in input capacitance 5 = 1mhz @ 0v 15 pf c out output capacitance 5 = 1mhz @ 0v 15 pf
157 radhard msi logic ut54acs240/ut54acts240 notes: 1. functional tests are conducted in accordance with mil-std-883 with the following input test conditions: v ih = v ih (min) + 20%, - 0%; v il = v il (max) + 0%, - 50%, as specified herein, for ttl, cmos, or schmitt compatible inputs. devices may be tested using any input voltage within th e above specified range, but are guaranteed to v ih (min) and v il (max). 2. supplied as a design limit but not guaranteed or tested. 3. per mil-prf-38535, for current density 5.0e5 amps/cm 2 , the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pf/mhz. 4. not more than one output may be shorted at a time for maximum duration of one second. 5. capacitance measured for initial qualification and when design changes may affect the value. capacitance is measured between the designated terminal and v ss at frequency of 1mhz and a signal amplitude of 50mv rms maximum. 6. maximum allowable relative shift equals 50mv. 7. all specifications valid for radiation dose 1e6 rads(si). 8. power does not include power contribution of any ttl output sink current. 9. power dissipation specified per switching output. 10. this value is guaranteed based on characterization data, but not tested.
radhard msi logic 158 ut54acs240/ut54acts240 ac electrical characteristics 2 (v dd = 5.0v 10%; v ss = 0v 1 , -55 c < t c < +125 c) notes: 1. maximum allowable relative shift equals 50mv. 2. all specifications valid for radiation dose 1e6 rads(si). symbol parameter minimum maximum unit t plh input to yn 1 10 ns t phl input to yn 1 13 ns t pzl g low to yn active 1 11 ns t pzh g low to yn active 2 13 ns t plz g high to yn three-state 2 11 ns t phz g high to yn three-state 2 14 ns
159 radhard msi logic ut54acs244/ut54acts244 radiation-hardened octal buffers & line drivers, three-state outputs features three-state outputs drive bus lines or buffer memory address registers radiation-hardened cmos - latchup immune high speed low power consumption single 5 volt supply available qml q or v processes flexible package - 20-pin dip - 20-lead flatpack description the ut54acs244 and the ut54acts244 are non-inverting octal buffer and line drivers which improve the performance and density of three-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. the devices are characterized over full military temperature range of -55 c to +125 c. function table logic symbol pinouts 20-pin dip top view 20-lead flatpack top view inputs output 1g , 2g a y l l l l h h h x z (1) 1 g en (2) 1a1 (4) 1a2 (6) 1a3 (8) 1a4 (18) 1y1 (12) 1y4 (14) 1y3 (16) 1y2 (19) 2g en (11) 2a1 (13) 2a2 (15) 2a3 (17) 2a4 (9) 2y1 (3) 2y4 (5) 2y3 (7) 2y2 note: 1. logic symbol in accordance with ansi/ieee std 91-1984 and iec publication 617-12. 1g 1a1 2y4 1a2 2y3 1a3 2y2 v dd 2g 1y1 2a4 1y2 1y3 1a4 2a2 2a3 2y1 1y4 v ss 2a1 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 1g 1a1 2y4 1a2 2y3 1a3 2y2 v dd 2g 1y1 2a4 1y2 1y3 1a4 2a2 2a3 2y1 1y4 v ss 2a1 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11
radhard msi logic 160 ut54acs244/ut54acts244 logic diagram radiation hardness specifications 1 notes: 1. logic will not latchup during radiation exposure within the limits defined in the table 2. device storage elements are immune to seu affects. absolute maximum ratings note: 1. stresses outside the listed absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. exposure to absolute ma ximum rating conditions for extended periods may affect device reliability. parameter limit units total dose 1.0e6 rads(si) seu threshold 2 80 mev-cm 2 /mg sel threshold 120 mev-cm 2 /mg neutron fluence 1.0e14 n/cm 2 1a1 1a2 1a3 1a4 1 g (2) (4) (6) (8) (1) (16) (14) (12) (18) 1y1 1y2 1y3 1y4 2a1 2a2 2a3 2a4 2 g (11) (13) (15) (17) (19) (7) (5) (3) (9) 2y1 2y2 2y3 2y4 symbol parameter limit units v dd supply voltage -0.3 to 7.0 v v i/o voltage any pin -.3 to v dd +.3 v t stg storage temperature range -65 to +150 c t j maximum junction temperature +175 c t ls lead temperature (soldering 5 seconds) +300 c jc thermal resistance junction to case 20 c/w i i dc input current 10 ma p d maximum power dissipation 1 w
161 radhard msi logic ut54acs244/ut54acts244 recommended operating conditions symbol parameter limit units v dd supply voltage 4.5 to 5.5 v v in input voltage any pin 0 to v dd v t c temperature range -55 to + 125 c
radhard msi logic 162 ut54acs244/ut54acts244 dc electrical characteristics 7 (v dd = 5.0v 10%; v ss = 0v 6 , -55 c < t c < +125 c) symbol parameter condition min max unit v il low-level input voltage 1 acts acs 0.8 .3v dd v v ih high-level input voltage 1 acts acs .5v dd .7v dd v i in input leakage current acts/acs v in = v dd or v ss -1 1 a v ol low-level output voltage 3 acts acs i ol = 12.0ma i ol = 100 a 0.40 0.25 v v oh high-level output voltage 3 acts acs i oh = -12.0ma i oh = -100 a .7v dd v dd - 0.25 v i ol output current 10 (sink) v in = v dd or v ss v ol = 0.4v 12 ma i oh output current 10 (source) v in = v dd or v ss v oh = v dd - 0.4v -12 ma i oz three-state output leakage current v o = v dd and v ss -30 30 a i os short-circuit output current 2 ,4 acts/acs v o = v dd and v ss -300 300 ma p total power dissipation 2,8,9 c l = 50pf 2.0 mw/ mhz i ddq quiescent supply current v dd = 5.5v 10 a i ddq quiescent supply current delta acts for input under test v in = v dd - 2.1v for all other inputs v in = v dd or v ss v dd = 5.5v 1.6 ma c in input capacitance 5 = 1mhz @ 0v 15 pf c out output capacitance 5 = 1mhz @ 0v 15 pf
163 radhard msi logic ut54acs244/ut54acts244 notes: 1. functional tests are conducted in accordance with mil-std-883 with the following input test conditions: v ih = v ih (min) + 20%, - 0%; v il = v il (max) + 0%, - 50%, as specified herein, for ttl, cmos, or schmitt compatible inputs. devices may be tested using any input voltage within th e above specified range, but are guaranteed to v ih (min) and v il (max). 2. supplied as a design limit but not guaranteed or tested. 3. per mil-prf-38535, for current density 5.0e5 amps/cm 2 , the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pf/mhz. 4. not more than one output may be shorted at a time for maximum duration of one second. 5. capacitance measured for initial qualification and when design changes may affect the value. capacitance is measured between the designated terminal and v ss at frequency of 1mhz and a signal amplitude of 50mv rms maximum. 6. maximum allowable relative shift equals 50mv. 7. all specifications valid for radiation dose 1e6 rads(si). 8. power does not include power contribution of any ttl output sink current. 9. power dissipation specified per switching output. 10. this value is guaranteed based on characterization data, but not tested.
radhard msi logic 164 ut54acs244/ut54acts244 ac electrical characteristics 2 (v dd = 5.0v 10%; v ss = 0v 1 , -55 c < t c < +125 c) notes: 1. maximum allowable relative shift equals 50mv. 2. all specifications valid for radiation dose 1e6 rads(si). symbol parameter minimum maximum unit t plh input to yn 1 11 ns t phl input to yn 1 11 ns t pzl g low to yn active 2 12 ns t pzh g low to yn active 2 12 ns t plz g high to yn three-state 2 12 ns t phz g high to yn three-state 2 12 ns
165 radhard msi logic ut54acs245/ut54acts245 radiation-hardened octal bus transceiver with three-state outputs features three-state outputs drive bus line directly radiation-hardened cmos - latchup immune high speed low power consumption single 5 volt supply available qml q or v processes flexible package - 20-pin dip - 20-lead flatpack description the ut54acs245 and the ut54acts245 are non-inverting octal bus transceivers designed for asynchronous two-way com- munication between data buses. the control function imple- mentation minimizes external timing requirements. the devices allow data transmission from the a bus to the b bus or from the b bus to the a bus depending upon the logic level at the direction control (dir) input. the enable input ( g ) dis- ables the device so that the buses are effectively isolated. the devices are characterized over full military temperature range of -55 c to +125 c. function table pinouts 20-pin dip top view 20-lead flatpack top view logic symbol enable g direction control dir operation l l b data to a bus l h a data to b bus h x isolation 1 2 3 4 5 7 6 20 19 18 17 16 14 15 dir a1 a2 a3 a4 a5 a6 v dd g b1 b2 b3 b5 8 13 a7 b6 b4 9 12 a8 b7 10 11 v ss b8 1 2 3 4 5 7 6 20 19 18 17 16 14 15 dir a1 a2 a3 a4 a5 a6 v dd g b1 b2 b3 b5 8 13 a7 b6 b4 9 12 a8 b7 10 11 v ss b8 (19) g g3 (2) a1 (3) a2 (4) (18) b1 (16) (17) b2 note: 1. logic symbol in accordance with ansi/ieee std 91-1984 and iec publication 617-12. a3 (5) a4 (6) a5 (7) a6 b3 (13) b6 (14) b5 (15) b4 (8) a7 (9) a8 (11) b8 (12) b7 (1) dir 3 en1 (ba) 3 en2 (ab) 1 2
radhard msi logic 166 ut54acs245/ut54acts245 logic diagram a1 a2 a3 a4 a5 a6 a7 a8 dir (1) (2) (19) (18) (3) (17) (4) (16) (5) (15) (6) (14) (7) (13) (8) (12) (9) (11) b1 b2 b3 b6 b5 b4 b8 b7 g
167 radhard msi logic ut54acs245/ut54acts245 radiation hardness specifications 1 notes: 1. logic will not latchup during radiation exposure within the limits defined in the table. 2. device storage elements are immune to seu affects. absolute maximum ratings note: 1. stresses outside the listed absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. exposure to absolute ma ximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter limit units total dose 1.0e6 rads(si) seu threshold 2 80 mev-cm 2 /mg sel threshold 120 mev-cm 2 /mg neutron fluence 1.0e14 n/cm 2 symbol parameter limit units v dd supply voltage -0.3 to 7.0 v v i/o voltage any pin -.3 to v dd +.3 v t stg storage temperature range -65 to +150 c t j maximum junction temperature +175 c t ls lead temperature (soldering 5 seconds) +300 c jc thermal resistance junction to case 20 c/w i i dc input current 10 ma p d maximum power dissipation 1 w symbol parameter limit units v dd supply voltage 4.5 to 5.5 v v in input voltage any pin 0 to v dd v t c temperature range -55 to + 125 c
radhard msi logic 168 ut54acs245/ut54acts245 dc electrical characteristics 7 (v dd = 5.0v 10%; v ss = 0v 6 , -55 c < t c < +125 c) symbol parameter condition min max unit v il low-level input voltage 1 acts acs 0.8 .3v dd v v ih high-level input voltage 1 acts acs .5v dd .7v dd v i in input leakage current acts/acs v in = v dd or v ss -1 1 a v ol low-level output voltage 3 acts acs i ol = 12.0ma i ol = 100 a 0.40 0.25 v v oh high-level output voltage 3 acts acs i oh = -12.0ma i oh = -100 a .7v dd v dd - 0.25 v i oz three-state output leakage current v o = v dd and v ss -30 30 a i os short-circuit output current 2 ,4 acts/acs v o = v dd and v ss -300 300 ma i ol output current 10 (sink) v in = v dd or v ss v ol = 0.4v 12 ma i oh output current 10 (source) v in = v dd or v ss v oh = v dd - 0.4v -12 ma p total power dissipation 2, 8, 9 c l = 50pf 2.0 mw/mhz i ddq quiescent supply current v dd = 5.5v 10 a i ddq quiescent supply current delta acts for input under test v in = v dd - 2.1v for all other inputs v in = v dd or v ss v dd = 5.5v 1.6 ma c in input capacitance 5 = 1mhz @ 0v 15 pf c out output capacitance 5 = 1mhz @ 0v 15 pf
169 radhard msi logic ut54acs245/ut54acts245 notes: 1. functional tests are conducted in accordance with mil-std-883 with the following input test conditions: v ih = v ih (min) + 20%, - 0%; v il = v il (max) + 0%, - 50%, as specified herein, for ttl, cmos, or schmitt compatible inputs. devices may be tested using any input voltage within th e above specified range, but are guaranteed to v ih (min) and v il (max). 2. supplied as a design limit but not guaranteed or tested. 3. per mil-prf-38535, for current density 5.0e5 amps/cm 2 , the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pf/mhz. 4. not more than one output may be shorted at a time for maximum duration of one second. 5. capacitance measured for initial qualification and when design changes may affect the value. capacitance is measured between the designated terminal and v ss at frequency of 1mhz and a signal amplitude of 50mv rms maximum. 6. maximum allowable relative shift equals 50mv. 7. all specifications valid for radiation dose 1e6 rads(si). 8. power does not include power contribution of any ttl output sink current. 9. power dissipation specified per switching output. 10. this value is guaranteed based on characterization data, but not tested.
radhard msi logic 170 ut54acs245/ut54acts245 ac electrical characteristics 2 (v dd = 5.0v 10%; v ss = 0v 1 , -55 c < t c < +125 c) notes: 1. maximum allowable relative shift equals 50mv. 2. all specifications valid for radiation dose 1e6 rads(si) symbol parameter minimum maximum unit t plh data to bus 1 11 ns t phl data to bus 1 15 ns t pzl g low to bus active 2 12 ns t pzh g low to bus active 2 12 ns t plz g high to bus three-state 2 12 ns t phz g high to bus three-state 2 12 ns
177 radhard msi logic ut54acs253/ut54acts253 radiation-hardened dual 4-input multiplexers, three-state outputs features permits multiplexing from n lines to 1 line performs parallel-to-serial conversion radiation-hardened cmos - latchup immune high speed low power consumption single 5 volt supply available qml q or v processes flexible package - 16-pin dip - 16-lead flatpack description the ut54acs253 and the ut54acts253 are 1-line to 4-line multiplexers that contain drivers to supply full binary decoding. separate output control inputs are provided for each of the two four-line sections. use the three-state outputs to drive data lines in bus-organized systems. with all but one of the common outputs disabled the low-impedance of the single enable output will drive the bus line to a high or low logic level. each output has its own strobe ( g ). the devices are characterized over full military temperature range of -55 c to +125 c. function table pinouts 16-pin dip top view 16-lead flatpack top view logic symbol select inputs data inputs output control output b a c0 c1 c2 c3 g y x x x x x x h z l l l x x x l l l l h x x x l h l h x l x x l l l h x h x x l h h l x x l x l l h l x x h x l h h h x x x l l l h h x x x h l h 1 2 3 4 5 7 6 16 15 14 13 12 10 11 1g b 1c3 1c2 1c1 1c0 1y v dd 2g a 2c3 2c2 2c1 2c0 8 9 v ss 2y 1 2 3 4 5 7 6 16 15 14 13 12 10 11 v dd 1g b 1c3 1c2 1c1 1c0 1y 2g a 2c3 2c2 2c1 2c0 v ss 2y 8 9 (14) a (2) b 1 0 mux note: 1. logic symbol in accordance with ansi/ieee std 91-1984 and iec publication 617-12. (1) 1g en (6) 1c0 0 (5) 1c1 (4) 1c2 (3) 1c3 (15) 2g (10) 2c0 (11) 2c1 (7) 1y 2c2 (13) 2c3 (9) 2y (12) 1 2 3 g 0 3 ---
radhard msi logic 178 ut54acs253/ut54acts253 logic diagram (7) 1y (9) 2y (1) (6) (5) (4) (3) (2) (14) (10) (11) (12) (13) 2c3 2c2 2c1 2c0 a b 1c3 1c2 1c1 1c0 1 g (15) output control output control 2g data 1 data 2 select 1g
179 radhard msi logic ut54acs253/ut54acts253 radiation hardness specifications 1 notes: 1. logic will not latchup during radiation exposure within the limits defined in the table. 2. device storage elements are immune to seu affects. absolute maximum ratings note: 1. stresses outside the listed absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. exposure to absolute ma ximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter limit units total dose 1.0e6 rads(si) seu threshold 2 80 mev-cm 2 /mg sel threshold 120 mev-cm 2 /mg neutron fluence 1.0e14 n/cm 2 symbol parameter limit units v dd supply voltage -0.3 to 7.0 v v i/o voltage any pin -.3 to v dd +.3 v t stg storage temperature range -65 to +150 c t j maximum junction temperature +175 c t ls lead temperature (soldering 5 seconds) +300 c jc thermal resistance junction to case 20 c/w i i dc input current 10 ma p d maximum power dissipation 1 w symbol parameter limit units v dd supply voltage 4.5 to 5.5 v v in input voltage any pin 0 to v dd v t c temperature range -55 to + 125 c
radhard msi logic 180 ut54acs253/ut54acts253 dc electrical characteristics 7 (v dd = 5.0v 10%; v ss = 0v 6 , -55 c < t c < +125 c) symbol parameter condition min max unit v il low-level input voltage 1 acts acs 0.8 .3v dd v v ih high-level input voltage 1 acts acs .5v dd .7v dd v i in input leakage current acts/acs v in = v dd or v ss -1 1 a v ol low-level output voltage 3 acts acs i ol = 8.0ma i ol = 100 a 0.40 0.25 v v oh high-level output voltage 3 acts acs i oh = -8.0ma i oh = -100 a .7v dd v dd - 0.25 v i os short-circuit output current 2 ,4 acts/acs v o = v dd and v ss -200 200 ma i oz three-state output leakage current v o = v dd and v ss -20 20 a i ddq quiescent supply current v dd = 5.5v 10 a i ol output current 10 (sink) v in = v dd or v ss v ol = 0.4v 8 ma i oh output current 10 (source) v in = v dd or v ss v oh = v dd - 0.4v -8 ma p total power dissipation 2, 8, 9 c l = 50pf 2.1 mw/ mhz i ddq quiescent supply current v dd = 5.5v 10 a i ddq quiescent supply current delta acts for input under test v in = v dd - 2.1v for all other inputs v in = v dd or v ss v dd = 5.5v 1.6 ma c in input capacitance 5 = 1mhz @ 0v 15 pf c out output capacitance 5 = 1mhz @ 0v 15 pf
181 radhard msi logic ut54acs253/ut54acts253 notes: 1. functional tests are conducted in accordance with mil-std-883 with the following input test conditions: v ih = v ih (min) + 20%, - 0%; v il = v il (max) + 0%, - 50%, as specified herein, for ttl, cmos, or schmitt compatible inputs. devices may be tested using any input voltage within th e above specified range, but are guaranteed to v ih (min) and v il (max). 2. supplied as a design limit but not guaranteed or tested. 3. per mil-prf-38535, for current density 5.0e5 amps/cm 2 , the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pf/mhz. 4. not more than one output may be shorted at a time for maximum duration of one second. 5. capacitance measured for initial qualification and when design changes may affect the value. capacitance is measured between the designated terminal and v ss at frequency of 1mhz and a signal amplitude of 50mv rms maximum. 6. maximum allowable relative shift equals 50mv. 7. all specifications valid for radiation dose 1e6 rads(si). 8. power does not include power contribution of any ttl output sink current. 9. power dissipation specified per switching output. 10. this value is guaranteed based on characterization data, but not tested.
radhard msi logic 182 ut54acs253/ut54acts253 ac electrical characteristics 2 (v dd = 5.0v 10%; v ss = 0v 1 , -55 c < t c < +125 c) notes: 1. maximum allowable relative shift equals 50mv. 2. all specifications valid for radiation dose 1e6 rads(si). symbol parameter minimum maximum unit t plh select to output yn 2 12 ns t phl select to output yn 2 16 ns t plh data to output yn 2 14 ns t phl data to output yn 2 16 ns t pzh g low to yn active 2 12 ns t pzl g low to yn active 1 12 ns t phz g high to yn three-state 2 11 ns t plz g high to yn three-state 2 10 ns
183 radhard msi logic ut54acs264/ut54acts264 radiation-hardened look-ahead carry generators for counters features performs look-ahead carry across n-bit counters accommodates active-high or active-low carry improves cascaded counters system performance radiation-hardened cmos - latchup immune high speed low power consumption single 5 volt supply available qml q or v processes flexible package - 16-pin dip - 16-lead flatpack description the ut54acs264 and the ut54acts264 are look-ahead gen- erators designed specifically to perform a carry-anticipate across any number of n-bit counters, thus increasing system clock frequency. a carry enable ce, and carry outputs rcoa and rcob are provided for n-bit cascading. use the counter with either active-high-carry or active-low-car- ry counters. for active-high-carry counters, ce is active high, the a set of inputs and output rcoa are used. the b set of inputs are connected to a low logic level. for active-low-carry counters, ce is active low, the b set of inputs and output rcob are used. the a set of inputs are connected to a high logic level. the devices are characterized over full military temperature range of -55 c to +125 c. pinouts 16-pin dip top view 16-lead flatpack top view 1 2 3 4 5 7 6 16 15 14 13 12 10 11 a1 b1 a0 b0 a3 b3 rcob v dd b2 a2 ce c0 c1 rcoa 8 9 v ss c2 1 2 3 4 5 7 6 16 15 14 13 12 10 11 v dd a1 b1 a0 b0 a3 b3 rcob b2 a2 ce c0 c1 rcoa v ss c2 8 9
radhard msi logic 184 ut54acs264/ut54acts264 logic symbol notes: 1. logic symbols in accordance with ansi/ieee std 91-1984 and iec publication 617-12. function table for c0 output function table for c1 output function table for rcob output function table for c2 output function table for rcoa output (12) c0 (11) c1 (9) c2 (10) rcoa (7) rcob 1 1 1 1 1 1,3 2,3 1,3,5 2,3,5 4,5 1,3,5,7 2,3,5,7 4,5,7 6,7 1,3,5,7, 4,5,7,9 6,7,9 8,9 1 2 4 6 8 (13) ce (4) b0 (3) a0 (2) b1 (1) a1 (15) b2 (14) a2 (6) b3 (5) a3 g9 z8 g7 z6 g5 z4 g3 z2 z1 active-high inputs (12) c0 (11) c1 (9) c2 (10) rcoa (7) rcob 1 1 1 1 1,2 3 5 3,4 1,2,4 7 5,6 3,4,6 1,2,4,6 9 7,8 5,6,8 3,4,6,8 1,2,4,6,8 (13) ce (4) b0 (3) a0 (2) b1 (1) a1 (15) b2 (14) a2 (6) b3 (5) a3 z9 g8 z7 g6 z5 g4 z3 g2 z1 active-low inputs 1,4,6,8 inputs output a0 b0 ce c0 h h x h h x h h l x x l x l l l inputs output a1 a0 b1 b0 ce c1 h x h x x h h h x h x h h h x x h h l x x x x l x l l x x l x x l l l l inputs output b3 b2 b1 b0 ce rcob h x x x x h x h x x x h x x h x x h x x x h x h x x x x h h l l l l l l inputs output a2 a1 a0 b2 b1 b0 ce c2 h x x h x x x h h h x x h x x h h h h x x h x h h h h x x x h h l x x x x x x l x l x l x x x l x x l l l x x l x x x l l l l l inputs output a3 a2 a1 a0 b3 b2 b1 ce rcoa h x x x h x x x h h h x x x h x x h h h h x x x h x h h h h h x x x h h l x x x x x x x l x l x x l x x x l x x l x l l x x l x x x l l l l x l x x x x l l l l l
185 radhard msi logic ut54acs264/ut54acts264 logic diagram (10) rcoa rcob (7) (9) c2 (11) c1 (12) c0 (13) (6) (5) (15) (14) (2) (1) (4) (3) ce b3 a3 a2 b1 a1 b0 a0 b2
radhard msi logic 186 ut54acs264/ut54acts264 radiation hardness specifications 1 notes: 1. logic will not latchup during radiation exposure within the limits defined in the table. 2. device storage elements are immune to seu affects. absolute maximum ratings note: 1. stresses outside the listed absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. exposure to absolute ma ximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter limit units total dose 1.0e6 rads(si) seu threshold 2 80 mev-cm 2 /mg sel threshold 120 mev-cm 2 /mg neutron fluence 1.0e14 n/cm 2 symbol parameter limit units v dd supply voltage -0.3 to 7.0 v v i/o voltage any pin -.3 to v dd +.3 v t stg storage temperature range -65 to +150 c t j maximum junction temperature +175 c t ls lead temperature (soldering 5 seconds) +300 c jc thermal resistance junction to case 20 c/w i i dc input current 10 ma p d maximum power dissipation 1 w symbol parameter limit units v dd supply voltage 4.5 to 5.5 v v in input voltage any pin 0 to v dd v t c temperature range -55 to + 125 c
187 radhard msi logic ut54acs264/ut54acts264 dc electrical characteristics 7 (v dd = 5.0v 10%; v ss = 0v 6 , -55 c < t c < +125 c) symbol parameter condition min max unit v il low-level input voltage 1 acts acs 0.8 .3v dd v v ih high-level input voltage 1 acts acs .5v dd .7v dd v i in input leakage current acts/acs v in = v dd or v ss -1 1 a v ol low-level output voltage 3 acts acs i ol = 8ma i ol = 100 a 0.40 0.25 v v oh high-level output voltage 3 acts acs i oh = -8ma i oh = -100 a .7v dd v dd - 0.25 v i os short-circuit output current 2 ,4 acts/acs v o = v dd and v ss -200 200 ma i ol output current 10 (sink) v in = v dd or v ss v ol = 0.4v 8 ma i oh output current 10 (source) v in = v dd or v ss v oh = v dd - 0.4v -8 ma p total power dissipation 2, 8, 9 c l = 50pf 2.2 mw/ mhz i ddq quiescent supply current v dd = 5.5v 10 a i ddq quiescent supply current delta acts for input under test v in = v dd - 2.1v for all other inputs v in = v dd or v ss v dd = 5.5v 1.6 ma c in input capacitance 5 = 1mhz @ 0v 15 pf c out output capacitance 5 = 1mhz @ 0v 15 pf
radhard msi logic 188 ut54acs264/ut54acts264 notes: 1. functional tests are conducted in accordance with mil-std-883 with the following input test conditions: v ih = v ih (min) + 20%, - 0%; v il = v il (max) + 0%, - 50%, as specified herein, for ttl, cmos, or schmitt compatible inputs. devices may be tested using any input voltage within th e above specified range, but are guaranteed to v ih (min) and v il (max). 2. supplied as a design limit but not guaranteed or tested. 3. per mil-prf-38535, for current density 5.0e5 amps/cm 2 , the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pf/mhz. 4. not more than one output may be shorted at a time for maximum duration of one second. 5. capacitance measured for initial qualification and when design changes may affect the value. capacitance is measured between the designated terminal and v ss at frequency of 1mhz and a signal amplitude of 50mv rms maximum. 6. maximum allowable relative shift equals 50mv. 7. all specifications valid for radiation dose 1e6 rads(si). 8. power does not include power contribution of any ttl output sink current. 9. power dissipation specified per switching output. 10. this value is guaranteed based on characterization data, but not tested. ac electrical characteristics 2 (v dd = 5.0v 10%; v ss = 0v 1 , -55 c < t c < +125 c) notes: 1. maximum allowable relative shift equals 50mv. 2. all specifications valid for radiation dose 1e6 rads(si). symbol parameter minimum maximum unit t plh ce to c0, c1, c2 1 17 ns t phl ce to c0, c1, c2 1 16 ns t plh an or bn to c0, c1, c2 1 15 ns t phl an or bn to c0, c1, c2 1 17 ns t plh an, bn or ce to rcoa 1 15 ns t phl an, bn or ce to rcoa 1 15 ns t plh bn or ce to rcob 1 12 ns t phl bn or ce to rcob 1 15 ns
189 radhard msi logic ut54acs273/ut54acts273 radiation-hardened octal d-flip-flops with clear features contains eight flip-flops with single-rail outputs buffered clock and direct clear inputs individual data input to each flip-flop applications include: - buffer/storage registers, shift registers, and pattern generators radiation-hardened cmos - latchup immune high speed low power consumption single 5 volt supply available qml q or v processes flexible package - 20-pin dip - 20-lead flatpack description the ut54acs273 and the ut54acts273 are positive-edge- triggered d-type flip-flops with a direct clear input. information at the d inputs meeting the setup time requirements is transferred to the q outputs on the positive-going edge of the clock pulse. when the clock input is at either the high or low level, the d input signal has no effect at the output. the devices are characterized over full military temperature range of -55 c to +125 c. function table pinouts 20-pin dip top view 20-lead flatpack top view logic symbol inputs outputs clr clk d x q x l x x l h h h l h l x h l no change 1 2 3 4 5 7 6 20 19 18 17 16 14 15 clr 1q 1d 2d 2q 3q 3d v dd 8q 8d 7d 7q 6d 8 13 4d 5d 6q 9 12 4q 5q 10 11 v ss clk 1 2 3 4 5 7 6 20 19 18 17 16 14 15 clr 1q 1d 2d 2q 3q 3d v dd 8q 8d 7d 7q 6d 8 13 4d 5d 6q 9 12 4q 5q 10 11 v ss clk (1) clr (11) clk c1 r (3) 1d (4) 2d (2) 1q (6) 3q (9) 4q (12) 5q (15) 6q (16) 7q (19) 8q 1d (7) 3d (8) 4d (13) 5d (14) 6d (17) 7d (18) 8d (5) 2q note: 1. logic symbol in accordance with ansi/ieee standard 91-1984 and iec publication 617-12.
radhard msi logic 190 ut54acs273/ut54acts273 logic diagram radiation hardness specifications 1 notes: 1. logic will not latchup during radiation exposure within the limits defined in the table. 2. device storage elements are immune to seu affects. absolute maximum ratings note: 1. stresses outside the listed absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, fun ctional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. exposure to absolute ma ximum rating conditions for extended periods may affect device reliability. parameter limit units total dose 1.0e6 rads(si) seu threshold 2 80 mev-cm 2 /mg sel threshold 120 mev-cm 2 /mg neutron fluence 1.0e14 n/cm 2 1d (3) 1q (2) 2d (4) 2q (5) 3d (7) 3q (6) 4d (8) 4q (9) 5d (13) 5q (12) 6d (14) 6q (15) 7d (17) 7q (16) 8d (18) 8q (19) c (11) (1) clr clk d r c d r c d r c d r c d r c d r c d r c d r symbol parameter limit units v dd supply voltage -0.3 to 7.0 v v i/o voltage any pin -.3 to v dd +.3 v t stg storage temperature range -65 to +150 c t j maximum junction temperature +175 c t ls lead temperature (soldering 5 seconds) +300 c jc thermal resistance junction to case 20 c/w i i dc input current 10 ma p d maximum power dissipation 1 w
191 radhard msi logic ut54acs273/ut54acts273 recommended operating conditions symbol parameter limit units v dd supply voltage 4.5 to 5.5 v v in input voltage any pin 0 to v dd v t c temperature range -55 to + 125 c
radhard msi logic 192 ut54acs273/ut54acts273 dc electrical characteristics 7 (v dd = 5.0v 10%; v ss = 0v 6 , -55 c < t c < +125 c) symbol parameter condition min max unit v il low-level input voltage 1 acts acs 0.8 .3v dd v v ih high-level input voltage 1 acts acs .5v dd .7v dd v i in input leakage current acts/acs v in = v dd or v ss -1 1 a v ol low-level output voltage 3 acts acs i ol = 8.0ma i ol = 100 a 0.40 0.25 v v oh high-level output voltage 3 acts acs i oh = -8.0ma i oh = -100 a .7v dd v dd - 0.25 v i os short-circuit output current 2 ,4 acts/acs v o = v dd and v ss -200 200 ma i ol output current 10 (sink) v in = v dd or v ss v ol = 0.4v 8 ma i oh output current 10 (source) v in = v dd or v ss v oh = v dd - 0.4v -8 ma p total power dissipation 2, 8, 9 c l = 50pf 1.9 mw/ mhz i ddq quiescent supply current v dd = 5.5v 10 a i ddq quiescent supply current delta acts for input under test v in = v dd - 2.1v for all other inputs v in = v dd or v ss v dd = 5.5v 1.6 ma c in input capacitance 5 = 1mhz @ 0v 15 pf c out output capacitance 5 = 1mhz @ 0v 15 pf
193 radhard msi logic ut54acs273/ut54acts273 notes: 1. functional tests are conducted in accordance with mil-std-883 with the following input test conditions: v ih = v ih (min) + 20%, - 0%; v il = v il (max) + 0%, - 50%, as specified herein, for ttl, cmos, or schmitt compatible inputs. devices may be tested using any input voltage within th e above specified range, but are guaranteed to v ih (min) and v il (max). 2. supplied as a design limit but not guaranteed or tested. 3. per mil-prf-38535, for current density 5.0e5 amps/cm 2 , the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pf/mhz. 4. not more than one output may be shorted at a time for maximum duration of one second. 5. capacitance measured for initial qualification and when design changes may affect the value. capacitance is measured between the designated terminal and v ss at frequency of 1mhz and a signal amplitude of 50mv rms maximum. 6. maximum allowable relative shift equals 50mv. 7. all specifications valid for radiation dose 1e6 rads(si). 8. power does not include power contribution of any ttl output sink current. 9. power dissipation specified per switching output. 10. this value is guaranteed based on characterization data, but not tested.
radhard msi logic 194 ut54acs273/ut54acts273 ac electrical characteristics 2 (v dd = 5.0v 10%; v ss = 0v 1 , -55 c < t c < +125 c) notes: 1. maximum allowable relative shift equals 50mv. 2. all specifications valid for radiation dose 1e6 rads(si). symbol parameter minimum maximum unit t plh clk to q 4 17 ns t phl clk to q 4 19 ns t phl clr to q 5 19 ns f max maximum clock frequency 63 mhz t su1 clr inactive setup time before clk 5 ns t su2 data setup time before clk 5 ns t h data hold time after clk 3 ns t w minimum pulse width clr low clk high clk low 8 ns
195 radhard msi logic ut54acs279/ut54acts279 radiation-hardened quadruple s-r latches features radiation-hardened cmos - latchup immune high speed low power consumption single 5 volt supply available qml q or v processes flexible package - 16-pin dip - 16-lead flatpack description the ut54acs279 and the ut54acts279 contain four basic s - r flip-flop latches. under conventional operation, the s - r inputs are normally held high. when the s input is pulsed low, the q output will be set high. when r is pulsed low, the q output will be reset low. if the s - r inputs are taken low simul- taneously, the q output is unpredictable. the devices are characterized over full military temperature range of -55 c to +125 c. function table note: 1. this configuration is nonstable. it may not persist when the s and r inputs return to their inactive (high) level. logic diagram pinouts 16-pin dip top view 16-lead flatpack top view logic symbol inputs output s r q h h q 0 l h h h l l l l h 1 r s1 s2 q (latches 1 & 3) r s q (latches 2 & 4) 1 2 3 4 5 7 6 16 15 14 13 12 10 11 1 r 1 s1 1 s2 1q 2 r 2 s 2q v dd 4 s 4 r 4q 3 s 2 3 s 1 3 r 8 9 v ss 3q 1 2 3 4 5 7 6 16 15 14 13 12 10 11 v dd 1 r 1 s1 1 s2 1q 2 r 2 s 2q 4 s 4 r 4q 3 s 2 3 s 1 3 r v ss 3q 8 9 1q (4) (7) 2q 3q (9) (13) 4q (1) 1 r note: 1. logic symbol in accordance with ansi/ieee standard 91-1984 and iec publication 617-12. r (2) 1 s 1 s1 (3) 1 s 2 s1 (5) 2 r r (6) 2 s s2 (10) 3 r r (11) 3 s 1 s3 (12) 3 s 2 s3 (14) 4 r r (15) 4 s s4
radhard msi logic 196 ut54acs279/ut54acts279 radiation hardness specifications 1 notes: 1. logic will not latchup during radiation exposure within the limits defined in the table. 2. device storage elements are immune to seu affects. absolute maximum ratings note: 1. stresses outside the listed absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. exposure to absolute ma ximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter limit units total dose 1.0e6 rads(si) seu threshold 2 80 mev-cm 2 /mg sel threshold 120 mev-cm 2 /mg neutron fluence 1.0e14 n/cm 2 symbol parameter limit units v dd supply voltage -0.3 to 7.0 v v i/o voltage any pin -.3 to v dd +.3 v t stg storage temperature range -65 to +150 c t j maximum junction temperature +175 c t ls lead temperature (soldering 5 seconds) +300 c jc thermal resistance junction to case 20 c/w i i dc input current 10 ma p d maximum power dissipation 1 w symbol parameter limit units v dd supply voltage 4.5 to 5.5 v v in input voltage any pin 0 to v dd v t c temperature range -55 to + 125 c
197 radhard msi logic ut54acs279/ut54acts279 dc electrical characteristics 7 (v dd = 5.0v 10%; v ss = 0v 6 , -55 c < t c < +125 c) symbol parameter condition min max unit v il low-level input voltage 1 acts acs 0.8 .3v dd v v ih high-level input voltage 1 acts acs .5v dd .7v dd v i in input leakage current acts/acs v in = v dd or v ss -1 1 a v ol low-level output voltage 3 acts acs i ol = 12.0ma i ol = 100 a 0.40 0.25 v v oh high-level output voltage 3 acts acs i oh = -12.0ma i oh = -100 a .7v dd v dd - 0.25 v i os short-circuit output current 2 ,4 acts/acs v o = v dd and v ss -300 300 ma i ol output current 10 (sink) v in = v dd or v ss v ol = 0.4v 12 ma i oh output current 10 (source) v in = v dd or v ss v oh = v dd - 0.4v -12 ma p total power dissipation 2, 8, 9 c l = 50pf 2.1 mw/ mhz i ddq quiescent supply current v dd = 5.5v 10 a i ddq quiescent supply current delta acts for input under test v in = v dd - 2.1v for all other inputs v in = v dd or v ss v dd = 5.5v 1.6 ma c in input capacitance 5 = 1mhz @ 0v 15 pf c out output capacitance 5 = 1mhz @ 0v 15 pf
radhard msi logic 198 ut54acs279/ut54acts279 notes: 1. functional tests are conducted in accordance with mil-std-883 with the following input test conditions: v ih = v ih (min) + 20%, - 0%; v il = v il (max) + 0%, - 50%, as specified herein, for ttl, cmos, or schmitt compatible inputs. devices may be tested using any input voltage within th e above specified range, but are guaranteed to v ih (min) and v il (max). 2. supplied as a design limit but not guaranteed or tested. 3. per mil-prf-38535, for current density 5.0e5 amps/cm 2 , the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pf/mhz. 4. not more than one output may be shorted at a time for maximum duration of one second. 5. capacitance measured for initial qualification and when design changes may affect the value. capacitance is measured between the designated terminal and v ss at frequency of 1mhz and a signal amplitude of 50mv rms maximum. 6. maximum allowable relative shift equals 50mv. 7. all specifications valid for radiation dose 1e6 rads(si). 8. power does not include power contribution of any ttl output sink current. 9. power dissipation specified per switching output. 10. this value is guaranteed based on characterization data, but not tested. ac electrical characteristics 2 (v dd = 5.0v 10%; v ss = 0v 1 , -55 c < t c < +125 c) notes: 1. maximum allowable relative shift equals 50mv. 2. all specifications valid for radiation dose 1e6 rads(si). symbol parameter minimum maximum unit t plh s to q 1 15 ns t phl s to q 1 18 ns t phl r to q 1 17 ns t w minimum pulse width s low r low 8 ns
199 radhard msi logic ut54acs280/ut54acts280 radiation-hardened 9-bit parity generators/checkers features generates either odd or even parity for nine data lines cascadable for n-bits parity radiation-hardened cmos - latchup immune high speed low power consumption single 5 volt supply available qml q or v processes flexible package - 14-pin dip - 14-lead flatpack description the ut54acs280 and the ut54acts280 are 9-bit parity gen- erators/checkers that use high-performance circuitry and fea- tures odd and even outputs to facilitate operation of either odd or even parity application. the word-length capability is easily expanded by cascading. the devices are characterized over full military temperature range of -55 c to +125 c. function table logic symbol pinouts 14-pin dip top view 14-lead flatpack top view number of inputs a thru i that are high output even odd 0,2,4,6,8 h l 1,3,5,7,9 l h (5) even (6) (8) a note: 1. logic symbol in accordance with ansi/ieee standard 91-1984 and iec publication 617-12. 2k (9) b (10) c (11) d (12) e (13) f (1) g (2) h (4) odd i 1 2 3 4 5 7 6 14 13 12 11 10 8 9 g h nc i even odd v ss v dd f e d c b a 1 2 3 4 5 7 6 14 13 12 11 10 8 9 v dd f e d c b a g h nc i even odd v ss
radhard msi logic 200 ut54acs280/ut54acts280 logic diagram a b c d e g h i f (8) (9) ( (10) (11) (12) (13) (1) (2) (4) (5) (6) even odd
201 radhard msi logic ut54acs280/ut54acts280 radiation hardness specifications 1 notes: 1. logic will not latchup during radiation exposure within the limits defined in the table. 2. device storage elements are immune to seu affects. absolute maximum ratings note: 1. stresses outside the listed absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. exposure to absolute ma ximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter limit units total dose 1.0e6 rads(si) seu threshold 2 80 mev-cm 2 /mg sel threshold 120 mev-cm 2 /mg neutron fluence 1.0e14 n/cm 2 symbol parameter limit units v dd supply voltage -0.3 to 7.0 v v i/o input voltage any pin -.3 to v dd +.3 v t stg storage temperature range -65 to +150 c t j maximum junction temperature +175 c t ls lead temperature (soldering 5 seconds) +300 c jc thermal resistance junction to case 20 c/w i i dc input current 10 ma p d maximum power dissipation 1 w symbol parameter limit units v dd supply voltage 4.5 to 5.5 v v in input voltage any pin 0 to v dd v t c temperature range -55 to + 125 c
radhard msi logic 202 ut54acs280/ut54acts280 dc electrical characteristics 7 (v dd = 5.0v 10%; v ss = 0v 6 , -55 c < t c < +125 c) symbol parameter condition min max unit v il low-level input voltage 1 acts acs 0.8 .3v dd v v ih high-level input voltage 1 acts acs .5v dd .7v dd v i in input leakage current acts/acs v in = v dd or v ss -1 1 a v ol low-level output voltage 3 acts acs i ol = 8.0ma i ol = 100 a 0.40 0.25 v v oh high-level output voltage 3 acts acs i oh = -8.0ma i oh = -100 a .7v dd v dd - 0.25 v i os short-circuit output current 2 ,4 acts/acs v o = v dd and v ss -200 200 ma i ol output current 10 (sink) v in = v dd or v ss v ol = 0.4v 8 ma i oh output current 10 (source) v in = v dd or v ss v oh = v dd - 0.4v -8 ma p total power dissipation 2, 8, 9 c l = 50pf 2.2 mw/ mhz i ddq quiescent supply current v dd = 5.5v 10 a i ddq quiescent supply current delta acts for input under test v in = v dd - 2.1v for all other inputs v in = v dd or v ss v dd = 5.5v 1.6 ma c in input capacitance 5 = 1mhz @ 0v 15 pf c out output capacitance 5 = 1mhz @ 0v 15 pf
203 radhard msi logic ut54acs280/ut54acts280 notes: 1. functional tests are conducted in accordance with mil-std-883 with the following input test conditions: v ih = v ih (min) + 20%, - 0%; v il = v il (max) + 0%, - 50%, as specified herein, for ttl, cmos, or schmitt compatible inputs. devices may be tested using any input voltage within th e above specified range, but are guaranteed to v ih (min) and v il (max). 2. supplied as a design limit but not guaranteed or tested. 3. per mil-prf-38535, for current density 5.0e5 amps/cm 2 , the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pf/mhz. 4. not more than one output may be shorted at a time for maximum duration of one second. 5. capacitance measured for initial qualification and when design changes may affect the value. capacitance is measured between the designated terminal and v ss at frequency of 1mhz and a signal amplitude of 50mv rms maximum. 6. maximum allowable relative shift equals 50mv. 7. all specifications valid for radiation dose 1e6 rads(si). 8. power does not include power contribution of any ttl output sink current. 9. power dissipation specified per switching output. 10. this value is guaranteed based on characterization data, but not tested.
radhard msi logic 204 ut54acs280/ut54acts280 ac electrical characteristics 2 (v dd = 5.0v 10%; v ss = 0v 1 , -55 c < t c < +125 c) notes: 1. maximum allowable relative shift equals 50mv. 2. all specifications valid for radiation dose 1e6 rads(si). symbol parameter minimum maximum unit t plh any input to even 1 20 ns t phl any input to even 1 20 ns t phl any input to odd 1 22 ns t plh any input to odd 1 20 ns
205 radhard msi logic ut54acs283/ut54acts283 radiation-hardened 4-bit binary full adders features radiation-hardened cmos - latchup immune high speed low power consumption single 5 volt supply available qml q or v processes flexible package - 16-pin dip - 16-lead flatpack description the ut54acs283 and the ut54acts283 are 4-bit binary adders. the adders perform addition of two 4-bit binary words. the sum ( ) outputs are provided for each bit and the resultant carry (c4) is obtained as the fifth bit. the adders feature full internal look-ahead across all four bits for fast carry generation. the devices are characterized over full military temperature range of -55 c to +125 c. logic symbol pinouts 16-pin dip top view 16-lead flatpack top view 0 (1) note: 1. logic symbol in accordance with ansi/ieee std 91-1984 and iec publication 617-12. (5) a1 (3) a2 (14) a3 (12) a4 3 (6) b1 0 (2) b2 (15) b3 (11) b4 3 (7) c0 c1 (4) 1 p q 2 (10) (13) 3 4 0 3 (9) c4 c0 1 2 3 4 5 7 6 16 15 14 13 12 10 11 b2 a2 1 a1 b1 c0 v dd b3 a3 3 a4 b4 4 8 9 v ss c4 2 1 2 3 4 5 7 6 16 15 14 13 12 10 11 8 9 b2 a2 1 a1 b1 c0 v ss 2 v dd b3 a3 3 a4 b4 4 c4
radhard msi logic 206 ut54acs283/ut54acts283 function table h = high level, l = low level note: input conditions at a1, a2, b1, b2, and c0 are used to determine outputs 1 and 2 and the value of the internal carry c2. the values at c2, a3, b3, a4, and b4 are then used to determine outputs 3, 4, and c4. input output when c0 = l when c2 = l when c0 = h when c2 = h a1 a3 b1 b3 a2 a4 b2 b4 1 3 2 4 c2 c4 1 3 2 4 c2 c4 l l l l l l l h l l h l l l h l l l h l l h l l h l l l h l h h l l l h l h h l l l h l l h l h h l h l h l h h l l l h l h h l h h l l l h h h h l l l h h l h l l l h l h l h h l h l l h h h l l l h l h l h h h l l l h h h l h l l h h l h l l h h l l h h l h h l h h h l h l h h l h h h h l h l h h h h h h l h h h h h
207 radhard msi logic ut54acs283/ut54acts283 logic diagram c4 (9) (10) (13) (1) (4) (12) (11) (15) (14) (2) (3) (6) (5) (7) b4 a4 b3 a3 b2 a2 b1 a1 c0
radhard msi logic 208 ut54acs283/ut54acts283 radiation hardness specifications 1 notes: 1. logic will not latchup during radiation exposure within the limits defined in the table. 2. device storage elements are immune to seu affects. absolute maximum ratings note: 1. stresses outside the listed absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. exposure to absolute ma ximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter limit units total dose 1.0e6 rads(si) seu threshold 2 80 mev-cm 2 /mg sel threshold 120 mev-cm 2 /mg neutron fluence 1.0e14 n/cm 2 symbol parameter limit units v dd supply voltage -0.3 to 7.0 v v i/o voltage any pin -.3 to v dd +.3 v t stg storage temperature range -65 to +150 c t j maximum junction temperature +175 c t ls lead temperature (soldering 5 seconds) +300 c jc thermal resistance junction to case 20 c/w i i dc input current 10 ma p d maximum power dissipation 1 w symbol parameter limit units v dd supply voltage 4.5 to 5.5 v v in input voltage any pin 0 to v dd v t c temperature range -55 to + 125 c
209 radhard msi logic ut54acs283/ut54acts283 dc electrical characteristics 7 (v dd = 5.0v 10%; v ss = 0v 6 , -55 c < t c < +125 c) symbol parameter condition min max unit v il low-level input voltage 1 acts acs 0.8 .3v dd v v ih high-level input voltage 1 acts acs .5v dd .7v dd v i in input leakage current acts/acs v in = v dd or v ss -1 1 a v ol low-level output voltage 3 acts acs i ol = 8.0ma i ol = 100 a 0.40 0.25 v v oh high-level output voltage 3 acts acs i oh = -8.0ma i oh = -100 a .7v dd v dd - 0.25 v i os short-circuit output current 2 ,4 acts/acs v o = v dd and v ss -200 200 ma i ol output current 10 (sink) v in = v dd or v ss v ol = 0.4v 8 ma i oh output current 10 (source) v in = v dd or v ss v oh = v dd - 0.4v -8 ma p total power dissipation 2, 8, 9 c l = 50pf 1.9 mw/ mhz i ddq quiescent supply current v dd = 5.5v 10 a i ddq quiescent supply current delta acts for input under test v in = v dd - 2.1v for all other inputs v in = v dd or v ss v dd = 5.5v 1.6 ma c in input capacitance 5 = 1mhz @ 0v 15 pf c out output capacitance 5 = 1mhz @ 0v 15 pf
radhard msi logic 210 ut54acs283/ut54acts283 notes: 1. functional tests are conducted in accordance with mil-std-883 with the following input test conditions: v ih = v ih (min) + 20%, - 0%; v il = v il (max) + 0%, - 50%, as specified herein, for ttl, cmos, or schmitt compatible inputs. devices may be tested using any input voltage within th e above specified range, but are guaranteed to v ih (min) and v il (max). 2. supplied as a design limit but not guaranteed or tested. 3. per mil-prf-38535, for current density 5.0e5 amps/cm 2 , the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pf/mhz. 4. not more than one output may be shorted at a time for maximum duration of one second. 5. capacitance measured for initial qualification and when design changes may affect the value. capacitance is measured between the designated terminal and v ss at frequency of 1mhz and a signal amplitude of 50mv rms maximum. 6. maximum allowable relative shift equals 50mv. 7. all specifications valid for radiation dose 1e6 rads(si). 8. power does not include power contribution of any ttl output sink current. 9. power dissipation specified per switching output. 10. this value is guaranteed based on characterization data, but not tested. ac electrical characteristics 2 (v dd = 5.0v 10%; v ss = 0v 1 , -55 c < t c < +125 c) notes: 1. maximum allowable relative shift equals 50mv. 2. all specifications valid for radiation dose 1e6 rads(si). symbol parameter minimum maximum unit t plh propagation delay c0 to n 2 16 ns t phl propagation delay c0 to n 2 19 ns t plh propagation delay c0 to c4 2 16 ns t phl propagation delay c0 to c4 2 17 ns t plh propagation delay an, bn to c4 2 16 ns t phl propagation delay an, bn to c4 2 15 ns t plh propagation delay an, bn to n 2 14 ns t phl propagation delay an, bn to n 2 16 ns
211 radhard msi logic ut54acs365/ut54acts365 radiation-hardened hex buffers/line drivers with three-state outputs features radiation-hardened cmos - latchup immune high speed low power consumption single 5 volt supply available qml q or v processes flexible package - 16-pin dip - 16-lead flatpack description the ut54acs365 and ut54acts365 are non-inverting hex buffer and line driver with three-state outputs. the output en- ables ( oe1 and oe2 ) control the three-state outputs. if oe1 or oe2 is high, the outputs will be in a high impedance state. for data, both oe1 and oe2 must be low. the devices are characterized over full military temperature range of -55 c to +125 c. function table logic symbol pinouts 16-pin dip top view 16-lead flatpack top view inputs output oe1 oe2 a y l l l l l l h h x h x z h x x z (1) oe1 (2) a1 (4) a2 (6) (3) y1 (7) (5) y2 note: 1. logic symbol in accordance with ansi/ieee std 91-1984 and iec publication 617-12. a3 (10) a4 (12) a5 (14) y3 (13) (11) y5 (9) y4 (15) oe2 en & a6 y6 1 2 3 4 5 7 6 16 15 14 13 12 10 11 oe1 a1 y1 a2 y2 a3 y3 v dd oe2 a6 y6 a5 y5 a4 8 9 v ss y4 1 2 3 4 5 7 6 16 15 14 13 12 10 11 v dd oe1 a1 y1 a2 y2 a3 y3 oe2 a6 y6 a5 y5 a4 v ss y4 8 9
radhard msi logic 212 ut54acs365/ut54acts365 logic diagram radiation hardness specifications 1 notes: 1. logic will not latchup during radiation exposure within the limits defined in the table. 2. device storage elements are immune to seu affects. absolute maximum ratings note: 1. stresses outside the listed absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. exposure to absolute ma ximum rating conditions for extended periods may affect device reliability. parameter limit units total dose 1.0e6 rads(si) seu threshold 2 80 mev-cm 2 /mg sel threshold 120 mev-cm 2 /mg neutron fluence 1.0e14 n/cm 2 oe1 oe2 (1) (3) (5) (7) (9) (11) (13) y1 y2 y3 y4 y5 y6 (15) (2) (4) (6) (10) (12) (14) a1 a2 a3 a4 a5 a6 symbol parameter limit units v dd supply voltage -0.3 to 7.0 v v i/o voltage any pin -.3 to v dd +.3 v t stg storage temperature range -65 to +150 c t j maximum junction temperature +175 c t ls lead temperature (soldering 5 seconds) +300 c jc thermal resistance junction to case 20 c/w i i dc input current 10 ma p d maximum power dissipation 1 w
213 radhard msi logic ut54acs365/ut54acts365 recommended operating conditions symbol parameter limit units v dd supply voltage 4.5 to 5.5 v v in input voltage any pin 0 to v dd v t c temperature range -55 to + 125 c
radhard msi logic 214 ut54acs365/ut54acts365 dc electrical characteristics 7 (v dd = 5.0v 10%; v ss = 0v 6 , -55 c < t c < +125 c) symbol parameter condition min max unit v il low-level input voltage 1 acts acs 0.8 .3v dd v v ih high-level input voltage 1 acts acs .5v dd .7v dd v i in input leakage current acts/acs v in = v dd or v ss -1 1 a v ol low-level output voltage 3 acts acs i ol = 12.0ma i ol = 100 a 0.40 0.25 v v oh high-level output voltage 3 acts acs i oh = -12.0ma i oh = -100 a .7v dd v dd - 0.25 v i oz three-state output leakage current v o = v dd and v ss -30 30 a i os short-circuit output current 2 ,4 acts/acs v o = v dd and v ss -300 300 ma i ol output current 10 (sink) v in = v dd or v ss v ol = 0.4v 12 ma i oh output current 10 (source) v in = v dd or v ss v oh = v dd - 0.4v -12 ma p total power dissipation 2, 8, 9 c l = 50pf 1.8 mw/ mhz i ddq quiescent supply current v dd = 5.5v 10 a i ddq quiescent supply current delta acts for input under test v in = v dd - 2.1v for all other inputs v in = v dd or v ss v dd = 5.5v 1.6 ma c in input capacitance 5 = 1mhz @ 0v 15 pf c out output capacitance 5 = 1mhz @ 0v 15 pf
215 radhard msi logic ut54acs365/ut54acts365 notes: 1. functional tests are conducted in accordance with mil-std-883 with the following input test conditions: v ih = v ih (min) + 20%, - 0%; v il = v il (max) + 0%, - 50%, as specified herein, for ttl, cmos, or schmitt compatible inputs. devices may be tested using any input voltage within th e above specified range, but are guaranteed to v ih (min) and v il (max). 2. supplied as a design limit but not guaranteed or tested. 3. per mil-prf-38535, for current density 5.0e5 amps/cm 2 , the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pf/mhz. 4. not more than one output may be shorted at a time for maximum duration of one second. 5. capacitance measured for initial qualification and when design changes may affect the value. capacitance is measured between the designated terminal and v ss at frequency of 1mhz and a signal amplitude of 50mv rms maximum. 6. maximum allowable relative shift equals 50mv. 7. all specifications valid for radiation dose 1e6 rads(si). 8. power does not include power contribution of any ttl output sink current. 9. power dissipation specified per switching output. 10. this value is guaranteed based on characterization data, but not tested.
radhard msi logic 216 ut54acs365/ut54acts365 ac electrical characteristics 2 (v dd = 5.0v 10%; v ss = 0v 1 , -55 c < t c < +125 c) notes: 1. maximum allowable relative shift equals 50mv. 2. all specifications valid for radiation dose 1e6 rads(si). symbol parameter minimum maximum unit t plh data to output 2 11 ns t phl data to output 2 13 ns t pzl oe low to output active 2 14 ns t pzh oe low to output active 2 15 ns t plz oe high to output three-state 2 12 ns t phz oe high to output three-state 2 14 ns
211 radhard msi logic ut54acs365/ut54acts365 radiation-hardened hex buffers/line drivers with three-state outputs features radiation-hardened cmos - latchup immune high speed low power consumption single 5 volt supply available qml q or v processes flexible package - 16-pin dip - 16-lead flatpack description the ut54acs365 and ut54acts365 are non-inverting hex buffer and line driver with three-state outputs. the output en- ables ( oe1 and oe2 ) control the three-state outputs. if oe1 or oe2 is high, the outputs will be in a high impedance state. for data, both oe1 and oe2 must be low. the devices are characterized over full military temperature range of -55 c to +125 c. function table logic symbol pinouts 16-pin dip top view 16-lead flatpack top view inputs output oe1 oe2 a y l l l l l l h h x h x z h x x z (1) oe1 (2) a1 (4) a2 (6) (3) y1 (7) (5) y2 note: 1. logic symbol in accordance with ansi/ieee std 91-1984 and iec publication 617-12. a3 (10) a4 (12) a5 (14) y3 (13) (11) y5 (9) y4 (15) oe2 en & a6 y6 1 2 3 4 5 7 6 16 15 14 13 12 10 11 oe1 a1 y1 a2 y2 a3 y3 v dd oe2 a6 y6 a5 y5 a4 8 9 v ss y4 1 2 3 4 5 7 6 16 15 14 13 12 10 11 v dd oe1 a1 y1 a2 y2 a3 y3 oe2 a6 y6 a5 y5 a4 v ss y4 8 9
radhard msi logic 212 ut54acs365/ut54acts365 logic diagram radiation hardness specifications 1 notes: 1. logic will not latchup during radiation exposure within the limits defined in the table. 2. device storage elements are immune to seu affects. absolute maximum ratings note: 1. stresses outside the listed absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. exposure to absolute ma ximum rating conditions for extended periods may affect device reliability. parameter limit units total dose 1.0e6 rads(si) seu threshold 2 80 mev-cm 2 /mg sel threshold 120 mev-cm 2 /mg neutron fluence 1.0e14 n/cm 2 oe1 oe2 (1) (3) (5) (7) (9) (11) (13) y1 y2 y3 y4 y5 y6 (15) (2) (4) (6) (10) (12) (14) a1 a2 a3 a4 a5 a6 symbol parameter limit units v dd supply voltage -0.3 to 7.0 v v i/o voltage any pin -.3 to v dd +.3 v t stg storage temperature range -65 to +150 c t j maximum junction temperature +175 c t ls lead temperature (soldering 5 seconds) +300 c jc thermal resistance junction to case 20 c/w i i dc input current 10 ma p d maximum power dissipation 1 w
213 radhard msi logic ut54acs365/ut54acts365 recommended operating conditions symbol parameter limit units v dd supply voltage 4.5 to 5.5 v v in input voltage any pin 0 to v dd v t c temperature range -55 to + 125 c
radhard msi logic 214 ut54acs365/ut54acts365 dc electrical characteristics 7 (v dd = 5.0v 10%; v ss = 0v 6 , -55 c < t c < +125 c) symbol parameter condition min max unit v il low-level input voltage 1 acts acs 0.8 .3v dd v v ih high-level input voltage 1 acts acs .5v dd .7v dd v i in input leakage current acts/acs v in = v dd or v ss -1 1 a v ol low-level output voltage 3 acts acs i ol = 12.0ma i ol = 100 a 0.40 0.25 v v oh high-level output voltage 3 acts acs i oh = -12.0ma i oh = -100 a .7v dd v dd - 0.25 v i oz three-state output leakage current v o = v dd and v ss -30 30 a i os short-circuit output current 2 ,4 acts/acs v o = v dd and v ss -300 300 ma i ol output current 10 (sink) v in = v dd or v ss v ol = 0.4v 12 ma i oh output current 10 (source) v in = v dd or v ss v oh = v dd - 0.4v -12 ma p total power dissipation 2, 8, 9 c l = 50pf 1.8 mw/ mhz i ddq quiescent supply current v dd = 5.5v 10 a i ddq quiescent supply current delta acts for input under test v in = v dd - 2.1v for all other inputs v in = v dd or v ss v dd = 5.5v 1.6 ma c in input capacitance 5 = 1mhz @ 0v 15 pf c out output capacitance 5 = 1mhz @ 0v 15 pf
215 radhard msi logic ut54acs365/ut54acts365 notes: 1. functional tests are conducted in accordance with mil-std-883 with the following input test conditions: v ih = v ih (min) + 20%, - 0%; v il = v il (max) + 0%, - 50%, as specified herein, for ttl, cmos, or schmitt compatible inputs. devices may be tested using any input voltage within th e above specified range, but are guaranteed to v ih (min) and v il (max). 2. supplied as a design limit but not guaranteed or tested. 3. per mil-prf-38535, for current density 5.0e5 amps/cm 2 , the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pf/mhz. 4. not more than one output may be shorted at a time for maximum duration of one second. 5. capacitance measured for initial qualification and when design changes may affect the value. capacitance is measured between the designated terminal and v ss at frequency of 1mhz and a signal amplitude of 50mv rms maximum. 6. maximum allowable relative shift equals 50mv. 7. all specifications valid for radiation dose 1e6 rads(si). 8. power does not include power contribution of any ttl output sink current. 9. power dissipation specified per switching output. 10. this value is guaranteed based on characterization data, but not tested.
radhard msi logic 216 ut54acs365/ut54acts365 ac electrical characteristics 2 (v dd = 5.0v 10%; v ss = 0v 1 , -55 c < t c < +125 c) notes: 1. maximum allowable relative shift equals 50mv. 2. all specifications valid for radiation dose 1e6 rads(si). symbol parameter minimum maximum unit t plh data to output 2 11 ns t phl data to output 2 13 ns t pzl oe low to output active 2 14 ns t pzh oe low to output active 2 15 ns t plz oe high to output three-state 2 12 ns t phz oe high to output three-state 2 14 ns
217 radhard msi logic ut54acs373/ut54acts373 radiation-hardened octal transparent latches with three-state outputs features 8 latches in a single package three-state bus-driving true outputs full parallel access for loading radiation-hardened cmos - latchup immune high speed low power consumption single 5 volt supply available qml q or v processes flexible package - 20-pin dip - 20-lead flatpack description the ut54acs373 and the ut54acts373 are 8-bit latches with three-state outputs designed for driving highly capacitive or relatively low-impedance loads. the device is suitable for buffer registers, i/o ports, and bidirectional bus drivers. the eight latches are transparent d latches. while the enable (c) is high the q outputs will follow the data (d) inputs. when the enable is taken low, the q outputs will be latched at the levels that were set up at the d inputs. an output-control input ( oc ) places the eight outputs in either a normal logic state (high or low logic levels) or a high-imped- ance state. the high-impedance third state and increased drive provide the capability to drive the bus line in a bus-organized system without need for interface or pull-up components. the output control oc does not affect the internal operations of the latches. old data can be retained or new data can be entered while the outputs are off. the devices are characterized over full military temperature range of -55 c to +125 c. function table note: 1. data may be latched internally. pinouts 20-pin dip top view 20-lead flatpack top view logic symbol inputs output oc c nd nq l h h h l h l l l l x nq 0 h x x z 1 1 2 3 4 5 7 6 20 19 18 17 16 14 15 oc 1q 1d 2d 2q 3q 3d v dd 8q 8d 7d 7q 6d 8 13 4d 5d 6q 9 12 4q 5q 10 11 v ss c 1 2 3 4 5 7 6 20 19 18 17 16 14 15 oc 1q 1d 2d 2q 3q 3d v dd 8q 8d 7d 7q 6d 8 13 4d 5d 6q 9 12 4q 5q 10 11 v ss c (1) oc en (3) 1d (4) 2d (7) (2) 1q (6) (5) 2q note: 1. logic symbol in accordance with ansi/ieee std 91-1984 and iec publication 617-12. 3d (8) 4d (13) 5d (14) 6d 3q (15) 6q (12) 5q (9) 4q (17) 7d (18) 8d (19) 8q (16) 7q (11) c c1 1d
radhard msi logic 218 ut54acs373/ut54acts373 logic diagram radiation hardness specifications 1 notes: 1. logic will not latchup during radiation exposure within the limits defined in the table. 2. device storage elements are immune to seu affects. absolute maximum rating note: 1. stresses outside the listed absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. exposure to absolute ma ximum rating conditions for extended periods may affect device reliability. parameter limit units total dose 1.0e6 rads(si) seu threshold 2 80 mev-cm 2 /mg sel threshold 120 mev-cm 2 /mg neutron fluence 1.0e14 n/cm 2 oc c 1d 2d 3d 4d 5d 6d 7d 8d (1) (11) (4) (7) (8) (13) (14) (17) (18) (2) (5) (6) (9) (12) (15) (16) (19) 1q 2q 3q 4q 5q 6q 7q 8q c d c d c d c d c d c d (3) d c c d q q q q q q q q symbol parameter limit units v dd supply voltage -0.3 to 7.0 v v i/o voltage any pin -.3 to v dd +.3 v t stg storage temperature range -65 to +150 c t j maximum junction temperature +175 c t ls lead temperature (soldering 5 seconds) +300 c jc thermal resistance junction to case 20 c/w i i dc input current 10 ma p d maximum power dissipation 1 w
219 radhard msi logic ut54acs373/ut54acts373 recommended operating conditions symbol parameter limit units v dd supply voltage 4.5 to 5.5 v v in input voltage any pin 0 to v dd v t c temperature range -55 to + 125 c
radhard msi logic 220 ut54acs373/ut54acts373 dc electrical characteristics 7 (v dd = 5.0v 10%; v ss = 0v 6 , -55 c < t c < +125 c) symbol parameter condition min max unit v il low-level input voltage 1 acts acs 0.8 .3v dd v v ih high-level input voltage 1 acts acs .5v dd .7v dd v i in input leakage current acts/acs v in = v dd or v ss -1 1 a v ol low-level output voltage 3 acts acs i ol = 8.0ma i ol = 100 a 0.40 0.25 v v oh high-level output voltage 3 acts acs i oh = -8.0ma i oh = -100 a .7v dd v dd - 0.25 v i oz three-state output leakage current v o = v dd and v ss -20 20 a i os short-circuit output current 2 ,4 acts/acs v o = v dd and v ss -200 200 ma i ol output current 10 (sink) v in = v dd or v ss v ol = 0.4v 8 ma i oh output current 10 (source) v in = v dd or v ss v oh = v dd - 0.4v -8 ma p total power dissipation 2, 8, 9 c l = 50pf 1.9 mw/ mhz i ddq quiescent supply current v dd = 5.5v 10 a i ddq quiescent supply current delta acts for input under test v in = v dd - 2.1v for all other inputs v in = v dd or v ss v dd = 5.5v 1.6 ma c in input capacitance 5 = 1mhz @ 0v 15 pf c out output capacitance 5 = 1mhz @ 0v 15 pf
221 radhard msi logic ut54acs373/ut54acts373 notes: 1. functional tests are conducted in accordance with mil-std-883 with the following input test conditions: v ih = v ih (min) + 20%, - 0%; v il = v il (max) + 0%, - 50%, as specified herein, for ttl, cmos, or schmitt compatible inputs. devices may be tested using any input voltage within th e above specified range, but are guaranteed to v ih (min) and v il (max). 2. supplied as a design limit but not guaranteed or tested. 3. per mil-prf-38535, for current density 5.0e5 amps/cm 2 , the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pf/mhz. 4. not more than one output may be shorted at a time for maximum duration of one second. 5. capacitance measured for initial qualification and when design changes may affect the value. capacitance is measured between the designated terminal and v ss at frequency of 1mhz and a signal amplitude of 50mv rms maximum. 6. maximum allowable relative shift equals 50mv. 7. all specifications valid for radiation dose 1e6 rads(si). 8. power does not include power contribution of any ttl output sink current. 9. power dissipation specified per switching output. 10. this value is guaranteed based on characterization data, but not tested.
radhard msi logic 222 ut54acs373/ut54acts373 ac electrical characteristics 2 (v dd = 5.0v 10%; v ss = 0v 1 , -55 c < t c < +125 c) notes: 1. maximum allowable relative shift equals 50mv. 2. all specifications valid for radiation dose 1e6 rads(si). symbol parameter minimum maximum unit t plh data to qn 1 14 ns t phl data to qn 1 16 ns t plh c to qn 1 16 ns t phl c to qn 1 18 ns t pzl oc low to qn 1 14 ns t pzh oc low to qn 1 14 ns t plz oc high to qn three-state 1 14 ns t phz oc high to qn three-state 1 14 ns f max maximum clock frequency 71 mhz t su data setup time before c 5 ns t h data hold time after c 4 ns t w minimum pulse width c high 7 ns
223 radhard msi logic ut54acs374/ut54acts374 radiation-hardened octal d-type flip-flops with three-state outputs features 8 latches in a single package three-state bus-driving true outputs full parallel access for loading radiation-hardened cmos - latchup immune high speed low power consumption single 5 volt supply available qml q or v processes flexible package - 20-pin dip - 20-lead flatpack description the ut54acs374 and the ut54acts374 are non-inverting octal d type flip-flops with three-state outputs designed for driv- ing highly capacitive or relatively low-impedance loads. the device is suitable for buffer registers, i/o ports, and bidirectional bus drivers. the eight flip-flops are edge triggered d-type flip-flops. on the positive transition of the clock the q outputs will follow the data (d) inputs. an output-control input ( oc ) places the eight outputs in either a normal logic state (high or low logic level) or a high-imped- ance state. the high-impedance third state and increased drive provide the capability to drive the bus line in a bus-organized system without the need for interface or pull-up components. the output control oc does not affect the internal operations of the flip-flops. old data can be retained or new data can be entered while the outputs are off. the devices are characterized over full military temperature range of -55 c to +125 c. function table pinouts 20-pin dip top view 20-lead flatpack top view logic symbol inputs output oc clk nd nq l h h l l l l l x nq 0 h x x z 1 2 3 4 5 7 6 20 19 18 17 16 14 15 oc 1q 1d 2d 2q 3q 3d v dd 8q 8d 7d 7q 6d 8 13 4d 5d 6q 9 12 4q 5q 10 11 v ss clk 1 2 3 4 5 7 6 20 19 18 17 16 14 15 oc 1q 1d 2d 2q 3q 3d v dd 8q 8d 7d 7q 6d 8 13 4d 5d 6q 9 12 4q 5q 10 11 v ss clk (1) oc en (3) 1d (4) 2d (7) (2) 1q (6) (5) 2q note: 1. logic symbol in accordance with ansi/ieee std 91-1984 and iec publication 617-12. 3d (8) 4d (13) 5d (14) 6d 3q (15) 6q (12) 5q (9) 4q (17) 7d (18) 8d (19) 8q (16) 7q (11) clk c1 1d
radhard msi logic 224 ut54acs374/ut54acts374 logic diagram radiation hardness specifications 1 notes: 1. logic will not latchup during radiation exposure within the limits defined in the table. 2. device storage elements are immune to seu affects. absolute maximum rating note: 1. stresses outside the listed absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. exposure to absolute ma ximum rating conditions for extended periods may affect device reliability. parameter limit units total dose 1.0e6 rads(si) seu threshold 2 80 mev-cm 2 /mg sel threshold 120 mev-cm 2 /mg neutron fluence 1.0e14 n/cm 2 oc clk 1d 2d 3d 4d 5d 6d 7d 8d (1) (11) (4) (7) (8) (13) (14) (17) (18) (2) (5) (6) (9) (12) (15) (16) (19) 1q 2q 3q 4q 5q 6q 7q 8q c d c d c d c d c d c d (3) d c c d q q q q q q q q symbol parameter limit units v dd supply voltage -0.3 to 7.0 v v i/o voltage any pin -.3 to v dd +.3 v t stg storage temperature range -65 to +150 c t j maximum junction temperature +175 c t ls lead temperature (soldering 5 seconds) +300 c jc thermal resistance junction to case 20 c/w i i dc input current 10 ma p d maximum power dissipation 1 w
225 radhard msi logic ut54acs374/ut54acts374 recommended operating conditions symbol parameter limit units v dd supply voltage 4.5 to 5.5 v v in input voltage any pin 0 to v dd v t c temperature range -55 to + 125 c
radhard msi logic 226 ut54acs374/ut54acts374 dc electrical characteristics 7 (v dd = 5.0v 10%; v ss = 0v 6 , -55 c < t c < +125 c) symbol parameter condition min max unit v il low-level input voltage 1 acts acs 0.8 .3v dd v v ih high-level input voltage 1 acts acs .5v dd .7v dd v i in input leakage current acts/acs v in = v dd or v ss -1 1 a v ol low-level output voltage 3 acts acs i ol = 8.0ma i ol = 100 a 0.40 0.25 v v oh high-level output voltage 3 acts acs i oh = -8.0ma i oh = -100 a .7v dd v dd - 0.25 v i oz three-state output leakage current v o = v dd and v ss -20 20 a i os short-circuit output current 2 ,4 acts/acs v o = v dd and v ss -200 200 ma i ol output current 10 (sink) v in = v dd or v ss v ol = 0.4v 8 ma i oh output current 10 (source) v in = v dd or v ss v oh = v dd - 0.4v -8 ma p total power dissipation 2, 8, 9 c l = 50pf 1.9 mw/ mhz i ddq quiescent supply current v dd = 5.5v 10 a i ddq quiescent supply current delta acts for input under test v in = v dd - 2.1v for all other inputs v in = v dd or v ss v dd = 5.5v 1.6 ma c in input capacitance 5 = 1mhz @ 0v 15 pf c out output capacitance 5 = 1mhz @ 0v 15 pf
227 radhard msi logic ut54acs374/ut54acts374 notes: 1. functional tests are conducted in accordance with mil-std-883 with the following input test conditions: v ih = v ih (min) + 20%, - 0%; v il = v il (max) + 0%, - 50%, as specified herein, for ttl, cmos, or schmitt compatible inputs. devices may be tested using any input voltage within th e above specified range, but are guaranteed to v ih (min) and v il (max). 2. supplied as a design limit but not guaranteed or tested. 3. per mil-prf-38535, for current density 5.0e5 amps/cm 2 , the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pf/mhz. 4. not more than one output may be shorted at a time for maximum duration of one second. 5. capacitance measured for initial qualification and when design changes may affect the value. capacitance is measured between the designated terminal and v ss at frequency of 1mhz and a signal amplitude of 50mv rms maximum. 6. maximum allowable relative shift equals 50mv. 7. all specifications valid for radiation dose 1e6 rads(si). 8. power does not include power contribution of any ttl output sink current. 9. power dissipation specified per switching output. 10. this value is guaranteed based on characterization data, but not tested.
radhard msi logic 228 ut54acs374/ut54acts374 ac electrical characteristics 2 (v dd = 5.0v 10%; v ss = 0v 1 , -55 c < t c < +125 c) notes: 1. maximum allowable relative shift equals 50mv. 2. all specifications valid for radiation dose 1e6 rads(si). symbol parameter minimum maximum unit t plh clk to qn 1 15 ns t phl clk to qn 1 18 ns t pzl oc low to qn active 1 13 ns t pzh oc low to qn active 1 13 ns t plz oc high to qn three-state 1 11 ns t phz oc high to qn three-state 1 12 ns f max maximum clock frequency 71 mhz t su data setup time before clk 5 ns t h data hold time after clk 2 ns t w minimum pulse width clk high, clk low 7 ns
229 radhard msi logic ut54acs540/ut54acts540 radiation-hardened octal buffers & line drivers, inverted three-state outputs features three-state outputs drive bus lines or buffer memory address registers radiation-hardened cmos - latchup immune high speed low power consumption single 5 volt supply available qml q or v processes flexible package - 20-pin dip - 20-lead flatpack description the ut54acs540 and the ut54acts540 are inverting octal buffers and line drivers which improve the performance and density of three-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. the devices are characterized over full military temperature range of -55 c to +125 c. function table logic symbol pinouts 20-pin dip top view 20-lead flatpack top view inputs output 1g 2g an yn l l l h l l h l h x x z x h x z (1) en (2) a1 (3) a2 (4) (18) y1 (16) (17) y2 note: 1. logic symbol in accordance with ansi/ieee std 91-1984 and iec publication 617-12. a3 (5) a4 (6) a5 (7) a6 y3 (13) y6 (14) y5 (15) y4 (8) a7 (9) a8 (11) y8 (12) y7 (19) & 1 g 2 g 1g a1 a2 a3 a4 a5 a6 v dd 2g y1 y2 y3 y5 a7 y6 y4 a8 y7 v ss y8 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 1g a1 a2 a3 a4 a5 a6 v dd 2g y1 y2 y3 y5 a7 y6 y4 a8 y7 v ss y8 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11
radhard msi logic 230 ut54acs540/ut54acts540 logic diagram radiation hardness specifications 1 notes: 1. logic will not latchup during radiation exposure within the limits defined in the table .2. device storage elements are immune to seu affects. absolute maximum ratings note: 1. stresses outside the listed absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. exposure to absolute ma ximum rating conditions for extended periods may affect device reliability. parameter limit units total dose 1.0e6 rads(si) seu threshold 2 80 mev-cm 2 /mg sel threshold 120 mev-cm 2 /mg neutron fluence 1.0e14 n/cm 2 a1 a2 a3 a4 a5 a6 a8 (1) (2) (3) (4) (5) (6) (7) (9) 1 g 2 g (19) a7 (8) y1 y2 y3 y4 y5 y6 y8 y7 (18) (17) (16) (15) (14) (13) (11) (12) symbol parameter limit units v dd supply voltage -0.3 to 7.0 v v i/o voltage any pin -.3 to v dd +.3 v t stg storage temperature range -65 to +150 c t j maximum junction temperature +175 c t ls lead temperature (soldering 5 seconds) +300 c jc thermal resistance junction to case 20 c/w i i dc input current 10 ma p d maximum power dissipation 1 w
231 radhard msi logic ut54acs540/ut54acts540 recommended operating conditions symbol parameter limit units v dd supply voltage 4.5 to 5.5 v v in input voltage any pin 0 to v dd v t c temperature range -55 to + 125 c
radhard msi logic 232 ut54acs540/ut54acts540 dc electrical characteristics 7 (v dd = 5.0v 10%; v ss = 0v 6 , -55 c < t c < +125 c) symbol parameter condition min max unit v il low-level input voltage 1 acts acs 0.8 .3v dd v v ih high-level input voltage 1 acts acs .5v dd .7v dd v i in input leakage current acts/acs v in = v dd or v ss -1 1 a v ol low-level output voltage 3 acts acs i ol = 12.0ma i ol = 100 a 0.40 0.25 v v oh high-level output voltage 3 acts acs i oh = -12.0ma i oh = -100 a .7v dd v dd - 0.25 v i oz three-state output leakage current v o = v dd and v ss -30 30 a i os short-circuit output current 2 ,4 acts/acs v o = v dd and v ss -300 300 ma i ol output current 10 (sink) v in = v dd or v ss v ol = 0.4v 12 ma i oh output current 10 (source) v in = v dd or v ss v oh = v dd - 0.4v -12 ma p total power dissipation 2, 8, 9 c l = 50pf 2.1 mw/ mhz i ddq quiescent supply current v dd = 5.5v 10 a i ddq quiescent supply current delta acts for input under test v in = v dd - 2.1v for all other inputs v in = v dd or v ss v dd = 5.5v 1.6 ma c in input capacitance 5 = 1mhz @ 0v 15 pf c out output capacitance 5 = 1mhz @ 0v 15 pf
233 radhard msi logic ut54acs540/ut54acts540 notes: 1. functional tests are conducted in accordance with mil-std-883 with the following input test conditions: v ih = v ih (min) + 20%, - 0%; v il = v il (max) + 0%, - 50%, as specified herein, for ttl, cmos, or schmitt compatible inputs. devices may be tested using any input voltage within th e above specified range, but are guaranteed to v ih (min) and v il (max). 2. supplied as a design limit but not guaranteed or tested. 3. per mil-prf-38535, for current density 5.0e5 amps/cm 2 , the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pf/mhz. 4. not more than one output may be shorted at a time for maximum duration of one second. 5. capacitance measured for initial qualification and when design changes may affect the value. capacitance is measured between the designated terminal and v ss at frequency of 1mhz and a signal amplitude of 50mv rms maximum. 6. maximum allowable relative shift equals 50mv. 7. all specifications valid for radiation dose 1e6 rads(si). 8. power does not include power contribution of any ttl output sink current. 9. power dissipation specified per switching output. 10. this value is guaranteed based on characterization data, but not tested.
radhard msi logic 234 ut54acs540/ut54acts540 ac electrical characteristics 2 (v dd = 5.0v 10%; v ss = 0v 1 , -55 c < t c < +125 c) notes: 1. maximum allowable relative shift equals 50mv. 2. all specifications valid for radiation dose 1e6 rads(si). symbol parameter minimum maximum unit t plh an to yn 1 12 ns t phl an to yn 1 13 ns t pzl g low to yn active 2 14 ns t pzh g low to yn active 2 15 ns t plz g high to yn three-state 2 13 ns t phz g high to yn three-state 2 14 ns
235 radhard msi logic ut54acs541/ut54acts541 radiation-hardened octal buffers & line drivers, three-state outp uts dec. 1, 2003 features ? three-state outputs drive bu s lines or buffer memory address registers ? 1.2 radiation-hardened cmos (acs541) and 0.6 crh cmos process (acts541) - latchup immune ? high speed ? low power consumption ? single 5 volt supply ? available qml q or v processes ? flexible package - 20-pin dip (not available for the acts541) - 20-lead flatpack description the ut54acs541 and the ut54acts541 are non-inverting oc- tal buffers and line drivers whic h improve the performance and density of three-state memory addr ess drivers, clock drivers, and bus-oriented receivers and transm itters. the devices are charac- terized over full military temperature range of -55 c to +125 c. function table logic symbol pinouts 20-pin dip top view 20-lead flatpack top view inputs output 1g 2g an yn l l l l l l h h h x x z x h x z (1) en (2) a1 (3) a2 (4) (18) y1 (16) (17) y2 note: 1. logic symbol in accordance with ansi/ieee std 91-1984 and iec publication 617-12. a3 (5) a4 (6) a5 (7) a6 y3 (13) y6 (14) y5 (15) y4 (8) a7 (9) a8 (11) y8 (12) y7 (19) & 1g 2g 1g a1 a2 a3 a4 a5 a6 v dd 2g y1 y2 y3 y5 a7 y6 y4 a8 y7 v ss y8 120 219 318 417 516 615 714 813 912 10 11 1g a1 a2 a3 a4 a5 a6 v dd 2g y1 y2 y3 y5 a7 y6 y4 a8 y7 v ss y8 120 219 318 417 516 615 714 813 912 10 11
radhard msi logic 236 ut54acs541/ut54acts541 logic diagram radiation hardness specifications 1 notes: 1. logic will not latchup during radiation ex posure within the limits defined in the table 2. device storage elements are immune to seu affects. absolute maximum ratings note: 1. stresses outside the listed absolute maximum ratings may cause permanent damage to the device . this is a stress rating only, functional operation of the device at these or any other cond itions beyond limits indicated in the operational sections is not recomm ended. exposure to absolute m aximum rating conditions for extended periods may affect device reliability. parameter limit units total dose 1.0e6 (acs541) 5.0e5 (acts541) rads(si) seu threshold 2 80 mev-cm 2 /mg sel threshold 120 mev-cm 2 /mg neutron fluence 1.0e14 n/cm 2 a1 a2 a3 a4 a5 a6 a8 (1) (2) (3) (4) (5) (6) (7) (9) 1g 2g (19) a7 (8) y1 y2 y3 y4 y5 y6 y8 y7 (18) (17) (16) (15) (14) (13) (11) (12) symbol parameter limit units v dd supply voltage -0.3 to 7.0 v v i/o voltage any pin -.3 to v dd +.3 v t stg storage temperature range -65 to +150 c t j maximum junction temperature +175 c t ls lead temperature (soldering 5 seconds) +300 c jc thermal resistance junction to case 20 c/w i i dc input current 10 ma p d maximum power dissipation 1 w
237 radhard msi logic ut54acs541/ut54acts541 recommended operating conditions symbol parameter limit units v dd supply voltage 4.5 to 5.5 v v in input voltage any pin 0 to v dd v t c temperature range -55 to + 125 c
radhard msi logic 238 ut54acs541/ut54acts541 dc electrical characteristics 7 (v dd = 5.0v 10%; v ss = 0v 6 , -55 c < t c < +125 c) symbol parameter condition min max unit v il low-level input voltage 1 acts acs 0.8 .3v dd v v ih high-level input voltage 1 acts acs .5v dd .7v dd v i in input leakage current acts/acs v in = v dd or v ss -1 1 a v ol low-level output voltage 3 acts acs i ol = 12.0ma i ol = 100 a 0.40 0.25 v v oh high-level output voltage 3 acts acs i oh = -12.0ma i oh = -100 a .7v dd v dd - 0.25 v i oz three-state output leakage current v o = v dd and v ss -30 30 a i os short-circuit output current 2 ,4 acts/acs v o = v dd and v ss -300 300 ma i ol output current 10 (sink) v in = v dd or v ss v ol = 0.4v 12 ma i oh output current 10 (source) v in = v dd or v ss v oh = v dd - 0.4v -12 ma p total power dissipation 2, 8, 9 c l = 50pf 2.1 mw/ mhz i ddq quiescent supply current v dd = 5.5v 10 a ? i ddq quiescent supply current delta acts for input under test v in = v dd - 2.1v for all other inputs v in = v dd or v ss v dd = 5.5v 1.6 ma c in input capacitance 5 ? = 1mhz @ 0v 15 pf c out output capacitance 5 ? = 1mhz @ 0v 15 pf
239 radhard msi logic ut54acs541/ut54acts541 notes: 1. functional tests are conducted in accordance with mi l-std-883 with the following input test conditions: v ih = v ih (min) + 20%, - 0%; v il = v il (max) + 0%, - 50%, as specified herein, for ttl, cmos, or schmitt compatible inputs. devices may be tested using any input voltage within t he above specified range, but are guaranteed to v ih (min) and v il (max). 2. supplied as a design limit bu t not guaranteed or tested. 3. per mil-prf-38535, for current density 5.0e5 amps/cm 2 , the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pf/mhz. 4. not more than one output may be shorted at a time for maximum duration of one second. 5. capacitance measured for initial qualifi cation and when design changes may affect the value. capacitance is measured between the designated terminal and v ss at frequency of 1mhz and a signal amplitude of 50mv rms maximum. 6. maximum allowable relative shift equals 50mv. 7. all acs specifications are valid for radiation dose < 1e6 rads(si), and all acts specifications are valid for radiation dose < 5e5 rads(si). 8. power does not include power contribution of any ttl output sink current. 9. power dissipation specified per switching output. 10. this value is guaranteed based on characterization data, but not tested.
radhard msi logic 240 ut54acs541/ut54acts541 ac electrical characteristics 2 (v dd = 5.0v 10%; v ss = 0v 1 , -55 c < t c < +125 c) notes: 1. maximum allowable relative shift equals 50mv. 2. for the acts version, all specifica tions are valid for radiation dose < 1e6 rads(si). for the acts version, all sp ecifications are valid for radiation dose < 5e5 rads(si). symbol parameter minimum maximum unit t plh an to yn 1 11 ns t phl an to yn 1 14 ns t pzl g low to yn active 2 14 ns t pzh g low to yn active 2 15 ns t plz g high to yn three-state 2 12 ns t phz g high to yn three-state 2 13 ns
241 radhard msi logic ut54acs4002/ut54acts4002 radiation-hardened dual 4-input nor gates features radiation-hardened cmos - latchup immune high speed low power consumption single 5 volt supply available qml q or v processes flexible package - 14-pin dip - 14-lead flatpack description the ut54acs4002 and the ut54acts4002 are dual 4-input nor gates. a high on any input forces the output to a low state. the circuits perform the boolean functions: y = a + b + c + d = a b c d . the devices are characterized over full military temperature range of -55 c to +125 c. function table logic symbol pinouts 14-pin dip top view 14-lead flatpack top view logic diagram inputs output an bn cn dn yn l l l l h h x x x l x h x x l x x h x l x x x h l y1 (1) (13) y2 (2) a1 (3) b1 (4) c1 (5) d1 (9) a2 (10) b2 (11) c2 (12) d2 note: 1. logic symbol in accordance with ansi/ieee standard 91-1984 and iec publication 617-12. 1 1 2 3 4 5 7 6 14 13 12 11 10 8 9 y1 a1 b1 c1 d1 nc v ss v dd y2 d2 c2 b2 a2 nc 1 2 3 4 5 7 6 14 13 12 11 10 8 9 v dd y2 d2 c2 b2 a2 nc y1 a1 b1 c1 d1 nc v ss a1 b1 y1 y2 c1 d1 a2 b2 c2 d2
radhard msi logic 242 ut54acs4002/ut54acts4002 radiation hardness specifications 1 notes: 1. logic will not latchup during radiation exposure within the limits defined in the table. 2. device storage elements are immune to seu affects. absolute maximum ratings note: 1. stresses outside the listed absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. exposure to absolute ma ximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter limit units total dose 1.0e6 rads(si) seu threshold 2 80 mev-cm 2 /mg sel threshold 120 mev-cm 2 /mg neutron fluence 1.0e14 n/cm 2 symbol parameter limit units v dd supply voltage -0.3 to 7.0 v v i/o voltage any pin -.3 to v dd +.3 v t stg storage temperature range -65 to +150 c t j maximum junction temperature +175 c t ls lead temperature (soldering 5 seconds) +300 c jc thermal resistance junction to case 20 c/w i i dc input current 10 ma p d maximum power dissipation 1 w symbol parameter limit units v dd supply voltage 4.5 to 5.5 v v in input voltage any pin 0 to v dd v t c temperature range -55 to + 125 c
243 radhard msi logic ut54acs4002/ut54acts4002 dc electrical characteristics 7 (v dd = 5.0v 10%; v ss = 0v 6 , -55 c < t c < +125 c) symbol parameter condition min max unit v il low-level input voltage 1 acts acs 0.8 .3v dd v v ih high-level input voltage 1 acts acs .5v dd .7v dd v i in input leakage current acts/acs v in = v dd or v ss -1 1 a v ol low-level output voltage 3 acts acs i ol = 8.0ma i ol = 100 a 0.40 0.25 v v oh high-level output voltage 3 acts acs i oh = -8.0ma i oh = -100 a .7v dd v dd - 0.25 v i os short-circuit output current 2 ,4 acts/acs v o = v dd and v ss -200 200 ma i ol output current 10 (sink) v in = v dd or v ss v ol = 0.4v 8 ma i oh output current 10 (source) v in = v dd or v ss v oh = v dd - 0.4v -8 ma p total power dissipation 2, 8, 9 c l = 50pf 1.9 mw/ mhz i ddq quiescent supply current v dd = 5.5v 10 a i ddq quiescent supply current delta acts for input under test v in = v dd - 2.1v for all other inputs v in = v dd or v ss v dd = 5.5v 1.6 ma c in input capacitance 5 = 1mhz @ 0v 15 pf c out output capacitance 5 = 1mhz @ 0v 15 pf
radhard msi logic 244 ut54acs4002/ut54acts4002 notes: 1. functional tests are conducted in accordance with mil-std-883 with the following input test conditions: v ih = v ih (min) + 20%, - 0%; v il = v il (max) + 0%, - 50%, as specified herein, for ttl, cmos, or schmitt compatible inputs. devices may be tested using any input voltage within th e above specified range, but are guaranteed to v ih (min) and v il (max). 2. supplied as a design limit but not guaranteed or tested. 3. per mil-prf-38535, for current density 5.0e5 amps/cm 2 , the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pf/mhz. 4. not more than one output may be shorted at a time for maximum duration of one second. 5. capacitance measured for initial qualification and when design changes may affect the value. capacitance is measured between the designated terminal and v ss at frequency of 1mhz and a signal amplitude of 50mv rms maximum. 6. maximum allowable relative shift equals 50mv. 7. all specifications valid for radiation dose 1e6 rads(si). 8. power does not include power contribution of any ttl output sink current. 9. power dissipation specified per switching output. 10. this value is guaranteed based on characterization data, but not tested. ac electrical characteristics 2 (v dd = 5.0v 10%; v ss = 0v 1 , -55 c < t c < +125 c) notes: 1. maximum allowable relative shift equals 50mv. 2. all specifications valid for radiation dose 1e6 rads(si). symbol parameter minimum maximum unit t phl input to output 1 12 ns t plh input to output 2 14 ns
245 radhard msi logic 2.0 radhard msi packages side-brazed packages
246 radhard msi logic flatpack packages
247 radhard msi logic 3.0 ordering information radhard msi - 14-lead packages: military temp erature range ut54 *** *** - * * * * lead finish: (see notes 1 and 2) (a) = solder (c) = gold (x) = optional screening: (see note 3) (c) = mil temp package type: (p) = 14-lead ceramic side-brazed dip (u) = 14-lead ceramic bottom- brazed dual-in-line flatpack part number: (see note 4) (00) = quadruple 2-input nand (02) = quadruple 2-input nor (04) = hex inverter (08) = quadruple 2-input and (10) = triple 3-input nand (11) = triple 3-input and (14) = hex inverter with schmitt trigger (20) = dual 4-input nand (27) = triple 3-input nor (34) = hex noninverting buffer (54) = 4-wide and-or invert (74) = dual d flip-flo p with clear and preset (86) = quadruple 2-input exclusive or (132) = quadruple 2-input nand schmitt trigger (164) = 8-bit shift register (220) = clock and wait-state (280) = 9-bit parity generator/checker (4002) = dual 4-input nor counter i/o type: (acs) = cmos compatible i/o level (acts) = ttl compatible i/o level notes: 1. lead finish (a,c, or x) must be specified. 2. if an ?x? is specified when ordering, then the part marking will match the lead finish and w ill be either ?a? (solder) or ?c? (gold). 3. military temperature range flow per utmc manufacturing flows do cument. devices have 48 hours of burn-in and are tested at -55 c, room temperature, and 125c. radiation characteristics are neith er tested nor guaranteed and may not be specified. 4. the following devices are not available in a dip package: ut54acs14 and ut54acs132.
radhard msi logic 248 ordering information radhard msi - 16-lead packages: military temp erature range ut54 *** *** - * * * * lead finish: (see notes 1 and 2) (a) = solder (c) = gold (x) = optional screening: (see note 3) (c) = mil temp package type: (p) = 16-lead ceramic side-brazed dip (u) = 16-lead ceramic bottom- brazed dual-in-line flatpack part number: (see note 4) (85) = 4-bit comparator (109) = dual j-k flip-flop (138) = 3-line to 8-line decoder/demultiplexer (139) = dual 2-line to 4-line decoder/demultiplexer (151) = 1 of 8 data selector/multiplexer (153) = dual 4 to 1 multiplexer (157) = quadruple 2 to 1 multiplexer (163) = 4-bit synchronous counter (165) = 8-bit parallel shift register (169) = 4-bit up/down binary counter (190) = synchronous 4-bit up/down bcd counter (191) = synchronous 4-bit up/down binary counter (193) = synchronous 4-bit up/down dual clock counter (253) = dual 4-input multiplexer (264) = look-ahead carry genrator for counter (279) = quadruple s-r latch (283) = 4-bit binary full adder (365) = hex buffer/line driv er with 3-sate outputs i/o type: (acs) = cmos compatible i/o level (acts) = ttl compatible i/o level notes: 1. lead finish (a,c, or x) must be specified. 2. if an ?x? is specified when ordering, then the part marking will match the lead fini sh and will be either ?a? (solder) or ?c? (gold). 3. military temperature range flow per utmc manufacturing flows document. devices have 48 hours of burn-in and are tested at -55 c, room temperature, and 125c. radiation characteristics are ne ither tested nor guaranteed and may not be specified. 4. the following devices are not availa ble in a dip pack age: ut54acs109.
249 radhard msi logic ordering information radhard msi - 20-lead packages: military temp erature range ut54 *** *** - * * * * lead finish: (see notes 1 and 2) (a) = solder (c) = gold (x) = optional screening: (see note 3) (c) = mil temp package type: (p) = 20-lead ceramic side-brazed dip (u) = 20-lead ceramic bottom- brazed dual-in-line flatpack part number: (see note 4) (240) = octal buffer & line driver with inverted 3-state outputs (244) = octal buffer & line driver with 3-state outputs (245) = octal bus transceiver with 3-state outputs (245s) = schmitt octal bus transceiver with 3-state outputs (273) = octal d flip-flop with clear (373) = octal transparent latch with 3-state outputs (374) = octal dff with 3-state outputs (540) = octal buffer & line driver with inverted 3-state outputs (541) = octal buffer & line driver with 3-state outputs i/o type: (acs) = cmos compatible i/o level (acts) = ttl compatible i/o level notes: 1. lead finish (a,c, or x) must be specified. 2. if an ?x? is specified when ordering, then the part marking will match the lead finish and w ill be either ?a? (solder) or ?c? (gold). 3. military temperature range flow per utmc manufacturing flows do cument. devices have 48 hours of burn-in and are tested at -55 c, room temperature, and 125c. radiation characteristics are neither tested nor guaranteed and may not be specified. 4. the following devices are not availa ble in a dip package: ut54acts541.
radhard msi logic 249a radhard msi: smd, class q & class v lead finish: (notes 1 & 2) (a) = solder (c) = gold (x) = optional case outline: (note 3) (c) = 14-lead ceramic side-brazed dip (x) = 14-lead ceramic bottom- brazed dual-in-line flatpack (e) = 16-lead ceramic side-brazed dip (x) = 16-lead ceramic bottom- brazed dual-in-line flatpack (r) = 20-lead ceramic side-brazed dip (x) = 20-lead ceramic bottom- brazed dual-in-line flatpack class designator: (v) = class v, qml qua lified to mil-prf-38535 (q) = class q, qml qualified to mil-prf-38535 device type: no options part number: please see smd cross reference total dose: (note 4) (h) = 1e6 rads(si) (g) = 5e5 rads(si) (f) = 3e5 rads(si) (r) = 1e5 rads(si) (-) = total dose characteristics neither tested nor guaranteed federal stock class designator 5962 * ***** 01 * * * notes: 1. lead finish (a, c, or x) must be specified. 2. if an ?x? is specified when ordering, part marking will match the lead finish and will be either ?a? (solder) or ?c? (gold). 3. products listed in the smd cross reference with a ? mark can only be procurred in a bo ttom-brazed dual-in-line flatpack. 4. products listed in the smd cross reference with a ? mark can only be procurred with a total dose guarantee of -, r, f, and g.

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