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| 8 bit microcontroller tlcs-870/x series tmp88ph41ug
the information contained herein is subject to change without notice. 021023_d toshiba is continually working to improve the qua lity and reliability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. it is the responsibility of the buyer, when utiliz ing toshiba products, to comply with the standards of safety in making a safe design for the entire sy stem, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that toshiba products are used within specified operating ranges as set forth in the most r ecent toshiba products specifications. also, please keep in mind the precauti ons and conditions set forth in the ? handling guide for semiconductor devices, ? or ? toshiba semiconductor reliability handbook ? etc. 021023_a the toshiba products listed in this document are intended for usage in general electronics applications (computer, personal equipment, of fice equipment, measuring equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ( ? unintended usage ? ). unintended usage include atomic energy control instruments, airplane or spaceship instruments, transportation in struments, traffic signal instruments, combustion control instruments, medical instrument s, all types of safety devices, etc. unintended usage of toshiba products listed in this document shall be made at the customer's own risk. 021023_b the products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohib ited under any applicable laws and regulations. 060106_q the information contained herein is presented only as a guide for the applications of our products. no responsibility is assumed by toshiba for any infring ements of patents or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any patents or other rights of toshiba or the third parties. 070122_c the products described in this document are subject to foreign exchange and foreign trade control laws. 060925_e for a discussion of how the reliability of microcontro llers can be predicted, please refer to section 1.3 of the chapter entitled quality and reliabil ity assurance/handling precautions. 030619_s ? 2008 toshiba corporation all rights reserved revision history date revision 2007/7/20 1 first release 2008/3/3 2 contents revised i table of contents tmp88ph41ug 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.4 pin names and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2. functional description 2.1 functions of the cpu core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.1 memory address map ............................................................................................................................... 7 2.1.2 program memory (rom) .......................................................................................................................... 8 2.1.3 data memory (ram) ............................................................................................................................... .. 8 2.1.4 system clock control circuit .................................................................................................................... 9 2.1.4.1 clock generator 2.1.4.2 timing generator 2.1.4.3 standby control circuit 2.1.4.4 controlling operation modes 2.1.5 reset circuit ............................................................................................................................... ............ 21 2.1.5.1 external reset input 2.1.5.2 adress trap reset 2.1.5.3 watchdog timer reset 2.1.5.4 system clock reset 3. interrupt control circuit 3.1 interrupt latches (il38 to il2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.2 interrupt enable register (eir) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.2.1 interrupt master enable flag (imf) .......................................................................................................... 25 3.2.2 individual interrupt enable flags (ef38 to ef3) ...................................................................................... 25 3.3 interrupt sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.3.1 interrupt acceptance processing is packaged as follows. ....................................................................... 28 3.3.2 saving/restoring general-purpose registers ............................................................................................ 29 3.3.2.1 using automatic register bank switcing 3.3.2.2 using register bank switching 3.3.2.3 using push and pop instructions 3.3.2.4 using data transfer instructions 3.3.3 interrupt return ............................................................................................................................... ......... 31 3.4 software interrupt (intsw) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.4.1 address error detection .......................................................................................................................... 32 3.4.2 debugging ............................................................................................................................... ............... 32 3.5 external interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4. special function register 4.1 sfr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.2 dbr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 ii 5. input/output ports 5.1 port p1 (p15 to p10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.2 port p2 (p22 to p20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.3 port p3 (p37 to p30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.4 port p4 (p47 to p40) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.5 port p6 (p67 to p60) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6. time base timer (tbt) and divider output (dvo) 6.1 time base timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.2 divider output (dvo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7. watchdog timer (wdt) 7.1 watchdog timer configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.2 watchdog timer control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 7.2.1 malfunction detection methods using the watchdog timer ................................................................... 52 7.2.2 watchdog timer enable ......................................................................................................................... 53 7.2.3 watchdog timer disable ........................................................................................................................ 54 7.2.4 watchdog timer interrupt (intwdt) ...................................................................................................... 54 7.2.5 watchdog timer reset ........................................................................................................................... 55 8. 16-bit timercounter 1 (tc1) 8.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 8.2 timercounter control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 8.3 function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 8.3.1 timer mode ............................................................................................................................... .............. 60 8.3.2 external trigger timer mode .................................................................................................................. 62 8.3.3 event counter mode ............................................................................................................................... 64 8.3.4 window mode ............................................................................................................................... .......... 65 8.3.5 pulse width measurement mode ............................................................................................................ 66 8.3.6 programmable pulse generate (ppg) output mode ............................................................................. 69 9. 16-bit timer (ctc) 9.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 9.2 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 9.3 function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 9.3.1 timer mode with software start ............................................................................................................... 77 9.3.2 timer mode with external trigger start .................................................................................................... 78 9.3.3 event counter mode ............................................................................................................................... . 79 9.3.4 programmable pulse generate (ppg) output mode .............................................................................. 80 10. 8-bit timercounter 3 (tc3) 10.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 iii 10.2 timercounter control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 10.3 function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 10.3.1 timer mode ............................................................................................................................... ............ 89 figure 10-3 ................................................................................................................ ...................................... 91 10.3.3 capture mode ............................................................................................................................... ........ 92 11. 8-bit timercounter 4 (tc4) 11.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 11.2 timercounter control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 11.3 function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 11.3.1 timer mode ............................................................................................................................... ............ 95 11.3.2 event counter mode ............................................................................................................................. 9 5 11.3.3 programmable divider output (pdo) mode ......................................................................................... 95 11.3.4 pulse width modulation (pwm) output mode ...................................................................................... 96 12. motor control circuit (pmd: programmable motor driver) 12.1 outline of motor control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 12.2 configuration of the motor control circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 12.3 position detection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 12.3.1 configuration of the position detection unit ......................................................................................... 104 12.3.2 position detection circ uit register functions ..................................................................................... 105 12.3.3 outline processing in the position detection unit .............................................................................. 108 12.4 timer unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 12.4.1 configuration of the timer unit ........................................................................................................... 110 12.4.1.1 timer circuit register functions 12.4.1.2 outline processing in the timer unit 12.5 three-phase pwm output unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 12.5.1 configuration of the three-phase pwm output unit ............................................................................. 114 12.5.1.1 pulse width modulation circuit (pwm waveform generating unit) 12.5.1.2 commutation control circuit 12.5.2 register functions of the waveform synthesis circuit ....................................................................... 118 12.5.3 port output as set with uoc/voc/ woc bits and upwm/vpwm/wpwm bits ................................... 120 12.5.4 protective circuit ............................................................................................................................... .. 122 12.5.5 functions of protective circuit registers ............................................................................................ 124 12.6 electrical angle timer and waveform arithmetic circuit . . . . . . . . . . . . . . . . . . 126 12.6.1 electrical angle timer and wa veform arithmetic circuit .................................................................... 127 12.6.1.1 functions of the electrical angle timer and waveform arithmetic circuit registers 12.6.1.2 list of pmd related control registers 13. asynchronous serial interface (uart) 13.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 13.2 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 13.3 transfer data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 13.4 transfer rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 13.5 data sampling method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 13.6 stop bit length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 13.7 parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 13.8 transmit/receive operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 13.8.1 data transmit operation .................................................................................................................... 144 13.8.2 data receive operation ..................................................................................................................... 144 13.9 status flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 iv 13.9.1 parity error ............................................................................................................................... ........... 145 13.9.2 framing error ............................................................................................................................... ....... 145 13.9.3 overrun error ............................................................................................................................... ....... 145 13.9.4 receive data buffer full ..................................................................................................................... 146 13.9.5 transmit data buffer empty ............................................................................................................... 146 13.9.6 transmit end flag .............................................................................................................................. 147 14. synchronous serial interface (sio) 14.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 14.2 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 14.3 serial clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 14.3.1 clock source ............................................................................................................................... ........ 151 14.3.1.1 internal clock 14.3.1.2 external clock 14.3.2 shift edge ............................................................................................................................... ............. 153 14.3.2.1 leading edge 14.3.2.2 trailing edge 14.4 number of bits to transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 14.5 number of words to transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 14.6 transfer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 14.6.1 4-bit and 8-bit transfer modes ............................................................................................................. 154 14.6.2 4-bit and 8-bit receive modes ............................................................................................................. 156 14.6.3 8-bit transfer / receive mode ............................................................................................................... 157 15. 10-bit ad converter (adc) 15.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 15.2 register configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 15.3 function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 15.3.1 software start mode ........................................................................................................................... 163 15.3.2 repeat mode ............................................................................................................................... ....... 163 15.3.3 register setting ............................................................................................................................... . 164 example : .................................................................................................................. .................................... 165 15.4 stop mode during ad conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 15.5 analog input voltage and ad conversion result . . . . . . . . . . . . . . . . . . . . . . . 166 15.6 precautions about ad converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 15.6.1 analog input pin voltage range ........................................................................................................... 167 15.6.2 analog input shared pins .................................................................................................................... 167 15.6.3 noise countermeasure ....................................................................................................................... 167 16. otp operation 16.1 operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 16.1.1 mcu mode ............................................................................................................................... ........... 169 16.1.1.1 program memory 16.1.1.2 data memory 16.1.1.3 input/output circuiry 16.1.2 prom mode ............................................................................................................................... ........ 170 16.1.2.1 programming flowchart (high-speed program writing) 16.1.2.2 program writing using a general-purpose prom programmer 17. input/output circuitry 17.1 control pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 v 17.2 input/output ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 17.3 nc pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 18. electrical characteristics 18.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 18.2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 18.3 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 18.4 ad conversion characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 18.5 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 18.6 dc characteristics, ac characteristics (prom mode) . . . . . . . . . . . . . . . . . . . 180 18.6.1 read operation in prom mode .......................................................................................................... 180 18.6.2 program operation (high-speed) ........................................................................................................ 181 18.7 recommended oscillation conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 18.8 handling precaution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 19. package dimensions this is a technical docu ment that describes the operat ing functions and electrical specifications of the 8-bit microc ontroller series tlcs-870/x (lsi). vi page 1 tmp88ph41ug cmos 8-bit microcontroller ? the information contained herein is subject to change without notice. 021023_d ? toshiba is continually working to improve the quality and reli ability of its products. neverthel ess, semiconductor devices in general can malfunction or fail due to their inherent el ectrical sensitivity and vul nerability to physical stre ss. it is the responsibility of the buyer, when utilizing toshiba products, to comply with the standards of sa fety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, pleas e ensure that toshiba products are used within specified operating ranges as set forth in the most recent toshiba products specifications. also, please keep in mind the precautions and conditions set forth in the ?handling gui de for semiconductor devices,? or ?toshiba se miconductor reliability handbook? etc. 021023_a ? the toshiba products listed in this document are intended for usage in general electronics applic ations (computer, personal eq uip- ment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neithe r intended nor warranted for usage in equipment that requires extr aordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bod ily injury (?unintended usage?). unintended us age include atomic energy control instru ments, airplane or spaceship instruments, transporta tion instruments, traffic signal instrume nts, combustion control instruments, medi cal instru- ments, all types of safety dev ices, etc. unintended usage of toshiba products li sted in this document shall be made at the cust omer's own risk. 021023_b ? the products described in this document shall not be used or embedded to any downstream products of which manufacture, use and /or sale are prohibited under any appl icable laws and regulations. 060106_q ? the information contained herein is present ed only as a guide for the applications of our products. no responsibility is assum ed by toshiba for any infringements of patents or other rights of the th ird parties which may result from its use. no license is gran ted by impli- cation or otherwise under any patents or other rights of toshiba or the third parties. 070122_c ? the products described in this document are subject to foreign exchange and foreign trade control laws. 060925_e ? for a discussion of how the reliability of microcontrollers c an be predicted, please refer to section 1.3 of the chapter entit led quality and reliability assurance/h andling precautions. 030619_s tmp88ph41ug 1.1 features 1. 8-bit single chip microcomputer tlcs-870/x series - instruction execution time : 0.20 s (at 20 mhz) - 181 types & 842 basic instructions 2. 25 interrupt sources (external : 6 internal : 19) 3. input / output ports (33 pins) large current output: 16pins (typ. 20ma), led direct drive 4. prescaler - time base timer divider output function (dvo) 5. watchdog timer select of "internal reset request" or "interrupt request". 6. 16-bit timer counter: 1 ch - timer, external trigger, wi ndow, pulse width measurement, event counter, programmable pulse generate (ppg) modes 7. 16-bit timer/counter(ctc): 1ch - ctc:timer,event counter or ppg (programmable pulse) output 8. 8-bit timer counter : 1 ch - timer, event counter, capture modes 9. 8-bit timer counter : 1 ch product no. rom (eprom) ram package mask rom mcu tmp88ph41ug 16384 bytes 512+128 bytes lqfp44-p-1010-0.80b TMP88CH41 page 2 1.1 features tmp88ph41ug - timer, event counter, pulse width modulation (pwm) output, programmable divider output (pdo) modes 10. programmable motor driver (pmd) : 1 ch - sine wave drive circuit (built-in sine wave data-table ram) rotor position detect function motor contro timer and capture function overload protective function auto commutation and auto position detection start function 11. 8-bit uart/sio : 1 ch 12. 10-bit successive approximation type ad converter - analog input: 8 ch 13. clock oscillation circuit : 1 set 14. low power consumption operation (2 modes) - stop mode: oscillation stops. (battery/capacitor back-up.) - idle mode: cpu stops. only peripherals operate using high frequency clock. release by interruputs (cpu restarts). 15. operation voltage: 4.5 v to 5.5 v at 20 mhz page 3 tmp88ph41ug 1.2 pin assignment figure 1-1 pin assignment 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 34 35 36 37 38 39 40 41 42 43 44 p47 (ctc) p61 (ain1) p62 (ain2) p64 (ain4) p63 (ain3) p67 (ain7/dbout1) p66 (ain6) p65 (ain5) p60 (ain0) p46 ( ppg2 ) p45 (so/txd) varef avdd avss ( int0 ) p10 (tc1/int2) p12 ( dvo ) p13 ( ppg1 ) p14 p15 nc nc (int1) p11 vss xout test vdd (int3/tc3) p21 ( pwm4/pdo4 /int4/tc4) p22 reset ( stop / int5 ) p20 (z1) p30 (y1) p31 xin p32(x1) p34(v1) p35(u1) p36( emg1 ) p40(pdw1) p41(pdv1) p42(pdu1) p43( sck ) p44(si/rxd) p33(w1) p37( cl1 ) page 4 1.3 block diagram tmp88ph41ug 1.3 block diagram figure 1-2 block diagram page 5 tmp88ph41ug 1.4 pin names and functions table 1-1 pin names and functions(1/2) pin name pin number input/output functions p15 42 io port15 p14 ppg1 41 io o port14 ppg1 output p13 dvo 40 io o port13 divider output p12 int2 tc1 39 io i i port12 external interrupt 2 input tc1 input p11 int1 38 io i port11 external interrupt 1 input p10 int0 37 io i port10 external interrupt 0 input p22 tc4 int4 pwm4/pdo4 7 io i i o port22 tc4 input external interrupt 4 input pwm4/pdo4 output p21 tc3 int3 6 io i i port21 tc3 pin input external interrupt 3 input p20 int5 stop 9 io i i port20 external interrupt 5 input stop mode release signal input p37 cl1 17 io i port37 pmd over load protection input1 p36 emg1 16 io i port36 pmd emergency stop input1 p35 u1 15 io o port35 pmd control output u1 p34 v1 14 io o port34 pmd control output v1 p33 w1 13 io o port33 pmd control output w1 p32 x1 12 io o port32 pmd control output x1 p31 y1 11 io o port31 pmd control output y1 p30 z1 10 io o port30 pmd control output z1 p47 ctc 25 io i port47 ctc input p46 ppg2 24 io i port46 ppg2 output p45 so txd 23 io o o port45 serial data output uart data output page 6 1.4 pin names and functions tmp88ph41ug p44 si rxd 22 io i i port44 serial data input uart data input p43 sck 21 io io port43 serial clock i/o p42 pdu1 20 io i port42 pmd control input u1 p41 pdv1 19 io i port41 pmd control input v1 p40 pdw1 18 io i port40 pmd control input w1 p67 ain7 dbout1 33 io i o port67 analog input7 pmd debug output1 p66 ain6 32 io i port66 analog input6 p65 ain5 31 io i port65 analog input5 p64 ain4 30 io i port64 analog input4 p63 ain3 29 io i port63 analog input3 p62 ain2 28 io o port62 analog input2 p61 ain1 27 io i port61 analog input1 p60 ain0 26 io i port60 analog input0 xin 2 i resonator connecting pins for high-frequency clock xout 3 o resonator connecting pins for high-frequency clock reset 8 i reset signal test 4 i test pin for out-going test and the serial prom mode control pin. usually fix to low level. fix to high level when the serial prom mode starts. varef 34 i analog base voltage input pin for a/d conversion avdd 35 i analog power supply avss 36 i analog power supply vdd 5 i +5v vss 25 io 0(gnd) nc 43 i non connection nc 44 i non connection table 1-1 pin names and functions(2/2) pin name pin number input/output functions page 7 tmp88ph41ug 2. functional description 2.1 functions of the cpu core the cpu core consists mainly of the cpu, system clock control circuit, and interrupt control circuit. this chapter describes the cpu core, program memory, data memory, and reset circuit of the tmp88ph41ug. 2.1.1 memory address map the memory of the tmp88ph41ug consists of four blocks: rom, ram, sfr (special function regis- ters), and dbr (data buffer registers), which are ma pped into one 1-mbyte addr ess space. the general-pur- pose registers consist of 16 banks, which are mapped into the ram addr ess space. figure 2-1 shows a memory address map of the tmp88ph41ug . figure 2-1 memory address map vector table for vector call instructions interrupt vector table interrupt vector table program memory rom ( bytes) ram ( bytes) ram (128 bytes) sfr rom: read-only memory program memory vector table sfr: special function registers input/output port peripheral hardware control register peripheral hardware status register system control register interrupt control register program status word dbr: data buffer registers input/output port peripheral hardware control registe r peripheral hardware status register ram: random access memory data memory stack general-purpose register bank random-access memory special function register general-purpose register bank (8 registers 16 banks) data buffer register (peripheral hardware control register / status register) 64 bytes 64 bytes 64 bytes 128 bytes bytes bytes 128 bytes 00000h 000c0h 000bfh 04000h 0003fh 00040h 01fffh fffffh fff7fh fff80h fff40h fff00h fff3fh bytes 512 512 16k 16128 dbr 01f80h 07effh 002bfh 128 page 8 2. functional description 2.1 functions of the cpu core tmp88ph41ug 2.1.2 program memory (rom) the tmp88ph41ug contains 16kbytes program memo ry (otp) located at ad dresses 04000h to 07effh and addresses fff00h to fffffh. 2.1.3 data memory (ram) the tmp88ph41ug contains 512bytes +128bytes ram. the first 128bytes location (00040h to 000bfh) of the internal ram is shared wi th a general-purpose register bank. the content of the data memory is indeterminate at power-on, so be sure to initialize it in the initialize rou- tine . note:because general-purpose registers exist in the ra m, never clear the current bank address of ram. in the above example, the ram is cleared except bank 0. example :clearing the inte rnal ram of the tmp88ph41ug (clear a ll ram addresses to 0, except bank 0) ld hl, 0048h ; set the start address ld a, 00h ; set the initialization data (00h) ld bc, 277h ; set byte counts (-1) sramclr: ld (hl+), a dec bc jrs f, sramclr page 9 tmp88ph41ug 2.1.4 system clock control circuit the system clock control circuit consists of a clock generator, timing generator, and standby control cir- cuit. figure 2-2 system clock control circuit 2.1.4.1 clock generator the clock generator generates the fundamental clock which serves as the reference for the system clocks supplied to the cpu core and peripheral hardware units. the high-frequency clock (frequency fc) can be obtai ned easily by connecting a resonator to the xin and xout pins. or a clock generated by an external os cillator can also be used. in this case, enter the external clock from the xin pin and leave the xout pin open. the tmp88ph41ug does not support the cr network that produces a time constant. figure 2-3 example fo r connecting a resonator adjusting the oscillation frequency note: although no hardware functions are provided that a llow the fundamental clock to be monitored directly from the outside, the oscillation frequency can be adjus ted by forwarding the pulse of a fixed frequency (e.g., clock output) to a port and monitoring it in a program while interrupts and the watchdog timer are disabled. for systems that require adjusting the os cillation frequency, an adjustment program must be created beforehand. 2.1.4.2 timing generator the timing generator generates various system cloc ks from the fundamental clock that are supplied to the cpu core and peripheral hardware units. the timing generator has the following functions: timing generator standby control circuit high-frequency clock oscillator circuit tbtcr syscr2 syscr1 xin xout clock generator fc 00036h 00038h 00039h system clocks timing generator control register system control register xin high-frequency clock xout (a) using a crystal or ceramic resonator xin xout (b) using an external oscillator (open) page 10 2. functional description 2.1 functions of the cpu core tmp88ph41ug 1. generate a divider output ( dvo ) pulse 2. generate the source clock for the time base timer 3. generate the source clock for the watchdog timer 4. generate the internal source clock for the timer counter 5. generate a warm-up clock when exiting stop mode (1) configuration of the timing generator the timing generator a 3-stage prescaler, 21-st age dividers, and a machine cycle counter. when reset and when entering/exiting stop mode , the prescaler and divi ders are cleared to 0. figure 2-4 configuration of the timing generator dv1ck fc prescaler divider divider selector timer counter machine cycle counter 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 s a y b 6 5 4 3 2 1 1 2 0 standby control circuit watchdog timer time base timer divider output etc. page 11 tmp88ph41ug note 1: fc: the high-frequency clock [hz], *: don?t care note 2: the cgcr register bits 4 and 3 show an indeterminate value when read. note 3: be sure to write ?0? to cgcr register bits 7, 6, 2, 1 and 0. note 1: *: don?t care note 2: be sure to write ?0? to tbtcr register bit 4. (2) machine cycle instruction execution and the intern al hardware operations are sync hronized to the system clocks. the minimum unit of instruction execution is referred to as the ?machine cycle?. the tlcs-870/x series has 15 types of instructions, from 1-cycl e instructions which are executed in one machine cycle up to 15-cycle instru ctions that require a maxi mum of 15 machine cycles. a machine cycle consists of four states (s0 to s3), with each st ate comprised of one main system clock cycle. figure 2-5 machine cycles divider control register cgcr (0030h) 76543210 0 0 dv1ck 0 0 0 (initial value: 000* *000) dv1ck selects input clock to the first divider stage 0: fc/4 1: fc/8 r/w timing generator control register tbtcr (0036h) 76543210 dvoen dvock 0 tbten tbtck (initial value: 0000 0000) main system clock states s0 s1 s2 s3 s0 s1 s2 s3 1/fc (0.20 s at 20 mhz) machine cycle page 12 2. functional description 2.1 functions of the cpu core tmp88ph41ug 2.1.4.3 standby control circuit the standby control circuit starts/stops the high-fre quency clock oscillator ci rcuit and selects the main system clock. the system contro l registers (syscr1, syscr2) are us ed to control operation modes of this circuit. figure 2-6 shows an operation mode tran sition diagram, followed by description of the sys- tem control registers. (1) single clock mode only the high-frequency clock osci llator circuit is used. because the main system clock is gener- ated from the high-frequency clock, the machin e cycle time in single clock mode is 4/fc [s]. 1. normal mode in this mode, the cpu core and peripheral hardware units are opera ted with the high-fre- quency clock. the tmp88ph41ug enters this normal mode after reset. 2. idle mode in this mode, the cpu and watchdog timer ar e turned off while the peripheral hardware units are operated with the hi gh-frequency clock. idle mode is entered into by using system control register 2. the device is placed out of this mode and back into normal mode by an interrupt from the peripheral hardware or an external interrupt. wh en imf (interrupt mas- ter enable flag) = 1 (interrupt enabled), the de vice returns to normal op eration after the inter- rupt has been serviced. when imf = 0 (interr upt disabled), the devi ce restarts execution beginning with the instruction next to one that placed it in idle mode. 3. stop mode the entire system operat ion including the oscillator circuit is halted, retaining the internal state immediately before being stopped, with a minimal amount of power consumed. stop mode is entered into by using system control register 1, and is exited by stop pin input (level or edge selectable). after an elap se of the warm-up time, the device restarts exe- cution beginning with the inst ruction next to one that placed it in stop mode. figure 2-6 operation mode transition diagram table 2-1 single clock mode operation mode oscillator circuit cpu core peripheral circuit machine cycle time high frequency low frequency single clock reset oscillate - reset reset 4/fc [s] normal operate operate idle stop stop stop stop - reset stop mode normal mode idle mode interrupt instruction input for releasing mode instruction reset deasserted page 13 tmp88ph41ug note 1: when entering from normal mode into stop mode, always be sure to set syscr1 page 14 2. functional description 2.1 functions of the cpu core tmp88ph41ug 2.1.4.4 controlling operation modes (1) stop mode stop mode is controlled by system control register 1 (syscr1) and the stop pin input. the stop pin is shared with p20 port and int5 (external interrupt input 5). stop mode is entered into by setting stop (syscr1 register b it 7) to 1. during stop mode, the device retains the following state. 1. stop oscillation, thereby stopping operation of all internal circuits. 2. the data memory, register, program status word, and port output latch hold the state in which they were immediately before entering stop mode. 3. clear the prescaler and divide r for the timing generator to 0. 4. the program counter holds the instruction ad dress two instructions ahead the one that placed the device in stop mode (e.g., ?set (syscr1).7?). the device is released from stop mode by the ac tive level or edge on stop pin input as selected by syscr1 page 15 tmp88ph41ug figure 2-7 released fr om stop mode by level note 1: once warm-up starts, the device does not return to stop mode even when the stop pin input is pulled low again. note 2: if relm is changed to 1 (level mode) after being set to 0 (edge mode), stop mode remains unchanged unless a rising edge on stop pin input is detected. a. released by edge (when relm = 0) the device is released from stop mode by a rising edge on stop pin input. this method is used in applications where a relatively short time of program processi ng is repeated at cer- tain fixed intervals. apply a fixed-period sign al (e.g., clock from the low-power oscillating source) to the stop pin. when relm = 0 (edge mode), the device is placed in stop mode even when the stop pin input level is high. figure 2-8 released fr om stop mode by edge example :entering stop mode from normal mode di ; imf 0 ld (syscr1) , 10010000b ; set to be released by edge when entering stop mode stop pin xout pin normal operation released from stop mode in hardware normal operation v ih stop mode warm-up detect low on stop pin input in a program before entering stop mode always released by a high level on stop pin input stop pin xout pin normal operation v ih stop mode warm-up stop mode placed into stop mode in a program released from stop mode in hardware by a rising edge on stop pin input. normal operation page 16 2. functional description 2.1 functions of the cpu core tmp88ph41ug the device is released from stop mode following the sequence described below. 1. only the high-frequency oscillator is oscillating. 2. a warm-up time is inserted in order to allow for the clock oscillation to stabilize. during warm-up, the internal circuits remain idle. the warm-up time can be selected from three choices according to the oscillator characteristics by using syscr1 page 17 tmp88ph41ug figure 2-9 entering and exit ing stop mode (when dv1ck = 0) oscillation instruction execution divider (a) entering stop mode (example: entered into by the set (syscr1). 7 instruction placed at address a) main system clock main system clock program counter stop stop a + 2 a + 3 n n + 1 n + 2 n + 3 n + 4 0 set (syscr1). 7 oscillator circuit oscillator circuit warm-up (b) exiting stop mode oscillation instruction execution divider program counter stop stop count up 0 0 1 2 3 a + 3 instruction at address a + 4 instruction at address a + 3 instruction at address a + 2 stop pin input a + 4 a + 5 a + 6 page 18 2. functional description 2.1 functions of the cpu core tmp88ph41ug (2) idle mode idle mode is controlled by system control re gister 2 (syscr2) and a maskable interrupt. dur- ing idle mode, the device retains the following state. 1. the cpu and watchdog timer stop operating. the peripheral hardware continues operating. 2. the data memory, register, program status word, and port output latch hold the state in which they were immediately before entering idle mode. 3. the program counter holds the instruction ad dress two instructions ahead the one that placed the device in idle mode. figure 2-10 idle mode example :placing the device in idle mode set (syscr2) . 4 place the device in idle mode (by instruction) stop the cpu and wdt interrupt handling execute the instruction next to one that placed device idle mode reset ye s no no no interrupt request ? imf = 1 reset input ? ye s yes (released by interrupt) (released normally) page 19 tmp88ph41ug the device can be released from id le mode normally or by an interr upt as selected with the inter- rupt master enable flag (imf). a. released normally (when imf = 0) the device can be released from idle mode by the interrupt source enabled by the inter- rupt individual enable flag (e f), and restarts execution beginning with the instruction next to one that placed it in idle mode. the interrupt latc h (il) for the interrupt source used to exit idle mode normally needs to be clear ed to 0 using a load instruction. b. released by interrupt (when imf = 1) the device can be released from idle mode by the interrupt source enabled by the inter- rupt individual enable flag (e f), and enters interrupt handling. after interrupt handling, the device returns to the instruction next to one that placed it in idle mode. the device can also be released from idle mode by pulling the reset pin input low, in which case the device is immediately reset as is normally reset by reset . after reset, the device starts oper- ating from normal mode. note: if a watchdog timer interrupt occurs immedi ately before entering idle mode, the device pro- cesses the watchdog timer interrupt without entering idle mode. page 20 2. functional description 2.1 functions of the cpu core tmp88ph41ug figure 2-11 entering and exiting idle mode (b) exiting idle mode (a) entering idle mode (example: entered into by the set instruction placed at address a) idle a + 2 a + 3 set (syscr2). 4 operating 1. released normally idle idle a + 3 a + 4 instruction at address a + 2 operating 2. released by interrupt idle idle a + 3 interrupt accepted operating main system clock interrupt request program counter instruction execution main system clock interrupt request program counter instruction execution watchdog timer main system clock interrupt request program counter instruction execution watchdog timer watchdog timer page 21 tmp88ph41ug 2.1.5 reset circuit the tmp88ph41ug has four ways to generate a reset: external reset input, address trap reset, watchdog timer reset and system clock reset. table 2-3 shows how the internal hardware is initialized by reset operation. at power-on time, the internal cause reset circuits (watch dog timer reset, address trap reset, and system clock reset) are not initialized. 2.1.5.1 external reset input the reset pin is a hysteresis input with a pull-up resistor included. by holding the reset pin low for at least three machine cycles (12/fc [s]) or more while the power supply voltage is within the rated operat- ing voltage range and the oscillator is oscillating stably, the device is reset and its internal state is initial- ized. when the reset pin input is released back high, the device is freed from reset and starts executing the program beginning with the vector addre ss stored at addresses ffffch to ffffeh. figure 2-12 reset circuit 2.1.5.2 adress trap reset if the cpu should start looping for reasons of noise, etc. and attempts to fetch instructions from the internal ram,sfr or dbr area, the de vice generats an internal reset. table 2-3 internal hardware in itialization by reset operation internal hardware initial value i nternal hardware initial value program counter (pc) (ffffeh to ffffch) prescaler and divider for the timing generator 0 stack pointer (sp) not initialized general-purpose registers (w, a, b, c, d, e, h, l) not initialized register bank selector (rbs) 0 watchdog timer enable jump status flag (jf) 1 zero flag (zf) not initialized output latch of input/output port see description of each input/output port. carry flag (cf) not initialized half carry flag (hf) not initialized sign flag (sf) not initialized overflow flag (vf) not initialized interrupt master enable flag (imf) 0 interrupt individual enable flag (ef) 0 control register see description of each control register. interrupt latch (il) 0 interrupt nesting flag (inf) 0 ram not initialized reset input vdd reset page 22 2. functional description 2.1 functions of the cpu core tmp88ph41ug the addess trap permission/prohibition is set by the address trap reset contro l register (atas,atkey). the address trap is permited initially and the inte rnal reset is generated by fetching from internal ram,sfr or dbr area. if th e address trap is prohibit ed, instructions in the internal ram area can be executed. note: read-modify-write instructions, such as a bit manipulat ion, cannot access atas or atkey register because these register are write only. note 1: in development tools, address trap cannot be pr ohibited in the internal ram,sfr or dbr area with the address trap control registers. when using dev elopment tools, even if the address trap permis- sion/prohibition setting is changed in the user?s pr ogram, this change is ineffective. to execute instructions from the ram area, development tools must be set accordingly. note 2: while the swi instruction at an address imm ediately before the address trap area is executing, the program counter is incremented to point to the next address in the address trap area; an address trap is therefore taken immediately. development tool setting ? to prohibit the address trap: 1. modify the iram (mapping attribute) area to (00040h to 000bfh) in the memory map win- dow. 2. set 000c0h to "address trap prohibition ar ea" as a new eram (mapping attribute) area. 3. load the user program 4. execute the address trap prohibition code in the user?s program 2.1.5.3 watchdog timer reset refer to the section ?watchdog timer.? 2.1.5.4 system clock reset when syscr2 page 23 tmp88ph41ug 3. interrupt control circuit the tmp88ph41ug has a total of 25 interrupt sources excl uding reset. interrupts can be nested with priorities. two of the internal interrupt sources are pseudo nonmaskable while the rest are maskable. interrupt sources are provided with interrupt latches (il) , which hold interrupt requests, and independent vectors. the interrupt latch is set to ?1? by th e generation of its interrupt request wh ich requests the cpu to accept its inter- rupts. interrupts are enabled or disabled by software using the interrupt master enable fl ag (imf) and in terrupt enable flag (ef). if more than one interrupts are generated simultaneously, interrup ts are accepted in order which is domi- nated by hardware. however, there are no prioritized interrupt factors among non-maskable interrupts. interrupt factors enable condition interrupt latch vector address priority internal/external (reset) nonmaskable ? ffffc high 0 internal intswi (software interrupt) pseudo nonmaskable ? ffff8 1 internal intwdt (watchdog timer interrupt) pseudo nonmaskable il2 ffff4 2 external int0 (external interrupt 0) imf? ef3 = 1, int0en = 1 il3 ffff0 3 - reserved imf? ef4 = 1 il4 fffec 4 external int1 (external interrupt 1) imf? ef5 = 1 il5 fffe8 5 internal inttbt (tbt interrupt) imf? ef6 = 1 il6 fffe4 6 - reserved imf? ef7 = 1 il7 fffe0 7 internal intemg (ch1 error detect interrupt) imf? ef8 = 1 il8 fffdc 8 - reserved imf? ef9 = 1 il9 fffd8 9 internal intclm1 (ch1 overload protection interrupt) imf? ef10 = 1 il10 fffd4 10 - reserved imf? ef11 = 1 il11 fffd0 11 internal inttmr31 (ch1 timer 3 interrupt) imf? ef12 = 1 il12 fffcc 12 - reserved imf? ef13 = 1 il13 fffc8 13 - reserved imf? ef14 = 1 il14 fffc4 14 external int5 (external interrupt 5) imf? ef15 = 1 il15 fffc0 15 internal intpdc1 (ch1 posision detect interrupt) imf? ef16 = 1 il16 fffbc 16 - reserved imf? ef17 = 1 il17 fffb8 17 internal intpwm1 (ch1 waveform generater interrupt) imf? ef18 = 1 il18 fffb4 18 - reserved imf? ef19 = 1 il19 fffb0 19 internal intedt1 (ch1 erectric angle timer interrupt) imf? ef20 = 1 il20 fffac 20 - reserved imf? ef21 = 1 il21 fffa8 21 internal inttmr11 (ch1 timer1 interrupt) imf? ef22 = 1 il22 fffa4 22 - reserved imf? ef23 = 1 il23 fffa0 23 internal inttmr21 (ch1 timer2 interrupt) imf? ef24 = 1 il24 fff9c 24 - reserved imf? ef25 = 1 il25 fff98 25 internal inttc1 (tc1 interrupt) imf? ef26 = 1 il26 fff94 26 internal intctc (ctc interrupt) imf? ef27 = 1 il27 fff90 27 - reserved imf? ef28 = 1 il28 fff8c 28 external int2 (external interrupt 2) imf? ef29 = 1 il29 fff88 29 external int3 (external interrupt 3) imf? ef30 = 1 il30 fff84 30 external int4 (external interrupt 4) imf? ef31 = 1 il31 fff80 31 internal intrx (uart receive interrupt) imf? ef32 = 1 il32 fff3c 32 internal inttx (uart transmit interrupt) imf? ef33 = 1 il33 fff38 33 internal intsio (sio interrupt) imf? ef34 = 1 il34 fff34 34 internal inttc3 (tc3 interrupt) imf? ef35= 1 il35 fff30 35 internal inttc4 (tc4 interrupt) imf? ef36 = 1 il36 fff2c 36 - reserved imf? ef37 = 1 il37 fff28 37 internal intadc (a/d converter interrupt) imf? ef38 = 1 il38 fff24 low 38 page 24 3. interrupt control circuit 3.1 interrupt latches (il38 to il2) tmp88ph41ug note 1: to use the watchdog timer interrupt (intwdt), clear wdtcr1 page 25 tmp88ph41ug 3.2 interrupt enab le register (eir) the interrupt enable register (eir) enables and disabl es the acceptance of interrupts, except for the pseudo non- maskable interrupts (software interrupt, undefined instru ction interrupt, address trap interrupt and watchdog inter- rupt). pseudo non-maskable interrupt is accep ted regardless of the contents of the eir. the eir consists of an interrupt mast er enable flag (imf) and the individua l interrupt enable flags (ef). these registers are located on address 003a h, 003bh, 002ch, 002dh and 002ah in sf r area, and they can be read and written by an instructions (including read-modify-write in structions such as bit manipulation or operation instruc- tions). 3.2.1 interrupt ma ster enable flag (imf) the interrupt enable register (imf ) enables and disables the acceptance of the whole maskable interrupt. while imf = ?0?, all maskable interrupts are not accepted regardless of the status on each individual interrupt enable flag (ef). by setting imf to ?1?, the inte rrupt becomes acceptable if th e individuals are enabled. when an interrupt is accepted, imf is cleared to ?0? after the latest st atus on imf is stacked. thus the maskable interrupts which follow are disabled temporarily . imf flag is set to "1" by the maskable interrupt return instruction [reti] after execu ting the interrupt service program r outine, and mcu can accept the inter- rupt again. the latest interrupt request is generated alr eady, it is available immedi ately after the [reti] instruc- tion is executed. on the pseudo non-maskable interrupt, the non-maskable return instruction [retn] is adopted. in this case, imf flag is set to "1" only when it performs the pseu do non-maskable interrupt service routine on the interrupt acceptable status (imf=1). however, imf is set to "0" in the pseudo non-maskable interrupt service routine, it maintains its status (imf="0"). the imf is located on bit0 in eirl (address: 003ah in sfr), and can be read and written by an instruction. the imf is normally set and cl eared by [ei] and [di] instruction respectively. during reset, the imf is initial- ized to ?0?. 3.2.2 individual interrupt enable flags (ef38 to ef3) each of these flags enables and disables the acceptan ce of its maskable interrupt . setting the corresponding bit of an individual interrupt enable flag to ?1? enables acceptan ce of its interrupt, and setting the bit to ?0? dis- ables acceptance. during reset, all the i ndividual interrupt enable flags (ef38 to ef3) ar e initialized to ?0? and all maskable interrupts are not accepted until they are set to ?1?. note:in main program, before manipulating the interrupt enable flag (ef) or the interrupt latch (il), be sure to clear imf to "0" (disable interrupt by di instruction). then set imf newly again as required after operating on the ef or il (enable interrupt by ei instruction) in interrupt service routine, because the imf become s "0" automatically, clearing imf need not execute nor- mally on interrupt service routine. however, if using mult iple interrupt on interrupt service routine, manipulat- ing ef or il should be executed before setting imf="1". example :enables interrupts individually and sets imf di ; imf 0 set (eirl), .5 ; ef5 1 clr (eirl), .6 ; ef6 0 clr (eirh), .4 ; ef12 0 clr (eird), .0 ; ef24 0 : ei ; imf 1 page 26 3. interrupt control circuit 3.2 interrupt enable register (eir) tmp88ph41ug note 1: il2 cannot alone be cleard. note 2: unable to detect the under-flow of counter. note 3: the nesting counter is set "0" initially, it performs c ount-up by the interrupt acceptance and count-down by executing t he interrupt return instruction. note 4: in main program, before manipulating the interrupt enable fl ag (ef) or the interrupt latch (il), be sure to clear imf to "0" (disable interrupt by di instruction). then set imf newly again as required after operating on the ef or il (enable interrupt by ei instruction) in interrupt service routine, because the imf becomes "0" automatically, clear ing imf need not execute normally on inter- rupt service routine. however, if using multiple interrupt on interrupt service routine, mani pulating ef or il should be exe- cuted before setting imf="1". note 5: do not clear il with read-modify-w rite instructions such as bit operations. interrupt latches (initial value: 0**0*0*0 *00*0000) ilh,ill (003dh, 003ch) 1514131211109876543210 il15 - - il12 - il10 - il8 - il6 il5 - il3 il2 inf ilh (003dh) ill (003ch) (initial value: 000*00*0 *0*0*0*0) ild,ile (002fh, 002eh) 1514131211109876543210 il31 il30 il29 - il27 il26 - il24 - il22 - il20 - il18 - il16 ild (002fh) ile (002eh) (initial value: *0*00000) ilc (002bh) 76543210 - il38 - il36 il35 il34 il33 il32 ile (002bh) il38 to il2 interrupt latches read write r/w 0: no interrupt request 1: interrupt request 0: clears the interrupt request (note1) 1: (unable to set interrupt latch) inf interrupt nesting flag 00: out of interrupt service 01: on interrupt service of level 1 10: on interrupt service of more than level 2 11: on interrupt service of more than level 3 00: reserved 01: clear the nesting counter 10: count-down 1 step for the nesting counter (note2) 11: reserved interrupt enable registers (initial value: 0**0*0*0 *00*0**0) eirh,eirl (003bh, 003ah) 1514131211109876543210 ef15 - - ef12 - ef10 - ef8 - ef6 ef5 - ef3 imf eirh (003bh) eirl (003ah) (initial value: 000*00*0 *0*0*0*0) eird,eire (002dh, 002ch) 1514131211109876543210 ef31 ef30 ef29 - ef27 ef26 - ef24 - ef22 - ef20 - ef18 - ef16 eird (002dh) eire (002ch) (initial value: *0*00000) eire (002ah) 76543210 - ef38 - ef36 ef35 ef34 ef33 ef32 eire (002ah) page 27 tmp88ph41ug note 1: do not set imf and the interrupt enable flag (ef38 to ef3) to ?1? at the same time. note 2: in main program, before manipulating the interrupt enable fl ag (ef) or the interrupt latch (il), be sure to clear imf to "0" (disable interrupt by di instruction). then set imf newly again as required after operating on the ef or il (enable interrupt by ei instruction) in interrupt service routine, because the imf becomes "0" automatically, clear ing imf need not execute normally on inter- rupt service routine. however, if using multiple interrupt on interrupt service routine, mani pulating ef or il should be exe- cuted before setting imf="1". ef38 to ef3 individual-interrupt enable flag (specified for each bit) 0: 1: disables the acceptance of each maskable interrupt. enables the acceptance of each maskable interrupt. r/w imf interrupt master enable flag 0: 1: disables the acceptance of all maskable interrupts enables the acceptance of all maskable interrupts page 28 3. interrupt control circuit 3.3 interrupt sequence tmp88ph41ug 3.3 interrupt sequence an interrupt request, which raised inte rrupt latch, is held, until interrupt is accepted or interrupt latch is cleared to ?0? by resetting or an instruction. interrupt accep tance sequence requires 12 machine cycles (2.4 s @20 mhz) after the completion of the current instruction. the interrupt serv ice task terminates upon execution of an interrupt return instruction [reti] (for maskable interrupts) or [retn] (for non-maskable interrupts). figure 3-1 shows the timing chart of interrupt acceptance processing. 3.3.1 interrupt acceptance proc essing is packaged as follows. a. the interrupt master enab le flag (imf) is cleared to ?0? in or der to disable the acceptance of any fol- lowing interrupt. b. the interrupt latch (il) for the interrupt source accepted is cleared to ?0?. c. the contents of the program coun ter (pc) and the program status word, including the interrupt master enable flag (imf), are saved (pushed) on the st ack in sequence of pswh, pswl, pce, pch, pcl. meanwhile, the stack pointer (sp) is decremented by 5. d. the entry address (interrupt vect or) of the corresponding interrupt service program, loaded on the vec- tor table, is transferred to the program counter. e. read the rbs control code from the vector table, add its msb(4bit) to the register bank selecter (rbs). f. count up the interrupt nesting counter. g. the instruction stored at the entry address of the inte rrupt service program is executed. note:when the contents of psw are saved on the stack, the contents of imf are also saved. note 1: a: return address, b: entry address, c: address which reti instruction is stored note 2: on condition that interrupt is enabled, it takes 62/fc [s] at maximum (if the interrupt latch is set at the first machin e cycle on 15 cycle instruction) to start interrupt accept ance processing since its interrupt latch is set. figure 3-1 timing chart of interrupt acceptance/return in terrupt instruction example: correspondence be tween vector table address for inttbt an d the entry address of the interrupt service program interrupt request interrupt latch (il) imf execute instruction pc sp 1-machine cycle interrupt service task n-3 n-4 n-4 a n-3 n n-5 a-1 a b b+1 b+2 a+1 a+2 b+3 c+2 c+1 execute instruction execute instruction execute reti instruction interrupt acceptance a+1 a n n-2 n-1 n-2 n-1 page 29 tmp88ph41ug figure 3-2 vector table address,entry address a maskable interrupt is not accepted until the imf is set to ?1? even if th e maskable interrupt higher than the level of current servicing interrupt is requested. in order to utilize nested interrupt service, the imf is set to ?1? in the interrupt service program. in this case, acceptable interrupt sour ces are selectively enabled by the individual interrupt enable flags. but don?t use the read-modify-write instruction for eirl(0003ah) on the pseudo non-maskable interrupt service task. to avoid overloaded nesting, clear the individual interrupt enable flag whose interrupt is currently serviced, before setting imf to ?1?. as for non-maskable interr upt, keep interrupt service shorten compared with length between interrupt requests; otherwise the status cannot be recovered as non-maskable interrupt would simply nested. 3.3.2 saving/restoring general-purpose registers during interrupt acceptance processing , the program counter (pc) and the program status word (psw, includes imf) are automati cally saved on the stack, but the accumulato r and others are not. these registers are saved by software if necessary. when multiple interrupt se rvices are nested, it is also necessary to avoid using the same data memory area for saving registers. the fo llowing four methods are used to save/restore the gen- eral-purpose registers. 3.3.2.1 using automatic register bank switcing by switching to non-use register bank, it can re store the general-purpose register at hige speed. usually the bank register "0" is assigned for main task and the bank register "1 to 15" are for the each interrupt service task. to make up its data memory efficiency, the common bank is assigned for non-mul- tiple intrrupt factor. it can return back to main-flow by executing the interrupt return instructions ([reti]/[retn]) from the current interrupt register bank automatically. thus, no need to restore the rbs by a program. 3.3.2.2 using register bank switching by switching to non-use register bank, it can restor e the general-purpose register at hige speed. usually the bank register "0" is assigned for main task and th e bank register "1 to 15" ar e for the each interrupt ser- vice task. example :register bank switching pintxx: (interrupt processing) ; begin of interrupt routine reti ; end of interrupt : vintxx: dp pintxx ; pintxx vector address setting db 1 ; rbs <- rbs + 1 rbs setting on pintxx 45h 23h 01h 06h fffe4h fffe5h fffe6h fffe7h vector rbs control code vector table address 12345h 12346h 12347h 12348h entry address interrupt service program page 30 3. interrupt control circuit 3.3 interrupt sequence tmp88ph41ug 3.3.2.3 using push and pop instructions if only a specific register is saved or interrupts of the same source are nested , general-purpose registers can be saved/restored using the push/pop instructions. figure 3-3 save/store register using push and pop instructions 3.3.2.4 using data transfer instructions to save only a specific register wi thout nested interrupts, data tran sfer instructions are available. example :register bank switching pintxx: ld rbs, n ; rbs <- n begin of interrupt routine (interrupt processing) reti ; end of interrupt , restore rbs and interrupt return : vintxx: dp pintxx ; pintxx vector address setting db 0 ; rbs <- rbs + 0 rbs setting on pintxx example :save/store register us ing push and pop instructions pintxx: push wa ; save wa register (interrupt processing) pop wa ; restore wa register reti ; return example :save/store register us ing data transfer instructions pintxx: ld (gsava), a ; save a register (interrupt processing) ld a, (gsava) ; restore a register reti ; return pc l pc h psw l psw h at acceptance of an interrupt pc l pc h psw l psw h a w pc l pc h psw l psw h b-5 b-4 b-3 b-2 b-1 b address (example) sp sp sp sp at execution of push instruction at execution of pop instruction at execution of reti instruction page 31 tmp88ph41ug figure 3-4 saving/restoring general-purpose r egisters under interrupt processing 3.3.3 interrupt return interrupt return instructions [reti]/[retn] perform as follows. interrupt requests are sampled during the final cycle of the instruction being executed. thus, the next inter- rupt can be accepted immediat ely after the interrupt retu rn instruction is executed. note: when the interrupt processing time is longer than t he interrupt request generation time, the interrupt service task is performed but not the main task. [reti] maskable interrupt return [retn] non-maskable interrupt return 1. the contents of the program counter and the program status word are restored from the stack. 2. the stack pointer is incremented 5 times. 3. the interrupt master enable flag is set to "1". 4. the interrupt nesting counter is decremented, and the interrupt nesting flag is changed. 1. the contents of the program counter and the program status word are restored from the stack. 2. the stack pointer is incremented 5 times. 3. the interrupt master enable flag is set to "1" only when a non-maskable interrupt is accepted in interrupt enable status. however, the interrupt master enable flag remains at "0" when so clear by an interrupt service program. 4. the interrupt nesting counter is decremented, and the interrupt nesting flag is changed. main task interrupt acceptance interrupt return interrupt service task saving registers restoring registers main task bank m interrupt acceptance interrupt return interrupt service task switch to bank n automatically restore to bank m automatically by [reti]/[retn] bank m bank n switch to bank n by ld, rbs and n instruction (a) saving/restoring by register bank changeover (b) saving/restoring general-purpose registers using push/pop data transfer instruction bank m page 32 3. interrupt control circuit 3.4 software interrupt (intsw) tmp88ph41ug 3.4 software interrupt (intsw) executing the swi instruction generates a software interr upt and immediately starts interrupt processing (intsw is highest prioritized interrupt). however, if processing of a non-maskable inerrupt is already underway, executing the swi instruction will not generate a software interrupt but will result in the same operation as the nop instruc- tion. use the swi instruction only for detection of the address error or for debugging. 3.4.1 address error detection ffh is read if for some cause such as noise the cpu attempts to fetch an instruction from a non-existent memory address during single chip mode. code ffh is th e swi instruction, so a software interrupt is gener- ated and an address error is detect ed. the address error detection range can be further expanded by writing ffh to unused areas of the program memory. address trap reset is generated in case that an instruction is fetched from ram, dbr or sfr areas. 3.4.2 debugging debugging efficiency can be increased by placing the swi instruction at the software break point setting address. page 33 tmp88ph41ug 3.5 external interrupts the tmp88ph41ug has 6 external interrupt inputs. these in puts are equipped with di gital noise reject circuits (pulse inputs of less than a certa in time are elimin ated as noise). edge selection is also possible with int1 to int4. the int0 /p10 pin can be configured as either an external inter- rupt input pin or an input/output port, and is configured as an input port during reset. edge selection, and noise reject control and int0 /p10 pin function selection are performed by the external inter- rupt control register (eintcr). note 1: in normal or idle mode, if a signal with no noise is input on an external interrupt pin, it takes a maximum of "signal establishment time" from the input si gnal's edge to set the interrupt latch. (1) int1 pin 49/fc [s] ( at eintcr< int1nc> = "1") , 193/fc [s] ( at eintcr page 34 3. interrupt control circuit 3.5 external interrupts tmp88ph41ug note 1: fc: high-frequency clock [hz], *: don?t care note 2: when the external interrupt control register (eintcr) is overwritten, the noise canceller may not operate normally. it i s recommended that external interrupts are disabl ed using the interrupt enable register (eir). note 3: the maximum time from modifying eintcr page 35 tmp88ph41ug 4. special function register the tmp88ph41ug adopts the memory mapped i/o system, and all peripheral control and transfers are per- formed through the special function register (sfr) or the data buffer register (dbr). the sfr is mapped on address 0000h to 003fh, dbr is mapped on address 1f80h to 1fffh. this chapter shows the arrangement of the special functi on register (sfr) and data buffer register (dbr) for tmp88ph41ug. 4.1 sfr address read write 0000h reserved 0001h p1dr 0002h p2dr 0003h p3dr 0004h p4dr 0005h reserved 0006h p6dr 0007h reserved 0008h reserved 0009h reserved 000ah reserved 000bh p1cr 000ch reserved 000dh reserved 000eh reserved 000fh tc1cr 0010h tc1dral 0011h tc1drah 0012h tc1drbl 0013h tc1drbh 0014h ctc1cr1 0015h ctc1cr2 0016h - ctc1drl 0017h - ctc1drh 0018h reserved 0019h reserved 001ah tc4cr 001bh tc4dr 001ch tc3dra 001dh tc3drb - 001eh tc3cr 001fh reserved 0020h reserved 0021h reserved 0022h reserved 0023h reserved 0024h reserved 0025h reserved page 36 4. special function register 4.1 sfr tmp88ph41ug note 1: do not access reserved areas by the program. note 2: ? ; cannot be accessed. note 3: write-only registers and interrupt latches cannot use the read-modify-write instructions (bit manipulation instructions such as set, clr, etc. and logical operation instructions such as and, or, etc.). 0026h adccra 0027h adccrb 0028h adcdrl - 0029h adcdrh - 002ah eirc 002bh ilc 002ch eire 002dh eird 002eh ile 002fh ild 0030h cgcr 0031h reserved 0032h reserved 0033h reserved 0034h - wdtcr1 0035h - wdtcr2 0036h tbtcr 0037h eintcr 0038h syscr1 0039h syscr2 003ah eirl 003bh eirh 003ch ill 003dh ilh 003eh pswl 003fh pswh address read write page 37 tmp88ph41ug 4.2 dbr address pmd ch read write 1f80h ? 1f81h ? 1f82h ? 1f83h p3ode 1f84h p4ode 1f85h ? 1f86h ? 1f87h ? 1f88h ? 1f89h p3cr 1f8ah p4cr 1f8bh ? 1f8ch p6cr 1f8dh ? 1f8eh ? 1f8fh ? 1f90h uartsel 1f91h uartsr uartcra 1f92h ? uartcrb 1f93h rdbuf tdbuf 1f94h ? atas 1f95h ? atkey 1f96h ? siocr1 1f97h siosr siocr2 1f98h siobr0 1f99h siobr1 1f9ah siobr2 1f9bh siobr3 1f9ch siobr4 1f9dh siobr5 1f9eh siobr6 1f9fh siobr7 1fa0h for pmd ch.1 pdcra 1fa1h for pmd ch.1 pdcrb 1fa2h for pmd ch.1 pdcrc ? 1fa3h for pmd ch.1 sdreg 1fa4h for pmd ch.1 mtcra 1fa5h for pmd ch.1 mtcrb 1fa6h for pmd ch.1 mcapl ? 1fa7h for pmd ch.1 mcaph ? 1fa8h for pmd ch.1 cmp1l 1fa9h for pmd ch.1 cmp1h 1faah for pmd ch.1 cmp2l 1fabh for pmd ch.1 cmp2h 1fach for pmd ch.1 cmp3l 1fadh for pmd ch.1 cmp3h 1faeh for pmd ch.1 mdcra 1fafh for pmd ch.1 mdcrb page 38 4. special function register 4.2 dbr tmp88ph41ug note 1: do not access reserved areas by the program. note 2: ? ; cannot be accessed. note 3: write-only registers and interrupt latches cannot use the read-modify-write instructions (bit manipulation instructions such as set, clr, etc. and logical operation instructions such as and, or, etc.). 1fb0h for pmd ch.1 emgcra 1fb1h for pmd ch.1 emgcrb 1fb2h for pmd ch.1 mdoutl 1fb3h for pmd ch.1 mdouth 1fb4h for pmd ch.1 mdcntl ? 1fb5h for pmd ch.1 mdcnth ? 1fb6h for pmd ch.1 mdprdl 1fb7h for pmd ch.1 mdprdh 1fb8h for pmd ch.1 cmpul 1fb9h for pmd ch.1 cmpuh 1fbah for pmd ch.1 cmpvl 1fbbh for pmd ch.1 cmpvh 1fbch for pmd ch.1 cmpwl 1fbdh for pmd ch.1 cmpwh 1fbeh for pmd ch.1 dtr 1fbfh for pmd ch.1 ? emgrel 1fc0h for pmd ch.1 edcra 1fc1h for pmd ch.1 edcrb 1fc2h for pmd ch.1 edsetl 1fc3h for pmd ch.1 edseth 1fc4h for pmd ch.1 eldegl 1fc5h for pmd ch.1 eldegh 1fc6h for pmd ch.1 ampl 1fc7h for pmd ch.1 amph 1fc8h for pmd ch.1 edcapl ? 1fc9h for pmd ch.1 edcaph ? 1fcah for pmd ch.1 ? wfmdr 1fcbh ? 1fcch reserved to : 1fffh reserved address pmd ch read write page 39 tmp88ph41ug 5. input/output ports the tmp88ph41ug contains 5 input/output ports comprised of 33 pins. all output ports contain a latch, and the output data ther efore are retained by the latch. but none of the input ports have a latch, so it is desirable that the input data be retain ed externally until it is read out, or read several times before being processed. figure 5-1 shows input/output timing. the timing at which external data is read in from input/out put ports is s1 state in the read cycle of instruction exe- cution. because this timing cannot be recognized from the out side, transient input data such as chattering needs to be dealt with in a program. the timing at which data is forwarded to input/output ports is s2 state in the write cycle of instruction execution. note: the read/write cycle positi ons vary depending on instructions. figure 5-1 example of input/output timing primary function secondary functions port p1 6-bit i/o port external interrupt input, timer/counter input/output, divider output port p2 3-bit i/o port external interrupt input, timer/counter input/output, stop mode release signal input port p3 8-bit i/o port motor control input/output port p4 8-bit i/o port timer/counter output, serial interface input/output, motor control circuit input port p6 8-bit i/o port analog input and motor control circuit output !" #" $" %" !" #" $" %" !" #" $" % & ' !" #" $" %" !" #" $" %" !" #" $" % ( & ( page 40 5. input/output ports tmp88ph41ug when an operation is performed for read from any input/output port except programmable input/output ports, whether the input value of the pin or the content of the output latch is read depends on the instruction executed, as shown below. 1. instructions which read the content of the output latch - xch r, (src) - set/clr/cpl (src).b - set/clr/cpl (pp).g - ld (src).b, cf - ld (pp).b, cf - xch cf, (src). b - add/addc/sub/subb/and/or/xor (src), n - add/addc/sub/subb/and/or/xor (src), (hl) instructions, the (src) side thereof - mxor (src), m 2. instructions which read the input value of the pin any instructions other than those listed above and add/addc/sub/subb/and/or/xor (src),(hl) instructions, the (hl) side thereof page 41 tmp88ph41ug 5.1 port p1 (p15 to p10) port p1 is an 6-bit input/output port shared with external interrupt input, timer/counter input/output, and divider output. this port is switched between input and output modes using the p1 port input/output control register (p1cr). when reset, the p1cr register is initialized to 0, with the p1 port set for input mode. also, the output latch (p1dr) is initialized to 0 when reset. figure 5-2 port p1 note 1: when a read instruction is excuted on p1 por t, indeterminate values are read in from bits 7 to 6. note 2: *: don?t care p1 port input/output register p1dr (00001h) 76543210 p15 p14 ppg1 p13 dvo p12 int2 tc1 p11 int1 p10 int0 read/write (initial value: **00 0000) p1cr (0000bh) 76543210 (initial value: **00 0000) page 42 5. input/output ports tmp88ph41ug 5.2 port p2 (p22 to p20) port p2 is a 3-bit input/output port shared with external interrupt input and stop mode release signal. when using this port as these functional pins or an input port, set the ou tput latch to 1. when reset, the output latch is initialized to 1. we recommend using the p20 pin as external interrupt inpu t, stop mode release signal input, or input port. when using this port as an output port, note that the interrupt la tch is set by a falling edge of output pulse. and note that outputs on this port during st op mode go to a high-imp edance state even if syscr1 page 43 tmp88ph41ug 5.3 port p3 (p37 to p30) port p3 is an 8-bit input/output port. this port is switched between input and output modes using the p3 port input/ output control register (p3cr). when rese t, the p3cr register is initialized to 0, with the p3 port set for input mode. also, the output latch (p3dr) is initialized to 0 when reset. the p3 port contains bitwise programmable open-drain control. the p3 port open-drain control register (p3ode) is used to select open-drain or tri-state mode fo r the port. when reset, the p3ode register is initialized to 0, with tri-state mode selected for the port. figure 5-4 port p3 note 1: even when open-drain mode is selected, the protecti ve diode remains connected. therefore, do not apply voltages exceeding v dd . note 2: read-modify-write (rmw) operation executes at open-dr ain mode is selected, read out the output latch states. when any other instruction is executed, external pin states is read out. note 3: for pmd circuit output, set the p3dr output latch to 1. note 4: when using p3 port as an input/ output port, disable the emg1 circuit. p3 port input/output registers p3dr (00003h) 76543210 p37 cl1 p36 emg1 p35 u1 p34 v1 p33 w1 p32 x1 p31 y1 p30 z1 read/write (initial value: 0000 0000) p3cr (01f89h) 76543210 (initial value: 0000 0000) p3cr p3 port input/output control (specify bitwise) 0: input mode 1: output mode r/w p3ode (01f83h) 76543210 (initial value: 0000 0000) p3ode p3 port open-drain control (specify bitwise) 0: tri-state 1: open drain r/w page 44 5. input/output ports tmp88ph41ug 5.4 port p4 (p47 to p40) port p4 is an 8-bit input/output port shared with serial interface input/output. this por t is switched between input and output modes using the p4 port input/output control regi ster (p4cr). when reset, the p4cr register is initialized to 0, with the p4 port set for input mode. also, the output latch (p4dr) is initialized to 0 when reset. the p4 port contains bitwise programmable open-drain cont rol. the p4 port open-drain control register (p4ode) is used to select open-drain or tri-state mode for the port. when reset, the p4ode register is initialized to 0, with tri- state mode selected for the port. figure 5-5 port p4 note 1: even when open-drain mode is selected, the protecti ve diode remains connected. therefore, do not apply voltages exceeding v dd . note 2: read-modify-write (rmw) operation executes at open-dr ain mode is selected, read out the output latch states. when any other instruction is executed, external pin states is read out. note 3: when using the ctc 16-bit timer (ctc) as an ordinary timer, set p47 (ctc) for output mode. p4 port input/output registers p4dr (00004h) 76543210 p47 ctc p46 ppg2 p45 so txd p44 si rxd p43 sck p42 pdu1 p41 pdv1 p40 pdw1 (initial value: 0000 0000) p4cr (01f8ah) 76543210 (initial value: 0000 0000) p4cr p4 port input/output control (specify bitwise) 0: input mode 1: output mode r/w p4ode (01f84h) 76543210 (initial value: 0000 0000) p4ode p4 port open-drain control (specify bitwise) 0: tri-state 1: open drain r/w page 45 tmp88ph41ug 5.5 port p6 (p67 to p60) port p6 is an 8-bit input/output port shared with ad co nverter analog input. this port is switched between input and output modes using the p6 port input/output control register (p6cr), p6 port output latch (p6dr), and adc- cra ! " # $% %&$ ' ( ) ( ) $ ! page 46 5. input/output ports tmp88ph41ug accept input. (a read-modify-write instruct ion first reads data from all of the eight bits and after modifying them (bit manip- ulation), writes data for all of the eight bits to the output latches.) page 47 tmp88ph41ug 6. time base timer (tbt) and divider output ( dvo ) 6.1 time base timer the time base timer generates time base for key scanning, dynamic displaying, etc. it also provides a time base timer interrupt (inttbt). an inttbt ( time base timer interrupt ) is generated on the first falling edge of source clock ( the divider out- put of the timing generator which is selected by tbtck. ) after time base timer has been enabled. the divider is not cleared by the program; therefore, onl y the first interrupt may be generated ahead of the set interrupt period ( figure 6-2 ). the interrupt frequency (tbtck) must be selected with the time base timer disabled (tbten="0"). (the inter- rupt frequency must not be changed with the disble from the enable state.) both frequency selection and enabling can be performed simultaneously. figure 6-1 time base timer configuration figure 6-2 time base timer interrupt example :set the time base timer frequency to fc/2 16 [hz] and enable an inttbt interrupt. ld (tbtcr) , 00000010b ; tbtck 010 (freq. set) ld (tbtcr) , 00001010b ; tbten 1 (tbt enable) di set (eirl) . 6 ei fc/2 23 ,fc/2 24 fc/2 21 ,fc/2 22 fc/2 16 ,fc/2 17 fc/2 14 ,fc/2 15 fc/2 13 ,fc/2 14 fc/2 12 ,fc/2 13 fc/2 11 ,fc/2 12 fc/2 9 ,fc/2 10 tbtcr tbten tbtck 3 mpx source clock falling edge detector time base timer control register inttbt interrupt request source clock enable tbt interrupt period tbtcr page 48 6. time base timer (tbt) and divider output (dvo) 6.1 time base timer tmp88ph41ug time base timer is controled by time base timer control register (tbtcr). note 1: fc; high-frequency clock [hz], *; don't care note 2: always set "0" in bit4 on tbtcr register. time base timer control register 7 6543210 tbtcr (00036h) (dvoen) (dvock) 0 tbten tbtck (initial value: 0000 0000) tbten time base timer enable / disable 0: disable 1: enable tbtck time base timer interrupt frequency select : [hz] normal, idle mode r/w dv1ck=0 dv1ck=1 000 fc/2 23 fc/2 24 001 fc/2 21 fc/2 22 010 fc/2 16 fc/2 17 011 fc/2 14 fc/2 15 100 fc/2 13 fc/2 14 101 fc/2 12 fc/2 13 110 fc/2 11 fc/2 12 111 fc/2 9 fc/2 10 table 6-1 time base timer interrupt frequency ( example : fc = 20.0 mhz ) tbtck time base timer interrupt frequency [hz] normal, idle mode dv1ck = 0 dv1ck = 1 000 2.38 1.20 001 9.53 4.78 010 305.18 153.50 011 1220.70 610.35 100 2441.40 1220.70 101 4882.83 2441.40 110 9765.63 4882.83 111 39063.00 19531.25 page 49 tmp88ph41ug 6.2 divider output ( dvo ) approximately 50% duty pulse can be output using the divider output circuit, which is useful for piezoelectric buzzer drive. divider output is from dvo pin. figure 6-3 divider output the divider output is controlled by the time base timer control register (tbtcr). note 1: selection of divider output frequency (dvock) must be made while divider output is disabled (dvoen="0"). also, in other words, when changing the state of the divider output frequency from enabled (dvoen="1") to disable(dvoen="0"), do not change the setting of the divider output frequency. note 2: in case of using dvo output, set output mode by p1cr register after setting the related port output latch to "1" by p1dr register. note 3: fc; high-frequency clock [hz], *; don't care note 4: be sure to write "0" to tbtcr register bit 4. time base timer control register 7654 321 0 tbtcr (00036h) dvoen dvock "0" (tbten) (tbtck) (initial value: 0000 0000) dvoen divider output enable / disable 0: disable 1: enable r/w dvock divider output ( dvo ) frequency selection: [hz] normal, idle mode r/w dv1ck=0 dv1ck=1 00 fc/2 13 fc/2 14 01 fc/2 12 fc/2 13 10 fc/2 11 fc/2 12 11 fc/2 10 fc/2 11 tbtcr output latch port output latch mpx dvoen tbtcr page 50 6. time base timer (tbt) and divider output (dvo) 6.2 divider output (dvo) tmp88ph41ug example : 2.44 khz pulse output (fc = 20.0 mhz) port setting ld (tbtcr) , 00000000b ; dvock "00" ld (tbtcr) , 10000000b ; dvoen "1" table 6-2 divider output frequency ( example : fc = 20.0 mhz ) dvock divider output frequency [hz] normal, idle mode dv1ck=0 dv1ck=1 00 2.4415 k 1.22075 k 01 4.8825 k 2.4415 k 10 9.765 k 4.8825 k 11 19.5325 k 9.765 k page 51 tmp88ph41ug 7. watchdog timer (wdt) the watchdog timer is a fail-safe system to detect rapidl y the cpu malfunctions such as endless loops due to spu- rious noises or the deadlock conditions, and return the cpu to a sy stem recovery routine. the watchdog timer signal for detecting malfunctions can be programmed only once as ?r eset request? or ?pseudo nonmaskable interrupt request?. upon the reset releas e, this signal is initia lized to ?reset request?. when the watchdog timer is not used to detect malfunctions, it can be used as the timer to provide a periodic inter- rupt. note: care must be taken in system des ign since the watchdog timer functions are not be operated completely due to effect of disturbing noise. 7.1 watchdog timer configuration figure 7-1 watchdog timer configuration 0034 h overflow wdt output internal reset binary counters wdtout writing clear code writing disable code wdten wdtt 2 0035 h watchdog timer control registers wdtcr1 wdtcr2 intwdt interrupt request interrupt request reset request reset release clock clear 1 2 controller q sr s r q selector fc/2 23 ,fc/2 24 fc/2 21 ,fc/2 22 fc/2 19 ,fc/2 20 fc/2 17 ,fc/2 18 page 52 7. watchdog timer (wdt) 7.2 watchdog timer control tmp88ph41ug 7.2 watchdog timer control the watchdog timer is controlled by the watchdog timer control registers (wdtcr1 and wdtcr2). the watch- dog timer is automatically enabled after the reset release. 7.2.1 malfunction detection me thods using the watchdog timer the cpu malfunction is detected, as shown below. 1. set the detection time, select the output, and clear the binary counter. 2. clear the binary counter repeatedly within the specified detection time. if the cpu malfunctions such as en dless loops or the deadlock condition s occur for some reason, the watch- dog timer output is activated by the binary-counter overflow unless the binary counters are cleared. when wdtcr1 page 53 tmp88ph41ug note 1: after clearing wdtcr1 page 54 7. watchdog timer (wdt) 7.2 watchdog timer control tmp88ph41ug 7.2.3 watchdog timer disable to disable the watchdog timer, set the register in accordance with the fo llowing procedures . setting the reg- ister in other procedures causes a malfunction of the microcontroller. 1. set the interrupt master flag (imf) to ?0?. 2. set wdtcr2 to the clear code (4eh). 3. set wdtcr1 page 55 tmp88ph41ug 7.2.5 watchdog timer reset when a binary-counter overflow occurs while wdt cr1 page 56 7. watchdog timer (wdt) 7.2 watchdog timer control tmp88ph41ug page 57 tmp88ph41ug 8. 16-bit timercounter 1 (tc1) 8.1 configuration figure 8-1 timercounter 1 (tc1) :::? pin tc1 :w:?::? mett1 start capture clear source clock ppg output mode write to tc1cr 16-bit up-counter clear tc1drb selector tc1dra tc1cr tc1 control register match inttc1 interript tff1 acap1 tc1ck window mode set toggle q 2 toggle set clear q y a d b c s b a y s tc1s clear mppg1 ppg output mode internal reset s enable mcap1 s y a b tc1s 2 set clear command start decoder external trigger start edge detector note: function i/o may not operate depending on i/o port setting. for more details, see the chapter "i/o port". port (note) q pulse width measurement mode falling rising trigger external cmp 16-bit timer register a, b pulse width measurement mode port (note) fc/2 11 , fc/2 12 fc/2 7 , fc/2 8 fc/2 3 , fc/2 4 page 58 8. 16-bit timercounter 1 (tc1) 8.2 timercounter control tmp88ph41ug 8.2 timercounter control the timercounter 1 is controlled by the timercounter 1 control register (tc1cr) and two 16-bit timer registers (tc1dra and tc1drb). note 1: fc: high-frequency clock [hz] note 2: the timer register consists of two shift registers. a va lue set in the timer register becomes valid at the rising edge o f the first source clock pulse that occurs after the upper byte (t c1drah and tc1drbh) is written. therefore, write the lower byte and the upper byte in this order (it is recommended to write the register with a 16-bit acce ss instruction). writing only the lower byte (tc1dral and tc1drbl) does not enable the setting of the timer register. note 3: to set the mode, source clock, ppg output control and timer f/f control, write to tc1cr during tc1cr page 59 tmp88ph41ug note 5: to set the timer registers, the following relationship must be satisfied. tc1dra > tc1drb > 1 (ppg output mode), tc1dra > 1 (other modes) note 6: set tc1cr page 60 8. 16-bit timercounter 1 (tc1) 8.3 function tmp88ph41ug 8.3 function timercounter 1 has six types of operating modes: timer, external trigger timer, event counter, window, pulse width measurement, programmable pulse generator output modes. 8.3.1 timer mode in the timer mode, the up-counter counts up using the in ternal clock. when a match between the up-counter and the timer register 1a (tc1dra) va lue is detected, an inttc1 interrupt is generated and the up-counter is cleared. after being cleared, the up-c ounter restarts counting. setting tc 1cr page 61 tmp88ph41ug figure 8-2 timer mode timing chart match detect acap1 tc1drb tc1dra inttc1 interruput request source clock counter source clock counter ? (a) timer mode (b) auto-capture ? 7 6 345 0 timer start 12 3 2 1 4 0 counter clear capture n + 1 n n n m + 2 m + 1 m m capture m + 2 m + 1 n + 1 n m ? 1 m ? 1 m ? 2 n ? 1 n ? 1 n ? 1 page 62 8. 16-bit timercounter 1 (tc1) 8.3 function tmp88ph41ug 8.3.2 external trigger timer mode in the external trigger timer mode, the up-counter starts counting by the input pulse triggering of the tc1 pin, and counts up at the edge of the internal clock. for the trigger edge used to start counting, either the rising or falling edge is defined in tc1cr page 63 tmp88ph41ug figure 8-3 external tri gger timer mode timing chart inttc1 interrupt request source clock up-counter tc1dra tc1 pin input inttc1 interrupt request source clock up-counter tc1dra tc1 pin input 0 at the rising edge (tc1s = 10) at the rising edge (tc1s = 10) (a) trigger start (mett1 = 0) count start match detect count start 0 1 2 3 4 2 3 n (b) trigger start and stop (mett1 = 1) count start count start 0 1 2 3 m 0 n n 0 count clear note: m < n count clear 1 2 3 1 n m ? 1 n ? 1 match detect count clear page 64 8. 16-bit timercounter 1 (tc1) 8.3 function tmp88ph41ug 8.3.3 event counter mode in the event counter mode, the up-counter counts up at the edge of the input pulse to the tc1 pin. either the rising or falling edge of the input pulse is se lected as the count up edge in tc1cr page 65 tmp88ph41ug 8.3.4 window mode in the window mode, the up-counter counts up at the rising edge of the pulse that is logical anded product of the input pulse to the tc1 pin (window pulse) and the internal source clock. eith er the positive logic (count up during high-going pulse) or negative logic (count up during low-going pulse) can be selected. when a match between the up-counter and the tc1dra va lue is detected, an inttc1 interrupt is generated and the up-counter is cleared. define the window pulse to the frequency which is sufficiently lower than the internal source clock pro- grammed with tc1cr page 66 8. 16-bit timercounter 1 (tc1) 8.3 function tmp88ph41ug 8.3.5 pulse width measurement mode in the pulse width measurement mode, the up-counter starts counting by the input pulse triggering of the tc1 pin, and counts up at the edge of the internal clock. either the rising or falling edge of the internal clock is selected as the trigger edge in tc1cr< tc1s>. either the single- or double-e dge capture is selected as the trig- ger edge in tc1cr page 67 tmp88ph41ug example :duty measurem ent (resolution fc/2 7 [hz], cgcr page 68 8. 16-bit timercounter 1 (tc1) 8.3 function tmp88ph41ug figure 8-6 pulse wi dth measurement mode tc1drb inttc1 interrupt request interrupt request tc1 pin input counter internal clock (mcap1 = "1") 23 n count start count start trigger (tc1s = "10") 1 3 2 1 4 0 n 0 capture n - 1 tc1drb inttc1 tc1 pin input counter internal clock (mcap1 = "0") 12 n count start count start (tc1s = "10") 3 2 1 4 0 n capture capture n + 1 m - 2 n + 3 n + 2 n + 1 m - 1 m0 m [application] high-or low-level pulse width measurement [application] (1) cycle/frequency measurement (2) duty measurement (a) single-edge capture (b) double-edge capture page 69 tmp88ph41ug 8.3.6 programmable pulse generate (ppg) output mode in the programmable pulse generation (ppg) mode, an arbitrary duty pulse is generated by counting per- formed in the internal clock. to start the timer, tc1c r page 70 8. 16-bit timercounter 1 (tc1) 8.3 function tmp88ph41ug figure 8-7 ppg output example :generating a pulse which is high-going for 800 s and low-going for 200 s (fc = 20 mhz, cgcr page 71 tmp88ph41ug figure 8-8 pp g mode timing chart inttc1 tc1dra internal clock counter tc1drb tc1dra ppg pin output 0 inttc1 interrupt request interrupt request 12 m01 2 n m01 n 2 n n + 1 n + 1 m (a) continuous pulse generation (tc1s = 01) tc1drb trigger count start timer start counter internal clock tc1 pin input ppg pin output 0 1m n n n + 1 m 0 (b) one-shot pulse generation (tc1s = 10) match detect note: m > n note: m > n [application] one-shot pulse output page 72 8. 16-bit timercounter 1 (tc1) 8.3 function tmp88ph41ug page 73 tmp88ph41ug 9. 16-bit timer (ctc) 9.1 configuration figure 9-1 ctc block diagram ctc1cr2 ctc1cr1 3 2 2 2 3 3 toggle q set clear ? ctc1s ctc1sm ctc1se ctc1cy ctc1e ? rising edge falling edge s a y b ctc pin h a b c d y e s fc/2 11 or fc/2 12 fc/2 7 or fc/2 8 fc/2 5 or fc/2 6 fc/2 3 or fc/2 4 fc/2 2 or fc/2 3 fc/2 or fc/2 2 ctc1ck ctc1s ctc1res extrgdis ctc1reg ctc1ck ctc1ff0 ppgff0 ctc1m ctc1cy ctc1se ctc1e ctc1sm ctc1m ctc1ff0 ppgff0 ctc1m ctc1reg last coincidence interrupt stop trigger clear start start control read/write control and clear interrupt select write register select read register ctc1dra ctc1drb ctc1drc 16-bit up counter intctc1 interrupt ppg2 pin edge detection comparator extrgdis page 74 9. 16-bit timer (ctc) 9.1 configuration tmp88ph41ug 9.2 control compare timer/counter 1 is controlled using compar e timer/counter 1 control registers (ctc1cr1 and ctc1cr2), as well as three 16-bit timer re gisters (ctc1dra, ctc1drb, and ctc1drc). note: ctc1dra, ctc1drb, and ctc1drc are write-only registers and must not be used with any of the read-modify-write instructions such as set, clr, etc. note 1: *: don?t care note 2: the ctc1cr1 page 75 tmp88ph41ug note 1: fc: clock [hz] note 2: make sure the timer/counter is idle (ctc1cr1 page 76 9. 16-bit timer (ctc) 9.1 configuration tmp88ph41ug note 10:specifying ctc1cr1 page 77 tmp88ph41ug 9.3 function compare timer/counter 1 has three modes: timer, event counter, and programmable pulse generator output modes. 9.3.1 timer mode with software start in this mode, the timer/counter (16-bit counter) counts up synchronously with the internal clock. when the counter value and the set value of compare timer regi ster 1a (ctc1dra) match, an intctc1 interrupt is generated and the counter is cleared. after the coun ter is cleared, it restarts and continues counting up. figure 9-2 timer mode timing chart note:if the ctc input port (p47) is set for input mode, the timer/counter is reset by an input edge on port. when using the timer/counter as an ordinary timer, set ctc1cr2 page 78 9. 16-bit timer (ctc) 9.1 configuration tmp88ph41ug 9.3.2 timer mode with ex ternal trigger start in this timer mode, the timer/counter starts counting as triggered by input on ctc pin (rising or falling edge selected with ctc1cr1 page 79 tmp88ph41ug figure 9-4 external tr igger mode timing chart 9.3.3 event counter mode in this mode, the timer/counter counts up at the active edge on ctc pin in put (rising or falling edge selected with the ctc1cr1 page 80 9. 16-bit timer (ctc) 9.1 configuration tmp88ph41ug 9.3.4 programmable pulse generate (ppg) output mode the timer/counter starts counting as a command or edge on ctc pin input (rising/falling edge and one/both edges respectively selected with the ctc1cr1 page 81 tmp88ph41ug figure 9-6 one register comm and start mode timing chart (i) one register used (ctc1reg = 00) when set to command start. ctc pin input counter timer register a 11 1 n n 0 intctc1 interrupt command start n ppg2 pin output 1 n 1 2 3 n successive page 82 9. 16-bit timer (ctc) 9.1 configuration tmp88ph41ug figure 9-7 two register one edge trigger star t mode timing chart (ii) two registers used (ctc1reg = 01) when set to the external trigger rising edge start and the one edge enable. ctc pin input counter internal clock timer register a timer register b 1 m m+1 m m+1 1 n 0 intctc1 interrupt start stop m n ppg2 pin output 1 2 0 n successive initial value ctc pin input counter internal clock timer register a timer register b 1 m m+1 0 n 0 intctc1 interrupt start start m n ppg2 pin output 1 one shot a) successive b) one shot page 83 tmp88ph41ug figure 9-8 two regster both edges trigger start mode timing chart when set to the external trigger rising edge start and the both edges enable. ctc pin input counter internal clock timer register a timer register b 1 m m+1 m 1 n 0 intctc1 interrupt start start stop m n ppg2 pin output 1 0 successive initial value ctc pin input counter internal clock timer register a timer register b 1 m m+1 mn m+1 0 11 n 2 00 0 intctc1 interrupt start m n ppg2 pin output m 1 m+1 0 one shot start start start a) successive b) one shot page 84 9. 16-bit timer (ctc) 9.1 configuration tmp88ph41ug note: in the single-shot mode, the ppg pin output is not toggled at the last register match; it st ays at the value specified wit h ctc1cr2 page 85 tmp88ph41ug detail operation at start that varies depending on how ctc1cr2 page 86 9. 16-bit timer (ctc) 9.1 configuration tmp88ph41ug page 87 tmp88ph41ug 10. 8-bit timercounter 3 (tc3) 10.1 configuration note: function input may not operate depending on i/o port setti ng. for more details, see the chapter "i/o port". figure 10-1 timercounter 3 (tc3) tc3ck tc3s fc/2 13 , fc/2 14 fc/2 12 , fc/2 13 fc/2 11 , fc/2 12 fc/2 10 , fc/2 11 fc/2 9 , fc/2 , fc/2 9 , fc/2 8 3 source clock capture clear tc3s inttc3 interrupt tc3 contorol register 8-bit timer register overflow detect h a b c d e f g s tc3m tc3cr edge detector tc3drb tc3dra capture acap tc3s falling rising a y b s match detect y 8-bit up-counter tc3 pin port (note) cmp fc/2 8 fc/2 7 10 page 88 10. 8-bit timercounter 3 (tc3) 10.1 configuration tmp88ph41ug 10.2 timercounter control the timercounter 3 is controlled by the timercounter 3 control register (tc3cr) and two 8-bit timer registers (tc3dra and tc3drb). note 1: fc: high-frequency clock [hz], * : don?t care note 2: set the operating mode and source clock when timercounter stops (tc3cr page 89 tmp88ph41ug 10.3 function timercounter 3 has three types of operating modes: timer, event counter and capture modes. 10.3.1 timer mode in the timer mode, the up-counter counts up using the internal clock. when a match between the up-counter and the timer register 3a (tc3dra) value is detected, an inttc3 interrupt is generated and the up-counter is cleared. after being cleared , the up-counter restarts counting. setting tc3cr page 90 10. 8-bit timercounter 3 (tc3) 10.1 configuration tmp88ph41ug figure 10-3 timer mode timing chart match detect tc3cr page 91 tmp88ph41ug 10.3.2 event counter mode in the event counter mode, the up-counter counts up at the rising edge of the input pulse to the tc3 pin. when a match between the up-counter and tc3dra value is detected, an inttc3 interrupt is generated and up-counter is cleared. after being cleared, the up-counter restarts counting at each rising edge of the input pulse to the tc3 pin. since a match is detected at the falling edge of the input pulse to tc3 pin, an inttc3 interrupt request is generated at the falling edge im mediately after the up-counter reaches the value set in tc3dra. the maximum applied frequencies are shown in table 10 -2. the pulse width larger than one machine cycle is required for high-going and low-going pulses. setting tc3cr page 92 10. 8-bit timercounter 3 (tc3) 10.1 configuration tmp88ph41ug 10.3.3 capture mode in the capture mode, the pulse width, frequency and du ty cycle of the pulse input to the tc3 pin are mea- sured with the internal clock. the capture mode is used to decode remote control signals, and identify ac50/60 hz. when the falling edge of the tc3 input is detected afte r the timer starts, the up-co unter value is captured into tc3drb. hereafter, whenever the rising edge is detect ed, the up-counter value is captured into tc3dra and the inttc3 interrupt request is generated. the up-counter is cleared at this time. generally, read tc3drb and tc3dra during inttc3 interrupt processing. after the up-counter is cleared, counting is continued and the next up-counter value is captured into tc3drb. when the rising edge is detected immediately after the timer starts, th e up-counter value is captured into tc3dra only, but not into tc3drb. the inttc3 interrupt request is generated. when the read instruction is executed to tc3drb at this time, the va lue at the completion of the last capture (ff im mediately after a reset) is read. the minimum input pulse width must be larger than one cycle width of the source clock programmed in tc3cr page 93 tmp88ph41ug 11. 8-bit timercounter 4 (tc4) 11.1 configuration figure 11-1 timercounter 4 (tc4) pwm output mode clear 3 2 source clock 8-bit up-counter overflow detect toggle clear timer f/f match detect s y 0 1 y s s 1 0 y pdo mode port (note) ::?:?:? (note) a b c d e f g h y s cmp note: function i/o may not operate depending on i/o port setting. for more details, see the chapter "i/o port". tc4cr tc4dr inttc4 interrupt tc4s tc4s tc4s tc4m tc4ck tc4 pin pwm4 / pdo4 / pin fc/2 11 , fc2 12 fc/2 7 , fc2 8 fc/2 5 , fc2 6 fc/2 3 , fc2 4 fc/2 2 , fc2 3 fc/2, fc2 2 fc, fc/2 page 94 11. 8-bit timercounter 4 (tc4) 11.1 configuration tmp88ph41ug 11.2 timercounter control the timercounter 4 is controlled by the timercounter 4 c ontrol register (tc4cr) and timer registers 4 (tc4dr). note 1: fc: high-frequency clock [hz], * : don?t care note 2: to set the timer registers, the following relationship must be satisfied. 1 tc4dr 255 note 3: to start timer operation (tc4cr page 95 tmp88ph41ug 11.3 function timercounter 4 has four types of operating modes: timer, event counter, programmable divider output (pdo), and pulse width modulation (pwm) output modes. 11.3.1 timer mode in the timer mode, the up-counter counts up using the internal clock. when a match between the up-counter and the tc4dr value is detected, an inttc4 interrupt is generated and the up-counter is cleared. after being cleared, the up-counter restarts counting. 11.3.2 event counter mode in the event counter mode, the up-counter counts up at the rising edge of the input pulse to the tc4 pin. when a match between the up-counter and the tc4dr va lue is detected, an inttc4 interrupt is generated and the up-counter is cl eared. after being cleared, the up-counter restarts counting at rising edge of the tc4 pin. since a match is detected at the falling edge of the input pulse to the tc4 pin, the inttc4 interrupt request is generated at the falling edge immediately after the up-counter reaches the value set in tc4dr. the minimum pulse width applied to the tc4 pin are shown in table 11-2. the pulse width larger than two machine cycles is required for high- and low-going pulses. note:the event counter mode can used in the normal and idle modes only. 11.3.3 programmable divi der output (pdo) mode the programmable divider output (pdo) mode is used to generated a pulse with a 50% duty cycle by count- ing with the internal clock. when a match between the up-counter and the tc4dr value is detected, the logic level output from the pdo4 pin is switched to the opposite state and inttc 4 interrupt request is generated. the up-counter is cleared at this time and then counting is continued. when a match between the up-counter and the tc4dr value is detected, the logic level outp ut from the pdo4 pin is switched to the opposite state again and inttc4 interrupt request is generated. the up-counter is cleared at this time, and then counting and pdo are continued. when the timer is stopped, the pdo4 pin is high. ther efore, if the timer is stopped when the pdo4 pin is low, the duty pulse may be shorter than the programmed value. table 11-1 internal source clock for timercounter 4 (example: fc = 20 mhz) tc4ck normal, idle mode dv1ck = 0 dv1ck = 1 resolution [ s] maximum time setting [ms] resolution [ s] maximum time setting [ms] 000 102.4 26.11 204.8 52.22 001 6.4 1.63 12.8 3.28 010 1.6 0.41 3.2 0.82 011 0.4 0.10 0.8 0.20 table 11-2 external source clock for timercounter 4 minimum pulse width normal, idle mode high-going 2 3 /fc low-going 2 3 /fc page 96 11. 8-bit timercounter 4 (tc4) 11.1 configuration tmp88ph41ug figure 11-2 pdo mode timing chart 11.3.4 pulse width modul ation (pwm) output mode the pulse width modulation (pwm) output mode is used to generate the pwm pulse with up to 8 bits of res- olution by an internal clock. when a match between the up-counter and the tc4dr value is detected, the logic level output from the pwm 4 pin becomes low. the up-counter continues counting. when the up-counter overflow occurs, the pwm 4 pin becomes high. the inttc4 interrupt request is generated at this time. when the timer is stopped, the pwm4 pin is high. therefore, if the timer is stopped when the pwm4 pin is low, one pmw cycle may be shor ter than the programmed value. tc4dr is serially connected to th e shift register. if tc4dr is programmed during pwm output, the data set to tc4dr is not shifted until one pwm cycle is complete d. therefore, a pulse can be modulated periodically. for the first time, the data written to tc4dr is shif ted when the timer is started by setting tc4cr page 97 tmp88ph41ug figure 11-3 pwm output mode timing chart (tc4) table 11-3 pwm mode (example: fc = 20 mhz) tc4ck normal, idle mode dv1ck = 0 dv1ck = 1 resolution [ns] cycle [ s] resolution [ns] cycle [ s] 000???? 001???? 010???? 011 400 102.4 800 204.8 100 200 51.2 400 102.4 101 100 25.6 200 51.2 110???? internal clock shift register counter n 0 ? ? 1 n + 1 ff 0 1 n n + 1 ff 01 m pwm cycle match detect mp n n m data shift rewrite data shift match detect match detect data shift n n m rewrite rewrite pwm4 pin inttc4 interrupt request timer f/f tc4dr tc4cr page 98 11. 8-bit timercounter 4 (tc4) 11.1 configuration tmp88ph41ug page 99 tmp88ph41ug 12. motor control circuit (pmd: programmable motor driver) the tmp88ph41ug contains one channel of motor contro l circuits used for sinusoidal waveform output. this motor control circuit can control brushless dc motors or ac motors with or without sensors. with its primary func- tions like those listed below incorporated in hardware, it helps to accomp lish sine wave motor control easily, with the software load significantly reduced. 1. rotor position detect function ? can detect the rotor position, with or without sensors ? can be set to determine the rotor position when detection matched a number of times, to prevent erro- neous detection ? can set a position detection inhibit period immediately after pwm-on 2. independent timer and timer capture functions for motor control ? contains one-channel magnitude comparison time r and two-channel coinci dence comparison timers that operate synchronously for position detection 3. pwm waveform generating function ? generates 12-bit pwm with 100 ns resolution ? can set a frequency of pwm interrupt occurrence ? can set the dead time at pwm-on 4. protective function ? provides overload protective function based on protection signal input 5. emergency stop function in case of failure ? can be made to stop in an emergency by emg input or timer overflow interrupt ? not easily cleared by software runaway 6. auto commutation/auto position detection start function ? comprised of dual-buffers, can activate auto commutation synchronously with position detection or timer ? can set a position detection period using the timer f unction and start auto position detection at the set time 7. electrical angle timer function ? can count 360 degrees of electrical angle with a set period in the range of 0 to 383 ? can output the counted el ectrical angle to the wave form arithmetic circuit 8. waveform arithmetic circuit ? calculate the output duty cycle fro m the sine wave data and voltage data which are read from the ram based on the elect rical angle timer ? output the calculation result to the waveform synthesis circuit page 100 12. motor contro l circuit (pmd: programmable motor driver) tmp88ph41ug 12.1 outline of motor control the following explains the method for controlling a brushless dc motor with sine wave drive. in a brushless dc motor, the rotor windings to which to apply electric current are determined from the rotor?s magnetic pole position, and the current-applied windings are ch anged as the rotor turns. the rotor?s magnetic pole position is determined using a sensor such as a hall ic or by detecting polarity ch ange (zero-cross) points of the induced voltage that devel- ops in the motor windings (sensorless control). for the sens orless case, the induced voltage is detected by applying electric current to two phases and not applying electric current to the remaining other phase. in this two-phase cur- rent on case, there are six current ap plication patterns as shown in table 12-1, which are changed synchronously with the phases of the rotor. in this two-phase current on case, the current on time in each phase is 120 degrees rela- tive to 180 degrees of the induced voltage. note: one of the upper or lower transistors is pwm controlled. for brushless dc motors, the number of revolutions is controlled by an applied voltage, and the voltage applica- tion is controlled by pwm. at this time, the current on wi ndings need to be changed in synchronism with the phases of the voltage induced by revolutions. control timing in cases where the current on wi ndings are changed by means of sensorless control is illustrated in figure 12-4. for thr ee-phase motors, zero-crossing occurs six times during one cycle of the induced voltage (electrical angle 360 degrees), so that the elect rical angle from on e zero-cross point to the next is 60 degrees. assuming that this period comprises one mode, the rotor position can be divided into six modes by zero-cross points. the six current application pa tterns shown above correspond one for one to these six modes. the timing at which the curr ent application patterns are changed (c ommutation) is out of phase by 30 degrees of electrical angle, wi th respect to the position det ection by an induced voltage. mode time is obtained by detecting a zero-cross point at some timing and finding an elapsed time from the preced- ing zero-cross point. because mode time co rresponds to 60 degrees of electrical angle, the following applies for the case illustrated in figure 12-4. 1. current on windings changeover (commutation) timing 30 degrees of electrical angle = mode time/2 2. position detection start timing 45 degrees of electrical angle = mode time 3/4 3. failure determination timing 120 degrees of electrical angle = mode time 2 timings are calculated in this way. the position detection start timing in 2 is needed to prevent erroneous detec- tion of the induced voltage for reasons th at even after current appl ication is turned off, th e current continues flowing due to the motor reactance. control is exercised by calculating the above timings successively for each of the zero-cross points detected six times during 360 degrees of electrical angle and activating commutation, position detection start, and other opera- tions according to that timing. in this way, operations can be synchronized to the phases of the induced voltage of the motor. the timing needed for motor control as in this example can be set freely as desired by using the internal timers of the microcontroller?s pmd unit. also, sine wave control requires controlling the pwm duty cycle for each pulse. co ntrol of pwm duty cycles is accomplished by counting degrees of electrical angle and cal culating the sine wave data and voltage data at the counted degree of electrical angle. table 12-1 current application patterns current application pattern upper transistor lower transistor current on winding uvwxyz mode 0 on off off off on off u v mode 1 on off off off off on u w mode 2 off on off off off on v w mode 3 off on off on off off v u mode 4 off off on on off off w u mode 5 off off on off on off w v page 101 tmp88ph41ug figure 12-1 conceptual di agram of dc motor control figure 12-2 example of sensorle ss dc motor control timing chart ! " # $ % % % &% ' (' %% ) % % & * ' ! " # $ %&'() $&% () '% *% page 102 12. motor contro l circuit (pmd: programmable motor driver) tmp88ph41ug 12.2 configuration of t he motor control circuit the motor control circuit consists of various units. these include a position de tection unit to det ect the zero-cross points of the induced voltage or position sensor signal, a timer unit to generate events at three instances of electrical angle timing, and a three-phase pwm output unit to produ ce three-phase output pwm wave forms. also included are an electrical angle timer unit to count degrees of electrical angle and a waveform arithmetic unit to calculate sinuso- idal waveform output duty cycles. the input/output units ar e configured as shown in the diagram below. when using ports for the pmd function, set the port input/output control register (p3cri) to 0 for the input ports, and for the out- put ports, set the data output latch (p3i) to 1 and then the port input/output control register to 1. other input/output ports can be set in the same way for use of the pmd function. figure 12-3 block diagram of the mo tor control circuit note 1: always use the ldw instruction to set data in the 9, 12 and 16-bit data registers. note 2: the emg circuit initially is enabl ed. for pmd output, fix the emg input port (p36) "h" high level or disable the emg circuit before using for pmd output. note 3: the emg circuit initially is enabled. when using port p3 as input/output io ports, disable emg. note 4: when going to stop mode, be sure to turn all of the pmd functions off before entering stop mode. ! " page 103 tmp88ph41ug 12.3 position detection unit the position detection unit identifies the motor's rotor position from input patterns on the position signal input port. applied to this position signal input port is the volta ge status of the motor windin gs for the case of sensorless dc motors or a hall element signal fo r the case of dc motors with sensors included. the expect ed patterns corre- sponding to specific rotor positions are set in the pmd ou tput register (mdout) beforehand, and when the input position signal and the expected value ma tch as the rotation, a position detec tion interrupt (intpdc) is generated. also, unmatch detection mode is used to detect the direction of motor rotation, where when the stat us of the position detection input port changes from the status in which it was at start of sampling, a position detection interrupt is gen- erated. for three-phase brushless dc motors, there are six patte rns of position signals, one for each mode, as summarized in table 12-2 from the timing chart in figure 12-2. once a predicted position signal pattern is set in the mdout register, a position detection interrupt is generated the moment the position signal input port goes to mode indicated by this expected value. th e position signals at each phase in the di agram are internal signals which cannot be observed from the outside. table 12-2 position signal input patterns position detection mode u phase (pdu) v phase (pdv) w phase (pdw) mode 0 h l h mode 1 h l l mode 2 h h l mode 3 l h l mode 4 l h h mode 5 l l h page 104 12. motor contro l circuit (pmd: programmable motor driver) tmp88ph41ug 12.3.1 configuration of the position detection unit figure 12-4 configuration of the position detection circuit ? the position detection unit is controlled by the position detection control register (pdcra, pdcrb). after the position de tection function is enab led, the unit starts sa mpling the position detec- tion port with timer 2 or in software. for the case of ordinary mode, when the status of the position detection input port matches the expected value of the pmd output register, the unit generates a posi- tion detection interrupt and finishes sampling, waiting for start of the next sampling. ? when unmatch detection mode is selected for position detection, the unit stores the sampled status of the position detection port in memory at the time it started sampling. when the port input status changes from the status in which it was at st art of sampling, an interrupt is generated. ? in unmatch detection mode, the port status at start of sampling can be read (pdcrc ! " # " "$ $ % $$ !& ' % $ ' ' ( ' ) ' ' * ' ) (+ ,-,., ,&, ,/,0 0 1 / & 2, -, ., 3 &, , /, 0 ., 2, - (, , "$ page 105 tmp88ph41ug ? a sampling delay is provided for use in modes where sampling is made while pwm is on or the lower phases are conducting current. it he lps to prevent erroneous detection due to noise that occurs immedi- ately after the transistor turns on, by starting sampling a set time after the pwm signal turned on. ? when detecting position while pwm is on or the lowe r phases are conducting current, a method can be selected whether to recount occurrences of matche d position detection after being compared for each pwm signal on (logical sum of three-phase pwm signals ) (e.g., starting from 0 in each pwm cycle) or counting occurrences of matching continuously ( pd crb page 106 12. motor contro l circuit (pmd: programmable motor driver) tmp88ph41ug figure 12-5 position detect ion sampling timing with the pwmon period selected figure 12-6 detection timing of the position detection position sdreg 6 to 0 sdreg sampling delay set a time for which to stop sampling in orde r to prevent erroneous detection due to noise that occurs immediately after pwm output tu rns on (immediately after the transistor turns on). (figure 12-5) !! "#$ % % $& ' #$ ' #$ #( ' #$ ! " #$ !& ' # () * * * * * ** * (++ % ! ' # ,- % $ ** * * page 107 tmp88ph41ug note: when changing setting, keep the pdcen bit reset to ?0? (disable position detection function). note: read-modify-write instructions, such as a bit manipulatio n instruction, cannot access t he pdcra because it contains a write only bit. position detection circuit registers [addresses (pmd1)] pdcrc (01fa2h) 76543210 ? ? emem smon pdtct (initial value: **00 0000) 5, 4 emem hold result of position detection at pwm edge (detect position detected position) 00: detected in the current pulse 01: detected while pwm off 10: detected in the current pulse 11: detected in the preceding pulse r 3 smon monitor sampling status 0: sampling idle 1: sampling in progress 2 to 0 pdtct hold position signal input sta- tus holds the status of the position signal input during unmatch detection mode. bits 2 to 0 correspond to w, v, and u phases. pdcrb (01fa1h) 76543210 splck splmd pdcmp (initial value: 0000 0000) 7, 6 splck select sampling input clock 00: fc/2 2 [hz] (200 ns at 20 mhz) 01: fc/2 3 (400 ns at 20 mhz) 10: fc/2 4 (800 ns at 20 mhz) 11: fc/2 5 (1.6 s at 20 mhz) r/w 5, 4 splmd sampling mode 00: sample when pwm is on 01: sample regularly 10: sample when lower phases conducting current 11: reserved 3 to 0 pdcmp position detection matched counts 1 to 15 times (counts 0 and 1 are assumed to be one time.) pdcra (01fa0h) 76543210 swstp swstt sptm3 sttm2 pdnum rcen dtmd pdcen (initial value: 0000 0000) 7 swstp stop sampling in software 0: no operation 1: stop sampling w 6 swstt start sampling in software 0: no operation 1: start sampling 5 sptm3 stop sampling using timer 3 0: disable 1: enable r/w 4 sttm2 start sampling using timer 2 0: disable 1: enable 3 pdnum number of position signal input pins 0: compare three pins (pdu/pdv/pdw) 1: compare one pin (pdu) only 2 rcen recount occurrences of match- ing when pwm is on 0: continue counting from previously pwm on 1: recount each time pwm turns on 1 dtmd position detection mode 0: ordinary mode 1: unmatch detection mode 0 pdcen enable/disable position detec- tion function 0: disable 1: enable (sampling starts) page 108 12. motor contro l circuit (pmd: programmable motor driver) tmp88ph41ug note: when changing setting, keep the pdcen bit reset to ?0? (disable position detection function). 12.3.3 outline processing in the position detection unit sdreg (01fa3h) 76543210 ? d6 d5 d4 d3 d2 d1 d0 (initial value: *000 0000) 6 to 0 sdreg sampling delay 2 3 /fc n bits (n = 0 to 6, maximum 50.8 s, resolution of 400 ns at 20 mhz) r/w !" !#$ % & !& "' ( ) * !" page 109 tmp88ph41ug 12.4 timer unit figure 12-7 timer circuit configuration the timer unit has an up counter (mode timer) which is cleared by a position detection interrupt (intpdc). using this counter, it can generate three types of timer interrup ts (inttmr1 to 3). these timer interrupts may be used to produce a commutation trigger, position detection start trigger, etc. also, the mode timer has a capture function which automatically captures register data in synchronism with position detection or overload protection. this cap- ture function allows motor revolutions to be calculated by measuring position detection intervals. ! "# $ "# # % ! !& "# $ # $ &' ( )*+*, * * * - , * * ) . /( 0 0 /( ! ! /( -! /( ! page 110 12. motor contro l circuit (pmd: programmable motor driver) tmp88ph41ug 12.4.1 configuration of the timer unit the timer unit consists mainly of a mode timer, thr ee timer comparator, and mode capture register, and is controlled by timer control regist ers and timer compare registers. ? the mode timer can be reset by a signal from the position detection circuit, timer 3, or overload pro- tective circuit. if the mode timer overflows without being reset, it stops at ffffh and sets an overflow flag in the control register. ? the value of the mode timer during counting can be read by capturing the coun t in software and read- ing the capture register. ? timer 1 and timers 2 and 3 generate an interrup t signal by magnitude comparison and matching com- parison, respectively. therefore, timer 1 can genera te an interrupt signal even when it could not write to the compare register in time a nd the counter value at the time of writing happens to exceed the regis- ter?s set value. ? when any one of timers 1 to 3 interrupts occurs, the next interrupts can be enabled by writing a new value to the respective compare registers (cmp1, cmp2, cmp3). ? when capturing by position detection is enabled, the capture register has the timer value captured in it each time position is detected. in this way, the capture register always holds the latest value. page 111 tmp88ph41ug 12.4.1.1 timer circuit register functions figure 12-8 dbout de bug output diagram mtcrb 7 dbout debug output debug output can be produced by setting this bit to 1. because interrupt signals to the interrupt control circuit are used for each interrupt, hardware debugging without software delays are possible. see the debug output diagram (figure 12-8). output ports: p67 for pmd1. 5 tmof mode timer overflow this bit shows that the timer has overflowed. 3clcp capture mode timer by over- load protection when this bit is set to 1, the timer valu e can be captured using the overload protection signal (cl) as a trigger. 2swcp capture mode timer in soft- ware when this bit is set to 1, the timer value can be captured in software (e.g., by writing to this register). 1 pdccp capture mode timer by posi- tion detection when this bit is set to 1, the timer value can be captured using the position detection sig- nal as a trigger. mtcra 7, 6, 5 tmck select clock select the timer clock. 4rbtm3 reset mode timer from timer 3 when this bit is set to 1, the mode time r is reset by a trigger from timer 3. 3rbcl reset mode timer by over- load protection when this bit is set to 1, the mode timer is re set by the overload protection signal (cl) as a trigger. 2 swres reset mode timer in software when this bit is set to 1, the mode timer is rese t in software (e.g., by writing to this regis- ter) 1rbpdc reset mode timer by position detection when this bit is set to 1, the mode timer is re set by the position detection signal as a trig- ger. 0 tmen enable/disable mode timer the mode timer is started by setting this bit to 1. therefore, timers 1 to 3 must be set with cmp before setting this bit. if this bit is set to 0 after setting cmp, cmp settings become ineffective. mcap mode capture position detection interval can be read out. cmp1 timer 1 (commutation) timers 1 to 3 are enabled while the mode timer is operating. an interrupt can be gener- ated once by setting the corresponding bit in th is register. the interrupt is disable when an interrupt is generated or the timer is reset. to use the timer again, set the register back again even if data is same. cmp2 timer 2 (position detection start) cmp3 timer 3 (overflow) page 112 12. motor contro l circuit (pmd: programmable motor driver) tmp88ph41ug note: read-modify-write instructions, such as a bit manipulation instruction, cannot access the mtcrb because it contains a write-only bit. note 1: when changing mtcra page 113 tmp88ph41ug note: read-modify-write instructions, such as a bit manipula tion instruction, cannot access the mtcrb or mtcra register because these registers contain write-only bits. 12.4.1.2 outline processing in the timer unit cmp3 (01fadh, 01fach) fedcba9876543210 (initial value: 0000 0000 0000 0000) df de dd dc db da d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 cmp1 timer 1 magnitude comparison compare register r/w cmp2 timer 2 matching comparison compare register cmp3 timer 3 matching comparison compare register ! " # # ! # $ $ ! % & % ' ( !() * * * * + * + % ! % ! , page 114 12. motor contro l circuit (pmd: programmable motor driver) tmp88ph41ug 12.5 three-phase pwm output unit the three-phase pwm output unit has the function to generate three-phase pwm waves with any desired pulse width and the commutation function capable of brushless dc motor control. in addition, it has the protective func- tions such as overload prot ection and emergency stop functi ons necessary to protect th e power drive unit, and the dead time adding function which helps to prevent the in-phase upper/lower transistors from getting shorted by simul- taneous turn-on when switched over. for the pwm output pin (u,v,w,x,y,z), set the port register pxdr and pxcr (x = 3) to 1. the pwm output ini- tially is set to be active low, so that if the output need s to be used active high, set up the mdcra register accord- ingly. 12.5.1 configuration of the three-phase pwm output unit the three-phase pwm output unit consists of a pulse width modulation circuit, commutation control circuit, protective circuit (emergency stop and over load), and a dead time control circuit. 12.5.1.1 pulse width modulation circuit (pwm waveform generating unit) this circuit produces three-phase independent pw m waveforms with an equal pwm frequency. for pwm waveform mode, triangular wave modulation or sawtooth wave modulation can be selected by using the pmd control register (mdcra) bit 1. the pwm frequency is set by using the pmd period register (mdprd). the following shows the relationshi p between the value of this register and the pwm counter clock set by the mdcrb register, pwmck. the pmd period register (mdprd) is comprised of dual-buffers, so that cmpu, v, w register is updated with pwm period. when the waveform arithmetic ci rcuit is operating, the pwm wavefo rm output unit r eceives calculation results from the waveform arithmetic circuit and by us ing the results as cmpu, v, w register set value, it outputs independent three-phase pwm waveforms. wh en the waveform calculati on function is enabled by the waveform arithmetic circuit and transfer of calculation results into the cmpu to w registers is enabled (with edcra register bit 2), the cmpu to w registers are disa bled against writing. when the waveform calculation func tion is enabled (with edcra regist er bit 1) and transfer of calcu- lation results into the cmpu, v, w registers is disabled (with edcra register bit 4), the calculation results are transferred to the buffers of cmpu, v, w registers, but not output to the port. read-accessing the cmpu, v, and w registers can read the calculation results of the waveform arith- metic circuit that have been input to a buffer. afte r changing the read calculation result data by software, writing the changed data to the cmpu, v, and w regi sters enables an arbitrar y waveform other than a sinusoidal wave to be output. when the registers are r ead after writing, the values written to the registers are read out if accessed before th e calculation results are transferre d after calculation is finished. triangular wave pwm: mdprd register set value 1 pwm frequency hz ] [ 2p wmck ---------------------------------------------------------------------------------------------- = sawtooth wave pwm: mdprd register set value 1 pwm frequency hz ] [ pwmck ------------------------------------------------------------------------------------ - = page 115 tmp88ph41ug figure 12-9 pwm waveforms the values of the pwm compare registers (cmpu/v/ w) and the carrier wave generated by the pwm counter (mdcnt) are compared for the relative magnitude by the comparator to produce pwm wave- forms. the pwm counter is a 12-bit up/down counter with a 100 ns (at fc = 20 mhz) resolution. for three-phase output control, two methods of generating three-phase pwm waveforms can be set. 1. three-phase independent mode: values are set independently in the three-phase pmd compare registers to produce three-phase independent pwm waveforms. this method may be used to produce sinusoidal or any other desired drive waveforms. 2. three-phase common mode: a valu e is set in only the u-phase pmd compare register to pro- duce three in-phase pwm waveforms using the u ph ase set value. this method may be used for dc motor square wave drive. the three-phase pmd compare regist ers each have a comparison regi ster to comprise a dual-buffer structure. the values of the pmd co mpare registers are loaded into th eir respective comparison registers synchronously with pwm period. page 116 12. motor contro l circuit (pmd: programmable motor driver) tmp88ph41ug 12.5.1.2 commutation control circuit output ports are controlled depending on the conten ts set in the pmd output register (mdout). the contents set in this register are divided into two, one for selecting the synchronizing signal for port output, and one for setting up port output. the synchronizing signal can be selected from timers 1 or 2, position detection signal, or without sync. port output can be synchronized to this synchronizing signal before being further synchronized to the pwm signal sync. the mdout register's synchronizing signal select bit becomes effective immediately after writing. othe r bits are dual-buffered, and are updated by the selected synchronizing signal. example: commutation timing for one timer period with pwm synchronization specified output on six ports can be set to be active high or active low independently of each other by using the mdcra register bits 5 and 4. furthermore, the u, v, and w phases can individu ally be selected between pwm output and h/l output by using the mdout register bits a to 8 and 5 to 0. when pwm output is selected, pwm waveforms are output; when h/l output is selected, a waveform which is fixed high or low is output. the mdout register bits e to c set the expected position sign al value for the position detection circuit. figure 12-10 pulse width modulation circuit inttmr pwm commutation 3 selector/ latch pwm control pwm interrupt intpwm clock selector pmd period register pmd compare register pwm counter pwm control register ? ? 3, 2, 1 7 60 mdcra b to 0 mdprd b to 0 mdcnt 1 to 0 mdcrb b to 0 cmpu b to 0 cmpw b to 0 cmpv buffer w buffer v buffer u selector/ latch three-phase common/ three-phase up/down pwmu pwmv pwmw stop mdcnt pwm synchronizing clock fc/2 page 117 tmp88ph41ug figure 12-11 commutation control circuit figure 12-12 dead time circuit s selector s selector gate control set reset latch 6 3 2 mdout 5, 4, 3, 2, 1, 0 a, 9, 87, 6 ? b ? , ? , ? mdout sync fc/4 pwm synchronizing clock position detection interrupt intpdc timer 1 interrupt inttmr1 timer 2 interrupt inttmr2 pmd output register u x v y w z pwmu pwmv pwmw ! " # $%& ' ( )% * *(*'*+*,*-*. page 118 12. motor contro l circuit (pmd: programmable motor driver) tmp88ph41ug 12.5.2 register functions of the waveform synthesis circuit mdcrb pwmck select pwm counter cloc k select pwm counter clock. mdcra 7 hlfint select half-period interrupt when this bit is set to 1, intpwm is generated every half period (at triangular wave peak and valley) in the case of center pwm output and pint = 00. in other cases, this setting has no meaning. 6 dtymd duty mode select whether to set the duty cycle independent ly for three phases using the cmpu to w registers or in common for all three phases by setting the cmpu register only. 5 polh upper-phase port polarity select the upper-phase output port polarity. make sure the waveform synthesis function (mdcra register bit 0) is idle before selecting this port polarity. 4 poll lower-phase port polarity select the lower-phase output port polarity. make sure the waveform synthesis function (mdcra register bit 0) is idle before selecting this port polarity. 3, 2 pint pwm interrupt frequency select the frequency at which to generate a pwm interrupt from four choices available: every pwm period or once every 2, 4, or 8 pwm periods. when setting of this bit is altered while operating, an interrupt may be generated at the time the bit is altered. 1 pwmmd pwm mode select pwm mode. pwm mode 0 is an edge pwm (sawtooth wave), and pwm mode 1 is a center pwm (triangular wave). 0pwmen enable/disable waveform generation circuit when enabling this circuit (for waveform output), be sure to set the output port polarity and other bits of this register (other than mdcra bit 0) beforehand. dtr dtr dead time set the dead time between the upper-phase and lower-phase outputs. mdout f updwn pwm counter flag this bit indicates whether the pwm counter is counting up or down. when edge pwm (sawtooth wave) is selected, it is always set to 0. e, d, c pdexp mode compare register set the data to be compared with the position detection input port. the comparison data is adopted as the expected value simultaneously when port output sync settings made with mdout are reflected in the ports. (this is the expected position detection inpu t value for the output set with mdout next time.) b psync select pw m synchronization select whether or not to synchronize port output to pwm period after being synchronized to the synchronizing signal selected with syncs. if selected to be synchronized to pwm, output is kept waiting for the next pwm after being synchronized with syncs. waveform settings are overwritten if new settings are written to the register during this time, and out- put is generated with those settings. a 9 8 wpwm vpwm upwm control uvw-phase pwm outputs set u, v, and w-phase port outputs. (see the table 12-3) 7, 6 syncs select port output sync signal select the synchronizing signal with which to output uvw-phase settings to ports. the synchronizing signal can be selected from time rs 1 or 2, position detection, or asynchro- nous. select asynchronous when the initial setting, otherwise the above setting isn?t reflected immediately. 5, 4 3, 2 1, 0 woc voc uoc control uvw-phase outputs set u, v, and w-phase port outputs. (see the table 12-3) mdcnt pwm counter this is a 12-bit read-only register used to count pwm periods. mdprd set pwm period this register determines pwm period, and is dual-buffered, allowing pwm period to be altered even while the pwm counter is operating. the buffers are loaded every pwm period. when 100 ns is selected for the pwm counter clock, make sure the least signifi- cant bit is set to 0. page 119 tmp88ph41ug note: when changing setting, keep the pwmen bit reset to ?0? (disable wave form synthesis function). note: when changing setting, keep the mdcr a page 120 12. motor contro l circuit (pmd: programmable motor driver) tmp88ph41ug 12.5.3 port output as se t with uoc/voc/woc bits and upwm/vpwm/wpwm bits mdout (01fb3h, 01fb2h) fedcba98 updwn pdexp psync wpwm vpwm upwm 76543210 syncs woc voc uoc (initial value: 00000000 00000000) f updwn pwm counter flag 0: counting up 1: counting down r e, d, c pdexp comparison register for posi- tion detection bit e: w-phase expected value bit d: v-phase expected value bit c: u-phase expected value r/w b psync select pwm synchronization 0: asynchronous 1: synchronized a wpwm w-phase pwm output 0: h/l level output 1: pwm waveform output 9 vpwm v-phase pwm output 0: h/l level output 1: pwm waveform output 8 upwm u-phase pwm output 0: h/l level output 1: pwm waveform output 7, 6 syncs select port output synchronizing signal 00: asynchronous 01: synchronized to position detection 10: synchronized to timer 1 11: synchronized to timer 2 5, 4 woc control w-phase output see the table 1-3 3, 2 voc control v-phase output 1, 0 uoc control u-phase output table 12-3 example of pin output settings u-phase output polarity: active high (polh,poll = 1) u-phase output polarity: active low (polh,poll = 0) uoc upwm uoc upwm 1: pwm output 0: h/l level output 1: pwm output 0: h/l level output u phase x phase u phase x phas e u phase x phase u phase x phase 0 0 pwm pwm l l 0 0 pwm pwm hh 0 1 l pwm l h 0 1 h pwm hl 1 0 pwm l h l 1 0 pwm hlh 1 1 pwm pwm hh 1 1 pwm pwm l l page 121 tmp88ph41ug mdcnt (01fb5h, 01fb4h) fedcba9876543210 (initial value: ****000000000000) ? ? ? ? db da d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 b to 0 pwm counter pwm period counter value r mdprd (01fb7h, 01fb6h) fedcba9876543210 (initial value: ****000000000000) ? ? ? ? db da d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 b to 0 pwm period pwm period mdprd 010h r/w cmpu (01fb9h, 01fb8h) fedcba9876543210 (initial value: ****000000000000) ? ? ? ? db da d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 cmpv (01fbbh, 01fbah) fedcba9876543210 (initial value: ****000000000000) ? ? ? ? db da d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 cmpw (01fbdh, 01fbch) fedcba9876543210 (initial value: ****000000000000) ? ? ? ? db da d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 b to 0 cmpu pwm compare u register set u-phase duty cycle r/w cmpv pwm compare v register set v-phase duty cycle cmpw pwm compare w register set w-phase duty cycle page 122 12. motor contro l circuit (pmd: programmable motor driver) tmp88ph41ug 12.5.4 protective circuit this circuit consists of an emg prot ective circuit and ov erload protective ci rcuit. these circ uits are activated by driving their respective port inputs active. figure 12-13 configuration of the protective circuit a. emg protective circuit this protective circuit is used for emergency st op, when the emg protec tive circuit is enabled. when the signal on emg input port goes active (negative edge triggered), the six ports are immedi- ately disabled high-impedance against output and an emg interrupt (intemg) is generated. the emg control register (emgcra) is used to set emg protection. if the emgcra page 123 tmp88ph41ug the number of times the overload protective input is sampled can be set by using the emgcra !! " page 124 12. motor contro l circuit (pmd: programmable motor driver) tmp88ph41ug 12.5.5 functions of prot ective circuit registers emgrel emg disable the emg protective circuit is disable from t he disabled state by writing ?5ah? and ?a5h? to this register in that order. after that, the emgcra register needs to be set. emgcrb 7rtcl return from overload protec- tive state when this bit is set to 1, the motor control ci rcuit is returned from overload protective state in software (e.g., by writing to this register). also, the current state can be known by read- ing this bit. mdout outputs at return from the overload protective state remain as set before the overload protective input was driven active. 6 rtpwm return by pwm sync when this bit is set to 1, the motor control ci rcuit is returned from overload protective state by pwm sync. if rtcl is set to 1, rtcl has priority. 5 rttm1 return by timer sync when this bit is set to 1, the motor control ci rcuit is returned from overload protective state by timer 1 sync. if rtcl is set to 1, rtcl has priority. 4 clst overload protective state the status of over load protection can be know n by reading this bit. 3, 2 clmd select output disabled phases during overload pro- tection select the phases to be disabled against out put during overload prot ection. this facility allows selecting to disable no phases, all pha ses, pwm phases, or all upper phases/all lower phases. 1cntst stop counter during overload protection can stop the pwm counter during overload protection. 0clen enable/disable overload pro- tection enable or disable the overload protective function. emgcra 7 to 4 clcnt overload protection sampling time set the length of time the overload protective input port is sampled. 2 emgst emg protective state the status of emg protection can be known by reading this bit. 1rte return from emg protective state the motor control circuit is returned from emg protective state by setting this bit to ?1? . when returning, set the mdout register a to 0 bits to ?0? . then set the emgcra reg- ister bit 1 to ?1? and set mdout waveform output. then set up the mdcra register. 0emgen enable/disable emg protec- tive circuit the emg protective circuit is activated by setting this bit to 1. this circuit initially is enabled. (to disable this circuit, make sure key code 5ah and a5h are written to the emgrel1 register beforehand.) page 125 tmp88ph41ug note: read-modify-write instructions, such as a bit manipulation instruction, cannot access the emgrel register because this register is write only. note: if during overload protection the port output state in two or more upper phases is on, all lo wer phases are disabled and a ll upper phases are enabled for output; when two or more lowe r phases are on, all upper phases are disabled and all lower phases are enabled for output. note 1: an instruction specifying a return from the emg state is invalid if the emg input is ?l?. note 2: read-modify-write instructions, such as a bit manipulation instruction, cannot access the emgcrb or emgcra register because these registers c ontain write-only bits. protective circuit registers [addresses (pmd1)] emgrel (01fbfh) 76543210 d7 d6 d5 d4 d3 d2 d1 d0 (initial value: 0000 0000) 7 to 0 emgrel emg disable can disable by writing 5ah and then a5h. w emgcrb (01fb1h) 765432 1 0 rtcl rtpwm rttm1 clst clmd cntst clen (initial value: 0000 0000) 7rtcl return from overload protec- tive state 0: no operation 1: return from protective state w 6rtpwm enable/disable return from overload protective state by pwm sync 0: disable 1: enable r/w 5 rttm1 enable/disable return from overload protective state by timer 1 0: disable 1: enable 4 clst overload protective state 0: no operation 1: under protection r 3, 2 clmd select output disabled phases during overload protection 00: no phases disabled against output 01: all phases disabled against output 10: pwm phases disabled against output 11: all upper/all lower phases disabled against output (note) r/w 1 cntst stop pwm counter during over- load protection 0: do not stop 1: stop the counter 0clen enable/disable overload pro- tective circuit 0: disable 1: enable emgcra (01fb0h) 765432 1 0 clcnt emgst rte emgen (initial value: 0000 *001) 7 to 4 clcnt overload protection sampling number of times. 2 2 /fc n ( n = 1 to 15, 0 and 1 are set as 1 at 20 mhz ) r/w 2 emgst emg protective state 0: no operation 1: under protection r 1 rte return from emg state 0: no operation 1: return from protective state (note 1) w 0emgen enable/disable emg protective circuit 0: disable 1: enable r/w page 126 12. motor contro l circuit (pmd: programmable motor driver) tmp88ph41ug 12.6 electrical angle timer and waveform arithmetic circuit electrical angle timer figure 12-15 electric al angle timer circuit waveform arithmetic circuit figure 12-16 waveform arithmetic circuit ! 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" # $ & ) *+#*) , - .*) /*) 0*) &'/ &'. &'0 ) 123 3 $ # " ! 04& 5 5% $ # 5( / 5%& #" 6 $ # page 127 tmp88ph41ug 12.6.1 electrical angle timer and waveform arit hmetic circuit the electrical angle timer finishes counting upon reaching the value set by the period set register (edset). the electrical angle timer counts 360 degrees of electrical angle in the range of 0 to 383 (17fh) and is cleared to 0 upon reaching 383. in this way, it is possible to obtain the elect rical angle of the frequency proportional to the value set by the period set register. the period with which to count up can be corrected by using the period correction register, allowing for fine adjustment of the freque ncy. the electrical angles counted by the electrical angle timer are presented to the waveform arithmetic circuit. an electrical angle timer interrupt signal is gene rated each time the electrical a ngle timer finishes counting. the waveform arithmetic circuit has a sine wave data table, which is used to extract sine wave data based on the electrical angle data received fr om the electrical angle timer. this sine wave data is multiplied by the value of the voltage amplitude register. for 2-phase modulation, the product obtained by this multiplication is presented to the waveform synthesis circuit. for 3- phase modulation, waveform data is further calculated based on the product of multiplication and the electrical angle data and the value of the pwm period register. the calculation is performed each time the electrical angle timer finishes counting or when a value is set in the electrical angle regist er, and the calculation results consisting of the u phase, the v phase ( + 120 degrees), and the w phase ( + 240 degrees) are sequentially presented to the pwm waveform output circuit. the sine wave data table is stored in the ram and requires initialization. ? to correct the period, set the number of times ?n? to be corrected in the period correction register (edset register f to c bits). the period is corrected by adding 1 to electrical angle c ounts 16 for ?n? times. for example, when a value 3 is set in the period correction register, the period for 13 times out of electrical angle counts 16 is the value ?mh? set in the period set register, and that for 3 times is ?m + 1h?. (correction is made almost at equal intervals.) ? because the electrical angle count er (eldeg) can be accessed even while the electrical angle timer is operating, the electri cal angles can be corr ected during operation. ? the electrical angle capture ed cap captures the electrical angle value from the electrical angle counter at the time the position is detected. ? when the waveform calculation func tion is enabled, waveform calcu lation is performed each time the electrical angle counter (eldeg) ar e accessed for write or the electri cal angle timer finishes count- ing. ? the calculation is performed in 35 machine cycl e of execution time, or 7 s (at 20 mhz). ? when transfer of calculation result to the cmp registers is enabled (edcra page 128 12. motor contro l circuit (pmd: programmable motor driver) tmp88ph41ug 12.6.1.1 functions of the electrical angle ti mer and waveform arithmetic circuit registers edcrb 3 calcst start calculation by software forcefully start calculation. when this bit is written while the waveform arithmetic circuit is calculating, the calculation is terminated and then newly started. 2 calcbsy calculation flag by reading this bit, the operation status of the waveform arithmetic circuit can be obtained. 1 edcalen enable/disable calculation start synchronized with elec- trical angle select whether to start calculation when the electrical angle timer finishes counting or when a value is set in the electrical angle r egister. when disabled, calculation is only started when calcst is set to 1. 0 edisel electrical angle interrupt set the electrical angle interrupt signal req uest timing to either when the electrical angle timer finishes counting or upon end of calculation. edcra 7 edcnt electrical angle count up/ down set whether the electrical angle timer counts up or down. 6 edrv select v-, w-phase select phase direction of v-phase and w-phase in relation to u-phase. 5, 4 edck select clock select the clock for the electrical angle time r. this setting can be altered even while the electrical angle timer is operating. 3 c2pen switch between 2-phase and 3-phase modulations select the modulation method with wh ich to perform waveform calculation. two-phase modulation data = ramdata (eldeg) amp note: the sign during 3-phase modulati on changes depending on the electrical angle. + for el ectrical angles 0 to 179 degrees (191) ? for electrical angles 180 (192) to 360 (383) degrees 2rwren auto transfer calculation results to cpm registers enable/disable transfer of calculation results by the waveform arithmetic circuit. when the waveform calculation function is enabled while at the same time transfer is enabled, cal- culation results are set as u, v, and w-phas e duty cycles of the pwm generation circuit and are reflected in the ports. 1calcen enable/disable waveform cal- culation function enable/disable the waveform calculation func tion. calculations are performed by the waveform arithmetic circuit by enabling the waveform calculation function. when the waveform calculation function is enabled, the calculated results can be read from the u, v, and w-phase compare registers (cmpu, v, w) of the pwm generation circuit. 0 edten electrical angle timer enable/disable the electrical angle timer. w hen enabled, the electrical angle timer starts counting; when disabled, the electrical angl e timer stops counting and is cleared to 0. edset f to c edth correct electrical angle period correct the period by adding 1 to electrical angl e counts 16 for ?n? times. the timer counts the electrical angle period set value ?m??for (16 ? n) times and counts (m + 1) for ?n? times b to 0 edt electrical angle period set the electrical angle period. eldeg electrical angle read the electrical angle. this register can also be set to initialize or correct the angle while counting. any value greater than 17fh cannot be set. amp set voltage amplitude set the voltage amplitude. the waveform arithmetic circuit multiplies the data set here by the sine wave data read out from the sine wave ram. the amplitude has its upper limit determined by the set value of the mdprd register when performing this multiplication. edcap capture electrical angle capture the value from the electrical angle timer when the position is detected. wfmdr set sine wave data to initialize the entire ram data of the sine wave table, set the addresses at which to set, sequentially from 000h to 17fh, in the eldeg register, and write waveform data to the wfmdr register each time. make sure the waveform arithmetic circuit is disabled when writing this data. three-phase modulation: data moprd 2 ---------------------- - ramdata eldeg () amp 2 -------------------------------------------------------------------- - = page 129 tmp88ph41ug typical settings of sine wave data note: during 3-phase modulation, the sign changes at 180 degrees of electrical angle. figure 12-17 typical sett ings of sine wave data ! " " " " " #$ #% # & & ( ! " " " " " #$ #% # & & ( page 130 12. motor contro l circuit (pmd: programmable motor driver) tmp88ph41ug note: read-modify-write instructions, such as a bit manipulation instruction, cannot access the edcrb register because this reg- ister is write only. note: when changing the edcra page 131 tmp88ph41ug one period of the electrical angle timer, t, is expressed by the equation below. note: read-modify-write instructions, such as a bit manipulation instruction, cannot access the wfmdr register because this register is write only. edset (01fc3h, 01fc2h) fedcba9876543210 (initial value: 00000000 00010000) edth edt f to c edth correct period (n) 0 to 15 times r/w b to 0 edt set period (m) 010h eldeg (01fc5h, 01fc4h) fedcba9876543210 (initial value: *******0 00000000) ???????d8d7d6d5d4d3d2d1d0 8 to 0 eldeg electrical angle set the initially and the count values of electrical angle. r/w amp (01fc7h, 01fc6h) fedcba9876543210 (initial value: ****0000 00000000) ? ? ? ? db da d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 b to 0 amp set voltage set the voltage to be used during waveform calculation. r/w edcap (01fc9h, 01fc8h) fedcba9876543210 (initial value: ******0 00000000) ???????d8d7d6d5d4d3d2d1d0 8 to 0 edcap captured value of electrical angle electrical angle timer val ue when position is detected. r wfmdr (01fcah) 76543210 d7 d6 d5 d4 d3 d2 d1 d0 (initial value: ********) 7 to 0 wfmdr sine wave data write sine wave data to ram of sine wave w tm n 16 ----- - + ?? ?? 384 set clock s [] where m set period, n period correction = = = page 132 12. motor contro l circuit (pmd: programmable motor driver) tmp88ph41ug 12.6.1.2 list of pmd related control registers (1) input/output pins and input/output control registers pmd1 input/output pins (p3, p4) and port input/output control registers (p3cr, p4cr) note: when using these pins as pmd function or input port, set the output latch (p*dr) to 1. example of the pmd pin port setting name address bit r or w description p3dr 00003h 7 r/w overload protection ( cl1 ) 6 r/w emg input ( emg1 ) 5 to 0 r/w u1/v1/w1/x1/y1/z1 outputs. p4dr 00004h 2 to 0 r/w position signal inputs (pdu1, pdv1, pdw1). p3cr 01f89h 7 to 0 r/w p3 port input/output control (can be set bitwise). 0: input mode 1: output mode p4cr 01f8ah 2, 1, 0 r/w p0 port input/output control (can be set bitwise). 0: input mode 1: output mode input/output p3dr p3cr p4dr p4cr cl1 input * 0 ? ? emg1 input * 0 ? ? u1output11?? pdu1 input ? ? * 0 page 133 tmp88ph41ug (2) motor control circu it control registers [address : pmd1] position detection control register (pd cr) and sampling delay register (sdreg) name address bit r or w description pdcrc 01fa2h 5, 4 r detect the position-detected position. 00: within the current pulse 01: when pwm is off 10: within the current pulse 11: within the preceding pulse 3r monitor the sampling status. 0: sampling idle 1: sampling in progress 2 to 0 r holds the status of the position signal input during unmatch detection mode. bits 2, 1, and 0: w, v, and u phases pdcrb 01fa1h 7, 6 r/w select the sampling input clock [hz]. 00: fc/2 2 01: fc/2 3 10: fc/2 4 11: fc/2 5 5, 4 r/w sampling mode. 00: when pwm is on 01: regularly 10: when lower phases are turned on 3 to 0 r/w detection position match counts 1 to 15. pdcra 01fa0h 7w 0: no operation 1: stop sampling in software 6w 0: no operation 1: start sampling in software 5r/w stop sampling using timer 3. 0: disable 1: enable 4r/w start sampling using timer 2. 0: disable 1: enable 3r/w number of position signal input pins. 0: compare three pins (pdu/pdv/pdw) 1: compare one pin (pdu) only 2r/w count occurrences of matching when pwm is on. 0: subsequent to matching counts when pwm previously was on 1: eecount occurrences of matching each time pwm is on 1r/w position detection mode. 0: ordinary mode 1: unmatch detection mode 0r/w enable/disable position detection function. 0: disable 1: enable (sampling starts) sdreg 01fa3h 6 to 0 r/w sampling delay. 2 3 /fc n bits (n = 0 to 6, maximum 50.8 s at 20 mhz). page 134 12. motor contro l circuit (pmd: programmable motor driver) tmp88ph41ug mode timer control register (mtcr), mode ca pture register (mcap), and compare registers (cmp1, cmp2, cmp3) name address bit r or w description mtcrb 01fa5h 7r/w debug output. 0: disable 1: enable (p67 for pmd1) 5r mode timer overflow. 0: no overflow 1: overflowed occurred 3r/w capture mode timer by overload protection. 0: disable 1: enable 2w capture mode timer by software. 0: no operation 1: capture 1r/w capture mode timer by position detection. 0: disable 1: enable mtcra 01fa4h 7, 6, 5 r/w select clock for mode timer [hz]. 000: fc/2 3 (400 ns at 20 mhz) 010: fc/2 4 (800 ns at 20 mhz) 100: fc/2 5 (1.6 s at 20 mhz) 110: fc/2 6 (3.2 s at 20 mhz) 001: fc/2 7 (6.4 s at 20 mhz) 011: reserved 101: reserved 111: reserved 4r/w reset timer by timer 3. 0: disable 1: enable 3r/w reset timer by overload protection. 0: disable 1: enable 2w reset timer by software. 0: no operation 1: reset 1r/w reset timer by position detection. 0: disable 1: enable 0r/w enable/disable mode timer. 0: disable 1: enable (timer starts) mcap 01fa7h, 01fa6h f to 0 r mode capture register. cmp1 01fa9h, 01fa8h f to 0 r/w compare register 1. cmp2 01fabh, 01faah f to 0 r/w compare register 2. cmp3 01fadh, 01fach f to 0 r/w compare register 3. page 135 tmp88ph41ug pmd control register (mdcr), dead time register (dtr), and pmd output register (mdout) name address bit r or w description mdcrb 01fafh 1, 0 r/w select clock for pwm counter. 00: fc/2 (100 ns at 20 mhz) 01: fc/2 2 (200 ns at 20 mhz) 10: fc/2 3 (400 ns at 20 mhz) 11: fc/2 4 (800 ns at 20 mhz) mdcra 01faeh 7r/w select half-period interrupt 0: interrupt every period as specified in pint. 1: interrupt every half-period only pint=00. 6r/w duty mode. 0: u phase in common 1: three phases independent 5r/w upper-phase port polarity. 0: active low 1: active high 4r/w lower-phase port polarity. 0: active low 1: active high 3, 2 r/w select pwm interrupt (trigger). 00: interrupt once every period 01: interrupt once 2 periods 10: interrupt once 4 periods 11: interrupt once 8 periods 1r/w pwm mode. 0: pwm mode0 (edge: sawtooth wave) 1: pwm mode1 (center: triangular wave) 0r/w enable/disable waveform synthesis function. 0: disable 1: enable (waveform output) dtr 01fbeh 5 to 0 r/w set dead time. 2 3 /fc 6bit (maximum 25.2 s at 20 mhz). mdout 01fb3h, 01fb2h fr 0: count up 1: count down e, d, c r/w comparison register for position detection. 6: w 5: v 4: u br/w select pwm synchronization. 0: asynchronous with pwm period 1: synchronized ar/w w-phase pwm output. 0: h/l level output 1: pwm waveform output 9r/w v-phase pwm output. 0: h/l level output 1: pwm waveform output 8r/w u-phase pwm output. 0: h/l level output 1: pwm waveform output 7, 6 r/w select port output synchronizing signal. 00: asynchronous 01: synchronized to position detection 10: synchronized to timer 1 11: synchronized to timer 2 5, 4 r/w control w-phase output 3, 2 r/w control v-phase output 1, 0 r/w control u-phase output page 136 12. motor contro l circuit (pmd: programmable motor driver) tmp88ph41ug pwm counter (mdcnt), pmd period regist er (mdprd), and pm d compare registers (cmpu, cmpv, cmpw) emg disable code register (emgrel) and emg control register (emgcr) name address bit r or w description mdcnt 01fb5h, 01fb4h b to 0 r read the pwm period counter value. mdprd 01fb7h, 01fb6h b to 0 r/w pwm period mdprd 010h. cmpu 01fb9h, 01fb8h b to 0 r/w set u-phase pwm duty cycle. cmpv 01fbbh, 01fbah b to 0 r/w set v-phase pwm duty cycle. cmpw 01fbdh, 01fbch b to 0 r/w set w-phase pwm duty cycle. name address bit r or w description emgrel 01fbfh 7 to 0 w code input for disable emg protection circuit. can be disable by writing 5ah and then a5h. emgcrb 01fb1h 7w return from overload protective state. 0: no operation 1: return from protective state 6r/w condition for returning from overload protective state: synchronized to pwm. 0: disable 1: enable 5r/w enable/disable return from overload protective state by timer 1. 0: disable 1: enable 4r overload protective state. 0: no operation 1: under protection 3, 2 r/w select output disabled phases during overload protection. 00: no phases disabled against output 01: all phases disabled against output 10: pwm phases disabled against output 11: all upper/all lower phases disabled against output 1r/w stop pwm counter (mdcnt) during overload protection. 0: do not stop 1: stop 0r/w enable/disable overload protective circuit. 0: disable 1: enable emgcra 01fb0h 7 to 4 r/w overload protection sampling time. 2 2 /fc n (n = 1 to 15, at 20 mhz) 2r emg protective state. 0: no operation 1: under protection 1w return from emg protective state. 0: no operation 1: return from protective state 0r/w enable/disable fanction of the emg protective circuit. 0: disable 1: enable (this circuit initially is enabled (= 1) . to disable this circuit, make sure key code 5ah and a5h are written to the emgrel1 register before- hand.) page 137 tmp88ph41ug electrical angle control register (edcr), electrical angle peri od register (e dset), electrical angle set register (eldeg), voltage set regist er (amp), and electrical angle capture register (edcap). name address bit r or w description edcrb 01fc1h 3w 0: no operation 1: start calculation 2r 0: waveform arithmetic circuit stopped 1: waveform arithmetic circuit calculatin 1r/w 0: start calculation insync with electrical angle 1: do not calculation insync with electrical angle 0r/w 0: interrupt when the electrical angle timer finishes counting 1: interrupt upon end of calculation edcra 01fc0h 7r/w 0: count up 1: count down 6r/w 0: v = u + 120 , w = u + 240 1: v = u ? 120 , w = u ? 240 5, 4 r/w select clock. 00: fc/2 3 01: fc/2 4 10: fc/2 5 11: fc/2 6 3r/w switch between 2/3-phase modulations. 0: two-phase modulation 1: three-phase modulation 2r/w transfer calculation result to cmp registers. 0: disable 1: enable 1r/w enable/disable waveform calculation function. 0: disable 1: enable 0r/w electrical angle timer. 0: disable 1: enable edset 01fc3h, 01fc2h f to c r/w correct period (n) 0 to 15 times. b to 0 r/w set period (1/m counter) 010h eldeg 01fc5h, 01fc4h 8 to 0 r/w initially set and count values of electrical angle. amp 01fc7h, 01fc6h b to 0 r/w set voltage used during waveform calculation. edcap 01fc9h, 01fc8h 8 to 0 r electrical angle timer value when position is detected. wfmdr 01fcah 7 to 0 w set sine wave data. page 138 12. motor contro l circuit (pmd: programmable motor driver) tmp88ph41ug page 139 tmp88ph41ug 13. asynchronous serial interface (uart) the tmp88ph41ug has a asynchronous se rial interface (uart) . it can connect the peripheral circuits through txd and rxd pin. txd and rxd pin are also used as th e general port. for txd pin, the corresponding general port should be set output mode (set its output control regist er to "1" after its output port latch to "1"). for rxd pin, should be set input mode. this uart and sio can not us e simultaneously because their input/output ports are common. 13.1 configuration figure 13-1 uart (asynch ronous serial interface) counter y a b c s s a b c d y e f g h uart status register uart control register 2 uart control register 1 transmit data buffer receive data buffer fc/13 fc/26 fc/52 fc/104 fc/208 fc/416 fc/96 stop bit parity bit fc/2 6 fc/2 7 fc/2 8 baud rate generator transmit/receive clock 2 4 3 2 2 2 noise rejection circuit m p x transmit control circuit shift register shift register receive control circuit mpx: multiplexer uartcra tdbuf rdbuf inttx intrx uartsr uartcrb rxd txd inttc4 page 140 13. asynchronous serial interface (uart) 13.2 control tmp88ph41ug 13.2 control uart is controlled by the uart c ontrol registers (uartcra, uartcrb). the operating status can be mon- itored using the uart status register (uartsr). note 1: when operations are disabled by setting uartcra page 141 tmp88ph41ug note: when an inttxd is generated, tbep flag is set to "1" automatically. uart status register uartsr (01f91h) 76543210 perr ferr oerr rbfl tend tbep (initial value: 0000 11**) perr parity error flag 0: 1: no parity error parity error read only ferr framing error flag 0: 1: no framing error framing error oerr overrun error flag 0: 1: no overrun error overrun error rbfl receive data buffer full flag 0: 1: receive data buffer empty receive data buffer full tend transmit end flag 0: 1: on transmitting transmit end tbep transmit data buffer empty flag 0: 1: transmit data buffer full (transmit data writing is finished) transmit data buffer empty uart receive data buffer rdbuf (01f93h) 76543210read only (initial value: 0000 0000) uart transmit data buffer tdbuf (01f93h) 76543210write only (initial value: 0000 0000) page 142 13. asynchronous serial interface (uart) 13.3 transfer data format tmp88ph41ug 13.3 transfer data format in uart, an one-bit start bit (low level), stop bit (bit length selectable at high level, by uartcra page 143 tmp88ph41ug 13.4 transfer rate the baud rate of uart is set of uartcra page 144 13. asynchronous serial interface (uart) 13.6 stop bit length tmp88ph41ug 13.6 stop bit length select a transmit stop bit length (1 bit or 2 bits) by uartcra page 145 tmp88ph41ug 13.9 status flag 13.9.1 parity error when parity determined using the receive data bits diff ers from the received parity bit, the parity error flag uartsr page 146 13. asynchronous serial interface (uart) 13.9 status flag tmp88ph41ug figure 13-7 generati on of overrun error note:receive operations are di sabled until the overrun error flag uartsr page 147 tmp88ph41ug figure 13-9 generation of transmit data buffer empty 13.9.6 transmit end flag when data are transmitted and no data is in tdbuf (uartsr page 148 13. asynchronous serial interface (uart) 13.9 status flag tmp88ph41ug page 149 tmp88ph41ug 14. synchronous serial interface (sio) the tmp88ph41ug has a clocked-synchronous 8-bit serial in terface. serial interface has an 8-byte transmit and receive data buffer that can automatically and continuously transfer up to 64 bits of data. serial interface is connected to outside peripherl devices via so, si, sck port. this sio and uart can not use simultaneously because their input/out put ports are common. 14.1 configuration figure 14-1 serial interface sio control / status register serial clock shift clock shift register 3 2 1 0 7 6 5 4 transmit and receive data buffer (8 bytes in dbr) control circuit cpu serial data output serial data input 8-bit transfer 4-bit transfer serial clock i/o buffer control circuit so si sck siocr2 siocr1 siosr intsio interrupt request page 150 14. synchronous serial interface (sio) 14.2 control tmp88ph41ug 14.2 control the serial interface is controlled by sio control registers (s iocr1/siocr2). the serial interface status can be determined by reading sio status register (siosr). the transmit and receive data buffer is controlled by the siocr2 page 151 tmp88ph41ug note 1: the lower 4 bits of each buffer are used during 4-bit tr ansfers. zeros (0) are stored to the upper 4bits when receiving. note 2: transmitting starts at the lowest address. received data are also stored starting from the lowest address to the highest address. ( the first buffer address transmitted is 01f98h ). note 3: the value to be loaded to buf is held after transfer is completed. note 4: siocr2 must be set when the serial interface is stopped (siof = 0). note 5: *: don't care note 6: siocr2 is write-only register, whic h cannot access any of in read-modify-wri te instruction such as bit operate, etc. note 7: t f ; frame time, t d ; data transfer time figure 14-2 fr ame time (t f ) and data transfer time (t d ) note 1: after siocr1 page 152 14. synchronous serial interface (sio) 14.3 serial clock tmp88ph41ug 14.3.1.1 internal clock any of six frequencies can be selected. the serial clock is output to the outside on the sck pin. the sck pin goes high when transfer starts. when data writing (in the transmit mo de) or reading (in the receive mode or the transmit/receive mode) cannot keep up with the serial clock rate, there is a wa it function that automatically stops the serial clock and holds the next shift operation until the read/write processing is completed. note: 1 kbit = 1024 bit (fc = 20 mhz) figure 14-3 automatic wait func tion (at 4-bit transmit mode) 14.3.1.2 external clock an external clock connected to the sck pin is used as the serial clock. in this case, the sck (p43) port should be set to input mode. to ensure shifting, a pulse width of more than 2 4 /fc is required. this pulse is needed for the shift operation to ex ecute certainly. actually, there is necessary processi ng time for inter- rupting, writing, and reading. the minimum pulse is determined by setting the mode and the program. figure 14-4 external clock pulse width table 14-1 serial clock rate normal, idle mode sck clock baud rate 000 fc/2 13 2.44 kbps 001 fc/2 8 78.13 kbps 010 fc/2 7 156.25 kbps 011 fc/2 6 312.50 kbps 100 fc/2 5 625.00 kbps 101 fc/2 4 125.00 kbps 110 - - 111 external external a 1 a 2 b 0 b 1 b 2 b 3 c 0 c 1 a 3 a c b a 0 pin (output) pin (output) written transmit data a utomat i ca ll y wait function sck so t sckl t sckh t sckl , t sckh > 2 4 /fc sck pin (input) page 153 tmp88ph41ug 14.3.2 shift edge the leading edge is used to transmit, a nd the trailing edge is used to receive. 14.3.2.1 leading edge transmitted data are shifted on the leading ed ge of the serial clock (falling edge of the sck pin input/ output). 14.3.2.2 trailing edge received data are shifted on the trailing edge of the serial clock (rising edge of the sck pin input/out- put). figure 14-5 shift edge 14.4 number of bits to transfer either 4-bit or 8-bit serial transfer can be selected. when 4-bit serial transfer is selected, only the lower 4 bits of the transmit/receive data buffer re gister are used. the upper 4 bits are cleared to ?0? when receiving. the data is transferred in sequence star ting at the least significant bit (lsb). 14.5 number of w ords to transfer up to 8 words consisting of 4 bits of data (4-bit serial tran sfer) or 8 bits (8-bit serial tr ansfer) of data can be trans- ferred continuously. the number of words to be transferred can be selected by siocr2 page 154 14. synchronous serial interface (sio) 14.6 transfer mode tmp88ph41ug figure 14-6 number of words to transfer (example: 1word = 4bit) 14.6 transfer mode siocr1 page 155 tmp88ph41ug siocr1 page 156 14. synchronous serial interface (sio) 14.6 transfer mode tmp88ph41ug figure 14-9 transmiiied data ho ld time at end of transfer 14.6.2 4-bit and 8- bit receive modes after setting the control registers to the receive mode , set siocr1 |