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hardware design guide, revision 8 may 11, 2006 tmxl84622 ultramapper ? lite 622/155 mbits/s sonet/sdh x ds3/e3/ds2/ds1/e1 1 introduction the last issue of this data sheet was april 6, 20 06 - revision 7. a change history is included in section 13, change history, on page 68. red change bars have been installed on all text, figures, and tables that were added or changed. all changes to the text are highlighted in red. changes within figures, and the figure title itself, are highlig hted in red, if feasible. f ormat- ting or grammatical changes have not been highlighted. deleted sections , paragraphs, figures, or tables will be specifically mentioned. the documentation package for the tmxl84622 ultramapper lite 622/155 mbits/s sone t/sdh x ds3/e3/ds2/ds1/e1 system chip consists of the following documents: ? the register description and the system design guide. these two documents are available on a password-protected website. ? the ultramapper lite product description and the ultramapper lite hardware design guide (this document). these two documents are available on the public website shown below. if the reader displays this document using acrobat reader ? , clicking on any blue text will brin g the reader to that reference point. to access related documents, including the documents mentione d above, please go to the following public website, or con- tact your agere representative (see the last page of this document). http://www.agere.com/telecom/index.html this document describes the hardware in terfaces of the agere systems tmxl84622 ultramapper lite device. information relevant to the use of the device in a boar d design is covered. pin descriptions, dc electrical characteristics, timing diagram s, ac timing parameters, packaging, and operating conditions are included. figure 1-1. ultramapper lite block diagram and high-level interface definition (x3) m13 mux tmux sts-12/ stm-4/ sts-3/ stm-1 frm (x3) x28/x21 ds1/j1/e1 (x3) x28/x21 vtmpr mrxc ds1/j1/e1 vt/ tu ds2/ e2 ds3/ e3 tpg/tpm x3 x28/x21 ds1/e1 dja cdr spempr (x3) (0-2) cdr mcdr stspp mpu jtag lopoh x6 ds3/e3 dja (x3) e13 mux spempr (x3) (3-5) (x3) s t s - 1 l t 6 3 1 s t s x c system interfaces transport modes 4 ds1/j1/e1 (x30): x28/x21 + prot. 4 ds2/e2 (x30): x21/x12 + prot. 4 vt/tu (x30): x28/x21 + prot. (x6) ds3/e3 (x3) sts-1 (x3) nsmi (x3) sts-1 (total of 3 sts-1 max) low-speed i/o 622 mb/sts-12/stm-4 155 mb/sts-3/stm-1 clock and data lopoh 622/155 mbits/s sonet/sdh adm front end ds3/e3/ds2/ds1/e1 pdh tributary termination toac mpu if poac ds3/e3 pll if (optional) jtag if (x3) (x3) 66 e2, vc12 ds3xclk, e3xclk ds2, vc11 ais clocks ds1xclk, e1xclk power and gnd pins not shown 6 12 49 5 6 sts-3/stm-1 mate interconnect high-speed if (x3) 8 clock/sync 6 protection link 622 mb/sts-12/stm-4 155 mb/sts-3/stm-1 clock and data 8 42 24 180 3 1 1 1 2 2 10/10/02 miscellaneous 24 cg pll if 5
table of contents contents page 2 agere systems inc. hardware design guide, revision 8 may 11, 2006 622/155 mbits/s sonet/sdh x ds3/e3/ds2/ds1/e1 tmxl84622 ultramapper lite 1 introduction ................................................................................................................. .......................................................1 2 pin information .............................................................................................................. .....................................................6 2.1 ball diagram .............................................................................................................. ..................................................6 2.2 package pin assignments ................................................................................................... ........................................7 2.3 pin matrix ................................................................................................................ ...................................................15 2.4 pin types ................................................................................................................. ..................................................17 2.5 pin definitions ........................................................................................................... .................................................18 3 operating conditions and reliability ......................................................................................... .......................................34 3.1 absolute maximum ratings .................................................................................................. .....................................34 3.2 recommended operating conditions ................ .......................................................................... .............................34 3.3 handling precautions ...................................................................................................... ..........................................34 3.4 thermal parameters (definitions and values) . .............................................................................. ............................35 3.5 reliability ............................................................................................................... ....................................................36 3.6 recommended powerup sequence .............................................................................................. ............................36 3.7 power consumption ......................................................................................................... .........................................36 4 electrical characteristics ................................................................................................... ...............................................38 4.1 lvcmos interface specifications ........................................................................................... ..................................38 4.2 lvds interface characteristics ............................................................................................ .....................................39 5 timing ....................................................................................................................... .......................................................40 5.1 tmux high-speed interface ................................................................................................. ....................................40 5.2 thssync characte ristics ........... ................ ................ ................. ................ ............. .......... ......................................41 5.3 sts-3/stm-1 mate interconnect timing ...................................................................................... .............................43 5.4 toac, poac, and lopoh timing .............................................................................................. .............................44 5.5 ds3/e3/sts-1 timing ....................................................................................................... ........................................45 5.6 nsmi timing ............................................................................................................... ...............................................46 5.7 shared low-speed line timing .............................................................................................. ..................................50 6 reference clocks ............................................................................................................. ................................................51 7 microprocessor interface timing .............................................................................................. ........................................56 7.1 synchronous write mode .................................................................................................... ......................................56 7.2 synchronous read mode ..................................................................................................... .....................................58 7.3 asynchronous write mode ................................................................................................... .....................................59 7.4 asynchronous read mode .................................................................................................... ....................................61 8 other timing ................................................................................................................. ...................................................63 9 hardware design file references .............................................................................................. .....................................63 10 700-pin pbgam1t diagrams .................................................................................................... .....................................64 11 device ordering information ................................................................................................. ..........................................66 12 glossary .................................................................................................................... .....................................................67 13 change history .............................................................................................................. .................................................68 13.1 changes to this document since revision 7 ................................................................................ ..........................68 13.2 navigating through an adobe acrobat document ............................................................................. .....................68
table of contents (continued) tables page agere systems inc. 3 hardware design guide, revision 8 tmxl84622 ultramapper lite may 11, 2006 622/155 mbits/s so net/sdh x ds3/e3/ds2/ds1/e1 table 2-1. package pin assignments in signal name order ........................................................................ .........................7 table 2-2. package pin matrix.................................................................................................. ............................................15 table 2-3. pin types ........................................................................................................... ..................................................17 table 2-4. tmux block, high-speed interface i/o ................................................................................ ...............................18 table 2-5. tmux block, protection link i/o ..................................................................................... ....................................18 table 2-6. tmux block, clock and sync i/o ...................................................................................... ..................................19 table 2-7. sts cross connect (stsxc) block, sts-3/stm- 1 mate interconnect ...................................................... ........20 table 2-8. synchronous payl oad envelope (spe) mapper block, external pll control ............................................... ......20 table 2-9. multirate cross connect (mrxc) block, toac input and output channels ................................................ ......21 table 2-10. multirate cross connect (m rxc) block, poac input and output channels ............................................... .....21 table 2-11. ds3/e3/sts-1 out................................................................................................... ..........................................22 table 2-12. ds3/e3/sts-1 in .................................................................................................... ...........................................22 table 2-13. nsmi/sts-1 in...................................................................................................... .............................................23 table 2-14. nsmi/sts-1 out..................................................................................................... ...........................................24 table 2-15. shared low-speed line in ........................................................................................... .....................................24 table 2-16. shared low-speed line out.......................................................................................... ....................................26 table 2-17. low-speed line in (neg ative-rail in dual-rail mode) ................................................................ ......................26 table 2-18. low-speed line out (negative-rail in dual-rail mode)............................................................... .....................27 table 2-19. reference clocks ................................................................................................... ...........................................28 table 2-20. low-order path overhead access, transmit direction ................................................................. ....................29 table 2-21. low-order path overhead access, receive direction.................................................................. ....................29 table 2-22. clock generator.................................................................................................... .............................................29 table 2-23. microprocessor interf ace ........................................................................................... ........................................30 table 2-24. boundary scan (ieee ? 1149.1) ....................................................................................................................... ..31 table 2-25. general-purpose interface .......................................................................................... ......................................31 table 2-26. cdr interface ...................................................................................................... ..............................................31 table 2-27. analog power and ground signals.................................................................................... ................................32 table 2-28. digital power and ground signals....... ............................................................................ ..................................33 table 2-29. no connects ........................................................................................................ ..............................................33 table 3-1. absolute maximum ratings ............................................................................................ .....................................34 table 3-2. recommended operating conditions.................................................................................... ..............................34 table 3-3. esd tolerance....................................................................................................... ..............................................34 table 3-4. thermal parameter values ............................................................................................ ......................................35 table 3-5. reliability data.................................................................................................... .................................................36 table 3-6. moisture sensitivity level .......................................................................................... ..........................................36 table 3-7. typical power consumption by application (50 mhz mpu clock) ......................................................... .............36 table 3-8. typical power consumption per block.. ............................................................................... ...............................37 table 4-1. lvcmos input specifications......................................................................................... .....................................38 table 4-2. lvcmos output specifications ........................................................................................ ...................................38 table 4-3. lvcmos bidirectional specifications ................................................................................. .................................38 table 4-4. lvds interface dc characteristics ................................................................................... ....................................39 table 5-1. high-speed interface input specification............................................................................ .................................40 table 5-2. protection link input specification................................................................................. ......................................40 table 5-3. high-speed interface outputs ........................................................................................ .....................................41 table 5-4. protection link outputs ............................................................................................. ..........................................41 table 5-5. sts-3/stm-1 mate interconnect input specification................................................................... ........................43 table 5-6. sts-3/stm- 1 mate interconnect output specification .................................................................. ......................43 table 5-7. toac, poac, and lopoh input specification........................................................................... ........................44 table 5-8. toac, poac, and lopoh output specification .......................................................................... ......................44 table 5-9. ds3/e3 input specification .......................................................................................... ........................................45 table 5-10. sts-1 input specification .......................................................................................... ........................................45
table of contents (continued) tables page 4 agere systems inc. hardware design guide, revision 8 may 11, 2006 622/155 mbits/s sonet/sdh x ds3/e3/ds2/ds1/e1 tmxl84622 ultramapper lite table 5-11. ds3/e3/sts-1 output specification .... .............................................................................. ................................45 table 5-12. nsmi input specifications.......................................................................................... ........................................49 table 5-13. nsmi output specifications ......................................................................................... ......................................49 table 5-14. shared low-speed line timing input specification ................................................................... .......................50 table 5-15. shared low-speed line timing output specification.................................................................. ......................50 table 6-1. high-speed interface input clocks specifications .................................................................... ...........................51 table 6-2. protection link input clock specifications .......................................................................... .................................51 table 6-3. ds3/e3/sts-1 input clocks specificatio ns ............................................................................ .............................51 table 6-4. ds1/e1 dja input clocks specifications.............................................................................. ...............................51 table 6-5. m13/e13 input clocks specifications................................................................................. ..................................52 table 6-6. ds3/e3 dja input clocks specifications.............................................................................. ...............................52 table 6-7. lopoh input clock specifications .................................................................................... ..................................52 table 6-8. microprocessor interface input clocks specifications ................................................................ .........................52 table 6-9. pll input clock specifications ..................................................................................... ......................................52 table 6-10. high-speed interface output clocks specif ications .................................................................. ........................52 table 6-11. protection link output clocks specifications....................................................................... ..............................52 table 6-12. line timing interface output clocks specifications................................................................. ..........................53 table 6-13. toac output clocks specifications .................................................................................. ................................53 table 6-14. poac output clocks specifications .................................................................................. ................................53 table 6-15. ds3/e3/sts-1 output clocks specifications.......................................................................... ...........................54 table 6-16. lopoh output clock specifications .................................................................................. ...............................54 table 6-17. nsmi output clocks specifications .................................................................................. .................................54 table 6-18. pll output clocks specifications................................................................................... ...................................54 table 6-19. shared low-spee d receive line input/output clocks specifications................................................... ............54 table 6-20. shared low-speed transmit line input/output clocks specifications.................................................. ............55 table 6-21. nsmi input/output clocks specificati ons ............................................................................ ..............................55 table 7-1. microprocessor interface synchronous write cycle specifications..................................................... ................57 table 7-2. microprocessor interface synchronous read cycle specifications...................................................... ...............58 table 7-3. microprocessor interface asynchronous write cycle specifications .................................................... ...............60 table 7-4. microprocessor interface asynchronous read cycle specifications..................................................... ..............62 table 8-1. general-purpose inputs.............................................................................................. .........................................63 table 8-2. miscellaneous output ................................................................................................ ..........................................63 table 8-3. general-purpose output.............................................................................................. ........................................63 table 11-1. device ordering information ............. ........................................................................... ......................................66
table of contents (continued) figures page agere systems inc. 5 hardware design guide, revision 8 may 11, 2006 622/155 mbits/s sonet/s dh x ds3/e3/ds2/ds1/e1 tmxl84622 ultramapper lite figure 1-1. ultramapperlite block di agram and high-level interface definition .................................................. .................1 figure 2-1. ultramapperlite packag e diagram (top view)......................................................................... ...........................6 figure 5-1. tmux lvds signal rise/fall timing... ............................................................................... ...............................40 figure 5-2. tmux lvds clock an d data timing .................................................................................... .............................40 figure 5-3. thssync timing diagram (mpu_master_slave = 1)...................................................................... ..........41 figure 5-4. thssync timing diagram (mpu_master_slave = 0)...................................................................... ..........41 figure 5-5. thssync timing diagram for synchronized vts ........................................................................ ....................42 figure 5-6. relationship between thssync and thsd ............. ................ ............. ............. ............. .......... ......................42 figure 5-7. sts-3/stm-1 mate rise/fall timing .................................................................................. ...............................43 figure 5-8. sts-3/stm-1 mate clock and data timing............................................................................. ..........................43 figure 5-9. toac, poac timing .................................................................................................. .......................................44 figure 5-10. lopoh timing...................................................................................................... ...........................................44 figure 5-11. ds3/e3 interface diagr am in m13/e13 block ......................................................................... .........................45 figure 5-12. nsmi clock and data timing for the sts-1 mode ..................................................................... .....................46 figure 5-13. nsmi clock and data dia gram for spempr nsmi mode.................................................................. .............46 figure 5-14. nsmi clock and data diagram for m13 nsmi mode (nsmi <---> m13 <- --> ds3 external i/o).....................47 figure 5-15. nsmi clock and data diagram for e13 nsmi mode 1 (nsmi <---> e13 <---> e3 external i/o)......................47 figure 5-16. nsmi clock and da ta diagram for e13 nsmi mode 2 (nsmi <- -> e13 <--> spempr <- -> stm-n) .............48 figure 5-17. nsmi clock and data dia gram for framer (frm) nsmi mode ............................................................ ...........49 figure 5-18. shared low-speed line clock and data timing ....................................................................... ......................50 figure 7-1. microprocessor interfac e synchronous write cycle?(mpmode pin = 1).................................................. ......56 figure 7-2. microprocessor interfac e synchronous read cycle?(mpmode pin = 1)................................................... .....58 figure 7-3. microprocessor interfac e asynchronous write cycle?(mpmode pin = 0) ................................................. .....59 figure 7-4. microprocessor interfac e asynchronous read cycle?(mpmode pin = 0).................................................. ....61 figure 10-1. 700-pin pbgam1t physical dimension ... ............................................................................. ..........................64 figure 10-2. bottom view of 700-pin pbgam1t balls location ..................................................................... .....................65
tmxl84622 ultramapper lite hardware design guide, revision 8 622/155 mbits/s sonet/sdh x ds3/ e3/ds2/ds1/e1 may 11, 2006 6 6 agere systems inc. 2 pin information 2.1 ball diagram the tmxl84622 ultramapper lite is housed in a 700-pin plastic ball grid array. figure 2-1 shows the ball assignment viewed from the top of the package. the pins are spaced on a 1.0 mm pitch. figure 2-1. ultramapper lite package diagram (top view) t d h al f k b p m l j ah r c e y n u an g ad v am aj ag ae ac aa w ap ak af ab a 19 30 26 28 24 32 22 20 18 4 6 8 10 12 14 16 2 34 523 25 7 31 29 15 21 3 27 11 17 913 1 33 t d h al f k b p m l j ah r c e y n u an g ad v am aj ag ae ac aa w ap ak af ab a 19 30 26 28 24 32 22 20 18 4 6 810 12 14 16 2 34 523 25 731 29 15 21 3 27 11 17 913 1 33
hardware design guide, revision 8 tmxl84622 ultramapper lite may 11, 2006 622/155 mbits/s so net/sdh x ds3/e3/ds2/ds1/e1 agere systems inc. 7 2.2 package pin assignments table 2-1. package pin assign ments in signal name order signal name pin signal name pin addr[0] e2 chirxdata[18] p34 addr[1] f3 chirxdata[19] r30 addr[2] d1 chirxdata[20] p33 addr[3] h5 chirxdata[21] r29 addr[4] f2 chirxdata[22] n34 addr[5] e1 chirxdata[23] p32 addr[6] g2 chirxdata[24] n33 addr[7] j6 chirxdata[25] p30 addr[8] j5 chirxdata[26] m34 addr[9] f1 chirxdata[27] p29 addr[10] k6 chirxdata[28] m33 addr[11] h3 chirxdata[29] l34 addr[12] h2 chirxdata[30] m32 addr[13] l6 chirxdata[31] n29 addr[14] g1 chirxdata[32] l33 addr[15] j3 chirxdata[33] k34 addr[16] j2 chirxdata[34] l32 addr[17] h1 chirxdata[35] m30 addr[18] l5 chirxdata[36] j34 addr[19] m6 chirxdata[37] k33 addr[20] k2 chirxdata[38] m29 adsn d2 chirxdata[39] l30 aps_intn r2 chirxdata[40] h34 bypass aj15 chirxdata[41] j33 cg_pllclkout al33 chirxdata[42] j32 chirxdata[1] y34 nc y33 chirxdata[2] v29 nc w29 chirxdata[3] w33 nc y32 chirxdata[4] w34 chitxdata[1] aj27 chirxdata[5] v30 chitxdata[2] an31 chirxdata[6] v32 chitxdata[3] ap32 chirxdata[7] v33 chitxdata[4] ak29 chirxdata[8] u33 chitxdata[5] aj29 chirxdata[9] u32 chitxdata[6] aj30 chirxdata[10] u30 chitxdata[7] am34 chirxdata[11] t34 chitxdata[8] ag30 chirxdata[12] t33 chitxdata[9] aj33 chirxdata[13] u29 chitxdata[10] ak34 chirxdata[14] r34 chitxdata[11] ah33 chirxdata[15] r33 chitxdata[12] af29 chirxdata[16] t29 chitxdata[13] af30 chirxdata[17] r32 chitxdata[14] aj34 chitxdata[15] ae29 data[6] m3 chitxdata[16] ag32 data[7] l1
tmxl84622 ultramapper lite hardware design guide, revision 8 622/155 mbits/s sonet/sdh x ds3/ e3/ds2/ds1/e1 may 11, 2006 8 8 agere systems inc. chitxdata[17] ag33 data[8] m2 chitxdata[18] ad29 data[9] p6 chitxdata[19] ah34 data[10] m1 chitxdata[20] af32 data[11] p5 chitxdata[21] af33 data[12] n2 chitxdata[22] ag34 data[13] p3 chitxdata[23] ad30 data[14] n1 chitxdata[24] ac29 data[15] r6 chitxdata[25] ae33 ds1xclk ak20 chitxdata[26] af34 ds2aisclk r1 chitxdata[27] ac30 ds3datainclk[1] u5 chitxdata[28] ad32 ds3datainclk[2] v2 chitxdata[29] ae34 ds3datainclk[3] w1 chitxdata[30] ad33 ds3datainclk[4] w2 chitxdata[31] ab29 ds3datainclk[5] y3 chitxdata[32] ac32 ds3datainclk[6] y5 chitxdata[33] ad34 ds3dataoutclk[1] y6 chitxdata[34] ac33 ds3dataoutclk[2] ac2 chitxdata[35] aa29 ds3dataoutclk[3] ac3 chitxdata[36] ac34 ds3dataoutclk[4] ad3 chitxdata[37] aa30 ds3dataoutclk[5] ag1 chitxdata[38] ab33 ds3dataoutclk[6] ad6 chitxdata[39] aa32 ds3negdatain[1] t1 chitxdata[40] ab34 ds3negdatain[2] u2 chitxdata[41] y29 ds3negdatain[3] v5 chitxdata[42] aa33 ds3negdatain[4] v6 nc y30 ds3negdatain[5] y1 nc aa34 ds3negdatain[6] aa2 clkin_pll aj32 ds3negdataout[1] ab1 csn c1 ds3negdataout[2] aa6 ctaprh ak8 ds3negdataout[3] ad2 ctaprp ak9 ds3negdataout[4] af1 ctapth aj9 ds3negdataout[5] ac6 ctaptl aj13 ds3negdataout[6] af3 data[0] j1 ds3posdatain[1] t2 data[1] m5 ds3posdatain[2] u3 data[2] l3 ds3posdatain[3] v3 data[3] k1 ds3posdatain[4] w6 data[4] l2 ds3posdatain[5] y2 data[5] n6 ds3posdatain[6] aa1 ds3posdataout[1] ab2 linerxclk[19] a8 ds3posdataout[2] aa5 linerxclk[20] c9 ds3posdataout[3] ad1 linerxclk[21] f11 ds3posdataout[4] ae1 linerxclk[22] c8 ds3posdataout[5] ad5 linerxclk[23] a6 ds3posdataout[6] af2 linerxclk[24] f9 table 2-1. package pin assign ments in signal name order (continued) signal name pin signal name pin
hardware design guide, revision 8 tmxl84622 ultramapper lite may 11, 2006 622/155 mbits/s so net/sdh x ds3/e3/ds2/ds1/e1 agere systems inc. 9 ds3rxclkout[1] aa3 linerxclk[25] a5 ds3rxclkout[2] ac1 linerxclk[26] e8 ds3rxclkout[3] ab6 linerxclk[27] c6 ds3rxclkout[4] ac5 linerxclk[28] c5 ds3rxclkout[5] ae2 linerxclk[29] b4 ds3rxclkout[6] ah1 linerxclk[30] e6 ds3xclk a21 linerxdata[1] b19 dsn e3 linerxdata[2] e18 dtn p1 linerxdata[3] b18 e1xclk ap21 linerxdata[4] c17 e2aisclk u6 linerxdata[5] a16 e3xclk f18 linerxdata[6] f17 ecsel am15 linerxdata[7] b15 etoggle aj16 linerxdata[8] c15 exdnup al17 linerxdata[9] e15 hp_intn r3 linerxdata[10] f15 ic3staten ap24 linerxdata[11] c14 iddq am24 linerxdata[12] e14 linerxclk[1] a19 linerxdata[13] f14 linerxclk[2] c18 linerxdata[14] a11 linerxclk[3] b17 linerxdata[15] f13 linerxclk[4] e17 linerxdata[16] a10 linerxclk[5] b16 linerxdata[17] e12 linerxclk[6] a15 linerxdata[18] b10 linerxclk[7] f16 linerxdata[19] e11 linerxclk[8] a14 linerxdata[20] b9 linerxclk[9] b14 linerxdata[21] a7 linerxclk[10] a13 linerxdata[22] b8 linerxclk[11] b13 linerxdata[23] f10 linerxclk[12] a12 linerxdata[24] e9 linerxclk[13] b12 linerxdata[25] b7 linerxclk[14] c12 linerxdata[26] b6 linerxclk[15] b11 linerxdata[27] a4 linerxclk[16] c11 linerxdata[28] b5 linerxclk[17] a9 linerxdata[29] f8 linerxclk[18] f12 linerxdata[30] a3 linetxclk[1] l29 linetxdata[13] b31 linetxclk[2] h32 linetxdata[14] c30 linetxclk[3] f34 linetxdata[15] c29 linetxclk[4] j29 linetxdata[16] e27 linetxclk[5] e34 linetxdata[17] a30 linetxclk[6] h30 linetxdata[18] f26 linetxclk[7] f32 linetxdata[19] a29 linetxclk[8] e32 linetxdata[20] c27 linetxclk[9] d33 linetxdata[21] f24 linetxclk[10] f30 linetxdata[22] c26 table 2-1. package pin assign ments in signal name order (continued) signal name pin signal name pin
tmxl84622 ultramapper lite hardware design guide, revision 8 622/155 mbits/s sonet/sdh x ds3/ e3/ds2/ds1/e1 may 11, 2006 10 10 agere systems inc. linetxclk[11] f29 linetxdata[23] a27 linetxclk[12] a32 linetxdata[24] f23 linetxclk[13] f27 linetxdata[25] a26 linetxclk[14] b30 linetxdata[26] c24 linetxclk[15] a31 linetxdata[27] b24 linetxclk[16] b29 linetxdata[28] c23 linetxclk[17] b28 linetxdata[29] b23 linetxclk[18] e26 linetxdata[30] a23 linetxclk[19] f25 lopohclkin b22 linetxclk[20] b27 lopohclkout f20 linetxclk[21] a28 lopohdatain c21 linetxclk[22] b26 lopohdataout b21 linetxclk[23] e24 lopohvalidin a22 linetxclk[24] b25 lopohvalidout e20 linetxclk[25] e23 losext an21 linetxclk[26] a25 lp_intn t6 linetxclk[27] f22 mode0_pll ag29 linetxclk[28] a24 mode1_pll ak32 linetxclk[29] f21 mode2_pll ak30 linetxclk[30] e21 mpclk f5 linetxdata[1] g34 mpmode f6 linetxdata[2] h33 nsmirxclk[1] ap26 linetxdata[3] k29 nsmirxclk[2] ap27 linetxdata[4] j30 nsmirxclk[3] aj24 linetxdata[5] g33 nsmirxdata[1] ak23 linetxdata[6] f33 nsmirxdata[2] ak24 linetxdata[7] d34 nsmirxdata[3] ap28 linetxdata[8] e33 nsmirxsync[1] an25 linetxdata[9] h29 nsmirxsync[2] an26 linetxdata[10] c34 nsmirxsync[3] an27 linetxdata[11] e30 nsmitxclk[1] ap29 linetxdata[12] e29 nsmitxclk[2] ap30 nsmitxclk[3] am29 rpscp an10 nsmitxdata[1] aj25 rpsdn am9 nsmitxdata[2] an28 rpsdp am8 nsmitxdata[3] ap31 rstn ap22 nsmitxsync[1] ak26 rtoacclk am17 nsmitxsync[2] an29 rtoacdata aj17 nsmitxsync[3] an30 rtoacsync am18 par[0] p2 rwn h6 par[1] r5 rxdataen[1] aj23 phasedetdown[1] ag3 rxdataen[2] am26 phasedetdown[2] ag5 rxdataen[3] am27 phasedetdown[3] af6 scan_en an24 phasedetdown[4] ak1 scanmode ap25 phasedetdown[5] aj1 sck1 am23 table 2-1. package pin assign ments in signal name order (continued) signal name pin signal name pin
hardware design guide, revision 8 tmxl84622 ultramapper lite may 11, 2006 622/155 mbits/s so net/sdh x ds3/e3/ds2/ds1/e1 agere systems inc. 11 phasedetdown[6] aj3 sck2 aj22 phasedetup[1] ag2 tck an22 phasedetup[2] ae6 tdi ak21 phasedetup[3] af5 tdo an23 phasedetup[4] ah2 thscn ap7 phasedetup[5] aj2 thscon ap5 phasedetup[6] al1 thscop ap4 pmrst am21 thscp ap6 ref10 aj6 thsdn an8 ref14 ak6 thsdp an7 reshi ap3 thssync al15 reslo aj8 tlsclk al14 rhscn an5 tlsdatan[1] an14 rhscp an4 tlsdatan[2] an16 rhsdn am6 tlsdatan[3] an18 rhsdp am5 tlsdatap[1] an13 rhsfsyncn aj20 tlsdatap[2] an15 rlsclk ak15 tlsdatap[3] an17 rlsdatan[1] ap14 tms ap23 rlsdatan[2] ap16 tpoacclk an20 rlsdatan[3] ap18 tpoacdata aj19 rlsdatap[1] ap13 tpoacsync am20 rlsdatap[2] ap15 tpscn ap9 rlsdatap[3] ap17 tpscp ap8 rpoacclk an19 tpsdn ap11 rpoacdata aj18 tpsdp ap10 rpoacsync ap20 trst aj21 rpscn an11 tstmode ak17 tstphase aj14 v dd15 p19 tstsftld am14 v dd15 p28 ttoacclk al18 v dd15 r7 ttoacdata ap19 v dd15 r28 ttoacsync ak18 v dd15 t7 txdataen[1] aj26 v dd15 t13 txdataen[2] ak27 v dd15 t14 txdataen[3] am30 v dd15 t21 v dd15 g9 v dd15 t22 v dd15 g10 v dd15 t28 v dd15 g11 v dd15 u13 v dd15 g12 v dd15 u14 v dd15 g13 v dd15 u21 v dd15 g14 v dd15 u22 v dd15 g15 v dd15 v13 v dd15 g16 v dd15 v14 v dd15 g19 v dd15 v21 v dd15 g20 v dd15 v22 table 2-1. package pin assign ments in signal name order (continued) signal name pin signal name pin
tmxl84622 ultramapper lite hardware design guide, revision 8 622/155 mbits/s sonet/sdh x ds3/ e3/ds2/ds1/e1 may 11, 2006 12 12 agere systems inc. v dd15 g21 v dd15 w7 v dd15 g22 v dd15 w13 v dd15 g23 v dd15 w14 v dd15 g24 v dd15 w21 v dd15 g25 v dd15 w22 v dd15 g26 v dd15 w28 v dd15 j7 v dd15 y7 v dd15 j28 v dd15 y28 v dd15 k7 v dd15 aa7 v dd15 k28 v dd15 aa16 v dd15 l7 v dd15 aa17 v dd15 l28 v dd15 aa18 v dd15 m7 v dd15 aa19 v dd15 m28 v dd15 aa28 v dd15 n7 v dd15 ab7 v dd15 n16 v dd15 ab16 v dd15 n17 v dd15 ab17 v dd15 n18 v dd15 ab18 v dd15 n19 v dd15 ab19 v dd15 n28 v dd15 ab28 v dd15 p7 v dd15 ac7 v dd15 p16 v dd15 ac28 v dd15 p17 v dd15 ad7 v dd15 p18 v dd15 ad28 v dd15 ae7 v dd33 e31 v dd15 ae28 v dd33 f4 v dd15 af7 v dd33 g8 v dd15 af28 v dd33 g17 v dd15 ah9 v dd33 g18 v dd15 ah10 v dd33 g27 v dd15 ah11 v dd33 h7 v dd15 ah12 v dd33 h28 v dd15 ah13 v dd33 h31 v dd15 ah14 v dd33 j4 v dd15 ah15 v dd33 l31 v dd15 ah16 v dd33 m4 v dd15 ah19 v dd33 p31 v dd15 ah20 v dd33 r4 v dd15 ah21 v dd33 u7 v dd15 ah22 v dd33 u28 v dd15 ah23 v dd33 u31 v dd15 ah24 v dd33 v4 v dd15 ah25 v dd33 v7 v dd15 ah26 v dd33 v28 v dd15a_cdr1 ak11 v dd33 y31 v dd15a_cdr2 aj10 v dd33 aa4 table 2-1. package pin assign ments in signal name order (continued) signal name pin signal name pin
hardware design guide, revision 8 tmxl84622 ultramapper lite may 11, 2006 622/155 mbits/s so net/sdh x ds3/e3/ds2/ds1/e1 agere systems inc. 13 v dd15a_ds3pll c20 v dd33 ac31 v dd15a_e3pll b20 v dd33 ad4 v dd15a_x4pll ak14 v dd33 af31 v dd33 a2 v dd33 ag4 v dd33 a33 v dd33 ag7 v dd33 b1 v dd33 ag28 v dd33 b3 v dd33 ah8 v dd33 b32 v dd33 ah17 v dd33 b34 v dd33 ah18 v dd33 c2 v dd33 ah27 v dd33 c33 v dd33 aj31 v dd33 d5 v dd33 ak4 v dd33 d8 v dd33 al6 v dd33 d11 v dd33 al9 v dd33 d14 v dd33 al12 v dd33 d17 v dd33 al21 v dd33 d20 v dd33 al24 v dd33 d23 v dd33 al27 v dd33 d26 v dd33 al30 v dd33 d29 v dd33 am2 v dd33 am33 v ss t16 v dd33 an1 v ss t17 v dd33 an3 v ss t18 v dd33 an32 v ss t19 v dd33 an34 v ss u1 v dd33 ap2 v ss u4 v dd33 ap33 v ss u16 v dd33a_sfpll ak33 v ss u17 v ss a1 v ss u18 v ss a17 v ss u19 v ss a18 v ss u34 v ss a34 v ss v1 v ss b2 v ss v16 v ss b33 v ss v17 v ss c3 v ss v18 v ss c32 v ss v19 v ss d6 v ss v31 v ss d9 v ss v34 v ss d12 v ss w16 v ss d15 v ss w17 v ss d18 v ss w18 v ss d21 v ss w19 v ss d24 v ss y4 v ss d27 v ss aa13 v ss d30 v ss aa14 v ss e4 v ss aa21 table 2-1. package pin assign ments in signal name order (continued) signal name pin signal name pin
tmxl84622 ultramapper lite hardware design guide, revision 8 622/155 mbits/s sonet/sdh x ds3/ e3/ds2/ds1/e1 may 11, 2006 14 14 agere systems inc. v ss e5 v ss aa22 v ss f31 v ss aa31 v ss h4 v ss ab13 v ss j31 v ss ab14 v ss l4 v ss ab21 v ss m31 v ss ab22 v ss n13 v ss ac4 v ss n14 v ss ad31 v ss n21 v ss af4 v ss n22 v ss ag6 v ss p4 v ss ag31 v ss p13 v ss aj4 v ss p14 v ss aj5 v ss p21 v ss ak2 v ss p22 v ss ak3 v ss r31 v ss ak5 v ss ak31 v ss an2 v ss al2 v ss an6 v ss al5 v ss an9 v ss al8 v ss an12 v ss al11 v ss an33 v ss al20 v ss ap1 v ss al23 v ss ap12 v ss al26 v ss ap34 v ss al29 v ssa_cdr1 ak12 v ss am1 v ssa_cdr2 aj12 v ss am3 v ssa_ds3pll f19 v ss am11 v ssa_e3pll a20 v ss am12 v ssa_sfpll al34 v ss am32 v ssa_x4pll aj11 table 2-1. package pin assign ments in signal name order (continued) signal name pin signal name pin
hardware design guide, revision 8 may 11, 2006 tmxl84622 ultramapper lite 622/155 mbits/s sonet/s dh x ds3/e3/ds2/ds1/e1 agere systems inc. 15 2.3 pin matrix table 2-2. package pin matrix pin number 12 34 5 6 7891011121314151617 a v ss v dd33 linerxdata [30] linerxdata [27] linerxclk [25] linerxclk [23] linerxdata [21] linerxclk [19] linerxclk [17] linerxdata [16] linerxdata [14] linerxclk [12] linerxclk [10] linerxclk [8] linerxclk [6] linerxdata [5] v ss b v dd33 v ss v dd33 linerxclk [29] linerxdata [28] linerxdata [26] linerxdata [25] linerxdata [22] linerxdata [20] linerxdata [18] linerxclk [15] linerxclk [13] linerxclk [11] linerxclk [9] linerxdata [7] linerxclk [5] linerxclk [3] c csn v dd33 v ss ? linerxclk [28] linerxclk [27] ? linerxclk [22] linerxclk [20] ? linerxclk [16] linerxclk [14] ? linerxdata [11] linerxdata [8] ? linerxdata [4] d addr[2] adsn ? ? v dd33 v ss ?v dd33 v ss ?v dd33 v ss ?v dd33 v ss ?v dd33 e addr[5] addr[0] dsn v ss v ss linerxclk [30] ? linerxclk [26] linerxdata [24] ? linerxdata [19] linerxdata [17] ? linerxdata [12] linerxdata [9] ? linerxclk [4] f addr[9] addr[4] addr[1] v dd33 mpclk mpmode ? linerxdata [29] linerxclk [24] linerxdata [23] linerxclk [21] linerxclk [18] linerxdata [15] linerxdata [13] linerxdata [10] linerxclk [7] linerxdata [6] g addr[14] addr[6] ? ? ? ? ? v dd33 v dd15 v dd15 v dd15 v dd15 v dd15 v dd15 v dd15 v dd15 v dd33 h addr[17] addr[12] addr[11] v ss addr[3] rwn v dd33 ?????????? j data[0] addr[16] addr[15] v dd33 addr[8] addr[7] v dd15 ?????????? k data[3] addr[20] ? ? ? addr[10] v dd15 ?????????? l data[7] data[4] data[2] v ss addr[18] addr[13] v dd15 ?????????? m data[10] data[8] data[6] v dd33 data[1] addr[19] v dd15 ?????????? n data[14] data[12] ? ? ? data[5] v dd15 ?????v ss v ss v dd15 v dd15 p dtn par[0] data[13] v ss data[11] data[9] v dd15 ?????v ss v ss v dd15 v dd15 r ds2aisclk aps_intn hp_intn v dd33 par[1] data[15] v dd15 ?????????? t ds3negdatain [1] ds3posdatain [1] ?? ? lp_intnv dd15 ?????v dd15 v dd15 ?v ss v ss u v ss ds3negdatain [2] ds3posdatain [2] v ss ds3datainclk [1] e2aisclk v dd33 ?????v dd15 v dd15 ?v ss v ss v v ss ds3datainclk [2] ds3posdatain [3] v dd33 ds3negdatain [3] ds3negdatain [4] v dd33 ?????v dd15 v dd15 ?v ss v ss w ds3datainclk [3] ds3datainclk [4] ?? ? ds3posdatain [4] v dd15 ?????v dd15 v dd15 ?v ss v ss y ds3negdatain [5] ds3posdatain [5] ds3datainclk [5] v ss ds3datainclk [6] ds3dataoutclk [1] v dd15 ?????????? aa ds3posdatain [6] ds3negdatain [6] ds3rxclkout [1] v dd33 ds3posdataout [2] ds3negdataout [2] v dd15 ?????v ss v ss ?v dd15 v dd15 ab ds3negdataout [1] ds3posdataout [1] ?? ? ds3rxclkout [3] v dd15 ?????v ss v ss ?v dd15 v dd15 ac ds3rxclkout [2] ds3dataoutclk [2] ds3dataoutclk [3] v ss ds3rxclkout [4] ds3negdataout [5] v dd15 ?????????? ad ds3posdataout [3] ds3negdataout [3] ds3dataoutclk [4] v dd33 ds3posdataout [5] ds3dataoutclk [6] v dd15 ?????????? ae ds3posdataout [4] ds3rxclkout [5] ?? ? phasedetup [2] v dd15 ?????????? af ds3negdataout [4] ds3posdataout [6] ds3negdataout [6] v ss phasedetup [3] phasedetdown [3] v dd15 ?????????? ag ds3dataoutclk [5] phasedetup [1] phasedetdown [1] v dd33 phasedetdown [2] v ss v dd33 ?????????? ah ds3rxclkout [6] phasedetup [4] ?? ? ? ?v dd33 v dd15 v dd15 v dd15 v dd15 v dd15 v dd15 v dd15 v dd15 v dd33 aj phasedetdown [5] phasedetup [5] phasedetdown [6] v ss v ss ref10 ? reslo ctapth v dd15a_cdr2 v ssa_x4pll v ssa_cdr2 ctaptl tstphase bypass etoggle rtoacdata ak phasedetdown [4] v ss v ss v dd33 v ss ref14 ? ctaprh ctaprp ? v dd15a_cdr1 v ssa_cdr1 ?v dd15a_x4pll rlsclk ? tstmode al phasedetup [6] v ss ??v ss v dd33 ?v ss v dd33 ?v ss v dd33 ? tlsclk thssync ? exdnup am v ss v dd33 v ss ? rhsdp rhsdn ? rpsdp rpsdn ? v ss v ss ? tstsftld ecsel ? rtoacclk an v dd33 v ss v dd33 rhscp rhscn v ss thsdp thsdn v ss rpscp rpscn v ss tlsdatap[1] tlsdatan[1] tlsdatap[2] tlsdatan[2] tlsdatap[3] ap v ss v dd33 reshi thscop thscon thscp thscn tpscp tpscn tpsdp tpsdn v ss rlsdatap[1] rlsdatan[1] rlsdatap[2] rlsdatan[2] rlsdatap[3]
tmxl84622 ultramapper lite 622/155 mbits/s sonet/sdh x ds3/e3/ds2/ds1/e1 hardware design guide, revision 8 may 11, 2006 16 agere systems inc. 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 a v ss linerxclk [1] v ssa_e3pll ds3xclk lopohvalidin linetxdata [30] linetxclk [28] linetxclk [26] linetxdata [25] linetxdata [23] linetxclk [21] linetxdata [19] linetxdata [17] linetxclk [15] linetxclk [12] v dd33 v ss b linerxdata [3] linerxdata [1] v dd15a_e3pll lopo- hdataout lopohclkin linetxdata [29] linetxdata [27] linetxclk [24] linetxclk [22] linetxclk [20] linetxclk [17] linetxlck [16] linetxclk [14] linetxdata [13] v dd33 v ss v dd33 c linerxclk [2] ?v dd15a_ds3pll lopo- hdatain ? linetxdata [28] linetxdata [26] ? linetxdata [22] linetxdata [20] ? linetxdata [15] linetxdata [14] ?v ss v dd33 linetxdata [10] d v ss ?v dd33 v ss ?v dd33 v ss ?v dd33 v ss ?v dd33 v ss ?? linetxclk [9] linetxdata [7] e linerxdata [2] ?lopohvalidout linetxclk [30] ? linetxclk [25] linetxclk [23] ? linetxclk [18] linetxdata [16] ? linetxdata [12] linetxdata [11] v dd33 linetxclk [8] linetxdata [8] linetxclk [5] f e3xclk v ssa_ds3pll lopohclkout linetxclk [29] linetxclk [27] linetxdata [24] linetxdata [21] linetxclk [19] linetxdata [18] linetxclk [13] ? linetxclk [11] linetxclk [10] v ss linetxclk [7] linetxdata [6] linetxclk [3] g v dd33 v dd15 v dd15 v dd15 v dd15 v dd15 v dd15 v dd15 v dd15 v dd33 ? ? ? ? ? linetxdata[5] linetx- data[1] h ????? ?????v dd33 linetxdata[9] linetxclk[6] v dd33 linetxclk[2] linetxdata[2] chirx- data[40] j ????? ?????v dd15 linetxclk[4] linetx- data[4] v ss chirxdata[42] chirxdata[41] chirx- data[36] k ????? ?????v dd15 linetxdata[3] ? ? ? chirxdata[37] chirx- data[33] l ????? ?????v dd15 linetxclk[1] chirx- data[39] v dd33 chirxdata[34] chirxdata[32] chirx- data[29] m ????? ?????v dd15 chirxdata[38] chirx- data[35] v ss chirxdata[30] chirxdata[28] chirx- data[26] n v dd15 v dd15 ?v ss v ss ?????v dd15 chirxdata[31] ? ? ? chirxdata[24] chirx- data[22] p v dd15 v dd15 ?v ss v ss ?????v dd15 chirxdata[27] chirx- data[25] v dd33 chirxdata[23] chirxdata[20] chirx- data[18] r ????? ?????v dd15 chirxdata[21] chirx- data[19] v ss chirxdata[17] chirxdata[15] chirx- data[14] t v ss v ss ?v dd15 v dd15 ?????v dd15 chirxdata[16] ? ? ? chirxdata[12] chirx- data[11] u v ss v ss ?v dd15 v dd15 ?????v dd33 chirxdata[13] chirx- data[10] v dd33 chirxdata[9] chirxdata[8] v ss v v ss v ss ?v dd15 v dd15 ?????v dd33 chirxdata[2] chirxdata[5] v ss chirxdata[6] chirxdata[7] v ss w v ss v ss ?v dd15 v dd15 ?????v dd15 nc ? ? ? chirxdata[3] chirxdata[4] y ????? ?????v dd15 chitxdata[41] nc v dd33 nc nc chirxdata[1] aa v dd15 v dd15 ?v ss v ss ?????v dd15 chitxdata[35] chitx- data[37] v ss chitxdata[39] chitxdata[42] nc ab v dd15 v dd15 ?v ss v ss ?????v dd15 chitxdata[31] ? ? ? chitxdata[38] chitx- data[40] ac ????? ?????v dd15 chitxdata[24] chitx- data[27] v dd33 chitxdata[32] chitxdata[34] chitx- data[36] ad ????? ?????v dd15 chitxdata[18] chitx- data[23] v ss chitxdata[28] chitxdata[30] chitx- data[33] ae ????? ?????v dd15 chitxdata[15] ? ? ? chitxdata[25] chitx- data[29] af ????? ?????v dd15 chitxdata[12] chitx- data[13] v dd33 chitxdata[20] chitxdata[21] chitx- data[26] ag ????? ?????v dd33 mode0_pll chitxdata[8] v ss chitxdata[16] chitxdata[17] chitx- data[22] ah v dd33 v dd15 v dd15 v dd15 v dd15 v dd15 v dd15 v dd15 v dd15 v dd33 ? ? ? ? ? chitxdata[11] chitx- data[19] aj rpoacdata tpoacdata rhsfsyncn trst sck2 rxdataen[1] nsmirx- clk[3] nsmitxdata[1] txdataen[1] chitxdata[1] ? chitxdata[5] chitxdata[6] v dd33 clkin_pll chitxdata[9] chitx- data[14] ak ttoacsync ? ds1xclk tdi ? nsmirxdata[1] nsmirx- data[2] ? nsmitxsync[1] txdataen[2] ? chitxdata[4] mode2_pll v ss mode1_pll v dd33a_sfpll chitx- data[10] al ttoacclk ? v ss v dd33 ?v ss v dd33 ?v ss v dd33 ?v ss v dd33 ? ? cg_pllclkout v ssa_sfpll am rtoacsync ? tpoacsync pmrst ? sck1 iddq ? rxdataen[ 2] rxdataen[3] ? nsmitxclk[3] txdataen[3] ? v ss v dd33 chitxdata[7] an tlsdatan [3] rpoacclk tpoacclk losext tck tdo scan_en nsmirxsync [1] nsmirxsync [2] nsmirxsync [3] nsmitxdata [2] nsmitxsync [2] nsmitxsync [3] chitxdata[2] v dd33 v ss v dd33 ap rlsdatan [3] ttoacdata rpoacsync e1xclk rstn tms ic3staten scanmode nsmirxclk[1] nsmir xclk[2] nsmirdata[3] nsmitxclk[1] nsmitxclk[2] nsmitxdata[3] chitxd ata[3] v dd33 v ss table 2-2. package pin matrix (continued) pin number
hardware design guide, revision 8 tmxl84622 ultramapper lite may 11, 2006 622/155 mbits/s so net/sdh x ds3/e3/ds2/ds1/e1 agere systems inc. 17 2.4 pin types table 2-3 describes each type of input, output, and i/o pin used on the ultramapper lite. table 2-3. pin types type label description i lvcmos input, lvttl switching thresholds. i pd lvcmos input, lvttl switching thresholds with internal 50 k ? pull-down resistor. i pu lvcmos input, lvttl switching thresholds with internal 50 k ? pull-up resistor. o lvcmos output. o od open-drain output. l in lvds inputs. l out lvds outputs. i/o bidirectional pin. lvcmos input with lvttl switchin g thresholds and lvcmos output. i/o pd bidirectional pin. lvcmos input with lvttl switchi ng thresholds with internal 50 k ? pull-down resis- tor and lvcmos output. ? power and ground, analog inputs for external re sistors, capacitors, voltage references, etc. nc no connect.
tmxl84622 ultramapper lite hardware design guide, revision 8 622/155 mbits/s sonet/sdh x ds3/ e3/ds2/ds1/e1 may 11, 2006 18 18 agere systems inc. 2.5 pin definitions this section describes the function of each of the de vice pins. all lvds input buffers have a built-in 100 ? terminating resistor with center tap pin available for external capacitor connection. all unused lvds inputs may be left unconnected. pin functionality is descriptive information. the actual fu nctionality is dependent upon the device configuration via the registers. table 2-4. tmux block, high-speed interface i/o pin symbol type name/description am5 rhsdp l in receive high-speed data. 622/155 mbits/s input data. also, input to internal clock and data recovery (cdr). cdr may be bypassed in 155 mbi ts/s mode. in 622 mbits/s mode, the internal cdr must be used. am6 rhsdn an4 rhscp l in receive high-speed clock. 155 mhz input clock for 155 mbits/s data if cdr is bypassed. not used in 622 mbits/s mode. an5 rhscn ak8 ctaprh ? center tap rh. lvds buffer terminator center tap for rhsdp/n and rhscp/n. an optional 0.1 f capacitor, connected between ctap pin and ground, will improve the common-mode re- jection of the lvds input buffers. an21 losext i pu external loss of signal input . active level is programmable by register tmux_losext_level. default to active-low. this pin can be pa rt of the high-p riority in terrupt when active. usually connected to optical transceiver to indicate loss of signal. an7 thsdp l out transmit high-speed data. 622/155 mbits/s output data. the frame location in slave mode is determined by thssync and tr ansmit high-speed cont rol parameter register (tmux_tframeoffseta). in master mode, the frame timing is arbitrary. an8 thsdn ap4 thscop l out transmit high-speed clock output. 622/155 mhz transmit output clock associated with thsdp/n. ap5 thscon ap3, aj8 reshi , reslo ? resistor. a 100 ? , 1% resistor is required between reshi and reslo pins as a reference for the lvds input buffer termination. aj6 ref10* * optional: selected by mpu/top-level register umpr_lvds_ref_sel. external reference voltage can be sourced from a low-impedan ce resistor (less than 1 k ? ) divider circuit decoupled with a 0.1 f capacitor. please refer to table 4-4, lvds interface dc characteristics, on page 39 for addi- tional information. i reference 1.0 v. external 1 v reference voltage pin (optional). ak6 ref14 * i reference 1.4 v. external 1.4 v reference voltage pin (optional). table 2-5. tmux block, protection link i/o pin symbol type name/description am8 rpsdp l in receive protection high-speed data. 622/155 mbits/s protection input data. also input to in- ternal protection cdr. cdr may be bypassed in 155 mbits/s mode. in 622 mbits/s mode, the internal cdr must be used. am9 rpsdn an10 rpscp l in receive protection high-speed clock. 155 mhz input clock for 155 mbits/s data if protection cdr is bypassed. not used in 622 mbits/s mode. an11 rpscn ak9 ctaprp ? center tap rp. lvds buffer terminator center tap for rpsdp/n and rpscp/n. an optional 0.1 f capacitor, connected between ctap pi n and ground, will improv e the common-mode re- jection of the lvds input buffers. ap10 tpsdp l out transmit protection high-speed data. 622/155 mbits/s protec tion output data. ap11 tpsdn ap8 tpscp l out transmit protection high-speed clock. 622/155 mhz transmit output clock associated with tpsdp/n. ap9 tpscn
hardware design guide, revision 8 tmxl84622 ultramapper lite may 11, 2006 622/155 mbits/s so net/sdh x ds3/e3/ds2/ds1/e1 agere systems inc. 19 table 2-6. tmux block, clock and sync i/o pin symbol type name/description ap6 thscp l in transmit high-speed clock. 622/155 mhz input clock for the transmit 622/155 mbits/s data. also used as a reference clock for a ll cdrs. there are five cdr circuits. the high- speed data and protection high-speed data have cdrs that operate at 155 mhz or 622 mhz. the mate inputs have three cdrs that operate at 155 mhz. the clock on this pin is also internally routed to the ds1/e1 fram ers and is used as an internal master clock. note: a 622 mhz clock must be supplied when the device operates in 622 mbits/s mode. a 155 mhz clock must be supplied when the de vice operates in 155 mbits/s mode. for version 3.0 devices and later, the following applies: a 622 mhz clock must be supplied when the device operates in 622 mbits/s mode. a 155 mhz or 622 mhz clock can be supplied when the device operates in 155 mbits/s mode (choice provisionable via umpr_oc3thsc_mode). ap7 thscn aj9 ctapth ? center tap th. lvds buffer terminator center tap for thscp/n. an optional 0.1 f capaci- tor, connected between ctap pin and ground, will improve the common-mode rejection of the lvds input buffers. aj20 rhsfsyncn o receive high-speed frame sync. this output indicates the start of the frame in the high- speed data input. only present when a valid frame signal is detected on the rhsdp/n inputs. it is an active-low pulse with width almo st equal to one e1 clock period or approxi- mately 500 ns. ak15 rlsclk o receive low-speed clock. 19.44 mhz receive output clock divided down from either rhscp/n or the recovered high-speed clock (when the cdr is used). may be used as a system timing reference. al14 tlsclk o transmit low-speed clock. 19.44 mhz transmit output clock divided down from thscp/n. al15 thssync i/o pd transmit high-speed frame sync. 2 khz/8 khz composite frame sync signal that identi- fies the locations of the j 0 , j 1-1 , j 1-2 , j 1-3 . . . j 1-12 , and v 1-1 bytes. this signal is used to align transmit frames before multiplexing. note: j 0 , j 1-1 , j 1-2 , and j 1-3 . . . j 1-12 occur every 125 s. v 1-1 occurs every 500 s. if the register mpu_master_slave = 1, th ssync is an output; ot herwise, thssync is an input. the positive 8 khz and 2 khz pu lses are synchronized to tl sclk (in master mode only). the rising edge is referenced for frame lo cation. for master/slave configuration, the thssync of all ultramapper lites (up to four) must be connected together. the master can be one of the ultramapper lites, and it sources the frame sync pulse to other ultramapper- lites. all ultramapper lites can also be configured as slaves and receive frame sync from the external system frame sync.
tmxl84622 ultramapper lite hardware design guide, revision 8 622/155 mbits/s sonet/sdh x ds3/ e3/ds2/ds1/e1 may 11, 2006 20 20 agere systems inc. table 2-7. sts cross connect (stsxc) block, sts-3/stm-1 mate interconnect pin symbol type name/description ap17, ap15, ap13 rlsdatap[3:1] l out receive low-speed data. these pins are usually used in 622 mbits/s applications (however, they can be used in a 155 mbits/s application). these pins are used on the device interfacing to the high-speed sts-n/ stm-n line. connect these pins to the high-speed data inputs (rhsdp/n) of the slave devices. this 155 mbits/s signal uses a so net structure. the overheads sup- ported are the a1/a2 and b2 bytes and line rdi. the data is scrambled. data from the rhsd is routed via the stsxc. ap18, ap16, ap14 rlsdatan[3:1] an17, an15, an13 tlsdatap[3:1] l in transmit low-speed data. these pins are usually used in 622 mbits/s ap- plications (however, they can be used in a 155 mbits/s application). these pins are used on the device interf acing to the high-speed sts-n/stm-n line. connect these pins to the high-speed data outputs (thsdp/n) of the slave devices. this 155 mbits/s input receives data from the slave high- speed outputs. these inputs have built-in clock and data recovery (cdr). the frame loca- tion expects a fixed relationship to the high-speed transmit frame sync (thssync). an18, an16, an14 tlsdatan[3:1] aj13 ctaptl ? center tap tl. lvds buffer terminator center tap for tlsdatap/n. an op- tional 0.1 f capacitor, connected between ctap pin and ground, will im- prove the common-mode rejection of the lvds input buffers. table 2-8. synchronous payl oad envelope (spe) mapper bl ock, external pll control pin symbol type name/description al1, aj2, ah2, af5, ae6, ag2 phasedetup[6:1] o phase detector up. signal out to external pll filter and oscillator circuits. used if spempr outputs ds3/e3 data without going through internal ds3/e3dja. if tstmode is high, then these pins are used for tstmux[5:0] (test mode output). for version 3.0 devices and later, these pins are no longer used. therefore, the ds3/e3 dja must be used. phasedetup [6] becomes a transmit chi frame sync output (chitxgfs_o) which is only app licable in chi compression mode. aj3, aj1, ak1, af6, ag5, ag3 phasedetdown[6:1] o phase detector down. signal out to external pl l filter and oscillator cir- cuits. used if spempr outputs ds3/ e3 data without go ing through inter- nal ds3/e3dja. if tstmode is hi gh, phasedetdown[4:1] are used for tstmux[9:6] (test mode output). for version 3.0 devices and later, these pins are no longer used. theref ore, the ds3/e3 dja must be used.
hardware design guide, revision 8 tmxl84622 ultramapper lite may 11, 2006 622/155 mbits/s so net/sdh x ds3/e3/ds2/ds1/e1 agere systems inc. 21 table 2-9. multirate cross connect (mrxc) block, toac input and output channels pin symbol type name/description am17 rtoacclk o receive transport overhead access channel clock. the frequency of this clock is determined by the toac provisioning registers. aj17 rtoacdata o receive transport overhead access channel data. 622/155 mbits/s transport overhead bytes are output on this pin. the content is deter mined by the toac provisioning registers. am18 rtoacsync o receive transport overhead access channel sync. active-high 8 khz frame sync. it is active during the clock period of the first bit of each frame. al18 ttoacclk o transmit transport overhead access channel clock. the frequency of this clock is determined by the toac provisioning registers. ap19 ttoacdata i pd transmit transport overhead access channel data. input for the transport overhead bytes. ak18 ttoacsync o transmit transport overhead access channel sync. active-high 8 khz frame sync. it is active during the clock period of the first bit of each frame. table 2-10. multirate cross connect (mrxc) block, poac input and output channels pin symbol type name/description an19 rpoacclk o receive path overhead access channel clock. output for the path overhead bytes. this is a 3-state output pin controlled by register provisioning. aj18 rpoacdata o receive path overhead access channel data. output for the path overhead bytes. this pin can be 3-stated. ap20 rpoacsync o receive path overhead access channel sync. output for poac channel. active-high during the first bit of each frame when the poac is connected to either the tmux or sts1lt. active-high during the lsb of the last byte of the frame when connected to the spempr. this pin can be individually 3-stated. an20 tpoacclk o transmit path overhead access channel clock. serial access channel clock output for the path overhead bytes. this pin can be individually 3-stated. aj19 tpoacdata i pd transmit path overhead access channel data. serial access channel data input for the path overhead bytes. am20 tpoacsync o transmit path overhead access channel sync. output for poac channel. active-high during the first bit of each frame when the poac is connected to either the tmux, the sts1lt, or the spempr. this pin can be individually 3-stated.
tmxl84622 ultramapper lite hardware design guide, revision 8 622/155 mbits/s sonet/sdh x ds3/ e3/ds2/ds1/e1 may 11, 2006 22 22 agere systems inc. table 2-11. ds3/e3/sts-1 out pin symbol type name/description af2, ad5, ae1, ad1, aa5, ab2 ds3posdataout[6:1] o ds3/e3/sts-1 positive data output. either contains the positive-rail of the b3zs/hdb3 encoded output data, or single-rail nrz data. af3, ac6, af1, ad2, aa6, ab1 ds3negdataout[6:1] o ds3/e3/sts-1 negative data output. negative-rail b3zs/hdb3 encoded output data. not used in single-ra il mode (held low in this case). ad6, ag1, ad3, ac3, ac2, y6 ds3dataoutclk[6:1] i pd ds3/e3/sts-1 data output clock. 44.736 mhz, 34.368 mhz, or 51.84 mhz clock input. this clock is required for m13, e13, or sts1lt applications and is typically connected to an oscillator or a clo cking chip. for ds3/e3 to sonet/sdh mapping applications, this clock is required only if an external clock smoothing pll is used. if the ds3/e3 dja is used, this clock is not re- quired. ds3xclk/e3xclk is needed for ds3/e3 dja in this case. for sts-1 to sonet mapping applications, the tmux can be used to supply the sts-1 rate dataout clock and this clock is therefore not needed. for sts-1 ? pdh applications, a 51.84 mhz clock must be supplied at this pin. ah1, ae2, ac5, ab6, ac1, aa3 ds3rxclkout[6:1] o ds3/e3/sts-1 receive clock output. 44.736 mhz ds3/34.368 mhz e3/51.84 mhz sts-1 clock out to external circuit. table 2-12. ds3/e3/sts-1 in pin symbol type name/description aa1, y2, w6, v3, u3, t2 ds3posdatain[6:1] i pd ds3/e3/sts-1 positive data input. either contains the positive-rail of the b3zs/hdb3 encoded input data, or single-rail nrz data. aa2, y1, v6, v5, u2, t1 ds3negdatain[6:1] i pd ds3/e3/sts-1 negative data input. either contains the negative-rail of the b3zs/hdb3 encoded input data or, in single-rail mode, this input may be used to count bipolar violations. y5, y3, w2, w1, v2, u5 ds3datainclk[6:1] i pd ds3/e3/sts-1 data input clock. 44.736 mhz, 34.368 mhz, or 51.84 mhz clock for the ds3/e3/sts-1 posit ive and negative data inputs.
hardware design guide, revision 8 tmxl84622 ultramapper lite may 11, 2006 622/155 mbits/s so net/sdh x ds3/e3/ds2/ds1/e1 agere systems inc. 23 table 2-13. nsmi/sts-1 in pin symbol type name/description ap28, ak24, ak23 nsmirxdata[3:1] i pd network serial multiplex inte rface (nsmi) receive* data. used in the following applications: ? 51.84 mbits/s serial data input that is used to bring in multiplexed ds1 or e1 channels to frm. ? sts-1 rate clear-channel receive data to spempr. ? ds3/e3 rate clear-channel receive data to m13/e13. additionally, it could be used as a sonet compliant sts-1 input signal to sts1lt from external liu. for v3.0 devices, these pins may also be used for ds3 clear channel (positive-rail or single-rail) input data (to the spempr block). aj24, ap27, ap26 nsmirxclk[3:1] i/o pd nsmi receive clock. used in the following applications: ? input (51.84 mhz) for the ds1/e1 application. ? output (51.84 mhz) for the sts-1 rate clear-channel application. ? output (44.736/34.368 mhz) for the ds3/e3 application. additionally, it could be used as an input clock for sonet compliant sts-1 to sts1lt from external liu. for v3.0 devices, these pins may also be used for ds3 clear channel ds3 rate input clock for positive (and negative) data inputs. an27, an26, an25 nsmirxsync[3:1] i/o pd nsmi receive frame sync. used in the following applications: ? input receive nsmi control for frm. ? output receive control frame sync signal for m13/e13. ? output receive control fram e sync signal for spempr. additionally, it could be used to ca rry sts-1 input transmit clock for sts1lts. for v3.0 devices, these pi ns may also be used for ds3 clear channel negativ e-rail input data (t o the spempr block). am27, am26, aj23 rxdataen[3:1] o nsmi receive data enable. in frm nsmi mode, this pin is not used. in the spempr nsmi mode, the signal on this output will be high during the poh of the spe. in m13 nsmi mode, the signal output on this pin goes low during the m1 byte of the first m1 frame of the ds3 frame. in e13 nsmi mode, the signal output on this pin goes low during the overhead bytes and control bits of the e3 frame. * the transmit path is toward the high-speed fiber output and the receive path is from the high-speed input. low-speed inputs, e .g., nsmirxdata, on the transmit path are labeled receive . low-speed outputs, e.g., nsmitxdata on the receive path are labeled transmit .
tmxl84622 ultramapper lite hardware design guide, revision 8 622/155 mbits/s sonet/sdh x ds3/ e3/ds2/ds1/e1 may 11, 2006 24 24 agere systems inc. table 2-14. nsmi/sts-1 out pin symbol type name/description ap31, an28, aj25 nsmitxdata[3:1] o nsmi transmit* data. nsmi outputs or sts-1 tx data outputs from sts1lts. nsmi output data fr om either the frm, spempr, or m13/e13 block. for v3.0 devices, th ese pins may also be used for ds3 clear channel (positive-rail or single-rail) output data (from the ds3 dja block). am29, ap30, ap29 nsmitxclk[3:1] o nsmi transmit clock output or sts-1 tx clock outputs from sts1lts. output clock at 51.84 mhz for the ds1/e1 application, the (51.84 mhz) sts-1 rate clear-channel application, or a (44.736 mhz/ 34.368 mhz) output clock for the ds 3/e3 application. for v3.0 devices, these pins may also be used for ds3 clear channel ds3 rate output clock (from the ds3 dja block). an30, an29, ak26 nsmitxsync[3:1] o transmit system frame sync output. output transmit control frame sync signal from frm, m13/e13, or spempr. for v3.0 devices, these pins may also be used for ds3 clear channel negative-rail output data (from the ds3 dja block). am30, ak27, aj26 txdataen[3:1] o transmit data enable for nsmi mode. this output is used to request data for a particular link when the frm nsmi is operating in nonloop timing mode. this output acts as a sync signal when the frm nsmi operates in loop-timing mode. in the spempr nsmi mode, the signa l on this output will be high during the poh of the spe. in m13 nsmi mode, the signal output on this pin goes low during the m1 byte of the first m1 frame of the ds3 frame. in e13 nsmi mode, the signal output on this pin goes low during the overhead bytes and control bits of the e3 frame. * the transmit path is toward the high-speed fiber output and the re ceive path is from the high-speed input. low-speed inputs, e .g., nsmirxdata, on the transmit path are labeled receive . low-speed outputs, e. g., nsmitxdata on the receive path are labeled transmit . table 2-15. shared low-speed line in pin symbol type name/description a3, f8, b5, a4, b6, b7, e9, f10, b8, a7, b9, e11, b10, e12, a10, f13, a11, f14, e14, c14, f15, e15, c15, b15, f17, a16, c17, b18, e18, b19 linerxdata[30:1] i pd line receive data [30:1]. inputs to the internal mu ltirate cross connect. they support a variety of transport modes such as ds1, e1, vt, or vc. the signals are used for received single-rail ds1/e1 line data input sourced from an external liu. in this mode, these signals w ill be routed via the cross connect to the vt mapper, the m13 multiplexer, e13 multiplexer, or the re- ceive line inputs of the ds1/e1 framers. these signals may also be used as input data for ds2/e2 applications (see the ultramapper family system de- sign guide ).
hardware design guide, revision 8 tmxl84622 ultramapper lite may 11, 2006 622/155 mbits/s so net/sdh x ds3/e3/ds2/ds1/e1 agere systems inc. 25 the transmit path is toward the high-speed fiber output and the receive path is from the high-speed input. low-speed inputs, e.g., linerxdata, on the transmit path are labeled receive . low-speed outputs, e.g., linetxdata, on the receive path are labeled transmit . e6, b4, c5, c6, e8, a5, f9, a6, c8, f11, c9, a8, f12, a9, c11, b11, c12, b12, a12, b13, a13, b14, a14, f16, a15, b16, e17, b17, c18, a19 linerxclk[30:1] i/o pd line receive clock [30:1]. configurable inputs to the internal multirate cross connect. these inputs are typically used for asynchronous clocks associated with the line receive data inputs from external line interface units or payload termination functions. in certain cases, this input can be used as an output. these pins may be used for ds2/e2 clocks in ds2/e2 ap plications. more in formation will be published in the ultramapper family system design guide . for input specifications, ta b l e 6 - 1 9 applies to these pins. table 2-15. shared low-speed line in (continued) pin symbol type name/description
tmxl84622 ultramapper lite hardware design guide, revision 8 622/155 mbits/s sonet/sdh x ds3/ e3/ds2/ds1/e1 may 11, 2006 26 26 agere systems inc. the transmit path is toward the high-speed fiber output and the receive path is from the high-speed input. low-speed inputs, e.g., chirxdata, on t he transmit path are labeled receive . low-speed outputs, e.g., chitxdata, on the receive path are labeled transmit . the transmit path is toward the high-speed fiber output and the receive path is from the high-speed input. low-speed inputs, e.g., chirxdata, on t he transmit path are labeled receive . low-speed outputs, e.g., chitxdata, on the receive path are labeled transmit . table 2-16. shared low-speed line out pin symbol type name/description a23, b23, c23, b24, c24, a26, f23, a27, c26, f24, c27, a29, f26, a30, e27, c29, c30, b31, e29, e30, c34, h29, e33, d34, f33,g33, j30, k29, h33, g34 linetxdata[30:1] o line transmit data [30:1]. outputs from the internal multirate cross connect. they support a variety of transport mo des such as asynch ronous ds1, e1, and synchronous vt or vc. the signals are used for transmit of single-rail ds1/e1 line data output sourced to an external liu. in this mo de, these signals will be routed via the cross connect from the vt mapper, the m13 multiplexer, e13 multiplexer, or the transmit line outputs of the ds1/e1 framers. each of these outputs comes from the internal mrxc and can be individually set to high impedance. these pins ma y be used for output data in ds2/e2 applications (see the ultramapper family system design guide ). e21, f21, a24, f22, a25, e23, b25, e24, b26, a28, b27, f25, e26, b28, b29, a31, b30, f27, a32, f29, f30, d33, e32, f32, h30, e34, j29, f34, h32, l29 linetxclk[30:1] i/o pd line transmit clock [30:1]. configurable outputs from the internal multirate cross connect. these outputs are typically used for asynchronous clocks associated with the line transmit data outputs to external line interface units or payload termination functions. each of these outputs comes from the internal mrxc and can be individually set to high impedance. in certain cases (ds2/e2 applications), this output is used as an input (input ds2/e2 clocks). more information will be published in the ultramapper family system design guide . for input specifications, ta b l e 6 - 2 0 applies to these pins. table 2-17. low-speed line in (negative-rail in dual-rail mode) pin symbol type name/description j32, j33, h34, l30, m29, k33, j34, m30, l32, k34, l33, n29, m32, l34, m33, p29, m34, p30, n33, p32, n34, r29, p33, r30, p34, r32, t29, r33, r34, u29, t33, t34, u30, u32, u33, v33, v32, v30, w34, w33, v29, y34 chirxdata[42:1] i pd line receive data [42:1]. inputs to the internal multirate cross connect. can be used in one of the following modes: asynchronous mode: in this mode, these inputs are used for ds1/e1 received negative-rail data. may also be used for 8 khz frame synchroniza- tion inputs that indicate the position of the f-bits in the line receive data. vt mapper mode: 8 khz sync for ds1/e1 or 2 khz sync signal for vc. only chirxdata pins [30:1] will ever be used. chirxdata pins [42:31] will not be needed for the applications above and can be left unconnected.
hardware design guide, revision 8 tmxl84622 ultramapper lite may 11, 2006 622/155 mbits/s so net/sdh x ds3/e3/ds2/ds1/e1 agere systems inc. 27 table 2-18. low-speed line out (negative-rail in dual-rail mode) pin symbol type name/description aa33, y29, ab34, aa32, ab33, aa30, ac34, aa29, ac33, ad34, ac32, ab29, ad33, ae34, ad32, ac30, af34, ae33, ac29, ad30, ag34, af33, af32, ah34, ad29, ag33, ag32, ae29, aj34, af30, af29, ah33, ak34, aj33, ag30, am34, aj30, aj29, ak29, ap32, an31, aj27 chitxdata[42:1] i/o line transmit data [42:1]. outputs from the internal multirate cross con- nect. can be used in one of the following modes: asynchronous mode: in this mode, these outputs are used for ds1/e1 trans- mit negative-rail data. may also be used for 8 khz frame synchronization out- puts that indicate the position of the f-bits in the line transmit data. vt mapper mode: 8 khz frame sync output for ds1/e1 or 2 khz frame sync output signal for vc. each of these outputs comes from the internal mrxc and can be individually set to high impedance. in rare cases, this output is used as an input. these pins have various func- tionalities in ds2/e2 applications. mo re information will be published in the ultramapper family system design guide. only chitxdata pins [30:1] will ever be used. chitxdata pins [42:31] will not be needed for the applications ab ove and can be left unconnected.
tmxl84622 ultramapper lite hardware design guide, revision 8 622/155 mbits/s sonet/sdh x ds3/ e3/ds2/ds1/e1 may 11, 2006 28 28 agere systems inc. table 2-19. reference clocks pin symbol type name/description r1 ds2aisclk i pd ds2 ais clock. see application note: configuring ultramapper family of devices for ported ds2 applications. vc11 ais clock . a 1.664 mhz clock input. in the vt mapper mode, this clock is used to generate vc11 ais. th e clock is used when vc11 is sent from the linetxdata[30:1] outputs. the 1.664 mhz clock is for a vc11 payload. there are 27 bytes per vt1.5 in each sts-1 frame, excluding the vt overhead (1 byte), 26 bytes/125 s = 1.664 mbits/s. (vc11 rate is 1.728 mbits/s.) if used, this input can be provided by a free-runni ng crystal oscillator, or clocking chip. u6 e2aisclk i pd e2 ais clock. see application note: configuring ultrama pper family of devices for ported ds2 applications. vc12 ais clock . a 2.240 mhz clock input. in the vt mapper mode, this clock is used to generate vc12 ais. the clock is used when vc12 is sent from the linetxdata[30:1] outputs. the 2.240 mhz clock is for a vc12 payl oad. there are 36 bytes per vt2.0 in each sts-1 frame, excluding the vt overhead (1 byte), 35 bytes/125 s = 2.240 mbits/s. (vc12 rate is 2.304 mbits/s.) if used, this input can be provided by a free-runni ng crystal oscillator, or clocking chip. ap21 e1xclk i pd e1 x clock. this clock signal is used for th ree purposes: to generate e1 ais (all 1s), as a reference to the e1 dja, and as a clock source for the test pat- tern generator and test pattern monitor. this input may be provided by a 2.048 mhz, a 32.768 mhz, or a 65.536 m hz 50 ppm free-running crystal oscillator, or clocking chip. note: for the e1 dja, an input of 32.768 mhz or 65.536 mhz must be used. ak20 ds1xclk i pd ds1 x clock . this clock signal is used for three purposes: to generate ds1 ais (all 1s), as a reference to the ds1 dja, and as a clock source for the test pattern generator and test pattern monitor. this input may be provided by a 1.544 mhz, a 24.704 mhz, or a 49.408 m hz 32 ppm free-running crystal oscillator, or clocking chip. note: for the ds1 dja, an input of 24.704 mhz or 49.408 mhz must be used. a21 ds3xclk i pd ds3 x clock. a 44.736 mhz 20 ppm clock input for ds3 dja and tpg. this input may be provided by a 44.736 mhz 20 ppm free-running crystal oscillator, or clocking chip. f18 e3xclk i pd e3 x clock. a 34.368 mhz 20 ppm clock input for e3 dja and tpg. this input may be provided by a 34.368 mhz 20 ppm free-running crystal oscil- lator, or clocking chip.
hardware design guide, revision 8 tmxl84622 ultramapper lite may 11, 2006 622/155 mbits/s so net/sdh x ds3/e3/ds2/ds1/e1 agere systems inc. 29 table 2-20. low-order path overhead access, transmit direction pin symbol type name/description b22 lopohclkin i pd low-order path overhead clock. 19.44 mhz clock supplied from external circuits that provide the low-order path overhead data. c21 lopohdatain i pd low-order path overhead data. the following parts of the low-order (vt) overhead are presented at this pin: comm unication channel bits (o bits), v5, j2, z6/n2, z7, and k4 byte. a22 lopohvalidin i pd low-order path overhead data input valid. this signal is a mask that indi- cates the location of the overhead bytes in the lopohdatain. table 2-21. low-order path overhead access, receive direction pin symbol type name/description f20 lopohclkout o low-order path overhead clock. 19.44 mhz clock supplied to external cir- cuits that receive the low-order path overhead data. b21 lopohdataout o low-order path overhead data. (line and path rei and rdi, o bits, v5, j2, z6/n2, and z7/k4 byte). e20 lopohvalidout o low-order path overhead data output valid. this signal is a mask which indicates the location of the overhead bytes in the lopohdataout. table 2-22. clock generator pin symbol type name/description aj32 clkin_pll i pd on-chip pll reference input. the clock generator can be used to derive a clock of the appropriate frequency (d s1/e1) synchronized to clkin_pll. al33 cg_pllclkout o pll test mode output. pll clock (1.544 mhz, 2.048 mhz) selected by device register. ak30, ak32, ag29 mode[2:0]_pll i pd pll input clock mode select bits. the settings of these mode select pins must correspond to the frequency of clkin_pll as shown below. mode[2:0]_pll clkin_pll mode[2:0]_pll clkin_pll 000 reserved 100 16.384 mhz 001 51.840 mhz 101 8.192 mhz 010 26.624 mhz 110 4.096 mhz 011 19.440 mhz 111 2.048 mhz
tmxl84622 ultramapper lite hardware design guide, revision 8 622/155 mbits/s sonet/sdh x ds3/ e3/ds2/ds1/e1 may 11, 2006 30 30 agere systems inc. table 2-23. microprocessor interface pin symbol type name/description f5 mpclk i microprocessor clock. this clock is required to properly sample address, data, and control signals from the microprocessor in both asynchronous and synchronous modes of operation. f6 mpmode i microprocessor mode. if the microprocessor interface is synchronous, mpmode should be set to 1. if the mi croprocessor interface is asynchro- nous, mpmode should be set to 0. c1 csn i pu chip select. active-low, high-order address signal. chip select must be set low at the beginning of any read or write access and returned high at the end of the cycle. d2 adsn i address strobe. active-low address strobe that indicates the beginning of a read or write access. it is a one mpclk cycle-wide pulse for synchronous mode. in asynchronous mode, it is active for the entire read/write cycle. address bus signals, addr[20:0], are available to the ultramapper lite when adsn is low. the address bus should remain valid for the duration of adsn. h6 rwn i read/write. rwn is set high during a read cycle, or set low during a write cycle. e3 dsn i data strobe. for a read cycle, the contents of the internal register will be output on data [15:0]; and for a write cycle, the data [15:0] will be clocked into the internal register. to initiate the start of the read/write operation, dsn must be low during the entire read/write cycle. this signal should only be used for asynchronous mode. k2, m6, l5, h1, j2, j3, g1, l6, h2, h3, k6, f1, j5, j6, g2, e1, f2, h5, d1, f3, e2 addr[20:0] i address [20:0]. addr[20] is the most significant bit and addr[0] is the least significant bit for addressing all the internal registers during micropro- cessor access cycles. all addresses are 21-bit word addresses; hence, in a typical application addr[0] of the tmxl84622 device would be connected to address bit 1 of a byte addressable system address bus. note: the ultramapper lite is little-endian, i.e., th e least significant byte is stored in the lowest address and the most significant byte is stored in the highest address. care must be ex ercised in connection to micropro- cessors that use big-endian byte ordering. r6, n1, p3, n2, p5, m1, p6, m2, l1, m3, n6, l2, k1, l3, m5, j1 data[15:0] i/o data [15:0]. 16-bit data bus input for write operations and output for read operations. data[15] is the msb, and data[0] is the lsb. r5, p2 par[1:0] i/o data parity. byte-wide parity bits for data. par[1] is the parity for data[15:8], and par[0] is the parity for data[7:0] p1 dtn o data transfer acknowledge. the delay associated with dtn going low de- pends on the ultramapper lite block being accessed. in asynchronous mode, when adsn or dsn is deasserted, the deassertion will drive the dtn signal high. when inactive, csn will drive dtn to be 3-stated. the microprocessor should wait after dtn is deasserted before starting the next operation. r3, t6 hp_intn, lp_intn o od high-priority and low-priority interrupt. active-low. each of the functional blocks contain their individual low-priority interrupts. high-pr iority interrupts are generated by tmux, and e13 blocks. each in terrupt is individually maskable. requires an external 5 k ? pull-up resistor. r2 aps_intn o od automatic protection switch interrupt. active-low. see the tmux section in the register description data sheet for specific interrupts. each interrupt is individually maskable. requires an external 5 k ? pull-up resistor.
hardware design guide, revision 8 tmxl84622 ultramapper lite may 11, 2006 622/155 mbits/s so net/sdh x ds3/e3/ds2/ds1/e1 agere systems inc. 31 table 2-24. boundary scan ( ieee ? 1149.1) pin symbol type name/description an22 tck i test clock. this signal provides timing for boundary-scan test operations. ak21 tdi i pu test data in. boundary-scan test data input signal, sampled on the rising edge of tck. ap23 tms i pu test mode select. controls boundary-scan test operations. tms is sampled on the rising edge of tck. aj21 trst i pu test reset (active-low). this signal provides an asynchronous reset for the boundary-scan tap controller. an23 tdo o test data out. boundary-scan test data output signal is updated on the fall- ing edge of tck. the tdo output will be high-impedance except when transmitting test data. table 2-25. general-purpose interface pin symbol type name/description ap22 rstn i pu global hardware reset. active-low. initializes all internal registers to their default state. this is an asynchrono us reset on the fa lling edge, but rstn should be held low for at least 1 s . rstn should be held low until both power supplies (1.5 v and 3.3 v) are st abilized upon powerup. am21 pmrst i/o pd performance monitor reset. resets error counters. when enabled as an input, it is a 1 s square wave that forces an update of pm counters upon the rising edge. when the pmrst is generated internally from the mpu clock, this pin is an output. ap24 ic3staten i pu output enable. when high, output buffers will operate no rmally. when low, all outputs will be forced to a high-impedance stat e. ic3staten should be held low until both power supplies (1.5 v and 3.3 v) are stabilized upon pow- erup. am23 sck1 i pd scan clock 1. reserved. do not connect. aj22 sck2 i pd scan clock 2. reserved. do not connect. an24 scan_en i pd scan enable. reserved. do not connect. ap25 scanmode i pd serial scan input for testing. reserved. do not connect. am24 i dd qi iddq input. this pin must be externally pulled down with a 1 k ? resistor. table 2-26. cdr interface pin symbol type name/description aj15 bypass i pd high-speed cdr bypass. reserved. do not connect. aj14 tstphase i pd test phase. reserved. do not connect. am15 ecsel i pd external clock select. reserved. do not connect. aj16 etoggle i pd external toggle. reserved. do not connect. al17 exdnup i pd external down up. reserved. do not connect. ak17 tstmode i pd test mode. reserved. do not connect. am14 tstsftld i pd test shift load. reserved. do not connect.
tmxl84622 ultramapper lite hardware design guide, revision 8 622/155 mbits/s sonet/sdh x ds3/ e3/ds2/ds1/e1 may 11, 2006 32 32 agere systems inc. table 2-27. analog power and ground signals pin symbol type name/description ak12 v ssa_cdr1 ? cdr1 ground. isolated ground for the internal cdr1. aj12 v ssa_cdr2 ? cdr2 ground. isolated ground for the internal cdr2. aj11 v ssa_x4pll ? x4pll ground. isolated ground for the internal x4pll. al34 v ssa_sfpll ? sfpll ground. isolated ground for the internal sfpll. f19 v ssa_ds3pll ? ds3pll ground. isolated ground for the internal ds3pll. a20 v ssa_e3pll ? e3pll ground. isolated ground for the internal e3pll. ak11 v dd15a_cdr1 ? cdr1 power. 1.5 v power supply for the internal cdr1, which is used by the high-speed receive cdr, the prot ection receive cdr, and the three cdrs associated with the mate intercon nect ports. good engineering prac- tice needs to be applied; refer to the evaluation board schematic. aj10 v dd15a_cdr2 ? cdr2 power. 1.5 v power supply for the internal cdr2, which is used by the high-speed receive cdr, the prot ection receive cdr, and the three cdrs associated with the mate intercon nect ports. good engineering prac- tice needs to be applied; refer to the evaluation board schematic. ak14 v dd15a_x4pll ? x4pll power. 1.5 v power supply for the internal x4pll, which is used for the transmit protection 1 + 1 port. good engineering practice needs to be applied; refer to the evaluation board schematic. c20 v dd15a_ds3pll ? ds3pll power. 1.5 v power supply for the internal ds3pll, which is used by the ds3dja. good engineering practice needs to be applied; refer to the evaluation board schematic. b20 v dd15a_e3pll ? e3pll power. 1.5 v power supply for the internal e3pll, which is used by the e3dja. good engineering practice ne eds to be applied; refer to the eval- uation board schematic. ak33 v dd33a_sfpll ? sfpll power. 3.3 v power supply for the internal sfpll, which is used by the cg block. good engineering practice needs to be applied; refer to the evaluation board schematic.
hardware design guide, revision 8 tmxl84622 ultramapper lite may 11, 2006 622/155 mbits/s so net/sdh x ds3/e3/ds2/ds1/e1 agere systems inc. 33 table 2-28. digital power and ground signals pin symbol type name/description aa7, aa16, aa17, aa18, aa1 9, aa28, ab7, ab16, ab17, ab18, ab19, ab28, ac7, ac 28, ad7, ad28, ae7, ae28, af7, af28, ah9, ah10, ah11 , ah12, ah13, ah14, ah15, ah16, ah19, ah20, ah21, ah22, ah23, ah24, ah25, ah26, g9, g10, g11, g12, g13, g14, g15, g16, g19, g20, g21, g22, g23, g24, g25, g26, j7, j28, k7, k28, l7, l28, m7, m28, n7, n16, n17, n18, n1 9, n28, p7, p16, p17, p18, p19, p28, r7, r28, t7, t13, t14, t21, t22, t28, u13, u14, u21, u22, v13, v14, v21, v2 2,w7, w13, w14, w21, w28, y7, y28, w22 v dd15 ? common power signals for 1.5 v v dd . a2, a33, aa4, ac31, ad4, af 31, ag4, ag7, ag28, ah8, ah17, ah18, ah27, aj31, ak4, al6, al9, al12, al21, al24, al27, al30, am2, am33 , an1, an3, an32, an34, ap2, ap33, b1, b3, b32, b34, c2, c33, d5, d8, d11, d14, d17, d20, d23, d26, d29, e31, f4, g8, g17, g18, g27, h7, h28, h31, j4, l31, m4, p31, r4, u7, u28, u31, v28, v4, v7, y31 v dd33 ? common power signals for 3.3 v v dd . a1, a17, a18, a34, aa13, aa 14, aa21, aa22, aa31, ab13, ab14, ab21, ab22, ac4, ad31, af4, ag6, ag31 , aj4, aj5, ak2, ak3, ak5, ak31, al2, al5, al11, al20, al23, al26, al29, al8, am1, am3, am11, am12, am32, an2, an6, an9, an12, an33, ap1, ap12, ap34, b2, b33, c3, c32, d6, d9, d12, d15, d18, d21, d24, d27, d30, e4, e5, f31, h4, j31, l4, m31, n13, n14, n21, n22, p4, p13, p14, p21, p22, r31, t16, t17, t18, t19, u1, u4, u1 6, u17, u18, u19, u34, v1, v16, v17, v18, v19, v31, v34, w16, w17, w18, w19, y4 v ss ? common ground signals. table 2-29. no connects pin symbol type name/description y32, w29, y33, y30, aa34 no connect nc no connect. these pins are not used.
tmxl84622 ultramapper lite hardware design guide, revision 8 622/155 mbits/s sonet/sdh x ds3/ e3/ds2/ds1/e1 may 11, 2006 34 34 agere systems inc. 3 operating conditio ns and reliability 3.1 absolute maximum ratings stresses in excess of the absolute ma ximum ratings can cause permanent damage to the device. these are absolute stress ratings only. functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. ex posure to absolute maximum ratings for extended periods can adversely affect device reliability. 3.2 recommended operating conditions table 3-2 lists the voltages, along with the tolerances, that are required for proper operation of the tmxl84622 device. table 3-2. recommended operating conditions * internal reference voltage is used if umpr_lvds_ ref_sel = 1, or else external voltage is used. 3.3 handling precautions although electrostatic discharge (esd) pr otection circuitry has been designed into this device, proper precautions must be taken to avoid exposure to esd and electrical overstress (e os) during all handling, assembly, and test operations. agere employs both a human-body model (hbm) and a charged-device model (cdm) qualification requirement in order to determine esd-suscept ibility limits and protection design evaluation. esd voltage thresholds are de pendent on the circuit parameters used in each of the models, as defined by jedec?s jesd22-a114 (hbm) and jesd22-c101 (cdm) standards. table 3-1. absolute maximum ratings parameter min max unit supply voltage (v dd33 )?0.54.2v supply voltage (v dd15 )?0.32.0v input voltage: lvcmos lvds ?0.3 ?0.3 5.25 v dd33 + 0.3 v v power dissipation ? ? mw storage temperature range ?65 125 c parameter symbol min typ max unit 3.3 v power supply v dd33 3.14 3.3 3.47 v 1.5 v power supply v dd15 1.4 1.5 1.6 v ground v ss ?0.0 ? v 1.0 v: lvds reference* ref10 ? 1.0 ? v 1.4 v: lvds reference* ref14 ? 1.4 ? v ambient temperature t a ?40 ? 85 c table 3-3. esd tolerance device minimum threshold hbm cdm tmxl84622 2000 v 500 v
hardware design guide, revision 8 tmxl84622 ultramapper lite may 11, 2006 622/155 mbits/s so net/sdh x ds3/e3/ds2/ds1/e1 agere systems inc. 35 3.4 thermal parameters (d efinitions and values) system and circuit board level performance depends not only on de vice electrical characteristic s, but also on device thermal characteristics. the therma l characteristics frequently determine the limits of circuit board or system performance, and they can be a major cost adder or cost avoidance factor. when t he die temperature is kept below 125 c, temperature activated failure mechanisms are minimized. the thermal parameters that agere provides for its packages help the chip and system designer choose the best package for thei r applications, including allowing the syst em designer to thermally design and in- tegrate their systems. it should be noted that all the parameters listed below are affect ed, to varying degrees, by package design (including paddle size) and choice of materials, the amount of copper in the test board or system board, and system airflow. ja - junction to air thermal resistance ja is a number used to express the thermal performance of a part under jedec standard natural convection conditions. ja is calculated using the following formula: ja = (t j ? t amb ) / p; where p = power jma - junction to moving air thermal resistance jma is effectively identical to ja but represents performance of a part mounted on a jedec four layer board inside a wind tunnel with forced air convection. jma is reported at airflows of 200 lfpm and 500 lfpm (linear feet per minute), which roughly correspond to 1 m/s and 2.5 m/s (respectively). jma is calculated using the following formula: jma = (t j ? t amb ) / p jc - junction to case thermal resistance jc is the thermal resistance from junction to the top of the case. this number is determined by forcing nearly 100% of the heat generated in the die out the top of the package by loweri ng the top case temperature. this is done by placing the top of the package in contact with a copper slug kept at room temperature using a liquid refrigeration unit. jc is calculated using the following formula: jc = (t j ? t c ) / p jb - junction to board thermal resistance jb is the thermal resistance from junction to board. this number is determined by forcing the heat generated in the die out of the package through the leads or balls by lowering the board temperature and insulating the package top. this is done using a special fixture, which keeps the board in contact with a water chilled copper slug around the perimeter of the package while insulating the package top. jb is calculated using the following formula: jb = (t j ? t b ) / p jt - junction temperature to case temperature jt correlates the junction temperature to the case temperature. it is generally used by the customer to infer the junction temperature while the part is operating in their syst em. it is not considered a true thermal resistance. jt is calculated using the following formula: jt = (t j ? t c ) / p table 3-4. thermal parameter values parameter temperature c/watt ja 13 jma (1 m/s) 9.7 jma (2.5 m/s) 8.2 jc 2.5 jb 7.8 jt 1
tmxl84622 ultramapper lite hardware design guide, revision 8 622/155 mbits/s sonet/sdh x ds3/ e3/ds2/ds1/e1 may 11, 2006 36 36 agere systems inc. 3.5 reliability product reliability can be calcul ated as the probability that the product will perform under no rmal operating co nditions for a set period of time. factors infl uencing the reliability of a prod uct cover a range of variables, including design and manufac- turing. the failure rate of a pr oduct is given as the number of units failing per unit time. this failure rate is known as fit, which is as follows: 1 fit = 1 failure/1 x 10 9 hours. another unit used for failure rate is kn own as mtbf, which is 1/fit. many assump tions are made when calculating the failure rate for a product, such as the average junction temperatur e and activation energy. the as sumptions made for calculating fit and mtbf are shown in table 3-5: moisture sensitivity level ?this is based on ipc/jedec test method j-std- 020 (which lists a means of testing and clas- sifying devices for a certain le vel of moisture sensitivity). 3.6 recommended powerup sequence the ultramapper lite device requires dual power supplies, a 3.3 v su pply for the i/o, and a 1.5 v supply for the core. during powerup, rstn should be held low (holding the device in reset) and ic3staten should be held low (3-stating all output buffers). after the 3.3 v and 1.5 v supplies are stable, mpclk (which affects the device reset) should be applied and must be present for at least two clock cycles before rstn and ic3staten are released. it is then recommended that ic3staten be released concurrent with, or after, the release of rstn. there are no constraints as to which supply (3.3 v or 1.5 v) must come up first, nor does it matter how long it takes the second supply to come up after the first supply. additionally, it is recommended that the trst pin be held low (or pulsed low) upon startup. 3.7 power consumption the power consumption of the device is ap plication dependent since it is not possibl e to use all the device features simul- taneously. the nominal measured values for power per block are shown in table 3-8. table 3-5. reliability data junction temperature fit (per 1 x 10 9 device hours) mtbf activation energy 55 c 22 4.55 x 107 hours 0.7ev table 3-6. moisture sensitivity level device level tmxl84622 2a l-tmxl84622 (pb-free) 3 table 3-7. typical power consumpti on by application (50 mhz mpu clock) application conditions typ 1.5 v power typ 3.3 v power typ total power oc12 to 84 ds1 transport mode. tmux, three spemprs, th ree vtmprss, three ds1dja3, and three frms. 1.60 w 0.50 w 2.10 w oc12 to 6 ds3 clear ch annel. tmux, six spemprs, one ds3dja, and six ds3 i/os. 1.00 w 0.75 w 1.75 w oc12 to stspp. high-speed loopback through stspp and tmux. 0.90 w 0.50 w 1.40 w oc12 to 84 ds1 portless transmux application, trans- port mode. tmux, three sts1lts, five spemprs, three vtmprs, two m13s, three ds1dja, and three frmrs. 1.70 w 0.85 w 2.55 w oc12 to 84 ds1 transmux application, transport mode. tmux, three sts1lts, th ree spemprs, three vtm- prs, three m13s , three ds1djas, and three frmrs. 1.70 w 0.60 w 2.30 w
hardware design guide, revision 8 tmxl84622 ultramapper lite may 11, 2006 622/155 mbits/s so net/sdh x ds3/e3/ds2/ds1/e1 agere systems inc. 37 testing has shown that, on the average, approxi mately 0.35 w can be saved by utilizing the divide by 16 mpu clock power down feature. please refer to mpu register 0x0019 in the ultramapper register description document for further information. additional mpu clock divisor options are available. additional power can be saved by powering down unused lvds buffers. for details, please see mpu register 0x0026 in the ultramapper register description document. table 3-8. typical power consumption per block typical power by block refers to all instances being used. block maximum instance typical, per single instance unit tmux 1 0.120 w stspp 1 0.020 w stsxc 1 0.200 w mrxc 1 0.050 w spempr 6 0.009 w sts1lt 3 0.028 w vtmpr 3 0.015 w e13 3 0.013 w m13 3 0.013 w tpg/tpm 1 tbd w frm 3 0.195 w ds1dja 3 0.026 w ds3dja 1 0.050 w mpu 1 0.420* w cdr/pll 1 0.150 w lvds i/o 15 0.020 w nsmi i/o 3 0.032 w ds3 i/o 6 0.050 w * measured with a 50 mhz mpclk. with a 25 mhz mpclk, the typi cal per single instance value of mpu power is approximately 0.2 w.
tmxl84622 ultramapper lite hardware design guide, revision 8 622/155 mbits/s sonet/sdh x ds3/ e3/ds2/ds1/e1 may 11, 2006 38 38 agere systems inc. 4 electrical characteristics 4.1 lvcmos interface specifications * excludes current due to pul l-up or pull-down resistors. table 4-1. lvcmos input specifications parameter symbol conditions min typ max unit input leakage current i i v ss < v in < v dd33 ? ? 1.0* a high-input voltage v ih ?2.0??v low-input voltage v il ?v ss ?0.8v input capacitance c i ???1.5pf table 4-2. lvcmos output specifications parameter symbol conditions min typ max unit output voltage low v ol i ol = max v ss ?0.5v output voltage high v oh i ol = max v dd ? 0.5 ? v dd v output current low i ol ???6*ma output current high i oh ????6*ma output capacitance c o ??3?pf hiz output leakage current i oz ???10a * output current = 10 ma (maximum) for dtn, nsmitxclk[3:1] and chitxdata[1, 3, 4, 5, 6, 10, 11]. table 4-3. lvcmos bidirectional specifications parameter symbol conditions min typ max unit leakage current i l v ss < v in < v dd33 ?? 11 a high-input voltage v ih ?2.0?v dd33 + 0.3 v low-input voltage v il ?v ss ?0.8 v biput capacitance c ib ? ? 5.0 ? pf output voltage low v ol i ol = ?6 ma* ? ? 0.5 v output voltage high v oh i oh = 6 ma* 2.4 ? ? v output current low iol ? ? ? 6 ma output current high ioh ? ? ? ?6 ma * the following bidirectional pins c an sink/source 10 ma: nsmirxclk[3:1].
hardware design guide, revision 8 tmxl84622 ultramapper lite may 11, 2006 622/155 mbits/s so net/sdh x ds3/e3/ds2/ds1/e1 agere systems inc. 39 4.2 lvds interface characteristics 3.3 v 5% v dd , ?40 c to +125 c junction temperature. . * the buffer will not produce output transitions when input is open-circuited. when the true and complement inputs are floating , the input buffer will not oscillate. ? 250 mv |v a ? v b | 450 mv note: the characteristics in the table above apply under the following conditions: external lvds reference chosen (umpr_lvds_ref_sel = 0). ref10 = 1.0 v 3% and ref14 = 1.4 v 3%. internal lvds reference chosen (umpr_lvds_ref_sel = 1). vdd33 supply controlled to within 3%. when umpr_lvds_ref_sel = 1, the internal reference levels are der ived using a resistor ladder from vdd33. these levels will var y as much as the vdd33 supply does and are therefore only as accurate as the v dd33. if vdd33 cannot be controlled to within 3%, one or more ieee specifications may be violated. while this may not necessarily lead to data errors during transmission, interoperabilit y issues may arise due to s pecification noncompliance. table 4-4. lvds interface dc characteristics parameter symbol test conditions min typ max unit input buffer parameters input voltage range: high (v ia or v ib ) low (v ia or v ib ) v i v ih v il |v gpd | < 925 mv, dc?1 mhz ? 0 ? ? 2.4 ? v v input differential threshold v idth dc?450 mhz ?100 ? 100 mv input differential hysteresis v hyst (+v idth ) ? (?v idth )???*mv receiver differential input impedance r in with build-in termination, center-tapped 80 100 120 ? output buffer parameters output voltage: high (v oa or v ob ) low (v oa or v ob ) v oh v ol r load = 100 ? 1% r load = 100 ? 1% ? 0.925 ? ? 1.475 ? v v output differential voltage ? |v od |r load = 100 ? 1% 0.25 ? 0.45 v output offset voltage v os r load = 100 ? 1% 1.125 ? 1.275 v output impedance, single ended r o v cm = 1.0 v and 1.4 v 80 100 120 ? r o mismatch between a and b ? r o v cm = 1.0 v and 1.4 v ? ? 10 % change in differential voltage between complementary states | ? v od |r load = 100 ? 1% ? ? 25 mv change in output offset voltage between complementary states ? v os r load = 100 ? 1% ? ? 25 mv output current i sa , i sb driver shorted to v ss ??24ma output current i sab drivers shorted together ? ? 12 ma
tmxl84622 ultramapper lite hardware design guide, revision 8 622/155 mbits/s sonet/sdh x ds3/ e3/ds2/ds1/e1 may 11, 2006 40 40 agere systems inc. 5 timing 5.1 tmux high-speed interface figure 5-1. tmux lvds signal rise/fall timing figure 5-2. tmux lvds clock and data timing table 5-1. high-speed interface input specification name reference edge rising/falling max rise time (ns) max fall time (ns) min setup (ns) min hold (ns) rhsdp/n (622 mhz)* * input serial data stream should have minimum eye opening of 0. 4 uip-p, and no more than 60 consecutive bits that have no tra nsitional edge within one minute. it must meet 100 ps maximum phase variation li mit over a 200 ns interval; this translates to a frequency cha nge of 500 ppm. asynchronous ? 0.5 0.5 ? ? rhsdp/n (155 mhz) * asynchronous ? 0.5 0.5 ? ? rhsdp/n (155 mhz) rhscp/n r/f 1.0 1.0 2 0 table 5-2. protection link input specification name reference edge rising/falling max rise time (ns) max fall time (ns) min setup (ns) min hold (ns) rpsdp/n (622 mhz)* * input serial data stream should have minimum eye opening of 0. 4 uip-p, and no more than 60 consecutive bits that have no tra nsitional edge within one minute. it must meet 100 ps maximum phase variation li mit over a 200 ns interval; this translates to a frequency cha nge of 500 ppm. asynchronous ? 0.5 0.5 ? ? rpsdp/n (155 mhz) * asynchronous ? 0.5 0.5 ? ? rpsdp/n (155 mhz) rpscp/n r 1.0 1.0 2 0 t f t r 80% 20% thscop/n rhscp/n t su t h t pd 50% 50% 50% 50% rhsdp/n thsdp/n
hardware design guide, revision 8 tmxl84622 ultramapper lite may 11, 2006 622/155 mbits/s so net/sdh x ds3/e3/ds2/ds1/e1 agere systems inc. 41 5.2 thssync characteristics thssync is an 8 khz composite frame sync pulse for sts-3 or sts-12. thssync contains j 0 , j 1 , and v 1-1 information as shown in figure 5-3. the time delay from any rising edge of a j 0 (8 khz) to the rising edge of the next j 0 is 125 s. the time delay between any two v 1-1 (2 khz) pulses is 500 s. this is tr ue whether in sts-3 or sts-12 mode. when mpu_master_slave = 1, then thssync is according to figure 5-3. figure 5-3. thssync timing di agram (mpu_master_slave = 1) when mpu_master_slave = 0, then thssyn c (supplied from an ex ternal source) can be according to figure 5-4. figure 5-4. thssync timing di agram (mpu_master_slave = 0) when supplied externally, the 8 khz thssync may have a 50/50 du ty cycle since the signal will only be sampled on the rising edge. in this case, thssync should be synchronous to thsc. although there are no setup/hold specifications for the thssync input with respect to thsc, thssync still needs to be sy nchronous to the input tr ansmit high-speed clock (thsc). the device looks for t he rising edge of thssync to occu r regularly in each frame wit hin a window, defined by the setting in tmux_sync_offset[3:0]. table 5-3. high-speed interface outputs name reference edge rising/falling propagation delay min (ns) max (ns) thsdp/n (622.08 mhz or 155.52 mhz) thscop/n r 0.3 0.8 thssync (mpu_master_slave = 1) tlsclk ? ?0.5 0.2 table 5-4. protection link outputs name reference edge rising/falling propagation delay min (ns) max (ns) tpsdp/n (622.08 mhz or 15 5.52 mhz) tpscp/n r 0.3 0.8 sts-3 j 0 j 1-1 j 0 j 1-2 j 1-3 v 1-1 j 1-1 j 1-2 j 1-3 first frame 50 ns second frame third frame fourth frame sts-12 v 1-2 v 1-3 j 0 j 0 j 1-1 j 1-2 j 1-3 j 1-1 j 1-2 j 1-3 v 1-1 v 1-2 v 1-3 j 1-1 j 1-2 j 1-3 j 1-5 j 1-7 j 1-9 j 1-11 j 1-4 j 1-6 j 1-8 j 1-10 j 1-12 50 ns j 1-1 j 1-2 j 1-3 j 1-5 j 1-7 j 1-9 j 1-11 j 1-4 j 1-6 j 1-8 j 1-10 j 1-12 j 1-1 j 1-2 j 1-3 j 1-5 j 1-7 j 1-9 j 1-11 j 1-4 j 1-6 j 1-8 j 1-10 j 1-12 j 1-1 j 1-2 j 1-3 j 1-5 j 1-7 j 1-9 j 1-11 j 1-4 j 1-6 j 1-8 j 1-10 j 1-12 j 0 j 0 j 0 j 0 12.5 ns first frame second frame third frame fourth frame sts-3 j0 first frame 50 ns sts-12 50 ns 125 s 125 s j0 j0 j0 second frame third frame fourth frame second frame third frame fourth frame first frame j0 j0 j0 j0
tmxl84622 ultramapper lite hardware design guide, revision 8 622/155 mbits/s sonet/sdh x ds3/ e3/ds2/ds1/e1 may 11, 2006 42 42 agere systems inc. a clock derived from thsc samples the in coming frame sync. if thssync is not sync hronous to thsc, over time, the rising edge of thssync will fall outside the windo w causing an sts-n/stm-n level lof. however, if the system needs to sync hronize vts, generated from different ultramapper lite devices or other external de- vices, then thssync need s to look like the waveform repr esentation in figure 5-5, i.e ., thssync must be composed of both the 8 khz and the 2 khz sync components (j 0 + v 1-1? v 1-3 ); the j 1 portion is not needed. figure 5-5. thssync timing di agram for synchronized vts figure 5-6 depicts the relationsh ip between the rising edge of the input thssync (when the de vice is in slave mode) and the beginning of the sonet frame output on thsd. the de lay between thssync and the start of the outgoing sonet frame is contributed to internal device delays (pertaining to multiplexing functionality, fifo, and parallel to serial conversi on). figure 5-6. rela tionship between thssync and thsd sts-3 j 0 j 0 v 1-1 first frame 50 ns second frame third frame fourth frame sts-12 v 1-2 v 1-3 j 0 j 0 v 1-1 v 1-2 v 1-3 50 ns j 0 j 0 j 0 j 0 first frame second frame third frame fourth frame thssync thsd x y a1 n 622 mbits/s mode: n = 80 8 bits. 155 mb its/s mode: n = 44 8 bits. for the case where tmux_tlbitcnt, tmux_tlstscnt, tmux_tlcolcnt, and tmux_tlrowcnt, all = 0 ( default). changing these register values will change the location of point x with relation to point y.
hardware design guide, revision 8 tmxl84622 ultramapper lite may 11, 2006 622/155 mbits/s so net/sdh x ds3/e3/ds2/ds1/e1 agere systems inc. 43 5.3 sts-3/stm-1 mate interconnect timing figure 5-7. sts-3/stm-1 mate rise/fall timing figure 5-8. sts-3/stm-1 ma te clock and data timing table 5-5. sts-3/stm-1 mate interconnect input specification name reference edge rising/falling max rise time (ns) max fall time (ns) min setup (ns) min hold (ns) tlsdatap/n[3:1] asynchronous ? ? ??? table 5-6. sts-3/stm-1 mate in terconnect output specification name reference edge rising/falling propagation delay min (ns) max (ns) rlsdatap/n[3:1] asynchronous ? ? ? t f t r 80% 20% clock clock tlsdatap/n t su t h t pd 50% 50% 50% 50% rlsdatap/n
tmxl84622 ultramapper lite hardware design guide, revision 8 622/155 mbits/s sonet/sdh x ds3/ e3/ds2/ds1/e1 may 11, 2006 44 44 agere systems inc. 5.4 toac, poac, and lopoh timing the relationships between data, clock, and sync signals are specific to the toac and poac operation mode selected. this is explained in detail in the toac/poac chapter of the system design guide. note: for information pertaining to the output clock duty cycle (in various toac/poac modes of operation), please refer totable 6-13 and table 6-14. figure 5-9. toac, poac timing note: for all modes, sync signals are high during t he clock period of the fi rst bit of each frame. figure 5-10. lopoh timing table 5-7. toac, poac, a nd lopoh input specification name reference edge rising/falling max rise time (ns) max fall time (ns) min setup (ns) min hold (ns) ttoacdata ttoacclk (output) r 10 10 3.5 0 tpoacdata tpoacclk (output) r 10 10 3.5 0 lopohdatain and lopohvalidin lopohclkin f 8 8 5 5 table 5-8. toac, poac, and lopoh output specification name reference edge rising/falling propagation delay min (ns) max (ns) rtoacdata, rtoacsync rtoacclk r 0 3.5 ttoacsync ttoacclk r 0 3.5 rpoacdata, rpoacsync rpoacclk f 0 3.5 tpoacsync tpoacclk r 0 3.5 lopohdataout and lopohv alidout lopohclkout r 0 5 tpoacclk t pd t su t h ttoacclk tpoacdata ttoacdata rpoacdata rtoacdata rpoacclk rtoacclk lopohclkin t su t h lopohdatain lopohdataout lopohclkout t pd
hardware design guide, revision 8 tmxl84622 ultramapper lite may 11, 2006 622/155 mbits/s so net/sdh x ds3/e3/ds2/ds1/e1 agere systems inc. 45 5.5 ds3/e3/sts-1 timing figure 5-11 shows a simplified representation of the ds3/e3/sts-1 i/o. figure 5-11. ds3/e3 interface diagram in m13/e13 block table 5-9. ds3/e3 input specification name reference edge rising/falling max rise time (ns) max fall time (ns) min setup (ns) min hold (ns) ds3posdatain[6:1] ds3negdatain[6:1] ds3datainclk r/f 5 5 3 3 table 5-10. sts-1 input specification name reference edge rising/falling max rise time (ns) max fall time (ns) min setup (ns) min hold (ns) ds3posdatain[6:1] ds3negdatain[6:1] ds3datainclk f 5 5 3 3 table 5-11. ds3/e3/sts-1 output specification name reference edge rising/falling propagation delay min (ns) max (ns) ds3posdataout[6:1], ds3negdataout[6:1] ds3rxclkout r/f 0 3 m13/e13 block demux mux q q clk clk d d ds3datainclk ds3posdatain ds3negdatain ds3dataoutclk ds3posdataout ds3negdataout ds3rxclkout
tmxl84622 ultramapper lite hardware design guide, revision 8 622/155 mbits/s sonet/sdh x ds3/ e3/ds2/ds1/e1 may 11, 2006 46 46 agere systems inc. 5.6 nsmi timing figure 5-12. nsmi clock and data timing for the sts-1 mode figure 5-13. nsmi clock and data diagram for spempr nsmi mode nsmitxclk t pd t su t h nsmirxclk nsmirxdata nsmitxdata nsmi_txdataen (output) nsmi_txclk (51.84 mhz output) sonet frame (for info only) nsmi_txdata (output) nsmi_txsync (output) nsmi_rxclk (51.84 mhz output) sonet frame (for info only) nsmi_rxdata (input) nsmi_rxsync (output) position of above pulse is provisionable 0-89 bytes + 0-7 bits before j1 note: tx and rx j1 are not aligned. transmit path pointer is fixed at 522. nsmi_rxdataen (output) 125 s position of above pulse is provisionable 0 - 89 bytes + 0 - 7 bits before j1 125 s separation depends on pointer z3 z3 89 columns z4 toh j1 toh c2 toh z4 z4 89 columns j1 toh c2 toh g1 toh notes: clock from spempr is at 51.84 mhz rate and is not gapped. tx dataen is provided to mark the poh time of the spe. j1 can occur anywhere in the frame and its position is optionally marked by txsync, wh ich is provisioned to be n columns (bytes ) plus m bits earlier in time than j1. during periods where the poh is pres ent, the txdataen signal goes high.
hardware design guide, revision 8 tmxl84622 ultramapper lite may 11, 2006 622/155 mbits/s so net/sdh x ds3/e3/ds2/ds1/e1 agere systems inc. 47 figure 5-14. nsmi clock and data diagram for m13 nsmi mode (nsmi <---> m13 <---> ds3 external i/o) figure 5-15. nsmi clock and data diagram for e13 nsmi mode 1 (nsmi <---> e13 <---> e3 external i/o) nsmi_txdataen nsmi_txclk 44.736 mhz x1 x2 m1 m3 ds3 frame (for info only) x1 nsmi_txdata nsmi_txsync 4760 bits position of this pulse is provisionable 0-256 bits before m1 nsmi_rxclk 44.736 mhz output x1 x2 m1 m3 ds3 frame x1 nsmi_rxdata nsmi_rxsync 4760 bits position of this pulse is provisionable 0-256 bits before m1 nsmi_rxdataen notes: clock from m13 is at 44.736 mhz rate and is not gapped. tx dataen is provided to mark the ds3 frame overhead times. m1 can occur asynchronously and its positio n is optionally marked by t xsync, which is provisioned to be 0 to 255 bits before th e m1 bit. txdataen goes low during ds3 frame overhead bits. nsmi_txdataen (output) nsmi_txclk (34.368 mhz output) e3 frame (for info only) nsmi_txdata (output) nsmi_txsync (output) nsmi_rxclk (34.368 mhz output) e3 frame (for info only) nsmi_rxdata (input) nsmi_rxsync (output) nsmi_rxdataen (output) 1536 bits position of this pulse is provisionable 0-256 bits before c11 frame, rai, rsvd c11 = 0 cj3 = 0 frame stuff = data 1536 bits position of this pulse is provisionable 0-256 bits before c11 frame, rai, rsvd c11 = 0 cj3 = 0 frame stuff = data notes: clock from e13 is at 34.368 mhz rate and is not gapped. txdataen is provided to mark the overhead time and control bits time of the e3 frame. c11?s (the first c-bit of the first tributary) position is optional ly marked by txsync, which is provisioned to be 0 to 255 bit s before c11 (bit 385 of the e3 frame). during periods where the oh is present, the txdataen signal goes low. all c-bits are zero and the stuff bits are used for data.
tmxl84622 ultramapper lite hardware design guide, revision 8 622/155 mbits/s sonet/sdh x ds3/ e3/ds2/ds1/e1 may 11, 2006 48 48 agere systems inc. figure 5-16. nsmi clock and data diagram for e13 nsmi mode 2 (nsmi <--> e13 <--> spempr <--> stm-n) nsmi_txdataen (output) nsmi_txclk (51.84 mhz output) e3 frame (for info only) nsmi_txdata (output) nsmi_txsync (output) nsmi_rxclk (51.84 mhz output) e3 frame (for info only) nsmi_rxdata (input) nsmi_rxsync (output) nsmi_rxdataen (output) 1536 bits position of this pulse is provisionable 0-256 bits before c11 frame, rai, rsvd c11 = 0 cj3 = 0 frame stuff = data 1536 bits position of this pulse is provisionable 0-256 bits before c11 frame, rai, rsvd c11 = 0 cj3 = 0 frame stuff = data notes: clock from e13 is at 51.84 mhz rate and is not gapped. txdat aen is the combination of an internal clock enable and data enable from spempr. txdataen is used to mark the overhead time and control bits time of the e3 frame. clock enable is used to gap the clock rate to 34.368 mhz. c11?s (the first c-bit of the first tribut ary) position is optionally marked by txsyn c, which is provisi oned to be 0 to 255 bit s before c11 (bit 385 of the e3 frame). during periods where the oh is pr esent, the txdataen signal goes low. all c-bits are zero and the stuff bits are used for data.
hardware design guide, revision 8 tmxl84622 ultramapper lite may 11, 2006 622/155 mbits/s so net/sdh x ds3/e3/ds2/ds1/e1 agere systems inc. 49 figure 5-17. nsmi clock and data di agram for framer (frm) nsmi mode table 5-12. nsmi input specifications name reference edge rising/falling max rise time (ns) max fall time (ns) min setup (ns) min hold (ns) nsmirxdata[3:1] nsmirxclk r 3.5 3.5 5 0 nsmirxsync[3:1] nsmirxclk r 3.5 3.5 5 0 nsmirxdata[3:1]* nsmirxclk r 3.5 3.5 3.5 3 nsmirxsync[3:1]* nsmirxclk r 3.5 3.5 3.5 3 * pertinent to ds3 clear channel applicat ion, which uses nsmi i/o?this featur e is available only in v3.0 devices. table 5-13. nsmi output specifications name reference edge rising/falling propagation delay min (ns) max (ns) nsmitxdata[3:1] nsmitxclk r 0.5 8.75 nsmitxsync[3:1] nsmitxclk r 0.5 8.75 rxdataen[3:1] nsmirxclk r 0.5 8.75 txdataen[3:1] nsmitxclk r 0.5 8.75 nsmirxsync[3:1] nsmirxclk r 0.5 8.75 note: the 193rd bit of a ds1 frame is not transmitted on the ns mi but is used to locate the fsync position. as a conse- quence of this, signaling bits are not transported in ultramapper lite versions 1?2.1. version 3 devices contain a mode allowing transmission of the framing bit. msb lsb start fsync lsb rsvd msb link number[0:4] data byte(time slot) for a ds0/e0 link data 1,1 data 2,1 data 1,2 data 2,2 data 2,2 data link#,byte# data 5,1 data 5,1 data 5,2 data 5,2 data 5,3 data 5,3 01100000 01010000 00100000 00010000 01101000 nsmitxclk 51.84mhz nsmitxdata nsmitxsync binary value links may appear in any order, bytes per link are sequential start goes low to signify data, high otherwise fsync high signifies 1 st byte of link n } link number provisionable 1:28 or 0:27 for ds1 nsmitxclk nsmitxdata nsmitxsync
tmxl84622 ultramapper lite hardware design guide, revision 8 622/155 mbits/s sonet/sdh x ds3/ e3/ds2/ds1/e1 may 11, 2006 50 50 agere systems inc. 5.7 shared low-speed line timing note: single-rail shown. figure 5-18. shared low-speed line clock and data timing table 5-14. shared low-speed line timing input specification name reference edge rising/falling max rise time (ns) max fall time (ns) min setup (ns) min hold (ns) linerxdata[30:1] linerxclk[30:1] r/f 10* 10* 15 10* * alternative spec: the maximum rise and fall times may be increased to 20 ns each if the minimum hold time is increased to 12 n s. the minimum setup time will remain at 15 ns. table 5-15. shared low-speed line timing output specification name reference edge rising/falling propagation delay min (ns) max (ns) linetxdata[30:1] linetxclk[30:1] r/f ?10 10 linetxclk t pd t su t h linerxclk linerxdata linetxdata
hardware design guide, revision 8 tmxl84622 ultramapper lite may 11, 2006 622/155 mbits/s so net/sdh x ds3/e3/ds2/ds1/e1 agere systems inc. 51 6 reference clocks table 6-1. high-speed interface input clocks specifications clock name period (ns) frequency accuracy (ppm) jitter rise (ns) fall (ns) min/ max duty cycle rhscp/n 6.43 155.52 mhz 20 ? 0.4 0.4 nom 45%?55% thscp/n 6.43 155.52 mhz 20 0.01 uip-p or 64 psp-p or 0.001 ui rms (12 khz?1.3 mhz) 0.4 0.4 nom 45%?55% thscp/n 1.6 622.08 mhz 20 0.04 uip-p or 64 psp-p (12 khz?5 mhz) 0.4 nom 0.6 max ? 45%?55% table 6-2. protection link input clock specifications clock name period (ns) frequency accuracy (ppm) jitter rise (ns) fall (ns) min/ max duty cycle rpscp/n 6.43 155.52 mhz 20 ? 0.4 0.4 nom 45%?55% table 6-3. ds3/e3/sts-1 input clocks specifications clock name period (ns) frequency accuracy (ppm) jitter rise (ns) fall (ns) min/ max duty cycle ds3dataoutclk[6:1] (ds3) 2 2.353 44.736 mhz 20 0.05 uip-p or 1.12 nsp-p (10 khz?400 khz) 5 5 max 40%?60% ds3datainclk[6:1] (ds3) 22.353 44.736 mhz 20 ? 3.5 2.5 max 45%?55% ds3dataoutclk[6:1] (e3) 29.090 34.368 mhz 20 0.03 uip-p or 0.87 nsp-p (100 khz?800 khz) 5 5 max 40%?60% ds3datainclk[6:1]] (e3) 29.090 34.368 mhz 20 ? 3.5 2.5 max 45%?55% ds3dataoutclk[6:1] (sts-1) 19.290 51.84 mhz 20 0.01 uip-p or 0.19 nsp-p or 0.001 ui rms (12 khz?400 khz) 5 5 max 40%?60% ds3datainclk[6:1] (sts-1) 19.290 51.84 mhz 20 ? 3.5 2.5 max 45%?55% table 6-4. ds1/e1 dja i nput clocks specifications clock name period (ns) frequency accuracy (ppm) jitter rise (ns) fall (ns) min/ max duty cycle e1xclk 15.25 65.536 mhz 50 0.1 uip-p or 1.5 nsp-p (20 khz?100 khz) 3.5 3.5 max 40%?60% ds1xclk 20.20 49.408 mhz 32 0.1 uip-p or 2.0 nsp-p (10 khz?40 khz) 3.5 3.5 max 40%?60% e1xclk 30.52 32.768 mhz 50 0.1 uip-p or 3.0 nsp-p (20 khz?100 khz) 3.5 3.5 max 40%?60% ds1xclk 40.40 24.704 mhz 32 0.1 uip-p or 4.0 nsp-p (10 khz?40 khz) 3.5 3.5 max 40%?60%
tmxl84622 ultramapper lite hardware design guide, revision 8 622/155 mbits/s sonet/sdh x ds3/ e3/ds2/ds1/e1 may 11, 2006 52 52 agere systems inc. table 6-5. m13/e13 input clocks specifications clock name period (ns) frequency accuracy (ppm) jitter rise (ns) fall (ns) min/max duty cycle ds2aisclk 158.42 6.312 mhz 30 ? 5 5 max 45%?55% e2aisclk 118.37 8.448 mhz 30 ? 5 5 max 45%?55% table 6-6. ds3/e3 dja i nput clocks specifications clock name period (ns) frequency accuracy (ppm) jitter rise (ns) fall (ns) min/max duty cycle ds3xclk 22.35 44.736 mhz 20 0.01 uip-p or 0.22 nsp-p (10 khz?400 khz) 3.5 3.5 max 45%?55% e3xclk 29.09 34.368 mhz 20 0.01 uip-p or 0.29 nsp-p (100 khz?800 khz) 3.5 3.5 max 45%?55% table 6-7. lopoh input clock specifications clock name period (ns) frequency accuracy (ppm) jitter rise (ns) fall (ns) min/max duty cycle lopohclkin 51.44 19.44 mhz ? ? 8 8 max 45%?55% table 6-8. microprocessor inte rface input clocks specifications clock name period (ns) frequency accuracy (ppm) jitter rise (ns) fall (ns) min/max duty cycle mpclk (min) 62.5 16 mhz ? ? 4 4 min 45%?55% mpclk (max)* * the following applies to the synchronous microprocessor mode (mpmode pin = 1): if dtn is used, then the maximum frequency fo r mpclk is determined by the processor?s setup specification for dtn. mpu maximum bus operating frequency = 1/(mpu dtn setup time + tdtnvp d). for example, an 8 ns setup time would limi t mpclk to 50 mhz for reliable dtn detection. 15.0 66.67 mhz ? ? 4 4 max 45%?55% table 6-9. pll input clock specifications clock name period (ns) frequency accuracy (ppm) jitter rise (ns) fall (ns) min/max duty cycle clkin_pll 19.2 51.84 mhz 20 gr-499 and g.823 ? ? ? 40%?60% table 6-10. high-speed interface output clocks specifications clock name period (ns) frequency accuracy (ppm) jitter rise (ns) fall (ns) min/max duty cycle thscop/n 6.43 155.52 mhz 20 0.1 uip-p ? ? ? 45%?55% thscop/n 1.6 622 mhz 20 0.1 uip-p ? ? ? 45%?55% table 6-11. protection link output clocks specifications clock name period (ns) frequency accuracy (ppm) jitter rise (ns) fall (ns) min/max duty cycle tpscp/n 6.43 155.52 mhz 20 ? ? ? ? 45%?55% tpscp/n 1.6 622.08 mhz 20 ? ? ? ? 45%?55%
hardware design guide, revision 8 tmxl84622 ultramapper lite may 11, 2006 622/155 mbits/s so net/sdh x ds3/e3/ds2/ds1/e1 agere systems inc. 53 table 6-12. line timing interface output clocks specifications clock name period (ns) frequency accuracy (ppm) jitter rise (ns) fall (ns) min/max duty cycle rlsclk 51.44 19.44 mhz 20 ? 1.5 1.5 nom 45%?55% tlsclk 51.44 19.44 mhz 20 ? 1.5 1.5 nom 45%?55% table 6-13. toac output clocks specifications clock name period (ns) frequency accuracy (ppm) jitter rise (ns) fall (ns) min/max duty cycle rtoacclk (sts1lt; full access) 578 1.728 mhz ? ? 1.5 1.5 nom 40%?60% rtoacclk (tmux; sts-12 d1-3 mode) 5.2 ( s) 192 khz ? ? 1.5 1.5 nom 27%?47%* rtoacclk (tmux; sts-12 d4-12 mode) 1.73 ( s) 576 khz ? ? 1.5 1.5 nom 43%?63%* rtoacclk (tmux; sts-12 full access) 48.22 20.736 mhz ? ? 1.5 1.5 nom 23%?43%* rtoacclk (tmux; sts-3 d1-3 mode) 5.2 ( s) 192 khz ? ? 1.5 1.5 nom 48%?68%* rtoacclk (tmux; sts-3 d4-12 mode) 1.73 ( s) 576 khz ? ? 1.5 1.5 nom 42%?62%* rtoacclk (tmux; sts-3 full access) 192.9 5.184 mhz ? ? 1.5 1.5 nom 23%?43%* ttoacclk (sts1lt; full access ) 578 1.728 mhz ? ? 1.5 1.5 nom 40%?60% ttoacclk (tmux; sts-12 d1-3 mode) 5.2 ( s) 192 khz ? ? 1.5 1.5 nom 27%?47%* ttoacclk (tmux; sts-12 d4-12 mode) 1.73 ( s) 576 khz ? ? 1.5 1.5 nom 43%?63%* ttoacclk (tmux; sts-12 full access) 48.22 20.736 mhz ? ? 1.5 1.5 nom 23%?43%* ttoacclk (tmux-sts-3 d1-3 mode) 5.2 ( s) 192 khz ? ? 1.5 1.5 nom 48%?68%* ttoacclk (tmux-sts-3 d4-12 mode) 1.73 ( s) 576 khz ? ? 1.5 1.5 nom 42%?62%* ttoacclk (tmux-sts-3 full access) 192.9 5.184 mhz ? ? 1.5 1.5 nom 23%?43%* * positive duty cycle. table 6-14. poac output clocks specifications clock name period (ns) frequency accuracy (ppm) jitter rise (ns) fall (ns) min/max duty cycle rpoacclk (tmux) 1.73 ( s) 576 khz ? ? 1.5 1.5 nom 40%?60% rpoacclk (sts1lt) 1.73 ( s) 576 khz ? ? 1.5 1.5 nom 40%?60% rpoacclk (spempr) 1.73 ( s) 576 khz ? ? 1.5 1.5 nom 40%?60% tpoacclk (tmux) 1.73 ( s) 576 khz ? ? 1.5 1.5 nom 40%?60% tpoacclk (sts1lt) 1.73 ( s) 576 khz ? ? 1.5 1.5 nom 40%?60% tpoacclk (spempr) 1.73 ( s) 576 khz ? ? 1.5 1.5 nom 40%?60%
tmxl84622 ultramapper lite hardware design guide, revision 8 622/155 mbits/s sonet/sdh x ds3/ e3/ds2/ds1/e1 may 11, 2006 54 54 agere systems inc. table 6-15. ds3/e3/sts-1 output clocks specifications clock name period (ns) frequency accuracy (ppm) jitter rise (ns) fall (ns) min/max duty cycle ds3rxclkout [6:1] (ds3) 22.353 44. 736 mhz 20 gr-253 1.5 1.5 nom 45%?55% ds3rxclkout [6:1] (e3) 29.09 34.3 68 mhz 20 g.783 1.5 1.5 nom 45%?55% ds3rxclkout [6:1] (sts-1) 19.29 51 .84 mhz 20 gr-253 1.5 1.5 nom 45%?55% table 6-16. lopoh output clock specifications clock name period (ns) frequency accuracy (ppm) jitter rise (ns) fall (ns) min/max duty cycle lopohclkout 51.44 19.44 mhz 20 ? 1.5 1.5 nom 45%?55% table 6-17. nsmi output clocks specifications clock name period (ns) frequency accuracy (ppm) jitter rise (ns) fall (ns) min/ max duty cycle rxdataen 19.29 51.84 mhz 20 ? 1.5 1.5 nom 45%?55% nsmitxclk 19.29 51.84 mhz 20 ? 1.5 1.5 nom 45%?55% table 6-18. pll output clocks specifications clock name period (ns) frequency accuracy (ppm) jitter rise (ns) fall (ns) min/max duty cycle cg_pllclkout 647.66 1.544 mhz 32 gr-499 ? ? ? 45%?55% cg_pllclkout 488.28 2.048 mhz 50 g.823 ? ? ? 45%?55% table 6-19. shared low-speed receive li ne input/output clocks specifications clock name period (ns) frequency accuracy (ppm) jitter rise (ns) fall (ns) min/max duty cycle linerxclk (framer; ds1) 647.66 1.544 mhz 32 ? 10 10 max 45%?55% linerxclk (framer; e1) 488.28 2.048 mhz 50 ? 10 10 max 45%?55% linerxclk(m12) 647.66 1.544 mhz 32 ? 10 10 max 45%?55% linerxclk (e12) 488.28 2.048 mhz 50 ? 10 10 max 45%?55% linerxclk (vtmpr; ds1) 647.66 1.544 mhz 32 ? 10 10 max 45%?55% linerxclk (vtmpr; e1) 488.28 2.048 mhz 50 ? 10 10 max 45%?55% linerxclk (vtmpr; vc11) 600.96 1.664 mhz 20 ? 10 10 max 45%?55% linerxclk (vtmpr; vc12) 446.42 2.24 mhz 20 ? 10 10 max 45%?55% linerxclk (m23) 158.42 6.312 mhz 30 ? 10 10 max 45%?55% linerxclk (e23) 118.37 8.448 mhz 30 ? 10 10 max 45%?55% linerxclk (dja; ds1) 647.66 1.544 mhz 32 ? 10 10 max 45%?55% linerxclk (dja; e1) 488.28 2.048 mhz 50 ? 10 10 max 45%?55% linerxclk (tpg; ds1) 647.66 1.544 mhz 32 ? 10 10 max 45%?55% linerxclk (tpg; e1) 488.28 2.048 mhz 50 ? 10 10 max 45%?55%
hardware design guide, revision 8 tmxl84622 ultramapper lite may 11, 2006 622/155 mbits/s so net/sdh x ds3/e3/ds2/ds1/e1 agere systems inc. 55 table 6-20. shared low-speed transmit line input/output clocks specifications clock name period (ns) frequency accuracy (ppm) jitter rise (ns) fall (ns) min/max duty cycle linetxclk (framer; ds1) 647.66 1.544 mhz 32 ? 1.5 1.5 nom 45%?55% linetxclk (framer; e1) 488.28 2.048 mhz 50 ? 1.5 1.5 nom 45%?55% linetxclk (m12) 647.66 1.544 mhz 32 ? 10 10 max 45%?55% linetxclk (e12) 488.28 2.048 mhz 50 ? 10 10 max 45%?55% linetxclk (vtmpr; ds1) 647.66 1.544 mhz 32 ? 1.5 1.5 nom 45%?55% linetxclk (vtmpr; e1) 488.28 2.048 mhz 50 ? 1.5 1.5 nom 45%?55% linetxclk (vtmpr; vc11) 600.96 1.664 mhz 20 ? 1.5 1.5 nom 45%?55% linetxclk (vtmpr; vc12) 446.42 2.24 mhz 20 ? 1.5 1.5 nom 45%?55% linetxclk (m23) 158.42 6.312 mhz 30 ? 10 10 max 45%?55% linetxclk (e23) 118.37 8.448 mhz 30 ? 10 10 max 45%?55% linetxclk (dja; ds1) 647.66 1.544 mhz 32 ? 1.5 1.5 nom 45%?55% linetxclk (dja; e1) 488.28 2.048 mhz 50 ? 1.5 1.5 nom 45%?55% linetxclk (tpg; ds1) 647.66 1.544 mhz 32 ? 1.5 1.5 nom 45%?55% linetxclk (tpg; e1) 488.28 2.048 mhz 50 ? 1.5 1.5 nom 45%?55% table 6-21. nsmi input/outp ut clocks specifications clock name period (ns) frequency accuracy (ppm) jitter rise (ns) fall (ns) min/max duty cycle nsmirxclk (sts1lt) 19.29 51.84 mhz 20 ? 3.5 3.5 max 45%?55% nsmirxclk (m13) 22.35 44.736 mhz 20 ? 1.5 1.5 nom 45%?55% nsmitxclk (sts1lt) 19.29 51.84 mhz 20 ? 1.5 1.5 nom 45%?55% nsmirxclk (e13) 29.09 34.368 mhz 20 ? 1.5 1.5 nom 45%?55% nsmirxclk (spempr) 19.29 51. 84 mhz 20 ? 3.5 3.5 max 45%?55% nsmirxclk (framer) 19.29 51.84 mhz 20 ? 3.5 3.5 max 45%?55%
tmxl84622 ultramapper lite hardware design guide, revision 8 622/155 mbits/s sonet/sdh x ds3/ e3/ds2/ds1/e1 may 11, 2006 56 56 agere systems inc. 7 microprocessor interface timing note: to allow proper operation of the micr oprocessor interface upon device/boar d bring up, the recommended powerup sequence (listed in section 3.6 recommended powerup sequence, on page 36 ) should be followed. specifically, to avoid potential bus contention is sues the ic3staten pin should be held low during boot up. 7.1 synchronous write mode the synchronous microprocessor interface mode is selected when mpmode (pin f6) = 1. in this mode, mpclk used for the ultramapper lite is the same as the microprocessor clock. inte rface timing for the synchr onous mode write cycle is given in figure 7-1 and in table 7-1, and for the read cycle in figure 7-2 and in table 7-2 . notes: mpclk input clock to ultramapper lite mpu block. addr [20:0] the address will be available throughout the entire cycle. csn (input) chip select is an active-low signal. adsn (input) address strobe is active-low. adsn must be one mpclk clock period wide. rwn (input) the read (h) write (l) signal is always high except during a write cycle. data[15:0] data will be available during cycle t1. dtn (output) data transfer acknowledge is ac tive-low for one clock and then driven hi gh before entering a high-impedance state. (this is done with an i/o pad using the input as feedback to qual ify the 3-state term.) dtn will become 3-stated when csn is high. typically, dtn is active for four or five mpclk cycles after adsn is low. figure 7-1. microprocessor interface sy nchronous write cycle?(mpmode pin = 1) mpclk addr[20:0] csn adsn rwn data[15:0] dtn (input) t ws t ws t dtnvpd t addrvs t csnvs t ws t 0 t 1 t 2 t 3 t n ? 2 t n ? 1 t n t aipd t apd t apd t apd t apd t dtnipd high z high z t adsnvdtf
hardware design guide, revision 8 tmxl84622 ultramapper lite may 11, 2006 622/155 mbits/s so net/sdh x ds3/e3/ds2/ds1/e1 agere systems inc. 57 * if dtn is used, then the maximum frequency for mpclk is determined by the processor?s setup specif ication for dtn. mpu maximum bus operating frequency = 1/(mpu dtn setup time + tdtnvpd). for example, a 8 ns setup time would limit mpclk to 50 mhz for reliable dtn detec tion. ? dtn fall is variable, depending on the bloc k selected for access and in some cases the state of the sonet frame. this interval is typically in the 100 ns to 200 ns range, but can be several hundred ns. it should never exc eed 35 mpclk cycles. certain registers in the vtmpr block ha ve a very long acknowledge cycle (in the order of 32 mpclk cycles). the reason for this is that those registers can also be accessed by the vt mpr lower order path overhead interface as part of sonet overhead termination functions. therefore the user must insert long enough delay or use the dtn signal to read/ write these registers correctly. additiona lly, if the high-speed cdr is used, during initialization, enough time must be provid ed to allow the cdr to stabi- lize. if the cdr has not stabilized, it may take much longer t han 35 mpclk cycles for accesses to certain vtmpr registers (dtn return times on the order of several s). it is recommended that the user wait at least 10 ms afte r the cdr has been reset before attempting to access any vtmpr regi s- ters. cdr provisioning is accomp lished via the umpr_clcr register. in addition to the above, the vt_rdy bit must be set before attempting any vtmpr register accesses. table 7-1. microprocessor interface synchronous write cycle specifications symbol parameter setup (min) hold (min) delay (min) delay (max) unit mpclk mpclk 16 mhz min?66 * mhz max frequency ? ? ? ? ns t ws adsn, rwn, data (write) valid to mpclk 6.7 ? ? ? ns t apd mpclk to addr, rwn, data, csn (write) invalid ? 0 ? ? ns t csnvs csn valid to mpclk 6 ? ? ? ns t addrvs addr valid to mpclk 3.5 ? ? ? ns t aipd mpclk to adsn invalid ? 0 ? ? ns t dtnvpd mpclk to dtn valid ? ? 2.5 12 ns t dtnipd mpclk to dtn invalid ? ? 2.5 12 ns t adsnvdtf adsn valid to dtn falling ? ? ? ? ? ns
tmxl84622 ultramapper lite hardware design guide, revision 8 622/155 mbits/s sonet/sdh x ds3/ e3/ds2/ds1/e1 may 11, 2006 58 58 agere systems inc. 7.2 synchronous read mode notes: mpclk input clock to ultramapper lite mpu block. addr [20:0] the address will be available throughout the entire cycle, and must be stable before adsn turns high. csn (input) chip select is an active-low signal. adsn (input) address strobe is active-low. adsn must be one mpclk clock period wide. rwn (input) the read (h) write (l) signal is always high during the read cycle. dtn (output) data transfer acknowledge on the host bus interface is in itiated on t6. this signal is active for one clock, and then d riven high before entering a high-impedance state. (this is done wi th an i/o pad using the input as feedbac k to qualify the 3-state term.) dtn wi ll become 3-stated when csn is high. typically, dtn is active four or five mpclk cycles after adsn is low. data [15:0] read data is stable in tn ? 1. the data is guaranteed to be stable no later than the time at which dtn becomes activ e. figure 7-2. microprocessor interface sy nchronous read cycle?(mpmode pin = 1) * if dtn is used, then the maximum frequency for mpclk is determined by the processor?s setup specif ication for dtn. mpu maximum bus operating frequency = 1/(mpu dtn setup time + tdnvpd). for example, an 8 ns setup time would limit mpclk to 50 mhz for reliable dtn detec tion. ? dtn fall is variable, depending on the bloc k selected for access and in some cases the state of the sonet frame. this interval is typically in the 100 ns to 200 ns range, but can be several hundred ns. it should never exc eed 35 mpclk cycles. certain registers in the vtmpr block ha ve a very long acknowledge cycle (in the order of 32 mpclk cycles). the reason for this is that those registers can also be accessed by the vt mpr lower order path overhead interface as part of sonet overhead termination functions. therefore the user must insert long enough delay or use the dtn signal to read/ write these registers correctly. additiona lly, if the high-speed cdr is used, during initialization, enough time must be provid ed to allow the cdr to stabi- lize. if the cdr has not stabilized, it may take much longer t han 35 mpclk cycles for accesses to certain vtmpr registers (dtn return times on the order of several s). it is recommended that the user wait at least 10 ms afte r the cdr has been reset before attempting to access any vtmpr regi s- ters. cdr provisioning is accomp lished via the umpr_clcr register. in addition to the above, the vt_rdy bit must be set before attempting any vtmpr register accesses. table 7-2. microprocessor interface synchronous read cycle specifications symbol parameter setup (min) hold (min) delay (min) delay (max) unit mpclk mpclk 16 mhz min?66 * mhz max frequency ? ? ? ? ns t avs addr valid to mpclk 3.5 ? ? ? ns t apd mpclk to addr invalid ? 0 ? ? ns t csnsu csn active to mpclk 6 ? ? ? ns t adsnsu adsn valid to mpclk 6 ? ? ? ns t snipd mpclk to adsn inactive ? 0 ? ? ns t dnvpd mpclk to dtn valid ? ? 2.5 12 ns t dnipd mpclk to dtn invalid ? ? 2.5 12 ns t daipd mpclk to data 3-state ? ? 3.5 15 ns t adsnvdtf adsn valid to dtn falling ? ? ? ? ? ns mpclk addr[20:0] csn adsn rwn t adsnsu t snipd t csnsu t avs t 0 t 1 t 2 t n ? 4 t n ? 3 t n ? 2 t n ? 1 t n dtn data[15:0] ( output ) t daipd t dnvpd t dnipd t adsnvdtf high z high z t apd
hardware design guide, revision 8 tmxl84622 ultramapper lite may 11, 2006 622/155 mbits/s so net/sdh x ds3/e3/ds2/ds1/e1 agere systems inc. 59 7.3 asynchronous write mode the asynchronous microprocessor interface mode is selected when mpmode (p in f6) = 0. interface timing for the asyn- chronous mode write cycle is given in figure 7- 3 and in table 7-3, and for the read cycle in figure 7-4 and in ta b l e 7 - 4 . although this is an asynchronous in terface, an mpclk is still required. this cloc k can be different (asy nchronous) from the mpu clock. internal to th e chip, rwn, adsn, and dsn will be sampled by mpclk. notes: addr [20:0] address is asynchronously passed from the host bus to the internal bus. the address will be available throughout the entire cycle. addr must be held constant while adsn and dsn are valid (low). csn (input) chip select is an active-low signal. csn must be held low (active) until adsn and dsn are deasserted. adsn (input) address strobe is active-low. adsn must be stable for the entire period. adsn and csn may be connected and driven f rom the same source. dsn (input) data strobe is active-low. data [15:0] write data is asynchronously passed from the host bus to the internal bus. data will be available throughout the ent ire cycle. data must be held constant while dsn is valid (low). rwn (input) the read/write signal should be high for a read cycle and low for a write cycle. it should always be held high, exce pt during a write cycle. rwn must be held low (write) until dsn is deasserted (high). dtn (output) data transfer acknowledge (active-low). dtn is driven ou t of 3-state to inactive-high on the assertion of csn. when the internal transac- tion is complete, dtn goes active-low. dtn is then driven high agai n when either adsn or dsn is deasserted. dtn will become 3-s tated when csn is high. dtn fall is variable, depend ing on the block selected for access and in some cases the state of the sonet fra me. this interval is typically in the 100 ns to 200 ns range, but can be several hundred ns. in lab measurements, it has never exceeded 1000 ns. figure 7-3. microprocessor interface asynchronous write cycle?(mpmode pin = 0) addr[20:0] csn adsn dsn rwn data[15:0] dtn (input) t avadsf t dvdsf t csfdtr t dsfdtf t adsrdtr t csrdt3 t dsrdi t dsrrwr t dsnrai t adsrai t aicsr t rwfdsf t avdsf high z high z t csfdsf
tmxl84622 ultramapper lite hardware design guide, revision 8 622/155 mbits/s sonet/sdh x ds3/ e3/ds2/ds1/e1 may 11, 2006 60 60 agere systems inc. 7.3 table 7-3. microprocessor interface asynchronous write cycle specifications symbol parameter setup (min) hold (min) delay (min) delay (max) unit mpclkmpclk 16 mhz min?66 mhz max frequency????ns t csfdsf csn fall setup and hold to dsn fall 0 ? ? ? ns t aicsr csn rise to addr invalid ? 0 ? ? ns t avadsf addr valid setup and hold to adsn fall 1.0 ? ? ? ns t adsrai adsn rise to addr invalid ? 1.42 ? ? ns t avdsf addr valid setup and hold to dsn fall 0 ? ? ? ns t dsnrai dsn rise to addr invalid ? 0 ? ? ns t rwfdsf rwn fall setup and hold to dsn fall 0 ? ? ? ns t dsrrwr dsn rise to rwn rise ? 0 ? ? ns t dvdsf data valid setup and hold to dsn fall 0 ? ? ? ns t dsrdi dsn rise to data invalid ? 0 ? ? ns t csfdtr csn fall to dtn rise ? ? 5.2 16.0 ns t dsfdtf dsn fall to dtn fall ? 0 ? * ns t adsrdtr adsn or dsn rise to dtn rise ? ? 2.9 13.3 ns t csrdt3 csn rise to dtn 3-state ? ? 2.9 13 ns * certain registers in the vtmpr block have a very long acknowledge cycle (in the order of 32 mpclk cycles). the reason for this is that those registers can also be accessed by the vtmpr lower order path overhead inte rface as part of sonet overhead termination functions. therefor e, the user must insert long enough delay or use the dtn signal to read/write t hese registers correctly. additi onally, if the high-speed cdr is used, during initialization, enough time must be provided to allow the cdr to stabilize. if the cdr has not stabilized, it may take much longer than 35 mpcl k cycles for accesses to certain vtmpr registers (dtn return times on the order of several s). it is recommended that the user wait at least 10 ms after the cdr has been reset before attempting to access any vtmpr registers. cdr prov isioning is accomplished via the umpr_clcr register. in addition to the above, the vt_rdy bit must be set before attempting any vtmpr register accesses.
hardware design guide, revision 8 tmxl84622 ultramapper lite may 11, 2006 622/155 mbits/s so net/sdh x ds3/e3/ds2/ds1/e1 agere systems inc. 61 7.4 asynchronous read mode notes: addr [20:0] address is asynchronously passed from the host bus to the internal bus. the address will be available throughout the entire cycle. csn (input) chip select is an active-low signal. adsn (input) address strobe is active-low. dsn (input) data strobe is active-low. rwn (input) the read (h) write (l) signal is always high during a read cycle. dtn (output) data transfer acknowledge (active-low). dtn is driven ou t of 3-state to inactive-high on the assertion of csn. when the internal transac- tion is complete, dtn goes active-low. dtn is then driven high agai n when either adsn or dsn is deasserted. dtn will become 3-s tated when csn is high. data [15:0] 16-bit data bus. figure 7-4. microprocessor interface asynchronous read cycle?(mpmode pin = 0) addr[20:0] csn adsn dsn dtn data[15:0] t adsrd3 t csrdt3 t adsrdtr t csfdsf rwn t avadsf t avdsf t aicsr t adsrai t dsnrai t dtvdv t dsfdtf t csfdtr high z high z high z high z
tmxl84622 ultramapper lite hardware design guide, revision 8 622/155 mbits/s sonet/sdh x ds3/ e3/ds2/ds1/e1 may 11, 2006 62 62 agere systems inc. table 7-4. microprocessor interface asynchronous read cycle specifications symbol parameter setup (min) hold (min) delay (min) delay (max) unit mpclk mpclk 16 mhz min?66 mhz max frequency ? ? ? ? ns t csfdsf csn fall setup and hold to dsn fall 0 ?* * csn must be held low (active) until adsn and dsn are deasserted. ??ns t aicsr csn rise to addr invalid ? 0 ? ? ns t avadsf addr valid setup and hold to adsn fall 1.0 ?? ? addr must be held constant while adsn and dsn are valid (low). ??ns t adsrai adsn rise to addr invalid ? 1.42 ? ? ns t avdsf addr valid setup and hold to dsn fall 0 ? ? ??ns t dsnrai dsn rise to addr invalid ? 0 ? ? ns t csfdtr csn fall to dtn rise ? ? 5.2 16.0 ns t dsfdtf dsn fall to dtn fall ? 0 ? ?? ? dtn fall is variable, depending on the block selected for access and in some cases, the state of the sonet frame. this inter val is typically in the 100 ns to 200 ns range, but can be several hundred ns. it should never exceed 35 mpclk cycles. certain registers in the vtmpr b lock have a very long acknowledge cycle (in the order of 32 mpclk cycles). t he reason for this is that those registers can also be accessed by the vtmpr lower order path overhead interface as part of sonet overhead te rmination functions. therefore the user must insert long enough delay or use the dtn signal to read/write these register s correctly. additionally, if the high-s peed cdr is used, during initialization, eno ugh time must be provided to allow the cdr to stabilize. if the cdr has not stabi lized, it may take much longer than 35 mpclk cycles for accesse s to certain vtmpr registers (dtn return times on the order of several s). it is recommended that the user wait at least 10 ms after the cdr has been reset before attempting to access any vtmpr regist ers. cdr provisioning is accomplished vi a the umpr_clcr register. in addition to th e above, the vt_rdy bit must be set before attempting any vtmpr register accesses. ns t adsrdtr adsn or dsn rise to dtn rise ? ? 2.9 13.3 ns t csrdt3 csn rise to dtn 3-state ? ? 2.9 13.0 ns t dtvdv dtn valid to data valid ? ? ? 0 ns t adsrd3 adsn rise to data 3-state ? ? 2.9 14 + mpclk data[15:0] is enabled by a retimed version of the adsn. ns
hardware design guide, revision 8 tmxl84622 ultramapper lite may 11, 2006 622/155 mbits/s so net/sdh x ds3/e3/ds2/ds1/e1 agere systems inc. 63 8 other timing this interface may be used as either synchronous or a synchronous mode. 9 hardware design file references (ibis, spice, bsdl, etc.) available upon request. table 8-1. general-purpose inputs name reference edge rising/falling rise time (ns) fall time (ns) setup (ns) hold (ns) rstn async ? ? ? ? ? pmrst async ? ? ? ? ? tdi and tms tclk r 5 5 19.5 6.4 table 8-2. miscellaneous output name reference edge rising/falling propagation delay min (ns) max (ns) rhsfsyncn asynchronous ? ? ? table 8-3. general-purpose output name reference edge rising/falling propagation delay min (ns) max (ns) tdo tclk f 12.5 45
tmxl84622 ultramapper lite hardware design guide, revision 8 622/155 mbits/s sonet/sdh x ds3/ e3/ds2/ds1/e1 may 11, 2006 64 64 agere systems inc. 10 700-pin pbgam1t diagrams figure 10-1. 700-pin pbga m1t physical dimension * 2 oz option *
hardware design guide, revision 8 tmxl84622 ultramapper lite may 11, 2006 622/155 mbits/s so net/sdh x ds3/e3/ds2/ds1/e1 agere systems inc. 65 figure 10-2. bottom view of 700-pin pbgam1t balls location
copyright ? 2006 agere systems inc. all rights reserved may 11, 2006 ds02-384bbac-8 (replaces ds02-384bbac-7) hardware de- sign guide, revi- tmxl84622 ultramapper lite hardware design guide, revision 8 622/155 mbits/s sonet/sdh x ds3/ e3/ds2/ds1/e1 may 11, 2006 agere systems inc. reserves the right to make changes to the pr oduct(s) or information contained herein without notice. no liab ility is assumed as a result of their use or application. agere, agere systems, and the agere logo are registered trademarks of agere systems inc. ultramapper is a trademark of agere systems inc. for additional information, contact your a gere systems account manager or the following: internet: home: http://www.agere.com sales: http://www.agere.com/sales e-mail: docmaster@agere.com n. america: agere systems inc., lehigh valley central campus, room 10a-301c, 1110 american parkway ne, allentown, pa 18109-9138 1-800-372-2447 , fax 610-712-4106 (in canada: 1-800-553-2448 , fax 610-712-4106) asia: china: (86) 21-54614688 (shanghai), (86) 755-25881122 (shenzhen), (86) 10-65391096 (beijing) japan: (81) 3-5421-1600 (tokyo), korea: (82) 2-767-1850 (seoul), singapore: (65) 6741-9855 , taiwan: (886) 2-2725-5858 (taipei) europe: tel. (44) 1344 865 900 11 device ordering information table 11-1. device ordering information device package comcode tmxl846221bl-21 700-pin pbgam1t 700054128 tmxl846221bl-3 700-pin pbgam1t 700052304 L-TMXL846221BL-3* 700-pin pbgam1t 700077979 * pb-free/rohs
hardware design guide, revision 8 tmxl84622 ultramapper lite may 11, 2006 622/155 mbits/s so net/sdh x ds3/e3/ds2/ds1/e1 agere systems inc. 67 12 glossary ais alarm indication signal ami alternate mark inversion aps automatic protection switch asm associated signaling mode ber bit error rate bom bit-oriented message bpv bipolar violation b8zs binary 8 zero code suppression cci common channel signaling cdr clock and data recovery chi concentrated highway interface cmi coded mark inversion crc cyclic redundancy check crv coding rule violation dacs digital access cross connects dja digital jitter attenuation esf extended superframe exz excessive zeros fcs frame check sequence fdl facility data link feac far-end alarm and control febe far-end block error hdb3 high-density bipolar of order three hdlc high-level data link control liu line interface unit loc loss of clock lof loss of frame los loss of signal lopoh low-order path overhead mcdr mate clock and data recovery mrxc multirate cross connect nsmi network serial multiplexed interface oof out of frame pbga pin ball grid array poac path overhead access channel prbs pseudorandom bit sequence prm performance report message qrss quasirandom signal source rai remote alarm indicator rdi remote defect indication rpoac receive path overhead access channel rei remote error indication sdh synchronous digital hierarchy sef severely errored frame tcm tandem connection monitoring toac transport overhead access channels upsr unidirectional path switch ring
copyright ? 2006 agere systems inc. all rights reserved may 11, 2006 ds02-384bbac-8 (replaces ds02-384bbac-7) hardware de- sign guide, revi- tmxl84622 ultramapper lite hardware design guide, revision 8 622/155 mbits/s sonet/sdh x ds3/ e3/ds2/ds1/e1 may 11, 2006 agere systems inc. reserves the right to make changes to the pr oduct(s) or information contained herein without notice. no liab ility is assumed as a result of their use or application. agere, agere systems, and the agere logo are registered trademarks of agere systems inc. ultramapper is a trademark of agere systems inc. for additional information, contact your a gere systems account manager or the following: internet: home: http://www.agere.com sales: http://www.agere.com/sales e-mail: docmaster@agere.com n. america: agere systems inc., lehigh valley central campus, room 10a-301c, 1110 american parkway ne, allentown, pa 18109-9138 1-800-372-2447 , fax 610-712-4106 (in canada: 1-800-553-2448 , fax 610-712-4106) asia: china: (86) 21-54614688 (shanghai), (86) 755-25881122 (shenzhen), (86) 10-65391096 (beijing) japan: (81) 3-5421-1600 (tokyo), korea: (82) 2-767-1850 (seoul), singapore: (65) 6741-9855 , taiwan: (886) 2-2725-5858 (taipei) europe: tel. (44) 1344 865 900 13 change history 13.1 changes to this document since revision 7 added table 2-13, nsmi/sts-1 in, on page 23 and table 2-14, nsmi/sts-1 out, on page 24 . added figure 5-17, nsmi clock and data diagram for framer (frm) nsmi mode on page 49 . added table 6-17, nsmi output clo cks specifications, on page 54 . updated table 6-21, nsmi input/output clocks specifications, on page 55 . 13.2 navigating through an adobe acrobat document if the reader displays this document in acrobat reader , clicking on any blue entry in the te xt will bring the re ader to that ref- erence point. ieee is a registered trademark of the institute of electrical and elec tronics engineers, inc. adobe acrobat and acrobat reader are registered trademarks of adobe systems incorporated.

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