imisc617 system clock chip international microcircuits, inc. 525 los coches st. milpitas, ca 95035 tel: 408-263-6300 fax 408-263-657 page 1 of 7 rev. 1.0 may 1996 product features ? supports pci system board designs p54, p55, and p6 ? integrates system clocks and distribution buffers ? an early host clock, 5 host clocks and 7 pci clocks ? supports 5v or 3.3v on eclk and b1out* ? 60 ma buffer switching current ? 28 pin ssop package for minimum board space block diagram o sc pll1 pll2 delay 3/5 ns ? 1/2/3 xin xout lf1 lf2 pwrgd f48/s2 f24/s1 b2out (1:7) b1out (1:5) 5 eclk 7 ref/s0 pll frequency synthesizer cmos lsi product description the imisc617 provides the clocks and the low skew distribution buffers required to drive the pentium ? cpu and pci busses. selectable delay between eclk and b1out*. mixed supply option for p55/54 applications. fixed 24 and 48 mhz for floppy and u.s.b. frequency table select outputs (mhz) f12/s2 f24/s1 ref/s0 eclk + b2out* 0004020 0 0 1 75 37.5 0104040 011 reserved reserved 1 0 0 50 33.3 1015025 1106030 1 1 1 66.6 33.3 + eclk = b1out* applications 60 ma of switching current is provided on all outputs at b1vdd = vdd = 5v. 3.3v operating modes support new low voltage components on the cpu bus. operating the b1 buffer at 3.3v (b1vdd) and routing the cpu clock through b1 distributes a 3.3v signal to the cpu bus. the outputs provide 30 ma switching current.
imisc617 system clock chip international microcircuits, inc. 525 los coches st. milpitas, ca 95035 tel: 408-263-6300 fax 408-263-657 page 2 of 7 rev. 1.0 may 1996 pll frequency synthesizer cmos lsi pin description x in x out - these pins form an on-chip reference oscillator when connected to terminals of an external parallel resonant crystal (nominally 14.318 mhz). oscin may also serve as input for an externally generated reference signal. eclk - early clock output. this output is synchronous to b1out* clocks and leads by 5 ns typically. b1out* - delayed buffered outputs of eclk. b2out* - buffered outputs for pci bus. synchronous to eclk. f24/s1 - when pwrgd is low this pin is used as an input select line, s1. when pwrgd is high this pin is 24 mhz output. this pin has an internal pull-up. f48/s2 - when pwrgd is low this pin is used as an input select line, s2. when pwrgd is high this pin is 48 mhz output. this pin has an internal pull-up. pwrgd - logic low on this input tristates all outputs. when logic transitions to high, it causes the select data to be latched and the outputs are enabled. this is a schmitt input with an internal pull-up. ref/s0 - when pwrgd is low this pin is used as an input select line, s0. when pwrgd is high this pin is a reference output of the crystal input. this pin has an internal pull-up. lf1 and lf2 - these are the loop filter pins for the clock generators. a 0.1f capacitor should be connected from each pin to avss. grounding lf puts pll in low power mode. vss - circuit ground. vdd - positive power supply. avss - analog circuit ground. avdd - analog positive power supply. b1vdd - 3.3v/5v logic level control for eclk and b1out* outputs.
imisc617 system clock chip international microcircuits, inc. 525 los coches st. milpitas, ca 95035 tel: 408-263-6300 fax 408-263-657 page 3 of 7 rev. 1.0 may 1996 pll frequency synthesizer cmos lsi maximum ratings voltage relative to vss: -0.3v voltage relative to vdd: 0.3v storage temperature: -65oc to 150oc ambient temperature: -55oc to +125oc maximum operating supply: 6v this device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to its circuit. for proper operation, vin and vout should be constrained to the range: vss< (vin or vout) < vdd unused inputs must always be tied to an appropriate logic voltage level (either vss or vdd). electrical characteristics characteristic symbol min typ max units conditions input low voltage v il - - 0.8 vdc input high voltage v ih 2.0 - - vdc pwrgd, f12/s2, f24/s1, input low current with i il, i ih 5a ref/s0 pull-up or pull-down --+ 50 output low voltage iol = 6ma v ol - - 0.4 vdc eclk and b1out* output high voltage ioh=6ma v oh 2.4 - - vdc output low voltage iol = 12ma v ol - - 0.4 vdc all other outputs output high voltage ioh=12ma v oh 2.4 - - vdc tri-state leakage current i oz - - 10 a lf1, lf2, and tristate outputs dynamic supply current i dd - - 95 ma eclk = 50 mhz static supply current i dd - 300 - a lf1 = lf2 = 0, xin = 1 short circuit current i os 25 - - ma 1 output at a time - max 30 sec. vdd=avdd= 5v + 10% b1vdd = 3.3v + 10%. ta = 0oc to 70oc
imisc617 system clock chip international microcircuits, inc. 525 los coches st. milpitas, ca 95035 tel: 408-263-6300 fax 408-263-657 page 4 of 7 rev. 1.0 may1996 pll frequency synthesizer cmos lsi switching characteristics characteristic symbol min typ max units conditions output rise (0.8v - 2.0v) ttlh, - - 1.5 ns 15 pf load. b1out* + eclk and fall (2.0v-0.8v) time tthl - - 1.5 ns 15pf load. all other outputs output duty cycle 45 50 55 % measured at 1.5v, 15 pf load b1out*-skew t1skw - - 250 ps measured at 1.5v b2out*-skew t2skw - - 500 ps measured at 1.5v b1out* - b2out* 1 - 4 ns measured at 1.5v eclk to b1out* offset2 toff 4 5.5 6.2 measured at 1.5v. d period adjacent cycles d p - - + 200 ps measured at 1.5v on eclk jitter absolute tjab - + 200 - ps measured at 1.5v on eclk vdd=avdd= 5v + 10% b1vdd = 3.3v + 10%. ta = 0oc to 70oc *see application note for implementation. connection diagrams 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 xin xout vss eclk b1out1 b1out2 b1vdd b1out3 b1out4 b1out5 vdd avss lf1 avdd ref/s0 f24/s1 vss b2out1 b2out2 b2out3 f48/s2 b2out4 b2out5 b2out6 b2out7 vdd pwrgd lf2
imisc617 system clock chip international microcircuits, inc. 525 los coches st. milpitas, ca 95035 tel: 408-263-6300 fax 408-263-657 page 5 of 7 rev. 1.0 may 1996 pll frequency synthesizer cmos lsi pcb layout suggestion fb1 c1(22uf) c2(0.1uf) u1 +5v/3.3v component layer imisc617 c3(0.1uf) c4(0.1uf) r1(10 ohm) c5(22uf) c6 +5v + c7(0.1uf) +5v connect avss to gnd plane at this point only fb2 c8(22uf) c9(0.1uf) notes 1. power supply bypass caps (0.1 m f and 22 m f) must be positioned close to vdd pins to be effective. 2. lf caps must be low leakage, such as multilayer ceramic z5u or x7r material.
imisc617 system clock chip international microcircuits, inc. 525 los coches st. milpitas, ca 95035 tel: 408-263-6300 fax 408-263-657 page 6 of 7 rev. 1.0 may 1996 pll frequency synthesizer cmos lsi application suggestion (update) 14.318mhz 24mhz 48mhz c1 22pf y1 14.318 mhz c2 22pf c2 0.1uf c3 0.1uf vdd vcc c4 0.1uf c5 22uf 10 ohm r1 c6 0.1uf xin xout vss eclk b1out1 b1out2 b1vdd b1out3 b1out4 b1out5 vdd avss lf1 avdd ref14/s0 24mhz/s1 vss b2out1 b2out2 b2out3 48mhz/s2 b2out4 b2out5 b2out6 b2out7 vdd pwrgd lf2 c7 0.1uf c9 0.1uf c8 22uf fb2 vdd 33 ohm 2.2k ohm 33 ohm 33 ohm r4 r4 s2 s0 s1 r5 2.2k ohm r6 2.2k ohm c1 22uf fb fb1 vcc jp2 3 2 1 1 . . . 12 power connecto r note 2 jp1 3 2 1 vcc 3.3v 3.3v note 3 1. all bypass caps must be as close as possible to their vdd, avdd, and b1vdd pins.
imisc617 system clock chip international microcircuits, inc. 525 los coches st. milpitas, ca 95035 tel: 408-263-6300 fax 408-263-657 page 7 of 7 rev. 1.0 may 1996 pll frequency synthesizer cmos lsi package drawing and dimensions 28 pin ssop outline dimensions inches millimeters symbol min nom max min nom max a 0.068 0.073 0.078 1.73 1.86 1.99 a 1 0.002 0.005 0.008 0.05 0.13 0.21 a 2 0.066 0.068 0.070 1.68 1.73 1.78 b 0.010 0.012 0.015 0.25 0.30 0.38 c 0.005 0.006 0.009 0.13 0.15 0.22 d 0.397 0.402 0.407 10.07 10.20 10.33 e 0.205 0.209 0.212 5.20 5.30 5.38 e 0.0256 bsc 0.65 bsc h 0.301 0.307 0.311 7.65 7.80 7.90 a 0o4o 8o0o 4o 8o l 0.022 0.030 0.037 0.55 0.75 0.95 ordering information part number package type production flow IMISC617AYB 28 pin ssop commercial, 0oc to 70oc marking: imi sc617ayb date code, lot # IMISC617AYB flow b = commercial, 0oc to 70oc package ssop revision imi device number b e a a 1 a 2 e h a l c d
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